From d1301c0af3b6a6fd16af6bba6c5d83ddf1ec6910 Mon Sep 17 00:00:00 2001 From: arthur Date: Mon, 6 May 2024 16:17:58 -0300 Subject: [PATCH 01/37] enable CTS clock NDR by default Signed-off-by: arthur --- src/cts/src/CtsOptions.h | 2 +- src/cts/src/TritonCTS.tcl | 11 ++++++++--- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/src/cts/src/CtsOptions.h b/src/cts/src/CtsOptions.h index 51ccb28323..16adc52e07 100644 --- a/src/cts/src/CtsOptions.h +++ b/src/cts/src/CtsOptions.h @@ -293,7 +293,7 @@ class CtsOptions utl::Logger* logger_ = nullptr; stt::SteinerTreeBuilder* sttBuilder_ = nullptr; bool obsAware_ = false; - bool applyNDR_ = false; + bool applyNDR_ = true; bool insertionDelay_ = true; bool bufferListInferred_ = false; bool sinkBufferInferred_ = false; diff --git a/src/cts/src/TritonCTS.tcl b/src/cts/src/TritonCTS.tcl index 5b5a95acca..20131675c4 100644 --- a/src/cts/src/TritonCTS.tcl +++ b/src/cts/src/TritonCTS.tcl @@ -85,7 +85,7 @@ sta::define_cmd_args "clock_tree_synthesis" {[-wire_unit unit] [-num_static_layers] \ [-sink_clustering_buffer] \ [-obstruction_aware] \ - [-apply_ndr] \ + [-dont_apply_ndr] \ [-sink_buffer_max_cap_derate] \ [-dont_use_dummy_load] \ [-delay_buffer_derate] \ @@ -101,7 +101,7 @@ proc clock_tree_synthesis { args } { -sink_clustering_levels -tree_buf \ -sink_buffer_max_cap_derate -delay_buffer_derate} \ flags {-post_cts_disable -sink_clustering_enable -balance_levels \ - -obstruction_aware -apply_ndr -dont_use_dummy_load + -obstruction_aware -dont_apply_ndr -dont_use_dummy_load };# checker off sta::check_argc_eq0 "clock_tree_synthesis" $args @@ -217,7 +217,12 @@ proc clock_tree_synthesis { args } { cts::set_dummy_load true } - cts::set_apply_ndr [info exists flags(-apply_ndr)] + + if { [info exists flags(-dont_apply_ndr)] } { + cts::set_apply_ndr false + } else { + cts::set_apply_ndr true + } if { [ord::get_db_block] == "NULL" } { From a1672a84bf504d0b5b04e9cc61283d2b91227df6 Mon Sep 17 00:00:00 2001 From: arthur Date: Thu, 16 May 2024 10:43:47 -0300 Subject: [PATCH 02/37] grt fix ndr pitch computing Signed-off-by: arthur --- src/grt/src/GlobalRouter.cpp | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/grt/src/GlobalRouter.cpp b/src/grt/src/GlobalRouter.cpp index 4cac309246..e438f7ff91 100644 --- a/src/grt/src/GlobalRouter.cpp +++ b/src/grt/src/GlobalRouter.cpp @@ -1036,9 +1036,7 @@ void GlobalRouter::computeTrackConsumption( int ndr_spacing = layer_rule->getSpacing(); int ndr_width = layer_rule->getWidth(); - int ndr_pitch = 2 - * (std::ceil(ndr_width / 2 + ndr_spacing - + default_width / 2 - default_pitch)); + int ndr_pitch = std::ceil(ndr_width / 2 + ndr_spacing+ default_width / 2); int consumption = std::ceil((float) ndr_pitch / default_pitch); (*edge_costs_per_layer)[layerIdx - 1] = consumption; From 85eabe6685f2e7e665e3d7fef30f13dbd07de849 Mon Sep 17 00:00:00 2001 From: andyfox-rushc Date: Sun, 30 Jun 2024 12:58:54 -0700 Subject: [PATCH 03/37] Record objects requiring concrete type conversion versus odb type conversion Signed-off-by: andyfox-rushc --- src/dbSta/include/db_sta/dbNetwork.hh | 35 +- src/dbSta/src/dbNetwork.cc | 438 +++++++++++++++++++++----- src/dbSta/test/hierclock_out.vok | 80 +++-- 3 files changed, 450 insertions(+), 103 deletions(-) diff --git a/src/dbSta/include/db_sta/dbNetwork.hh b/src/dbSta/include/db_sta/dbNetwork.hh index 47f3b92c06..a43c47c770 100644 --- a/src/dbSta/include/db_sta/dbNetwork.hh +++ b/src/dbSta/include/db_sta/dbNetwork.hh @@ -96,6 +96,7 @@ class dbNetwork : public ConcreteNetwork void init(dbDatabase* db, Logger* logger); void setBlock(dbBlock* block); void clear() override; + CellPortIterator* portIterator(const Cell* cell) const; void readLefAfter(dbLib* lib); void readDefAfter(dbBlock* block); @@ -118,7 +119,7 @@ class dbNetwork : public ConcreteNetwork bool isPlaced(const Pin* pin) const; LibertyCell* libertyCell(dbInst* inst); - + LibertyPort* libertyPort(const Pin*) const; dbInst* staToDb(const Instance* instance) const; void staToDb(const Instance* instance, dbInst*& db_inst, @@ -143,6 +144,11 @@ class dbNetwork : public ConcreteNetwork dbMaster* staToDb(const LibertyCell* cell) const; dbMTerm* staToDb(const Port* port) const; dbMTerm* staToDb(const LibertyPort* port) const; + void staToDb(const Port* port, + dbBTerm*& bterm, + dbMTerm*& mterm, + dbModBTerm*& modbterm) const; + void staToDb(PortDirection* dir, dbSigType& sig_type, dbIoType& io_type) const; @@ -169,6 +175,7 @@ class dbNetwork : public ConcreteNetwork const dbIoType& io_type) const; // dbStaCbk::inDbBTermCreate Port* makeTopPort(dbBTerm* bterm); + dbBTerm* isTopPort(const Port*) const; void setTopPortDirection(dbBTerm* bterm, const dbIoType& io_type); ObjectId id(const Port* port) const override; @@ -218,6 +225,26 @@ class dbNetwork : public ConcreteNetwork Pin* pin(const Term* term) const override; ObjectId id(const Term* term) const override; + //////////////////////////////////////////////////////////////// + // Cell functions + const char* name(const Cell* instance) const override; + + bool isConcreteCell(const Cell*) const; + void registerConcreteCell(const Cell*); + + //////////////////////////////////////////////////////////////// + // Port functions + Cell* cell(const Port* port) const override; + void registerConcretePort(const Port*); + void registerLibertyPort(const Port*, const LibertyPort*); + void registerHPorts(); + void registerHPort(const Port*); + bool isHPort(const Port*) const; + bool isConcretePort(const Port*) const; + bool isLibertyPort(const Port*) const; + + PortDirection* direction(const Port* port) const override; + //////////////////////////////////////////////////////////////// // Net functions ObjectId id(const Net* net) const override; @@ -264,6 +291,8 @@ class dbNetwork : public ConcreteNetwork // hierarchy handler, set in openroad tested in network child traverserser void setHierarchy() { hierarchy_ = true; } bool hasHierarchy() const { return hierarchy_; } + bool hasMembers(const Port* port) const; + Port* findMember(const Port* port, int index) const; using Network::cell; using Network::direction; @@ -313,6 +342,10 @@ class dbNetwork : public ConcreteNetwork private: bool hierarchy_ = false; + std::set concrete_cells_; + std::set concrete_ports_; + std::map liberty_ports_; + std::set h_ports_; }; } // namespace sta diff --git a/src/dbSta/src/dbNetwork.cc b/src/dbSta/src/dbNetwork.cc index 9078cd2e22..6d9d9745cb 100644 --- a/src/dbSta/src/dbNetwork.cc +++ b/src/dbSta/src/dbNetwork.cc @@ -43,6 +43,8 @@ #include "sta/PortDirection.hh" #include "utl/Logger.h" +//#define DEBUG_DBNWK 1 + namespace sta { using utl::ORD; @@ -598,52 +600,87 @@ const char* dbNetwork::name(const Instance* instance) const return tmpStringCopy(mod_inst->getName()); } -void dbNetwork::makeVerilogCell(Library* library, dbModInst* mod_inst) +const char* dbNetwork::name(const Cell* cell) const { - dbModule* master = mod_inst->getMaster(); - Cell* local_cell - = ConcreteNetwork::makeCell(library, master->getName(), false, nullptr); - master->staSetCell((void*) (local_cell)); + dbMaster* db_master = nullptr; + dbModule* db_module = nullptr; + staToDb(cell, db_master, db_module); + if (db_master) { + return ConcreteNetwork::name(cell); + } else { + return db_module->getName(); + } + return nullptr; +} - std::map name2modbterm; +//////////////////////////////////////////////////////////////// +// Module port iterator, allows traversal across dbModulePorts +class dbModulePortIterator : public CellPortIterator +{ + public: + explicit dbModulePortIterator(const dbModule* cell); + ~dbModulePortIterator(); + virtual bool hasNext(); + virtual Port* next(); - for (auto modbterm : master->getModBTerms()) { - const char* port_name = modbterm->getName(); - Port* port = ConcreteNetwork::makePort(local_cell, port_name); - PortDirection* dir = dbToSta(modbterm->getSigType(), modbterm->getIoType()); - setDirection(port, dir); - name2modbterm[std::string(port_name)] = modbterm; - } + private: + dbSet::iterator iter_; + const dbModule* module_; +}; - // make the bus ports. This will generate the bus bits. - groupBusPorts(local_cell, [=](const char* port_name) { - return portMsbFirst(port_name, master->getName()); - }); +dbModulePortIterator::dbModulePortIterator(const dbModule* cell) +{ + iter_ = (const_cast(cell)->getModBTerms()).begin(); + module_ = cell; +} - CellPortIterator* ccport_iter = portIterator(local_cell); - while (ccport_iter->hasNext()) { - Port* cport = ccport_iter->next(); - const ConcretePort* ccport = reinterpret_cast(cport); - std::string port_name = ccport->name(); - - if (ccport->isBus()) { - PortMemberIterator* pmi = memberIterator(cport); - while (pmi->hasNext()) { - Port* bitport = pmi->next(); - const ConcretePort* cbitport - = reinterpret_cast(bitport); - dbModBTerm* modbterm = name2modbterm[std::string(cbitport->name())]; - modbterm->staSetPort(bitport); - } - } else if (ccport->isBundle()) { - ; - } else if (ccport->isBusBit()) { - ; - } else { - dbModBTerm* modbterm = name2modbterm[port_name]; - modbterm->staSetPort(cport); +dbModulePortIterator::~dbModulePortIterator() +{ +} + +bool dbModulePortIterator::hasNext() +{ + if (iter_ == (const_cast(module_))->getModBTerms().end()) + return false; + return true; +} + +Port* dbModulePortIterator::next() +{ + if (iter_ == (const_cast(module_))->getModBTerms().end()) + return nullptr; + dbModBTerm* modbterm = *iter_; + Port* ret = reinterpret_cast(modbterm); + // advance to next + iter_++; + return ret; +} + +CellPortIterator* dbNetwork::portIterator(const Cell* cell) const +{ + if (isConcreteCell(cell) || cell == top_cell_) { + return ConcreteNetwork::portIterator(cell); + } else { + dbMaster* db_master; + dbModule* db_module; + staToDb(cell, db_master, db_module); + if (db_module) { + return new dbModulePortIterator(db_module); } } + return nullptr; +} + +Cell* dbNetwork::cell(const Port* port) const +{ + if (isConcretePort(port)) { + const ConcretePort* cport = reinterpret_cast(port); + return cport->cell(); + } else { + const dbModBTerm* modbterm = reinterpret_cast(port); + return (reinterpret_cast(modbterm->getParent())); + } + return nullptr; } Cell* dbNetwork::cell(const Instance* instance) const @@ -664,9 +701,6 @@ Cell* dbNetwork::cell(const Instance* instance) const // look up the cell in the verilog library. return dbToSta(master); } - // no traversal of the hierarchy this way; we would have to split - // Cell into dbMaster and dbModule otherwise. When we have full - // odb hierarchy this can be revisited. return nullptr; } @@ -845,9 +879,8 @@ ObjectId dbNetwork::id(const Pin* pin) const Instance* dbNetwork::instance(const Pin* pin) const { - dbITerm* iterm; - - dbBTerm* bterm; + dbITerm* iterm = nullptr; + dbBTerm* bterm = nullptr; dbModITerm* moditerm = nullptr; dbModBTerm* modbterm = nullptr; @@ -950,7 +983,8 @@ Port* dbNetwork::port(const Pin* pin) const dbModITerm* moditerm; dbModBTerm* modbterm; Port* ret = nullptr; - + static int debug; + debug++; // Will return the bterm for a top level pin staToDb(pin, iterm, bterm, moditerm, modbterm); @@ -977,19 +1011,76 @@ Port* dbNetwork::port(const Pin* pin) const return ret; } +PortDirection* dbNetwork::direction(const Port* port) const +{ + static int debug; + debug++; + +#ifdef DEBUG_DBNWK + printf("D %d Getting direction of port %s\n", debug, name(port)); + if (isBus(port)) { + printf("This is a bus !\n"); + int from_ix = fromIndex(port); + Port* bus_pin = findBusBit(port, from_ix); + port = bus_pin; + if (libertyPort(port)) { + printf("This is a liberty bus port!\n"); + return PortDirection::unknown(); + } + } else if (isBundle(port)) { + printf("This is a bundle\n"); + } else if (libertyPort(port)) { + printf("This is a liberty port\n"); + } +#endif + dbMTerm* mterm = nullptr; + dbModBTerm* modbterm = nullptr; + dbBTerm* bterm = nullptr; + staToDb(port, bterm, mterm, modbterm); + if (bterm) { + PortDirection* dir = dbToSta(bterm->getSigType(), bterm->getIoType()); + return dir; + } else if (modbterm) { + PortDirection* dir = dbToSta(modbterm->getSigType(), modbterm->getIoType()); + return dir; + } else { + const ConcretePort* cport = reinterpret_cast(port); + return cport->direction(); + } + return PortDirection::unknown(); +} + PortDirection* dbNetwork::direction(const Pin* pin) const { + static int debug; + debug++; + // ODB does not undestand tristates so look to liberty before ODB for port // direction. - LibertyPort* lib_port = libertyPort(pin); - if (lib_port) { - return lib_port->direction(); + +#ifdef DEBUG_DBNWK + printf("D %d **Getting direction of pin %s on instance %s of cell %s\n", + debug, + name(pin), + name(instance(pin)), + name(cell(port(pin)))); + if (cell(port(pin)) == top_cell_) + printf("A top port !\n"); + else + printf("Not a top port !\n"); +#endif + + if (isConcretePort(port(pin))) { + LibertyPort* lib_port = libertyPort(pin); + if (lib_port) { + return lib_port->direction(); + } } + dbITerm* iterm; dbBTerm* bterm; dbModBTerm* modbterm; dbModITerm* moditerm; - // pin -> iterm or moditerm staToDb(pin, iterm, bterm, moditerm, modbterm); if (iterm) { @@ -1000,6 +1091,7 @@ PortDirection* dbNetwork::direction(const Pin* pin) const PortDirection* dir = dbToSta(bterm->getSigType(), bterm->getIoType()); return dir; } + if (modbterm) { PortDirection* dir = dbToSta(modbterm->getSigType(), modbterm->getIoType()); return dir; @@ -1009,11 +1101,39 @@ PortDirection* dbNetwork::direction(const Pin* pin) const std::string pin_name = moditerm->getName(); dbModInst* mod_inst = moditerm->getParent(); dbModule* module = mod_inst->getMaster(); + +#ifdef DEBUG_DBNWK + printf( + "D %d *** Getting direction of pin %s from dbModule %s instance %s\n", + debug, + name(pin), + module->getName(), + mod_inst->getName()); + printf("Dump of bterms on module\n"); + for (dbModBTerm* mod_bterm : module->getModBTerms()) { + debug++; + printf("D %d module bterm %s \n", debug, mod_bterm->getName()); + } +#endif + dbModBTerm* modbterm_local = module->findModBTerm(pin_name.c_str()); +#ifdef DEBUG_DBNWK + if (!modbterm_local) { + printf("Something very bad ! Cannot find pin %s on module %s\n", + pin_name.c_str(), + module->getName()); + } +#endif PortDirection* dir = dbToSta(modbterm_local->getSigType(), modbterm_local->getIoType()); return dir; } + // + // note the nasty default behaviour here. + // if not a liberty port then return unknown + // presumably unlinked lefs fall through here + // This is probably a bug in the original code. + // return PortDirection::unknown(); } @@ -1355,19 +1475,6 @@ void dbNetwork::readDbAfter(odb::dbDatabase* db) makeLibrary(lib); } readDbNetlistAfter(); - if (hierarchy_) { - // we make the library for the verilog hierarchical cells - // this is in the same fashion as the original dbInst code - // which uses the void* staGetCell to associate a cell with - // concrete cell. We do same for verilog hierarchical cells. - Library* verilog_library = makeLibrary("verilog", nullptr); - dbSet modinsts = block_->getModInsts(); - dbSet::iterator modinst_iter_ = modinsts.begin(); - dbSet::iterator modinst_end_ = modinsts.end(); - for (; modinst_iter_ != modinst_end_; modinst_iter_++) { - makeVerilogCell(verilog_library, *modinst_iter_); - } - } } for (auto* observer : observers_) { @@ -1387,30 +1494,52 @@ void dbNetwork::makeLibrary(dbLib* lib) void dbNetwork::makeCell(Library* library, dbMaster* master) { const char* cell_name = master->getConstName(); +#ifdef DEBUG_DBNWK + printf("Making cell %s\n", cell_name); +#endif + Cell* cell = makeCell(library, cell_name, true, nullptr); master->staSetCell(reinterpret_cast(cell)); + // keep track of db leaf cells. These are cells for which we + // use the concrete network. + registerConcreteCell(cell); ConcreteCell* ccell = reinterpret_cast(cell); ccell->setExtCell(reinterpret_cast(master)); // Use the default liberty for "linking" the db/LEF masters. LibertyCell* lib_cell = findLibertyCell(cell_name); if (lib_cell) { +#ifdef DEBUG_DBNWK + printf("A liberty cell %s\n", cell_name); +#endif ccell->setLibertyCell(lib_cell); lib_cell->setExtCell(reinterpret_cast(master)); } for (dbMTerm* mterm : master->getMTerms()) { const char* port_name = mterm->getConstName(); +#ifdef DEBUG_DBNWK + printf("Making mterm port %s\n", port_name); +#endif + Port* port = makePort(cell, port_name); PortDirection* dir = dbToSta(mterm->getSigType(), mterm->getIoType()); setDirection(port, dir); mterm->staSetPort(reinterpret_cast(port)); ConcretePort* cport = reinterpret_cast(port); cport->setExtPort(reinterpret_cast(mterm)); - + registerConcretePort(port); if (lib_cell) { LibertyPort* lib_port = lib_cell->findLibertyPort(port_name); +#ifdef DEBUG_DBNWK + if (dir->isPowerGround()) + printf("A power ground port %p (lib port %p)\n", port, lib_port); + +#endif if (lib_port) { +#ifdef DEBUG_DBNWK + printf("A liberty port\n"); +#endif cport->setLibertyPort(lib_port); lib_port->setExtPort(mterm); } else if (!dir->isPowerGround() && !lib_cell->findPgPort(port_name)) { @@ -1423,6 +1552,7 @@ void dbNetwork::makeCell(Library* library, dbMaster* master) } } // Assume msb first busses because LEF has no clue about busses. + // This generates the top level ports groupBusPorts(cell, [](const char*) { return true; }); // Fill in liberty to db/LEF master correspondence for libraries not used @@ -1443,14 +1573,42 @@ void dbNetwork::makeCell(Library* library, dbMaster* master) } } } + + CellPortIterator* port_iter = portIterator(cell); + while (port_iter->hasNext()) { + Port* cur_port = port_iter->next(); +#ifdef DEBUG_DBNWK + printf("Registering liberty port %s\n", name(cur_port)); +#endif + registerConcretePort(cur_port); + } + delete lib_iter; } +bool dbNetwork::isHPort(const Port* port) const +{ + return (h_ports_.find(port) != h_ports_.end()); +} + +void dbNetwork::registerHPort(const Port* port) +{ + h_ports_.insert(port); +} + +void dbNetwork::registerHPorts() +{ + for (auto b : block_->getModBTerms()) { + h_ports_.insert(reinterpret_cast(b)); + } +} + void dbNetwork::readDbNetlistAfter() { makeTopCell(); findConstantNets(); checkLibertyCorners(); + registerHPorts(); } void dbNetwork::makeTopCell() @@ -1464,12 +1622,23 @@ void dbNetwork::makeTopCell() const char* design_name = block_->getConstName(); Library* top_lib = makeLibrary(design_name, nullptr); top_cell_ = makeCell(top_lib, design_name, false, nullptr); + // bterms in top cell include bus components for (dbBTerm* bterm : block_->getBTerms()) { makeTopPort(bterm); } groupBusPorts(top_cell_, [=](const char* port_name) { return portMsbFirst(port_name, design_name); }); + + // record the top level ports + CellPortIterator* port_iter = portIterator(top_cell_); + while (port_iter->hasNext()) { + Port* cur_port = port_iter->next(); +#ifdef DEBUG_DBNWK + printf("Registering top level port %s\n", name(cur_port)); +#endif + registerConcretePort(cur_port); + } } Port* dbNetwork::makeTopPort(dbBTerm* bterm) @@ -1478,6 +1647,7 @@ Port* dbNetwork::makeTopPort(dbBTerm* bterm) Port* port = makePort(top_cell_, port_name); PortDirection* dir = dbToSta(bterm->getSigType(), bterm->getIoType()); setDirection(port, dir); + registerConcretePort(port); return port; } @@ -1533,8 +1703,11 @@ void dbNetwork::readLibertyAfter(LibertyLibrary* lib) while (port_iter->hasNext()) { ConcretePort* cport = port_iter->next(); const char* port_name = cport->name(); + Port* cur_port = reinterpret_cast(cport); + registerConcretePort(cur_port); LibertyPort* lport = lcell->findLibertyPort(port_name); if (lport) { + registerLibertyPort(cur_port, lport); cport->setLibertyPort(lport); lport->setExtPort(cport->extPort()); } else if (!cport->direction()->isPowerGround() @@ -1738,9 +1911,13 @@ Port* dbNetwork::makePort(Cell* cell, const char* name) } // Making the bterm creates the port in the db callback odb::dbBTerm::create(net, name); - return findPort(cell, name); + Port* ret = findPort(cell, name); + registerConcretePort(ret); + return ret; } - return ConcreteNetwork::makePort(cell, name); + Port* cur_port = ConcreteNetwork::makePort(cell, name); + registerConcretePort(cur_port); + return cur_port; } Pin* dbNetwork::makePin(Instance* inst, Port* port, Net* net) @@ -1911,15 +2088,11 @@ void dbNetwork::staToDb(const Cell* cell, { module = nullptr; master = nullptr; - if (findLibertyCell(name(cell))) { + if (isConcreteCell(cell) || cell == top_cell_) { master = reinterpret_cast(const_cast(cell)); } else { if (block_) { - if (block_->findModule(name(cell))) { - module = reinterpret_cast(const_cast(cell)); - } else { - master = reinterpret_cast(const_cast(cell)); - } + module = reinterpret_cast(const_cast(cell)); } } } @@ -1944,6 +2117,49 @@ dbMTerm* dbNetwork::staToDb(const Port* port) const return reinterpret_cast(cport->extPort()); } +dbBTerm* dbNetwork::isTopPort(const Port* port) const +{ + CellPortIterator* port_iter = portIterator(top_cell_); + while (port_iter->hasNext()) { + if (port == port_iter->next()) { + const ConcretePort* cport = reinterpret_cast(port); + if (cport->isBus()) { + return block_->findBTerm(busName(port)); + } + return block_->findBTerm(name(port)); + } + } + return nullptr; +} + +void dbNetwork::staToDb(const Port* port, + dbBTerm*& bterm, + dbMTerm*& mterm, + dbModBTerm*& modbterm) const +{ + mterm = nullptr; + modbterm = nullptr; + + if (isConcretePort(port)) { + const ConcretePort* cport = reinterpret_cast(port); + mterm = reinterpret_cast(cport->extPort()); +#ifdef DEBUG_DBNWK + printf("A leaf port\n"); +#endif + return; + } else { + dbObject* obj = reinterpret_cast(const_cast(port)); + dbObjectType type = obj->getObjectType(); + if (type == dbModBTermObj) { + Port* port_unconst = const_cast(port); + modbterm = reinterpret_cast(port_unconst); + } else if (type == dbBTermObj) { + Port* port_unconst = const_cast(port); + bterm = reinterpret_cast(port_unconst); + } + } +} + dbMTerm* dbNetwork::staToDb(const LibertyPort* port) const { return reinterpret_cast(port->extPort()); @@ -1998,7 +2214,7 @@ Net* dbNetwork::dbToSta(dbModNet* net) const Port* dbNetwork::dbToSta(dbModBTerm* modbterm) const { - return reinterpret_cast(modbterm->staPort()); + return reinterpret_cast(modbterm); } Term* dbNetwork::dbToStaTerm(dbModITerm* moditerm) const @@ -2013,7 +2229,7 @@ Term* dbNetwork::dbToStaTerm(dbModBTerm* modbterm) const Cell* dbNetwork::dbToSta(dbModule* master) const { - return ((Cell*) (master->getStaCell())); + return reinterpret_cast(master); } Instance* dbNetwork::dbToSta(dbInst* inst) const @@ -2088,6 +2304,80 @@ LibertyCell* dbNetwork::libertyCell(dbInst* inst) return libertyCell(dbToSta(inst)); } +LibertyPort* dbNetwork::libertyPort(const Pin* pin) const +{ + const Port* cur_port = port(pin); + if (isHPort(cur_port)) { + return nullptr; + } + LibertyPort* ret = ConcreteNetwork::libertyPort(pin); + return ret; +} + +/* +We keep a registry of the concrete cells. +For these we know to use the concrete network interface. +*/ + +void dbNetwork::registerConcreteCell(const Cell* cell) +{ + concrete_cells_.insert(cell); +} + +bool dbNetwork::isConcreteCell(const Cell* cell) const +{ + return (concrete_cells_.find(cell) != concrete_cells_.end()); +} + +void dbNetwork::registerConcretePort(const Port* port) +{ + concrete_ports_.insert(port); +} + +void dbNetwork::registerLibertyPort(const Port* port, const LibertyPort* lport) +{ + liberty_ports_[port] = lport; +} + +bool dbNetwork::isConcretePort(const Port* port) const +{ + if (concrete_ports_.find(port) != concrete_ports_.end()) { + return true; + } + return false; +} + +bool dbNetwork::hasMembers(const Port* port) const +{ + static int debug; + debug++; +#ifdef DEBUG_DBNWK + printf("D: %d Checking if (%s) port %s has members\n", + debug, + isBus(port) ? "bus" : "non-bus", + name(port)); +#endif + if (isConcretePort(port)) { + const ConcretePort* cport = reinterpret_cast(port); + return cport->hasMembers(); + } else { + // TODO: bus ports in hierarchy. + return false; + } + return false; +} + +Port* dbNetwork::findMember(const Port* port, int index) const +{ + if (isConcretePort(port)) { + const ConcretePort* cport = reinterpret_cast(port); + return reinterpret_cast(cport->findMember(index)); + } else { + // TODO: hierarhcial ports + return nullptr; + } +} + //////////////////////////////////////////////////////////////// // Observer diff --git a/src/dbSta/test/hierclock_out.vok b/src/dbSta/test/hierclock_out.vok index 4b2e73d21f..9467c5a14c 100644 --- a/src/dbSta/test/hierclock_out.vok +++ b/src/dbSta/test/hierclock_out.vok @@ -83,29 +83,29 @@ module hierclock (a_count_valid_o, .rst_n_i(rst_n_i), .clk_i(clk_i)); counter U2 (.count_valid_o(a_count_valid_o), + .\count_value_o[3] (a_count_o[3]), + .\count_value_o[2] (a_count_o[2]), + .\count_value_o[1] (a_count_o[1]), + .\count_value_o[0] (a_count_o[0]), + .\load_value_i[3] (a_i[3]), + .\load_value_i[2] (a_i[2]), + .\load_value_i[1] (a_i[1]), + .\load_value_i[0] (a_i[0]), .load_i(a_ld_i), .rst_n_i(rst_n_i), - .clk_i(clk1_int), - .count_value_o({a_count_o[3], - a_count_o[2], - a_count_o[1], - a_count_o[0]}), - .load_value_i({a_i[3], - a_i[2], - a_i[1], - a_i[0]})); + .clk_i(clk1_int)); counter-1 U3 (.count_valid_o(b_count_valid_o), + .\count_value_o[3] (b_count_o[3]), + .\count_value_o[2] (b_count_o[2]), + .\count_value_o[1] (b_count_o[1]), + .\count_value_o[0] (b_count_o[0]), + .\load_value_i[3] (b_i[3]), + .\load_value_i[2] (b_i[2]), + .\load_value_i[1] (b_i[1]), + .\load_value_i[0] (b_i[0]), .load_i(b_ld_i), .rst_n_i(rst_n_i), - .clk_i(clk2_int), - .count_value_o({b_count_o[3], - b_count_o[2], - b_count_o[1], - b_count_o[0]}), - .load_value_i({b_i[3], - b_i[2], - b_i[1], - b_i[0]})); + .clk_i(clk2_int)); endmodule module clockgen (clk2_o, clk1_o, @@ -166,17 +166,29 @@ module clockgen (clk2_o, .QN(_19_)); endmodule module counter (count_valid_o, + \count_value_o[3] , + \count_value_o[2] , + \count_value_o[1] , + \count_value_o[0] , + \load_value_i[3] , + \load_value_i[2] , + \load_value_i[1] , + \load_value_i[0] , load_i, rst_n_i, - clk_i, - count_value_o, - load_value_i); + clk_i); output count_valid_o; + output \count_value_o[3] ; + output \count_value_o[2] ; + output \count_value_o[1] ; + output \count_value_o[0] ; + input \load_value_i[3] ; + input \load_value_i[2] ; + input \load_value_i[1] ; + input \load_value_i[0] ; input load_i; input rst_n_i; input clk_i; - output [3:0] count_value_o; - input [3:0] load_value_i; INV_X1 \U2/_49_ (.A(_41_), @@ -256,17 +268,29 @@ module counter (count_valid_o, .QN(_38_)); endmodule module counter-1 (count_valid_o, + \count_value_o[3] , + \count_value_o[2] , + \count_value_o[1] , + \count_value_o[0] , + \load_value_i[3] , + \load_value_i[2] , + \load_value_i[1] , + \load_value_i[0] , load_i, rst_n_i, - clk_i, - count_value_o, - load_value_i); + clk_i); output count_valid_o; + output \count_value_o[3] ; + output \count_value_o[2] ; + output \count_value_o[1] ; + output \count_value_o[0] ; + input \load_value_i[3] ; + input \load_value_i[2] ; + input \load_value_i[1] ; + input \load_value_i[0] ; input load_i; input rst_n_i; input clk_i; - output [3:0] count_value_o; - input [3:0] load_value_i; INV_X1 \U3/_49_ (.A(_41_), From e4fd3ab9751d9e98901ab16666d159d13415aee7 Mon Sep 17 00:00:00 2001 From: andyfox-rushc Date: Sun, 30 Jun 2024 16:04:40 -0700 Subject: [PATCH 04/37] Reoved debug prints. Signed-off-by: Andy Fox Signed-off-by: andyfox-rushc --- src/dbSta/src/dbNetwork.cc | 120 +++++-------------------------------- 1 file changed, 16 insertions(+), 104 deletions(-) diff --git a/src/dbSta/src/dbNetwork.cc b/src/dbSta/src/dbNetwork.cc index 6d9d9745cb..d6af54e932 100644 --- a/src/dbSta/src/dbNetwork.cc +++ b/src/dbSta/src/dbNetwork.cc @@ -43,8 +43,6 @@ #include "sta/PortDirection.hh" #include "utl/Logger.h" -//#define DEBUG_DBNWK 1 - namespace sta { using utl::ORD; @@ -1013,26 +1011,6 @@ Port* dbNetwork::port(const Pin* pin) const PortDirection* dbNetwork::direction(const Port* port) const { - static int debug; - debug++; - -#ifdef DEBUG_DBNWK - printf("D %d Getting direction of port %s\n", debug, name(port)); - if (isBus(port)) { - printf("This is a bus !\n"); - int from_ix = fromIndex(port); - Port* bus_pin = findBusBit(port, from_ix); - port = bus_pin; - if (libertyPort(port)) { - printf("This is a liberty bus port!\n"); - return PortDirection::unknown(); - } - } else if (isBundle(port)) { - printf("This is a bundle\n"); - } else if (libertyPort(port)) { - printf("This is a liberty port\n"); - } -#endif dbMTerm* mterm = nullptr; dbModBTerm* modbterm = nullptr; dbBTerm* bterm = nullptr; @@ -1052,29 +1030,11 @@ PortDirection* dbNetwork::direction(const Port* port) const PortDirection* dbNetwork::direction(const Pin* pin) const { - static int debug; - debug++; - // ODB does not undestand tristates so look to liberty before ODB for port // direction. - -#ifdef DEBUG_DBNWK - printf("D %d **Getting direction of pin %s on instance %s of cell %s\n", - debug, - name(pin), - name(instance(pin)), - name(cell(port(pin)))); - if (cell(port(pin)) == top_cell_) - printf("A top port !\n"); - else - printf("Not a top port !\n"); -#endif - - if (isConcretePort(port(pin))) { - LibertyPort* lib_port = libertyPort(pin); - if (lib_port) { - return lib_port->direction(); - } + LibertyPort* lib_port = libertyPort(pin); + if (lib_port) { + return lib_port->direction(); } dbITerm* iterm; @@ -1091,7 +1051,6 @@ PortDirection* dbNetwork::direction(const Pin* pin) const PortDirection* dir = dbToSta(bterm->getSigType(), bterm->getIoType()); return dir; } - if (modbterm) { PortDirection* dir = dbToSta(modbterm->getSigType(), modbterm->getIoType()); return dir; @@ -1101,29 +1060,7 @@ PortDirection* dbNetwork::direction(const Pin* pin) const std::string pin_name = moditerm->getName(); dbModInst* mod_inst = moditerm->getParent(); dbModule* module = mod_inst->getMaster(); - -#ifdef DEBUG_DBNWK - printf( - "D %d *** Getting direction of pin %s from dbModule %s instance %s\n", - debug, - name(pin), - module->getName(), - mod_inst->getName()); - printf("Dump of bterms on module\n"); - for (dbModBTerm* mod_bterm : module->getModBTerms()) { - debug++; - printf("D %d module bterm %s \n", debug, mod_bterm->getName()); - } -#endif - dbModBTerm* modbterm_local = module->findModBTerm(pin_name.c_str()); -#ifdef DEBUG_DBNWK - if (!modbterm_local) { - printf("Something very bad ! Cannot find pin %s on module %s\n", - pin_name.c_str(), - module->getName()); - } -#endif PortDirection* dir = dbToSta(modbterm_local->getSigType(), modbterm_local->getIoType()); return dir; @@ -1494,10 +1431,6 @@ void dbNetwork::makeLibrary(dbLib* lib) void dbNetwork::makeCell(Library* library, dbMaster* master) { const char* cell_name = master->getConstName(); -#ifdef DEBUG_DBNWK - printf("Making cell %s\n", cell_name); -#endif - Cell* cell = makeCell(library, cell_name, true, nullptr); master->staSetCell(reinterpret_cast(cell)); // keep track of db leaf cells. These are cells for which we @@ -1509,19 +1442,12 @@ void dbNetwork::makeCell(Library* library, dbMaster* master) // Use the default liberty for "linking" the db/LEF masters. LibertyCell* lib_cell = findLibertyCell(cell_name); if (lib_cell) { -#ifdef DEBUG_DBNWK - printf("A liberty cell %s\n", cell_name); -#endif ccell->setLibertyCell(lib_cell); lib_cell->setExtCell(reinterpret_cast(master)); } for (dbMTerm* mterm : master->getMTerms()) { const char* port_name = mterm->getConstName(); -#ifdef DEBUG_DBNWK - printf("Making mterm port %s\n", port_name); -#endif - Port* port = makePort(cell, port_name); PortDirection* dir = dbToSta(mterm->getSigType(), mterm->getIoType()); setDirection(port, dir); @@ -1531,15 +1457,7 @@ void dbNetwork::makeCell(Library* library, dbMaster* master) registerConcretePort(port); if (lib_cell) { LibertyPort* lib_port = lib_cell->findLibertyPort(port_name); -#ifdef DEBUG_DBNWK - if (dir->isPowerGround()) - printf("A power ground port %p (lib port %p)\n", port, lib_port); - -#endif if (lib_port) { -#ifdef DEBUG_DBNWK - printf("A liberty port\n"); -#endif cport->setLibertyPort(lib_port); lib_port->setExtPort(mterm); } else if (!dir->isPowerGround() && !lib_cell->findPgPort(port_name)) { @@ -1577,9 +1495,6 @@ void dbNetwork::makeCell(Library* library, dbMaster* master) CellPortIterator* port_iter = portIterator(cell); while (port_iter->hasNext()) { Port* cur_port = port_iter->next(); -#ifdef DEBUG_DBNWK - printf("Registering liberty port %s\n", name(cur_port)); -#endif registerConcretePort(cur_port); } @@ -1634,9 +1549,6 @@ void dbNetwork::makeTopCell() CellPortIterator* port_iter = portIterator(top_cell_); while (port_iter->hasNext()) { Port* cur_port = port_iter->next(); -#ifdef DEBUG_DBNWK - printf("Registering top level port %s\n", name(cur_port)); -#endif registerConcretePort(cur_port); } } @@ -2140,14 +2052,14 @@ void dbNetwork::staToDb(const Port* port, mterm = nullptr; modbterm = nullptr; + // if it is a concrete port we get the port stuff from the extPort + // void* field in the fake library created. if (isConcretePort(port)) { const ConcretePort* cport = reinterpret_cast(port); mterm = reinterpret_cast(cport->extPort()); -#ifdef DEBUG_DBNWK - printf("A leaf port\n"); -#endif return; } else { + // just get the port directly from odb dbObject* obj = reinterpret_cast(const_cast(port)); dbObjectType type = obj->getObjectType(); if (type == dbModBTermObj) { @@ -2306,6 +2218,10 @@ LibertyCell* dbNetwork::libertyCell(dbInst* inst) LibertyPort* dbNetwork::libertyPort(const Pin* pin) const { + // We keep a note of the hierarchical ports and avoid + // trying to coerce them with the concrete network api calls + // Because of the way the fake library is build up outside of + // odb there is no easy way of doing the type conversion. const Port* cur_port = port(pin); if (isHPort(cur_port)) { return nullptr; @@ -2317,6 +2233,10 @@ LibertyPort* dbNetwork::libertyPort(const Pin* pin) const /* We keep a registry of the concrete cells. For these we know to use the concrete network interface. +The concrete cells are created outside of the odb world +-- attempting to type cast those can lead to bad pointers. +So we simply note them and then when we inspect a cell +we can decide whether or not to use the ConcreteNetwork api. */ void dbNetwork::registerConcreteCell(const Cell* cell) @@ -2349,19 +2269,11 @@ bool dbNetwork::isConcretePort(const Port* port) const bool dbNetwork::hasMembers(const Port* port) const { - static int debug; - debug++; -#ifdef DEBUG_DBNWK - printf("D: %d Checking if (%s) port %s has members\n", - debug, - isBus(port) ? "bus" : "non-bus", - name(port)); -#endif if (isConcretePort(port)) { const ConcretePort* cport = reinterpret_cast(port); return cport->hasMembers(); } else { - // TODO: bus ports in hierarchy. + // TODO: bus ports in hierarchy. (Bus support in next pull) return false; } return false; @@ -2373,7 +2285,7 @@ Port* dbNetwork::findMember(const Port* port, int index) const const ConcretePort* cport = reinterpret_cast(port); return reinterpret_cast(cport->findMember(index)); } else { - // TODO: hierarhcial ports + // TODO: hierarhcial ports, bus support in next pull. return nullptr; } } From f9f9817becc913a78f93076679cb339dfee037be Mon Sep 17 00:00:00 2001 From: andyfox-rushc Date: Mon, 1 Jul 2024 22:07:04 -0700 Subject: [PATCH 05/37] Remove extraneous tables only stash concrete ports/cells added notes to review with Matt. Signed-Off-by: Andy Fox --- src/dbSta/include/db_sta/dbNetwork.hh | 7 +- src/dbSta/src/dbNetwork.cc | 116 +++++++++++++++++--------- 2 files changed, 79 insertions(+), 44 deletions(-) diff --git a/src/dbSta/include/db_sta/dbNetwork.hh b/src/dbSta/include/db_sta/dbNetwork.hh index a43c47c770..c389877704 100644 --- a/src/dbSta/include/db_sta/dbNetwork.hh +++ b/src/dbSta/include/db_sta/dbNetwork.hh @@ -236,10 +236,7 @@ class dbNetwork : public ConcreteNetwork // Port functions Cell* cell(const Port* port) const override; void registerConcretePort(const Port*); - void registerLibertyPort(const Port*, const LibertyPort*); - void registerHPorts(); - void registerHPort(const Port*); - bool isHPort(const Port*) const; + bool isConcretePort(const Port*) const; bool isLibertyPort(const Port*) const; @@ -344,8 +341,6 @@ class dbNetwork : public ConcreteNetwork bool hierarchy_ = false; std::set concrete_cells_; std::set concrete_ports_; - std::map liberty_ports_; - std::set h_ports_; }; } // namespace sta diff --git a/src/dbSta/src/dbNetwork.cc b/src/dbSta/src/dbNetwork.cc index d6af54e932..994d26bdce 100644 --- a/src/dbSta/src/dbNetwork.cc +++ b/src/dbSta/src/dbNetwork.cc @@ -35,6 +35,46 @@ // dbSta, OpenSTA on OpenDB +/* + Need to distinguish between (a) hierarchical cells + and leaf cells (b) hierarchical ports and leaf ports. + + Leaf ports/cells use weird void* field. + + Two approaches: + + Option A + + (1) Stash all liberty cells pointers in map + (2) Stash all concrete ports in map + --note extport (on cport) + -- extcell (on cell) + These special cases require us to know the type to get the values. + So have to discriminate them. + + A.1 use map, maybe not to bad. + A.2 Possibility of using pointer tricks to avoid map (mark up lower bit, +unusued in processors). + + + option B + (1) Stash all hierarchical cells in map + (2) Stash all hierarchical ports in map + -- ok, but then we need to flush table + -- and do house keeping with each port update. + -- feels wrong + + option C + Somehow use block (which has stash of instances/ports). + -- wont work needs name and name discrimination needs type + -- wont work as db has no physical <-> virtual address conversion + (1) Use bterm hash table (bterm ports) + (2) use inst hash table (binst) + + +Recommended conclusion: use map for concrete cells. They are invariant. + + */ #include "db_sta/dbNetwork.hh" #include "odb/db.h" @@ -600,10 +640,10 @@ const char* dbNetwork::name(const Instance* instance) const const char* dbNetwork::name(const Cell* cell) const { - dbMaster* db_master = nullptr; - dbModule* db_module = nullptr; + dbMaster* db_master; + dbModule* db_module; staToDb(cell, db_master, db_module); - if (db_master) { + if (db_master || cell == top_cell_) { return ConcreteNetwork::name(cell); } else { return db_module->getName(); @@ -671,6 +711,10 @@ CellPortIterator* dbNetwork::portIterator(const Cell* cell) const Cell* dbNetwork::cell(const Port* port) const { + // Check -- can we just do is HPort ? + // rather than stash everything at leaf level + // looks like we have to keep cports and ccells in tables. + // if (isConcretePort(port)) { const ConcretePort* cport = reinterpret_cast(port); return cport->cell(); @@ -1065,6 +1109,9 @@ PortDirection* dbNetwork::direction(const Pin* pin) const = dbToSta(modbterm_local->getSigType(), modbterm_local->getIoType()); return dir; } + + // Review with Matt -- seems to occur with some cases. (lef based ?) + // eg block_sta.tcl // // note the nasty default behaviour here. // if not a liberty port then return unknown @@ -1501,29 +1548,11 @@ void dbNetwork::makeCell(Library* library, dbMaster* master) delete lib_iter; } -bool dbNetwork::isHPort(const Port* port) const -{ - return (h_ports_.find(port) != h_ports_.end()); -} - -void dbNetwork::registerHPort(const Port* port) -{ - h_ports_.insert(port); -} - -void dbNetwork::registerHPorts() -{ - for (auto b : block_->getModBTerms()) { - h_ports_.insert(reinterpret_cast(b)); - } -} - void dbNetwork::readDbNetlistAfter() { makeTopCell(); findConstantNets(); checkLibertyCorners(); - registerHPorts(); } void dbNetwork::makeTopCell() @@ -1619,7 +1648,6 @@ void dbNetwork::readLibertyAfter(LibertyLibrary* lib) registerConcretePort(cur_port); LibertyPort* lport = lcell->findLibertyPort(port_name); if (lport) { - registerLibertyPort(cur_port, lport); cport->setLibertyPort(lport); lport->setExtPort(cport->extPort()); } else if (!cport->direction()->isPowerGround() @@ -1994,14 +2022,22 @@ void dbNetwork::staToDb(const Term* term, } } +// Primary -- needs concrete test void dbNetwork::staToDb(const Cell* cell, dbMaster*& master, dbModule*& module) const { module = nullptr; master = nullptr; + // + // Check with Matt.. + // Can we kill this test ? eg look up cell by name in library ? -- apparently + // not looping problem staToDb is called by name. Or do something different ?? + // Otherwise we are stuck with map. + // if (isConcreteCell(cell) || cell == top_cell_) { - master = reinterpret_cast(const_cast(cell)); + const ConcreteCell* ccell = reinterpret_cast(cell); + master = reinterpret_cast(ccell->extCell()); } else { if (block_) { module = reinterpret_cast(const_cast(cell)); @@ -2009,12 +2045,16 @@ void dbNetwork::staToDb(const Cell* cell, } } +// +// Left in, these are only called by db Cells. +// dbMaster* dbNetwork::staToDb(const Cell* cell) const { const ConcreteCell* ccell = reinterpret_cast(cell); return reinterpret_cast(ccell->extCell()); } +// called only on db cells. dbMaster* dbNetwork::staToDb(const LibertyCell* cell) const { const ConcreteCell* ccell = cell; @@ -2023,8 +2063,6 @@ dbMaster* dbNetwork::staToDb(const LibertyCell* cell) const dbMTerm* dbNetwork::staToDb(const Port* port) const { - // Todo fix to use modbterm - const ConcretePort* cport = reinterpret_cast(port); return reinterpret_cast(cport->extPort()); } @@ -2052,8 +2090,13 @@ void dbNetwork::staToDb(const Port* port, mterm = nullptr; modbterm = nullptr; + // + // Primary, needs concrete test + // // if it is a concrete port we get the port stuff from the extPort // void* field in the fake library created. + // + // if (isConcretePort(port)) { const ConcretePort* cport = reinterpret_cast(port); mterm = reinterpret_cast(cport->extPort()); @@ -2218,16 +2261,18 @@ LibertyCell* dbNetwork::libertyCell(dbInst* inst) LibertyPort* dbNetwork::libertyPort(const Pin* pin) const { - // We keep a note of the hierarchical ports and avoid - // trying to coerce them with the concrete network api calls - // Because of the way the fake library is build up outside of - // odb there is no easy way of doing the type conversion. + // Primary: needs concrete test. + // Look up instance const Port* cur_port = port(pin); - if (isHPort(cur_port)) { - return nullptr; + const Instance* cur_instance = instance(pin); + dbInst* db_inst = nullptr; + dbModInst* mod_inst = nullptr; + staToDb(cur_instance, db_inst, mod_inst); + if (db_inst) { + LibertyPort* ret = ConcreteNetwork::libertyPort(pin); + return ret; } - LibertyPort* ret = ConcreteNetwork::libertyPort(pin); - return ret; + return nullptr; } /* @@ -2254,11 +2299,6 @@ void dbNetwork::registerConcretePort(const Port* port) concrete_ports_.insert(port); } -void dbNetwork::registerLibertyPort(const Port* port, const LibertyPort* lport) -{ - liberty_ports_[port] = lport; -} - bool dbNetwork::isConcretePort(const Port* port) const { if (concrete_ports_.find(port) != concrete_ports_.end()) { From b7bbedd473f4624d9b02479d6f95e9b40c253cbb Mon Sep 17 00:00:00 2001 From: andyfox-rushc Date: Sat, 20 Jul 2024 15:06:46 -0700 Subject: [PATCH 06/37] Support for bus ports in odb. Signed-off-by: Andy Fox andy@rushc.com Signed-off-by: andyfox-rushc --- src/dbSta/include/db_sta/dbNetwork.hh | 8 + src/dbSta/src/dbNetwork.cc | 278 +++++++++++++++-- src/dbSta/src/dbReadVerilog.cc | 34 ++- src/dbSta/src/dbSta.i | 3 +- src/dbSta/test/hier2_out.vok | 12 +- src/dbSta/test/hierclock_out.vok | 122 +++----- src/odb/include/odb/db.h | 33 ++- src/odb/include/odb/dbObject.h | 1 + .../codeGenerator/schema/chip/dbBusPort.json | 53 ++++ .../codeGenerator/schema/chip/dbModBterm.json | 21 +- src/odb/src/db/CMakeLists.txt | 1 + src/odb/src/db/dbBlock.cpp | 7 + src/odb/src/db/dbBlock.h | 3 + src/odb/src/db/dbBusPort.cpp | 279 ++++++++++++++++++ src/odb/src/db/dbBusPort.h | 73 +++++ src/odb/src/db/dbDatabase.h | 5 +- src/odb/src/db/dbModBTerm.cpp | 75 ++++- src/odb/src/db/dbModBTerm.h | 3 + src/odb/src/db/dbModule.cpp | 17 ++ src/odb/src/db/dbObject.cpp | 1 + 20 files changed, 904 insertions(+), 125 deletions(-) create mode 100644 src/odb/src/codeGenerator/schema/chip/dbBusPort.json create mode 100644 src/odb/src/db/dbBusPort.cpp create mode 100644 src/odb/src/db/dbBusPort.h diff --git a/src/dbSta/include/db_sta/dbNetwork.hh b/src/dbSta/include/db_sta/dbNetwork.hh index c389877704..3bcb14a522 100644 --- a/src/dbSta/include/db_sta/dbNetwork.hh +++ b/src/dbSta/include/db_sta/dbNetwork.hh @@ -196,6 +196,8 @@ class dbNetwork : public ConcreteNetwork Instance* topInstance() const override; // Name local to containing cell/instance. const char* name(const Instance* instance) const override; + const char* name(const Port* port) const override; + const char* busName(const Port* port) const override; ObjectId id(const Instance* instance) const override; Cell* cell(const Instance* instance) const override; Instance* parent(const Instance* instance) const override; @@ -240,6 +242,7 @@ class dbNetwork : public ConcreteNetwork bool isConcretePort(const Port*) const; bool isLibertyPort(const Port*) const; + LibertyPort* libertyPort(const Port* port) const override; PortDirection* direction(const Port* port) const override; //////////////////////////////////////////////////////////////// @@ -288,8 +291,13 @@ class dbNetwork : public ConcreteNetwork // hierarchy handler, set in openroad tested in network child traverserser void setHierarchy() { hierarchy_ = true; } bool hasHierarchy() const { return hierarchy_; } + + int fromIndex(const Port* port) const; + int toIndex(const Port* port) const; + bool isBus(const Port*) const; bool hasMembers(const Port* port) const; Port* findMember(const Port* port, int index) const; + PortMemberIterator* memberIterator(const Port* port) const; using Network::cell; using Network::direction; diff --git a/src/dbSta/src/dbNetwork.cc b/src/dbSta/src/dbNetwork.cc index 994d26bdce..e500e15f7e 100644 --- a/src/dbSta/src/dbNetwork.cc +++ b/src/dbSta/src/dbNetwork.cc @@ -91,6 +91,7 @@ using odb::dbBlock; using odb::dbBoolProperty; using odb::dbBTerm; using odb::dbBTermObj; +using odb::dbBusPort; using odb::dbChip; using odb::dbDatabase; using odb::dbInst; @@ -623,6 +624,49 @@ ObjectId dbNetwork::id(const Instance* instance) const return staToDb(instance)->getId(); } +const char* dbNetwork::name(const Port* port) const +{ + if (isConcretePort(port)) { + const ConcretePort* cport = reinterpret_cast(port); + return cport->name(); + } else { + dbMTerm* mterm = nullptr; + dbModBTerm* modbterm = nullptr; + dbBTerm* bterm = nullptr; + staToDb(port, bterm, mterm, modbterm); + if (bterm) { + return bterm->getName().c_str(); + } + if (mterm) { + return mterm->getName().c_str(); + } + if (modbterm) { + return modbterm->getName(); + } + } + return nullptr; +} + +const char* dbNetwork::busName(const Port* port) const +{ + if (isConcretePort(port)) { + const ConcretePort* cport = reinterpret_cast(port); + return cport->busName(); + } else { + dbMTerm* mterm = nullptr; + dbModBTerm* modbterm = nullptr; + dbBTerm* bterm = nullptr; + staToDb(port, bterm, mterm, modbterm); + if (modbterm) { + if (modbterm->isBusPort()) { + return modbterm->getBusPort()->getName(); + } + } + assert(0); + return nullptr; + } +} + const char* dbNetwork::name(const Instance* instance) const { if (instance == top_instance_) { @@ -653,6 +697,8 @@ const char* dbNetwork::name(const Cell* cell) const //////////////////////////////////////////////////////////////// // Module port iterator, allows traversal across dbModulePorts +// Traverse the ports in creation order (from end to beginning). + class dbModulePortIterator : public CellPortIterator { public: @@ -662,13 +708,20 @@ class dbModulePortIterator : public CellPortIterator virtual Port* next(); private: - dbSet::iterator iter_; + const dbModBTerm* iter_; const dbModule* module_; + int ix; }; dbModulePortIterator::dbModulePortIterator(const dbModule* cell) { - iter_ = (const_cast(cell)->getModBTerms()).begin(); + // skip to end + const dbModBTerm* first_mod_bterm = cell->getHeadDbModBTerm(); + for (iter_ = cell->getHeadDbModBTerm(); iter_; iter_ = iter_->getNext()) { + first_mod_bterm = iter_; + } + iter_ = first_mod_bterm; + ix = 0; module_ = cell; } @@ -678,19 +731,29 @@ dbModulePortIterator::~dbModulePortIterator() bool dbModulePortIterator::hasNext() { - if (iter_ == (const_cast(module_))->getModBTerms().end()) - return false; - return true; + if (iter_) + return true; + return false; } Port* dbModulePortIterator::next() { - if (iter_ == (const_cast(module_))->getModBTerms().end()) - return nullptr; - dbModBTerm* modbterm = *iter_; + ix++; + dbModBTerm* modbterm = const_cast(iter_); Port* ret = reinterpret_cast(modbterm); - // advance to next - iter_++; + // advance to next, in case of bus port + // next modbterm is the one after the bus port + if (modbterm->isBusPort()) { + dbBusPort* bp = modbterm->getBusPort(); + int size = bp->getSize(); + // skip into the content of the bus + iter_ = iter_->getPrev(); + for (int skip_ix = 0; skip_ix < size && (iter_->getPrev()); skip_ix++) { + iter_ = iter_->getPrev(); + } + } else { + iter_ = iter_->getPrev(); + } return ret; } @@ -711,10 +774,6 @@ CellPortIterator* dbNetwork::portIterator(const Cell* cell) const Cell* dbNetwork::cell(const Port* port) const { - // Check -- can we just do is HPort ? - // rather than stash everything at leaf level - // looks like we have to keep cports and ccells in tables. - // if (isConcretePort(port)) { const ConcretePort* cport = reinterpret_cast(port); return cport->cell(); @@ -2029,12 +2088,6 @@ void dbNetwork::staToDb(const Cell* cell, { module = nullptr; master = nullptr; - // - // Check with Matt.. - // Can we kill this test ? eg look up cell by name in library ? -- apparently - // not looping problem staToDb is called by name. Or do something different ?? - // Otherwise we are stuck with map. - // if (isConcreteCell(cell) || cell == top_cell_) { const ConcreteCell* ccell = reinterpret_cast(cell); master = reinterpret_cast(ccell->extCell()); @@ -2259,11 +2312,19 @@ LibertyCell* dbNetwork::libertyCell(dbInst* inst) return libertyCell(dbToSta(inst)); } +LibertyPort* dbNetwork::libertyPort(const Port* port) const +{ + if (isConcretePort(port)) { + LibertyPort* ret = ConcreteNetwork::libertyPort(port); + return ret; + } + return nullptr; +} + LibertyPort* dbNetwork::libertyPort(const Pin* pin) const { // Primary: needs concrete test. // Look up instance - const Port* cur_port = port(pin); const Instance* cur_instance = instance(pin); dbInst* db_inst = nullptr; dbModInst* mod_inst = nullptr; @@ -2291,6 +2352,8 @@ void dbNetwork::registerConcreteCell(const Cell* cell) bool dbNetwork::isConcreteCell(const Cell* cell) const { + if (!hierarchy_) + return true; return (concrete_cells_.find(cell) != concrete_cells_.end()); } @@ -2301,33 +2364,194 @@ void dbNetwork::registerConcretePort(const Port* port) bool dbNetwork::isConcretePort(const Port* port) const { + if (!hierarchy_) + return true; if (concrete_ports_.find(port) != concrete_ports_.end()) { return true; } return false; } -bool dbNetwork::hasMembers(const Port* port) const +/* +PortBus support +*/ + +bool dbNetwork::isBus(const Port* port) const { if (isConcretePort(port)) { - const ConcretePort* cport = reinterpret_cast(port); - return cport->hasMembers(); + return ConcreteNetwork::isBus(port); } else { - // TODO: bus ports in hierarchy. (Bus support in next pull) - return false; + dbMTerm* mterm = nullptr; + dbBTerm* bterm = nullptr; + dbModBTerm* modbterm = nullptr; + staToDb(port, bterm, mterm, modbterm); + if (modbterm && modbterm->isBusPort()) { + return true; + } else { + return false; + } } return false; } +int dbNetwork::fromIndex(const Port* port) const +{ + if (isConcretePort(port)) { + return ConcreteNetwork::fromIndex(port); + } else { + dbMTerm* mterm = nullptr; + dbBTerm* bterm = nullptr; + dbModBTerm* modbterm = nullptr; + staToDb(port, bterm, mterm, modbterm); + if (modbterm && modbterm->isBusPort()) { + return modbterm->getBusPort()->getStartIx(); + } + } + assert(0); + return 0; +} + +int dbNetwork::toIndex(const Port* port) const +{ + if (isConcretePort(port)) { + return ConcreteNetwork::toIndex(port); + } else { + dbMTerm* mterm = nullptr; + dbBTerm* bterm = nullptr; + dbModBTerm* modbterm = nullptr; + staToDb(port, bterm, mterm, modbterm); + if (modbterm && modbterm->isBusPort()) { + int start_ix = modbterm->getBusPort()->getStartIx(); + if (modbterm->getBusPort()->isUpdown()) { + return (start_ix + (modbterm->getBusPort()->getSize() - 1)); + } else { + return (start_ix - (modbterm->getBusPort()->getSize() - 1)); + } + } + } + assert(0); + return 0; +} + +bool dbNetwork::hasMembers(const Port* port) const +{ + if (hierarchy_) { + dbMTerm* mterm = nullptr; + dbBTerm* bterm = nullptr; + dbModBTerm* modbterm = nullptr; + staToDb(port, bterm, mterm, modbterm); + if (modbterm && modbterm->isBusPort()) { + return true; + } else { + return false; + } + } else { + const ConcretePort* cport = reinterpret_cast(port); + return cport->hasMembers(); + } +} + Port* dbNetwork::findMember(const Port* port, int index) const { if (isConcretePort(port)) { const ConcretePort* cport = reinterpret_cast(port); return reinterpret_cast(cport->findMember(index)); } else { - // TODO: hierarhcial ports, bus support in next pull. + // get the indexed busport member. + dbMTerm* mterm = nullptr; + dbBTerm* bterm = nullptr; + dbModBTerm* modbterm = nullptr; + staToDb(port, bterm, mterm, modbterm); + if (modbterm && modbterm->isBusPort()) { + dbBusPort* busport = modbterm->getBusPort(); + return reinterpret_cast(busport->fetchIndexedPort(index)); + } return nullptr; } + return nullptr; +} + +class DbNetworkPortMemberIterator : public PortMemberIterator +{ + public: + explicit DbNetworkPortMemberIterator(const Port* port, const dbNetwork* nwk); + ~DbNetworkPortMemberIterator(); + virtual bool hasNext(); + virtual Port* next(); + + private: + int size_; + int ix_; + dbModBTerm* next_; + dbSet::iterator iter_; + const dbNetwork* nwk_; +}; + +DbNetworkPortMemberIterator::DbNetworkPortMemberIterator(const Port* port, + const dbNetwork* nwk) +{ + size_ = 0; + ix_ = -1; + next_ = nullptr; + dbMTerm* mterm = nullptr; + dbBTerm* bterm = nullptr; + dbModBTerm* modbterm = nullptr; + nwk_ = nwk; + + nwk_->staToDb(port, bterm, mterm, modbterm); + if (modbterm && modbterm->isBusPort()) { + dbBusPort* busport = modbterm->getBusPort(); + size_ = busport->getSize(); + // advance iterator to this modbterm. + // note port iterator uses getModBTerms order. + // so member iterator does likewise. We traverse backwards + // through the list. + next_ = modbterm->getPrev(); + } +} + +DbNetworkPortMemberIterator::~DbNetworkPortMemberIterator() +{ +} + +/* +Note the side effect: hasNext() increments iterators +in this traverser. Others do it in next() +*/ + +bool DbNetworkPortMemberIterator::hasNext() +{ + ix_++; + if (ix_ == 0) { + if (next_) { + return true; + } else { + return false; + } + } else { + if (ix_ < size_) { + // note how we keep traversing through the modbterms on the "cell" + // so a busport -> port -> busport is feasible. + next_ = next_->getPrev(); + return true; + } + } + next_ = nullptr; + return false; +} + +Port* DbNetworkPortMemberIterator::next() +{ + return reinterpret_cast(next_); +} + +PortMemberIterator* dbNetwork::memberIterator(const Port* port) const +{ + if (!hierarchy_) { + return ConcreteNetwork::memberIterator(port); + } else { + return new DbNetworkPortMemberIterator(port, this); + } } //////////////////////////////////////////////////////////////// diff --git a/src/dbSta/src/dbReadVerilog.cc b/src/dbSta/src/dbReadVerilog.cc index 3b6f878f20..1d8d460c43 100644 --- a/src/dbSta/src/dbReadVerilog.cc +++ b/src/dbSta/src/dbReadVerilog.cc @@ -53,6 +53,7 @@ namespace ord { using odb::dbBlock; using odb::dbBTerm; +using odb::dbBusPort; using odb::dbChip; using odb::dbDatabase; using odb::dbInst; @@ -367,23 +368,31 @@ void Verilog2db::makeDbModule( CellPortIterator* cp_iter = network_->portIterator(cell); while (cp_iter->hasNext()) { Port* port = cp_iter->next(); - /* Ports are prefixed by instance name*/ if (network_->isBus(port)) { + int from_index = network_->fromIndex(port); + int to_index = network_->toIndex(port); + bool up_down = to_index >= from_index ? true : false; + int size = up_down ? (to_index - from_index) + 1 + : (from_index - to_index) + 1; + // make the bus port as part of the port set for the cell. + dbBusPort* dbbusport = dbBusPort::create(module, + network_->name(port), + network_->fromIndex(port), + up_down, + size); const char* port_name = network_->name(port); - const char* cell_name = network_->name(cell); - int from = network_->fromIndex(port); - int to = network_->toIndex(port); - string key = "bus_msb_first "; - key += key + port_name + " " + cell_name; - key += port_name; - odb::dbBoolProperty::create(block_, key.c_str(), from > to); + dbModBTerm* bmodterm = dbModBTerm::create(module, port_name); + bmodterm->setBusPort(dbbusport); + dbIoType io_type = staToDb(network_->direction(port)); + bmodterm->setIoType(io_type); + // Make a modbterm for each bus bit - int start_index = from < to ? from : to; - int end_index = from < to ? to : from; - for (int i = start_index; i <= end_index; i++) { + // Keep traversal in terms of bits + for (int i = 0; i < size; i++) { + int ix = up_down ? from_index + i : from_index - i; // use actual here std::string bus_bit_port = port_name + std::string("[") - + std::to_string(i) + std::string("]"); + + std::to_string(ix) + std::string("]"); dbModBTerm* bmodterm = dbModBTerm::create(module, bus_bit_port.c_str()); dbIoType io_type = staToDb(network_->direction(port)); @@ -419,6 +428,7 @@ void Verilog2db::makeDbModule( } } } + InstanceChildIterator* child_iter = network_->childIterator(inst); while (child_iter->hasNext()) { Instance* child = child_iter->next(); diff --git a/src/dbSta/src/dbSta.i b/src/dbSta/src/dbSta.i index ac23942210..c014b64245 100644 --- a/src/dbSta/src/dbSta.i +++ b/src/dbSta/src/dbSta.i @@ -168,7 +168,8 @@ write_verilog_cmd(const char *filename, { // This does NOT want the SDC (cmd) network because it wants // to see the sta internal names. - Sta *sta = Sta::sta(); + ord::OpenRoad *openroad = ord::getOpenRoad(); + sta::dbSta *sta = openroad->getSta(); Network *network = sta->network(); sta::writeVerilog(filename, sort, include_pwr_gnd, remove_cells, network); delete remove_cells; diff --git a/src/dbSta/test/hier2_out.vok b/src/dbSta/test/hier2_out.vok index 27d5465169..fb3f0ebab1 100644 --- a/src/dbSta/test/hier2_out.vok +++ b/src/dbSta/test/hier2_out.vok @@ -9,16 +9,16 @@ module top (a, INV_X1 _4_ (.ZN(a_int), .A(a)); - gate1 gate2_inst (.zn(out), + gate1 gate2_inst (.a1(a_int), .a2(b), - .a1(a_int)); + .zn(out)); endmodule -module gate1 (zn, +module gate1 (a1, a2, - a1); - output zn; - input a2; + zn); input a1; + input a2; + output zn; AND2_X1 \gate2_inst/_5_ (.ZN(zn), diff --git a/src/dbSta/test/hierclock_out.vok b/src/dbSta/test/hierclock_out.vok index 9467c5a14c..58bb619316 100644 --- a/src/dbSta/test/hierclock_out.vok +++ b/src/dbSta/test/hierclock_out.vok @@ -78,43 +78,43 @@ module hierclock (a_count_valid_o, wire \U3/_42_ ; wire [2:0] \U1/counter_q ; - clockgen U1 (.clk2_o(clk2_int), + clockgen U1 (.clk_i(clk_i), + .rst_n_i(rst_n_i), .clk1_o(clk1_int), + .clk2_o(clk2_int)); + counter U2 (.clk_i(clk1_int), .rst_n_i(rst_n_i), - .clk_i(clk_i)); - counter U2 (.count_valid_o(a_count_valid_o), - .\count_value_o[3] (a_count_o[3]), - .\count_value_o[2] (a_count_o[2]), - .\count_value_o[1] (a_count_o[1]), - .\count_value_o[0] (a_count_o[0]), - .\load_value_i[3] (a_i[3]), - .\load_value_i[2] (a_i[2]), - .\load_value_i[1] (a_i[1]), - .\load_value_i[0] (a_i[0]), .load_i(a_ld_i), + .load_value_i({a_i[3], + a_i[2], + a_i[1], + a_i[0]}), + .count_value_o({a_count_o[3], + a_count_o[2], + a_count_o[1], + a_count_o[0]}), + .count_valid_o(a_count_valid_o)); + counter-1 U3 (.clk_i(clk2_int), .rst_n_i(rst_n_i), - .clk_i(clk1_int)); - counter-1 U3 (.count_valid_o(b_count_valid_o), - .\count_value_o[3] (b_count_o[3]), - .\count_value_o[2] (b_count_o[2]), - .\count_value_o[1] (b_count_o[1]), - .\count_value_o[0] (b_count_o[0]), - .\load_value_i[3] (b_i[3]), - .\load_value_i[2] (b_i[2]), - .\load_value_i[1] (b_i[1]), - .\load_value_i[0] (b_i[0]), .load_i(b_ld_i), - .rst_n_i(rst_n_i), - .clk_i(clk2_int)); + .load_value_i({b_i[3], + b_i[2], + b_i[1], + b_i[0]}), + .count_value_o({b_count_o[3], + b_count_o[2], + b_count_o[1], + b_count_o[0]}), + .count_valid_o(b_count_valid_o)); endmodule -module clockgen (clk2_o, - clk1_o, +module clockgen (clk_i, rst_n_i, - clk_i); - output clk2_o; - output clk1_o; - input rst_n_i; + clk1_o, + clk2_o); input clk_i; + input rst_n_i; + output clk1_o; + output clk2_o; INV_X1 \U1/_28_ (.A(rst_n_i), @@ -165,30 +165,18 @@ module clockgen (clk2_o, .Q(counter_q[3]), .QN(_19_)); endmodule -module counter (count_valid_o, - \count_value_o[3] , - \count_value_o[2] , - \count_value_o[1] , - \count_value_o[0] , - \load_value_i[3] , - \load_value_i[2] , - \load_value_i[1] , - \load_value_i[0] , - load_i, +module counter (clk_i, rst_n_i, - clk_i); - output count_valid_o; - output \count_value_o[3] ; - output \count_value_o[2] ; - output \count_value_o[1] ; - output \count_value_o[0] ; - input \load_value_i[3] ; - input \load_value_i[2] ; - input \load_value_i[1] ; - input \load_value_i[0] ; - input load_i; - input rst_n_i; + load_i, + load_value_i, + count_value_o, + count_valid_o); input clk_i; + input rst_n_i; + input load_i; + input [3:0] load_value_i; + output [3:0] count_value_o; + output count_valid_o; INV_X1 \U2/_49_ (.A(_41_), @@ -267,30 +255,18 @@ module counter (count_valid_o, .Q(counter_q[3]), .QN(_38_)); endmodule -module counter-1 (count_valid_o, - \count_value_o[3] , - \count_value_o[2] , - \count_value_o[1] , - \count_value_o[0] , - \load_value_i[3] , - \load_value_i[2] , - \load_value_i[1] , - \load_value_i[0] , - load_i, +module counter-1 (clk_i, rst_n_i, - clk_i); - output count_valid_o; - output \count_value_o[3] ; - output \count_value_o[2] ; - output \count_value_o[1] ; - output \count_value_o[0] ; - input \load_value_i[3] ; - input \load_value_i[2] ; - input \load_value_i[1] ; - input \load_value_i[0] ; - input load_i; - input rst_n_i; + load_i, + load_value_i, + count_value_o, + count_valid_o); input clk_i; + input rst_n_i; + input load_i; + input [3:0] load_value_i; + output [3:0] count_value_o; + output count_valid_o; INV_X1 \U3/_49_ (.A(_41_), diff --git a/src/odb/include/odb/db.h b/src/odb/include/odb/db.h index 0bb8d69d98..f86eab4a70 100644 --- a/src/odb/include/odb/db.h +++ b/src/odb/include/odb/db.h @@ -128,6 +128,7 @@ class dbViaParams; // Generator Code Begin ClassDeclarations class dbAccessPoint; +class dbBusPort; class dbDft; class dbGCellGrid; class dbGlobalConnect; @@ -7147,6 +7148,31 @@ class dbAccessPoint : public dbObject // User Code End dbAccessPoint }; +class dbBusPort : public dbObject +{ + public: + const char* getName() const; + + int getStartIx() const; + + int getSize() const; + + bool isUpdown() const; + + dbModule* getParent() const; + + dbModBTerm* getFirstmember() const; + + // User Code Begin dbBusPort + static dbBusPort* create(dbModule* parentModule, + const char* name, + int from_index, + bool updown, + int size); + dbModBTerm* fetchIndexedPort(int offset); + // User Code End dbBusPort +}; + // Top level DFT (Design for Testing) class class dbDft : public dbObject { @@ -7567,7 +7593,11 @@ class dbModBTerm : public dbObject void disconnect(); void staSetPort(void* p); void* staPort(); - + bool isBusPort() const; + void setBusPort(dbBusPort*); + dbBusPort* getBusPort() const; + dbModBTerm* getNext() const; + dbModBTerm* getPrev() const; static dbModBTerm* create(dbModule* parentModule, const char* name); // User Code End dbModBTerm @@ -7678,6 +7708,7 @@ class dbModule : public dbObject void staSetCell(void* cell); void* getStaCell(); + const dbModBTerm* getHeadDbModBTerm() const; static dbModule* create(dbBlock* block, const char* name); diff --git a/src/odb/include/odb/dbObject.h b/src/odb/include/odb/dbObject.h index ef30f72ee8..6ac1809fa8 100644 --- a/src/odb/include/odb/dbObject.h +++ b/src/odb/include/odb/dbObject.h @@ -87,6 +87,7 @@ enum dbObjectType dbBPinObj, // Generator Code Begin DbObjectType dbAccessPointObj, + dbBusPortObj, dbDftObj, dbGCellGridObj, dbGlobalConnectObj, diff --git a/src/odb/src/codeGenerator/schema/chip/dbBusPort.json b/src/odb/src/codeGenerator/schema/chip/dbBusPort.json new file mode 100644 index 0000000000..3b3bab93f1 --- /dev/null +++ b/src/odb/src/codeGenerator/schema/chip/dbBusPort.json @@ -0,0 +1,53 @@ +{ + "name":"dbBusPort", + "type":"dbObject", + "fields":[ + { + "name":"_name", + "type":"char *", + "flags":["no-set"], + "default":"nullptr", + "schema":"db_schema_odb_busport" + }, + { + "name": "_start_ix", + "type": "int", + "flags":["no-set"], + "default":"0", + "schema":"db_schema_odb_busport" + }, + { + "name":"_size", + "type":"int", + "flags":["no-set"], + "default":"0", + "schema":"db_schema_odb_busport" + }, + { + "name":"_updown", + "type":"bool", + "flags":["no-set"], + "default":"false", + "schema":"db_schema_odb_busport" + }, + + { + "name":"_parent", + "type":"dbId<_dbModule>", + "flags":["no-set"], + "schema":"db_schema_odb_busport", + "parent":"dbBlock" + }, + + { + "name":"_firstmember", + "type": "dbId<_dbModBTerm>", + "flags":["no-set"], + "default":"0", + "schema":"db_schema_odb_busport", + "parent":"dbBlock" + } + ], + "constructors":[], + "cpp_includes":["dbBlock.h","dbModBTerm.h","dbModule.h","dbModNet.h","dbHashTable.hpp","dbModITerm.h","dbBusPort.h"] +} diff --git a/src/odb/src/codeGenerator/schema/chip/dbModBterm.json b/src/odb/src/codeGenerator/schema/chip/dbModBterm.json index b8ca1eaf82..85b94614fb 100644 --- a/src/odb/src/codeGenerator/schema/chip/dbModBterm.json +++ b/src/odb/src/codeGenerator/schema/chip/dbModBterm.json @@ -7,7 +7,7 @@ "type":"char *", "flags":["no-set"], "default":"nullptr", - "schema":"db_schema_update_hierarchy" + "schema":"db_schema_update_hierarchy" }, { "name":"_flags", @@ -51,14 +51,29 @@ "schema":"db_schema_update_hierarchy", "parent":"dbBlock" }, + { + "name":"_busPort", + "type":"dbId<_dbBusPort>", + "flags":["private"], + "schema":"db_schema_odb_busport", + "parent":"dbBlock" + }, + { "name":"_next_entry", - "type":"dbId<_dbModBTerm>", + "type":"dbId<_dbModBTerm>", "flags":["private"], "schema":"db_schema_update_hierarchy", "parent":"dbBlock" + }, + { + "name":"_prev_entry", + "type":"dbId<_dbModBTerm>", + "flags":["private"], + "schema":"db_schema_odb_busport", + "parent":"dbBlock" } ], "constructors":[], - "cpp_includes":["dbBlock.h","dbModule.h","dbModNet.h","dbHashTable.hpp","dbModITerm.h"] + "cpp_includes":["dbBlock.h","dbModule.h","dbModNet.h","dbHashTable.hpp","dbModITerm.h","dbBusPort.h"] } diff --git a/src/odb/src/db/CMakeLists.txt b/src/odb/src/db/CMakeLists.txt index 5490e7f2cc..56bab7daf0 100644 --- a/src/odb/src/db/CMakeLists.txt +++ b/src/odb/src/db/CMakeLists.txt @@ -85,6 +85,7 @@ add_library(db dbGroupGroundNetItr.cpp # Generator Code Begin cpp dbAccessPoint.cpp + dbBusPort.cpp dbDft.cpp dbGCellGrid.cpp dbGlobalConnect.cpp diff --git a/src/odb/src/db/dbBlock.cpp b/src/odb/src/db/dbBlock.cpp index 2a7859197b..1ca20381d5 100644 --- a/src/odb/src/db/dbBlock.cpp +++ b/src/odb/src/db/dbBlock.cpp @@ -51,6 +51,7 @@ #include "dbBlockage.h" #include "dbBox.h" #include "dbBoxItr.h" +#include "dbBusPort.h" #include "dbCCSeg.h" #include "dbCCSegItr.h" #include "dbCapNode.h" @@ -212,6 +213,9 @@ _dbBlock::_dbBlock(_dbDatabase* db) _modnet_tbl = new dbTable<_dbModNet>( db, this, (GetObjTbl_t) &_dbBlock::getObjectTable, dbModNetObj); + _busport_tbl = new dbTable<_dbBusPort>( + db, this, (GetObjTbl_t) &_dbBlock::getObjectTable, dbBusPortObj); + _powerdomain_tbl = new dbTable<_dbPowerDomain>( db, this, (GetObjTbl_t) &_dbBlock::getObjectTable, dbPowerDomainObj); @@ -348,6 +352,7 @@ _dbBlock::_dbBlock(_dbDatabase* db) _modbterm_hash.setTable(_modbterm_tbl); _moditerm_hash.setTable(_moditerm_tbl); _modnet_hash.setTable(_modnet_tbl); + _busport_hash.setTable(_busport_tbl); _powerdomain_hash.setTable(_powerdomain_tbl); _logicport_hash.setTable(_logicport_tbl); _powerswitch_hash.setTable(_powerswitch_tbl); @@ -966,6 +971,7 @@ dbOStream& operator<<(dbOStream& stream, const _dbBlock& block) stream << block._modbterm_hash; stream << block._moditerm_hash; stream << block._modnet_hash; + stream << block._busport_hash; } stream << block._powerdomain_hash; stream << block._logicport_hash; @@ -1085,6 +1091,7 @@ dbIStream& operator>>(dbIStream& stream, _dbBlock& block) stream >> block._modbterm_hash; stream >> block._moditerm_hash; stream >> block._modnet_hash; + stream >> block._busport_hash; } stream >> block._powerdomain_hash; stream >> block._logicport_hash; diff --git a/src/odb/src/db/dbBlock.h b/src/odb/src/db/dbBlock.h index 27c355dcc8..5b2266fe97 100644 --- a/src/odb/src/db/dbBlock.h +++ b/src/odb/src/db/dbBlock.h @@ -93,6 +93,7 @@ class _dbModInst; class _dbModITerm; class _dbModBTerm; class _dbModNet; +class _dbBusPort; class _dbGroup; class _dbAccessPoint; class _dbGlobalConnect; @@ -185,6 +186,7 @@ class _dbBlock : public _dbObject dbHashTable<_dbModBTerm> _modbterm_hash; dbHashTable<_dbModITerm> _moditerm_hash; dbHashTable<_dbModNet> _modnet_hash; + dbHashTable<_dbBusPort> _busport_hash; dbHashTable<_dbLevelShifter> _levelshifter_hash; dbHashTable<_dbGroup> _group_hash; @@ -243,6 +245,7 @@ class _dbBlock : public _dbObject dbTable<_dbModBTerm>* _modbterm_tbl; dbTable<_dbModITerm>* _moditerm_tbl; dbTable<_dbModNet>* _modnet_tbl; + dbTable<_dbBusPort>* _busport_tbl; dbTable<_dbCapNode>* _cap_node_tbl; dbTable<_dbRSeg>* _r_seg_tbl; diff --git a/src/odb/src/db/dbBusPort.cpp b/src/odb/src/db/dbBusPort.cpp new file mode 100644 index 0000000000..665478de5e --- /dev/null +++ b/src/odb/src/db/dbBusPort.cpp @@ -0,0 +1,279 @@ +/////////////////////////////////////////////////////////////////////////////// +// BSD 3-Clause License +// +// Copyright (c) 2022, The Regents of the University of California +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// * Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +// Generator Code Begin Cpp +#include "dbBusPort.h" + +#include "dbBlock.h" +#include "dbBusPort.h" +#include "dbDatabase.h" +#include "dbDiff.hpp" +#include "dbHashTable.hpp" +#include "dbModBTerm.h" +#include "dbModITerm.h" +#include "dbModNet.h" +#include "dbModule.h" +#include "dbTable.h" +#include "dbTable.hpp" +#include "odb/db.h" +namespace odb { +template class dbTable<_dbBusPort>; + +bool _dbBusPort::operator==(const _dbBusPort& rhs) const +{ + if (_name != rhs._name) { + return false; + } + if (_start_ix != rhs._start_ix) { + return false; + } + if (_size != rhs._size) { + return false; + } + if (_updown != rhs._updown) { + return false; + } + if (_parent != rhs._parent) { + return false; + } + if (_firstmember != rhs._firstmember) { + return false; + } + + return true; +} + +bool _dbBusPort::operator<(const _dbBusPort& rhs) const +{ + return true; +} + +void _dbBusPort::differences(dbDiff& diff, + const char* field, + const _dbBusPort& rhs) const +{ + DIFF_BEGIN + DIFF_FIELD(_name); + DIFF_FIELD(_start_ix); + DIFF_FIELD(_size); + DIFF_FIELD(_updown); + DIFF_FIELD(_parent); + DIFF_FIELD(_firstmember); + DIFF_END +} + +void _dbBusPort::out(dbDiff& diff, char side, const char* field) const +{ + DIFF_OUT_BEGIN + DIFF_OUT_FIELD(_name); + DIFF_OUT_FIELD(_start_ix); + DIFF_OUT_FIELD(_size); + DIFF_OUT_FIELD(_updown); + DIFF_OUT_FIELD(_parent); + DIFF_OUT_FIELD(_firstmember); + + DIFF_END +} + +_dbBusPort::_dbBusPort(_dbDatabase* db) +{ + _name = nullptr; + _start_ix = 0; + _size = 0; + _updown = false; + _firstmember = 0; +} + +_dbBusPort::_dbBusPort(_dbDatabase* db, const _dbBusPort& r) +{ + _name = r._name; + _start_ix = r._start_ix; + _size = r._size; + _updown = r._updown; + _parent = r._parent; + _firstmember = r._firstmember; +} + +dbIStream& operator>>(dbIStream& stream, _dbBusPort& obj) +{ + if (obj.getDatabase()->isSchema(db_schema_odb_busport)) { + stream >> obj._name; + } + if (obj.getDatabase()->isSchema(db_schema_odb_busport)) { + stream >> obj._start_ix; + } + if (obj.getDatabase()->isSchema(db_schema_odb_busport)) { + stream >> obj._size; + } + if (obj.getDatabase()->isSchema(db_schema_odb_busport)) { + stream >> obj._updown; + } + if (obj.getDatabase()->isSchema(db_schema_odb_busport)) { + stream >> obj._parent; + } + if (obj.getDatabase()->isSchema(db_schema_odb_busport)) { + stream >> obj._firstmember; + } + return stream; +} + +dbOStream& operator<<(dbOStream& stream, const _dbBusPort& obj) +{ + if (obj.getDatabase()->isSchema(db_schema_odb_busport)) { + stream << obj._name; + } + if (obj.getDatabase()->isSchema(db_schema_odb_busport)) { + stream << obj._start_ix; + } + if (obj.getDatabase()->isSchema(db_schema_odb_busport)) { + stream << obj._size; + } + if (obj.getDatabase()->isSchema(db_schema_odb_busport)) { + stream << obj._updown; + } + if (obj.getDatabase()->isSchema(db_schema_odb_busport)) { + stream << obj._parent; + } + if (obj.getDatabase()->isSchema(db_schema_odb_busport)) { + stream << obj._firstmember; + } + return stream; +} + +_dbBusPort::~_dbBusPort() +{ + if (_name) { + free((void*) _name); + } +} + +//////////////////////////////////////////////////////////////////// +// +// dbBusPort - Methods +// +//////////////////////////////////////////////////////////////////// + +const char* dbBusPort::getName() const +{ + _dbBusPort* obj = (_dbBusPort*) this; + return obj->_name; +} + +int dbBusPort::getStartIx() const +{ + _dbBusPort* obj = (_dbBusPort*) this; + return obj->_start_ix; +} + +int dbBusPort::getSize() const +{ + _dbBusPort* obj = (_dbBusPort*) this; + return obj->_size; +} + +bool dbBusPort::isUpdown() const +{ + _dbBusPort* obj = (_dbBusPort*) this; + return obj->_updown; +} + +dbModule* dbBusPort::getParent() const +{ + _dbBusPort* obj = (_dbBusPort*) this; + if (obj->_parent == 0) { + return nullptr; + } + _dbBlock* par = (_dbBlock*) obj->getOwner(); + return (dbModule*) par->_module_tbl->getPtr(obj->_parent); +} + +dbModBTerm* dbBusPort::getFirstmember() const +{ + _dbBusPort* obj = (_dbBusPort*) this; + if (obj->_firstmember == 0) { + return nullptr; + } + _dbBlock* par = (_dbBlock*) obj->getOwner(); + return (dbModBTerm*) par->_modbterm_tbl->getPtr(obj->_firstmember); +} + +// User Code Begin dbBusPortPublicMethods +dbBusPort* dbBusPort::create(dbModule* parentModule, + const char* name, + int from_index, + bool updown, + int size) +{ + _dbModule* module = (_dbModule*) parentModule; + _dbBlock* block = (_dbBlock*) module->getOwner(); + std::string str_name(name); + _dbBusPort* busport = block->_busport_tbl->create(); + busport->_start_ix = from_index; + busport->_size = size; + busport->_updown = updown; + busport->_firstmember = 0; + busport->_name = strdup(name); + busport->_parent = module->getOID(); + ZALLOCATED(busport->_name); + return (dbBusPort*) busport; +} + +// note on connectivity model +// we assume a fully connected model at the bit level +// so a bus port is a partition on the bit level model. +// eg +// for ports: {a,bus[3:0],j} +// then the fully connected model is a,bus[3],bus[2],bus[1],bus[0],j +// and to get the index element 1 from busPort we use bus[3]+1 = bus[2]. +// + +dbModBTerm* dbBusPort::fetchIndexedPort(int offset) +{ + _dbBusPort* obj = (_dbBusPort*) this; + _dbBlock* block_ = (_dbBlock*) obj->getOwner(); + if (obj->_firstmember == 0 || offset >= obj->_size) + return nullptr; + else { + int id = obj->_firstmember; + _dbModBTerm* element = block_->_modbterm_tbl->getPtr(id); + for (int posn = 0; (element != nullptr) && (posn != offset); posn++) { + id = element->_next_entry; + element = block_->_modbterm_tbl->getPtr(id); + } + return (dbModBTerm*) element; + } + return nullptr; +} + +// User Code End dbBusPortPublicMethods +} // namespace odb + // Generator Code End Cpp diff --git a/src/odb/src/db/dbBusPort.h b/src/odb/src/db/dbBusPort.h new file mode 100644 index 0000000000..df2214103b --- /dev/null +++ b/src/odb/src/db/dbBusPort.h @@ -0,0 +1,73 @@ +/////////////////////////////////////////////////////////////////////////////// +// BSD 3-Clause License +// +// Copyright (c) 2022, The Regents of the University of California +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// * Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +// Generator Code Begin Header +#pragma once + +#include "dbCore.h" +#include "odb/odb.h" + +namespace odb { +class dbIStream; +class dbOStream; +class dbDiff; +class _dbDatabase; +class _dbModule; +class _dbModBTerm; + +class _dbBusPort : public _dbObject +{ + public: + _dbBusPort(_dbDatabase*, const _dbBusPort& r); + _dbBusPort(_dbDatabase*); + + ~_dbBusPort(); + + bool operator==(const _dbBusPort& rhs) const; + bool operator!=(const _dbBusPort& rhs) const { return !operator==(rhs); } + bool operator<(const _dbBusPort& rhs) const; + void differences(dbDiff& diff, + const char* field, + const _dbBusPort& rhs) const; + void out(dbDiff& diff, char side, const char* field) const; + + char* _name; + int _start_ix; + int _size; + bool _updown; + dbId<_dbModule> _parent; + dbId<_dbModBTerm> _firstmember; +}; +dbIStream& operator>>(dbIStream& stream, _dbBusPort& obj); +dbOStream& operator<<(dbOStream& stream, const _dbBusPort& obj); +} // namespace odb + // Generator Code End Header \ No newline at end of file diff --git a/src/odb/src/db/dbDatabase.h b/src/odb/src/db/dbDatabase.h index 019e5fd763..fe69497a2a 100644 --- a/src/odb/src/db/dbDatabase.h +++ b/src/odb/src/db/dbDatabase.h @@ -70,7 +70,10 @@ namespace odb { const uint db_schema_major = 0; // Not used... const uint db_schema_initial = 57; -const uint db_schema_minor = 85; // Current revision number +const uint db_schema_minor = 86; // Current revision number + +// Revision where bus ports added to odb +const uint db_schema_odb_busport = 86; // Revision where constraint region was added to dbBTerm const uint db_schema_bterm_constraint_region = 85; diff --git a/src/odb/src/db/dbModBTerm.cpp b/src/odb/src/db/dbModBTerm.cpp index 6172a41750..0e0a469eb0 100644 --- a/src/odb/src/db/dbModBTerm.cpp +++ b/src/odb/src/db/dbModBTerm.cpp @@ -34,6 +34,7 @@ #include "dbModBTerm.h" #include "dbBlock.h" +#include "dbBusPort.h" #include "dbDatabase.h" #include "dbDiff.hpp" #include "dbHashTable.hpp" @@ -69,9 +70,15 @@ bool _dbModBTerm::operator==(const _dbModBTerm& rhs) const if (_prev_net_modbterm != rhs._prev_net_modbterm) { return false; } + if (_busPort != rhs._busPort) { + return false; + } if (_next_entry != rhs._next_entry) { return false; } + if (_prev_entry != rhs._prev_entry) { + return false; + } return true; } @@ -93,7 +100,9 @@ void _dbModBTerm::differences(dbDiff& diff, DIFF_FIELD(_modnet); DIFF_FIELD(_next_net_modbterm); DIFF_FIELD(_prev_net_modbterm); + DIFF_FIELD(_busPort); DIFF_FIELD(_next_entry); + DIFF_FIELD(_prev_entry); DIFF_END } @@ -107,7 +116,9 @@ void _dbModBTerm::out(dbDiff& diff, char side, const char* field) const DIFF_OUT_FIELD(_modnet); DIFF_OUT_FIELD(_next_net_modbterm); DIFF_OUT_FIELD(_prev_net_modbterm); + DIFF_OUT_FIELD(_busPort); DIFF_OUT_FIELD(_next_entry); + DIFF_OUT_FIELD(_prev_entry); DIFF_END } @@ -127,7 +138,9 @@ _dbModBTerm::_dbModBTerm(_dbDatabase* db, const _dbModBTerm& r) _modnet = r._modnet; _next_net_modbterm = r._next_net_modbterm; _prev_net_modbterm = r._prev_net_modbterm; + _busPort = r._busPort; _next_entry = r._next_entry; + _prev_entry = r._prev_entry; } dbIStream& operator>>(dbIStream& stream, _dbModBTerm& obj) @@ -153,9 +166,15 @@ dbIStream& operator>>(dbIStream& stream, _dbModBTerm& obj) if (obj.getDatabase()->isSchema(db_schema_update_hierarchy)) { stream >> obj._prev_net_modbterm; } + if (obj.getDatabase()->isSchema(db_schema_odb_busport)) { + stream >> obj._busPort; + } if (obj.getDatabase()->isSchema(db_schema_update_hierarchy)) { stream >> obj._next_entry; } + if (obj.getDatabase()->isSchema(db_schema_odb_busport)) { + stream >> obj._prev_entry; + } return stream; } @@ -182,9 +201,15 @@ dbOStream& operator<<(dbOStream& stream, const _dbModBTerm& obj) if (obj.getDatabase()->isSchema(db_schema_update_hierarchy)) { stream << obj._prev_net_modbterm; } + if (obj.getDatabase()->isSchema(db_schema_odb_busport)) { + stream << obj._busPort; + } if (obj.getDatabase()->isSchema(db_schema_update_hierarchy)) { stream << obj._next_entry; } + if (obj.getDatabase()->isSchema(db_schema_odb_busport)) { + stream << obj._prev_entry; + } return stream; } @@ -318,11 +343,17 @@ dbModBTerm* dbModBTerm::create(dbModule* parentModule, const char* name) modbterm->_modnet = 0; modbterm->_next_net_modbterm = 0; modbterm->_prev_net_modbterm = 0; - + modbterm->_busPort = 0; modbterm->_name = strdup(name); ZALLOCATED(modbterm->_name); modbterm->_parent = module->getOID(); modbterm->_next_entry = module->_modbterms; + // set back pointer. + if (module->_modbterms != 0) { + _dbModBTerm* head_entry = block->_modbterm_tbl->getPtr(module->_modbterms); + head_entry->_prev_entry = modbterm->getOID(); + } + modbterm->_prev_entry = 0; module->_modbterms = modbterm->getOID(); return (dbModBTerm*) modbterm; @@ -398,6 +429,48 @@ void* dbModBTerm::staPort() return _modbterm->_sta_port; } +bool dbModBTerm::isBusPort() const +{ + _dbModBTerm* _modbterm = (_dbModBTerm*) this; + return (_modbterm->_busPort != 0); +} + +dbBusPort* dbModBTerm::getBusPort() const +{ + _dbModBTerm* _modbterm = (_dbModBTerm*) this; + if (_modbterm->_busPort != 0) { + _dbBlock* block = (_dbBlock*) _modbterm->getOwner(); + return (dbBusPort*) block->_busport_tbl->getPtr(_modbterm->_busPort); + } + return nullptr; +} + +void dbModBTerm::setBusPort(dbBusPort* bus_port) +{ + _dbModBTerm* _modbterm = (_dbModBTerm*) this; + _modbterm->_busPort = bus_port->getId(); +} + +dbModBTerm* dbModBTerm::getNext() const +{ + _dbModBTerm* _modbterm = (_dbModBTerm*) this; + if (_modbterm->_next_entry != 0) { + _dbBlock* block_ = (_dbBlock*) _modbterm->getOwner(); + return (dbModBTerm*) block_->_modbterm_tbl->getPtr(_modbterm->_next_entry); + } + return nullptr; +} + +dbModBTerm* dbModBTerm::getPrev() const +{ + _dbModBTerm* _modbterm = (_dbModBTerm*) this; + if (_modbterm->_prev_entry != 0) { + _dbBlock* block_ = (_dbBlock*) _modbterm->getOwner(); + return (dbModBTerm*) block_->_modbterm_tbl->getPtr(_modbterm->_prev_entry); + } + return nullptr; +} + // User Code End dbModBTermPublicMethods } // namespace odb // Generator Code End Cpp diff --git a/src/odb/src/db/dbModBTerm.h b/src/odb/src/db/dbModBTerm.h index 51388bf3b3..4512c07635 100644 --- a/src/odb/src/db/dbModBTerm.h +++ b/src/odb/src/db/dbModBTerm.h @@ -44,6 +44,7 @@ class _dbDatabase; class _dbModITerm; class _dbModule; class _dbModNet; +class _dbBusPort; class _dbModBTerm : public _dbObject { @@ -68,7 +69,9 @@ class _dbModBTerm : public _dbObject dbId<_dbModNet> _modnet; dbId<_dbModBTerm> _next_net_modbterm; dbId<_dbModBTerm> _prev_net_modbterm; + dbId<_dbBusPort> _busPort; dbId<_dbModBTerm> _next_entry; + dbId<_dbModBTerm> _prev_entry; // User Code Begin Fields void* _sta_port = nullptr; diff --git a/src/odb/src/db/dbModule.cpp b/src/odb/src/db/dbModule.cpp index 115bc0ef31..994de5d615 100644 --- a/src/odb/src/db/dbModule.cpp +++ b/src/odb/src/db/dbModule.cpp @@ -213,6 +213,23 @@ dbModInst* dbModule::getModInst() const // User Code Begin dbModulePublicMethods +const dbModBTerm* dbModule::getHeadDbModBTerm() const +{ + _dbModule* obj = (_dbModule*) this; + _dbBlock* block_ = (_dbBlock*) obj->getOwner(); + if (obj->_modbterms == 0) { + return nullptr; + } + // note that the odb objects are "pre-pended" + // so first object is at tail. This means we are returning + // last object added. The application calling this routine + // needs to be aware of this (and possibly skip to the end + // of the list and then use prev to reconstruct creation order). + else { + return (dbModBTerm*) (block_->_modbterm_tbl->getPtr(obj->_modbterms)); + } +} + int dbModule::getModInstCount() { _dbModule* module = (_dbModule*) this; diff --git a/src/odb/src/db/dbObject.cpp b/src/odb/src/db/dbObject.cpp index a4ba9ee722..dd94fcdb64 100644 --- a/src/odb/src/db/dbObject.cpp +++ b/src/odb/src/db/dbObject.cpp @@ -91,6 +91,7 @@ static const char* name_tbl[] = {"dbDatabase", "dbBPin", // Generator Code Begin ObjectNames "dbAccessPoint", + "dbBusPort", "dbDft", "dbGCellGrid", "dbGlobalConnect", From 40d975c5a5dd37dcbe037f417a45ae18d19d2493 Mon Sep 17 00:00:00 2001 From: andyfox-rushc Date: Sun, 21 Jul 2024 07:07:53 -0700 Subject: [PATCH 07/37] Cleanups from tidy -- override on virtuals/if/else returns. Signed-off-by:Andy Fox andy@rushc.com Signed-off-by: andyfox-rushc --- src/dbSta/include/db_sta/dbNetwork.hh | 12 +-- src/dbSta/src/dbNetwork.cc | 143 +++++++++++--------------- 2 files changed, 68 insertions(+), 87 deletions(-) diff --git a/src/dbSta/include/db_sta/dbNetwork.hh b/src/dbSta/include/db_sta/dbNetwork.hh index 3bcb14a522..edcc3e805b 100644 --- a/src/dbSta/include/db_sta/dbNetwork.hh +++ b/src/dbSta/include/db_sta/dbNetwork.hh @@ -292,12 +292,12 @@ class dbNetwork : public ConcreteNetwork void setHierarchy() { hierarchy_ = true; } bool hasHierarchy() const { return hierarchy_; } - int fromIndex(const Port* port) const; - int toIndex(const Port* port) const; - bool isBus(const Port*) const; - bool hasMembers(const Port* port) const; - Port* findMember(const Port* port, int index) const; - PortMemberIterator* memberIterator(const Port* port) const; + int fromIndex(const Port* port) const override; + int toIndex(const Port* port) const override; + bool isBus(const Port*) const override; + bool hasMembers(const Port* port) const override; + Port* findMember(const Port* port, int index) const override; + PortMemberIterator* memberIterator(const Port* port) const override; using Network::cell; using Network::direction; diff --git a/src/dbSta/src/dbNetwork.cc b/src/dbSta/src/dbNetwork.cc index b915ebc91e..09b5b448b7 100644 --- a/src/dbSta/src/dbNetwork.cc +++ b/src/dbSta/src/dbNetwork.cc @@ -662,7 +662,7 @@ const char* dbNetwork::busName(const Port* port) const return modbterm->getBusPort()->getName(); } } - assert(0); + logger_->error(ORD, 2020, "Error: database badly formed bus name"); return nullptr; } } @@ -689,7 +689,8 @@ const char* dbNetwork::name(const Cell* cell) const staToDb(cell, db_master, db_module); if (db_master || cell == top_cell_) { return ConcreteNetwork::name(cell); - } else { + } + if (db_module) { return db_module->getName(); } return nullptr; @@ -731,8 +732,9 @@ dbModulePortIterator::~dbModulePortIterator() bool dbModulePortIterator::hasNext() { - if (iter_) + if (iter_) { return true; + } return false; } @@ -761,13 +763,12 @@ CellPortIterator* dbNetwork::portIterator(const Cell* cell) const { if (isConcreteCell(cell) || cell == top_cell_) { return ConcreteNetwork::portIterator(cell); - } else { - dbMaster* db_master; - dbModule* db_module; - staToDb(cell, db_master, db_module); - if (db_module) { - return new dbModulePortIterator(db_module); - } + } + dbMaster* db_master; + dbModule* db_module; + staToDb(cell, db_master, db_module); + if (db_module) { + return new dbModulePortIterator(db_module); } return nullptr; } @@ -777,11 +778,9 @@ Cell* dbNetwork::cell(const Port* port) const if (isConcretePort(port)) { const ConcretePort* cport = reinterpret_cast(port); return cport->cell(); - } else { - const dbModBTerm* modbterm = reinterpret_cast(port); - return (reinterpret_cast(modbterm->getParent())); } - return nullptr; + const dbModBTerm* modbterm = reinterpret_cast(port); + return (reinterpret_cast(modbterm->getParent())); } Cell* dbNetwork::cell(const Instance* instance) const @@ -789,7 +788,6 @@ Cell* dbNetwork::cell(const Instance* instance) const if (instance == top_instance_) { return reinterpret_cast(top_cell_); } - dbInst* db_inst; dbModInst* mod_inst; staToDb(instance, db_inst, mod_inst); @@ -799,7 +797,6 @@ Cell* dbNetwork::cell(const Instance* instance) const } if (mod_inst) { dbModule* master = mod_inst->getMaster(); - // look up the cell in the verilog library. return dbToSta(master); } return nullptr; @@ -810,7 +807,6 @@ Instance* dbNetwork::parent(const Instance* instance) const if (instance == top_instance_) { return nullptr; } - dbInst* db_inst; dbModInst* mod_inst; staToDb(instance, db_inst, mod_inst); @@ -834,9 +830,8 @@ bool dbNetwork::isLeaf(const Instance* instance) const dbModule* db_module; Cell* cur_cell = cell(instance); staToDb(cur_cell, db_master, db_module); - if (db_module) { + if (db_module) return false; - } return true; } return instance != top_instance_; @@ -894,7 +889,7 @@ Pin* dbNetwork::findPin(const Instance* instance, const char* port_name) const dbModITerm* miterm = mod_inst->findModITerm(port_name); return dbToSta(miterm); } - return nullptr; // no pins on dbModInst in odb currently + return nullptr; } Pin* dbNetwork::findPin(const Instance* instance, const Port* port) const @@ -1168,8 +1163,6 @@ PortDirection* dbNetwork::direction(const Pin* pin) const return dir; } - // Review with Matt -- seems to occur with some cases. (lef based ?) - // eg block_sta.tcl // // note the nasty default behaviour here. // if not a liberty port then return unknown @@ -2351,8 +2344,9 @@ void dbNetwork::registerConcreteCell(const Cell* cell) bool dbNetwork::isConcreteCell(const Cell* cell) const { - if (!hierarchy_) + if (!hierarchy_) { return true; + } return (concrete_cells_.find(cell) != concrete_cells_.end()); } @@ -2363,8 +2357,9 @@ void dbNetwork::registerConcretePort(const Port* port) bool dbNetwork::isConcretePort(const Port* port) const { - if (!hierarchy_) + if (!hierarchy_) { return true; + } if (concrete_ports_.find(port) != concrete_ports_.end()) { return true; } @@ -2379,16 +2374,14 @@ bool dbNetwork::isBus(const Port* port) const { if (isConcretePort(port)) { return ConcreteNetwork::isBus(port); - } else { - dbMTerm* mterm = nullptr; - dbBTerm* bterm = nullptr; - dbModBTerm* modbterm = nullptr; - staToDb(port, bterm, mterm, modbterm); - if (modbterm && modbterm->isBusPort()) { - return true; - } else { - return false; - } + } + + dbMTerm* mterm = nullptr; + dbBTerm* bterm = nullptr; + dbModBTerm* modbterm = nullptr; + staToDb(port, bterm, mterm, modbterm); + if (modbterm && modbterm->isBusPort()) { + return true; } return false; } @@ -2397,16 +2390,16 @@ int dbNetwork::fromIndex(const Port* port) const { if (isConcretePort(port)) { return ConcreteNetwork::fromIndex(port); - } else { - dbMTerm* mterm = nullptr; - dbBTerm* bterm = nullptr; - dbModBTerm* modbterm = nullptr; - staToDb(port, bterm, mterm, modbterm); - if (modbterm && modbterm->isBusPort()) { - return modbterm->getBusPort()->getStartIx(); - } } - assert(0); + dbMTerm* mterm = nullptr; + dbBTerm* bterm = nullptr; + dbModBTerm* modbterm = nullptr; + staToDb(port, bterm, mterm, modbterm); + if (modbterm && modbterm->isBusPort()) { + return modbterm->getBusPort()->getStartIx(); + } + + logger_->error(ORD, 2021, "Error: bad bus from_index defintion"); return 0; } @@ -2414,21 +2407,20 @@ int dbNetwork::toIndex(const Port* port) const { if (isConcretePort(port)) { return ConcreteNetwork::toIndex(port); - } else { - dbMTerm* mterm = nullptr; - dbBTerm* bterm = nullptr; - dbModBTerm* modbterm = nullptr; - staToDb(port, bterm, mterm, modbterm); - if (modbterm && modbterm->isBusPort()) { - int start_ix = modbterm->getBusPort()->getStartIx(); - if (modbterm->getBusPort()->isUpdown()) { - return (start_ix + (modbterm->getBusPort()->getSize() - 1)); - } else { - return (start_ix - (modbterm->getBusPort()->getSize() - 1)); - } + } + dbMTerm* mterm = nullptr; + dbBTerm* bterm = nullptr; + dbModBTerm* modbterm = nullptr; + staToDb(port, bterm, mterm, modbterm); + if (modbterm && modbterm->isBusPort()) { + int start_ix = modbterm->getBusPort()->getStartIx(); + if (modbterm->getBusPort()->isUpdown()) { + return (start_ix + (modbterm->getBusPort()->getSize() - 1)); } + return (start_ix - (modbterm->getBusPort()->getSize() - 1)); } - assert(0); + + logger_->error(ORD, 2022, "Error: bad bus to_index defintion"); return 0; } @@ -2441,13 +2433,12 @@ bool dbNetwork::hasMembers(const Port* port) const staToDb(port, bterm, mterm, modbterm); if (modbterm && modbterm->isBusPort()) { return true; - } else { - return false; } - } else { - const ConcretePort* cport = reinterpret_cast(port); - return cport->hasMembers(); + return false; } + + const ConcretePort* cport = reinterpret_cast(port); + return cport->hasMembers(); } Port* dbNetwork::findMember(const Port* port, int index) const @@ -2455,17 +2446,15 @@ Port* dbNetwork::findMember(const Port* port, int index) const if (isConcretePort(port)) { const ConcretePort* cport = reinterpret_cast(port); return reinterpret_cast(cport->findMember(index)); - } else { - // get the indexed busport member. - dbMTerm* mterm = nullptr; - dbBTerm* bterm = nullptr; - dbModBTerm* modbterm = nullptr; - staToDb(port, bterm, mterm, modbterm); - if (modbterm && modbterm->isBusPort()) { - dbBusPort* busport = modbterm->getBusPort(); - return reinterpret_cast(busport->fetchIndexedPort(index)); - } - return nullptr; + } + // get the indexed busport member. + dbMTerm* mterm = nullptr; + dbBTerm* bterm = nullptr; + dbModBTerm* modbterm = nullptr; + staToDb(port, bterm, mterm, modbterm); + if (modbterm && modbterm->isBusPort()) { + dbBusPort* busport = modbterm->getBusPort(); + return reinterpret_cast(busport->fetchIndexedPort(index)); } return nullptr; } @@ -2513,11 +2502,6 @@ DbNetworkPortMemberIterator::~DbNetworkPortMemberIterator() { } -/* -Note the side effect: hasNext() increments iterators -in this traverser. Others do it in next() -*/ - bool DbNetworkPortMemberIterator::hasNext() { ix_++; @@ -2529,8 +2513,6 @@ bool DbNetworkPortMemberIterator::hasNext() } } else { if (ix_ < size_) { - // note how we keep traversing through the modbterms on the "cell" - // so a busport -> port -> busport is feasible. next_ = next_->getPrev(); return true; } @@ -2548,9 +2530,8 @@ PortMemberIterator* dbNetwork::memberIterator(const Port* port) const { if (!hierarchy_) { return ConcreteNetwork::memberIterator(port); - } else { - return new DbNetworkPortMemberIterator(port, this); } + return new DbNetworkPortMemberIterator(port, this); } //////////////////////////////////////////////////////////////// From 918b5a3b667fc4c549d075f5d828427caf593fc2 Mon Sep 17 00:00:00 2001 From: andyfox-rushc Date: Sun, 21 Jul 2024 11:10:00 -0700 Subject: [PATCH 08/37] More ctidy clean ups -- overrides, memory. Signed-off-by: Andy Fox andy@rushc.com Signed-off-by: andyfox-rushc --- src/dbSta/include/db_sta/dbNetwork.hh | 6 +++--- src/dbSta/src/dbNetwork.cc | 29 +++++++++++++-------------- 2 files changed, 17 insertions(+), 18 deletions(-) diff --git a/src/dbSta/include/db_sta/dbNetwork.hh b/src/dbSta/include/db_sta/dbNetwork.hh index edcc3e805b..db2900dd0e 100644 --- a/src/dbSta/include/db_sta/dbNetwork.hh +++ b/src/dbSta/include/db_sta/dbNetwork.hh @@ -96,7 +96,7 @@ class dbNetwork : public ConcreteNetwork void init(dbDatabase* db, Logger* logger); void setBlock(dbBlock* block); void clear() override; - CellPortIterator* portIterator(const Cell* cell) const; + CellPortIterator* portIterator(const Cell* cell) const override; void readLefAfter(dbLib* lib); void readDefAfter(dbBlock* block); @@ -119,7 +119,7 @@ class dbNetwork : public ConcreteNetwork bool isPlaced(const Pin* pin) const; LibertyCell* libertyCell(dbInst* inst); - LibertyPort* libertyPort(const Pin*) const; + LibertyPort* libertyPort(const Pin*) const override; dbInst* staToDb(const Instance* instance) const; void staToDb(const Instance* instance, dbInst*& db_inst, @@ -229,7 +229,7 @@ class dbNetwork : public ConcreteNetwork //////////////////////////////////////////////////////////////// // Cell functions - const char* name(const Cell* instance) const override; + const char* name(const Cell* cell) const override; bool isConcreteCell(const Cell*) const; void registerConcreteCell(const Cell*); diff --git a/src/dbSta/src/dbNetwork.cc b/src/dbSta/src/dbNetwork.cc index 09b5b448b7..546c37e808 100644 --- a/src/dbSta/src/dbNetwork.cc +++ b/src/dbSta/src/dbNetwork.cc @@ -635,13 +635,13 @@ const char* dbNetwork::name(const Port* port) const dbBTerm* bterm = nullptr; staToDb(port, bterm, mterm, modbterm); if (bterm) { - return bterm->getName().c_str(); + return tmpStringCopy(bterm->getName().c_str()); } if (mterm) { - return mterm->getName().c_str(); + return tmpStringCopy(mterm->getName().c_str()); } if (modbterm) { - return modbterm->getName(); + return tmpStringCopy(modbterm->getName()); } } return nullptr; @@ -652,19 +652,18 @@ const char* dbNetwork::busName(const Port* port) const if (isConcretePort(port)) { const ConcretePort* cport = reinterpret_cast(port); return cport->busName(); - } else { - dbMTerm* mterm = nullptr; - dbModBTerm* modbterm = nullptr; - dbBTerm* bterm = nullptr; - staToDb(port, bterm, mterm, modbterm); - if (modbterm) { - if (modbterm->isBusPort()) { - return modbterm->getBusPort()->getName(); - } + } + dbMTerm* mterm = nullptr; + dbModBTerm* modbterm = nullptr; + dbBTerm* bterm = nullptr; + staToDb(port, bterm, mterm, modbterm); + if (modbterm) { + if (modbterm->isBusPort()) { + return modbterm->getBusPort()->getName(); } - logger_->error(ORD, 2020, "Error: database badly formed bus name"); - return nullptr; } + logger_->error(ORD, 2020, "Error: database badly formed bus name"); + return nullptr; } const char* dbNetwork::name(const Instance* instance) const @@ -704,7 +703,7 @@ class dbModulePortIterator : public CellPortIterator { public: explicit dbModulePortIterator(const dbModule* cell); - ~dbModulePortIterator(); + ~dbModulePortIterator() override; virtual bool hasNext(); virtual Port* next(); From 5fba3b615587b68ae7c5632cfa757e56eba9cea2 Mon Sep 17 00:00:00 2001 From: andyfox-rushc Date: Sun, 21 Jul 2024 20:03:18 -0700 Subject: [PATCH 09/37] Ctidy clean ups. Signed-off-by:Andy Fox andy@rushc.com Signed-off-by: andyfox-rushc --- src/dbSta/src/dbNetwork.cc | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/src/dbSta/src/dbNetwork.cc b/src/dbSta/src/dbNetwork.cc index 546c37e808..84a11fc3df 100644 --- a/src/dbSta/src/dbNetwork.cc +++ b/src/dbSta/src/dbNetwork.cc @@ -704,8 +704,8 @@ class dbModulePortIterator : public CellPortIterator public: explicit dbModulePortIterator(const dbModule* cell); ~dbModulePortIterator() override; - virtual bool hasNext(); - virtual Port* next(); + virtual bool hasNext() override; + virtual Port* next() override; private: const dbModBTerm* iter_; @@ -2462,7 +2462,7 @@ class DbNetworkPortMemberIterator : public PortMemberIterator { public: explicit DbNetworkPortMemberIterator(const Port* port, const dbNetwork* nwk); - ~DbNetworkPortMemberIterator(); + ~DbNetworkPortMemberIterator() = default; virtual bool hasNext(); virtual Port* next(); @@ -2497,10 +2497,6 @@ DbNetworkPortMemberIterator::DbNetworkPortMemberIterator(const Port* port, } } -DbNetworkPortMemberIterator::~DbNetworkPortMemberIterator() -{ -} - bool DbNetworkPortMemberIterator::hasNext() { ix_++; From e9d26897f86d765f6e40d0326e1b818673b1c70d Mon Sep 17 00:00:00 2001 From: andyfox-rushc Date: Sat, 27 Jul 2024 11:58:47 -0700 Subject: [PATCH 10/37] Removed dbVector for busses -- use order from allocation and then realloc on demand. Signed-off-by: Andy Fox Signed-off-by: andyfox-rushc --- src/dbSta/src/dbNetwork.cc | 27 +- src/dbSta/src/dbReadVerilog.cc | 30 +- src/odb/include/odb/db.h | 27 +- .../codeGenerator/schema/chip/dbBusPort.json | 47 ++-- .../codeGenerator/schema/chip/dbModBterm.json | 87 +++--- src/odb/src/db/dbBusPort.cpp | 256 +++++++++++------- src/odb/src/db/dbBusPort.h | 20 +- 7 files changed, 284 insertions(+), 210 deletions(-) diff --git a/src/dbSta/src/dbNetwork.cc b/src/dbSta/src/dbNetwork.cc index 84a11fc3df..c7210abc59 100644 --- a/src/dbSta/src/dbNetwork.cc +++ b/src/dbSta/src/dbNetwork.cc @@ -659,7 +659,9 @@ const char* dbNetwork::busName(const Port* port) const staToDb(port, bterm, mterm, modbterm); if (modbterm) { if (modbterm->isBusPort()) { - return modbterm->getBusPort()->getName(); + // modbterm has the name of the bus and refers + // to the BusPort which has the contents. + return modbterm->getName(); } } logger_->error(ORD, 2020, "Error: database badly formed bus name"); @@ -710,7 +712,6 @@ class dbModulePortIterator : public CellPortIterator private: const dbModBTerm* iter_; const dbModule* module_; - int ix; }; dbModulePortIterator::dbModulePortIterator(const dbModule* cell) @@ -721,7 +722,6 @@ dbModulePortIterator::dbModulePortIterator(const dbModule* cell) first_mod_bterm = iter_; } iter_ = first_mod_bterm; - ix = 0; module_ = cell; } @@ -739,15 +739,12 @@ bool dbModulePortIterator::hasNext() Port* dbModulePortIterator::next() { - ix++; dbModBTerm* modbterm = const_cast(iter_); Port* ret = reinterpret_cast(modbterm); - // advance to next, in case of bus port - // next modbterm is the one after the bus port if (modbterm->isBusPort()) { dbBusPort* bp = modbterm->getBusPort(); int size = bp->getSize(); - // skip into the content of the bus + // content of bus iter_ = iter_->getPrev(); for (int skip_ix = 0; skip_ix < size && (iter_->getPrev()); skip_ix++) { iter_ = iter_->getPrev(); @@ -2395,7 +2392,7 @@ int dbNetwork::fromIndex(const Port* port) const dbModBTerm* modbterm = nullptr; staToDb(port, bterm, mterm, modbterm); if (modbterm && modbterm->isBusPort()) { - return modbterm->getBusPort()->getStartIx(); + return modbterm->getBusPort()->getFrom(); } logger_->error(ORD, 2021, "Error: bad bus from_index defintion"); @@ -2412,8 +2409,8 @@ int dbNetwork::toIndex(const Port* port) const dbModBTerm* modbterm = nullptr; staToDb(port, bterm, mterm, modbterm); if (modbterm && modbterm->isBusPort()) { - int start_ix = modbterm->getBusPort()->getStartIx(); - if (modbterm->getBusPort()->isUpdown()) { + int start_ix = modbterm->getBusPort()->getFrom(); + if (modbterm->getBusPort()->getUpdown()) { return (start_ix + (modbterm->getBusPort()->getSize() - 1)); } return (start_ix - (modbterm->getBusPort()->getSize() - 1)); @@ -2446,14 +2443,14 @@ Port* dbNetwork::findMember(const Port* port, int index) const const ConcretePort* cport = reinterpret_cast(port); return reinterpret_cast(cport->findMember(index)); } - // get the indexed busport member. dbMTerm* mterm = nullptr; dbBTerm* bterm = nullptr; dbModBTerm* modbterm = nullptr; staToDb(port, bterm, mterm, modbterm); if (modbterm && modbterm->isBusPort()) { dbBusPort* busport = modbterm->getBusPort(); - return reinterpret_cast(busport->fetchIndexedPort(index)); + modbterm = modbterm->getPrev(); + modbterm = busport->getBusIndexedElement(index); } return nullptr; } @@ -2489,11 +2486,7 @@ DbNetworkPortMemberIterator::DbNetworkPortMemberIterator(const Port* port, if (modbterm && modbterm->isBusPort()) { dbBusPort* busport = modbterm->getBusPort(); size_ = busport->getSize(); - // advance iterator to this modbterm. - // note port iterator uses getModBTerms order. - // so member iterator does likewise. We traverse backwards - // through the list. - next_ = modbterm->getPrev(); + next_ = busport->getFirstMember(); } } diff --git a/src/dbSta/src/dbReadVerilog.cc b/src/dbSta/src/dbReadVerilog.cc index 1d8d460c43..9462e16d9a 100644 --- a/src/dbSta/src/dbReadVerilog.cc +++ b/src/dbSta/src/dbReadVerilog.cc @@ -364,37 +364,39 @@ void Verilog2db::makeDbModule( return; } if (hierarchy_) { - // make the module bterms + // make the module ports CellPortIterator* cp_iter = network_->portIterator(cell); while (cp_iter->hasNext()) { Port* port = cp_iter->next(); if (network_->isBus(port)) { - int from_index = network_->fromIndex(port); - int to_index = network_->toIndex(port); - bool up_down = to_index >= from_index ? true : false; - int size = up_down ? (to_index - from_index) + 1 - : (from_index - to_index) + 1; // make the bus port as part of the port set for the cell. - dbBusPort* dbbusport = dbBusPort::create(module, - network_->name(port), - network_->fromIndex(port), - up_down, - size); const char* port_name = network_->name(port); dbModBTerm* bmodterm = dbModBTerm::create(module, port_name); + dbBusPort* dbbusport + = dbBusPort::create(module, + bmodterm, // the root of the bus port + network_->fromIndex(port), + network_->toIndex(port)); bmodterm->setBusPort(dbbusport); dbIoType io_type = staToDb(network_->direction(port)); bmodterm->setIoType(io_type); // Make a modbterm for each bus bit // Keep traversal in terms of bits + int from_index = network_->fromIndex(port); + int to_index = network_->toIndex(port); + bool updown = (from_index <= to_index) ? true : false; + int size + = updown ? to_index - from_index + 1 : from_index - to_index + 1; for (int i = 0; i < size; i++) { - int ix = up_down ? from_index + i : from_index - i; - // use actual here + int ix = updown ? from_index + i : from_index - i; std::string bus_bit_port = port_name + std::string("[") + std::to_string(ix) + std::string("]"); - dbModBTerm* bmodterm + dbModBTerm* modbterm = dbModBTerm::create(module, bus_bit_port.c_str()); + if (i == 0) { + dbbusport->setFirstMember(modbterm); + } dbIoType io_type = staToDb(network_->direction(port)); bmodterm->setIoType(io_type); } diff --git a/src/odb/include/odb/db.h b/src/odb/include/odb/db.h index 59bdbf07fb..2e02ae4707 100644 --- a/src/odb/include/odb/db.h +++ b/src/odb/include/odb/db.h @@ -7139,25 +7139,32 @@ class dbAccessPoint : public dbObject class dbBusPort : public dbObject { public: - const char* getName() const; + int getFrom() const; - int getStartIx() const; + int getTo() const; - int getSize() const; + dbModBTerm* getPort() const; - bool isUpdown() const; + dbModBTerm* getMembers() const; dbModule* getParent() const; - dbModBTerm* getFirstmember() const; - // User Code Begin dbBusPort + // get element by bit index in bus (allows for up/down) + // linear access + dbModBTerm* getBusIndexedElement(int index) const; + + void setFirstMember(dbModBTerm*); + dbModBTerm* getFirstMember(); + int getSize() const; + bool getUpdown() const; + // reallocate the bus port so all members sequential. + void Realloc(); static dbBusPort* create(dbModule* parentModule, - const char* name, + dbModBTerm* root, int from_index, - bool updown, - int size); - dbModBTerm* fetchIndexedPort(int offset); + int to_index); + // User Code End dbBusPort }; diff --git a/src/odb/src/codeGenerator/schema/chip/dbBusPort.json b/src/odb/src/codeGenerator/schema/chip/dbBusPort.json index 3b3bab93f1..f0c11c83b3 100644 --- a/src/odb/src/codeGenerator/schema/chip/dbBusPort.json +++ b/src/odb/src/codeGenerator/schema/chip/dbBusPort.json @@ -3,51 +3,48 @@ "type":"dbObject", "fields":[ { - "name":"_name", - "type":"char *", - "flags":["no-set"], - "default":"nullptr", - "schema":"db_schema_odb_busport" + "name":"_flags", + "type":"uint", + "flags":["private"], + "default":"0", + "schema":"db_schema_update_hierarchy" }, { - "name": "_start_ix", + "name": "_from", "type": "int", "flags":["no-set"], "default":"0", - "schema":"db_schema_odb_busport" + "schema":"db_schema_odb_busport" }, { - "name":"_size", + "name":"_to", "type":"int", "flags":["no-set"], "default":"0", - "schema":"db_schema_odb_busport" + "schema":"db_schema_odb_busport" }, { - "name":"_updown", - "type":"bool", + "name":"_port", + "type":"dbId<_dbModBTerm>", "flags":["no-set"], - "default":"false", - "schema":"db_schema_odb_busport" + "schema":"db_schema_odb_busport", + "parent":"dbBlock" }, - { - "name":"_parent", - "type":"dbId<_dbModule>", + "name":"_members", + "type":"dbId<_dbModBTerm>", "flags":["no-set"], - "schema":"db_schema_odb_busport", - "parent":"dbBlock" + "schema":"db_schema_odb_busport", + "parent":"dbBlock" }, - { - "name":"_firstmember", - "type": "dbId<_dbModBTerm>", + "name":"_parent", + "type":"dbId<_dbModule>", "flags":["no-set"], - "default":"0", - "schema":"db_schema_odb_busport", - "parent":"dbBlock" + "schema":"db_schema_odb_busport", + "parent":"dbBlock" } ], "constructors":[], - "cpp_includes":["dbBlock.h","dbModBTerm.h","dbModule.h","dbModNet.h","dbHashTable.hpp","dbModITerm.h","dbBusPort.h"] + "cpp_includes":[ "dbVector.h","dbBlock.h","dbModBTerm.h","dbModule.h","dbModNet.h","dbHashTable.hpp","dbModITerm.h","dbBusPort.h"] } diff --git a/src/odb/src/codeGenerator/schema/chip/dbModBterm.json b/src/odb/src/codeGenerator/schema/chip/dbModBterm.json index 85b94614fb..ec040a9ed9 100644 --- a/src/odb/src/codeGenerator/schema/chip/dbModBterm.json +++ b/src/odb/src/codeGenerator/schema/chip/dbModBterm.json @@ -7,14 +7,14 @@ "type":"char *", "flags":["no-set"], "default":"nullptr", - "schema":"db_schema_update_hierarchy" + "schema":"db_schema_update_hierarchy" }, - { - "name":"_flags", - "type":"uint", - "flags":["private"], + { + "name":"_flags", + "type":"uint", + "flags":["private"], "default":"0", - "schema":"db_schema_update_hierarchy" + "schema":"db_schema_update_hierarchy" }, { "name":"_parent_moditerm", @@ -24,55 +24,54 @@ "schema":"db_schema_update_hierarchy" }, { - "name":"_parent", - "type":"dbId<_dbModule>", - "flags":["no-set"], - "schema":"db_schema_update_hierarchy", - "parent":"dbBlock" + "name":"_parent", + "type":"dbId<_dbModule>", + "flags":["no-set"], + "schema":"db_schema_update_hierarchy", + "parent":"dbBlock" }, { - "name":"_modnet", - "type":"dbId<_dbModNet>", - "flags":["private"], - "schema":"db_schema_update_hierarchy", - "parent":"dbBlock" + "name":"_modnet", + "type":"dbId<_dbModNet>", + "flags":["private"], + "schema":"db_schema_update_hierarchy", + "parent":"dbBlock" }, { - "name":"_next_net_modbterm", - "type":"dbId<_dbModBTerm>", - "flags":["private"], - "schema":"db_schema_update_hierarchy", - "parent":"dbBlock" + "name":"_next_net_modbterm", + "type":"dbId<_dbModBTerm>", + "flags":["private"], + "schema":"db_schema_update_hierarchy", + "parent":"dbBlock" }, { - "name":"_prev_net_modbterm", - "type":"dbId<_dbModBTerm>", - "flags":["private"], - "schema":"db_schema_update_hierarchy", - "parent":"dbBlock" + "name":"_prev_net_modbterm", + "type":"dbId<_dbModBTerm>", + "flags":["private"], + "schema":"db_schema_update_hierarchy", + "parent":"dbBlock" }, { - "name":"_busPort", - "type":"dbId<_dbBusPort>", - "flags":["private"], - "schema":"db_schema_odb_busport", - "parent":"dbBlock" + "name":"_busPort", + "type":"dbId<_dbBusPort>", + "flags":["private"], + "schema":"db_schema_odb_busport", + "parent":"dbBlock" }, - - { - "name":"_next_entry", - "type":"dbId<_dbModBTerm>", - "flags":["private"], - "schema":"db_schema_update_hierarchy", + { + "name":"_next_entry", + "type":"dbId<_dbModBTerm>", + "flags":["private"], + "schema":"db_schema_update_hierarchy", "parent":"dbBlock" - }, - { - "name":"_prev_entry", - "type":"dbId<_dbModBTerm>", - "flags":["private"], - "schema":"db_schema_odb_busport", + }, + { + "name":"_prev_entry", + "type":"dbId<_dbModBTerm>", + "flags":["private"], + "schema":"db_schema_odb_busport", "parent":"dbBlock" - } + } ], "constructors":[], "cpp_includes":["dbBlock.h","dbModule.h","dbModNet.h","dbHashTable.hpp","dbModITerm.h","dbBusPort.h"] diff --git a/src/odb/src/db/dbBusPort.cpp b/src/odb/src/db/dbBusPort.cpp index 665478de5e..28c568d472 100644 --- a/src/odb/src/db/dbBusPort.cpp +++ b/src/odb/src/db/dbBusPort.cpp @@ -44,28 +44,29 @@ #include "dbModule.h" #include "dbTable.h" #include "dbTable.hpp" +#include "dbVector.h" #include "odb/db.h" namespace odb { template class dbTable<_dbBusPort>; bool _dbBusPort::operator==(const _dbBusPort& rhs) const { - if (_name != rhs._name) { + if (_flags != rhs._flags) { return false; } - if (_start_ix != rhs._start_ix) { + if (_from != rhs._from) { return false; } - if (_size != rhs._size) { + if (_to != rhs._to) { return false; } - if (_updown != rhs._updown) { + if (_port != rhs._port) { return false; } - if (_parent != rhs._parent) { + if (_members != rhs._members) { return false; } - if (_firstmember != rhs._firstmember) { + if (_parent != rhs._parent) { return false; } @@ -82,128 +83,127 @@ void _dbBusPort::differences(dbDiff& diff, const _dbBusPort& rhs) const { DIFF_BEGIN - DIFF_FIELD(_name); - DIFF_FIELD(_start_ix); - DIFF_FIELD(_size); - DIFF_FIELD(_updown); + DIFF_FIELD(_flags); + DIFF_FIELD(_from); + DIFF_FIELD(_to); + DIFF_FIELD(_port); + DIFF_FIELD(_members); DIFF_FIELD(_parent); - DIFF_FIELD(_firstmember); DIFF_END } void _dbBusPort::out(dbDiff& diff, char side, const char* field) const { DIFF_OUT_BEGIN - DIFF_OUT_FIELD(_name); - DIFF_OUT_FIELD(_start_ix); - DIFF_OUT_FIELD(_size); - DIFF_OUT_FIELD(_updown); + DIFF_OUT_FIELD(_flags); + DIFF_OUT_FIELD(_from); + DIFF_OUT_FIELD(_to); + DIFF_OUT_FIELD(_port); + DIFF_OUT_FIELD(_members); DIFF_OUT_FIELD(_parent); - DIFF_OUT_FIELD(_firstmember); DIFF_END } _dbBusPort::_dbBusPort(_dbDatabase* db) { - _name = nullptr; - _start_ix = 0; - _size = 0; - _updown = false; - _firstmember = 0; + _flags = 0; + _from = 0; + _to = 0; } _dbBusPort::_dbBusPort(_dbDatabase* db, const _dbBusPort& r) { - _name = r._name; - _start_ix = r._start_ix; - _size = r._size; - _updown = r._updown; + _flags = r._flags; + _from = r._from; + _to = r._to; + _port = r._port; + _members = r._members; _parent = r._parent; - _firstmember = r._firstmember; } dbIStream& operator>>(dbIStream& stream, _dbBusPort& obj) { - if (obj.getDatabase()->isSchema(db_schema_odb_busport)) { - stream >> obj._name; + if (obj.getDatabase()->isSchema(db_schema_update_hierarchy)) { + stream >> obj._flags; } if (obj.getDatabase()->isSchema(db_schema_odb_busport)) { - stream >> obj._start_ix; + stream >> obj._from; } if (obj.getDatabase()->isSchema(db_schema_odb_busport)) { - stream >> obj._size; + stream >> obj._to; } if (obj.getDatabase()->isSchema(db_schema_odb_busport)) { - stream >> obj._updown; + stream >> obj._port; } if (obj.getDatabase()->isSchema(db_schema_odb_busport)) { - stream >> obj._parent; + stream >> obj._members; } if (obj.getDatabase()->isSchema(db_schema_odb_busport)) { - stream >> obj._firstmember; + stream >> obj._parent; } return stream; } dbOStream& operator<<(dbOStream& stream, const _dbBusPort& obj) { - if (obj.getDatabase()->isSchema(db_schema_odb_busport)) { - stream << obj._name; + if (obj.getDatabase()->isSchema(db_schema_update_hierarchy)) { + stream << obj._flags; } if (obj.getDatabase()->isSchema(db_schema_odb_busport)) { - stream << obj._start_ix; + stream << obj._from; } if (obj.getDatabase()->isSchema(db_schema_odb_busport)) { - stream << obj._size; + stream << obj._to; } if (obj.getDatabase()->isSchema(db_schema_odb_busport)) { - stream << obj._updown; + stream << obj._port; } if (obj.getDatabase()->isSchema(db_schema_odb_busport)) { - stream << obj._parent; + stream << obj._members; } if (obj.getDatabase()->isSchema(db_schema_odb_busport)) { - stream << obj._firstmember; + stream << obj._parent; } return stream; } -_dbBusPort::~_dbBusPort() -{ - if (_name) { - free((void*) _name); - } -} - //////////////////////////////////////////////////////////////////// // // dbBusPort - Methods // //////////////////////////////////////////////////////////////////// -const char* dbBusPort::getName() const +int dbBusPort::getFrom() const { _dbBusPort* obj = (_dbBusPort*) this; - return obj->_name; + return obj->_from; } -int dbBusPort::getStartIx() const +int dbBusPort::getTo() const { _dbBusPort* obj = (_dbBusPort*) this; - return obj->_start_ix; + return obj->_to; } -int dbBusPort::getSize() const +dbModBTerm* dbBusPort::getPort() const { _dbBusPort* obj = (_dbBusPort*) this; - return obj->_size; + if (obj->_port == 0) { + return nullptr; + } + _dbBlock* par = (_dbBlock*) obj->getOwner(); + return (dbModBTerm*) par->_modbterm_tbl->getPtr(obj->_port); } -bool dbBusPort::isUpdown() const +dbModBTerm* dbBusPort::getMembers() const { _dbBusPort* obj = (_dbBusPort*) this; - return obj->_updown; + if (obj->_members == 0) { + return nullptr; + } + _dbBlock* par = (_dbBlock*) obj->getOwner(); + return (dbModBTerm*) par->_modbterm_tbl->getPtr(obj->_members); } dbModule* dbBusPort::getParent() const @@ -216,62 +216,134 @@ dbModule* dbBusPort::getParent() const return (dbModule*) par->_module_tbl->getPtr(obj->_parent); } -dbModBTerm* dbBusPort::getFirstmember() const +// User Code Begin dbBusPortPublicMethods + +/* + Get the indexed element. eg b[2] gets the element in the sequence + at index 2. Note that depending on the from/to the offset + of this index will change. eg + b[1:5] + element is at offset 1 in the array + b[5:1] element is at offset 4 in the array + */ +dbModBTerm* dbBusPort::getBusIndexedElement(int index) const { _dbBusPort* obj = (_dbBusPort*) this; - if (obj->_firstmember == 0) { - return nullptr; + _dbBlock* block_ = (_dbBlock*) obj->getOwner(); + int offset; + if (getUpdown()) { + offset = index - getFrom(); + } else { + offset = getFrom() - index; } - _dbBlock* par = (_dbBlock*) obj->getOwner(); - return (dbModBTerm*) par->_modbterm_tbl->getPtr(obj->_firstmember); + if (offset < getSize()) { + // the _flags are set to non zero if we cannot + // count on the order of the modbterms (eg + // if some have been deleted or added in non-linear way). + // + if (obj->_flags == 0U) { + return (dbModBTerm*) (block_->_modbterm_tbl->getPtr(obj->getId() + offset + + 1)); + } + // if we cannot count on the order, skip to the dbModBterm + dbModBTerm* cur = (dbModBTerm*) (block_->_modbterm_tbl->getPtr(obj->_port)); + if (cur != nullptr) { + cur = cur->getPrev(); + for (int i = 0; i < offset; i++) { + cur = cur->getPrev(); + } + return cur; + } + } + + return nullptr; +} + +void dbBusPort::setFirstMember(dbModBTerm* modbterm) +{ + if (modbterm) { + _dbBusPort* obj = (_dbBusPort*) this; + _dbModBTerm* mbt = (_dbModBTerm*) modbterm; + obj->_members = mbt->getId(); + } +} + +dbModBTerm* dbBusPort::getFirstMember() +{ + _dbBusPort* obj = (_dbBusPort*) this; + _dbBlock* block = (_dbBlock*) obj->getOwner(); + if (obj->_members != 0) { + dbModBTerm* ret + = (dbModBTerm*) (block->_modbterm_tbl->getPtr(obj->_members)); + return ret; + } + return nullptr; +} + +int dbBusPort::getSize() const +{ + _dbBusPort* obj = (_dbBusPort*) this; + if (getUpdown()) { + return (obj->_to - obj->_from + 1); + } + return (obj->_from - obj->_to + 1); +} + +bool dbBusPort::getUpdown() const +{ + _dbBusPort* obj = (_dbBusPort*) this; + if (obj->_to >= obj->_from) { + return true; + } + return false; } -// User Code Begin dbBusPortPublicMethods dbBusPort* dbBusPort::create(dbModule* parentModule, - const char* name, - int from_index, - bool updown, - int size) + dbModBTerm* port, + int from_ix, + int to_ix) { _dbModule* module = (_dbModule*) parentModule; _dbBlock* block = (_dbBlock*) module->getOwner(); - std::string str_name(name); _dbBusPort* busport = block->_busport_tbl->create(); - busport->_start_ix = from_index; - busport->_size = size; - busport->_updown = updown; - busport->_firstmember = 0; - busport->_name = strdup(name); + busport->_port = port->getId(); + busport->_from = from_ix; + busport->_to = to_ix; + busport->_flags = 0U; busport->_parent = module->getOID(); - ZALLOCATED(busport->_name); return (dbBusPort*) busport; } -// note on connectivity model -// we assume a fully connected model at the bit level -// so a bus port is a partition on the bit level model. -// eg -// for ports: {a,bus[3:0],j} -// then the fully connected model is a,bus[3],bus[2],bus[1],bus[0],j -// and to get the index element 1 from busPort we use bus[3]+1 = bus[2]. // - -dbModBTerm* dbBusPort::fetchIndexedPort(int offset) +// Reallocate the bus to preserve sequential db ordering +// +// +void dbBusPort::Realloc() { + /* _dbBusPort* obj = (_dbBusPort*) this; - _dbBlock* block_ = (_dbBlock*) obj->getOwner(); - if (obj->_firstmember == 0 || offset >= obj->_size) - return nullptr; - else { - int id = obj->_firstmember; - _dbModBTerm* element = block_->_modbterm_tbl->getPtr(id); - for (int posn = 0; (element != nullptr) && (posn != offset); posn++) { - id = element->_next_entry; - element = block_->_modbterm_tbl->getPtr(id); + _dbBlock* block = (_dbBlock*) obj->getOwner(); + dbModule* parentModule (_dbModule*) obj -> getParent(); + if (obj -> _flags !=0U){ + dbModBTerm* busport = block -> modbterm_tbl -> getPtr(obj -> _port); + dbModBTerm* cur = busport -> getPrev(); + // + //sequentially reallocate the elements + //to assure they are layed out for sequential access + //after being tampered with. + // + int size = obj -> getSize(); + for (int i =0; i < size; i++){ + dbModBTerm* new_cur = dbModBTerm::create(parentModule,cur -> getName()); + new_cur -> _modnet = cur -> _modnet; + new_cur -> _next_net_modbterm = cur -> _modbterm; + new_cur -> _prev_net_modbterm = cur -> _modbterm; + new_cur -> _busPort = cur -> _busPort; + new_cur -> _name = cur -> _name; + new_cur -> _parent = cur -> _parent; } - return (dbModBTerm*) element; } - return nullptr; + */ } // User Code End dbBusPortPublicMethods diff --git a/src/odb/src/db/dbBusPort.h b/src/odb/src/db/dbBusPort.h index df2214103b..a001bbf78c 100644 --- a/src/odb/src/db/dbBusPort.h +++ b/src/odb/src/db/dbBusPort.h @@ -36,13 +36,17 @@ #include "dbCore.h" #include "odb/odb.h" +// User Code Begin Includes +#include "dbVector.h" +// User Code End Includes + namespace odb { class dbIStream; class dbOStream; class dbDiff; class _dbDatabase; -class _dbModule; class _dbModBTerm; +class _dbModule; class _dbBusPort : public _dbObject { @@ -50,7 +54,7 @@ class _dbBusPort : public _dbObject _dbBusPort(_dbDatabase*, const _dbBusPort& r); _dbBusPort(_dbDatabase*); - ~_dbBusPort(); + ~_dbBusPort() = default; bool operator==(const _dbBusPort& rhs) const; bool operator!=(const _dbBusPort& rhs) const { return !operator==(rhs); } @@ -60,14 +64,14 @@ class _dbBusPort : public _dbObject const _dbBusPort& rhs) const; void out(dbDiff& diff, char side, const char* field) const; - char* _name; - int _start_ix; - int _size; - bool _updown; + uint _flags; + int _from; + int _to; + dbId<_dbModBTerm> _port; + dbId<_dbModBTerm> _members; dbId<_dbModule> _parent; - dbId<_dbModBTerm> _firstmember; }; dbIStream& operator>>(dbIStream& stream, _dbBusPort& obj); dbOStream& operator<<(dbOStream& stream, const _dbBusPort& obj); } // namespace odb - // Generator Code End Header \ No newline at end of file + // Generator Code End Header From 0732c9c1b3d89e301f0af4ff5af8f911d52d2737 Mon Sep 17 00:00:00 2001 From: andyfox-rushc Date: Mon, 29 Jul 2024 09:47:16 -0700 Subject: [PATCH 11/37] added todo comment for realloc. Signed-off-by: Andy Fox Signed-off-by: andyfox-rushc --- src/odb/src/db/dbBusPort.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/odb/src/db/dbBusPort.cpp b/src/odb/src/db/dbBusPort.cpp index 28c568d472..022c054413 100644 --- a/src/odb/src/db/dbBusPort.cpp +++ b/src/odb/src/db/dbBusPort.cpp @@ -315,8 +315,8 @@ dbBusPort* dbBusPort::create(dbModule* parentModule, } // -// Reallocate the bus to preserve sequential db ordering -// +// TODO: Reallocate the bus to preserve sequential db ordering +// This to be added as part of "scaffolding functions" // void dbBusPort::Realloc() { From 8603412cca789a9011acaf519a553896b1ade1a9 Mon Sep 17 00:00:00 2001 From: osamahammad21 Date: Wed, 31 Jul 2024 01:36:55 +0000 Subject: [PATCH 12/37] drt: fix ndr support Signed-off-by: osamahammad21 --- src/drt/src/dr/FlexDR.h | 28 +- src/drt/src/dr/FlexDR_graphics.cpp | 4 +- src/drt/src/dr/FlexDR_init.cpp | 6 + src/drt/src/dr/FlexDR_maze.cpp | 233 +++++++++---- src/drt/src/dr/FlexGridGraph.h | 225 +++++++++---- src/drt/src/dr/FlexGridGraph_maze.cpp | 199 +----------- src/drt/src/io/io.cpp | 7 +- src/drt/test/ndr_vias1.defok | 313 ++++++++---------- src/drt/test/ndr_vias2.defok | 450 ++++++++++++-------------- 9 files changed, 739 insertions(+), 726 deletions(-) diff --git a/src/drt/src/dr/FlexDR.h b/src/drt/src/dr/FlexDR.h index 88ff37495b..54914b4d77 100644 --- a/src/drt/src/dr/FlexDR.h +++ b/src/drt/src/dr/FlexDR.h @@ -484,6 +484,7 @@ class FlexDRWorker std::vector markers_; std::vector bestMarkers_; FlexDRWorkerRegionQuery rq_; + std::vector ndrs_; // persistent gc worker std::unique_ptr gcWorker_; @@ -768,6 +769,16 @@ class FlexDRWorker bool isMacroPin = false, bool resetHorz = true, bool resetVert = true); + void modMinSpacingCostPlanarHelper(const Rect& box, + frMIdx z, + ModCostType type, + frCoord width, + frCoord minSpacing, + bool isBlockage, + bool isMacroPin, + bool resetHorz, + bool resetVert, + bool ndr); void modCornerToCornerSpacing(const Rect& box, frMIdx z, ModCostType type); void modMinSpacingCostVia(const Rect& box, frMIdx z, @@ -776,6 +787,17 @@ class FlexDRWorker bool isCurrPs, bool isBlockage = false, frNonDefaultRule* ndr = nullptr); + void modMinSpacingCostViaHelper(const Rect& box, + frMIdx z, + ModCostType type, + frCoord width, + frCoord minSpacing, + frViaDef* viaDef, + drEolSpacingConstraint drCon, + bool isUpperVia, + bool isCurrPs, + bool isBlockage, + bool ndr); void modCornerToCornerSpacing_helper(const Rect& box, frMIdx z, @@ -788,14 +810,16 @@ class FlexDRWorker const drEolSpacingConstraint& drCon, frMIdx i, frMIdx j, - frMIdx z); + frMIdx z, + bool ndr = false); void modMinSpacingCostVia_eol_helper(const Rect& box, const Rect& testBox, ModCostType type, bool isUpperVia, frMIdx i, frMIdx j, - frMIdx z); + frMIdx z, + bool ndr = false); // eolSpc void modEolSpacingCost_helper(const Rect& testbox, frMIdx z, diff --git a/src/drt/src/dr/FlexDR_graphics.cpp b/src/drt/src/dr/FlexDR_graphics.cpp index 0236baa00d..053fa43359 100644 --- a/src/drt/src/dr/FlexDR_graphics.cpp +++ b/src/drt/src/dr/FlexDR_graphics.cpp @@ -183,7 +183,9 @@ gui::Descriptor::Properties GridGraphDescriptor::getProperties( costs.push_back( {name + " edge length", graph->getEdgeLength(x, y, z, dir)}); costs.push_back( - {name + " total cost", graph->getCosts(x, y, z, dir, layer)}); + {name + " total cost", + graph->getCosts( + x, y, z, dir, layer, data.graph->getNDR() != nullptr)}); } props.insert(props.end(), costs.begin(), costs.end()); return props; diff --git a/src/drt/src/dr/FlexDR_init.cpp b/src/drt/src/dr/FlexDR_init.cpp index e3862e2a84..151e94eb54 100644 --- a/src/drt/src/dr/FlexDR_init.cpp +++ b/src/drt/src/dr/FlexDR_init.cpp @@ -2034,6 +2034,12 @@ void FlexDRWorker::initNets(const frDesign* design) if (ENABLE_BOUNDARY_MAR_FIX) { initNets_boundaryArea(); } + // fill ndrs_ for all nets in the worker + for (auto& net : nets) { + if (net->hasNDR()) { + ndrs_.push_back(net->getNondefaultRule()); + } + } } void FlexDRWorker::initTrackCoords_route( diff --git a/src/drt/src/dr/FlexDR_maze.cpp b/src/drt/src/dr/FlexDR_maze.cpp index 69610fc25a..298e11e196 100644 --- a/src/drt/src/dr/FlexDR_maze.cpp +++ b/src/drt/src/dr/FlexDR_maze.cpp @@ -280,21 +280,69 @@ void FlexDRWorker::modMinSpacingCostPlanar(const Rect& box, bool isMacroPin, bool resetHorz, bool resetVert) +{ + // calculate costs for non-NDR nets + frCoord default_width + = getTech()->getLayer(gridGraph_.getLayerNum(z))->getWidth(); + frCoord default_spacing = 0; + if (ndr) { + default_spacing = ndr->getSpacing(z); + } + modMinSpacingCostPlanarHelper(box, + z, + type, + default_width, + default_spacing, + isBlockage, + isMacroPin, + resetHorz, + resetVert, + false); + // caclulate costs for NDR nets + // get all unique width,spacing pairs from ndrs + for (auto ndr : ndrs_) { + frCoord ndr_width; + frCoord ndr_min_spc; + if (ndr->getWidth(z) != 0) { + ndr_width = ndr->getWidth(z); + } else { + ndr_width = default_width; + } + ndr_min_spc = std::max(default_spacing, ndr->getSpacing(z)); + modMinSpacingCostPlanarHelper(box, + z, + type, + ndr_width, + ndr_min_spc, + isBlockage, + isMacroPin, + resetHorz, + resetVert, + true); + } +} + +void FlexDRWorker::modMinSpacingCostPlanarHelper(const Rect& box, + frMIdx z, + ModCostType type, + frCoord width, + frCoord minSpacing, + bool isBlockage, + bool isMacroPin, + bool resetHorz, + bool resetVert, + bool ndr) { auto lNum = gridGraph_.getLayerNum(z); frCoord width1 = box.minDXDY(); - frCoord length1 = box.maxDXDY(); // layer default width - frCoord width2 = getTech()->getLayer(lNum)->getWidth(); + frCoord width2 = width; frCoord halfwidth2 = width2 / 2; // spacing value needed bool use_min_spacing = isBlockage && USEMINSPACING_OBS; frCoord bloatDist = getTech()->getLayer(lNum)->getMinSpacingValue( - width1, width2, length1, use_min_spacing); - - if (ndr) { - bloatDist = std::max(bloatDist, ndr->getSpacing(z)); - } + width1, width2, box.maxDXDY(), use_min_spacing); + bloatDist = std::max(bloatDist, minSpacing); frSquaredDistance bloatDistSquare = bloatDist; bloatDistSquare *= bloatDist; @@ -329,32 +377,37 @@ void FlexDRWorker::modMinSpacingCostPlanar(const Rect& box, if (distSquare < bloatDistSquare) { switch (type) { case subRouteShape: - gridGraph_.subRouteShapeCostPlanar(i, j, z); // safe access + gridGraph_.subRouteShapeCostPlanar(i, j, z, ndr); // safe access break; case addRouteShape: - gridGraph_.addRouteShapeCostPlanar(i, j, z); // safe access + gridGraph_.addRouteShapeCostPlanar(i, j, z, ndr); // safe access break; case subFixedShape: - gridGraph_.subFixedShapeCostPlanar(i, j, z); // safe access + gridGraph_.subFixedShapeCostPlanar(i, j, z, ndr); // safe access break; case addFixedShape: - gridGraph_.addFixedShapeCostPlanar(i, j, z); // safe access + gridGraph_.addFixedShapeCostPlanar(i, j, z, ndr); // safe access break; case resetFixedShape: if (resetHorz) { gridGraph_.setFixedShapeCostPlanarHorz( - i, j, z, 0); // safe access + i, j, z, 0, ndr); // safe access } if (resetVert) { gridGraph_.setFixedShapeCostPlanarVert( - i, j, z, 0); // safe access + i, j, z, 0, ndr); // safe access } break; case setFixedShape: - gridGraph_.setFixedShapeCostPlanarHorz(i, j, z, 1); // safe access - gridGraph_.setFixedShapeCostPlanarVert(i, j, z, 1); // safe access + gridGraph_.setFixedShapeCostPlanarHorz( + i, j, z, 1, ndr); // safe access + gridGraph_.setFixedShapeCostPlanarVert( + i, j, z, 1, ndr); // safe access break; case resetBlocked: + if (ndr) { + return; + } if (isMacroPin) { if (j >= mPinLL.y() && j <= mPinUR.y()) { gridGraph_.resetBlocked(i, j, z, frDirEnum::E); @@ -380,6 +433,9 @@ void FlexDRWorker::modMinSpacingCostPlanar(const Rect& box, } break; case setBlocked: // set blocked + if (ndr) { + return; + } gridGraph_.setBlocked(i, j, z, frDirEnum::E); gridGraph_.setBlocked(i, j, z, frDirEnum::N); if (i == 0) { @@ -402,22 +458,23 @@ void FlexDRWorker::modMinSpacingCostVia_eol_helper(const Rect& box, bool isUpperVia, frMIdx i, frMIdx j, - frMIdx z) + frMIdx z, + bool ndr) { frMIdx zIdx = isUpperVia ? z : z - 1; if (testBox.overlaps(box)) { switch (type) { case subRouteShape: - gridGraph_.subRouteShapeCostVia(i, j, zIdx); + gridGraph_.subRouteShapeCostVia(i, j, zIdx, ndr); break; case addRouteShape: - gridGraph_.addRouteShapeCostVia(i, j, zIdx); + gridGraph_.addRouteShapeCostVia(i, j, zIdx, ndr); break; case subFixedShape: - gridGraph_.subFixedShapeCostVia(i, j, zIdx); // safe access + gridGraph_.subFixedShapeCostVia(i, j, zIdx, ndr); // safe access break; case addFixedShape: - gridGraph_.addFixedShapeCostVia(i, j, zIdx); // safe access + gridGraph_.addFixedShapeCostVia(i, j, zIdx, ndr); // safe access break; default:; } @@ -431,7 +488,8 @@ void FlexDRWorker::modMinSpacingCostVia_eol(const Rect& box, const drEolSpacingConstraint& drCon, frMIdx i, frMIdx j, - frMIdx z) + frMIdx z, + bool ndr) { if (drCon.eolSpace == 0) { return; @@ -446,13 +504,15 @@ void FlexDRWorker::modMinSpacingCostVia_eol(const Rect& box, tmpBx.yMax(), tmpBx.xMax() + eolWithin, tmpBx.yMax() + eolSpace); - modMinSpacingCostVia_eol_helper(box, testBox, type, isUpperVia, i, j, z); + modMinSpacingCostVia_eol_helper( + box, testBox, type, isUpperVia, i, j, z, ndr); testBox.init(tmpBx.xMin() - eolWithin, tmpBx.yMin() - eolSpace, tmpBx.xMax() + eolWithin, tmpBx.yMin()); - modMinSpacingCostVia_eol_helper(box, testBox, type, isUpperVia, i, j, z); + modMinSpacingCostVia_eol_helper( + box, testBox, type, isUpperVia, i, j, z, ndr); } // eol to left and right if (tmpBx.dy() <= eolWidth) { @@ -460,13 +520,15 @@ void FlexDRWorker::modMinSpacingCostVia_eol(const Rect& box, tmpBx.yMin() - eolWithin, tmpBx.xMax() + eolSpace, tmpBx.yMax() + eolWithin); - modMinSpacingCostVia_eol_helper(box, testBox, type, isUpperVia, i, j, z); + modMinSpacingCostVia_eol_helper( + box, testBox, type, isUpperVia, i, j, z, ndr); testBox.init(tmpBx.xMin() - eolSpace, tmpBx.yMin() - eolWithin, tmpBx.xMin(), tmpBx.yMax() + eolWithin); - modMinSpacingCostVia_eol_helper(box, testBox, type, isUpperVia, i, j, z); + modMinSpacingCostVia_eol_helper( + box, testBox, type, isUpperVia, i, j, z, ndr); } } @@ -481,11 +543,11 @@ void FlexDRWorker::modMinimumcutCostVia(const Rect& box, // default via dimension frViaDef* viaDef = nullptr; if (isUpperVia) { - viaDef = (lNum < getTech()->getTopLayerNum()) + viaDef = (lNum < gridGraph_.getMaxLayerNum()) ? getTech()->getLayer(lNum + 1)->getDefaultViaDef() : nullptr; } else { - viaDef = (lNum > getTech()->getBottomLayerNum()) + viaDef = (lNum > gridGraph_.getMinLayerNum()) ? getTech()->getLayer(lNum - 1)->getDefaultViaDef() : nullptr; } @@ -608,20 +670,79 @@ void FlexDRWorker::modMinSpacingCostVia(const Rect& box, bool isBlockage, frNonDefaultRule* ndr) { + // mod costs for non-NDR nets auto lNum = gridGraph_.getLayerNum(z); - frCoord width1 = box.minDXDY(); - frCoord length1 = box.maxDXDY(); - // default via dimension - frViaDef* viaDef = nullptr; + frViaDef* defaultViaDef = nullptr; if (isUpperVia) { - viaDef = (lNum < getTech()->getTopLayerNum()) - ? getTech()->getLayer(lNum + 1)->getDefaultViaDef() - : nullptr; + defaultViaDef = (lNum < gridGraph_.getMaxLayerNum()) + ? getTech()->getLayer(lNum + 1)->getDefaultViaDef() + : nullptr; } else { - viaDef = (lNum > getTech()->getBottomLayerNum()) - ? getTech()->getLayer(lNum - 1)->getDefaultViaDef() - : nullptr; + defaultViaDef = (lNum > gridGraph_.getMinLayerNum()) + ? getTech()->getLayer(lNum - 1)->getDefaultViaDef() + : nullptr; } + frCoord defaultMinSpacing = 0; + drEolSpacingConstraint drCon; + if (ndr) { + defaultMinSpacing = ndr->getSpacing(z); + drCon = ndr->getDrEolSpacingConstraint(z); + } + frCoord defaultWidth = getTech()->getLayer(lNum)->getWidth(); + modMinSpacingCostViaHelper(box, + z, + type, + defaultWidth, + defaultMinSpacing, + defaultViaDef, + drCon, + isUpperVia, + isCurrPs, + isBlockage, + false); + // mod costs for ndrs + for (auto ndr : ndrs_) { + frCoord width = defaultWidth; + frViaDef* viadef = defaultViaDef; + frCoord minSpacing = defaultMinSpacing; + drEolSpacingConstraint ndrDrCon = ndr->getDrEolSpacingConstraint(z); + if (isUpperVia && lNum < gridGraph_.getMaxLayerNum() + && ndr->getPrefVia(z) != nullptr) { + viadef = ndr->getPrefVia(z); + } else if (!isUpperVia && lNum > gridGraph_.getMinLayerNum() + && ndr->getPrefVia(z - 1) != nullptr) { + viadef = ndr->getPrefVia(z - 1); + } + if (ndr->getWidth(z) != 0) { + width = ndr->getWidth(z); + } + minSpacing = std::max(minSpacing, ndr->getSpacing(z)); + modMinSpacingCostViaHelper(box, + z, + type, + width, + minSpacing, + viadef, + ndrDrCon, + isUpperVia, + isCurrPs, + isBlockage, + true); + } +} + +void FlexDRWorker::modMinSpacingCostViaHelper(const Rect& box, + frMIdx z, + ModCostType type, + frCoord width, + frCoord minSpacing, + frViaDef* viaDef, + drEolSpacingConstraint drCon, + bool isUpperVia, + bool isCurrPs, + bool isBlockage, + bool ndr) +{ if (viaDef == nullptr) { return; } @@ -636,36 +757,30 @@ void FlexDRWorker::modMinSpacingCostVia(const Rect& box, frCoord length2 = viaBox.maxDXDY(); // via prl should check min area patch metal if not fat via - frCoord defaultWidth = getTech()->getLayer(lNum)->getWidth(); + auto lNum = gridGraph_.getLayerNum(z); bool isH = (getTech()->getLayer(lNum)->getDir() == dbTechLayerDir::HORIZONTAL); - bool isFatVia - = (isH) ? (viaBox.dy() > defaultWidth) : (viaBox.dx() > defaultWidth); + bool isFatVia = (isH) ? (viaBox.dy() > width) : (viaBox.dx() > width); frCoord length2_mar = length2; frCoord patchLength = 0; if (!isFatVia) { auto minAreaConstraint = getTech()->getLayer(lNum)->getAreaConstraint(); auto minArea = minAreaConstraint ? minAreaConstraint->getMinArea() : 0; - patchLength = frCoord(ceil(1.0 * minArea / defaultWidth + patchLength = frCoord(ceil(1.0 * minArea / width / getTech()->getManufacturingGrid())) * frCoord(getTech()->getManufacturingGrid()); length2_mar = std::max(length2_mar, patchLength); } // spacing value needed + frCoord width1 = box.minDXDY(); + frCoord length1 = box.maxDXDY(); frCoord prl = isCurrPs ? (length2_mar) : std::min(length1, length2_mar); bool use_min_spacing = isBlockage && USEMINSPACING_OBS && !isFatVia; frCoord bloatDist = getTech()->getLayer(lNum)->getMinSpacingValue( width1, width2, prl, use_min_spacing); - - drEolSpacingConstraint drCon; - if (ndr) { - bloatDist = std::max(bloatDist, ndr->getSpacing(z)); - drCon = ndr->getDrEolSpacingConstraint(z); - } - // other obj eol spc to curr obj - // no need to bloat eolWithin because eolWithin always < minSpacing + bloatDist = std::max(minSpacing, bloatDist); frCoord bloatDistEolX = 0; frCoord bloatDistEolY = 0; if (drCon.eolWidth == 0) { @@ -733,29 +848,27 @@ void FlexDRWorker::modMinSpacingCostVia(const Rect& box, bool use_min_spacing = isBlockage && USEMINSPACING_OBS && !isFatVia; frCoord reqDist = getTech()->getLayer(lNum)->getMinSpacingValue( width1, width2, prl, use_min_spacing); - - if (ndr) { - reqDist = std::max(reqDist, ndr->getSpacing(z)); - } + reqDist = std::max(reqDist, minSpacing); if (distSquare < (frSquaredDistance) reqDist * reqDist) { switch (type) { case subRouteShape: - gridGraph_.subRouteShapeCostVia(i, j, zIdx); // safe access + gridGraph_.subRouteShapeCostVia(i, j, zIdx, ndr); // safe access break; case addRouteShape: - gridGraph_.addRouteShapeCostVia(i, j, zIdx); // safe access + gridGraph_.addRouteShapeCostVia(i, j, zIdx, ndr); // safe access break; case subFixedShape: - gridGraph_.subFixedShapeCostVia(i, j, zIdx); // safe access + gridGraph_.subFixedShapeCostVia(i, j, zIdx, ndr); // safe access break; case addFixedShape: - gridGraph_.addFixedShapeCostVia(i, j, zIdx); // safe access + gridGraph_.addFixedShapeCostVia(i, j, zIdx, ndr); // safe access break; default:; } } // eol, other obj to curr obj - modMinSpacingCostVia_eol(box, tmpBx, type, isUpperVia, drCon, i, j, z); + modMinSpacingCostVia_eol( + box, tmpBx, type, isUpperVia, drCon, i, j, z, ndr); } } } @@ -2495,8 +2608,8 @@ void FlexDRWorker::routeNet_postAstarWritePath( } auto net_ndr = net->getFrNet()->getNondefaultRule(); if (net_ndr != nullptr - && net_ndr->getPrefVia((startLayerNum + 1) / 2)) { - via = net_ndr->getPrefVia((startLayerNum + 1) / 2); + && net_ndr->getPrefVia((startLayerNum + 1) / 2 - 1)) { + via = net_ndr->getPrefVia((startLayerNum + 1) / 2 - 1); } auto currVia = std::make_unique(via); if (net->hasNDR() && AUTO_TAPER_NDR_NETS) { diff --git a/src/drt/src/dr/FlexGridGraph.h b/src/drt/src/dr/FlexGridGraph.h index bac8a764b5..88a1f79d4e 100644 --- a/src/drt/src/dr/FlexGridGraph.h +++ b/src/drt/src/dr/FlexGridGraph.h @@ -117,6 +117,11 @@ class FlexGridGraph } // unsafe access frLayerNum getLayerNum(frMIdx z) const { return zCoords_[z]; } + + // unsafe access + frLayerNum getMinLayerNum() const { return zCoords_.front(); } + frLayerNum getMaxLayerNum() const { return zCoords_.back(); } + bool hasMazeXIdx(frCoord in) const { return std::binary_search(xCoords_.begin(), xCoords_.end(), in); @@ -246,26 +251,50 @@ class FlexGridGraph frUInt4 getFixedShapeCostAdj(frMIdx x, frMIdx y, frMIdx z, - frDirEnum dir) const + frDirEnum dir, + bool consider_ndr) const { frUInt4 sol = 0; if (dir != frDirEnum::D && dir != frDirEnum::U) { reverse(x, y, z, dir); + const Node& node = nodes_[getIdx(x, y, z)]; if (dir == frDirEnum::W || dir == frDirEnum::E) { - sol = nodes_[getIdx(x, y, z)].fixedShapeCostPlanarHorz; + if (consider_ndr) { + sol = std::max(node.fixedShapeCostPlanarHorz, + node.fixedShapeCostPlanarHorzNDR); + } else { + sol = node.fixedShapeCostPlanarHorz; + } } else { - sol = nodes_[getIdx(x, y, z)].fixedShapeCostPlanarVert; + if (consider_ndr) { + sol = std::max(node.fixedShapeCostPlanarVert, + node.fixedShapeCostPlanarVertNDR); + } else { + sol = node.fixedShapeCostPlanarVert; + } } } else { correctU(x, y, z, dir); const Node& node = nodes_[getIdx(x, y, z)]; - sol = isOverrideShapeCost(x, y, z, dir) ? 0 : node.fixedShapeCostVia; + if (isOverrideShapeCost(x, y, z, dir)) { + sol = 0; + } else { + if (consider_ndr) { + sol = std::max(node.fixedShapeCostVia, node.fixedShapeCostViaNDR); + } else { + sol = node.fixedShapeCostVia; + } + } } return (sol); } - bool hasFixedShapeCostAdj(frMIdx x, frMIdx y, frMIdx z, frDirEnum dir) const + bool hasFixedShapeCostAdj(frMIdx x, + frMIdx y, + frMIdx z, + frDirEnum dir, + bool consider_ndr = false) const { - return getFixedShapeCostAdj(x, y, z, dir); + return getFixedShapeCostAdj(x, y, z, dir, consider_ndr); } bool isOverrideShapeCost(frMIdx x, frMIdx y, frMIdx z, frDirEnum dir) const { @@ -280,23 +309,38 @@ class FlexGridGraph frUInt4 getRouteShapeCostAdj(frMIdx x, frMIdx y, frMIdx z, - frDirEnum dir) const + frDirEnum dir, + bool consider_ndr) const { frUInt4 sol = 0; if (dir != frDirEnum::D && dir != frDirEnum::U) { reverse(x, y, z, dir); auto idx = getIdx(x, y, z); - sol = nodes_[idx].routeShapeCostPlanar; + if (consider_ndr) { + sol = std::max(nodes_[idx].routeShapeCostPlanar, + nodes_[idx].routeShapeCostPlanarNDR); + } else { + sol = nodes_[idx].routeShapeCostPlanar; + } } else { correctU(x, y, z, dir); auto idx = getIdx(x, y, z); - sol = nodes_[idx].routeShapeCostVia; + if (consider_ndr) { + sol = std::max(nodes_[idx].routeShapeCostVia, + nodes_[idx].routeShapeCostViaNDR); + } else { + sol = nodes_[idx].routeShapeCostVia; + } } return (sol); } - bool hasRouteShapeCostAdj(frMIdx x, frMIdx y, frMIdx z, frDirEnum dir) const + bool hasRouteShapeCostAdj(frMIdx x, + frMIdx y, + frMIdx z, + frDirEnum dir, + bool consider_ndr = false) const { - return getRouteShapeCostAdj(x, y, z, dir); + return getRouteShapeCostAdj(x, y, z, dir, consider_ndr); } // gets marker cost in the adjacent node following dir frUInt4 getMarkerCostAdj(frMIdx x, frMIdx y, frMIdx z, frDirEnum dir) const @@ -465,35 +509,51 @@ class FlexGridGraph } } } - void addRouteShapeCostPlanar(frMIdx x, frMIdx y, frMIdx z) + void addRouteShapeCostPlanar(frMIdx x, frMIdx y, frMIdx z, bool ndr = false) { auto& node = nodes_[getIdx(x, y, z)]; - node.routeShapeCostPlanar = addToByte(node.routeShapeCostPlanar, 1); + if (ndr) { + node.routeShapeCostPlanarNDR = addToByte(node.routeShapeCostPlanarNDR, 1); + } else { + node.routeShapeCostPlanar = addToByte(node.routeShapeCostPlanar, 1); + } } - void addRouteShapeCostVia(frMIdx x, frMIdx y, frMIdx z) + void addRouteShapeCostVia(frMIdx x, frMIdx y, frMIdx z, bool ndr = false) { auto& node = nodes_[getIdx(x, y, z)]; - node.routeShapeCostVia = addToByte(node.routeShapeCostVia, 1); + if (ndr) { + node.routeShapeCostViaNDR = addToByte(node.routeShapeCostViaNDR, 1); + } else { + node.routeShapeCostVia = addToByte(node.routeShapeCostVia, 1); + } } - void subRouteShapeCostPlanar(frMIdx x, frMIdx y, frMIdx z) + void subRouteShapeCostPlanar(frMIdx x, frMIdx y, frMIdx z, bool ndr = false) { auto& node = nodes_[getIdx(x, y, z)]; - node.routeShapeCostPlanar = subFromByte(node.routeShapeCostPlanar, 1); + if (ndr) { + node.routeShapeCostPlanarNDR + = subFromByte(node.routeShapeCostPlanarNDR, 1); + } else { + node.routeShapeCostPlanar = subFromByte(node.routeShapeCostPlanar, 1); + } } - void subRouteShapeCostVia(frMIdx x, frMIdx y, frMIdx z) + void subRouteShapeCostVia(frMIdx x, frMIdx y, frMIdx z, bool ndr = false) { auto& node = nodes_[getIdx(x, y, z)]; - node.routeShapeCostVia = subFromByte(node.routeShapeCostVia, 1); - } - void resetRouteShapeCostPlanar(frMIdx x, frMIdx y, frMIdx z) - { - auto idx = getIdx(x, y, z); - nodes_[idx].routeShapeCostPlanar = 0; + if (ndr) { + node.routeShapeCostViaNDR = subFromByte(node.routeShapeCostViaNDR, 1); + } else { + node.routeShapeCostVia = subFromByte(node.routeShapeCostVia, 1); + } } - void resetRouteShapeCostVia(frMIdx x, frMIdx y, frMIdx z) + void resetRouteShapeCostVia(frMIdx x, frMIdx y, frMIdx z, bool ndr = false) { auto idx = getIdx(x, y, z); - nodes_[idx].routeShapeCostVia = 0; + if (ndr) { + nodes_[idx].routeShapeCostViaNDR = 0; + } else { + nodes_[idx].routeShapeCostVia = 0; + } } void addMarkerCostPlanar(frMIdx x, frMIdx y, frMIdx z) { @@ -589,59 +649,105 @@ class FlexGridGraph } return (currCost == 0); } - void addFixedShapeCostPlanar(frMIdx x, frMIdx y, frMIdx z) + void addFixedShapeCostPlanar(frMIdx x, frMIdx y, frMIdx z, bool ndr = false) { if (isValid(x, y, z)) { auto& node = nodes_[getIdx(x, y, z)]; - node.fixedShapeCostPlanarHorz - = addToByte(node.fixedShapeCostPlanarHorz, 1); - node.fixedShapeCostPlanarVert - = addToByte(node.fixedShapeCostPlanarVert, 1); + if (ndr) { + node.fixedShapeCostPlanarHorzNDR + = addToByte(node.fixedShapeCostPlanarHorzNDR, 1); + node.fixedShapeCostPlanarVertNDR + = addToByte(node.fixedShapeCostPlanarVertNDR, 1); + } else { + node.fixedShapeCostPlanarHorz + = addToByte(node.fixedShapeCostPlanarHorz, 1); + node.fixedShapeCostPlanarVert + = addToByte(node.fixedShapeCostPlanarVert, 1); + } } } - void setFixedShapeCostPlanarVert(frMIdx x, frMIdx y, frMIdx z, frUInt4 c) + void setFixedShapeCostPlanarVert(frMIdx x, + frMIdx y, + frMIdx z, + frUInt4 c, + bool ndr = false) { if (isValid(x, y, z)) { auto& node = nodes_[getIdx(x, y, z)]; - node.fixedShapeCostPlanarVert = c; + if (ndr) { + node.fixedShapeCostPlanarVertNDR = c; + } else { + node.fixedShapeCostPlanarVert = c; + } } } - void setFixedShapeCostPlanarHorz(frMIdx x, frMIdx y, frMIdx z, frUInt4 c) + void setFixedShapeCostPlanarHorz(frMIdx x, + frMIdx y, + frMIdx z, + frUInt4 c, + bool ndr = false) { if (isValid(x, y, z)) { auto& node = nodes_[getIdx(x, y, z)]; - node.fixedShapeCostPlanarHorz = c; + if (ndr) { + node.fixedShapeCostPlanarHorzNDR = c; + } else { + node.fixedShapeCostPlanarHorz = c; + } } } - void addFixedShapeCostVia(frMIdx x, frMIdx y, frMIdx z) + void addFixedShapeCostVia(frMIdx x, frMIdx y, frMIdx z, bool ndr = false) { if (isValid(x, y, z)) { auto& node = nodes_[getIdx(x, y, z)]; - node.fixedShapeCostVia = addToByte(node.fixedShapeCostVia, 1); + if (ndr) { + node.fixedShapeCostViaNDR = addToByte(node.fixedShapeCostViaNDR, 1); + } else { + node.fixedShapeCostVia = addToByte(node.fixedShapeCostVia, 1); + } } } - void setFixedShapeCostVia(frMIdx x, frMIdx y, frMIdx z, frUInt4 c) + void setFixedShapeCostVia(frMIdx x, + frMIdx y, + frMIdx z, + frUInt4 c, + bool ndr = false) { if (isValid(x, y, z)) { auto& node = nodes_[getIdx(x, y, z)]; - node.fixedShapeCostVia = c; + if (ndr) { + node.fixedShapeCostViaNDR = c; + } else { + node.fixedShapeCostVia = c; + } } } - void subFixedShapeCostPlanar(frMIdx x, frMIdx y, frMIdx z) + void subFixedShapeCostPlanar(frMIdx x, frMIdx y, frMIdx z, bool ndr = false) { if (isValid(x, y, z)) { auto& node = nodes_[getIdx(x, y, z)]; - node.fixedShapeCostPlanarHorz - = subFromByte(node.fixedShapeCostPlanarHorz, 1); - node.fixedShapeCostPlanarVert - = subFromByte(node.fixedShapeCostPlanarVert, 1); + if (ndr) { + node.fixedShapeCostPlanarHorzNDR + = subFromByte(node.fixedShapeCostPlanarHorzNDR, 1); + node.fixedShapeCostPlanarVertNDR + = subFromByte(node.fixedShapeCostPlanarVertNDR, 1); + } else { + node.fixedShapeCostPlanarHorz + = subFromByte(node.fixedShapeCostPlanarHorz, 1); + node.fixedShapeCostPlanarVert + = subFromByte(node.fixedShapeCostPlanarVert, 1); + } } } - void subFixedShapeCostVia(frMIdx x, frMIdx y, frMIdx z) + void subFixedShapeCostVia(frMIdx x, frMIdx y, frMIdx z, bool ndr = false) { if (isValid(x, y, z)) { auto& node = nodes_[getIdx(x, y, z)]; - node.fixedShapeCostVia = subFromByte(node.fixedShapeCostVia, 1); + if (ndr) { + node.fixedShapeCostViaNDR = subFromByte(node.fixedShapeCostViaNDR, 1); + } else { + node.fixedShapeCostVia = subFromByte(node.fixedShapeCostVia, 1); + } } } @@ -802,23 +908,12 @@ class FlexGridGraph void setDstTaperBox(frBox3D* t) { dstTaperBox = t; } - frCoord getCostsNDR(frMIdx gridX, - frMIdx gridY, - frMIdx gridZ, - frDirEnum dir, - frDirEnum prevDir, - frLayer* layer) const; - frCoord getViaCostsNDR(frMIdx gridX, - frMIdx gridY, - frMIdx gridZ, - frDirEnum dir, - frDirEnum prevDir, - frLayer* layer) const; frCost getCosts(frMIdx gridX, frMIdx gridY, frMIdx gridZ, frDirEnum dir, - frLayer* layer) const; + frLayer* layer, + bool considerNDR) const; bool useNDRCosts(const FlexWavefrontGrid& p) const; frNonDefaultRule* getNDR() const { return ndr_; } @@ -956,9 +1051,19 @@ class FlexGridGraph frUInt4 fixedShapeCostPlanarHorz : cost_bits; // Byte8 frUInt4 fixedShapeCostPlanarVert : cost_bits; + // Byte9 + frUInt4 routeShapeCostPlanarNDR : cost_bits; + // Byte10 + frUInt4 routeShapeCostViaNDR : cost_bits; + // Byte 11 + frUInt4 fixedShapeCostViaNDR : cost_bits; + // Byte 12 + frUInt4 fixedShapeCostPlanarHorzNDR : cost_bits; + // Byte 13 + frUInt4 fixedShapeCostPlanarVertNDR : cost_bits; }; #ifndef DEBUG_DRT_UNDERFLOW - static_assert(sizeof(Node) == 12); + static_assert(sizeof(Node) == 16); #endif frVector nodes_; std::vector prevDirs_; diff --git a/src/drt/src/dr/FlexGridGraph_maze.cpp b/src/drt/src/dr/FlexGridGraph_maze.cpp index d108725bbe..936667d52d 100644 --- a/src/drt/src/dr/FlexGridGraph_maze.cpp +++ b/src/drt/src/dr/FlexGridGraph_maze.cpp @@ -473,210 +473,23 @@ frCost FlexGridGraph::getNextPathCost(const FlexWavefrontGrid& currGrid, } } } - - if (useNDRCosts(currGrid)) { - nextPathCost += getCostsNDR(gridX, gridY, gridZ, dir, currDir, layer); - } else { - nextPathCost += getCosts(gridX, gridY, gridZ, dir, layer); - } + nextPathCost + += getCosts(gridX, gridY, gridZ, dir, layer, useNDRCosts(currGrid)); return nextPathCost; } -frCoord FlexGridGraph::getCostsNDR(frMIdx gridX, - frMIdx gridY, - frMIdx gridZ, - frDirEnum dir, - frDirEnum prevDir, - frLayer* layer) const -{ - if ((dir == frDirEnum::U || dir == frDirEnum::D)) { - return getViaCostsNDR(gridX, gridY, gridZ, dir, prevDir, layer); - } - frCoord el = getEdgeLength(gridX, gridY, gridZ, dir); - frCoord cost = el; - cost += (hasGridCost(gridX, gridY, gridZ, dir) ? GRIDCOST * el : 0); - cost += (!hasGuide(gridX, gridY, gridZ, dir) ? GUIDECOST * el : 0); - frMIdx startX, startY, endX, endY; - frCoord r, x1, x2, y1, y2; - frCoord sp, wext; - frCoord layerWidth = std::max((int) layer->getWidth(), ndr_->getWidth(gridZ)); - sp = std::max( - ndr_->getSpacing(gridZ), - layer->getMinSpacingValue(layerWidth, layer->getWidth(), 0, false)); - wext = std::max(ndr_->getWireExtension(gridZ), (int) layer->getWidth() / 2) - - layer->getWidth() / 2; - - // get iteration bounds - r = layerWidth / 2 + sp + layer->getWidth() / 2 - 1; - if (dir == frDirEnum::N || dir == frDirEnum::S) { - startX = getLowerBoundIndex(xCoords_, x1 = (xCoords_[gridX] - r)); - endX = getUpperBoundIndex(xCoords_, x2 = (xCoords_[gridX] + r)); - startY = endY = gridY; - y1 = y2 = yCoords_[startY]; - if (prevDir == frDirEnum::UNKNOWN || prevDir != dir) { - if (dir == frDirEnum::N) { - startY - = getLowerBoundIndex(yCoords_, y1 = (yCoords_[gridY] - r - wext)); - } else { - endY = getUpperBoundIndex(yCoords_, y2 = (yCoords_[gridY] + r + wext)); - } - } - if (prevDir != frDirEnum::UNKNOWN) { - getNextGrid(gridX, gridY, gridZ, dir); - if (isDst(gridX, gridY, gridZ)) { - if (dir == frDirEnum::N) { - endY - = getUpperBoundIndex(yCoords_, y2 = (yCoords_[gridY] + r + wext)); - } else { - startY - = getLowerBoundIndex(yCoords_, y1 = (yCoords_[gridY] - r - wext)); - } - } - getPrevGrid(gridX, gridY, gridZ, dir); - } - } else { - startY = getLowerBoundIndex(yCoords_, y1 = (yCoords_[gridY] - r)); - endY = getUpperBoundIndex(yCoords_, y2 = (yCoords_[gridY] + r)); - startX = endX = gridX; - x1 = x2 = xCoords_[startX]; - if (prevDir == frDirEnum::UNKNOWN || prevDir != dir) { - if (dir == frDirEnum::E) { - startX - = getLowerBoundIndex(xCoords_, x1 = (xCoords_[gridX] - r - wext)); - } else { - endX = getUpperBoundIndex(xCoords_, x2 = (xCoords_[gridX] + r + wext)); - } - } - if (prevDir != frDirEnum::UNKNOWN) { - getNextGrid(gridX, gridY, gridZ, dir); - if (isDst(gridX, gridY, gridZ)) { - if (dir == frDirEnum::E) { - endX - = getUpperBoundIndex(xCoords_, x2 = (xCoords_[gridX] + r + wext)); - } else { - startX - = getLowerBoundIndex(xCoords_, x1 = (xCoords_[gridX] - r - wext)); - } - } - getPrevGrid(gridX, gridY, gridZ, dir); - } - } - if (xCoords_[startX] < x1) { - startX++; - } - if (xCoords_[endX] > x2) { - endX--; - } - if (yCoords_[startY] < y1) { - startY++; - } - if (yCoords_[endY] > y2) { - endY--; - } - // get costs - for (frMIdx x = startX; x <= endX; x++) { - for (frMIdx y = startY; y <= endY; y++) { - cost += (hasFixedShapeCostAdj(x, y, gridZ, dir) ? ggFixedShapeCost_ * el - : 0); - cost += (hasRouteShapeCostAdj(x, y, gridZ, dir) ? ggDRCCost_ * el : 0); - cost += (hasMarkerCostAdj(x, y, gridZ, dir) ? ggMarkerCost_ * el : 0); - cost += (isBlocked(x, y, gridZ, dir) - ? BLOCKCOST * layer->getMinWidth() * 20 - : 0); - } - } - return cost; -} - -frCoord FlexGridGraph::getViaCostsNDR(frMIdx gridX, - frMIdx gridY, - frMIdx gridZ, - frDirEnum dir, - frDirEnum prevDir, - frLayer* layer) const -{ - if (ndr_->getPrefVia(dir == frDirEnum::U ? gridZ : gridZ - 1) == nullptr) { - return getCosts(gridX, gridY, gridZ, dir, layer); - } - frMIdx startX, startY, endX, endY; - frCoord x1, x2, y1, y2; - frCoord layerWidth = std::max((int) layer->getWidth(), ndr_->getWidth(gridZ)); - frCoord r, sp; - sp = std::max( - ndr_->getSpacing(gridZ), - layer->getMinSpacingValue(layerWidth, layer->getWidth(), 0, false)); - - // get iteration bounds - r = layerWidth / 2 + sp + layer->getWidth() / 2 - 1; - frCoord el = getEdgeLength(gridX, gridY, gridZ, dir); - frCoord cost = el; - - startX = getLowerBoundIndex(xCoords_, x1 = (xCoords_[gridX] - r)); - endX = getUpperBoundIndex(xCoords_, x2 = (xCoords_[gridX] + r)); - startY = getLowerBoundIndex(yCoords_, y1 = (yCoords_[gridY] - r)); - endY = getUpperBoundIndex(yCoords_, y2 = (yCoords_[gridY] + r)); - cost += (hasFixedShapeCostAdj(gridX, gridY, gridZ, dir) - ? ggFixedShapeCost_ * el - : 0); - cost - += (hasRouteShapeCostAdj(gridX, gridY, gridZ, dir) ? ggDRCCost_ * el : 0); - cost += (hasMarkerCostAdj(gridX, gridY, gridZ, dir) ? ggMarkerCost_ * el : 0); - cost += (isBlocked(gridX, gridY, gridZ, dir) - ? BLOCKCOST * layer->getMinWidth() * 20 - : 0); - dir = frDirEnum::UNKNOWN; - - if (xCoords_[startX] < x1) { - startX++; - } - if (xCoords_[endX] > x2) { - endX--; - } - if (yCoords_[startY] < y1) { - startY++; - } - if (yCoords_[endY] > y2) { - endY--; - } - switch (prevDir) { - case frDirEnum::N: - endY = gridY - 1; - break; - case frDirEnum::S: - startY = gridY + 1; - break; - case frDirEnum::E: - startX = gridX + 1; - break; - case frDirEnum::W: - endX = gridX - 1; - break; - default: - break; - } - // get costs - for (frMIdx x = startX; x <= endX; x++) { - for (frMIdx y = startY; y <= endY; y++) { - cost += (hasFixedShapeCostAdj(x, y, gridZ, dir) ? ggFixedShapeCost_ * el - : 0); - cost += (hasRouteShapeCostAdj(x, y, gridZ, dir) ? ggDRCCost_ * el : 0); - cost += (hasMarkerCostAdj(x, y, gridZ, dir) ? ggMarkerCost_ * el : 0); - } - } - return cost; -} - frCost FlexGridGraph::getCosts(frMIdx gridX, frMIdx gridY, frMIdx gridZ, frDirEnum dir, - frLayer* layer) const + frLayer* layer, + bool considerNDR) const { bool gridCost = hasGridCost(gridX, gridY, gridZ, dir); - bool drcCost = hasRouteShapeCostAdj(gridX, gridY, gridZ, dir); + bool drcCost = hasRouteShapeCostAdj(gridX, gridY, gridZ, dir, considerNDR); bool markerCost = hasMarkerCostAdj(gridX, gridY, gridZ, dir); - bool shapeCost = hasFixedShapeCostAdj(gridX, gridY, gridZ, dir); + bool shapeCost = hasFixedShapeCostAdj(gridX, gridY, gridZ, dir, considerNDR); bool blockCost = isBlocked(gridX, gridY, gridZ, dir); bool guideCost = hasGuide(gridX, gridY, gridZ, dir); frCoord edgeLength = getEdgeLength(gridX, gridY, gridZ, dir); diff --git a/src/drt/src/io/io.cpp b/src/drt/src/io/io.cpp index b75dbf92ba..56ab2c53dc 100644 --- a/src/drt/src/io/io.cpp +++ b/src/drt/src/io/io.cpp @@ -417,8 +417,11 @@ void io::Parser::createNDR(odb::dbTechNonDefaultRule* ndr) std::vector vias; ndr->getUseVias(vias); for (auto via : vias) { - fnd->addVia(design_->getTech()->getVia(via->getName()), - via->getBottomLayer()->getNumber() / 2); + z = design_->tech_->getLayer(via->getBottomLayer()->getName()) + ->getLayerNum() + / 2 + - 1; + fnd->addVia(design_->getTech()->getVia(via->getName()), z); } std::vector viaRules; ndr->getUseViaRules(viaRules); diff --git a/src/drt/test/ndr_vias1.defok b/src/drt/test/ndr_vias1.defok index c0e9fd7e49..bd68ce95cd 100644 --- a/src/drt/test/ndr_vias1.defok +++ b/src/drt/test/ndr_vias1.defok @@ -214,69 +214,72 @@ PINS 1 ; END PINS NETS 8 ; - clk ( PIN clk ) ( clkbuf_0_clk A ) + USE CLOCK + NONDEFAULTRULE NDR_3W_3S - + ROUTED met1 ( 96600 148410 210 ) ( * 151130 210 ) - NEW met1 ( 89470 151130 210 ) ( 96600 * 210 ) - NEW met2 ( 89470 340 0 ) ( * 151130 210 ) - NEW met1 ( 96600 148410 210 ) ( 110400 * 210 ) + + ROUTED met2 ( 89470 340 0 ) ( * 148410 210 ) + NEW met1 ( 89470 148410 210 ) ( 110400 * 210 ) NEW met1 ( 110400 148410 210 ) ( * 151130 210 ) NEW met1 ( 110400 151130 210 ) ( 149500 * 210 ) NEW met1 TAPER ( 149500 151130 ) ( 151110 * ) - NEW met1 ( 89470 151130 ) M1M2_PR_R + NEW met1 ( 89470 148410 ) M1M2_PR_R NEW li1 TAPER ( 151110 151130 ) L1M1_PR_R ; - clknet_0_clk ( clkbuf_2_3__f_clk A ) ( clkbuf_2_2__f_clk A ) ( clkbuf_2_1__f_clk A ) ( clkbuf_2_0__f_clk A ) ( clkbuf_0_clk X ) + USE CLOCK + NONDEFAULTRULE NDR_3W_3S - + ROUTED met1 TAPER ( 167900 118490 ) ( 169510 * ) - NEW met1 TAPER ( 167900 169830 ) ( 169510 * ) + + ROUTED met1 TAPER ( 167900 169830 ) ( 169510 * ) + NEW met1 TAPER ( 167900 118490 ) ( 169510 * ) NEW met2 ( 152030 169830 210 ) ( * 172890 210 ) NEW met1 TAPER ( 130870 172890 ) ( 132710 * ) NEW met1 ( 132710 172890 210 ) ( 152030 * 210 ) NEW met1 ( 152030 169830 210 ) ( 167900 * 210 ) + NEW met1 ( 152950 118150 210 ) ( * 118490 210 ) + NEW met2 ( 152030 118150 210 ) ( * 150450 210 ) + NEW met1 TAPER ( 152030 150450 ) ( 154790 * ) + NEW met2 ( 154790 150450 210 ) ( * 169830 210 ) + NEW met1 ( 152950 118490 210 ) ( 167900 * 210 ) + NEW met2 ( 119370 118150 210 ) ( * 118490 210 ) + NEW met2 ( 118450 118490 210 ) ( 119370 * 210 ) NEW met1 TAPER ( 116610 118490 ) ( 118220 * ) - NEW met1 TAPER ( 152950 151130 ) ( 154330 * ) - NEW met2 ( 154330 118490 210 ) ( * 151130 210 ) - NEW met2 ( 152950 151130 210 ) ( * 169830 210 ) - NEW met1 ( 118220 118490 210 ) ( 167900 * 210 ) - NEW li1 TAPER ( 169510 118490 ) L1M1_PR_R + NEW met1 ( 118220 118490 210 ) ( 118450 * 210 ) + NEW met1 ( 119370 118150 210 ) ( 152950 * 210 ) NEW li1 TAPER ( 169510 169830 ) L1M1_PR_R + NEW li1 TAPER ( 169510 118490 ) L1M1_PR_R NEW met1 ( 152030 169830 ) M1M2_PR_R NEW met1 ( 152030 172890 ) M1M2_PR_R NEW li1 TAPER ( 130870 172890 ) L1M1_PR_R - NEW met1 ( 152950 169830 ) M1M2_PR_R - NEW li1 TAPER ( 116610 118490 ) L1M1_PR_R - NEW li1 TAPER ( 152950 151130 ) L1M1_PR_R - NEW met1 TAPER ( 154330 151130 ) M1M2_PR_R - NEW met1 ( 154330 118490 ) M1M2_PR_R - NEW met1 TAPER ( 152950 151130 ) M1M2_PR_R - NEW met1 TAPER ( 152950 169830 ) RECT ( -490 -70 0 70 ) - NEW met1 TAPER ( 154330 118490 ) RECT ( -490 -70 0 70 ) - NEW met1 TAPER ( 152950 151130 ) RECT ( -490 -70 0 70 ) ; + NEW met1 ( 154790 169830 ) M1M2_PR_R + NEW li1 TAPER ( 152030 150450 ) L1M1_PR_R + NEW met1 TAPER ( 152030 150450 ) M1M2_PR_R + NEW met1 ( 152030 118150 ) M1M2_PR_R + NEW met1 ( 154790 150450 ) M1M2_PR_R + NEW met1 ( 119370 118150 ) M1M2_PR_R + NEW met1 ( 118450 118490 ) M1M2_PR_R + NEW li1 TAPER ( 116610 118490 ) L1M1_PR_R ; - clknet_2_0__leaf_clk ( _414_ CLK ) ( _418_ CLK ) ( _428_ CLK ) ( _429_ CLK ) ( _432_ CLK ) ( _434_ CLK ) ( _444_ CLK ) ( _445_ CLK ) ( clkbuf_2_0__f_clk X ) + USE CLOCK + NONDEFAULTRULE NDR_3W_3S - + ROUTED met1 ( 87630 120870 210 ) ( 91540 * 210 ) + + ROUTED met1 ( 88550 120870 210 ) ( 91540 * 210 ) NEW met1 TAPER ( 91540 120870 ) ( 93150 * ) - NEW met2 ( 87630 104890 210 ) ( * 120870 210 ) - NEW met1 ( 87630 104890 210 ) ( 87860 * 210 ) - NEW met1 TAPER ( 87860 104890 ) ( 89470 * ) + NEW met2 ( 88550 104890 210 ) ( * 120870 210 ) + NEW met1 TAPER ( 88550 104890 ) ( 89470 * ) NEW met1 ( 143750 88570 210 ) ( 144900 * 210 ) NEW met1 TAPER ( 144900 88570 ) ( 146510 * ) + NEW met1 ( 88550 118490 210 ) ( 96600 * 210 ) NEW met2 ( 125350 115430 210 ) ( * 120870 210 ) NEW met1 ( 125350 115430 210 ) ( 142140 * 210 ) NEW met1 TAPER ( 142140 115430 ) ( 143750 * ) NEW met2 ( 117530 115430 210 ) ( * 117810 210 ) NEW met1 ( 117530 115430 210 ) ( 125350 * 210 ) - NEW met2 ( 111090 118490 210 ) ( * 120870 210 ) - NEW met1 ( 111090 118490 210 ) ( 115460 * 210 ) - NEW met1 TAPER ( 115460 118490 ) ( 115690 * ) - NEW met1 TAPER ( 115690 117810 ) ( * 118490 ) - NEW met1 TAPER ( 115690 117810 ) ( 117530 * ) - NEW met2 ( 111090 120870 210 ) ( * 134470 210 ) - NEW met1 ( 87630 118490 210 ) ( 111090 * 210 ) + NEW met2 ( 111090 118150 210 ) ( * 120870 210 ) + NEW met1 ( 111090 118150 210 ) ( 112010 * 210 ) + NEW met1 ( 112010 117810 210 ) ( * 118150 210 ) + NEW met1 ( 112010 117810 210 ) ( 115460 * 210 ) + NEW met1 TAPER ( 115460 117810 ) ( 117530 * ) + NEW met2 ( 111090 120870 210 ) ( * 134810 210 ) + NEW met1 ( 96600 118150 210 ) ( * 118490 210 ) + NEW met1 ( 96600 118150 210 ) ( 111090 * 210 ) NEW met2 ( 136850 115430 210 ) ( * 148070 210 ) NEW met2 ( 143750 88570 210 ) ( * 115430 210 ) NEW li1 TAPER ( 93150 120870 ) L1M1_PR_R - NEW met1 ( 87630 120870 ) M1M2_PR_R - NEW met1 ( 87630 104890 ) M1M2_PR_R + NEW met1 ( 88550 120870 ) M1M2_PR_R + NEW met1 TAPER ( 88550 104890 ) M1M2_PR_R NEW li1 TAPER ( 89470 104890 ) L1M1_PR_R - NEW met1 ( 87630 118490 ) M1M2_PR_R + NEW met1 ( 88550 118490 ) M1M2_PR_R NEW met1 ( 143750 88570 ) M1M2_PR_R NEW li1 TAPER ( 146510 88570 ) L1M1_PR_R NEW li1 TAPER ( 136850 148070 ) L1M1_PR_R @@ -291,115 +294,98 @@ NETS 8 ; NEW met1 ( 117530 115430 ) M1M2_PR_R NEW li1 TAPER ( 111090 120870 ) L1M1_PR_R NEW met1 TAPER ( 111090 120870 ) M1M2_PR_R - NEW met1 ( 111090 118490 ) M1M2_PR_R - NEW li1 TAPER ( 111090 134470 ) L1M1_PR_R - NEW met1 TAPER ( 111090 134470 ) M1M2_PR_R - NEW met1 ( 136850 115430 ) M1M2_PR_R - NEW met2 TAPER ( 87630 118490 ) RECT ( -70 -305 70 0 ) - NEW met1 TAPER ( 136850 148070 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 143750 115430 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 125350 120870 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 117530 117810 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 111090 120870 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 111090 134470 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 136850 115430 ) RECT ( -490 -70 0 70 ) ; + NEW met1 ( 111090 118150 ) M1M2_PR_R + NEW li1 TAPER ( 111090 134810 ) L1M1_PR_R + NEW met1 TAPER ( 111090 134810 ) M1M2_PR_R + NEW met1 ( 136850 115430 ) M1M2_PR_R ; - clknet_2_1__leaf_clk ( _423_ CLK ) ( _424_ CLK ) ( _425_ CLK ) ( _426_ CLK ) ( _427_ CLK ) ( _440_ CLK ) ( _441_ CLK ) ( _442_ CLK ) ( _443_ CLK ) ( clkbuf_2_1__f_clk X ) + USE CLOCK + NONDEFAULTRULE NDR_3W_3S - + ROUTED met1 TAPER ( 205850 112710 ) ( 206310 * ) - NEW met2 ( 205850 96730 210 ) ( * 112710 210 ) - NEW met1 ( 200330 112710 210 ) ( 204700 * 210 ) - NEW met1 TAPER ( 204700 112710 ) ( 205850 * ) - NEW met1 ( 200330 129030 210 ) ( 204700 * 210 ) + + ROUTED met1 TAPER ( 163530 88230 ) ( 164450 * ) + NEW met1 ( 163530 85850 210 ) ( * 86700 210 ) + NEW met1 TAPER ( 163530 86700 ) ( * 88230 ) + NEW met1 ( 163530 85850 210 ) ( 178710 * 210 ) + NEW met2 ( 178710 85850 210 ) ( * 90950 210 ) + NEW met2 ( 158010 88230 210 ) ( * 102170 210 ) + NEW met1 ( 158010 88230 210 ) ( 162610 * 210 ) + NEW met1 TAPER ( 162610 88230 ) ( 163530 * ) + NEW met1 TAPER ( 169510 117810 ) ( 170430 * ) + NEW met1 TAPER ( 169510 117470 ) ( * 117810 ) + NEW met1 TAPER ( 168130 117470 ) ( 169510 * ) + NEW met1 ( 200330 113050 210 ) ( 204700 * 210 ) + NEW met1 TAPER ( 204700 113050 ) ( 206310 * ) + NEW met2 ( 200330 113050 210 ) ( * 117810 210 ) + NEW met1 TAPER ( 170430 117810 ) ( 173190 * ) + NEW met1 ( 173190 117810 210 ) ( 200330 * 210 ) + NEW met2 ( 199410 117810 210 ) ( * 137190 210 ) + NEW met1 ( 199410 129030 210 ) ( 204700 * 210 ) NEW met1 TAPER ( 204700 129030 ) ( 206310 * ) - NEW met2 ( 200330 112710 210 ) ( * 131100 210 ) - NEW met2 ( 199410 131100 210 ) ( 200330 * 210 ) - NEW met2 ( 199410 131100 210 ) ( * 137190 210 ) - NEW met2 ( 164450 88570 210 ) ( * 90950 210 ) - NEW met1 ( 164450 90950 210 ) ( 177100 * 210 ) - NEW met1 TAPER ( 177100 90950 ) ( 178710 * ) - NEW met2 ( 158010 88570 210 ) ( * 101830 210 ) - NEW met1 ( 158010 88570 210 ) ( 162610 * 210 ) - NEW met1 TAPER ( 162610 88570 ) ( 164450 * ) - NEW met1 TAPER ( 171350 118490 ) ( 172730 * ) - NEW met2 ( 172730 90950 210 ) ( * 118490 210 ) - NEW met2 ( 172730 118490 210 ) ( * 120530 210 ) - NEW met1 TAPER ( 168130 120530 ) ( 172730 * ) - NEW met1 ( 172730 120530 210 ) ( 200330 * 210 ) + NEW met2 ( 205850 96730 210 ) ( * 113050 210 ) NEW met1 ( 152950 129370 210 ) ( 154330 * 210 ) NEW met1 TAPER ( 154330 129370 ) ( 156170 * ) NEW met2 ( 152950 129370 210 ) ( * 148070 210 ) - NEW met2 ( 156170 120530 210 ) ( * 129370 210 ) - NEW met1 ( 156170 120530 210 ) ( 168130 * 210 ) - NEW li1 TAPER ( 206310 112710 ) L1M1_PR_R - NEW met1 TAPER ( 205850 112710 ) M1M2_PR_R + NEW met2 ( 156170 117470 210 ) ( * 129370 210 ) + NEW met2 ( 158010 102170 210 ) ( * 117470 210 ) + NEW met1 ( 156170 117470 210 ) ( 168130 * 210 ) NEW li1 TAPER ( 205850 96730 ) L1M1_PR_R NEW met1 TAPER ( 205850 96730 ) M1M2_PR_R - NEW met1 ( 200330 112710 ) M1M2_PR_R - NEW li1 TAPER ( 206310 129030 ) L1M1_PR_R - NEW met1 ( 200330 129030 ) M1M2_PR_R - NEW met1 ( 200330 120530 ) M1M2_PR_R + NEW li1 TAPER ( 164450 88230 ) L1M1_PR_R + NEW met1 ( 178710 85850 ) M1M2_PR_R + NEW li1 TAPER ( 178710 90950 ) L1M1_PR_R + NEW met1 TAPER ( 178710 90950 ) M1M2_PR_R + NEW li1 TAPER ( 158010 102170 ) L1M1_PR_R + NEW met1 TAPER ( 158010 102170 ) M1M2_PR_R + NEW met1 ( 158010 88230 ) M1M2_PR_R + NEW li1 TAPER ( 170430 117810 ) L1M1_PR_R + NEW li1 TAPER ( 206310 113050 ) L1M1_PR_R + NEW met1 ( 200330 113050 ) M1M2_PR_R + NEW met1 ( 200330 117810 ) M1M2_PR_R + NEW met1 TAPER ( 205850 113050 ) M1M2_PR_R NEW li1 TAPER ( 199410 137190 ) L1M1_PR_R NEW met1 TAPER ( 199410 137190 ) M1M2_PR_R - NEW li1 TAPER ( 164450 88570 ) L1M1_PR_R - NEW met1 TAPER ( 164450 88570 ) M1M2_PR_R - NEW met1 ( 164450 90950 ) M1M2_PR_R - NEW li1 TAPER ( 178710 90950 ) L1M1_PR_R - NEW li1 TAPER ( 158010 101830 ) L1M1_PR_R - NEW met1 TAPER ( 158010 101830 ) M1M2_PR_R - NEW met1 ( 158010 88570 ) M1M2_PR_R - NEW li1 TAPER ( 171350 118490 ) L1M1_PR_R - NEW met1 TAPER ( 172730 118490 ) M1M2_PR_R - NEW met1 ( 172730 90950 ) M1M2_PR_R - NEW met1 TAPER ( 172730 120530 ) M1M2_PR_R + NEW met1 ( 199410 117810 ) M1M2_PR_R + NEW li1 TAPER ( 206310 129030 ) L1M1_PR_R + NEW met1 ( 199410 129030 ) M1M2_PR_R NEW li1 TAPER ( 156170 129370 ) L1M1_PR_R NEW met1 ( 152950 129370 ) M1M2_PR_R NEW li1 TAPER ( 152950 148070 ) L1M1_PR_R NEW met1 TAPER ( 152950 148070 ) M1M2_PR_R - NEW met1 ( 156170 120530 ) M1M2_PR_R + NEW met1 ( 156170 117470 ) M1M2_PR_R NEW met1 TAPER ( 156170 129370 ) M1M2_PR_R - NEW met1 TAPER ( 205850 96730 ) RECT ( -355 -70 0 70 ) - NEW met2 TAPER ( 200330 129030 ) RECT ( -70 -305 70 0 ) - NEW met2 TAPER ( 200330 120530 ) RECT ( -70 -305 70 0 ) - NEW met1 TAPER ( 199410 137190 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 164450 88570 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 158010 101830 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 172730 90950 ) RECT ( -490 -70 0 70 ) - NEW met1 TAPER ( 152950 148070 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 156170 129370 ) RECT ( -490 -70 0 70 ) ; + NEW met1 ( 158010 117470 ) M1M2_PR_R ; - clknet_2_2__leaf_clk ( _411_ CLK ) ( _413_ CLK ) ( _415_ CLK ) ( _416_ CLK ) ( _417_ CLK ) ( _421_ CLK ) ( _430_ CLK ) ( _431_ CLK ) ( _433_ CLK ) ( _437_ CLK ) ( clkbuf_2_2__f_clk X ) + USE CLOCK + NONDEFAULTRULE NDR_3W_3S - + ROUTED met1 TAPER ( 98210 151130 ) ( 100050 * ) - NEW met2 ( 109250 183770 210 ) ( * 186150 210 ) + + ROUTED met2 ( 109250 183770 210 ) ( * 186150 210 ) NEW met1 ( 98210 183770 210 ) ( 107410 * 210 ) NEW met1 TAPER ( 107410 183770 ) ( 109250 * ) NEW met2 ( 96830 183770 210 ) ( * 186150 210 ) NEW met1 ( 96830 183770 210 ) ( 98210 * 210 ) + NEW met1 TAPER ( 98210 151130 ) ( 100050 * ) NEW met2 ( 98210 151130 210 ) ( * 183770 210 ) - NEW met2 ( 137770 210460 210 ) ( * 210630 210 ) - NEW met3 ( 137770 210460 450 ) ( 143290 * 450 ) - NEW met2 ( 143290 210460 210 ) ( * 210630 210 ) - NEW met1 ( 143290 210630 210 ) ( 148810 * 210 ) + NEW met1 TAPER ( 136850 210630 ) ( 137770 * ) + NEW met1 ( 136850 208250 210 ) ( * 209100 210 ) + NEW met1 TAPER ( 136850 209100 ) ( * 210630 ) + NEW met1 ( 136850 208250 210 ) ( 146970 * 210 ) + NEW met1 ( 146970 208250 210 ) ( * 210630 210 ) + NEW met1 ( 146970 210630 210 ) ( 148810 * 210 ) NEW met1 TAPER ( 148810 210630 ) ( 150650 * ) - NEW met1 TAPER ( 135930 210630 ) ( 137770 * ) - NEW met1 ( 126270 210630 210 ) ( 135930 * 210 ) + NEW met1 ( 126270 208250 210 ) ( 136850 * 210 ) NEW met2 ( 140990 159290 210 ) ( * 175270 210 ) NEW met1 ( 140990 159290 210 ) ( 142140 * 210 ) NEW met1 TAPER ( 142140 159290 ) ( 143750 * ) - NEW met2 ( 131790 172210 210 ) ( * 175270 210 ) - NEW met1 ( 131790 175270 210 ) ( 139380 * 210 ) + NEW met1 TAPER ( 130410 172210 ) ( 131790 * ) + NEW met2 ( 130410 172210 210 ) ( * 175270 210 ) + NEW met1 ( 130410 175270 210 ) ( 139380 * 210 ) NEW met1 TAPER ( 139380 175270 ) ( 140990 * ) - NEW met2 ( 125810 175270 210 ) ( * 183430 210 ) - NEW met1 ( 125810 175270 210 ) ( 131790 * 210 ) + NEW met2 ( 125810 175270 210 ) ( * 183770 210 ) + NEW met1 ( 125810 175270 210 ) ( 130410 * 210 ) NEW met2 ( 125810 206380 210 ) ( 126270 * 210 ) - NEW met2 ( 125810 183430 210 ) ( * 206380 210 ) - NEW met2 ( 111550 197370 210 ) ( * 199750 210 ) + NEW met2 ( 125810 183770 210 ) ( * 206380 210 ) + NEW met2 ( 111550 197370 210 ) ( * 200090 210 ) NEW met1 ( 111550 197370 210 ) ( 125810 * 210 ) NEW met1 TAPER ( 125810 199750 ) ( 126270 * ) NEW met1 ( 109250 186150 210 ) ( 125810 * 210 ) - NEW met2 ( 126270 206380 210 ) ( * 210630 210 ) - NEW met1 ( 98210 151130 ) M1M2_PR_R - NEW li1 TAPER ( 100050 151130 ) L1M1_PR_R - NEW met1 ( 126270 210630 ) M1M2_PR_R + NEW met2 ( 126270 206380 210 ) ( * 208250 210 ) + NEW met1 ( 126270 208250 ) M1M2_PR_R NEW li1 TAPER ( 109250 183770 ) L1M1_PR_R NEW met1 TAPER ( 109250 183770 ) M1M2_PR_R NEW met1 ( 109250 186150 ) M1M2_PR_R @@ -407,94 +393,75 @@ NETS 8 ; NEW li1 TAPER ( 96830 186150 ) L1M1_PR_R NEW met1 TAPER ( 96830 186150 ) M1M2_PR_R NEW met1 ( 96830 183770 ) M1M2_PR_R + NEW met1 ( 98210 151130 ) M1M2_PR_R + NEW li1 TAPER ( 100050 151130 ) L1M1_PR_R NEW li1 TAPER ( 137770 210630 ) L1M1_PR_R - NEW met1 TAPER ( 137770 210630 ) M1M2_PR_R - NEW met2 ( 137770 210460 ) M2M3_PR - NEW met2 ( 143290 210460 ) M2M3_PR - NEW met1 ( 143290 210630 ) M1M2_PR_R NEW li1 TAPER ( 150650 210630 ) L1M1_PR_R NEW li1 TAPER ( 140990 175270 ) L1M1_PR_R NEW met1 TAPER ( 140990 175270 ) M1M2_PR_R NEW met1 ( 140990 159290 ) M1M2_PR_R NEW li1 TAPER ( 143750 159290 ) L1M1_PR_R NEW li1 TAPER ( 131790 172210 ) L1M1_PR_R - NEW met1 TAPER ( 131790 172210 ) M1M2_PR_R - NEW met1 ( 131790 175270 ) M1M2_PR_R - NEW li1 TAPER ( 125810 183430 ) L1M1_PR_R - NEW met1 TAPER ( 125810 183430 ) M1M2_PR_R + NEW met1 TAPER ( 130410 172210 ) M1M2_PR_R + NEW met1 ( 130410 175270 ) M1M2_PR_R + NEW li1 TAPER ( 125810 183770 ) L1M1_PR_R + NEW met1 TAPER ( 125810 183770 ) M1M2_PR_R NEW met1 ( 125810 175270 ) M1M2_PR_R - NEW li1 TAPER ( 111550 199750 ) L1M1_PR_R - NEW met1 TAPER ( 111550 199750 ) M1M2_PR_R + NEW li1 TAPER ( 111550 200090 ) L1M1_PR_R + NEW met1 TAPER ( 111550 200090 ) M1M2_PR_R NEW met1 ( 111550 197370 ) M1M2_PR_R NEW met1 ( 125810 197370 ) M1M2_PR_R NEW li1 TAPER ( 126270 199750 ) L1M1_PR_R NEW met1 TAPER ( 125810 199750 ) M1M2_PR_R - NEW met1 ( 125810 186150 ) M1M2_PR_R - NEW met1 TAPER ( 109250 183770 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 96830 186150 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 137770 210630 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 140990 175270 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 131790 172210 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 125810 183430 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 111550 199750 ) RECT ( -355 -70 0 70 ) - NEW met2 TAPER ( 125810 197370 ) RECT ( -70 -305 70 0 ) - NEW met2 TAPER ( 125810 199750 ) RECT ( -70 -305 70 0 ) - NEW met2 TAPER ( 125810 186150 ) RECT ( -70 -305 70 0 ) ; + NEW met1 ( 125810 186150 ) M1M2_PR_R ; - clknet_2_3__leaf_clk ( _412_ CLK ) ( _419_ CLK ) ( _420_ CLK ) ( _422_ CLK ) ( _435_ CLK ) ( _436_ CLK ) ( _438_ CLK ) ( _439_ CLK ) ( clkbuf_2_3__f_clk X ) + USE CLOCK + NONDEFAULTRULE NDR_3W_3S - + ROUTED met1 TAPER ( 204010 194310 ) ( 205850 * ) - NEW met2 ( 201250 164730 210 ) ( * 177990 210 ) - NEW met1 ( 201250 177990 210 ) ( 205620 * 210 ) - NEW met1 TAPER ( 205620 177990 ) ( 207230 * ) - NEW met1 ( 192050 177990 210 ) ( 201250 * 210 ) - NEW met2 ( 192050 153850 210 ) ( * 164730 210 ) - NEW met1 ( 192050 164730 210 ) ( 199535 * 210 ) - NEW met1 TAPER ( 199535 164730 ) ( 201250 * ) - NEW met2 ( 192050 177990 210 ) ( * 191930 210 ) - NEW met1 ( 165830 175610 210 ) ( 171580 * 210 ) + + ROUTED met1 ( 165830 175610 210 ) ( 171580 * 210 ) NEW met1 TAPER ( 171580 175610 ) ( 173190 * ) - NEW met2 ( 170430 170510 210 ) ( * 175610 210 ) - NEW met2 ( 177330 164730 210 ) ( * 170510 210 ) - NEW met1 TAPER ( 170430 170510 ) ( 173135 * ) - NEW met1 ( 173135 170510 210 ) ( 177330 * 210 ) - NEW met1 ( 177330 164730 210 ) ( 192050 * 210 ) + NEW met2 ( 170890 170510 210 ) ( * 175610 210 ) + NEW met2 ( 192050 179350 210 ) ( * 191590 210 ) + NEW met1 ( 173190 179350 210 ) ( 192050 * 210 ) + NEW met2 ( 173190 175610 210 ) ( * 179350 210 ) + NEW met1 TAPER ( 204010 194310 ) ( 205850 * ) + NEW met2 ( 192050 153850 210 ) ( * 179350 210 ) NEW met1 ( 153870 175610 210 ) ( * 176460 210 ) NEW met1 TAPER ( 153870 176460 ) ( * 177990 ) NEW met1 TAPER ( 153870 177990 ) ( 154790 * ) NEW met1 ( 153870 175610 210 ) ( 165830 * 210 ) + NEW met1 ( 192050 164730 210 ) ( 193200 * 210 ) + NEW met2 ( 201250 164390 210 ) ( * 178330 210 ) + NEW met1 ( 201250 178330 210 ) ( 205620 * 210 ) + NEW met1 TAPER ( 205620 178330 ) ( 207230 * ) + NEW met1 ( 193200 164390 210 ) ( * 164730 210 ) + NEW met1 ( 193200 164390 210 ) ( 199410 * 210 ) + NEW met1 TAPER ( 199410 164390 ) ( 201250 * ) NEW met2 ( 165830 175610 210 ) ( * 193200 210 ) NEW met2 ( 163990 193200 210 ) ( 165830 * 210 ) NEW met2 ( 163990 193200 210 ) ( * 210630 210 ) - NEW met2 ( 192050 191930 210 ) ( * 194310 210 ) + NEW met2 ( 192050 191590 210 ) ( * 194310 210 ) NEW met1 ( 192050 194310 210 ) ( 204010 * 210 ) - NEW li1 TAPER ( 192050 191930 ) L1M1_PR_R - NEW met1 TAPER ( 192050 191930 ) M1M2_PR_R + NEW met1 ( 165830 175610 ) M1M2_PR_R + NEW li1 TAPER ( 173190 175610 ) L1M1_PR_R + NEW li1 TAPER ( 170890 170510 ) L1M1_PR_R + NEW met1 TAPER ( 170890 170510 ) M1M2_PR_R + NEW met1 ( 170890 175610 ) M1M2_PR_R + NEW li1 TAPER ( 192050 191590 ) L1M1_PR_R + NEW met1 TAPER ( 192050 191590 ) M1M2_PR_R + NEW met1 ( 192050 179350 ) M1M2_PR_R + NEW met1 ( 173190 179350 ) M1M2_PR_R + NEW met1 TAPER ( 173190 175610 ) M1M2_PR_R + NEW met1 ( 192050 164730 ) M1M2_PR_R NEW li1 TAPER ( 205850 194310 ) L1M1_PR_R - NEW li1 TAPER ( 201250 164730 ) L1M1_PR_R - NEW met1 TAPER ( 201250 164730 ) M1M2_PR_R - NEW met1 ( 201250 177990 ) M1M2_PR_R - NEW li1 TAPER ( 207230 177990 ) L1M1_PR_R - NEW met1 ( 192050 177990 ) M1M2_PR_R NEW li1 TAPER ( 192050 153850 ) L1M1_PR_R NEW met1 TAPER ( 192050 153850 ) M1M2_PR_R - NEW met1 ( 192050 164730 ) M1M2_PR_R - NEW met1 ( 165830 175610 ) M1M2_PR_R - NEW li1 TAPER ( 173190 175610 ) L1M1_PR_R - NEW li1 TAPER ( 170430 170510 ) L1M1_PR_R - NEW met1 TAPER ( 170430 170510 ) M1M2_PR_R - NEW met1 ( 170430 175610 ) M1M2_PR_R - NEW met1 ( 177330 164730 ) M1M2_PR_R - NEW met1 ( 177330 170510 ) M1M2_PR_R NEW li1 TAPER ( 154790 177990 ) L1M1_PR_R + NEW li1 TAPER ( 201250 164390 ) L1M1_PR_R + NEW met1 TAPER ( 201250 164390 ) M1M2_PR_R + NEW met1 ( 201250 178330 ) M1M2_PR_R + NEW li1 TAPER ( 207230 178330 ) L1M1_PR_R NEW li1 TAPER ( 163990 210630 ) L1M1_PR_R NEW met1 TAPER ( 163990 210630 ) M1M2_PR_R - NEW met1 ( 192050 194310 ) M1M2_PR_R - NEW met1 TAPER ( 192050 191930 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 201250 164730 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 192050 153850 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 170430 170510 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 170430 175610 ) RECT ( -490 -70 0 70 ) - NEW met1 TAPER ( 163990 210630 ) RECT ( -355 -70 0 70 ) ; + NEW met1 ( 192050 194310 ) M1M2_PR_R ; - ctrl.state.out\[1\] ( _412_ Q ) ( _290_ B2 ) ( _285_ A ) + USE SIGNAL + ROUTED met1 ( 167670 208250 ) ( 170890 * ) NEW met2 ( 170890 208250 ) ( * 209950 ) @@ -517,12 +484,12 @@ NETS 8 ; NEW met2 ( 158470 191590 ) ( * 194650 ) NEW met2 ( 158470 200430 ) ( * 207570 ) NEW met1 ( 158470 194650 ) ( 167210 * ) - NEW li1 ( 167210 194650 ) L1M1_PR_MR NEW met1 ( 158470 207570 ) M1M2_PR NEW li1 ( 158470 209950 ) L1M1_PR_MR NEW met1 ( 158470 209950 ) M1M2_PR NEW li1 ( 158010 213350 ) L1M1_PR_MR NEW met1 ( 158470 213350 ) M1M2_PR + NEW li1 ( 167210 194650 ) L1M1_PR_MR NEW li1 ( 166290 207570 ) L1M1_PR_MR NEW li1 ( 158010 200090 ) L1M1_PR_MR NEW met1 ( 158470 200430 ) M1M2_PR diff --git a/src/drt/test/ndr_vias2.defok b/src/drt/test/ndr_vias2.defok index d0c7e13125..24f293267d 100644 --- a/src/drt/test/ndr_vias2.defok +++ b/src/drt/test/ndr_vias2.defok @@ -220,64 +220,68 @@ NETS 8 ; + ROUTED met2 ( 89470 340 0 ) ( * 18700 210 ) NEW met3 ( 89470 18700 450 ) ( 89700 * 450 ) NEW met5 ( 89700 18700 2400 ) ( 151340 * 2400 ) - NEW met4 ( 149500 82800 450 ) ( 151340 * 450 ) - NEW met4 ( 151340 18700 450 ) ( * 82800 450 ) - NEW met3 ( 149500 145180 450 ) ( 151110 * 450 ) + NEW met3 ( 151110 145180 450 ) ( 151340 * 450 ) NEW met2 ( 151110 145180 210 ) ( * 151130 210 ) - NEW met4 ( 149500 82800 450 ) ( * 145180 450 ) + NEW met4 ( 151340 18700 450 ) ( * 145180 450 ) NEW met2 ( 89470 18700 ) M2M3_PR_R NEW met3 ( 89700 18700 ) M3M4_PR_R NEW met4 ( 89700 18700 ) M4M5_PR_R NEW met4 ( 151340 18700 ) M4M5_PR_R - NEW met3 ( 149500 145180 ) M3M4_PR_R + NEW met3 ( 151340 145180 ) M3M4_PR_R NEW met2 ( 151110 145180 ) M2M3_PR_R NEW li1 TAPER ( 151110 151130 ) L1M1_PR_R NEW met1 TAPER ( 151110 151130 ) M1M2_PR_R - NEW met3 TAPER ( 89470 18700 ) RECT ( -445 -150 0 150 ) - NEW met4 TAPER ( 89700 18700 ) RECT ( -150 -600 150 0 ) - NEW met1 TAPER ( 151110 151130 ) RECT ( -355 -70 0 70 ) ; + NEW met3 TAPER ( 89470 18700 ) RECT ( -390 -150 0 150 ) + NEW met3 TAPER ( 151340 145180 ) RECT ( 0 -150 390 150 ) ; - clknet_0_clk ( clkbuf_2_3__f_clk A ) ( clkbuf_2_2__f_clk A ) ( clkbuf_2_1__f_clk A ) ( clkbuf_2_0__f_clk A ) ( clkbuf_0_clk X ) + USE CLOCK + NONDEFAULTRULE NDR_3W_3S - + ROUTED met2 ( 116610 118830 210 ) ( * 120700 210 ) - NEW met2 ( 130870 171700 210 ) ( * 172890 210 ) - NEW met3 ( 116610 120700 450 ) ( 131100 * 450 ) - NEW met3 ( 131100 120700 450 ) ( * 121380 450 ) - NEW met3 ( 131100 121380 450 ) ( 152260 * 450 ) - NEW met4 ( 152260 121380 450 ) ( * 123420 450 ) - NEW met2 ( 169510 169830 210 ) ( * 171700 210 ) + + ROUTED met3 ( 116610 124100 450 ) ( 117300 * 450 ) + NEW met2 ( 116610 118830 210 ) ( * 124100 210 ) + NEW met4 ( 129260 171700 450 ) ( * 172380 450 ) + NEW met3 ( 129260 172380 450 ) ( * 173060 450 ) + NEW met3 ( 129260 173060 450 ) ( 130870 * 450 ) + NEW met2 ( 130870 172890 210 ) ( * 173060 210 ) + NEW met3 ( 154100 124100 450 ) ( 169510 * 450 ) + NEW met2 ( 169510 118830 210 ) ( * 124100 210 ) + NEW met5 ( 117300 124100 2400 ) ( 154100 * 2400 ) + NEW met4 ( 154100 124100 450 ) ( * 131100 450 ) + NEW met1 ( 167210 169830 210 ) ( 167900 * 210 ) + NEW met1 TAPER ( 167900 169830 ) ( 169510 * ) + NEW met2 ( 167210 169830 210 ) ( * 171700 210 ) + NEW met3 ( 166980 171700 450 ) ( 167210 * 450 ) NEW met2 ( 152950 151300 210 ) ( * 151470 210 ) NEW met3 ( 152950 151300 450 ) ( 153180 * 450 ) NEW met4 ( 153180 151300 450 ) ( * 171700 450 ) - NEW met4 ( 152260 151300 450 ) ( 153180 * 450 ) - NEW met3 ( 130870 171700 450 ) ( 169510 * 450 ) - NEW met4 ( 152260 123420 450 ) ( * 151300 450 ) - NEW met2 ( 169510 118830 210 ) ( * 123420 210 ) - NEW met3 ( 152260 123420 450 ) ( 169510 * 450 ) - NEW met2 ( 116610 120700 ) M2M3_PR_R + NEW met4 ( 153180 131100 450 ) ( 154100 * 450 ) + NEW met4 ( 153180 131100 450 ) ( * 151300 450 ) + NEW met5 ( 129260 171700 2400 ) ( 166980 * 2400 ) + NEW met3 ( 117300 124100 ) M3M4_PR_R + NEW met4 ( 117300 124100 ) M4M5_PR_R + NEW met2 ( 116610 124100 ) M2M3_PR_R NEW li1 TAPER ( 116610 118830 ) L1M1_PR_R NEW met1 TAPER ( 116610 118830 ) M1M2_PR_R - NEW met2 ( 130870 171700 ) M2M3_PR_R + NEW met4 ( 129260 171700 ) M4M5_PR_R + NEW met3 ( 129260 172380 ) M3M4_PR_R + NEW met2 ( 130870 173060 ) M2M3_PR_R NEW li1 TAPER ( 130870 172890 ) L1M1_PR_R NEW met1 TAPER ( 130870 172890 ) M1M2_PR_R - NEW met3 ( 152260 123420 ) M3M4_PR_R - NEW met3 ( 152260 121380 ) M3M4_PR_R + NEW met3 ( 154100 124100 ) M3M4_PR_R + NEW met2 ( 169510 124100 ) M2M3_PR_R + NEW li1 TAPER ( 169510 118830 ) L1M1_PR_R + NEW met1 TAPER ( 169510 118830 ) M1M2_PR_R + NEW met4 ( 154100 124100 ) M4M5_PR_R NEW li1 TAPER ( 169510 169830 ) L1M1_PR_R - NEW met1 TAPER ( 169510 169830 ) M1M2_PR_R - NEW met2 ( 169510 171700 ) M2M3_PR_R + NEW met1 ( 167210 169830 ) M1M2_PR_R + NEW met2 ( 167210 171700 ) M2M3_PR_R + NEW met3 ( 166980 171700 ) M3M4_PR_R + NEW met4 ( 166980 171700 ) M4M5_PR_R NEW li1 TAPER ( 152950 151470 ) L1M1_PR_R NEW met1 TAPER ( 152950 151470 ) M1M2_PR_R NEW met2 ( 152950 151300 ) M2M3_PR_R NEW met3 ( 153180 151300 ) M3M4_PR_R - NEW met3 ( 153180 171700 ) M3M4_PR_R - NEW li1 TAPER ( 169510 118830 ) L1M1_PR_R - NEW met1 TAPER ( 169510 118830 ) M1M2_PR_R - NEW met2 ( 169510 123420 ) M2M3_PR_R - NEW met1 TAPER ( 116610 118830 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 130870 172890 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 169510 169830 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 152950 151470 ) RECT ( -355 -70 0 70 ) - NEW met3 TAPER ( 152950 151300 ) RECT ( -445 -150 0 150 ) - NEW met3 TAPER ( 153180 171700 ) RECT ( -630 -150 0 150 ) - NEW met1 TAPER ( 169510 118830 ) RECT ( -355 -70 0 70 ) ; + NEW met4 ( 153180 171700 ) M4M5_PR_R + NEW met3 TAPER ( 167210 171700 ) RECT ( 0 -150 390 150 ) + NEW met3 TAPER ( 152950 151300 ) RECT ( -390 -150 0 150 ) + NEW met5 TAPER ( 153180 171700 ) RECT ( -1870 -800 0 800 ) ; - clknet_2_0__leaf_clk ( _414_ CLK ) ( _418_ CLK ) ( _428_ CLK ) ( _429_ CLK ) ( _432_ CLK ) ( _434_ CLK ) ( _444_ CLK ) ( _445_ CLK ) ( clkbuf_2_0__f_clk X ) + USE CLOCK + NONDEFAULTRULE NDR_3W_3S + ROUTED met1 ( 90390 120870 210 ) ( 91540 * 210 ) @@ -288,27 +292,26 @@ NETS 8 ; NEW met2 ( 111090 120700 210 ) ( * 120870 210 ) NEW met3 ( 93150 120700 450 ) ( 111090 * 450 ) NEW met2 ( 93150 120700 210 ) ( * 120870 210 ) - NEW met1 TAPER ( 115690 118150 ) ( 117990 * ) - NEW met1 TAPER ( 115690 118150 ) ( * 118490 ) - NEW met1 ( 111090 118490 210 ) ( 115460 * 210 ) - NEW met1 TAPER ( 115460 118490 ) ( 115690 * ) - NEW met2 ( 111090 118490 210 ) ( * 120700 210 ) + NEW met1 ( 111090 118150 210 ) ( 115460 * 210 ) + NEW met1 TAPER ( 115460 118150 ) ( 117990 * ) + NEW met2 ( 111090 118150 210 ) ( * 120700 210 ) NEW met2 ( 125350 118150 210 ) ( * 120870 210 ) NEW met1 TAPER ( 117990 118150 ) ( 120060 * ) NEW met1 ( 120060 118150 210 ) ( 125350 * 210 ) + NEW met2 ( 125350 117300 210 ) ( * 118150 210 ) NEW met2 ( 111090 120870 210 ) ( * 134470 210 ) - NEW met2 ( 131790 117300 210 ) ( * 118150 210 ) - NEW met3 ( 131790 117300 450 ) ( 144900 * 450 ) - NEW met4 ( 144900 89420 450 ) ( * 117300 450 ) + NEW met2 ( 143750 113220 210 ) ( * 115430 210 ) + NEW met2 ( 143750 113220 210 ) ( 144670 * 210 ) + NEW met3 ( 144670 113220 450 ) ( 144900 * 450 ) + NEW met4 ( 144900 90100 450 ) ( * 113220 450 ) + NEW met3 ( 144900 89420 450 ) ( * 90100 450 ) NEW met3 ( 144900 89420 450 ) ( 146510 * 450 ) NEW met2 ( 146510 88570 210 ) ( * 89420 210 ) NEW met2 ( 143750 115430 210 ) ( * 117300 210 ) - NEW met1 ( 125350 118150 210 ) ( 131790 * 210 ) - NEW met4 ( 137540 117300 450 ) ( * 131100 450 ) - NEW met4 ( 136620 131100 450 ) ( 137540 * 450 ) - NEW met4 ( 136620 131100 450 ) ( * 145180 450 ) - NEW met3 ( 136620 145180 450 ) ( 136850 * 450 ) + NEW met3 ( 125350 117300 450 ) ( 143750 * 450 ) + NEW met3 ( 136850 145180 450 ) ( 137540 * 450 ) NEW met2 ( 136850 145180 210 ) ( * 148070 210 ) + NEW met4 ( 137540 117300 450 ) ( * 145180 450 ) NEW li1 TAPER ( 93150 120870 ) L1M1_PR_R NEW met1 ( 90390 120870 ) M1M2_PR_R NEW li1 TAPER ( 89470 104890 ) L1M1_PR_R @@ -319,166 +322,171 @@ NETS 8 ; NEW met2 ( 93150 120700 ) M2M3_PR_R NEW met1 TAPER ( 93150 120870 ) M1M2_PR_R NEW li1 TAPER ( 117990 118150 ) L1M1_PR_R - NEW met1 ( 111090 118490 ) M1M2_PR_R + NEW met1 ( 111090 118150 ) M1M2_PR_R NEW li1 TAPER ( 125350 120870 ) L1M1_PR_R NEW met1 TAPER ( 125350 120870 ) M1M2_PR_R NEW met1 ( 125350 118150 ) M1M2_PR_R + NEW met2 ( 125350 117300 ) M2M3_PR_R NEW li1 TAPER ( 111090 134470 ) L1M1_PR_R NEW met1 TAPER ( 111090 134470 ) M1M2_PR_R - NEW met1 ( 131790 118150 ) M1M2_PR_R - NEW met2 ( 131790 117300 ) M2M3_PR_R - NEW met3 ( 144900 117300 ) M3M4_PR_R - NEW met3 ( 144900 89420 ) M3M4_PR_R + NEW li1 TAPER ( 143750 115430 ) L1M1_PR_R + NEW met1 TAPER ( 143750 115430 ) M1M2_PR_R + NEW met2 ( 144670 113220 ) M2M3_PR_R + NEW met3 ( 144900 113220 ) M3M4_PR_R + NEW met3 ( 144900 90100 ) M3M4_PR_R NEW met2 ( 146510 89420 ) M2M3_PR_R NEW li1 TAPER ( 146510 88570 ) L1M1_PR_R NEW met1 TAPER ( 146510 88570 ) M1M2_PR_R - NEW li1 TAPER ( 143750 115430 ) L1M1_PR_R - NEW met1 TAPER ( 143750 115430 ) M1M2_PR_R NEW met2 ( 143750 117300 ) M2M3_PR_R NEW met3 ( 137540 117300 ) M3M4_PR_R - NEW met3 ( 136620 145180 ) M3M4_PR_R + NEW met3 ( 137540 145180 ) M3M4_PR_R NEW met2 ( 136850 145180 ) M2M3_PR_R NEW li1 TAPER ( 136850 148070 ) L1M1_PR_R NEW met1 TAPER ( 136850 148070 ) M1M2_PR_R - NEW met1 TAPER ( 89470 104890 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 111090 120870 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 93150 120870 ) RECT ( -490 -70 0 70 ) - NEW met1 TAPER ( 125350 120870 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 111090 134470 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 146510 88570 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 143750 115430 ) RECT ( -355 -70 0 70 ) - NEW met3 TAPER ( 143750 117300 ) RECT ( -705 -150 0 150 ) - NEW met3 TAPER ( 137540 117300 ) RECT ( -630 -150 0 150 ) - NEW met3 TAPER ( 136620 145180 ) RECT ( -435 -150 0 150 ) - NEW met1 TAPER ( 136850 148070 ) RECT ( -355 -70 0 70 ) ; + NEW met3 TAPER ( 144670 113220 ) RECT ( -390 -150 0 150 ) + NEW met3 TAPER ( 137540 117300 ) RECT ( -600 -150 0 150 ) ; - clknet_2_1__leaf_clk ( _423_ CLK ) ( _424_ CLK ) ( _425_ CLK ) ( _426_ CLK ) ( _427_ CLK ) ( _440_ CLK ) ( _441_ CLK ) ( _442_ CLK ) ( _443_ CLK ) ( clkbuf_2_1__f_clk X ) + USE CLOCK + NONDEFAULTRULE NDR_3W_3S - + ROUTED met2 ( 156170 124270 210 ) ( * 129030 210 ) - NEW met3 ( 155940 129540 450 ) ( 156170 * 450 ) - NEW met2 ( 156170 129030 210 ) ( * 129540 210 ) - NEW met2 ( 158010 101660 210 ) ( * 101830 210 ) - NEW met3 ( 155940 101660 450 ) ( 158010 * 450 ) - NEW met4 ( 155940 101660 450 ) ( * 129540 450 ) - NEW met1 ( 158010 88570 210 ) ( 162610 * 210 ) - NEW met1 TAPER ( 162610 88570 ) ( 164450 * ) - NEW met2 ( 158010 88570 210 ) ( * 101660 210 ) - NEW met1 ( 164450 91290 210 ) ( 177100 * 210 ) - NEW met1 TAPER ( 177100 91290 ) ( 178710 * ) - NEW met2 ( 164450 88570 210 ) ( * 91290 210 ) - NEW met3 ( 152950 147900 450 ) ( 155940 * 450 ) - NEW met2 ( 152950 147900 210 ) ( * 148070 210 ) - NEW met4 ( 155940 129540 450 ) ( * 147900 450 ) - NEW met1 ( 165830 117810 210 ) ( 168130 * 210 ) - NEW met1 TAPER ( 168130 117810 ) ( 170430 * ) - NEW met2 ( 165830 117810 210 ) ( * 124270 210 ) - NEW met1 ( 200330 113050 210 ) ( 204700 * 210 ) - NEW met1 TAPER ( 204700 113050 ) ( 206310 * ) - NEW met2 ( 200330 113050 210 ) ( * 117810 210 ) - NEW met1 TAPER ( 170430 117810 ) ( 173190 * ) - NEW met1 ( 173190 117810 210 ) ( 200330 * 210 ) - NEW met2 ( 199410 137020 210 ) ( * 137190 210 ) - NEW met2 ( 199410 137020 210 ) ( 199870 * 210 ) - NEW met2 ( 199870 130900 210 ) ( * 137020 210 ) - NEW met2 ( 199870 130900 210 ) ( 200330 * 210 ) - NEW met2 ( 200330 117810 210 ) ( * 130900 210 ) + + ROUTED met3 ( 200100 124780 450 ) ( 200330 * 450 ) + NEW met4 ( 200100 117300 450 ) ( * 124780 450 ) NEW met1 ( 200330 129030 210 ) ( 204700 * 210 ) NEW met1 TAPER ( 204700 129030 ) ( 206310 * ) + NEW met2 ( 206310 113050 210 ) ( * 117300 210 ) + NEW met3 ( 200100 117300 450 ) ( 206310 * 450 ) + NEW met2 ( 205850 96730 210 ) ( * 110500 210 ) + NEW met2 ( 205850 110500 210 ) ( 206310 * 210 ) + NEW met2 ( 206310 110500 210 ) ( * 113050 210 ) + NEW met2 ( 200330 124780 210 ) ( * 131100 210 ) + NEW met2 ( 199410 131100 210 ) ( 200330 * 210 ) + NEW met2 ( 199410 131100 210 ) ( * 137190 210 ) + NEW met2 ( 171350 117300 210 ) ( * 118490 210 ) + NEW met3 ( 171350 117300 450 ) ( 171580 * 450 ) + NEW met2 ( 156170 124270 210 ) ( * 129370 210 ) NEW met1 ( 156170 124270 210 ) ( 165830 * 210 ) - NEW met2 ( 205850 96390 210 ) ( * 113050 210 ) - NEW li1 TAPER ( 205850 96390 ) L1M1_PR_R - NEW met1 TAPER ( 205850 96390 ) M1M2_PR_R - NEW li1 TAPER ( 156170 129030 ) L1M1_PR_R - NEW met1 TAPER ( 156170 129030 ) M1M2_PR_R + NEW met1 ( 165830 123930 210 ) ( * 124270 210 ) + NEW met1 ( 165830 123930 210 ) ( 171350 * 210 ) + NEW met2 ( 171350 118490 210 ) ( * 123930 210 ) + NEW met3 ( 155940 129540 450 ) ( 156170 * 450 ) + NEW met2 ( 156170 129370 210 ) ( * 129540 210 ) + NEW met1 TAPER ( 157090 101830 ) ( 158010 * ) + NEW met2 ( 157090 101660 210 ) ( * 101830 210 ) + NEW met3 ( 156860 101660 450 ) ( 157090 * 450 ) + NEW met4 ( 156860 101660 450 ) ( * 127500 450 ) + NEW met4 ( 155940 127500 450 ) ( 156860 * 450 ) + NEW met4 ( 155940 127500 450 ) ( * 129540 450 ) + NEW met2 ( 178710 91290 210 ) ( * 91460 210 ) + NEW met3 ( 172500 91460 450 ) ( 178710 * 450 ) + NEW met4 ( 172500 91460 450 ) ( * 117300 450 ) + NEW met4 ( 171580 117300 450 ) ( 172500 * 450 ) + NEW met2 ( 164450 88230 210 ) ( * 89420 210 ) + NEW met3 ( 164450 89420 450 ) ( 172500 * 450 ) + NEW met3 ( 172500 89420 450 ) ( * 91460 450 ) + NEW met5 ( 171580 117300 2400 ) ( 200100 * 2400 ) + NEW met3 ( 152950 147220 450 ) ( 155940 * 450 ) + NEW met2 ( 152950 147220 210 ) ( * 148070 210 ) + NEW met4 ( 155940 129540 450 ) ( * 147220 450 ) + NEW met2 ( 200330 124780 ) M2M3_PR_R + NEW met3 ( 200100 124780 ) M3M4_PR_R + NEW met4 ( 200100 117300 ) M4M5_PR_R + NEW li1 TAPER ( 206310 129030 ) L1M1_PR_R + NEW met1 ( 200330 129030 ) M1M2_PR_R + NEW li1 TAPER ( 206310 113050 ) L1M1_PR_R + NEW met1 TAPER ( 206310 113050 ) M1M2_PR_R + NEW met2 ( 206310 117300 ) M2M3_PR_R + NEW met3 ( 200100 117300 ) M3M4_PR_R + NEW li1 TAPER ( 205850 96730 ) L1M1_PR_R + NEW met1 TAPER ( 205850 96730 ) M1M2_PR_R + NEW li1 TAPER ( 199410 137190 ) L1M1_PR_R + NEW met1 TAPER ( 199410 137190 ) M1M2_PR_R + NEW li1 TAPER ( 171350 118490 ) L1M1_PR_R + NEW met1 TAPER ( 171350 118490 ) M1M2_PR_R + NEW met2 ( 171350 117300 ) M2M3_PR_R + NEW met3 ( 171580 117300 ) M3M4_PR_R + NEW met4 ( 171580 117300 ) M4M5_PR_R + NEW li1 TAPER ( 156170 129370 ) L1M1_PR_R + NEW met1 TAPER ( 156170 129370 ) M1M2_PR_R NEW met1 ( 156170 124270 ) M1M2_PR_R + NEW met1 ( 171350 123930 ) M1M2_PR_R NEW met3 ( 155940 129540 ) M3M4_PR_R NEW met2 ( 156170 129540 ) M2M3_PR_R NEW li1 TAPER ( 158010 101830 ) L1M1_PR_R - NEW met1 TAPER ( 158010 101830 ) M1M2_PR_R - NEW met2 ( 158010 101660 ) M2M3_PR_R - NEW met3 ( 155940 101660 ) M3M4_PR_R - NEW li1 TAPER ( 164450 88570 ) L1M1_PR_R - NEW met1 ( 158010 88570 ) M1M2_PR_R + NEW met1 TAPER ( 157090 101830 ) M1M2_PR_R + NEW met2 ( 157090 101660 ) M2M3_PR_R + NEW met3 ( 156860 101660 ) M3M4_PR_R NEW li1 TAPER ( 178710 91290 ) L1M1_PR_R - NEW met1 ( 164450 91290 ) M1M2_PR_R - NEW met1 TAPER ( 164450 88570 ) M1M2_PR_R - NEW met3 ( 155940 147900 ) M3M4_PR_R - NEW met2 ( 152950 147900 ) M2M3_PR_R + NEW met1 TAPER ( 178710 91290 ) M1M2_PR_R + NEW met2 ( 178710 91460 ) M2M3_PR_R + NEW met3 ( 172500 91460 ) M3M4_PR_R + NEW li1 TAPER ( 164450 88230 ) L1M1_PR_R + NEW met1 TAPER ( 164450 88230 ) M1M2_PR_R + NEW met2 ( 164450 89420 ) M2M3_PR_R + NEW met3 ( 155940 147220 ) M3M4_PR_R + NEW met2 ( 152950 147220 ) M2M3_PR_R NEW li1 TAPER ( 152950 148070 ) L1M1_PR_R NEW met1 TAPER ( 152950 148070 ) M1M2_PR_R - NEW li1 TAPER ( 170430 117810 ) L1M1_PR_R - NEW met1 ( 165830 117810 ) M1M2_PR_R - NEW met1 ( 165830 124270 ) M1M2_PR_R - NEW li1 TAPER ( 206310 113050 ) L1M1_PR_R - NEW met1 ( 200330 113050 ) M1M2_PR_R - NEW met1 ( 200330 117810 ) M1M2_PR_R - NEW met1 TAPER ( 205850 113050 ) M1M2_PR_R - NEW li1 TAPER ( 199410 137190 ) L1M1_PR_R - NEW met1 TAPER ( 199410 137190 ) M1M2_PR_R - NEW li1 TAPER ( 206310 129030 ) L1M1_PR_R - NEW met1 ( 200330 129030 ) M1M2_PR_R - NEW met1 TAPER ( 205850 96390 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 156170 129030 ) RECT ( -355 -70 0 70 ) - NEW met3 TAPER ( 155940 129540 ) RECT ( -435 -150 0 150 ) - NEW met1 TAPER ( 158010 101830 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 164450 88570 ) RECT ( -490 -70 0 70 ) - NEW met1 TAPER ( 152950 148070 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 205850 113050 ) RECT ( -490 -70 0 70 ) - NEW met1 TAPER ( 199410 137190 ) RECT ( -355 -70 0 70 ) - NEW met2 TAPER ( 200330 129030 ) RECT ( -70 -305 70 0 ) ; + NEW met3 TAPER ( 200330 124780 ) RECT ( 0 -150 390 150 ) + NEW met4 TAPER ( 200100 117300 ) RECT ( -150 -620 150 0 ) + NEW met3 TAPER ( 171350 117300 ) RECT ( -390 -150 0 150 ) + NEW met3 TAPER ( 155940 129540 ) RECT ( -390 -150 0 150 ) + NEW met3 TAPER ( 157090 101660 ) RECT ( 0 -150 390 150 ) ; - clknet_2_2__leaf_clk ( _411_ CLK ) ( _413_ CLK ) ( _415_ CLK ) ( _416_ CLK ) ( _417_ CLK ) ( _421_ CLK ) ( _430_ CLK ) ( _431_ CLK ) ( _433_ CLK ) ( _437_ CLK ) ( clkbuf_2_2__f_clk X ) + USE CLOCK + NONDEFAULTRULE NDR_3W_3S - + ROUTED met2 ( 126270 199580 210 ) ( * 199750 210 ) - NEW met3 ( 126270 199580 450 ) ( 130180 * 450 ) - NEW met4 ( 130180 199580 450 ) ( * 212500 450 ) - NEW met2 ( 111550 199580 210 ) ( * 199750 210 ) - NEW met3 ( 111550 199580 450 ) ( 126270 * 450 ) - NEW met2 ( 130410 179690 210 ) ( * 179860 210 ) - NEW met3 ( 130180 179860 450 ) ( 130410 * 450 ) - NEW met4 ( 130180 179860 450 ) ( * 199580 450 ) - NEW met2 ( 125810 179690 210 ) ( * 183430 210 ) - NEW met1 ( 125810 179690 210 ) ( 130410 * 210 ) - NEW met2 ( 96830 185980 210 ) ( * 186150 210 ) - NEW met3 ( 96830 185980 450 ) ( 111550 * 450 ) - NEW met2 ( 111550 185980 210 ) ( * 199580 210 ) - NEW met2 ( 109250 183770 210 ) ( * 185980 210 ) + + ROUTED met2 ( 125810 183770 210 ) ( * 183940 210 ) + NEW met3 ( 125810 183940 450 ) ( 130180 * 450 ) + NEW met4 ( 130180 183940 450 ) ( * 212500 450 ) + NEW met2 ( 130870 179690 210 ) ( * 183940 210 ) + NEW met3 ( 130180 183940 450 ) ( 130870 * 450 ) + NEW met1 TAPER ( 125810 199750 ) ( 126270 * ) + NEW met2 ( 125810 199580 210 ) ( * 199750 210 ) + NEW met3 ( 125810 199580 450 ) ( 130180 * 450 ) + NEW met2 ( 109250 183770 210 ) ( * 183940 210 ) + NEW met3 ( 109250 183940 450 ) ( 125810 * 450 ) + NEW met2 ( 96830 183770 210 ) ( * 186150 210 ) + NEW met1 ( 96830 183770 210 ) ( 107410 * 210 ) + NEW met1 TAPER ( 107410 183770 ) ( 109250 * ) + NEW met3 ( 96830 180540 450 ) ( 97060 * 450 ) + NEW met2 ( 96830 180540 210 ) ( * 183770 210 ) + NEW met1 TAPER ( 111090 199750 ) ( 111550 * ) + NEW met2 ( 111090 199580 210 ) ( * 199750 210 ) + NEW met3 ( 111090 199580 450 ) ( 125810 * 450 ) NEW met3 ( 97060 151300 450 ) ( 100050 * 450 ) NEW met2 ( 100050 151130 210 ) ( * 151300 210 ) - NEW met4 ( 97060 151300 450 ) ( * 185980 450 ) - NEW met1 ( 130410 179690 210 ) ( 131100 * 210 ) + NEW met4 ( 97060 151300 450 ) ( * 180540 450 ) NEW met2 ( 137770 210970 210 ) ( * 212500 210 ) NEW met2 ( 150650 210970 210 ) ( * 212500 210 ) NEW met3 ( 137770 212500 450 ) ( 150650 * 450 ) + NEW met1 ( 130870 179690 210 ) ( 131330 * 210 ) NEW met3 ( 130180 212500 450 ) ( 137770 * 450 ) NEW met2 ( 140990 159290 210 ) ( * 175270 210 ) NEW met1 ( 140990 159290 210 ) ( 142140 * 210 ) NEW met1 TAPER ( 142140 159290 ) ( 143750 * ) NEW met1 TAPER ( 132710 172890 ) ( 134550 * ) NEW met1 ( 134550 172890 210 ) ( 140990 * 210 ) - NEW met1 ( 131100 179350 210 ) ( 132710 * 210 ) + NEW met1 ( 131330 179350 210 ) ( 132710 * 210 ) NEW met2 ( 132710 172890 210 ) ( * 179350 210 ) - NEW met1 ( 131100 179350 210 ) ( * 179690 210 ) + NEW met1 ( 131330 179350 210 ) ( * 179690 210 ) + NEW li1 TAPER ( 125810 183770 ) L1M1_PR_R + NEW met1 TAPER ( 125810 183770 ) M1M2_PR_R + NEW met2 ( 125810 183940 ) M2M3_PR_R + NEW met3 ( 130180 183940 ) M3M4_PR_R + NEW met3 ( 130180 212500 ) M3M4_PR_R + NEW met1 ( 130870 179690 ) M1M2_PR_R + NEW met2 ( 130870 183940 ) M2M3_PR_R NEW li1 TAPER ( 126270 199750 ) L1M1_PR_R - NEW met1 TAPER ( 126270 199750 ) M1M2_PR_R - NEW met2 ( 126270 199580 ) M2M3_PR_R + NEW met1 TAPER ( 125810 199750 ) M1M2_PR_R + NEW met2 ( 125810 199580 ) M2M3_PR_R NEW met3 ( 130180 199580 ) M3M4_PR_R - NEW met3 ( 130180 212500 ) M3M4_PR_R - NEW li1 TAPER ( 111550 199750 ) L1M1_PR_R - NEW met1 TAPER ( 111550 199750 ) M1M2_PR_R - NEW met2 ( 111550 199580 ) M2M3_PR_R - NEW met1 ( 130410 179690 ) M1M2_PR_R - NEW met2 ( 130410 179860 ) M2M3_PR_R - NEW met3 ( 130180 179860 ) M3M4_PR_R - NEW li1 TAPER ( 125810 183430 ) L1M1_PR_R - NEW met1 TAPER ( 125810 183430 ) M1M2_PR_R - NEW met1 ( 125810 179690 ) M1M2_PR_R - NEW li1 TAPER ( 96830 186150 ) L1M1_PR_R - NEW met1 TAPER ( 96830 186150 ) M1M2_PR_R - NEW met2 ( 96830 185980 ) M2M3_PR_R - NEW met2 ( 111550 185980 ) M2M3_PR_R NEW li1 TAPER ( 109250 183770 ) L1M1_PR_R NEW met1 TAPER ( 109250 183770 ) M1M2_PR_R - NEW met2 ( 109250 185980 ) M2M3_PR_R - NEW met3 ( 97060 185980 ) M3M4_PR_R + NEW met2 ( 109250 183940 ) M2M3_PR_R + NEW li1 TAPER ( 96830 186150 ) L1M1_PR_R + NEW met1 TAPER ( 96830 186150 ) M1M2_PR_R + NEW met1 ( 96830 183770 ) M1M2_PR_R + NEW met3 ( 97060 180540 ) M3M4_PR_R + NEW met2 ( 96830 180540 ) M2M3_PR_R + NEW li1 TAPER ( 111550 199750 ) L1M1_PR_R + NEW met1 TAPER ( 111090 199750 ) M1M2_PR_R + NEW met2 ( 111090 199580 ) M2M3_PR_R NEW met3 ( 97060 151300 ) M3M4_PR_R NEW met2 ( 100050 151300 ) M2M3_PR_R NEW li1 TAPER ( 100050 151130 ) L1M1_PR_R @@ -497,73 +505,59 @@ NETS 8 ; NEW met1 ( 140990 172890 ) M1M2_PR_R NEW met1 ( 132710 179350 ) M1M2_PR_R NEW met1 TAPER ( 132710 172890 ) M1M2_PR_R - NEW met1 TAPER ( 126270 199750 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 111550 199750 ) RECT ( -355 -70 0 70 ) - NEW met3 TAPER ( 130410 179860 ) RECT ( 0 -150 445 150 ) - NEW met1 TAPER ( 125810 183430 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 96830 186150 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 109250 183770 ) RECT ( -355 -70 0 70 ) - NEW met3 TAPER ( 109250 185980 ) RECT ( -705 -150 0 150 ) - NEW met3 TAPER ( 97060 185980 ) RECT ( -630 -150 0 150 ) - NEW met1 TAPER ( 100050 151130 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 137770 210970 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 150650 210970 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 140990 175270 ) RECT ( -355 -70 0 70 ) - NEW met2 TAPER ( 140990 172890 ) RECT ( -70 -305 70 0 ) - NEW met1 TAPER ( 132710 172890 ) RECT ( -490 -70 0 70 ) ; + NEW met4 TAPER ( 130180 199580 ) RECT ( -150 -620 150 0 ) + NEW met3 TAPER ( 97060 180540 ) RECT ( 0 -150 390 150 ) ; - clknet_2_3__leaf_clk ( _412_ CLK ) ( _419_ CLK ) ( _420_ CLK ) ( _422_ CLK ) ( _435_ CLK ) ( _436_ CLK ) ( _438_ CLK ) ( _439_ CLK ) ( clkbuf_2_3__f_clk X ) + USE CLOCK + NONDEFAULTRULE NDR_3W_3S - + ROUTED met1 TAPER ( 191130 191590 ) ( 192050 * ) - NEW met2 ( 191130 191420 210 ) ( * 191590 210 ) - NEW met3 ( 191130 191420 450 ) ( 192740 * 450 ) + + ROUTED met1 TAPER ( 190670 191590 ) ( 192050 * ) + NEW met2 ( 190670 191420 210 ) ( * 191590 210 ) + NEW met3 ( 190670 191420 450 ) ( 192740 * 450 ) NEW met1 ( 192970 194310 210 ) ( 204010 * 210 ) NEW met1 TAPER ( 204010 194310 ) ( 205850 * ) NEW met2 ( 192970 191420 210 ) ( * 194310 210 ) NEW met3 ( 192740 191420 450 ) ( 192970 * 450 ) - NEW met2 ( 201250 164730 210 ) ( * 165580 210 ) - NEW met3 ( 201250 165580 450 ) ( 207230 * 450 ) + NEW met2 ( 201250 164390 210 ) ( * 165580 210 ) + NEW met3 ( 201250 165580 450 ) ( 206310 * 450 ) + NEW met2 ( 206310 165580 210 ) ( 207230 * 210 ) NEW met2 ( 207230 165580 210 ) ( * 177990 210 ) - NEW met3 ( 192740 179180 450 ) ( 207230 * 450 ) - NEW met2 ( 207230 177990 210 ) ( * 179180 210 ) - NEW met1 ( 193430 158950 210 ) ( 201250 * 210 ) - NEW met2 ( 201250 158950 210 ) ( * 164730 210 ) - NEW met4 ( 192740 179180 450 ) ( * 191420 450 ) + NEW met3 ( 192740 165580 450 ) ( 201250 * 450 ) + NEW met1 TAPER ( 190670 153850 ) ( 192050 * ) + NEW met2 ( 190670 153850 210 ) ( * 154020 210 ) + NEW met3 ( 190670 154020 450 ) ( 192740 * 450 ) + NEW met4 ( 192740 154020 450 ) ( * 165580 450 ) + NEW met4 ( 192740 165580 450 ) ( * 191420 450 ) NEW met3 ( 163990 207060 450 ) ( 164220 * 450 ) NEW met2 ( 163990 207060 210 ) ( * 210630 210 ) NEW met3 ( 154790 178500 450 ) ( 164220 * 450 ) NEW met2 ( 154790 178330 210 ) ( * 178500 210 ) - NEW met2 ( 173190 175610 210 ) ( * 178500 210 ) + NEW met2 ( 173190 175270 210 ) ( * 178500 210 ) NEW met3 ( 164220 178500 450 ) ( 173190 * 450 ) - NEW met2 ( 171350 169830 210 ) ( * 175610 210 ) - NEW met1 ( 171350 175610 210 ) ( 171580 * 210 ) - NEW met1 TAPER ( 171580 175610 ) ( 173190 * ) - NEW met2 ( 171350 166260 210 ) ( * 169830 210 ) + NEW met1 TAPER ( 170890 170170 ) ( 171810 * ) + NEW met2 ( 171810 170170 210 ) ( * 174420 210 ) + NEW met2 ( 171810 174420 210 ) ( 173190 * 210 ) + NEW met2 ( 173190 174420 210 ) ( * 175270 210 ) + NEW met2 ( 171810 168980 210 ) ( * 170170 210 ) NEW met4 ( 164220 178500 450 ) ( * 207060 450 ) - NEW met3 ( 171350 166260 450 ) ( 186300 * 450 ) - NEW met1 ( 192970 158610 210 ) ( 193430 * 210 ) - NEW met1 ( 192970 158270 210 ) ( * 158610 210 ) - NEW met2 ( 192970 158100 210 ) ( * 158270 210 ) - NEW met3 ( 186300 158100 450 ) ( 192970 * 450 ) - NEW met2 ( 192050 153850 210 ) ( * 158100 210 ) - NEW met4 ( 186300 158100 450 ) ( * 166260 450 ) - NEW met1 ( 193430 158610 210 ) ( * 158950 210 ) + NEW met3 ( 171810 168980 450 ) ( 192740 * 450 ) NEW li1 TAPER ( 192050 191590 ) L1M1_PR_R - NEW met1 TAPER ( 191130 191590 ) M1M2_PR_R - NEW met2 ( 191130 191420 ) M2M3_PR_R + NEW met1 TAPER ( 190670 191590 ) M1M2_PR_R + NEW met2 ( 190670 191420 ) M2M3_PR_R NEW met3 ( 192740 191420 ) M3M4_PR_R NEW li1 TAPER ( 205850 194310 ) L1M1_PR_R NEW met1 ( 192970 194310 ) M1M2_PR_R NEW met2 ( 192970 191420 ) M2M3_PR_R - NEW li1 TAPER ( 201250 164730 ) L1M1_PR_R - NEW met1 TAPER ( 201250 164730 ) M1M2_PR_R + NEW li1 TAPER ( 201250 164390 ) L1M1_PR_R + NEW met1 TAPER ( 201250 164390 ) M1M2_PR_R NEW met2 ( 201250 165580 ) M2M3_PR_R - NEW met2 ( 207230 165580 ) M2M3_PR_R + NEW met2 ( 206310 165580 ) M2M3_PR_R NEW li1 TAPER ( 207230 177990 ) L1M1_PR_R NEW met1 TAPER ( 207230 177990 ) M1M2_PR_R - NEW met3 ( 192740 179180 ) M3M4_PR_R - NEW met2 ( 207230 179180 ) M2M3_PR_R - NEW met1 ( 201250 158950 ) M1M2_PR_R - NEW met3 ( 186300 166260 ) M3M4_PR_R + NEW met3 ( 192740 165580 ) M3M4_PR_R + NEW li1 TAPER ( 192050 153850 ) L1M1_PR_R + NEW met1 TAPER ( 190670 153850 ) M1M2_PR_R + NEW met2 ( 190670 154020 ) M2M3_PR_R + NEW met3 ( 192740 154020 ) M3M4_PR_R + NEW met3 ( 192740 168980 ) M3M4_PR_R NEW met3 ( 164220 207060 ) M3M4_PR_R NEW met2 ( 163990 207060 ) M2M3_PR_R NEW li1 TAPER ( 163990 210630 ) L1M1_PR_R @@ -572,29 +566,15 @@ NETS 8 ; NEW met2 ( 154790 178500 ) M2M3_PR_R NEW li1 TAPER ( 154790 178330 ) L1M1_PR_R NEW met1 TAPER ( 154790 178330 ) M1M2_PR_R - NEW li1 TAPER ( 173190 175610 ) L1M1_PR_R - NEW met1 TAPER ( 173190 175610 ) M1M2_PR_R + NEW li1 TAPER ( 173190 175270 ) L1M1_PR_R + NEW met1 TAPER ( 173190 175270 ) M1M2_PR_R NEW met2 ( 173190 178500 ) M2M3_PR_R - NEW li1 TAPER ( 171350 169830 ) L1M1_PR_R - NEW met1 TAPER ( 171350 169830 ) M1M2_PR_R - NEW met1 ( 171350 175610 ) M1M2_PR_R - NEW met2 ( 171350 166260 ) M2M3_PR_R - NEW met1 ( 192970 158270 ) M1M2_PR_R - NEW met2 ( 192970 158100 ) M2M3_PR_R - NEW met3 ( 186300 158100 ) M3M4_PR_R - NEW li1 TAPER ( 192050 153850 ) L1M1_PR_R - NEW met1 TAPER ( 192050 153850 ) M1M2_PR_R - NEW met2 ( 192050 158100 ) M2M3_PR_R - NEW met3 TAPER ( 192970 191420 ) RECT ( 0 -150 615 150 ) - NEW met1 TAPER ( 201250 164730 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 207230 177990 ) RECT ( -355 -70 0 70 ) - NEW met3 TAPER ( 164220 207060 ) RECT ( 0 -150 435 150 ) - NEW met1 TAPER ( 163990 210630 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 154790 178330 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 173190 175610 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 171350 169830 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 192050 153850 ) RECT ( -355 -70 0 70 ) - NEW met3 TAPER ( 192050 158100 ) RECT ( -705 -150 0 150 ) ; + NEW li1 TAPER ( 170890 170170 ) L1M1_PR_R + NEW met1 TAPER ( 171810 170170 ) M1M2_PR_R + NEW met2 ( 171810 168980 ) M2M3_PR_R + NEW met3 TAPER ( 192970 191420 ) RECT ( 0 -150 570 150 ) + NEW met4 TAPER ( 192740 168980 ) RECT ( -150 -620 150 0 ) + NEW met3 TAPER ( 164220 207060 ) RECT ( 0 -150 390 150 ) ; - ctrl.state.out\[1\] ( _412_ Q ) ( _290_ B2 ) ( _285_ A ) + USE SIGNAL + ROUTED met2 ( 170890 205530 ) ( * 209950 ) NEW met1 ( 167670 207910 ) ( 170890 * ) From cb99d097b26a7981e2c175a2b5ec4bf5bbe260ed Mon Sep 17 00:00:00 2001 From: andyfox-rushc Date: Wed, 31 Jul 2024 12:09:03 -0700 Subject: [PATCH 13/37] Comments showing what will be removed for next pull request and can be ignored in this review. Signed-off-by: Andy Fox andy@rushc.com Signed-off-by: andyfox-rushc --- src/dbSta/src/dbNetwork.cc | 5 +++++ src/odb/src/db/dbBusPort.cpp | 9 ++++++--- 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/src/dbSta/src/dbNetwork.cc b/src/dbSta/src/dbNetwork.cc index c7210abc59..39a07d50a8 100644 --- a/src/dbSta/src/dbNetwork.cc +++ b/src/dbSta/src/dbNetwork.cc @@ -718,6 +718,10 @@ dbModulePortIterator::dbModulePortIterator(const dbModule* cell) { // skip to end const dbModBTerm* first_mod_bterm = cell->getHeadDbModBTerm(); + // + // Next pull request remove this. Use reverse on list + // so head is first element in natural order + // for (iter_ = cell->getHeadDbModBTerm(); iter_; iter_ = iter_->getNext()) { first_mod_bterm = iter_; } @@ -746,6 +750,7 @@ Port* dbModulePortIterator::next() int size = bp->getSize(); // content of bus iter_ = iter_->getPrev(); + // Next pull request remove this, use offset mechanism for (int skip_ix = 0; skip_ix < size && (iter_->getPrev()); skip_ix++) { iter_ = iter_->getPrev(); } diff --git a/src/odb/src/db/dbBusPort.cpp b/src/odb/src/db/dbBusPort.cpp index 022c054413..4738211cc1 100644 --- a/src/odb/src/db/dbBusPort.cpp +++ b/src/odb/src/db/dbBusPort.cpp @@ -237,6 +237,10 @@ dbModBTerm* dbBusPort::getBusIndexedElement(int index) const offset = getFrom() - index; } if (offset < getSize()) { + // + // TODO. Future pull request: support for making vector of objects unclean. + // if we cannot count on the order, skip to the dbModBterm + // // the _flags are set to non zero if we cannot // count on the order of the modbterms (eg // if some have been deleted or added in non-linear way). @@ -245,7 +249,6 @@ dbModBTerm* dbBusPort::getBusIndexedElement(int index) const return (dbModBTerm*) (block_->_modbterm_tbl->getPtr(obj->getId() + offset + 1)); } - // if we cannot count on the order, skip to the dbModBterm dbModBTerm* cur = (dbModBTerm*) (block_->_modbterm_tbl->getPtr(obj->_port)); if (cur != nullptr) { cur = cur->getPrev(); @@ -315,8 +318,8 @@ dbBusPort* dbBusPort::create(dbModule* parentModule, } // -// TODO: Reallocate the bus to preserve sequential db ordering -// This to be added as part of "scaffolding functions" +// TODO future pull request: Reallocate the bus to preserve sequential db +// ordering This to be added as part of "scaffolding functions" // void dbBusPort::Realloc() { From 052be6a021f6d3e93bbb05cb8ee6ef89a4b9ccf4 Mon Sep 17 00:00:00 2001 From: andyfox-rushc Date: Wed, 31 Jul 2024 13:17:30 -0700 Subject: [PATCH 14/37] Reformatting to support ctidy response. Signed-off-by: Andy Fox andy@rushc.com Signed-off-by: andyfox-rushc --- src/dbSta/src/dbNetwork.cc | 7 ++----- src/odb/include/odb/db.h | 4 ++-- 2 files changed, 4 insertions(+), 7 deletions(-) diff --git a/src/dbSta/src/dbNetwork.cc b/src/dbSta/src/dbNetwork.cc index 39a07d50a8..9a5e777beb 100644 --- a/src/dbSta/src/dbNetwork.cc +++ b/src/dbSta/src/dbNetwork.cc @@ -705,7 +705,7 @@ class dbModulePortIterator : public CellPortIterator { public: explicit dbModulePortIterator(const dbModule* cell); - ~dbModulePortIterator() override; + ~dbModulePortIterator() = default; virtual bool hasNext() override; virtual Port* next() override; @@ -729,10 +729,6 @@ dbModulePortIterator::dbModulePortIterator(const dbModule* cell) module_ = cell; } -dbModulePortIterator::~dbModulePortIterator() -{ -} - bool dbModulePortIterator::hasNext() { if (iter_) { @@ -2456,6 +2452,7 @@ Port* dbNetwork::findMember(const Port* port, int index) const dbBusPort* busport = modbterm->getBusPort(); modbterm = modbterm->getPrev(); modbterm = busport->getBusIndexedElement(index); + return reinterpret_cast(modbterm); } return nullptr; } diff --git a/src/odb/include/odb/db.h b/src/odb/include/odb/db.h index 2e02ae4707..c96142ffa1 100644 --- a/src/odb/include/odb/db.h +++ b/src/odb/include/odb/db.h @@ -7162,8 +7162,8 @@ class dbBusPort : public dbObject void Realloc(); static dbBusPort* create(dbModule* parentModule, dbModBTerm* root, - int from_index, - int to_index); + int from_ix, + int to_ix); // User Code End dbBusPort }; From fe5098d6c562c996ca26281acd5ea50ffae1ea2c Mon Sep 17 00:00:00 2001 From: andyfox-rushc Date: Wed, 31 Jul 2024 13:43:55 -0700 Subject: [PATCH 15/37] Ctidy clean ups. Signed-off-by: Andy Fox. Signed-off-by: andyfox-rushc --- src/dbSta/src/dbNetwork.cc | 3 +-- src/dbSta/src/dbReadVerilog.cc | 2 ++ src/odb/include/odb/db.h | 2 +- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/dbSta/src/dbNetwork.cc b/src/dbSta/src/dbNetwork.cc index 9a5e777beb..7b72501587 100644 --- a/src/dbSta/src/dbNetwork.cc +++ b/src/dbSta/src/dbNetwork.cc @@ -705,7 +705,7 @@ class dbModulePortIterator : public CellPortIterator { public: explicit dbModulePortIterator(const dbModule* cell); - ~dbModulePortIterator() = default; + ~dbModulePortIterator() override = default; virtual bool hasNext() override; virtual Port* next() override; @@ -2450,7 +2450,6 @@ Port* dbNetwork::findMember(const Port* port, int index) const staToDb(port, bterm, mterm, modbterm); if (modbterm && modbterm->isBusPort()) { dbBusPort* busport = modbterm->getBusPort(); - modbterm = modbterm->getPrev(); modbterm = busport->getBusIndexedElement(index); return reinterpret_cast(modbterm); } diff --git a/src/dbSta/src/dbReadVerilog.cc b/src/dbSta/src/dbReadVerilog.cc index 9462e16d9a..b29cd0e56e 100644 --- a/src/dbSta/src/dbReadVerilog.cc +++ b/src/dbSta/src/dbReadVerilog.cc @@ -428,6 +428,8 @@ void Verilog2db::makeDbModule( "Created module iterm {} ", moditerm->getName()); } + // reverse the ports on the dbModule to natural order + module->getModBTerms().reverse(); } } diff --git a/src/odb/include/odb/db.h b/src/odb/include/odb/db.h index 1b06509b75..27c1ddcceb 100644 --- a/src/odb/include/odb/db.h +++ b/src/odb/include/odb/db.h @@ -7161,7 +7161,7 @@ class dbBusPort : public dbObject // reallocate the bus port so all members sequential. void Realloc(); static dbBusPort* create(dbModule* parentModule, - dbModBTerm* root, + dbModBTerm* port, int from_ix, int to_ix); From b0ee6cf9a54232d0ca0ffc54c063eafc754bc84a Mon Sep 17 00:00:00 2001 From: Eder Monteiro Date: Thu, 1 Aug 2024 23:08:57 -0300 Subject: [PATCH 16/37] grt: add -show_segments option to draw_route_guides command Signed-off-by: Eder Monteiro --- src/grt/README.md | 19 +++++++++-- src/grt/src/AbstractGrouteRenderer.h | 5 ++- src/grt/src/GlobalRouter.i | 4 +-- src/grt/src/GlobalRouter.tcl | 6 ++-- src/grt/src/GrouteRenderer.cpp | 48 ++++++++++++++++++++++++---- src/grt/src/GrouteRenderer.h | 8 ++++- 6 files changed, 75 insertions(+), 15 deletions(-) diff --git a/src/grt/README.md b/src/grt/README.md index f3fa076e02..0130fbb89d 100644 --- a/src/grt/README.md +++ b/src/grt/README.md @@ -229,12 +229,14 @@ repair_antennas ### Plot Global Routing Guides The `draw_route_guides` command plots the route guides for a set of nets. +It also plots the route segments for a set of nets when using the -show_segments flag. To erase the route guides from the GUI, pass an empty list to this command: `draw_route_guides {}`. ```tcl draw_route_guides - net_names + net_names + [-show_segments] [-show_pin_locations] ``` @@ -243,6 +245,7 @@ draw_route_guides | Switch Name | Description | | ----- | ----- | | `net_names` | Tcl list of set of nets (e.g. `{net1, net2}`). | +| `-show_segments` | Draw the route segments instead of the route guides. | | `-show_pin_locations` | Draw circles for the pin positions on the routing grid. | ### Report Wirelength @@ -309,6 +312,12 @@ This command reads global routing guides. read_guides file_name ``` +#### Options + +| Switch Name | Description | +| ----- | ----- | +| `file_name` | Path to global routing guide. | + ### Write Global Routing Segments This command writes global routing segments, the raw routing data generated by @@ -318,6 +327,12 @@ the global routing tool. write_global_route_segments file_name ``` +#### Options + +| Switch Name | Description | +| ----- | ----- | +| `file_name` | Path to global routing segments file. | + ### Read Global Routing Segments This command reads global routing segments, the raw routing data generated by @@ -333,7 +348,7 @@ read_global_route_segments file_name | Switch Name | Description | | ----- | ----- | -| `file_name` | Path to global routing guide. | +| `file_name` | Path to global routing segments file. | ## Example scripts diff --git a/src/grt/src/AbstractGrouteRenderer.h b/src/grt/src/AbstractGrouteRenderer.h index eeea1e0239..9dc6e534f9 100644 --- a/src/grt/src/AbstractGrouteRenderer.h +++ b/src/grt/src/AbstractGrouteRenderer.h @@ -15,7 +15,10 @@ class AbstractGrouteRenderer public: virtual ~AbstractGrouteRenderer() = default; - virtual void highlightRoute(odb::dbNet* net, bool show_pin_locations) = 0; + virtual void highlightRoute(odb::dbNet* net, + bool show_segments, + bool show_pin_locations) + = 0; virtual void clearRoute() = 0; }; diff --git a/src/grt/src/GlobalRouter.i b/src/grt/src/GlobalRouter.i index 7ab1850350..00697cd840 100644 --- a/src/grt/src/GlobalRouter.i +++ b/src/grt/src/GlobalRouter.i @@ -223,7 +223,7 @@ add_net_to_route(odb::dbNet* net) } void -highlight_net_route(odb::dbNet *net, bool show_pin_locations) +highlight_net_route(odb::dbNet *net, bool show_segments, bool show_pin_locations) { if (!gui::Gui::enabled()) { return; @@ -234,7 +234,7 @@ highlight_net_route(odb::dbNet *net, bool show_pin_locations) router->setRenderer(std::make_unique(router, router->db()->getTech())); } - router->getRenderer()->highlightRoute(net, show_pin_locations); + router->getRenderer()->highlightRoute(net, show_segments, show_pin_locations); } void diff --git a/src/grt/src/GlobalRouter.tcl b/src/grt/src/GlobalRouter.tcl index 3df04e782d..24f1ad25e8 100644 --- a/src/grt/src/GlobalRouter.tcl +++ b/src/grt/src/GlobalRouter.tcl @@ -393,12 +393,13 @@ proc read_guides { args } { } sta::define_cmd_args "draw_route_guides" { net_names \ + [-show_segments] [-show_pin_locations] } proc draw_route_guides { args } { sta::parse_key_args "draw_route_guides" args \ keys {} \ - flags {-show_pin_locations} + flags {-show_pin_locations -show_segments} sta::check_argc_eq1 "draw_route_guides" $args set net_names [lindex $args 0] set block [ord::get_db_block] @@ -408,9 +409,10 @@ proc draw_route_guides { args } { grt::clear_route_guides set show_pins [info exists flags(-show_pin_locations)] + set show_segments [info exists flags(-show_segments)] foreach net [get_nets $net_names] { if { $net != "NULL" } { - grt::highlight_net_route [sta::sta_to_db_net $net] $show_pins + grt::highlight_net_route [sta::sta_to_db_net $net] $show_segments $show_pins } } } diff --git a/src/grt/src/GrouteRenderer.cpp b/src/grt/src/GrouteRenderer.cpp index 3f0859994f..ceb083a420 100644 --- a/src/grt/src/GrouteRenderer.cpp +++ b/src/grt/src/GrouteRenderer.cpp @@ -16,9 +16,12 @@ GrouteRenderer::GrouteRenderer(GlobalRouter* groute, odb::dbTech* tech) gui::Gui::get()->registerRenderer(this); } -void GrouteRenderer::highlightRoute(odb::dbNet* net, bool show_pin_locations) +void GrouteRenderer::highlightRoute(odb::dbNet* net, + bool show_segments, + bool show_pin_locations) { nets_.insert(net); + show_segments_[net] = show_segments; show_pin_locations_[net] = show_pin_locations; redraw(); } @@ -34,9 +37,10 @@ void GrouteRenderer::drawLayer(odb::dbTechLayer* layer, gui::Painter& painter) // draw on grid pin locations for (const Pin& pin : gr_net->getPins()) { if (pin.getConnectionLayer() == layer->getRoutingLevel()) { + float circle_factor = show_segments_[net] ? 8 : 1.5; painter.drawCircle(pin.getOnGridPosition().x(), pin.getOnGridPosition().y(), - (int) (groute_->getTileSize() / 1.5)); + (int) (groute_->getTileSize() / circle_factor)); } } } @@ -48,16 +52,35 @@ void GrouteRenderer::drawLayer(odb::dbTechLayer* layer, gui::Painter& painter) int layer1 = seg.init_layer; int layer2 = seg.final_layer; if (layer1 != layer2) { - continue; + if (show_segments_[net]) { + odb::dbTechLayer* via_layer1 = tech_->findRoutingLayer(layer1); + odb::dbTechLayer* via_layer2 = tech_->findRoutingLayer(layer2); + if (via_layer1 == layer) { + drawViaRect(seg, via_layer1, painter); + } else if (via_layer2 == layer) { + drawViaRect(seg, via_layer2, painter); + } else { + continue; + } + } else { + continue; + } } odb::dbTechLayer* seg_layer = tech_->findRoutingLayer(layer1); if (seg_layer != layer) { continue; } - // Draw rect because drawLine does not have a way to set the pen - // thickness. - odb::Rect rect = groute_->globalRoutingToBox(seg); - painter.drawRect(rect); + if (show_segments_[net]) { + odb::Point pt1(seg.init_x, seg.init_y); + odb::Point pt2(seg.final_x, seg.final_y); + painter.setPenWidth(layer->getMinWidth() * 2); + painter.drawLine(pt1, pt2); + } else { + // Draw rect because drawLine does not have a way to set the pen + // thickness. + odb::Rect rect = groute_->globalRoutingToBox(seg); + painter.drawRect(rect); + } } } } @@ -69,4 +92,15 @@ void GrouteRenderer::clearRoute() redraw(); } +void GrouteRenderer::drawViaRect(const GSegment& seg, + odb::dbTechLayer* layer, + gui::Painter& painter) +{ + int width = layer->getMinWidth() * 2; + odb::Point ll(seg.init_x - width, seg.init_y - width); + odb::Point ur(seg.init_x + width, seg.init_y + width); + odb::Rect via_rect(ll, ur); + painter.drawRect(via_rect); +} + } // namespace grt diff --git a/src/grt/src/GrouteRenderer.h b/src/grt/src/GrouteRenderer.h index b6753afc39..18b5dfa339 100644 --- a/src/grt/src/GrouteRenderer.h +++ b/src/grt/src/GrouteRenderer.h @@ -17,16 +17,22 @@ class GrouteRenderer : public gui::Renderer, public AbstractGrouteRenderer public: GrouteRenderer(GlobalRouter* groute, odb::dbTech* tech); - void highlightRoute(odb::dbNet* net, bool show_pin_locations) override; + void highlightRoute(odb::dbNet* net, + bool show_segments, + bool show_pin_locations) override; void clearRoute() override; void drawLayer(odb::dbTechLayer* layer, gui::Painter& painter) override; private: + void drawViaRect(const GSegment& seg, + odb::dbTechLayer* layer, + gui::Painter& painter); GlobalRouter* groute_; odb::dbTech* tech_; std::set nets_; + std::unordered_map show_segments_; std::unordered_map show_pin_locations_; }; From 0f4f81ee7b1c2d5dd2fae33cbec9061b9f0b7230 Mon Sep 17 00:00:00 2001 From: luis201420 Date: Fri, 2 Aug 2024 16:36:31 +0000 Subject: [PATCH 17/37] dpl: testing padding values Signed-off-by: luis201420 --- src/dpl/src/DecapPlacement.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/dpl/src/DecapPlacement.cpp b/src/dpl/src/DecapPlacement.cpp index d9f2c5a8bc..3e9d080375 100644 --- a/src/dpl/src/DecapPlacement.cpp +++ b/src/dpl/src/DecapPlacement.cpp @@ -39,6 +39,7 @@ #include "dpl/Opendp.h" #include "odb/dbShape.h" #include "utl/Logger.h" +#include "Padding.h" namespace dpl { @@ -228,6 +229,7 @@ void Opendp::insertDecapInPos(dbMaster* master, master, inst_name.c_str(), /* physical_only */ true); + std::cerr << master->getConstName() << " " << padding_->padRight(inst).v << " " << padding_->padGlobalLeft() << std::endl; inst->setOrient(orient); inst->setLocation(pos_x, pos_y); inst->setPlacementStatus(dbPlacementStatus::PLACED); From 966d02ea9f8f365533df3972d74cfd2cd86005c1 Mon Sep 17 00:00:00 2001 From: luis201420 Date: Fri, 2 Aug 2024 17:24:59 +0000 Subject: [PATCH 18/37] dpl: insert decap cells considering padding value Signed-off-by: luis201420 --- src/dpl/src/DecapPlacement.cpp | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/dpl/src/DecapPlacement.cpp b/src/dpl/src/DecapPlacement.cpp index 3e9d080375..ab9c0e7a15 100644 --- a/src/dpl/src/DecapPlacement.cpp +++ b/src/dpl/src/DecapPlacement.cpp @@ -65,8 +65,10 @@ vector Opendp::findDecapCellIndices(const int& gap_width, vector id_masters; double cap_acum = 0.0; int width_acum = 0; + const int min_space = padding_->padGlobalRight().v + padding_->padGlobalLeft().v; for (int i = 0; i < decap_masters_.size(); i++) { - while (decap_masters_[i]->master->getWidth() <= (gap_width - width_acum) + const int master_width = decap_masters_[i]->master->getWidth(); + while ((width_acum + master_width) <= (gap_width - min_space) && (cap_acum + decap_masters_[i]->capacitance) <= (target - current)) { id_masters.push_back(i); @@ -229,7 +231,7 @@ void Opendp::insertDecapInPos(dbMaster* master, master, inst_name.c_str(), /* physical_only */ true); - std::cerr << master->getConstName() << " " << padding_->padRight(inst).v << " " << padding_->padGlobalLeft() << std::endl; + std::cerr << master->getConstName() << " " << padding_->padRight(inst).v << " " << padding_->padGlobalLeft() << " " << padding_->padGlobalRight() << std::endl; inst->setOrient(orient); inst->setLocation(pos_x, pos_y); inst->setPlacementStatus(dbPlacementStatus::PLACED); From e2473319a5dac9ac7f63ed05bbbb44edf94e6362 Mon Sep 17 00:00:00 2001 From: luis201420 Date: Fri, 2 Aug 2024 17:55:48 +0000 Subject: [PATCH 19/37] dpl: converting padding value to dbu Signed-off-by: luis201420 --- src/dpl/src/DecapPlacement.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/dpl/src/DecapPlacement.cpp b/src/dpl/src/DecapPlacement.cpp index ab9c0e7a15..d2c91dfae4 100644 --- a/src/dpl/src/DecapPlacement.cpp +++ b/src/dpl/src/DecapPlacement.cpp @@ -65,10 +65,11 @@ vector Opendp::findDecapCellIndices(const int& gap_width, vector id_masters; double cap_acum = 0.0; int width_acum = 0; - const int min_space = padding_->padGlobalRight().v + padding_->padGlobalLeft().v; + const DbuX site_width = grid_->getSiteWidth(); + const DbuX min_space = gridToDbu(padding_->padGlobalRight() + padding_->padGlobalLeft(), site_width); for (int i = 0; i < decap_masters_.size(); i++) { const int master_width = decap_masters_[i]->master->getWidth(); - while ((width_acum + master_width) <= (gap_width - min_space) + while ((width_acum + master_width) <= (gap_width - min_space.v) && (cap_acum + decap_masters_[i]->capacitance) <= (target - current)) { id_masters.push_back(i); From 298940bb410b99760789792ee3608f068e242685 Mon Sep 17 00:00:00 2001 From: luis201420 Date: Fri, 2 Aug 2024 23:06:16 +0000 Subject: [PATCH 20/37] dpl: adding clang-format Signed-off-by: luis201420 --- src/dpl/src/DecapPlacement.cpp | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/dpl/src/DecapPlacement.cpp b/src/dpl/src/DecapPlacement.cpp index d2c91dfae4..7da0e78d3a 100644 --- a/src/dpl/src/DecapPlacement.cpp +++ b/src/dpl/src/DecapPlacement.cpp @@ -36,10 +36,10 @@ #include "DecapObjects.h" #include "Objects.h" +#include "Padding.h" #include "dpl/Opendp.h" #include "odb/dbShape.h" #include "utl/Logger.h" -#include "Padding.h" namespace dpl { @@ -66,15 +66,16 @@ vector Opendp::findDecapCellIndices(const int& gap_width, double cap_acum = 0.0; int width_acum = 0; const DbuX site_width = grid_->getSiteWidth(); - const DbuX min_space = gridToDbu(padding_->padGlobalRight() + padding_->padGlobalLeft(), site_width); + const DbuX min_space = gridToDbu( + padding_->padGlobalRight() + padding_->padGlobalLeft(), site_width); for (int i = 0; i < decap_masters_.size(); i++) { const int master_width = decap_masters_[i]->master->getWidth(); + const double master_cap = decap_masters_[i]->capacitance; while ((width_acum + master_width) <= (gap_width - min_space.v) - && (cap_acum + decap_masters_[i]->capacitance) - <= (target - current)) { + && (cap_acum + master_cap) <= (target - current)) { id_masters.push_back(i); - cap_acum += decap_masters_[i]->capacitance; - width_acum += decap_masters_[i]->master->getWidth(); + cap_acum += master_cap; + width_acum += master_width; if (width_acum == gap_width) { return id_masters; } @@ -232,7 +233,6 @@ void Opendp::insertDecapInPos(dbMaster* master, master, inst_name.c_str(), /* physical_only */ true); - std::cerr << master->getConstName() << " " << padding_->padRight(inst).v << " " << padding_->padGlobalLeft() << " " << padding_->padGlobalRight() << std::endl; inst->setOrient(orient); inst->setLocation(pos_x, pos_y); inst->setPlacementStatus(dbPlacementStatus::PLACED); From 872751efb3c777216834da85f393818bebc67d70 Mon Sep 17 00:00:00 2001 From: andyfox-rushc Date: Fri, 2 Aug 2024 17:06:09 -0700 Subject: [PATCH 21/37] BusPort iterators using auto generated iterator. Signed-off-by: Andy Fox andy@rushc.com Signed-off-by: andyfox-rushc --- src/dbSta/src/dbNetwork.cc | 110 +++++++--------- src/dbSta/src/dbReadVerilog.cc | 22 ++-- src/odb/include/odb/db.h | 18 ++- src/odb/include/odb/dbCompare.h | 9 ++ .../codeGenerator/schema/chip/dbBusPort.json | 4 +- .../codeGenerator/schema/chip/dbModule.json | 2 +- src/odb/src/db/CMakeLists.txt | 2 + src/odb/src/db/dbBusPort.cpp | 20 ++- src/odb/src/db/dbBusPort.h | 7 ++ src/odb/src/db/dbModBTerm.cpp | 12 -- src/odb/src/db/dbModule.cpp | 7 ++ src/odb/src/db/dbModuleBusPortModBTermItr.cpp | 117 ++++++++++++++++++ src/odb/src/db/dbModuleBusPortModBTermItr.h | 73 +++++++++++ src/odb/src/db/dbModuleModBTermItr.cpp | 16 +++ src/odb/src/db/dbModuleModInstItr.cpp | 1 + 15 files changed, 324 insertions(+), 96 deletions(-) create mode 100644 src/odb/src/db/dbModuleBusPortModBTermItr.cpp create mode 100644 src/odb/src/db/dbModuleBusPortModBTermItr.h diff --git a/src/dbSta/src/dbNetwork.cc b/src/dbSta/src/dbNetwork.cc index 7b72501587..4c9c689e86 100644 --- a/src/dbSta/src/dbNetwork.cc +++ b/src/dbSta/src/dbNetwork.cc @@ -108,6 +108,7 @@ using odb::dbModITerm; using odb::dbModITermObj; using odb::dbModNetObj; using odb::dbModule; +using odb::dbModuleBusPortModBTermItr; using odb::dbModuleObj; using odb::dbMTerm; using odb::dbNet; @@ -699,39 +700,47 @@ const char* dbNetwork::name(const Cell* cell) const //////////////////////////////////////////////////////////////// // Module port iterator, allows traversal across dbModulePorts -// Traverse the ports in creation order (from end to beginning). +// Note that a port is not the same as a dbModBTerm. +// +// A Port is a higher level concept. +// A Port can be one of: +// (a) singleton +// (b) bus port (which has many singletons inside it) +// (c) bundle port -- todo (which has many singletons inside it). +// +// This iterator goes through the ports via the lowest level connections: +// the singleton modbterms . To see what is inside the +// aggregated ports (eg bus port/bundle port) we use the member +// Iterator. (Though this iterator simply skips them). +// +// +// TODO: remove the traversal at the lowest level. +// class dbModulePortIterator : public CellPortIterator { public: - explicit dbModulePortIterator(const dbModule* cell); + explicit dbModulePortIterator(dbModule* cell); ~dbModulePortIterator() override = default; virtual bool hasNext() override; virtual Port* next() override; private: - const dbModBTerm* iter_; + dbSet::iterator iter_; + dbSet::iterator end_; const dbModule* module_; }; -dbModulePortIterator::dbModulePortIterator(const dbModule* cell) +dbModulePortIterator::dbModulePortIterator(dbModule* cell) { - // skip to end - const dbModBTerm* first_mod_bterm = cell->getHeadDbModBTerm(); - // - // Next pull request remove this. Use reverse on list - // so head is first element in natural order - // - for (iter_ = cell->getHeadDbModBTerm(); iter_; iter_ = iter_->getNext()) { - first_mod_bterm = iter_; - } - iter_ = first_mod_bterm; + iter_ = cell->getModBTerms().begin(); + end_ = cell->getModBTerms().end(); module_ = cell; } bool dbModulePortIterator::hasNext() { - if (iter_) { + if (iter_ != end_) { return true; } return false; @@ -739,21 +748,16 @@ bool dbModulePortIterator::hasNext() Port* dbModulePortIterator::next() { - dbModBTerm* modbterm = const_cast(iter_); - Port* ret = reinterpret_cast(modbterm); - if (modbterm->isBusPort()) { - dbBusPort* bp = modbterm->getBusPort(); - int size = bp->getSize(); - // content of bus - iter_ = iter_->getPrev(); - // Next pull request remove this, use offset mechanism - for (int skip_ix = 0; skip_ix < size && (iter_->getPrev()); skip_ix++) { - iter_ = iter_->getPrev(); + dbModBTerm* ret = *iter_; + if (ret->isBusPort()) { + dbBusPort* bus_port = ret->getBusPort(); + // TODO clean this up so iter_ = iter_ + bus_port -> getSize() + for (int i = 0; i < bus_port->getSize(); i++) { + iter_++; } - } else { - iter_ = iter_->getPrev(); } - return ret; + iter_++; + return (reinterpret_cast(ret)); } CellPortIterator* dbNetwork::portIterator(const Cell* cell) const @@ -2132,13 +2136,6 @@ void dbNetwork::staToDb(const Port* port, mterm = nullptr; modbterm = nullptr; - // - // Primary, needs concrete test - // - // if it is a concrete port we get the port stuff from the extPort - // void* field in the fake library created. - // - // if (isConcretePort(port)) { const ConcretePort* cport = reinterpret_cast(port); mterm = reinterpret_cast(cport->extPort()); @@ -2416,7 +2413,6 @@ int dbNetwork::toIndex(const Port* port) const } return (start_ix - (modbterm->getBusPort()->getSize() - 1)); } - logger_->error(ORD, 2022, "Error: bad bus to_index defintion"); return 0; } @@ -2433,7 +2429,6 @@ bool dbNetwork::hasMembers(const Port* port) const } return false; } - const ConcretePort* cport = reinterpret_cast(port); return cport->hasMembers(); } @@ -2460,59 +2455,48 @@ class DbNetworkPortMemberIterator : public PortMemberIterator { public: explicit DbNetworkPortMemberIterator(const Port* port, const dbNetwork* nwk); - ~DbNetworkPortMemberIterator() = default; + ~DbNetworkPortMemberIterator(); virtual bool hasNext(); virtual Port* next(); private: - int size_; - int ix_; - dbModBTerm* next_; - dbSet::iterator iter_; + dbSet::iterator members_; const dbNetwork* nwk_; + int ix_; + int size_; }; +DbNetworkPortMemberIterator::~DbNetworkPortMemberIterator() +{ +} + DbNetworkPortMemberIterator::DbNetworkPortMemberIterator(const Port* port, const dbNetwork* nwk) { - size_ = 0; - ix_ = -1; - next_ = nullptr; dbMTerm* mterm = nullptr; dbBTerm* bterm = nullptr; dbModBTerm* modbterm = nullptr; nwk_ = nwk; - nwk_->staToDb(port, bterm, mterm, modbterm); if (modbterm && modbterm->isBusPort()) { dbBusPort* busport = modbterm->getBusPort(); + members_ = busport->getBusPortMembers().begin(); size_ = busport->getSize(); - next_ = busport->getFirstMember(); + ix_ = 0; } } bool DbNetworkPortMemberIterator::hasNext() { - ix_++; - if (ix_ == 0) { - if (next_) { - return true; - } else { - return false; - } - } else { - if (ix_ < size_) { - next_ = next_->getPrev(); - return true; - } - } - next_ = nullptr; - return false; + return (ix_ != size_); } Port* DbNetworkPortMemberIterator::next() { - return reinterpret_cast(next_); + dbModBTerm* ret = *members_; + members_++; + ix_++; + return reinterpret_cast(ret); } PortMemberIterator* dbNetwork::memberIterator(const Port* port) const diff --git a/src/dbSta/src/dbReadVerilog.cc b/src/dbSta/src/dbReadVerilog.cc index b29cd0e56e..490f189c5c 100644 --- a/src/dbSta/src/dbReadVerilog.cc +++ b/src/dbSta/src/dbReadVerilog.cc @@ -35,6 +35,8 @@ #include "db_sta/dbReadVerilog.hh" +#include + #include #include @@ -364,6 +366,7 @@ void Verilog2db::makeDbModule( return; } if (hierarchy_) { + dbBusPort* dbbusport = nullptr; // make the module ports CellPortIterator* cp_iter = network_->portIterator(cell); while (cp_iter->hasNext()) { @@ -372,17 +375,19 @@ void Verilog2db::makeDbModule( // make the bus port as part of the port set for the cell. const char* port_name = network_->name(port); dbModBTerm* bmodterm = dbModBTerm::create(module, port_name); - dbBusPort* dbbusport - = dbBusPort::create(module, - bmodterm, // the root of the bus port - network_->fromIndex(port), - network_->toIndex(port)); + dbbusport = dbBusPort::create(module, + bmodterm, // the root of the bus port + network_->fromIndex(port), + network_->toIndex(port)); bmodterm->setBusPort(dbbusport); dbIoType io_type = staToDb(network_->direction(port)); bmodterm->setIoType(io_type); - + // // Make a modbterm for each bus bit // Keep traversal in terms of bits + // These modbterms are annotated as being + // part of the port bus. + // int from_index = network_->fromIndex(port); int to_index = network_->toIndex(port); bool updown = (from_index <= to_index) ? true : false; @@ -413,6 +418,7 @@ void Verilog2db::makeDbModule( bmodterm->getName()); } } + module->getModBTerms().reverse(); // make the instance iterms InstancePinIterator* ip_iter = network_->pinIterator(inst); while (ip_iter->hasNext()) { @@ -428,11 +434,8 @@ void Verilog2db::makeDbModule( "Created module iterm {} ", moditerm->getName()); } - // reverse the ports on the dbModule to natural order - module->getModBTerms().reverse(); } } - InstanceChildIterator* child_iter = network_->childIterator(inst); while (child_iter->hasNext()) { Instance* child = child_iter->next(); @@ -512,6 +515,7 @@ void Verilog2db::makeDbModule( && module->getChildren().orderReversed()) { module->getChildren().reverse(); } + if (module->getInsts().reversible() && module->getInsts().orderReversed()) { module->getInsts().reverse(); } diff --git a/src/odb/include/odb/db.h b/src/odb/include/odb/db.h index 27c1ddcceb..002dcf2b91 100644 --- a/src/odb/include/odb/db.h +++ b/src/odb/include/odb/db.h @@ -176,6 +176,8 @@ class dbTechLayerWrongDirSpacingRule; // Extraction Objects class dbExtControl; +// Custom iterators +class dbModuleBusPortModBTermItr; /// /// dbProperty - Property base class. /// @@ -7153,18 +7155,23 @@ class dbBusPort : public dbObject // get element by bit index in bus (allows for up/down) // linear access dbModBTerm* getBusIndexedElement(int index) const; - void setFirstMember(dbModBTerm*); dbModBTerm* getFirstMember(); + + dbSet getBusPortMembers(); int getSize() const; bool getUpdown() const; - // reallocate the bus port so all members sequential. - void Realloc(); + static dbBusPort* create(dbModule* parentModule, dbModBTerm* port, int from_ix, int to_ix); + private: + // dbModuleBusPortModBTermItr* _members_iter=nullptr; + // reallocate the bus port so all members sequential. + void Realloc(); + // User Code End dbBusPort }; @@ -7586,15 +7593,15 @@ class dbModBTerm : public dbObject dbIoType getIoType(); void connect(dbModNet* net); void disconnect(); - void staSetPort(void* p); - void* staPort(); bool isBusPort() const; void setBusPort(dbBusPort*); dbBusPort* getBusPort() const; dbModBTerm* getNext() const; dbModBTerm* getPrev() const; + static dbModBTerm* create(dbModule* parentModule, const char* name); + private: // User Code End dbModBTerm }; @@ -7690,6 +7697,7 @@ class dbModule : public dbObject dbSet getModInsts(); dbSet getModNets(); dbSet getModBTerms(); + dbModBTerm* getModBTerm(uint id); dbSet getInsts(); dbModInst* findModInst(const char* name); diff --git a/src/odb/include/odb/dbCompare.h b/src/odb/include/odb/dbCompare.h index 7098117f53..35a46744c4 100644 --- a/src/odb/include/odb/dbCompare.h +++ b/src/odb/include/odb/dbCompare.h @@ -496,6 +496,15 @@ struct less } }; +template <> +struct less +{ + bool operator()(const odb::dbBusPort* lhs, const odb::dbBusPort* rhs) const + { + return odb::compare_by_id(lhs, rhs); + } +}; + template <> struct less { diff --git a/src/odb/src/codeGenerator/schema/chip/dbBusPort.json b/src/odb/src/codeGenerator/schema/chip/dbBusPort.json index f0c11c83b3..429267ff3d 100644 --- a/src/odb/src/codeGenerator/schema/chip/dbBusPort.json +++ b/src/odb/src/codeGenerator/schema/chip/dbBusPort.json @@ -1,7 +1,7 @@ { "name":"dbBusPort", "type":"dbObject", - "fields":[ + "fields": [ { "name":"_flags", "type":"uint", @@ -46,5 +46,5 @@ } ], "constructors":[], - "cpp_includes":[ "dbVector.h","dbBlock.h","dbModBTerm.h","dbModule.h","dbModNet.h","dbHashTable.hpp","dbModITerm.h","dbBusPort.h"] + "cpp_includes":[ "dbVector.h","dbBlock.h","dbModBTerm.h","dbModule.h","dbModNet.h","dbHashTable.hpp","dbModITerm.h","dbBusPort.h", "dbModuleBusPortModBTermItr.h"] } diff --git a/src/odb/src/codeGenerator/schema/chip/dbModule.json b/src/odb/src/codeGenerator/schema/chip/dbModule.json index 7092a5d84c..507d239843 100644 --- a/src/odb/src/codeGenerator/schema/chip/dbModule.json +++ b/src/odb/src/codeGenerator/schema/chip/dbModule.json @@ -39,7 +39,7 @@ { "name":"_modbterms", "type":"dbId<_dbModBTerm>", - "flags":["no-set","no-get"], + "flags":["no-set","no-get"], "schema":"db_schema_update_hierarchy" } ], diff --git a/src/odb/src/db/CMakeLists.txt b/src/odb/src/db/CMakeLists.txt index 56bab7daf0..356bbec025 100644 --- a/src/odb/src/db/CMakeLists.txt +++ b/src/odb/src/db/CMakeLists.txt @@ -83,6 +83,7 @@ add_library(db wOrder.cpp dbGroupPowerNetItr.cpp dbGroupGroundNetItr.cpp + dbBusPortMemberItr.cpp # Generator Code Begin cpp dbAccessPoint.cpp dbBusPort.cpp @@ -132,6 +133,7 @@ add_library(db dbGroupItr.cpp dbGroupModInstItr.cpp dbGuideItr.cpp + dbModuleBusPortModBTermItr.cpp dbModuleInstItr.cpp dbModuleModBTermItr.cpp dbModuleModInstItr.cpp diff --git a/src/odb/src/db/dbBusPort.cpp b/src/odb/src/db/dbBusPort.cpp index 4738211cc1..7188fef874 100644 --- a/src/odb/src/db/dbBusPort.cpp +++ b/src/odb/src/db/dbBusPort.cpp @@ -42,6 +42,7 @@ #include "dbModITerm.h" #include "dbModNet.h" #include "dbModule.h" +#include "dbModuleBusPortModBTermItr.h" #include "dbTable.h" #include "dbTable.hpp" #include "dbVector.h" @@ -286,10 +287,11 @@ dbModBTerm* dbBusPort::getFirstMember() int dbBusPort::getSize() const { _dbBusPort* obj = (_dbBusPort*) this; - if (getUpdown()) { - return (obj->_to - obj->_from + 1); - } - return (obj->_from - obj->_to + 1); + // we keep how the size is computed in the + // database low level object so that if + // we need to use it during low level + // iterators we can. + return obj->size(); } bool dbBusPort::getUpdown() const @@ -317,6 +319,16 @@ dbBusPort* dbBusPort::create(dbModule* parentModule, return (dbBusPort*) busport; } +dbSet dbBusPort::getBusPortMembers() +{ + _dbBusPort* obj = (_dbBusPort*) this; + if (obj->_members_iter == nullptr) { + _dbBlock* block = (_dbBlock*) obj->getOwner(); + obj->_members_iter = new dbModuleBusPortModBTermItr(block->_modbterm_tbl); + } + return dbSet(this, obj->_members_iter); +} + // // TODO future pull request: Reallocate the bus to preserve sequential db // ordering This to be added as part of "scaffolding functions" diff --git a/src/odb/src/db/dbBusPort.h b/src/odb/src/db/dbBusPort.h index a001bbf78c..95333d2416 100644 --- a/src/odb/src/db/dbBusPort.h +++ b/src/odb/src/db/dbBusPort.h @@ -37,6 +37,7 @@ #include "odb/odb.h" // User Code Begin Includes +#include "dbModuleBusPortModBTermItr.h" #include "dbVector.h" // User Code End Includes @@ -70,6 +71,12 @@ class _dbBusPort : public _dbObject dbId<_dbModBTerm> _port; dbId<_dbModBTerm> _members; dbId<_dbModule> _parent; + + // User Code Begin Fields + // need to make sure this is destroyed + dbModuleBusPortModBTermItr* _members_iter = nullptr; + int size() { return abs(_from - _to) + 1; } + // User Code End Fields }; dbIStream& operator>>(dbIStream& stream, _dbBusPort& obj); dbOStream& operator<<(dbOStream& stream, const _dbBusPort& obj); diff --git a/src/odb/src/db/dbModBTerm.cpp b/src/odb/src/db/dbModBTerm.cpp index 0e0a469eb0..650e9eccc0 100644 --- a/src/odb/src/db/dbModBTerm.cpp +++ b/src/odb/src/db/dbModBTerm.cpp @@ -417,18 +417,6 @@ void dbModBTerm::disconnect() _modbterm->_prev_net_modbterm = 0; } -void dbModBTerm::staSetPort(void* p) -{ - _dbModBTerm* _modbterm = (_dbModBTerm*) this; - _modbterm->_sta_port = p; -} - -void* dbModBTerm::staPort() -{ - _dbModBTerm* _modbterm = (_dbModBTerm*) this; - return _modbterm->_sta_port; -} - bool dbModBTerm::isBusPort() const { _dbModBTerm* _modbterm = (_dbModBTerm*) this; diff --git a/src/odb/src/db/dbModule.cpp b/src/odb/src/db/dbModule.cpp index 994de5d615..3e107ea95f 100644 --- a/src/odb/src/db/dbModule.cpp +++ b/src/odb/src/db/dbModule.cpp @@ -371,6 +371,13 @@ dbSet dbModule::getModBTerms() return dbSet(module, block->_module_modbterm_itr); } +dbModBTerm* dbModule::getModBTerm(uint id) +{ + _dbModule* module = (_dbModule*) this; + _dbBlock* block = (_dbBlock*) module->getOwner(); + return (dbModBTerm*) (block->_modbterm_tbl->getObject(id)); +} + dbSet dbModule::getInsts() { _dbModule* module = (_dbModule*) this; diff --git a/src/odb/src/db/dbModuleBusPortModBTermItr.cpp b/src/odb/src/db/dbModuleBusPortModBTermItr.cpp new file mode 100644 index 0000000000..89d0db7cc7 --- /dev/null +++ b/src/odb/src/db/dbModuleBusPortModBTermItr.cpp @@ -0,0 +1,117 @@ +/////////////////////////////////////////////////////////////////////////////// +// BSD 3-Clause License +// +// Copyright (c) 2019, Nefelus Inc +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// * Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +// Generator Code Begin Cpp +#include "dbModuleBusPortModBTermItr.h" + +#include "dbBusPort.h" +#include "dbModBTerm.h" +#include "dbModule.h" +#include "dbTable.h" + +namespace odb { + +//////////////////////////////////////////////////////////////////// +// +// dbModuleBusPortModBTermItr - Methods +// +//////////////////////////////////////////////////////////////////// + +bool dbModuleBusPortModBTermItr::reversible() +{ + return true; +} + +bool dbModuleBusPortModBTermItr::orderReversed() +{ + return true; +} + +void dbModuleBusPortModBTermItr::reverse(dbObject* parent) +{ +} + +uint dbModuleBusPortModBTermItr::sequential() +{ + return 0; +} + +uint dbModuleBusPortModBTermItr::size(dbObject* parent) +{ + uint id; + uint cnt = 0; + + for (id = dbModuleBusPortModBTermItr::begin(parent); + id != dbModuleBusPortModBTermItr::end(parent); + id = dbModuleBusPortModBTermItr::next(id)) { + ++cnt; + } + + return cnt; +} + +uint dbModuleBusPortModBTermItr::begin(dbObject* parent) +{ + // User Code Begin begin + _dbBusPort* _busport = (_dbBusPort*) parent; + _iter = _modbterm_tbl->getPtr(_busport->_members); + _size = abs(_busport->_from - _busport->_to) + 1; + _ix = 0; + return _busport->_members; + // User Code End begin +} + +uint dbModuleBusPortModBTermItr::end(dbObject* /* unused: parent */) +{ + if (_ix == _size) { + return _iter->getId(); + } + return 0; +} + +uint dbModuleBusPortModBTermItr::next(uint id, ...) +{ + // User Code Begin next + _dbModBTerm* lmodbterm = _modbterm_tbl->getPtr(id); + _ix++; + uint ret = lmodbterm->_next_entry; + _iter = _modbterm_tbl->getPtr(ret); + return ret; + // User Code End next +} + +dbObject* dbModuleBusPortModBTermItr::getObject(uint id, ...) +{ + return _modbterm_tbl->getPtr(id); +} +} // namespace odb + // Generator Code End Cpp diff --git a/src/odb/src/db/dbModuleBusPortModBTermItr.h b/src/odb/src/db/dbModuleBusPortModBTermItr.h new file mode 100644 index 0000000000..50ea27e4b2 --- /dev/null +++ b/src/odb/src/db/dbModuleBusPortModBTermItr.h @@ -0,0 +1,73 @@ +/////////////////////////////////////////////////////////////////////////////// +// BSD 3-Clause License +// +// Copyright (c) 2020, The Regents of the University of California +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// * Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +// Generator Code Begin Header +#pragma once + +#include "odb/dbIterator.h" +#include "odb/odb.h" + +namespace odb { +class _dbModBTerm; + +template +class dbTable; + +class dbModuleBusPortModBTermItr : public dbIterator +{ + public: + dbModuleBusPortModBTermItr(dbTable<_dbModBTerm>* modbterm_tbl) + { + _modbterm_tbl = modbterm_tbl; + } + + bool reversible() override; + bool orderReversed() override; + void reverse(dbObject* parent) override; + uint sequential() override; + uint size(dbObject* parent) override; + uint begin(dbObject* parent) override; + uint end(dbObject* parent) override; + uint next(uint id, ...) override; + dbObject* getObject(uint id, ...) override; + + private: + dbTable<_dbModBTerm>* _modbterm_tbl; + // User Code Begin begin + int _ix = 0; + int _size = 0; + _dbModBTerm* _iter = nullptr; + // User Code End begin +}; + +} // namespace odb + // Generator Code End Header diff --git a/src/odb/src/db/dbModuleModBTermItr.cpp b/src/odb/src/db/dbModuleModBTermItr.cpp index e5efa521ac..e29828350c 100644 --- a/src/odb/src/db/dbModuleModBTermItr.cpp +++ b/src/odb/src/db/dbModuleModBTermItr.cpp @@ -33,6 +33,8 @@ // Generator Code Begin Cpp #include "dbModuleModBTermItr.h" +#include "dbBusPort.h" +#include "dbModBTerm.h" #include "dbModBTerm.h" #include "dbModule.h" #include "dbTable.h" @@ -57,6 +59,20 @@ bool dbModuleModBTermItr::orderReversed() void dbModuleModBTermItr::reverse(dbObject* parent) { + // User Code Begin reverse + _dbModule* module = (_dbModule*) parent; + uint next = module->_modbterms; + uint prev = 0; + uint list = 0; + while (next != 0) { + list = next; + _dbModBTerm* modbterm = _modbterm_tbl->getPtr(next); + next = modbterm->_next_entry; + modbterm->_next_entry = prev; + prev = list; + } + module->_modbterms = list; + // User Code End reverse } uint dbModuleModBTermItr::sequential() diff --git a/src/odb/src/db/dbModuleModInstItr.cpp b/src/odb/src/db/dbModuleModInstItr.cpp index f891745da9..63b47fac96 100644 --- a/src/odb/src/db/dbModuleModInstItr.cpp +++ b/src/odb/src/db/dbModuleModInstItr.cpp @@ -33,6 +33,7 @@ // Generator Code Begin Cpp #include "dbModuleModInstItr.h" +#include "dbModInst.h" #include "dbModInst.h" #include "dbModule.h" #include "dbTable.h" From 4e94f6ca5be534c318471589bd70eacd01307c6f Mon Sep 17 00:00:00 2001 From: andyfox-rushc Date: Fri, 2 Aug 2024 17:37:42 -0700 Subject: [PATCH 22/37] Work in progress. removed default destructor in dbBusPort. Signed-off-by: Andy Fox andy@rushc.com Signed-off-by: andyfox-rushc --- src/dbSta/src/dbNetwork.cc | 4 +- src/odb/src/codeGenerator/schema.json | 42 ++++++++++++------- .../codeGenerator/schema/chip/dbBusPort.json | 1 + src/odb/src/db/CMakeLists.txt | 1 - src/odb/src/db/dbBusPort.cpp | 9 ++++ src/odb/src/db/dbBusPort.h | 2 +- src/odb/src/db/dbModuleBusPortModBTermItr.h | 4 +- src/odb/src/db/dbModuleModBTermItr.cpp | 1 - src/odb/src/db/dbModuleModInstItr.cpp | 1 - 9 files changed, 41 insertions(+), 24 deletions(-) diff --git a/src/dbSta/src/dbNetwork.cc b/src/dbSta/src/dbNetwork.cc index 4c9c689e86..5827d0e055 100644 --- a/src/dbSta/src/dbNetwork.cc +++ b/src/dbSta/src/dbNetwork.cc @@ -2462,8 +2462,8 @@ class DbNetworkPortMemberIterator : public PortMemberIterator private: dbSet::iterator members_; const dbNetwork* nwk_; - int ix_; - int size_; + int ix_ = 0; + int size_ = 0; }; DbNetworkPortMemberIterator::~DbNetworkPortMemberIterator() diff --git a/src/odb/src/codeGenerator/schema.json b/src/odb/src/codeGenerator/schema.json index 63fa0b5474..c4791a2ba3 100644 --- a/src/odb/src/codeGenerator/schema.json +++ b/src/odb/src/codeGenerator/schema.json @@ -1,6 +1,16 @@ { - "classes_dir": "schema", - "iterators":[ + "classes_dir": "schema", + "iterators":[ + { + "name": "dbModuleModBTermItr", + "parentObject": "dbModBTerm", + "tableName": "modbterm_tbl", + "reversible": "true", + "orderReversed": "true", + "flags":["private"], + "sequential": 0, + "includes": ["dbModBTerm.h", "dbModule.h", "dbBusPort.h"] + }, { "name": "dbModuleInstItr", "parentObject": "dbInst", @@ -16,26 +26,26 @@ "tableName": "modinst_tbl", "reversible": "true", "orderReversed": "true", - "sequential": 0, - "includes": ["dbModInst.h", "dbModule.h"] + "sequential": 0, + "includes": ["dbModInst.h", "dbModule.h"] }, { - "name": "dbModuleModBTermItr", - "parentObject": "dbModBTerm", - "tableName": "modbterm_tbl", - "reversible": "true", + "name": "dbModuleBusPortModBTermItr", + "parentObject": "dbModBTerm", + "tableName": "modbterm_tbl", + "reversible": "true", "orderReversed": "true", "flags":["private"], - "sequential": 0, - "includes": ["dbModBTerm.h", "dbModule.h"] + "sequential": 0, + "includes": ["dbModBTerm.h", "dbModule.h", "dbBusPort.h"] }, { - "name": "dbModuleModInstModITermItr", - "parentObject": "dbModITerm", - "tableName": "moditerm_tbl", - "reversible": "true", - "orderReversed": "true", - "sequential": 0, + "name": "dbModuleModInstModITermItr", + "parentObject": "dbModITerm", + "tableName": "moditerm_tbl", + "reversible": "true", + "orderReversed": "true", + "sequential": 0, "includes": ["dbModITerm.h", "dbModule.h", "dbModInst.h"] }, { diff --git a/src/odb/src/codeGenerator/schema/chip/dbBusPort.json b/src/odb/src/codeGenerator/schema/chip/dbBusPort.json index 429267ff3d..cc1afd556d 100644 --- a/src/odb/src/codeGenerator/schema/chip/dbBusPort.json +++ b/src/odb/src/codeGenerator/schema/chip/dbBusPort.json @@ -1,6 +1,7 @@ { "name":"dbBusPort", "type":"dbObject", + "needs_non_default_destructor" : "true", "fields": [ { "name":"_flags", diff --git a/src/odb/src/db/CMakeLists.txt b/src/odb/src/db/CMakeLists.txt index 356bbec025..8b59131699 100644 --- a/src/odb/src/db/CMakeLists.txt +++ b/src/odb/src/db/CMakeLists.txt @@ -83,7 +83,6 @@ add_library(db wOrder.cpp dbGroupPowerNetItr.cpp dbGroupGroundNetItr.cpp - dbBusPortMemberItr.cpp # Generator Code Begin cpp dbAccessPoint.cpp dbBusPort.cpp diff --git a/src/odb/src/db/dbBusPort.cpp b/src/odb/src/db/dbBusPort.cpp index 7188fef874..c5d184272c 100644 --- a/src/odb/src/db/dbBusPort.cpp +++ b/src/odb/src/db/dbBusPort.cpp @@ -169,6 +169,15 @@ dbOStream& operator<<(dbOStream& stream, const _dbBusPort& obj) return stream; } +_dbBusPort::~_dbBusPort() +{ + // User Code Begin d + if (_members_iter != nullptr) { + delete (_members_iter); + } + // User Code End d +} + //////////////////////////////////////////////////////////////////// // // dbBusPort - Methods diff --git a/src/odb/src/db/dbBusPort.h b/src/odb/src/db/dbBusPort.h index 95333d2416..c408d0d6a0 100644 --- a/src/odb/src/db/dbBusPort.h +++ b/src/odb/src/db/dbBusPort.h @@ -55,7 +55,7 @@ class _dbBusPort : public _dbObject _dbBusPort(_dbDatabase*, const _dbBusPort& r); _dbBusPort(_dbDatabase*); - ~_dbBusPort() = default; + ~_dbBusPort(); bool operator==(const _dbBusPort& rhs) const; bool operator!=(const _dbBusPort& rhs) const { return !operator==(rhs); } diff --git a/src/odb/src/db/dbModuleBusPortModBTermItr.h b/src/odb/src/db/dbModuleBusPortModBTermItr.h index 50ea27e4b2..523b1256c8 100644 --- a/src/odb/src/db/dbModuleBusPortModBTermItr.h +++ b/src/odb/src/db/dbModuleBusPortModBTermItr.h @@ -62,11 +62,11 @@ class dbModuleBusPortModBTermItr : public dbIterator private: dbTable<_dbModBTerm>* _modbterm_tbl; - // User Code Begin begin + // User Code Begin b1 int _ix = 0; int _size = 0; _dbModBTerm* _iter = nullptr; - // User Code End begin + // User Code End b1 }; } // namespace odb diff --git a/src/odb/src/db/dbModuleModBTermItr.cpp b/src/odb/src/db/dbModuleModBTermItr.cpp index e29828350c..d02e1aa42d 100644 --- a/src/odb/src/db/dbModuleModBTermItr.cpp +++ b/src/odb/src/db/dbModuleModBTermItr.cpp @@ -35,7 +35,6 @@ #include "dbBusPort.h" #include "dbModBTerm.h" -#include "dbModBTerm.h" #include "dbModule.h" #include "dbTable.h" diff --git a/src/odb/src/db/dbModuleModInstItr.cpp b/src/odb/src/db/dbModuleModInstItr.cpp index 63b47fac96..f891745da9 100644 --- a/src/odb/src/db/dbModuleModInstItr.cpp +++ b/src/odb/src/db/dbModuleModInstItr.cpp @@ -33,7 +33,6 @@ // Generator Code Begin Cpp #include "dbModuleModInstItr.h" -#include "dbModInst.h" #include "dbModInst.h" #include "dbModule.h" #include "dbTable.h" From d3af1b9f88ecaf57059e48d6b104902a7f62f766 Mon Sep 17 00:00:00 2001 From: andyfox-rushc Date: Fri, 2 Aug 2024 17:57:13 -0700 Subject: [PATCH 23/37] ctidy feedback. Signed-off-by: Andy Fox andy@rushc.com Signed-off-by: andyfox-rushc --- src/dbSta/src/dbNetwork.cc | 7 +------ src/odb/src/db/dbBusPort.cpp | 4 +--- src/odb/src/db/dbBusPort.h | 1 - 3 files changed, 2 insertions(+), 10 deletions(-) diff --git a/src/dbSta/src/dbNetwork.cc b/src/dbSta/src/dbNetwork.cc index 5827d0e055..59b1cf701b 100644 --- a/src/dbSta/src/dbNetwork.cc +++ b/src/dbSta/src/dbNetwork.cc @@ -108,7 +108,6 @@ using odb::dbModITerm; using odb::dbModITermObj; using odb::dbModNetObj; using odb::dbModule; -using odb::dbModuleBusPortModBTermItr; using odb::dbModuleObj; using odb::dbMTerm; using odb::dbNet; @@ -2455,7 +2454,7 @@ class DbNetworkPortMemberIterator : public PortMemberIterator { public: explicit DbNetworkPortMemberIterator(const Port* port, const dbNetwork* nwk); - ~DbNetworkPortMemberIterator(); + ~DbNetworkPortMemberIterator() = default; virtual bool hasNext(); virtual Port* next(); @@ -2466,10 +2465,6 @@ class DbNetworkPortMemberIterator : public PortMemberIterator int size_ = 0; }; -DbNetworkPortMemberIterator::~DbNetworkPortMemberIterator() -{ -} - DbNetworkPortMemberIterator::DbNetworkPortMemberIterator(const Port* port, const dbNetwork* nwk) { diff --git a/src/odb/src/db/dbBusPort.cpp b/src/odb/src/db/dbBusPort.cpp index c5d184272c..a66595687b 100644 --- a/src/odb/src/db/dbBusPort.cpp +++ b/src/odb/src/db/dbBusPort.cpp @@ -172,9 +172,7 @@ dbOStream& operator<<(dbOStream& stream, const _dbBusPort& obj) _dbBusPort::~_dbBusPort() { // User Code Begin d - if (_members_iter != nullptr) { - delete (_members_iter); - } + delete (_members_iter); // User Code End d } diff --git a/src/odb/src/db/dbBusPort.h b/src/odb/src/db/dbBusPort.h index c408d0d6a0..aaacbbfbaa 100644 --- a/src/odb/src/db/dbBusPort.h +++ b/src/odb/src/db/dbBusPort.h @@ -73,7 +73,6 @@ class _dbBusPort : public _dbObject dbId<_dbModule> _parent; // User Code Begin Fields - // need to make sure this is destroyed dbModuleBusPortModBTermItr* _members_iter = nullptr; int size() { return abs(_from - _to) + 1; } // User Code End Fields From 41b4c399ecd6d3c698cfc91a61cbfbdb9a182564 Mon Sep 17 00:00:00 2001 From: andyfox-rushc Date: Sat, 3 Aug 2024 12:35:01 -0700 Subject: [PATCH 24/37] Fixed odb generation issue. Signed-off-by: Andy Fox andy@rushc.com Signed-off-by: andyfox-rushc --- src/dbSta/src/dbNetwork.cc | 2 +- src/dbSta/src/dbReadVerilog.cc | 5 +++ src/odb/include/odb/db.h | 6 +++ .../codeGenerator/schema/chip/dbBusPort.json | 7 +++- src/odb/src/db/dbBusPort.cpp | 39 +++++++++++++++++-- src/odb/src/db/dbBusPort.h | 1 + src/odb/src/db/dbModuleBusPortModBTermItr.cpp | 3 -- src/odb/src/db/dbModuleBusPortModBTermItr.h | 4 +- 8 files changed, 57 insertions(+), 10 deletions(-) diff --git a/src/dbSta/src/dbNetwork.cc b/src/dbSta/src/dbNetwork.cc index 59b1cf701b..ec3c3c1415 100644 --- a/src/dbSta/src/dbNetwork.cc +++ b/src/dbSta/src/dbNetwork.cc @@ -750,7 +750,7 @@ Port* dbModulePortIterator::next() dbModBTerm* ret = *iter_; if (ret->isBusPort()) { dbBusPort* bus_port = ret->getBusPort(); - // TODO clean this up so iter_ = iter_ + bus_port -> getSize() + // todo: remove this using custom iterator for (int i = 0; i < bus_port->getSize(); i++) { iter_++; } diff --git a/src/dbSta/src/dbReadVerilog.cc b/src/dbSta/src/dbReadVerilog.cc index 490f189c5c..b2c7b4fd0f 100644 --- a/src/dbSta/src/dbReadVerilog.cc +++ b/src/dbSta/src/dbReadVerilog.cc @@ -382,12 +382,14 @@ void Verilog2db::makeDbModule( bmodterm->setBusPort(dbbusport); dbIoType io_type = staToDb(network_->direction(port)); bmodterm->setIoType(io_type); + // // Make a modbterm for each bus bit // Keep traversal in terms of bits // These modbterms are annotated as being // part of the port bus. // + int from_index = network_->fromIndex(port); int to_index = network_->toIndex(port); bool updown = (from_index <= to_index) ? true : false; @@ -402,6 +404,9 @@ void Verilog2db::makeDbModule( if (i == 0) { dbbusport->setFirstMember(modbterm); } + if (i == size - 1) { + dbbusport->setLast(modbterm); + } dbIoType io_type = staToDb(network_->direction(port)); bmodterm->setIoType(io_type); } diff --git a/src/odb/include/odb/db.h b/src/odb/include/odb/db.h index 499595659a..365f489d9c 100644 --- a/src/odb/include/odb/db.h +++ b/src/odb/include/odb/db.h @@ -7155,8 +7155,14 @@ class dbBusPort : public dbObject dbModBTerm* getPort() const; + void setMembers(dbModBTerm* members); + dbModBTerm* getMembers() const; + void setLast(dbModBTerm* last); + + dbModBTerm* getLast() const; + dbModule* getParent() const; // User Code Begin dbBusPort diff --git a/src/odb/src/codeGenerator/schema/chip/dbBusPort.json b/src/odb/src/codeGenerator/schema/chip/dbBusPort.json index cc1afd556d..b56c05cdad 100644 --- a/src/odb/src/codeGenerator/schema/chip/dbBusPort.json +++ b/src/odb/src/codeGenerator/schema/chip/dbBusPort.json @@ -34,7 +34,12 @@ { "name":"_members", "type":"dbId<_dbModBTerm>", - "flags":["no-set"], + "schema":"db_schema_odb_busport", + "parent":"dbBlock" + }, + { + "name":"_last", + "type":"dbId<_dbModBTerm>", "schema":"db_schema_odb_busport", "parent":"dbBlock" }, diff --git a/src/odb/src/db/dbBusPort.cpp b/src/odb/src/db/dbBusPort.cpp index a66595687b..e2e71c02fb 100644 --- a/src/odb/src/db/dbBusPort.cpp +++ b/src/odb/src/db/dbBusPort.cpp @@ -67,6 +67,9 @@ bool _dbBusPort::operator==(const _dbBusPort& rhs) const if (_members != rhs._members) { return false; } + if (_last != rhs._last) { + return false; + } if (_parent != rhs._parent) { return false; } @@ -89,6 +92,7 @@ void _dbBusPort::differences(dbDiff& diff, DIFF_FIELD(_to); DIFF_FIELD(_port); DIFF_FIELD(_members); + DIFF_FIELD(_last); DIFF_FIELD(_parent); DIFF_END } @@ -101,6 +105,7 @@ void _dbBusPort::out(dbDiff& diff, char side, const char* field) const DIFF_OUT_FIELD(_to); DIFF_OUT_FIELD(_port); DIFF_OUT_FIELD(_members); + DIFF_OUT_FIELD(_last); DIFF_OUT_FIELD(_parent); DIFF_END @@ -120,6 +125,7 @@ _dbBusPort::_dbBusPort(_dbDatabase* db, const _dbBusPort& r) _to = r._to; _port = r._port; _members = r._members; + _last = r._last; _parent = r._parent; } @@ -140,6 +146,9 @@ dbIStream& operator>>(dbIStream& stream, _dbBusPort& obj) if (obj.getDatabase()->isSchema(db_schema_odb_busport)) { stream >> obj._members; } + if (obj.getDatabase()->isSchema(db_schema_odb_busport)) { + stream >> obj._last; + } if (obj.getDatabase()->isSchema(db_schema_odb_busport)) { stream >> obj._parent; } @@ -163,6 +172,9 @@ dbOStream& operator<<(dbOStream& stream, const _dbBusPort& obj) if (obj.getDatabase()->isSchema(db_schema_odb_busport)) { stream << obj._members; } + if (obj.getDatabase()->isSchema(db_schema_odb_busport)) { + stream << obj._last; + } if (obj.getDatabase()->isSchema(db_schema_odb_busport)) { stream << obj._parent; } @@ -171,9 +183,6 @@ dbOStream& operator<<(dbOStream& stream, const _dbBusPort& obj) _dbBusPort::~_dbBusPort() { - // User Code Begin d - delete (_members_iter); - // User Code End d } //////////////////////////////////////////////////////////////////// @@ -204,6 +213,13 @@ dbModBTerm* dbBusPort::getPort() const return (dbModBTerm*) par->_modbterm_tbl->getPtr(obj->_port); } +void dbBusPort::setMembers(dbModBTerm* members) +{ + _dbBusPort* obj = (_dbBusPort*) this; + + obj->_members = members->getImpl()->getOID(); +} + dbModBTerm* dbBusPort::getMembers() const { _dbBusPort* obj = (_dbBusPort*) this; @@ -214,6 +230,23 @@ dbModBTerm* dbBusPort::getMembers() const return (dbModBTerm*) par->_modbterm_tbl->getPtr(obj->_members); } +void dbBusPort::setLast(dbModBTerm* last) +{ + _dbBusPort* obj = (_dbBusPort*) this; + + obj->_last = last->getImpl()->getOID(); +} + +dbModBTerm* dbBusPort::getLast() const +{ + _dbBusPort* obj = (_dbBusPort*) this; + if (obj->_last == 0) { + return nullptr; + } + _dbBlock* par = (_dbBlock*) obj->getOwner(); + return (dbModBTerm*) par->_modbterm_tbl->getPtr(obj->_last); +} + dbModule* dbBusPort::getParent() const { _dbBusPort* obj = (_dbBusPort*) this; diff --git a/src/odb/src/db/dbBusPort.h b/src/odb/src/db/dbBusPort.h index aaacbbfbaa..23c07daad1 100644 --- a/src/odb/src/db/dbBusPort.h +++ b/src/odb/src/db/dbBusPort.h @@ -70,6 +70,7 @@ class _dbBusPort : public _dbObject int _to; dbId<_dbModBTerm> _port; dbId<_dbModBTerm> _members; + dbId<_dbModBTerm> _last; dbId<_dbModule> _parent; // User Code Begin Fields diff --git a/src/odb/src/db/dbModuleBusPortModBTermItr.cpp b/src/odb/src/db/dbModuleBusPortModBTermItr.cpp index 89d0db7cc7..208f1dae07 100644 --- a/src/odb/src/db/dbModuleBusPortModBTermItr.cpp +++ b/src/odb/src/db/dbModuleBusPortModBTermItr.cpp @@ -92,9 +92,6 @@ uint dbModuleBusPortModBTermItr::begin(dbObject* parent) uint dbModuleBusPortModBTermItr::end(dbObject* /* unused: parent */) { - if (_ix == _size) { - return _iter->getId(); - } return 0; } diff --git a/src/odb/src/db/dbModuleBusPortModBTermItr.h b/src/odb/src/db/dbModuleBusPortModBTermItr.h index 523b1256c8..0e3e323637 100644 --- a/src/odb/src/db/dbModuleBusPortModBTermItr.h +++ b/src/odb/src/db/dbModuleBusPortModBTermItr.h @@ -62,11 +62,11 @@ class dbModuleBusPortModBTermItr : public dbIterator private: dbTable<_dbModBTerm>* _modbterm_tbl; - // User Code Begin b1 + // User Code Begin Fields int _ix = 0; int _size = 0; _dbModBTerm* _iter = nullptr; - // User Code End b1 + // User Code End Fields }; } // namespace odb From 15a18704c6c0ab1eecf03a8b1d7a53af36359c9c Mon Sep 17 00:00:00 2001 From: andyfox-rushc Date: Sun, 4 Aug 2024 12:38:16 -0700 Subject: [PATCH 25/37] Customized generated iterator for ports on a module. Signed-off-by: Andy Fox Signed-off-by: andyfox-rushc --- src/dbSta/src/dbNetwork.cc | 20 +++-------- src/odb/include/odb/db.h | 10 ++---- src/odb/src/codeGenerator/schema.json | 10 ++++++ .../codeGenerator/schema/chip/dbModule.json | 3 +- src/odb/src/db/CMakeLists.txt | 1 + src/odb/src/db/dbBusPort.cpp | 33 ------------------- src/odb/src/db/dbModule.cpp | 33 ++++++++++++------- src/odb/src/db/dbModule.h | 4 ++- src/odb/src/db/dbModuleBusPortModBTermItr.cpp | 3 ++ 9 files changed, 48 insertions(+), 69 deletions(-) diff --git a/src/dbSta/src/dbNetwork.cc b/src/dbSta/src/dbNetwork.cc index ec3c3c1415..843b0c4056 100644 --- a/src/dbSta/src/dbNetwork.cc +++ b/src/dbSta/src/dbNetwork.cc @@ -707,14 +707,11 @@ const char* dbNetwork::name(const Cell* cell) const // (b) bus port (which has many singletons inside it) // (c) bundle port -- todo (which has many singletons inside it). // -// This iterator goes through the ports via the lowest level connections: -// the singleton modbterms . To see what is inside the -// aggregated ports (eg bus port/bundle port) we use the member -// Iterator. (Though this iterator simply skips them). +// This iterator uses the odb generate iterator dbModulePortItr +// which has knowledge of he underlying port types and skips +// over their contents. // // -// TODO: remove the traversal at the lowest level. -// class dbModulePortIterator : public CellPortIterator { @@ -732,8 +729,8 @@ class dbModulePortIterator : public CellPortIterator dbModulePortIterator::dbModulePortIterator(dbModule* cell) { - iter_ = cell->getModBTerms().begin(); - end_ = cell->getModBTerms().end(); + iter_ = cell->getPorts().begin(); + end_ = cell->getPorts().end(); module_ = cell; } @@ -748,13 +745,6 @@ bool dbModulePortIterator::hasNext() Port* dbModulePortIterator::next() { dbModBTerm* ret = *iter_; - if (ret->isBusPort()) { - dbBusPort* bus_port = ret->getBusPort(); - // todo: remove this using custom iterator - for (int i = 0; i < bus_port->getSize(); i++) { - iter_++; - } - } iter_++; return (reinterpret_cast(ret)); } diff --git a/src/odb/include/odb/db.h b/src/odb/include/odb/db.h index 365f489d9c..61cc66f6d0 100644 --- a/src/odb/include/odb/db.h +++ b/src/odb/include/odb/db.h @@ -7181,11 +7181,6 @@ class dbBusPort : public dbObject int from_ix, int to_ix); - private: - // dbModuleBusPortModBTermItr* _members_iter=nullptr; - // reallocate the bus port so all members sequential. - void Realloc(); - // User Code End dbBusPort }; @@ -7710,6 +7705,9 @@ class dbModule : public dbObject dbSet getChildren(); dbSet getModInsts(); dbSet getModNets(); + // Get the ports of a module (STA world uses ports, which contain members). + dbSet getPorts(); + // Get the leaf level connections on a module (flat connected view). dbSet getModBTerms(); dbModBTerm* getModBTerm(uint id); dbSet getInsts(); @@ -7723,8 +7721,6 @@ class dbModule : public dbObject int getModInstCount(); int getDbInstCount(); - void staSetCell(void* cell); - void* getStaCell(); const dbModBTerm* getHeadDbModBTerm() const; static dbModule* create(dbBlock* block, const char* name); diff --git a/src/odb/src/codeGenerator/schema.json b/src/odb/src/codeGenerator/schema.json index c4791a2ba3..7a1970c34f 100644 --- a/src/odb/src/codeGenerator/schema.json +++ b/src/odb/src/codeGenerator/schema.json @@ -1,6 +1,16 @@ { "classes_dir": "schema", "iterators":[ + { + "name": "dbModulePortItr", + "parentObject": "dbModBTerm", + "tableName": "modbterm_tbl", + "reversible": "true", + "orderReversed": "true", + "flags":["private"], + "sequential": 0, + "includes": ["dbModBTerm.h", "dbModule.h", "dbBusPort.h", "dbBlock.h"] + }, { "name": "dbModuleModBTermItr", "parentObject": "dbModBTerm", diff --git a/src/odb/src/codeGenerator/schema/chip/dbModule.json b/src/odb/src/codeGenerator/schema/chip/dbModule.json index 507d239843..f7f1754abd 100644 --- a/src/odb/src/codeGenerator/schema/chip/dbModule.json +++ b/src/odb/src/codeGenerator/schema/chip/dbModule.json @@ -1,6 +1,7 @@ { "name":"dbModule", "type":"dbObject", + "needs_non_default_destructor" : "true", "fields":[ { "name":"_name", @@ -43,7 +44,7 @@ "schema":"db_schema_update_hierarchy" } ], - "cpp_includes":["dbBlock.h","dbHashTable.hpp", "dbModBTerm.h", "dbModInst.h", "dbInst.h"], + "cpp_includes":["dbBlock.h","dbHashTable.hpp", "dbModBTerm.h", "dbModInst.h", "dbInst.h", "dbModulePortItr.h"], "h_includes": [ "dbVector.h", "odb/dbSet.h" diff --git a/src/odb/src/db/CMakeLists.txt b/src/odb/src/db/CMakeLists.txt index 8b59131699..128aa341cb 100644 --- a/src/odb/src/db/CMakeLists.txt +++ b/src/odb/src/db/CMakeLists.txt @@ -142,6 +142,7 @@ add_library(db dbModuleModNetItr.cpp dbModuleModNetModBTermItr.cpp dbModuleModNetModITermItr.cpp + dbModulePortItr.cpp dbNetTrackItr.cpp dbRegionGroupItr.cpp # Generator Code End cpp diff --git a/src/odb/src/db/dbBusPort.cpp b/src/odb/src/db/dbBusPort.cpp index e2e71c02fb..bf26c1670b 100644 --- a/src/odb/src/db/dbBusPort.cpp +++ b/src/odb/src/db/dbBusPort.cpp @@ -299,7 +299,6 @@ dbModBTerm* dbBusPort::getBusIndexedElement(int index) const return cur; } } - return nullptr; } @@ -369,38 +368,6 @@ dbSet dbBusPort::getBusPortMembers() return dbSet(this, obj->_members_iter); } -// -// TODO future pull request: Reallocate the bus to preserve sequential db -// ordering This to be added as part of "scaffolding functions" -// -void dbBusPort::Realloc() -{ - /* - _dbBusPort* obj = (_dbBusPort*) this; - _dbBlock* block = (_dbBlock*) obj->getOwner(); - dbModule* parentModule (_dbModule*) obj -> getParent(); - if (obj -> _flags !=0U){ - dbModBTerm* busport = block -> modbterm_tbl -> getPtr(obj -> _port); - dbModBTerm* cur = busport -> getPrev(); - // - //sequentially reallocate the elements - //to assure they are layed out for sequential access - //after being tampered with. - // - int size = obj -> getSize(); - for (int i =0; i < size; i++){ - dbModBTerm* new_cur = dbModBTerm::create(parentModule,cur -> getName()); - new_cur -> _modnet = cur -> _modnet; - new_cur -> _next_net_modbterm = cur -> _modbterm; - new_cur -> _prev_net_modbterm = cur -> _modbterm; - new_cur -> _busPort = cur -> _busPort; - new_cur -> _name = cur -> _name; - new_cur -> _parent = cur -> _parent; - } - } - */ -} - // User Code End dbBusPortPublicMethods } // namespace odb // Generator Code End Cpp diff --git a/src/odb/src/db/dbModule.cpp b/src/odb/src/db/dbModule.cpp index 3e107ea95f..6f66968bc2 100644 --- a/src/odb/src/db/dbModule.cpp +++ b/src/odb/src/db/dbModule.cpp @@ -40,6 +40,7 @@ #include "dbInst.h" #include "dbModBTerm.h" #include "dbModInst.h" +#include "dbModulePortItr.h" #include "dbTable.h" #include "dbTable.hpp" #include "odb/db.h" @@ -364,6 +365,26 @@ dbSet dbModule::getModInsts() return dbSet(module, block->_module_modinst_itr); } +// +// The ports include higher level views. These have a special +// iterator which knows about how to skip the contents +// of the hierarchical objects (busports) +// + +dbSet dbModule::getPorts() +{ + _dbModule* obj = (_dbModule*) this; + if (obj->_port_iter == nullptr) { + _dbBlock* block = (_dbBlock*) obj->getOwner(); + obj->_port_iter = new dbModulePortItr(block->_modbterm_tbl); + } + return dbSet(this, obj->_port_iter); +} + +// +// The modbterms are the leaf level connections +//"flat view" +// dbSet dbModule::getModBTerms() { _dbModule* module = (_dbModule*) this; @@ -508,18 +529,6 @@ std::string dbModule::getHierarchicalName() const return ""; } -void* dbModule::getStaCell() -{ - _dbModule* module = (_dbModule*) this; - return module->_sta_cell; -} - -void dbModule::staSetCell(void* cell) -{ - _dbModule* module = (_dbModule*) this; - module->_sta_cell = cell; -} - dbBlock* dbModule::getOwner() { _dbModule* obj = (_dbModule*) this; diff --git a/src/odb/src/db/dbModule.h b/src/odb/src/db/dbModule.h index fda8088e5c..520818e0e6 100644 --- a/src/odb/src/db/dbModule.h +++ b/src/odb/src/db/dbModule.h @@ -39,6 +39,7 @@ #include "odb/odb.h" // User Code Begin Includes #include "dbHashTable.h" +#include "dbModulePortItr.h" // User Code End Includes namespace odb { @@ -80,7 +81,8 @@ class _dbModule : public _dbObject dbId<_dbModBTerm> _modbterms; // User Code Begin Fields - void* _sta_cell = nullptr; + // custom iterator for traversing ports + dbModulePortItr* _port_iter = nullptr; // User Code End Fields }; dbIStream& operator>>(dbIStream& stream, _dbModule& obj); diff --git a/src/odb/src/db/dbModuleBusPortModBTermItr.cpp b/src/odb/src/db/dbModuleBusPortModBTermItr.cpp index 208f1dae07..89d0db7cc7 100644 --- a/src/odb/src/db/dbModuleBusPortModBTermItr.cpp +++ b/src/odb/src/db/dbModuleBusPortModBTermItr.cpp @@ -92,6 +92,9 @@ uint dbModuleBusPortModBTermItr::begin(dbObject* parent) uint dbModuleBusPortModBTermItr::end(dbObject* /* unused: parent */) { + if (_ix == _size) { + return _iter->getId(); + } return 0; } From f7fa1c9551c93551f2a9647727ec728284f4188f Mon Sep 17 00:00:00 2001 From: andyfox-rushc Date: Sun, 4 Aug 2024 12:52:44 -0700 Subject: [PATCH 26/37] Attempt to silence odb commit message. Signed-off-by: Andy Fox Signed-off-by: andyfox-rushc --- src/odb/src/db/dbModuleBusPortModBTermItr.cpp | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/odb/src/db/dbModuleBusPortModBTermItr.cpp b/src/odb/src/db/dbModuleBusPortModBTermItr.cpp index 89d0db7cc7..208f1dae07 100644 --- a/src/odb/src/db/dbModuleBusPortModBTermItr.cpp +++ b/src/odb/src/db/dbModuleBusPortModBTermItr.cpp @@ -92,9 +92,6 @@ uint dbModuleBusPortModBTermItr::begin(dbObject* parent) uint dbModuleBusPortModBTermItr::end(dbObject* /* unused: parent */) { - if (_ix == _size) { - return _iter->getId(); - } return 0; } From f34ef08bb2831f7f87eb5518c867bb15fdc8deb8 Mon Sep 17 00:00:00 2001 From: andyfox-rushc Date: Sun, 4 Aug 2024 12:59:07 -0700 Subject: [PATCH 27/37] Add missing port iterator files. Signed-off-by: Andy Fox Signed-off-by: andyfox-rushc --- src/odb/src/db/dbModulePortItr.cpp | 118 +++++++++++++++++++++++++++++ src/odb/src/db/dbModulePortItr.h | 71 +++++++++++++++++ 2 files changed, 189 insertions(+) create mode 100644 src/odb/src/db/dbModulePortItr.cpp create mode 100644 src/odb/src/db/dbModulePortItr.h diff --git a/src/odb/src/db/dbModulePortItr.cpp b/src/odb/src/db/dbModulePortItr.cpp new file mode 100644 index 0000000000..38de40fcc8 --- /dev/null +++ b/src/odb/src/db/dbModulePortItr.cpp @@ -0,0 +1,118 @@ +/////////////////////////////////////////////////////////////////////////////// +// BSD 3-Clause License +// +// Copyright (c) 2019, Nefelus Inc +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// * Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +// Generator Code Begin Cpp +#include "dbModulePortItr.h" + +#include "dbBlock.h" +#include "dbBusPort.h" +#include "dbModBTerm.h" +#include "dbModule.h" +#include "dbTable.h" + +namespace odb { + +//////////////////////////////////////////////////////////////////// +// +// dbModulePortItr - Methods +// +//////////////////////////////////////////////////////////////////// + +bool dbModulePortItr::reversible() +{ + return true; +} + +bool dbModulePortItr::orderReversed() +{ + return true; +} + +void dbModulePortItr::reverse(dbObject* parent) +{ +} + +uint dbModulePortItr::sequential() +{ + return 0; +} + +uint dbModulePortItr::size(dbObject* parent) +{ + uint id; + uint cnt = 0; + + for (id = dbModulePortItr::begin(parent); id != dbModulePortItr::end(parent); + id = dbModulePortItr::next(id)) { + ++cnt; + } + + return cnt; +} + +uint dbModulePortItr::begin(dbObject* parent) +{ + // User Code Begin begin + _dbModule* _module = (_dbModule*) parent; + return _module->_modbterms; + // User Code End begin +} + +uint dbModulePortItr::end(dbObject* /* unused: parent */) +{ + return 0; +} + +uint dbModulePortItr::next(uint id, ...) +{ + // User Code Begin next + _dbModBTerm* modbterm = _modbterm_tbl->getPtr(id); + if (modbterm->_busPort != 0) { + _dbBlock* block = (_dbBlock*) modbterm->getOwner(); + _dbBusPort* bus_port = block->_busport_tbl->getPtr(modbterm->_busPort); + if (bus_port) { + modbterm = _modbterm_tbl->getPtr(bus_port->_last); + } + } + if (modbterm) { + return modbterm->_next_entry; + } + return 0; + // User Code End next +} + +dbObject* dbModulePortItr::getObject(uint id, ...) +{ + return _modbterm_tbl->getPtr(id); +} +} // namespace odb +// Generator Code End Cpp diff --git a/src/odb/src/db/dbModulePortItr.h b/src/odb/src/db/dbModulePortItr.h new file mode 100644 index 0000000000..00fb6124d1 --- /dev/null +++ b/src/odb/src/db/dbModulePortItr.h @@ -0,0 +1,71 @@ +/////////////////////////////////////////////////////////////////////////////// +// BSD 3-Clause License +// +// Copyright (c) 2020, The Regents of the University of California +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// * Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +// Generator Code Begin Header +#pragma once + +#include "odb/dbIterator.h" +#include "odb/odb.h" + +namespace odb { +class _dbModBTerm; + +template +class dbTable; + +class dbModulePortItr : public dbIterator +{ + public: + dbModulePortItr(dbTable<_dbModBTerm>* modbterm_tbl) + { + _modbterm_tbl = modbterm_tbl; + } + + bool reversible() override; + bool orderReversed() override; + void reverse(dbObject* parent) override; + uint sequential() override; + uint size(dbObject* parent) override; + uint begin(dbObject* parent) override; + uint end(dbObject* parent) override; + uint next(uint id, ...) override; + dbObject* getObject(uint id, ...) override; + + private: + dbTable<_dbModBTerm>* _modbterm_tbl; + // User Code Begin Fields + dbModulePortItr* _port_iter = nullptr; + // User Code End Fields +}; + +} // namespace odb + // Generator Code End Header From 45de0098704c7f288e7dd343011dc0c73e77e46d Mon Sep 17 00:00:00 2001 From: osamahammad21 Date: Mon, 5 Aug 2024 01:23:48 +0300 Subject: [PATCH 28/37] drt: update defok Signed-off-by: osamahammad21 --- src/drt/src/dr/FlexDR_init.cpp | 2 +- src/drt/src/dr/FlexDR_maze.cpp | 10 +- src/drt/test/ndr_vias1.defok | 353 ++++++++++++-------------- src/drt/test/ndr_vias2.defok | 445 ++++++++++++++++----------------- 4 files changed, 373 insertions(+), 437 deletions(-) diff --git a/src/drt/src/dr/FlexDR_init.cpp b/src/drt/src/dr/FlexDR_init.cpp index 9b417b2d61..be7d25812c 100644 --- a/src/drt/src/dr/FlexDR_init.cpp +++ b/src/drt/src/dr/FlexDR_init.cpp @@ -2037,7 +2037,7 @@ void FlexDRWorker::initNets(const frDesign* design) // fill ndrs_ for all nets in the worker for (auto& net : nets) { if (net->hasNDR()) { - ndrs_.push_back(net->getNondefaultRule()); + ndrs_.emplace_back(net->getNondefaultRule()); } } } diff --git a/src/drt/src/dr/FlexDR_maze.cpp b/src/drt/src/dr/FlexDR_maze.cpp index 77a54a791b..ad016353de 100644 --- a/src/drt/src/dr/FlexDR_maze.cpp +++ b/src/drt/src/dr/FlexDR_maze.cpp @@ -301,14 +301,11 @@ void FlexDRWorker::modMinSpacingCostPlanar(const Rect& box, // caclulate costs for NDR nets // get all unique width,spacing pairs from ndrs for (auto ndr : ndrs_) { - frCoord ndr_width; - frCoord ndr_min_spc; + frCoord ndr_width = default_width; if (ndr->getWidth(z) != 0) { ndr_width = ndr->getWidth(z); - } else { - ndr_width = default_width; } - ndr_min_spc = std::max(default_spacing, ndr->getSpacing(z)); + frCoord ndr_min_spc = std::max(default_spacing, ndr->getSpacing(z)); modMinSpacingCostPlanarHelper(box, z, type, @@ -325,7 +322,7 @@ void FlexDRWorker::modMinSpacingCostPlanar(const Rect& box, void FlexDRWorker::modMinSpacingCostPlanarHelper(const Rect& box, frMIdx z, ModCostType type, - frCoord width, + frCoord width2, frCoord minSpacing, bool isBlockage, bool isMacroPin, @@ -336,7 +333,6 @@ void FlexDRWorker::modMinSpacingCostPlanarHelper(const Rect& box, auto lNum = gridGraph_.getLayerNum(z); frCoord width1 = box.minDXDY(); // layer default width - frCoord width2 = width; frCoord halfwidth2 = width2 / 2; // spacing value needed bool use_min_spacing = isBlockage && USEMINSPACING_OBS; diff --git a/src/drt/test/ndr_vias1.defok b/src/drt/test/ndr_vias1.defok index bd356e7f80..7543083017 100644 --- a/src/drt/test/ndr_vias1.defok +++ b/src/drt/test/ndr_vias1.defok @@ -214,69 +214,72 @@ PINS 1 ; END PINS NETS 8 ; - clk ( PIN clk ) ( clkbuf_0_clk A ) + USE CLOCK + NONDEFAULTRULE NDR_3W_3S - + ROUTED met1 ( 96600 148410 210 ) ( * 151130 210 ) - NEW met1 ( 89470 151130 210 ) ( 96600 * 210 ) - NEW met2 ( 89470 340 0 ) ( * 151130 210 ) - NEW met1 ( 96600 148410 210 ) ( 110400 * 210 ) + + ROUTED met2 ( 89470 340 0 ) ( * 148410 210 ) + NEW met1 ( 89470 148410 210 ) ( 110400 * 210 ) NEW met1 ( 110400 148410 210 ) ( * 151130 210 ) NEW met1 ( 110400 151130 210 ) ( 149500 * 210 ) NEW met1 TAPER ( 149500 151130 ) ( 151110 * ) - NEW met1 ( 89470 151130 ) M1M2_PR_R + NEW met1 ( 89470 148410 ) M1M2_PR_R NEW li1 TAPER ( 151110 151130 ) L1M1_PR_R ; - clknet_0_clk ( clkbuf_2_3__f_clk A ) ( clkbuf_2_2__f_clk A ) ( clkbuf_2_1__f_clk A ) ( clkbuf_2_0__f_clk A ) ( clkbuf_0_clk X ) + USE CLOCK + NONDEFAULTRULE NDR_3W_3S - + ROUTED met1 TAPER ( 167900 118490 ) ( 169510 * ) - NEW met1 TAPER ( 167900 169830 ) ( 169510 * ) + + ROUTED met1 TAPER ( 167900 169830 ) ( 169510 * ) + NEW met1 TAPER ( 167900 118490 ) ( 169510 * ) NEW met2 ( 152030 169830 210 ) ( * 172890 210 ) NEW met1 TAPER ( 130870 172890 ) ( 132710 * ) NEW met1 ( 132710 172890 210 ) ( 152030 * 210 ) NEW met1 ( 152030 169830 210 ) ( 167900 * 210 ) + NEW met1 ( 152950 118150 210 ) ( * 118490 210 ) + NEW met2 ( 152030 118150 210 ) ( * 150450 210 ) + NEW met1 TAPER ( 152030 150450 ) ( 154790 * ) + NEW met2 ( 154790 150450 210 ) ( * 169830 210 ) + NEW met1 ( 152950 118490 210 ) ( 167900 * 210 ) + NEW met2 ( 119370 118150 210 ) ( * 118490 210 ) + NEW met2 ( 118450 118490 210 ) ( 119370 * 210 ) NEW met1 TAPER ( 116610 118490 ) ( 118220 * ) - NEW met1 TAPER ( 152490 150450 ) ( 154330 * ) - NEW met2 ( 154330 118490 210 ) ( * 150450 210 ) - NEW met2 ( 152950 150450 210 ) ( * 169830 210 ) - NEW met1 ( 118220 118490 210 ) ( 167900 * 210 ) - NEW li1 TAPER ( 169510 118490 ) L1M1_PR_R + NEW met1 ( 118220 118490 210 ) ( 118450 * 210 ) + NEW met1 ( 119370 118150 210 ) ( 152950 * 210 ) NEW li1 TAPER ( 169510 169830 ) L1M1_PR_R + NEW li1 TAPER ( 169510 118490 ) L1M1_PR_R NEW met1 ( 152030 169830 ) M1M2_PR_R NEW met1 ( 152030 172890 ) M1M2_PR_R NEW li1 TAPER ( 130870 172890 ) L1M1_PR_R - NEW met1 ( 152950 169830 ) M1M2_PR_R - NEW li1 TAPER ( 116610 118490 ) L1M1_PR_R - NEW li1 TAPER ( 152490 150450 ) L1M1_PR_R - NEW met1 TAPER ( 154330 150450 ) M1M2_PR_R - NEW met1 ( 154330 118490 ) M1M2_PR_R - NEW met1 TAPER ( 152950 150450 ) M1M2_PR_R - NEW met1 TAPER ( 152950 169830 ) RECT ( -490 -70 0 70 ) - NEW met1 TAPER ( 154330 118490 ) RECT ( -490 -70 0 70 ) - NEW met1 TAPER ( 152950 150450 ) RECT ( -490 -70 0 70 ) ; + NEW met1 ( 154790 169830 ) M1M2_PR_R + NEW li1 TAPER ( 152030 150450 ) L1M1_PR_R + NEW met1 TAPER ( 152030 150450 ) M1M2_PR_R + NEW met1 ( 152030 118150 ) M1M2_PR_R + NEW met1 ( 154790 150450 ) M1M2_PR_R + NEW met1 ( 119370 118150 ) M1M2_PR_R + NEW met1 ( 118450 118490 ) M1M2_PR_R + NEW li1 TAPER ( 116610 118490 ) L1M1_PR_R ; - clknet_2_0__leaf_clk ( _414_ CLK ) ( _418_ CLK ) ( _428_ CLK ) ( _429_ CLK ) ( _432_ CLK ) ( _434_ CLK ) ( _444_ CLK ) ( _445_ CLK ) ( clkbuf_2_0__f_clk X ) + USE CLOCK + NONDEFAULTRULE NDR_3W_3S - + ROUTED met1 ( 87630 120870 210 ) ( 91540 * 210 ) + + ROUTED met1 ( 88550 120870 210 ) ( 91540 * 210 ) NEW met1 TAPER ( 91540 120870 ) ( 93150 * ) - NEW met2 ( 87630 104890 210 ) ( * 120870 210 ) - NEW met1 ( 87630 104890 210 ) ( 87860 * 210 ) - NEW met1 TAPER ( 87860 104890 ) ( 89470 * ) + NEW met2 ( 88550 104890 210 ) ( * 120870 210 ) + NEW met1 TAPER ( 88550 104890 ) ( 89470 * ) NEW met1 ( 143750 88570 210 ) ( 144900 * 210 ) NEW met1 TAPER ( 144900 88570 ) ( 146510 * ) + NEW met1 ( 88550 118490 210 ) ( 96600 * 210 ) NEW met2 ( 125350 115430 210 ) ( * 120870 210 ) NEW met1 ( 125350 115430 210 ) ( 142140 * 210 ) NEW met1 TAPER ( 142140 115430 ) ( 143750 * ) NEW met2 ( 117530 115430 210 ) ( * 117810 210 ) NEW met1 ( 117530 115430 210 ) ( 125350 * 210 ) - NEW met2 ( 111090 118490 210 ) ( * 120870 210 ) - NEW met1 ( 111090 118490 210 ) ( 115460 * 210 ) - NEW met1 TAPER ( 115460 118490 ) ( 115690 * ) - NEW met1 TAPER ( 115690 117810 ) ( * 118490 ) - NEW met1 TAPER ( 115690 117810 ) ( 117530 * ) - NEW met2 ( 111090 120870 210 ) ( * 134470 210 ) - NEW met1 ( 87630 118490 210 ) ( 111090 * 210 ) + NEW met2 ( 111090 118150 210 ) ( * 120870 210 ) + NEW met1 ( 111090 118150 210 ) ( 112010 * 210 ) + NEW met1 ( 112010 117810 210 ) ( * 118150 210 ) + NEW met1 ( 112010 117810 210 ) ( 115460 * 210 ) + NEW met1 TAPER ( 115460 117810 ) ( 117530 * ) + NEW met2 ( 111090 120870 210 ) ( * 134810 210 ) + NEW met1 ( 96600 118150 210 ) ( * 118490 210 ) + NEW met1 ( 96600 118150 210 ) ( 111090 * 210 ) NEW met2 ( 136850 115430 210 ) ( * 148070 210 ) NEW met2 ( 143750 88570 210 ) ( * 115430 210 ) NEW li1 TAPER ( 93150 120870 ) L1M1_PR_R - NEW met1 ( 87630 120870 ) M1M2_PR_R - NEW met1 ( 87630 104890 ) M1M2_PR_R + NEW met1 ( 88550 120870 ) M1M2_PR_R + NEW met1 TAPER ( 88550 104890 ) M1M2_PR_R NEW li1 TAPER ( 89470 104890 ) L1M1_PR_R - NEW met1 ( 87630 118490 ) M1M2_PR_R + NEW met1 ( 88550 118490 ) M1M2_PR_R NEW met1 ( 143750 88570 ) M1M2_PR_R NEW li1 TAPER ( 146510 88570 ) L1M1_PR_R NEW li1 TAPER ( 136850 148070 ) L1M1_PR_R @@ -291,116 +294,98 @@ NETS 8 ; NEW met1 ( 117530 115430 ) M1M2_PR_R NEW li1 TAPER ( 111090 120870 ) L1M1_PR_R NEW met1 TAPER ( 111090 120870 ) M1M2_PR_R - NEW met1 ( 111090 118490 ) M1M2_PR_R - NEW li1 TAPER ( 111090 134470 ) L1M1_PR_R - NEW met1 TAPER ( 111090 134470 ) M1M2_PR_R - NEW met1 ( 136850 115430 ) M1M2_PR_R - NEW met2 TAPER ( 87630 118490 ) RECT ( -70 -305 70 0 ) - NEW met1 TAPER ( 136850 148070 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 143750 115430 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 125350 120870 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 117530 117810 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 111090 120870 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 111090 134470 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 136850 115430 ) RECT ( -490 -70 0 70 ) ; + NEW met1 ( 111090 118150 ) M1M2_PR_R + NEW li1 TAPER ( 111090 134810 ) L1M1_PR_R + NEW met1 TAPER ( 111090 134810 ) M1M2_PR_R + NEW met1 ( 136850 115430 ) M1M2_PR_R ; - clknet_2_1__leaf_clk ( _423_ CLK ) ( _424_ CLK ) ( _425_ CLK ) ( _426_ CLK ) ( _427_ CLK ) ( _440_ CLK ) ( _441_ CLK ) ( _442_ CLK ) ( _443_ CLK ) ( clkbuf_2_1__f_clk X ) + USE CLOCK + NONDEFAULTRULE NDR_3W_3S - + ROUTED met1 TAPER ( 205850 112710 ) ( 206310 * ) - NEW met2 ( 205850 96730 210 ) ( * 112710 210 ) - NEW met1 ( 200330 112710 210 ) ( 204700 * 210 ) - NEW met1 TAPER ( 204700 112710 ) ( 205850 * ) - NEW met1 ( 200330 129030 210 ) ( 204700 * 210 ) + + ROUTED met1 TAPER ( 163530 88230 ) ( 164450 * ) + NEW met1 ( 163530 85850 210 ) ( * 86700 210 ) + NEW met1 TAPER ( 163530 86700 ) ( * 88230 ) + NEW met1 ( 163530 85850 210 ) ( 178710 * 210 ) + NEW met2 ( 178710 85850 210 ) ( * 90950 210 ) + NEW met2 ( 158010 88230 210 ) ( * 102170 210 ) + NEW met1 ( 158010 88230 210 ) ( 162610 * 210 ) + NEW met1 TAPER ( 162610 88230 ) ( 163530 * ) + NEW met1 TAPER ( 169510 117810 ) ( 170430 * ) + NEW met1 TAPER ( 169510 117470 ) ( * 117810 ) + NEW met1 TAPER ( 168130 117470 ) ( 169510 * ) + NEW met1 ( 200330 113050 210 ) ( 204700 * 210 ) + NEW met1 TAPER ( 204700 113050 ) ( 206310 * ) + NEW met2 ( 200330 113050 210 ) ( * 117810 210 ) + NEW met1 TAPER ( 170430 117810 ) ( 173190 * ) + NEW met1 ( 173190 117810 210 ) ( 200330 * 210 ) + NEW met2 ( 199410 117810 210 ) ( * 137190 210 ) + NEW met1 ( 199410 129030 210 ) ( 204700 * 210 ) NEW met1 TAPER ( 204700 129030 ) ( 206310 * ) - NEW met2 ( 200330 112710 210 ) ( * 131100 210 ) - NEW met2 ( 199410 131100 210 ) ( 200330 * 210 ) - NEW met2 ( 199410 131100 210 ) ( * 137190 210 ) - NEW met2 ( 164450 88570 210 ) ( * 90950 210 ) - NEW met1 ( 164450 90950 210 ) ( 177100 * 210 ) - NEW met1 TAPER ( 177100 90950 ) ( 178710 * ) - NEW met2 ( 158010 88570 210 ) ( * 101830 210 ) - NEW met1 ( 158010 88570 210 ) ( 162610 * 210 ) - NEW met1 TAPER ( 162610 88570 ) ( 164450 * ) - NEW met1 TAPER ( 170890 117810 ) ( 172730 * ) - NEW met2 ( 172730 90950 210 ) ( * 117810 210 ) - NEW met2 ( 172730 117810 210 ) ( * 120530 210 ) - NEW met1 TAPER ( 168130 120530 ) ( 172730 * ) - NEW met1 ( 172730 120530 210 ) ( 200330 * 210 ) + NEW met2 ( 205850 96730 210 ) ( * 113050 210 ) NEW met1 ( 152950 129370 210 ) ( 154330 * 210 ) NEW met1 TAPER ( 154330 129370 ) ( 156170 * ) NEW met2 ( 152950 129370 210 ) ( * 148070 210 ) - NEW met2 ( 156170 120530 210 ) ( * 129370 210 ) - NEW met1 ( 156170 120530 210 ) ( 168130 * 210 ) - NEW li1 TAPER ( 206310 112710 ) L1M1_PR_R - NEW met1 TAPER ( 205850 112710 ) M1M2_PR_R + NEW met2 ( 156170 117470 210 ) ( * 129370 210 ) + NEW met2 ( 158010 102170 210 ) ( * 117470 210 ) + NEW met1 ( 156170 117470 210 ) ( 168130 * 210 ) NEW li1 TAPER ( 205850 96730 ) L1M1_PR_R NEW met1 TAPER ( 205850 96730 ) M1M2_PR_R - NEW met1 ( 200330 112710 ) M1M2_PR_R - NEW li1 TAPER ( 206310 129030 ) L1M1_PR_R - NEW met1 ( 200330 129030 ) M1M2_PR_R - NEW met1 ( 200330 120530 ) M1M2_PR_R + NEW li1 TAPER ( 164450 88230 ) L1M1_PR_R + NEW met1 ( 178710 85850 ) M1M2_PR_R + NEW li1 TAPER ( 178710 90950 ) L1M1_PR_R + NEW met1 TAPER ( 178710 90950 ) M1M2_PR_R + NEW li1 TAPER ( 158010 102170 ) L1M1_PR_R + NEW met1 TAPER ( 158010 102170 ) M1M2_PR_R + NEW met1 ( 158010 88230 ) M1M2_PR_R + NEW li1 TAPER ( 170430 117810 ) L1M1_PR_R + NEW li1 TAPER ( 206310 113050 ) L1M1_PR_R + NEW met1 ( 200330 113050 ) M1M2_PR_R + NEW met1 ( 200330 117810 ) M1M2_PR_R + NEW met1 TAPER ( 205850 113050 ) M1M2_PR_R NEW li1 TAPER ( 199410 137190 ) L1M1_PR_R NEW met1 TAPER ( 199410 137190 ) M1M2_PR_R - NEW li1 TAPER ( 164450 88570 ) L1M1_PR_R - NEW met1 TAPER ( 164450 88570 ) M1M2_PR_R - NEW met1 ( 164450 90950 ) M1M2_PR_R - NEW li1 TAPER ( 178710 90950 ) L1M1_PR_R - NEW li1 TAPER ( 158010 101830 ) L1M1_PR_R - NEW met1 TAPER ( 158010 101830 ) M1M2_PR_R - NEW met1 ( 158010 88570 ) M1M2_PR_R - NEW li1 TAPER ( 170890 117810 ) L1M1_PR_R - NEW met1 TAPER ( 172730 117810 ) M1M2_PR_R - NEW met1 ( 172730 90950 ) M1M2_PR_R - NEW met1 TAPER ( 172730 120530 ) M1M2_PR_R + NEW met1 ( 199410 117810 ) M1M2_PR_R + NEW li1 TAPER ( 206310 129030 ) L1M1_PR_R + NEW met1 ( 199410 129030 ) M1M2_PR_R NEW li1 TAPER ( 156170 129370 ) L1M1_PR_R NEW met1 ( 152950 129370 ) M1M2_PR_R NEW li1 TAPER ( 152950 148070 ) L1M1_PR_R NEW met1 TAPER ( 152950 148070 ) M1M2_PR_R - NEW met1 ( 156170 120530 ) M1M2_PR_R + NEW met1 ( 156170 117470 ) M1M2_PR_R NEW met1 TAPER ( 156170 129370 ) M1M2_PR_R - NEW met1 TAPER ( 205850 96730 ) RECT ( -355 -70 0 70 ) - NEW met2 TAPER ( 200330 129030 ) RECT ( -70 -305 70 0 ) - NEW met2 TAPER ( 200330 120530 ) RECT ( -70 -305 70 0 ) - NEW met1 TAPER ( 199410 137190 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 164450 88570 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 158010 101830 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 172730 90950 ) RECT ( -490 -70 0 70 ) - NEW met1 TAPER ( 152950 148070 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 156170 129370 ) RECT ( -490 -70 0 70 ) ; + NEW met1 ( 158010 117470 ) M1M2_PR_R ; - clknet_2_2__leaf_clk ( _411_ CLK ) ( _413_ CLK ) ( _415_ CLK ) ( _416_ CLK ) ( _417_ CLK ) ( _421_ CLK ) ( _430_ CLK ) ( _431_ CLK ) ( _433_ CLK ) ( _437_ CLK ) ( clkbuf_2_2__f_clk X ) + USE CLOCK + NONDEFAULTRULE NDR_3W_3S - + ROUTED met1 TAPER ( 98210 151130 ) ( 100050 * ) - NEW met2 ( 109250 183770 210 ) ( * 186150 210 ) + + ROUTED met2 ( 109250 183770 210 ) ( * 186150 210 ) NEW met1 ( 98210 183770 210 ) ( 107410 * 210 ) NEW met1 TAPER ( 107410 183770 ) ( 109250 * ) NEW met2 ( 96830 183770 210 ) ( * 186150 210 ) NEW met1 ( 96830 183770 210 ) ( 98210 * 210 ) + NEW met1 TAPER ( 98210 151130 ) ( 100050 * ) NEW met2 ( 98210 151130 210 ) ( * 183770 210 ) + NEW met1 TAPER ( 136850 210630 ) ( 137770 * ) + NEW met1 ( 136850 208250 210 ) ( * 209100 210 ) + NEW met1 TAPER ( 136850 209100 ) ( * 210630 ) + NEW met1 ( 136850 208250 210 ) ( 146970 * 210 ) + NEW met1 ( 146970 208250 210 ) ( * 210630 210 ) + NEW met1 ( 146970 210630 210 ) ( 148810 * 210 ) + NEW met1 TAPER ( 148810 210630 ) ( 150595 * ) + NEW met1 ( 126270 208250 210 ) ( 136850 * 210 ) NEW met2 ( 140990 159290 210 ) ( * 175270 210 ) NEW met1 ( 140990 159290 210 ) ( 142140 * 210 ) NEW met1 TAPER ( 142140 159290 ) ( 143750 * ) - NEW met2 ( 131790 172210 210 ) ( * 175270 210 ) - NEW met1 ( 131790 175270 210 ) ( 139380 * 210 ) + NEW met1 TAPER ( 130410 172210 ) ( 131790 * ) + NEW met2 ( 130410 172210 210 ) ( * 175270 210 ) + NEW met1 ( 130410 175270 210 ) ( 139380 * 210 ) NEW met1 TAPER ( 139380 175270 ) ( 140990 * ) - NEW met2 ( 125810 175270 210 ) ( * 183430 210 ) - NEW met1 ( 125810 175270 210 ) ( 131790 * 210 ) + NEW met2 ( 125810 175270 210 ) ( * 183770 210 ) + NEW met1 ( 125810 175270 210 ) ( 130410 * 210 ) + NEW met2 ( 125810 206380 210 ) ( 126270 * 210 ) + NEW met2 ( 125810 183770 210 ) ( * 206380 210 ) + NEW met2 ( 111550 197370 210 ) ( * 200090 210 ) + NEW met1 ( 111550 197370 210 ) ( 125810 * 210 ) + NEW met1 TAPER ( 125810 199750 ) ( 126270 * ) NEW met1 ( 109250 186150 210 ) ( 125810 * 210 ) - NEW met1 ( 146970 210970 210 ) ( 148810 * 210 ) - NEW met1 TAPER ( 148810 210970 ) ( 150650 * ) - NEW met1 ( 146970 210970 210 ) ( * 213350 210 ) - NEW met1 ( 144900 213350 210 ) ( 146970 * 210 ) - NEW met2 ( 125810 183430 210 ) ( * 193200 210 ) - NEW met2 ( 126270 200090 210 ) ( * 214030 210 ) - NEW met1 ( 126270 214030 210 ) ( 138230 * 210 ) - NEW met1 ( 138230 213690 210 ) ( * 214030 210 ) - NEW met1 ( 138230 213690 210 ) ( 144900 * 210 ) - NEW met1 ( 144900 213350 210 ) ( * 213690 210 ) - NEW met2 ( 137770 210970 210 ) ( * 214030 210 ) - NEW met2 ( 125810 193200 210 ) ( 126270 * 210 ) - NEW met2 ( 126270 193200 210 ) ( * 200090 210 ) - NEW met2 ( 111550 200090 210 ) ( * 200260 210 ) - NEW met3 ( 111550 200260 450 ) ( 126270 * 450 ) - NEW met1 ( 98210 151130 ) M1M2_PR_R - NEW li1 TAPER ( 100050 151130 ) L1M1_PR_R + NEW met2 ( 126270 206380 210 ) ( * 208250 210 ) + NEW met1 ( 126270 208250 ) M1M2_PR_R NEW li1 TAPER ( 109250 183770 ) L1M1_PR_R NEW met1 TAPER ( 109250 183770 ) M1M2_PR_R NEW met1 ( 109250 186150 ) M1M2_PR_R @@ -408,93 +393,75 @@ NETS 8 ; NEW li1 TAPER ( 96830 186150 ) L1M1_PR_R NEW met1 TAPER ( 96830 186150 ) M1M2_PR_R NEW met1 ( 96830 183770 ) M1M2_PR_R + NEW met1 ( 98210 151130 ) M1M2_PR_R + NEW li1 TAPER ( 100050 151130 ) L1M1_PR_R + NEW li1 TAPER ( 137770 210630 ) L1M1_PR_R + NEW li1 TAPER ( 150595 210630 ) L1M1_PR_R NEW li1 TAPER ( 140990 175270 ) L1M1_PR_R NEW met1 TAPER ( 140990 175270 ) M1M2_PR_R NEW met1 ( 140990 159290 ) M1M2_PR_R NEW li1 TAPER ( 143750 159290 ) L1M1_PR_R NEW li1 TAPER ( 131790 172210 ) L1M1_PR_R - NEW met1 TAPER ( 131790 172210 ) M1M2_PR_R - NEW met1 ( 131790 175270 ) M1M2_PR_R - NEW li1 TAPER ( 125810 183430 ) L1M1_PR_R - NEW met1 TAPER ( 125810 183430 ) M1M2_PR_R + NEW met1 TAPER ( 130410 172210 ) M1M2_PR_R + NEW met1 ( 130410 175270 ) M1M2_PR_R + NEW li1 TAPER ( 125810 183770 ) L1M1_PR_R + NEW met1 TAPER ( 125810 183770 ) M1M2_PR_R NEW met1 ( 125810 175270 ) M1M2_PR_R - NEW met1 ( 125810 186150 ) M1M2_PR_R - NEW li1 TAPER ( 150650 210970 ) L1M1_PR_R - NEW li1 TAPER ( 126270 200090 ) L1M1_PR_R - NEW met1 TAPER ( 126270 200090 ) M1M2_PR_R - NEW met1 ( 126270 214030 ) M1M2_PR_R - NEW li1 TAPER ( 137770 210970 ) L1M1_PR_R - NEW met1 TAPER ( 137770 210970 ) M1M2_PR_R - NEW met1 ( 137770 214030 ) M1M2_PR_R NEW li1 TAPER ( 111550 200090 ) L1M1_PR_R NEW met1 TAPER ( 111550 200090 ) M1M2_PR_R - NEW met2 ( 111550 200260 ) M2M3_PR - NEW met2 ( 126270 200260 ) M2M3_PR - NEW met1 TAPER ( 109250 183770 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 96830 186150 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 140990 175270 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 131790 172210 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 125810 183430 ) RECT ( -355 -70 0 70 ) - NEW met2 TAPER ( 125810 186150 ) RECT ( -70 -305 70 0 ) - NEW met1 TAPER ( 126270 200090 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 137770 210970 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 137770 214030 ) RECT ( -490 -70 0 70 ) - NEW met1 TAPER ( 111550 200090 ) RECT ( -355 -70 0 70 ) ; + NEW met1 ( 111550 197370 ) M1M2_PR_R + NEW met1 ( 125810 197370 ) M1M2_PR_R + NEW li1 TAPER ( 126270 199750 ) L1M1_PR_R + NEW met1 TAPER ( 125810 199750 ) M1M2_PR_R + NEW met1 ( 125810 186150 ) M1M2_PR_R ; - clknet_2_3__leaf_clk ( _412_ CLK ) ( _419_ CLK ) ( _420_ CLK ) ( _422_ CLK ) ( _435_ CLK ) ( _436_ CLK ) ( _438_ CLK ) ( _439_ CLK ) ( clkbuf_2_3__f_clk X ) + USE CLOCK + NONDEFAULTRULE NDR_3W_3S - + ROUTED met1 TAPER ( 204010 194310 ) ( 205850 * ) - NEW met2 ( 201250 164730 210 ) ( * 177990 210 ) - NEW met1 ( 201250 177990 210 ) ( 205620 * 210 ) - NEW met1 TAPER ( 205620 177990 ) ( 207230 * ) - NEW met1 ( 192050 177990 210 ) ( 201250 * 210 ) - NEW met2 ( 192050 153850 210 ) ( * 164730 210 ) - NEW met1 ( 192050 164730 210 ) ( 199535 * 210 ) - NEW met1 TAPER ( 199535 164730 ) ( 201250 * ) - NEW met2 ( 192050 177990 210 ) ( * 191930 210 ) - NEW met1 ( 165830 175610 210 ) ( 171580 * 210 ) + + ROUTED met1 ( 165830 175610 210 ) ( 171580 * 210 ) NEW met1 TAPER ( 171580 175610 ) ( 173190 * ) - NEW met2 ( 170430 170510 210 ) ( * 175610 210 ) - NEW met2 ( 177330 164730 210 ) ( * 170510 210 ) - NEW met1 TAPER ( 170430 170510 ) ( 173135 * ) - NEW met1 ( 173135 170510 210 ) ( 177330 * 210 ) - NEW met1 ( 177330 164730 210 ) ( 192050 * 210 ) + NEW met2 ( 170890 170510 210 ) ( * 175610 210 ) + NEW met2 ( 192050 179350 210 ) ( * 191590 210 ) + NEW met1 ( 173190 179350 210 ) ( 192050 * 210 ) + NEW met2 ( 173190 175610 210 ) ( * 179350 210 ) + NEW met1 TAPER ( 204010 194310 ) ( 205850 * ) + NEW met2 ( 192050 153850 210 ) ( * 179350 210 ) NEW met1 ( 153870 175610 210 ) ( * 176460 210 ) NEW met1 TAPER ( 153870 176460 ) ( * 177990 ) NEW met1 TAPER ( 153870 177990 ) ( 154790 * ) NEW met1 ( 153870 175610 210 ) ( 165830 * 210 ) + NEW met1 ( 192050 164730 210 ) ( 193200 * 210 ) + NEW met2 ( 201250 164390 210 ) ( * 178330 210 ) + NEW met1 ( 201250 178330 210 ) ( 205620 * 210 ) + NEW met1 TAPER ( 205620 178330 ) ( 207230 * ) + NEW met1 ( 193200 164390 210 ) ( * 164730 210 ) + NEW met1 ( 193200 164390 210 ) ( 199410 * 210 ) + NEW met1 TAPER ( 199410 164390 ) ( 201250 * ) NEW met2 ( 165830 175610 210 ) ( * 193200 210 ) NEW met2 ( 163990 193200 210 ) ( 165830 * 210 ) NEW met2 ( 163990 193200 210 ) ( * 210630 210 ) - NEW met2 ( 192050 191930 210 ) ( * 194310 210 ) + NEW met2 ( 192050 191590 210 ) ( * 194310 210 ) NEW met1 ( 192050 194310 210 ) ( 204010 * 210 ) - NEW li1 TAPER ( 192050 191930 ) L1M1_PR_R - NEW met1 TAPER ( 192050 191930 ) M1M2_PR_R + NEW met1 ( 165830 175610 ) M1M2_PR_R + NEW li1 TAPER ( 173190 175610 ) L1M1_PR_R + NEW li1 TAPER ( 170890 170510 ) L1M1_PR_R + NEW met1 TAPER ( 170890 170510 ) M1M2_PR_R + NEW met1 ( 170890 175610 ) M1M2_PR_R + NEW li1 TAPER ( 192050 191590 ) L1M1_PR_R + NEW met1 TAPER ( 192050 191590 ) M1M2_PR_R + NEW met1 ( 192050 179350 ) M1M2_PR_R + NEW met1 ( 173190 179350 ) M1M2_PR_R + NEW met1 TAPER ( 173190 175610 ) M1M2_PR_R + NEW met1 ( 192050 164730 ) M1M2_PR_R NEW li1 TAPER ( 205850 194310 ) L1M1_PR_R - NEW li1 TAPER ( 201250 164730 ) L1M1_PR_R - NEW met1 TAPER ( 201250 164730 ) M1M2_PR_R - NEW met1 ( 201250 177990 ) M1M2_PR_R - NEW li1 TAPER ( 207230 177990 ) L1M1_PR_R - NEW met1 ( 192050 177990 ) M1M2_PR_R NEW li1 TAPER ( 192050 153850 ) L1M1_PR_R NEW met1 TAPER ( 192050 153850 ) M1M2_PR_R - NEW met1 ( 192050 164730 ) M1M2_PR_R - NEW met1 ( 165830 175610 ) M1M2_PR_R - NEW li1 TAPER ( 173190 175610 ) L1M1_PR_R - NEW li1 TAPER ( 170430 170510 ) L1M1_PR_R - NEW met1 TAPER ( 170430 170510 ) M1M2_PR_R - NEW met1 ( 170430 175610 ) M1M2_PR_R - NEW met1 ( 177330 164730 ) M1M2_PR_R - NEW met1 ( 177330 170510 ) M1M2_PR_R NEW li1 TAPER ( 154790 177990 ) L1M1_PR_R + NEW li1 TAPER ( 201250 164390 ) L1M1_PR_R + NEW met1 TAPER ( 201250 164390 ) M1M2_PR_R + NEW met1 ( 201250 178330 ) M1M2_PR_R + NEW li1 TAPER ( 207230 178330 ) L1M1_PR_R NEW li1 TAPER ( 163990 210630 ) L1M1_PR_R NEW met1 TAPER ( 163990 210630 ) M1M2_PR_R - NEW met1 ( 192050 194310 ) M1M2_PR_R - NEW met1 TAPER ( 192050 191930 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 201250 164730 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 192050 153850 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 170430 170510 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 170430 175610 ) RECT ( -490 -70 0 70 ) - NEW met1 TAPER ( 163990 210630 ) RECT ( -355 -70 0 70 ) ; + NEW met1 ( 192050 194310 ) M1M2_PR_R ; - ctrl.state.out\[1\] ( _412_ Q ) ( _290_ B2 ) ( _285_ A ) + USE SIGNAL + ROUTED met1 ( 167670 208250 ) ( 170890 * ) NEW met2 ( 170890 208250 ) ( * 209950 ) @@ -506,30 +473,28 @@ NETS 8 ; NEW li1 ( 170890 209950 ) L1M1_PR_MR NEW met1 ( 170890 209950 ) M1M2_PR ; - ctrl.state.out\[2\] ( _413_ Q ) ( _297_ A ) ( _293_ A ) ( _290_ A1 ) ( _284_ A ) ( _279_ A ) + USE SIGNAL - + ROUTED met1 ( 158010 200090 ) ( * 200430 ) + + ROUTED met2 ( 158470 207570 ) ( * 209950 ) + NEW met1 ( 158010 213350 ) ( 158470 * ) + NEW met2 ( 158470 209950 ) ( * 213350 ) + NEW met1 ( 158470 207570 ) ( 166290 * ) + NEW met1 ( 158010 200090 ) ( * 200430 ) NEW met1 ( 158010 200430 ) ( 158470 * ) NEW met2 ( 158470 194650 ) ( * 200430 ) NEW met1 ( 158010 191590 ) ( 158470 * ) NEW met2 ( 158470 191590 ) ( * 194650 ) + NEW met2 ( 158470 200430 ) ( * 207570 ) NEW met1 ( 158470 194650 ) ( 167210 * ) - NEW met2 ( 158470 200430 ) ( * 207000 ) - NEW met1 ( 158010 211650 ) ( 158470 * ) - NEW met2 ( 158010 211650 ) ( * 213350 ) - NEW met2 ( 158010 207570 ) ( * 211650 ) - NEW met2 ( 158010 207000 ) ( 158470 * ) - NEW met2 ( 158010 207000 ) ( * 207570 ) - NEW met1 ( 158010 207570 ) ( 166290 * ) + NEW met1 ( 158470 207570 ) M1M2_PR + NEW li1 ( 158470 209950 ) L1M1_PR_MR + NEW met1 ( 158470 209950 ) M1M2_PR + NEW li1 ( 158010 213350 ) L1M1_PR_MR + NEW met1 ( 158470 213350 ) M1M2_PR NEW li1 ( 167210 194650 ) L1M1_PR_MR NEW li1 ( 166290 207570 ) L1M1_PR_MR NEW li1 ( 158010 200090 ) L1M1_PR_MR NEW met1 ( 158470 200430 ) M1M2_PR NEW met1 ( 158470 194650 ) M1M2_PR NEW li1 ( 158010 191590 ) L1M1_PR_MR - NEW met1 ( 158470 191590 ) M1M2_PR - NEW li1 ( 158470 211650 ) L1M1_PR_MR - NEW met1 ( 158010 211650 ) M1M2_PR - NEW li1 ( 158010 213350 ) L1M1_PR_MR - NEW met1 ( 158010 213350 ) M1M2_PR - NEW met1 ( 158010 207570 ) M1M2_PR ; + NEW met1 ( 158470 191590 ) M1M2_PR ; END NETS END DESIGN diff --git a/src/drt/test/ndr_vias2.defok b/src/drt/test/ndr_vias2.defok index 43eb640182..0be0599adf 100644 --- a/src/drt/test/ndr_vias2.defok +++ b/src/drt/test/ndr_vias2.defok @@ -220,64 +220,67 @@ NETS 8 ; + ROUTED met2 ( 89470 340 0 ) ( * 18700 210 ) NEW met3 ( 89470 18700 450 ) ( 89700 * 450 ) NEW met5 ( 89700 18700 2400 ) ( 151340 * 2400 ) - NEW met4 ( 149500 82800 450 ) ( 151340 * 450 ) - NEW met4 ( 151340 18700 450 ) ( * 82800 450 ) - NEW met3 ( 149500 145180 450 ) ( 151110 * 450 ) + NEW met3 ( 151110 145180 450 ) ( 151340 * 450 ) NEW met2 ( 151110 145180 210 ) ( * 151130 210 ) - NEW met4 ( 149500 82800 450 ) ( * 145180 450 ) + NEW met4 ( 151340 18700 450 ) ( * 145180 450 ) NEW met2 ( 89470 18700 ) M2M3_PR_R NEW met3 ( 89700 18700 ) M3M4_PR_R NEW met4 ( 89700 18700 ) M4M5_PR_R NEW met4 ( 151340 18700 ) M4M5_PR_R - NEW met3 ( 149500 145180 ) M3M4_PR_R + NEW met3 ( 151340 145180 ) M3M4_PR_R NEW met2 ( 151110 145180 ) M2M3_PR_R NEW li1 TAPER ( 151110 151130 ) L1M1_PR_R NEW met1 TAPER ( 151110 151130 ) M1M2_PR_R - NEW met3 TAPER ( 89470 18700 ) RECT ( -445 -150 0 150 ) - NEW met4 TAPER ( 89700 18700 ) RECT ( -150 -600 150 0 ) - NEW met1 TAPER ( 151110 151130 ) RECT ( -355 -70 0 70 ) ; + NEW met3 TAPER ( 89470 18700 ) RECT ( -390 -150 0 150 ) + NEW met3 TAPER ( 151340 145180 ) RECT ( 0 -150 390 150 ) ; - clknet_0_clk ( clkbuf_2_3__f_clk A ) ( clkbuf_2_2__f_clk A ) ( clkbuf_2_1__f_clk A ) ( clkbuf_2_0__f_clk A ) ( clkbuf_0_clk X ) + USE CLOCK + NONDEFAULTRULE NDR_3W_3S - + ROUTED met2 ( 116610 118830 210 ) ( * 120700 210 ) - NEW met2 ( 130870 171700 210 ) ( * 172890 210 ) - NEW met3 ( 116610 120700 450 ) ( 131100 * 450 ) - NEW met3 ( 131100 120700 450 ) ( * 121380 450 ) - NEW met3 ( 131100 121380 450 ) ( 152260 * 450 ) - NEW met4 ( 152260 121380 450 ) ( * 123420 450 ) - NEW met2 ( 169510 169830 210 ) ( * 171700 210 ) + + ROUTED met3 ( 116610 124100 450 ) ( 117300 * 450 ) + NEW met2 ( 116610 118830 210 ) ( * 124100 210 ) + NEW met4 ( 129260 171700 450 ) ( * 172380 450 ) + NEW met3 ( 129260 172380 450 ) ( * 173060 450 ) + NEW met3 ( 129260 173060 450 ) ( 130870 * 450 ) + NEW met2 ( 130870 172890 210 ) ( * 173060 210 ) + NEW met3 ( 153180 124100 450 ) ( 169510 * 450 ) + NEW met2 ( 169510 118830 210 ) ( * 124100 210 ) + NEW met4 ( 153180 124100 450 ) ( 154100 * 450 ) + NEW met5 ( 117300 124100 2400 ) ( 154100 * 2400 ) + NEW met1 ( 167210 169830 210 ) ( 167900 * 210 ) + NEW met1 TAPER ( 167900 169830 ) ( 169510 * ) + NEW met2 ( 167210 169830 210 ) ( * 171700 210 ) + NEW met3 ( 166980 171700 450 ) ( 167210 * 450 ) NEW met2 ( 152950 151300 210 ) ( * 151470 210 ) NEW met3 ( 152950 151300 450 ) ( 153180 * 450 ) NEW met4 ( 153180 151300 450 ) ( * 171700 450 ) - NEW met4 ( 152260 151300 450 ) ( 153180 * 450 ) - NEW met3 ( 130870 171700 450 ) ( 169510 * 450 ) - NEW met4 ( 152260 123420 450 ) ( * 151300 450 ) - NEW met2 ( 169510 118830 210 ) ( * 123420 210 ) - NEW met3 ( 152260 123420 450 ) ( 169510 * 450 ) - NEW met2 ( 116610 120700 ) M2M3_PR_R + NEW met5 ( 129260 171700 2400 ) ( 166980 * 2400 ) + NEW met4 ( 153180 124100 450 ) ( * 151300 450 ) + NEW met3 ( 117300 124100 ) M3M4_PR_R + NEW met4 ( 117300 124100 ) M4M5_PR_R + NEW met2 ( 116610 124100 ) M2M3_PR_R NEW li1 TAPER ( 116610 118830 ) L1M1_PR_R NEW met1 TAPER ( 116610 118830 ) M1M2_PR_R - NEW met2 ( 130870 171700 ) M2M3_PR_R + NEW met4 ( 129260 171700 ) M4M5_PR_R + NEW met3 ( 129260 172380 ) M3M4_PR_R + NEW met2 ( 130870 173060 ) M2M3_PR_R NEW li1 TAPER ( 130870 172890 ) L1M1_PR_R NEW met1 TAPER ( 130870 172890 ) M1M2_PR_R - NEW met3 ( 152260 123420 ) M3M4_PR_R - NEW met3 ( 152260 121380 ) M3M4_PR_R + NEW met3 ( 153180 124100 ) M3M4_PR_R + NEW met2 ( 169510 124100 ) M2M3_PR_R + NEW li1 TAPER ( 169510 118830 ) L1M1_PR_R + NEW met1 TAPER ( 169510 118830 ) M1M2_PR_R + NEW met4 ( 154100 124100 ) M4M5_PR_R NEW li1 TAPER ( 169510 169830 ) L1M1_PR_R - NEW met1 TAPER ( 169510 169830 ) M1M2_PR_R - NEW met2 ( 169510 171700 ) M2M3_PR_R + NEW met1 ( 167210 169830 ) M1M2_PR_R + NEW met2 ( 167210 171700 ) M2M3_PR_R + NEW met3 ( 166980 171700 ) M3M4_PR_R + NEW met4 ( 166980 171700 ) M4M5_PR_R NEW li1 TAPER ( 152950 151470 ) L1M1_PR_R NEW met1 TAPER ( 152950 151470 ) M1M2_PR_R NEW met2 ( 152950 151300 ) M2M3_PR_R NEW met3 ( 153180 151300 ) M3M4_PR_R - NEW met3 ( 153180 171700 ) M3M4_PR_R - NEW li1 TAPER ( 169510 118830 ) L1M1_PR_R - NEW met1 TAPER ( 169510 118830 ) M1M2_PR_R - NEW met2 ( 169510 123420 ) M2M3_PR_R - NEW met1 TAPER ( 116610 118830 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 130870 172890 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 169510 169830 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 152950 151470 ) RECT ( -355 -70 0 70 ) - NEW met3 TAPER ( 152950 151300 ) RECT ( -445 -150 0 150 ) - NEW met3 TAPER ( 153180 171700 ) RECT ( -630 -150 0 150 ) - NEW met1 TAPER ( 169510 118830 ) RECT ( -355 -70 0 70 ) ; + NEW met4 ( 153180 171700 ) M4M5_PR_R + NEW met3 TAPER ( 167210 171700 ) RECT ( 0 -150 390 150 ) + NEW met3 TAPER ( 152950 151300 ) RECT ( -390 -150 0 150 ) + NEW met5 TAPER ( 153180 171700 ) RECT ( -1870 -800 0 800 ) ; - clknet_2_0__leaf_clk ( _414_ CLK ) ( _418_ CLK ) ( _428_ CLK ) ( _429_ CLK ) ( _432_ CLK ) ( _434_ CLK ) ( _444_ CLK ) ( _445_ CLK ) ( clkbuf_2_0__f_clk X ) + USE CLOCK + NONDEFAULTRULE NDR_3W_3S + ROUTED met1 ( 90390 120870 210 ) ( 91540 * 210 ) @@ -288,27 +291,26 @@ NETS 8 ; NEW met2 ( 111090 120700 210 ) ( * 120870 210 ) NEW met3 ( 93150 120700 450 ) ( 111090 * 450 ) NEW met2 ( 93150 120700 210 ) ( * 120870 210 ) - NEW met1 TAPER ( 115690 118150 ) ( 117990 * ) - NEW met1 TAPER ( 115690 118150 ) ( * 118490 ) - NEW met1 ( 111090 118490 210 ) ( 115460 * 210 ) - NEW met1 TAPER ( 115460 118490 ) ( 115690 * ) - NEW met2 ( 111090 118490 210 ) ( * 120700 210 ) + NEW met1 ( 111090 118150 210 ) ( 115460 * 210 ) + NEW met1 TAPER ( 115460 118150 ) ( 117990 * ) + NEW met2 ( 111090 118150 210 ) ( * 120700 210 ) NEW met2 ( 125350 118150 210 ) ( * 120870 210 ) NEW met1 TAPER ( 117990 118150 ) ( 120060 * ) NEW met1 ( 120060 118150 210 ) ( 125350 * 210 ) + NEW met2 ( 125350 117300 210 ) ( * 118150 210 ) NEW met2 ( 111090 120870 210 ) ( * 134470 210 ) - NEW met2 ( 131330 117300 210 ) ( * 118150 210 ) - NEW met3 ( 131330 117300 450 ) ( 144900 * 450 ) - NEW met4 ( 144900 89420 450 ) ( * 117300 450 ) + NEW met2 ( 143750 113220 210 ) ( * 115430 210 ) + NEW met2 ( 143750 113220 210 ) ( 144670 * 210 ) + NEW met3 ( 144670 113220 450 ) ( 144900 * 450 ) + NEW met4 ( 144900 90100 450 ) ( * 113220 450 ) + NEW met3 ( 144900 89420 450 ) ( * 90100 450 ) NEW met3 ( 144900 89420 450 ) ( 146510 * 450 ) NEW met2 ( 146510 88570 210 ) ( * 89420 210 ) - NEW met2 ( 143750 115770 210 ) ( * 117300 210 ) - NEW met1 ( 125350 118150 210 ) ( 131330 * 210 ) - NEW met4 ( 137540 117300 450 ) ( * 131100 450 ) - NEW met4 ( 136620 131100 450 ) ( 137540 * 450 ) - NEW met4 ( 136620 131100 450 ) ( * 145180 450 ) - NEW met3 ( 136620 145180 450 ) ( 136850 * 450 ) + NEW met2 ( 143750 115430 210 ) ( * 117300 210 ) + NEW met3 ( 125350 117300 450 ) ( 143750 * 450 ) + NEW met3 ( 136850 145180 450 ) ( 137540 * 450 ) NEW met2 ( 136850 145180 210 ) ( * 148070 210 ) + NEW met4 ( 137540 117300 450 ) ( * 145180 450 ) NEW li1 TAPER ( 93150 120870 ) L1M1_PR_R NEW met1 ( 90390 120870 ) M1M2_PR_R NEW li1 TAPER ( 89470 104890 ) L1M1_PR_R @@ -319,171 +321,171 @@ NETS 8 ; NEW met2 ( 93150 120700 ) M2M3_PR_R NEW met1 TAPER ( 93150 120870 ) M1M2_PR_R NEW li1 TAPER ( 117990 118150 ) L1M1_PR_R - NEW met1 ( 111090 118490 ) M1M2_PR_R + NEW met1 ( 111090 118150 ) M1M2_PR_R NEW li1 TAPER ( 125350 120870 ) L1M1_PR_R NEW met1 TAPER ( 125350 120870 ) M1M2_PR_R NEW met1 ( 125350 118150 ) M1M2_PR_R + NEW met2 ( 125350 117300 ) M2M3_PR_R NEW li1 TAPER ( 111090 134470 ) L1M1_PR_R NEW met1 TAPER ( 111090 134470 ) M1M2_PR_R - NEW met1 ( 131330 118150 ) M1M2_PR_R - NEW met2 ( 131330 117300 ) M2M3_PR_R - NEW met3 ( 144900 117300 ) M3M4_PR_R - NEW met3 ( 144900 89420 ) M3M4_PR_R + NEW li1 TAPER ( 143750 115430 ) L1M1_PR_R + NEW met1 TAPER ( 143750 115430 ) M1M2_PR_R + NEW met2 ( 144670 113220 ) M2M3_PR_R + NEW met3 ( 144900 113220 ) M3M4_PR_R + NEW met3 ( 144900 90100 ) M3M4_PR_R NEW met2 ( 146510 89420 ) M2M3_PR_R NEW li1 TAPER ( 146510 88570 ) L1M1_PR_R NEW met1 TAPER ( 146510 88570 ) M1M2_PR_R - NEW li1 TAPER ( 143750 115770 ) L1M1_PR_R - NEW met1 TAPER ( 143750 115770 ) M1M2_PR_R NEW met2 ( 143750 117300 ) M2M3_PR_R NEW met3 ( 137540 117300 ) M3M4_PR_R - NEW met3 ( 136620 145180 ) M3M4_PR_R + NEW met3 ( 137540 145180 ) M3M4_PR_R NEW met2 ( 136850 145180 ) M2M3_PR_R NEW li1 TAPER ( 136850 148070 ) L1M1_PR_R NEW met1 TAPER ( 136850 148070 ) M1M2_PR_R - NEW met1 TAPER ( 89470 104890 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 111090 120870 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 93150 120870 ) RECT ( -490 -70 0 70 ) - NEW met1 TAPER ( 125350 120870 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 111090 134470 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 146510 88570 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 143750 115770 ) RECT ( -355 -70 0 70 ) - NEW met3 TAPER ( 143750 117300 ) RECT ( -705 -150 0 150 ) - NEW met3 TAPER ( 137540 117300 ) RECT ( -630 -150 0 150 ) - NEW met3 TAPER ( 136620 145180 ) RECT ( -435 -150 0 150 ) - NEW met1 TAPER ( 136850 148070 ) RECT ( -355 -70 0 70 ) ; + NEW met3 TAPER ( 144670 113220 ) RECT ( -390 -150 0 150 ) + NEW met3 TAPER ( 137540 117300 ) RECT ( -600 -150 0 150 ) ; - clknet_2_1__leaf_clk ( _423_ CLK ) ( _424_ CLK ) ( _425_ CLK ) ( _426_ CLK ) ( _427_ CLK ) ( _440_ CLK ) ( _441_ CLK ) ( _442_ CLK ) ( _443_ CLK ) ( clkbuf_2_1__f_clk X ) + USE CLOCK + NONDEFAULTRULE NDR_3W_3S - + ROUTED met2 ( 156170 124270 210 ) ( * 129030 210 ) - NEW met3 ( 155940 129540 450 ) ( 156170 * 450 ) - NEW met2 ( 156170 129030 210 ) ( * 129540 210 ) - NEW met2 ( 158010 102170 210 ) ( * 102340 210 ) - NEW met3 ( 155940 102340 450 ) ( 158010 * 450 ) - NEW met4 ( 155940 102340 450 ) ( * 129540 450 ) - NEW met1 ( 158010 88570 210 ) ( 162610 * 210 ) - NEW met1 TAPER ( 162610 88570 ) ( 164450 * ) - NEW met2 ( 158010 88570 210 ) ( * 102170 210 ) - NEW met1 ( 164450 90950 210 ) ( 177100 * 210 ) - NEW met1 TAPER ( 177100 90950 ) ( 178710 * ) - NEW met2 ( 164450 88570 210 ) ( * 90950 210 ) - NEW met3 ( 152950 147900 450 ) ( 155940 * 450 ) - NEW met2 ( 152950 147900 210 ) ( * 148070 210 ) - NEW met4 ( 155940 129540 450 ) ( * 147900 450 ) - NEW met1 ( 165830 117810 210 ) ( 168130 * 210 ) - NEW met1 TAPER ( 168130 117810 ) ( 170430 * ) - NEW met2 ( 165830 117810 210 ) ( * 124270 210 ) - NEW met1 ( 200330 113050 210 ) ( 204700 * 210 ) - NEW met1 TAPER ( 204700 113050 ) ( 206310 * ) - NEW met2 ( 200330 113050 210 ) ( * 117810 210 ) - NEW met1 TAPER ( 170430 117810 ) ( 173190 * ) - NEW met1 ( 173190 117810 210 ) ( 200330 * 210 ) - NEW met2 ( 199410 137020 210 ) ( * 137190 210 ) - NEW met2 ( 199410 137020 210 ) ( 199870 * 210 ) - NEW met2 ( 199870 130900 210 ) ( * 137020 210 ) - NEW met2 ( 199870 130900 210 ) ( 200330 * 210 ) - NEW met2 ( 200330 117810 210 ) ( * 130900 210 ) + + ROUTED met3 ( 200100 124780 450 ) ( 200330 * 450 ) + NEW met4 ( 200100 117300 450 ) ( * 124780 450 ) NEW met1 ( 200330 129030 210 ) ( 204700 * 210 ) NEW met1 TAPER ( 204700 129030 ) ( 206310 * ) + NEW met2 ( 206310 113050 210 ) ( * 117300 210 ) + NEW met3 ( 200100 117300 450 ) ( 206310 * 450 ) + NEW met2 ( 205850 96730 210 ) ( * 110500 210 ) + NEW met2 ( 205850 110500 210 ) ( 206310 * 210 ) + NEW met2 ( 206310 110500 210 ) ( * 113050 210 ) + NEW met2 ( 200330 124780 210 ) ( * 131100 210 ) + NEW met2 ( 199410 131100 210 ) ( 200330 * 210 ) + NEW met2 ( 199410 131100 210 ) ( * 137190 210 ) + NEW met2 ( 171350 117300 210 ) ( * 118490 210 ) + NEW met3 ( 171350 117300 450 ) ( 171580 * 450 ) + NEW met2 ( 156170 124270 210 ) ( * 129370 210 ) NEW met1 ( 156170 124270 210 ) ( 165830 * 210 ) - NEW met2 ( 205850 96390 210 ) ( * 113050 210 ) - NEW li1 TAPER ( 205850 96390 ) L1M1_PR_R - NEW met1 TAPER ( 205850 96390 ) M1M2_PR_R - NEW li1 TAPER ( 156170 129030 ) L1M1_PR_R - NEW met1 TAPER ( 156170 129030 ) M1M2_PR_R + NEW met1 ( 165830 123930 210 ) ( * 124270 210 ) + NEW met1 ( 165830 123930 210 ) ( 171350 * 210 ) + NEW met2 ( 171350 118490 210 ) ( * 123930 210 ) + NEW met3 ( 155940 129540 450 ) ( 156170 * 450 ) + NEW met2 ( 156170 129370 210 ) ( * 129540 210 ) + NEW met1 TAPER ( 157090 102170 ) ( 158010 * ) + NEW met2 ( 157090 102170 210 ) ( * 102340 210 ) + NEW met3 ( 156860 102340 450 ) ( 157090 * 450 ) + NEW met4 ( 156860 102340 450 ) ( * 127500 450 ) + NEW met4 ( 155940 127500 450 ) ( 156860 * 450 ) + NEW met4 ( 155940 127500 450 ) ( * 129540 450 ) + NEW met2 ( 178710 91290 210 ) ( * 91460 210 ) + NEW met3 ( 172500 91460 450 ) ( 178710 * 450 ) + NEW met4 ( 172500 91460 450 ) ( * 117300 450 ) + NEW met4 ( 171580 117300 450 ) ( 172500 * 450 ) + NEW met2 ( 164450 88230 210 ) ( * 89420 210 ) + NEW met3 ( 164450 89420 450 ) ( 172500 * 450 ) + NEW met3 ( 172500 89420 450 ) ( * 91460 450 ) + NEW met5 ( 171580 117300 2400 ) ( 200100 * 2400 ) + NEW met3 ( 152950 147220 450 ) ( 155940 * 450 ) + NEW met2 ( 152950 147220 210 ) ( * 148070 210 ) + NEW met4 ( 155940 129540 450 ) ( * 147220 450 ) + NEW met2 ( 200330 124780 ) M2M3_PR_R + NEW met3 ( 200100 124780 ) M3M4_PR_R + NEW met4 ( 200100 117300 ) M4M5_PR_R + NEW li1 TAPER ( 206310 129030 ) L1M1_PR_R + NEW met1 ( 200330 129030 ) M1M2_PR_R + NEW li1 TAPER ( 206310 113050 ) L1M1_PR_R + NEW met1 TAPER ( 206310 113050 ) M1M2_PR_R + NEW met2 ( 206310 117300 ) M2M3_PR_R + NEW met3 ( 200100 117300 ) M3M4_PR_R + NEW li1 TAPER ( 205850 96730 ) L1M1_PR_R + NEW met1 TAPER ( 205850 96730 ) M1M2_PR_R + NEW li1 TAPER ( 199410 137190 ) L1M1_PR_R + NEW met1 TAPER ( 199410 137190 ) M1M2_PR_R + NEW li1 TAPER ( 171350 118490 ) L1M1_PR_R + NEW met1 TAPER ( 171350 118490 ) M1M2_PR_R + NEW met2 ( 171350 117300 ) M2M3_PR_R + NEW met3 ( 171580 117300 ) M3M4_PR_R + NEW met4 ( 171580 117300 ) M4M5_PR_R + NEW li1 TAPER ( 156170 129370 ) L1M1_PR_R + NEW met1 TAPER ( 156170 129370 ) M1M2_PR_R NEW met1 ( 156170 124270 ) M1M2_PR_R + NEW met1 ( 171350 123930 ) M1M2_PR_R NEW met3 ( 155940 129540 ) M3M4_PR_R NEW met2 ( 156170 129540 ) M2M3_PR_R NEW li1 TAPER ( 158010 102170 ) L1M1_PR_R - NEW met1 TAPER ( 158010 102170 ) M1M2_PR_R - NEW met2 ( 158010 102340 ) M2M3_PR_R - NEW met3 ( 155940 102340 ) M3M4_PR_R - NEW li1 TAPER ( 164450 88570 ) L1M1_PR_R - NEW met1 ( 158010 88570 ) M1M2_PR_R - NEW li1 TAPER ( 178710 90950 ) L1M1_PR_R - NEW met1 ( 164450 90950 ) M1M2_PR_R - NEW met1 TAPER ( 164450 88570 ) M1M2_PR_R - NEW met3 ( 155940 147900 ) M3M4_PR_R - NEW met2 ( 152950 147900 ) M2M3_PR_R + NEW met1 TAPER ( 157090 102170 ) M1M2_PR_R + NEW met2 ( 157090 102340 ) M2M3_PR_R + NEW met3 ( 156860 102340 ) M3M4_PR_R + NEW li1 TAPER ( 178710 91290 ) L1M1_PR_R + NEW met1 TAPER ( 178710 91290 ) M1M2_PR_R + NEW met2 ( 178710 91460 ) M2M3_PR_R + NEW met3 ( 172500 91460 ) M3M4_PR_R + NEW li1 TAPER ( 164450 88230 ) L1M1_PR_R + NEW met1 TAPER ( 164450 88230 ) M1M2_PR_R + NEW met2 ( 164450 89420 ) M2M3_PR_R + NEW met3 ( 155940 147220 ) M3M4_PR_R + NEW met2 ( 152950 147220 ) M2M3_PR_R NEW li1 TAPER ( 152950 148070 ) L1M1_PR_R NEW met1 TAPER ( 152950 148070 ) M1M2_PR_R - NEW li1 TAPER ( 170430 117810 ) L1M1_PR_R - NEW met1 ( 165830 117810 ) M1M2_PR_R - NEW met1 ( 165830 124270 ) M1M2_PR_R - NEW li1 TAPER ( 206310 113050 ) L1M1_PR_R - NEW met1 ( 200330 113050 ) M1M2_PR_R - NEW met1 ( 200330 117810 ) M1M2_PR_R - NEW met1 TAPER ( 205850 113050 ) M1M2_PR_R - NEW li1 TAPER ( 199410 137190 ) L1M1_PR_R - NEW met1 TAPER ( 199410 137190 ) M1M2_PR_R - NEW li1 TAPER ( 206310 129030 ) L1M1_PR_R - NEW met1 ( 200330 129030 ) M1M2_PR_R - NEW met1 TAPER ( 205850 96390 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 156170 129030 ) RECT ( -355 -70 0 70 ) - NEW met3 TAPER ( 155940 129540 ) RECT ( -435 -150 0 150 ) - NEW met1 TAPER ( 158010 102170 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 164450 88570 ) RECT ( -490 -70 0 70 ) - NEW met1 TAPER ( 152950 148070 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 205850 113050 ) RECT ( -490 -70 0 70 ) - NEW met1 TAPER ( 199410 137190 ) RECT ( -355 -70 0 70 ) - NEW met2 TAPER ( 200330 129030 ) RECT ( -70 -305 70 0 ) ; + NEW met3 TAPER ( 200330 124780 ) RECT ( 0 -150 390 150 ) + NEW met4 TAPER ( 200100 117300 ) RECT ( -150 -620 150 0 ) + NEW met3 TAPER ( 171350 117300 ) RECT ( -390 -150 0 150 ) + NEW met3 TAPER ( 155940 129540 ) RECT ( -390 -150 0 150 ) + NEW met3 TAPER ( 157090 102340 ) RECT ( 0 -150 390 150 ) ; - clknet_2_2__leaf_clk ( _411_ CLK ) ( _413_ CLK ) ( _415_ CLK ) ( _416_ CLK ) ( _417_ CLK ) ( _421_ CLK ) ( _430_ CLK ) ( _431_ CLK ) ( _433_ CLK ) ( _437_ CLK ) ( clkbuf_2_2__f_clk X ) + USE CLOCK + NONDEFAULTRULE NDR_3W_3S - + ROUTED met2 ( 126270 199580 210 ) ( * 199750 210 ) - NEW met3 ( 126270 199580 450 ) ( 130180 * 450 ) - NEW met4 ( 130180 199580 450 ) ( * 212500 450 ) - NEW met2 ( 111550 199580 210 ) ( * 199750 210 ) - NEW met3 ( 111550 199580 450 ) ( 126270 * 450 ) - NEW met2 ( 130410 179690 210 ) ( * 179860 210 ) - NEW met3 ( 130180 179860 450 ) ( 130410 * 450 ) - NEW met4 ( 130180 179860 450 ) ( * 199580 450 ) - NEW met2 ( 125810 179690 210 ) ( * 183430 210 ) - NEW met1 ( 125810 179690 210 ) ( 130410 * 210 ) - NEW met2 ( 109250 183770 210 ) ( * 186150 210 ) - NEW met1 ( 109250 186150 210 ) ( 111550 * 210 ) - NEW met2 ( 111550 186150 210 ) ( * 199580 210 ) + + ROUTED met2 ( 125810 183770 210 ) ( * 183940 210 ) + NEW met3 ( 125810 183940 450 ) ( 130180 * 450 ) + NEW met4 ( 130180 183940 450 ) ( * 212500 450 ) + NEW met2 ( 130870 179690 210 ) ( * 183940 210 ) + NEW met3 ( 130180 183940 450 ) ( 130870 * 450 ) + NEW met1 TAPER ( 125810 199750 ) ( 126270 * ) + NEW met2 ( 125810 199580 210 ) ( * 199750 210 ) + NEW met3 ( 125810 199580 450 ) ( 130180 * 450 ) + NEW met2 ( 109250 183770 210 ) ( * 183940 210 ) + NEW met3 ( 109250 183940 450 ) ( 125810 * 450 ) NEW met2 ( 96830 183770 210 ) ( * 186150 210 ) NEW met1 ( 96830 183770 210 ) ( 107410 * 210 ) NEW met1 TAPER ( 107410 183770 ) ( 109250 * ) - NEW met3 ( 96830 183260 450 ) ( 97060 * 450 ) - NEW met2 ( 96830 183260 210 ) ( * 183770 210 ) + NEW met3 ( 96830 180540 450 ) ( 97060 * 450 ) + NEW met2 ( 96830 180540 210 ) ( * 183770 210 ) + NEW met1 TAPER ( 111090 199750 ) ( 111550 * ) + NEW met2 ( 111090 199580 210 ) ( * 199750 210 ) + NEW met3 ( 111090 199580 450 ) ( 125810 * 450 ) NEW met3 ( 97060 151300 450 ) ( 100050 * 450 ) NEW met2 ( 100050 151130 210 ) ( * 151300 210 ) - NEW met4 ( 97060 151300 450 ) ( * 183260 450 ) - NEW met1 ( 130410 179690 210 ) ( 131100 * 210 ) + NEW met4 ( 97060 151300 450 ) ( * 180540 450 ) NEW met2 ( 137770 210970 210 ) ( * 212500 210 ) NEW met2 ( 150650 210970 210 ) ( * 212500 210 ) NEW met3 ( 137770 212500 450 ) ( 150650 * 450 ) + NEW met1 ( 130870 179690 210 ) ( 131330 * 210 ) NEW met3 ( 130180 212500 450 ) ( 137770 * 450 ) NEW met2 ( 140990 159290 210 ) ( * 175270 210 ) NEW met1 ( 140990 159290 210 ) ( 142140 * 210 ) NEW met1 TAPER ( 142140 159290 ) ( 143750 * ) NEW met1 TAPER ( 132710 172890 ) ( 134550 * ) NEW met1 ( 134550 172890 210 ) ( 140990 * 210 ) - NEW met1 ( 131100 179350 210 ) ( 132710 * 210 ) + NEW met1 ( 131330 179350 210 ) ( 132710 * 210 ) NEW met2 ( 132710 172890 210 ) ( * 179350 210 ) - NEW met1 ( 131100 179350 210 ) ( * 179690 210 ) + NEW met1 ( 131330 179350 210 ) ( * 179690 210 ) + NEW li1 TAPER ( 125810 183770 ) L1M1_PR_R + NEW met1 TAPER ( 125810 183770 ) M1M2_PR_R + NEW met2 ( 125810 183940 ) M2M3_PR_R + NEW met3 ( 130180 183940 ) M3M4_PR_R + NEW met3 ( 130180 212500 ) M3M4_PR_R + NEW met1 ( 130870 179690 ) M1M2_PR_R + NEW met2 ( 130870 183940 ) M2M3_PR_R NEW li1 TAPER ( 126270 199750 ) L1M1_PR_R - NEW met1 TAPER ( 126270 199750 ) M1M2_PR_R - NEW met2 ( 126270 199580 ) M2M3_PR_R + NEW met1 TAPER ( 125810 199750 ) M1M2_PR_R + NEW met2 ( 125810 199580 ) M2M3_PR_R NEW met3 ( 130180 199580 ) M3M4_PR_R - NEW met3 ( 130180 212500 ) M3M4_PR_R - NEW li1 TAPER ( 111550 199750 ) L1M1_PR_R - NEW met1 TAPER ( 111550 199750 ) M1M2_PR_R - NEW met2 ( 111550 199580 ) M2M3_PR_R - NEW met1 ( 130410 179690 ) M1M2_PR_R - NEW met2 ( 130410 179860 ) M2M3_PR_R - NEW met3 ( 130180 179860 ) M3M4_PR_R - NEW li1 TAPER ( 125810 183430 ) L1M1_PR_R - NEW met1 TAPER ( 125810 183430 ) M1M2_PR_R - NEW met1 ( 125810 179690 ) M1M2_PR_R NEW li1 TAPER ( 109250 183770 ) L1M1_PR_R NEW met1 TAPER ( 109250 183770 ) M1M2_PR_R - NEW met1 ( 109250 186150 ) M1M2_PR_R - NEW met1 ( 111550 186150 ) M1M2_PR_R + NEW met2 ( 109250 183940 ) M2M3_PR_R NEW li1 TAPER ( 96830 186150 ) L1M1_PR_R NEW met1 TAPER ( 96830 186150 ) M1M2_PR_R NEW met1 ( 96830 183770 ) M1M2_PR_R - NEW met3 ( 97060 183260 ) M3M4_PR_R - NEW met2 ( 96830 183260 ) M2M3_PR_R + NEW met3 ( 97060 180540 ) M3M4_PR_R + NEW met2 ( 96830 180540 ) M2M3_PR_R + NEW li1 TAPER ( 111550 199750 ) L1M1_PR_R + NEW met1 TAPER ( 111090 199750 ) M1M2_PR_R + NEW met2 ( 111090 199580 ) M2M3_PR_R NEW met3 ( 97060 151300 ) M3M4_PR_R NEW met2 ( 100050 151300 ) M2M3_PR_R NEW li1 TAPER ( 100050 151130 ) L1M1_PR_R @@ -502,72 +504,59 @@ NETS 8 ; NEW met1 ( 140990 172890 ) M1M2_PR_R NEW met1 ( 132710 179350 ) M1M2_PR_R NEW met1 TAPER ( 132710 172890 ) M1M2_PR_R - NEW met1 TAPER ( 126270 199750 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 111550 199750 ) RECT ( -355 -70 0 70 ) - NEW met3 TAPER ( 130410 179860 ) RECT ( 0 -150 445 150 ) - NEW met1 TAPER ( 125810 183430 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 109250 183770 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 96830 186150 ) RECT ( -355 -70 0 70 ) - NEW met3 TAPER ( 97060 183260 ) RECT ( 0 -150 435 150 ) - NEW met1 TAPER ( 100050 151130 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 137770 210970 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 150650 210970 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 140990 175270 ) RECT ( -355 -70 0 70 ) - NEW met2 TAPER ( 140990 172890 ) RECT ( -70 -305 70 0 ) - NEW met1 TAPER ( 132710 172890 ) RECT ( -490 -70 0 70 ) ; + NEW met4 TAPER ( 130180 199580 ) RECT ( -150 -620 150 0 ) + NEW met3 TAPER ( 97060 180540 ) RECT ( 0 -150 390 150 ) ; - clknet_2_3__leaf_clk ( _412_ CLK ) ( _419_ CLK ) ( _420_ CLK ) ( _422_ CLK ) ( _435_ CLK ) ( _436_ CLK ) ( _438_ CLK ) ( _439_ CLK ) ( clkbuf_2_3__f_clk X ) + USE CLOCK + NONDEFAULTRULE NDR_3W_3S - + ROUTED met1 TAPER ( 191130 191590 ) ( 192050 * ) - NEW met2 ( 191130 191420 210 ) ( * 191590 210 ) - NEW met3 ( 191130 191420 450 ) ( 192740 * 450 ) + + ROUTED met1 TAPER ( 190670 191590 ) ( 192050 * ) + NEW met2 ( 190670 191420 210 ) ( * 191590 210 ) + NEW met3 ( 190670 191420 450 ) ( 192740 * 450 ) NEW met1 ( 192970 194310 210 ) ( 204010 * 210 ) NEW met1 TAPER ( 204010 194310 ) ( 205850 * ) NEW met2 ( 192970 191420 210 ) ( * 194310 210 ) NEW met3 ( 192740 191420 450 ) ( 192970 * 450 ) - NEW met2 ( 201250 164730 210 ) ( * 165580 210 ) - NEW met3 ( 201250 165580 450 ) ( 207230 * 450 ) + NEW met2 ( 201250 164390 210 ) ( * 165580 210 ) + NEW met3 ( 201250 165580 450 ) ( 206310 * 450 ) + NEW met2 ( 206310 165580 210 ) ( 207230 * 210 ) NEW met2 ( 207230 165580 210 ) ( * 177990 210 ) - NEW met3 ( 192740 179180 450 ) ( 207230 * 450 ) - NEW met2 ( 207230 177990 210 ) ( * 179180 210 ) - NEW met1 ( 193430 158950 210 ) ( 201250 * 210 ) - NEW met2 ( 201250 158950 210 ) ( * 164730 210 ) - NEW met4 ( 192740 179180 450 ) ( * 191420 450 ) + NEW met3 ( 192740 165580 450 ) ( 201250 * 450 ) + NEW met1 TAPER ( 190670 153850 ) ( 192050 * ) + NEW met2 ( 190670 153850 210 ) ( * 154020 210 ) + NEW met3 ( 190670 154020 450 ) ( 192740 * 450 ) + NEW met4 ( 192740 154020 450 ) ( * 165580 450 ) + NEW met4 ( 192740 165580 450 ) ( * 191420 450 ) NEW met3 ( 163990 207060 450 ) ( 164220 * 450 ) NEW met2 ( 163990 207060 210 ) ( * 210630 210 ) NEW met3 ( 154790 178500 450 ) ( 164220 * 450 ) NEW met2 ( 154790 178330 210 ) ( * 178500 210 ) - NEW met2 ( 173190 175610 210 ) ( * 178500 210 ) + NEW met2 ( 173190 175270 210 ) ( * 178500 210 ) NEW met3 ( 164220 178500 450 ) ( 173190 * 450 ) - NEW met2 ( 171350 169830 210 ) ( * 175610 210 ) - NEW met1 ( 171350 175610 210 ) ( 171580 * 210 ) - NEW met1 TAPER ( 171580 175610 ) ( 173190 * ) - NEW met2 ( 171350 166260 210 ) ( * 169830 210 ) + NEW met1 TAPER ( 170890 170510 ) ( 171810 * ) + NEW met2 ( 171810 170510 210 ) ( * 174420 210 ) + NEW met2 ( 171810 174420 210 ) ( 173190 * 210 ) + NEW met2 ( 173190 174420 210 ) ( * 175270 210 ) + NEW met2 ( 171810 168980 210 ) ( * 170510 210 ) NEW met4 ( 164220 178500 450 ) ( * 207060 450 ) - NEW met3 ( 171350 166260 450 ) ( 186300 * 450 ) - NEW met1 ( 192970 158610 210 ) ( 193430 * 210 ) - NEW met1 ( 192970 158270 210 ) ( * 158610 210 ) - NEW met2 ( 192970 158100 210 ) ( * 158270 210 ) - NEW met3 ( 186300 158100 450 ) ( 192970 * 450 ) - NEW met2 ( 192050 153850 210 ) ( * 158100 210 ) - NEW met4 ( 186300 158100 450 ) ( * 166260 450 ) - NEW met1 ( 193430 158610 210 ) ( * 158950 210 ) + NEW met3 ( 171810 168980 450 ) ( 192740 * 450 ) NEW li1 TAPER ( 192050 191590 ) L1M1_PR_R - NEW met1 TAPER ( 191130 191590 ) M1M2_PR_R - NEW met2 ( 191130 191420 ) M2M3_PR_R + NEW met1 TAPER ( 190670 191590 ) M1M2_PR_R + NEW met2 ( 190670 191420 ) M2M3_PR_R NEW met3 ( 192740 191420 ) M3M4_PR_R NEW li1 TAPER ( 205850 194310 ) L1M1_PR_R NEW met1 ( 192970 194310 ) M1M2_PR_R NEW met2 ( 192970 191420 ) M2M3_PR_R - NEW li1 TAPER ( 201250 164730 ) L1M1_PR_R - NEW met1 TAPER ( 201250 164730 ) M1M2_PR_R + NEW li1 TAPER ( 201250 164390 ) L1M1_PR_R + NEW met1 TAPER ( 201250 164390 ) M1M2_PR_R NEW met2 ( 201250 165580 ) M2M3_PR_R - NEW met2 ( 207230 165580 ) M2M3_PR_R + NEW met2 ( 206310 165580 ) M2M3_PR_R NEW li1 TAPER ( 207230 177990 ) L1M1_PR_R NEW met1 TAPER ( 207230 177990 ) M1M2_PR_R - NEW met3 ( 192740 179180 ) M3M4_PR_R - NEW met2 ( 207230 179180 ) M2M3_PR_R - NEW met1 ( 201250 158950 ) M1M2_PR_R - NEW met3 ( 186300 166260 ) M3M4_PR_R + NEW met3 ( 192740 165580 ) M3M4_PR_R + NEW li1 TAPER ( 192050 153850 ) L1M1_PR_R + NEW met1 TAPER ( 190670 153850 ) M1M2_PR_R + NEW met2 ( 190670 154020 ) M2M3_PR_R + NEW met3 ( 192740 154020 ) M3M4_PR_R + NEW met3 ( 192740 168980 ) M3M4_PR_R NEW met3 ( 164220 207060 ) M3M4_PR_R NEW met2 ( 163990 207060 ) M2M3_PR_R NEW li1 TAPER ( 163990 210630 ) L1M1_PR_R @@ -576,29 +565,15 @@ NETS 8 ; NEW met2 ( 154790 178500 ) M2M3_PR_R NEW li1 TAPER ( 154790 178330 ) L1M1_PR_R NEW met1 TAPER ( 154790 178330 ) M1M2_PR_R - NEW li1 TAPER ( 173190 175610 ) L1M1_PR_R - NEW met1 TAPER ( 173190 175610 ) M1M2_PR_R + NEW li1 TAPER ( 173190 175270 ) L1M1_PR_R + NEW met1 TAPER ( 173190 175270 ) M1M2_PR_R NEW met2 ( 173190 178500 ) M2M3_PR_R - NEW li1 TAPER ( 171350 169830 ) L1M1_PR_R - NEW met1 TAPER ( 171350 169830 ) M1M2_PR_R - NEW met1 ( 171350 175610 ) M1M2_PR_R - NEW met2 ( 171350 166260 ) M2M3_PR_R - NEW met1 ( 192970 158270 ) M1M2_PR_R - NEW met2 ( 192970 158100 ) M2M3_PR_R - NEW met3 ( 186300 158100 ) M3M4_PR_R - NEW li1 TAPER ( 192050 153850 ) L1M1_PR_R - NEW met1 TAPER ( 192050 153850 ) M1M2_PR_R - NEW met2 ( 192050 158100 ) M2M3_PR_R - NEW met3 TAPER ( 192970 191420 ) RECT ( 0 -150 615 150 ) - NEW met1 TAPER ( 201250 164730 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 207230 177990 ) RECT ( -355 -70 0 70 ) - NEW met3 TAPER ( 164220 207060 ) RECT ( 0 -150 435 150 ) - NEW met1 TAPER ( 163990 210630 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 154790 178330 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 173190 175610 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 171350 169830 ) RECT ( -355 -70 0 70 ) - NEW met1 TAPER ( 192050 153850 ) RECT ( -355 -70 0 70 ) - NEW met3 TAPER ( 192050 158100 ) RECT ( -705 -150 0 150 ) ; + NEW li1 TAPER ( 170890 170510 ) L1M1_PR_R + NEW met1 TAPER ( 171810 170510 ) M1M2_PR_R + NEW met2 ( 171810 168980 ) M2M3_PR_R + NEW met3 TAPER ( 192970 191420 ) RECT ( 0 -150 570 150 ) + NEW met4 TAPER ( 192740 168980 ) RECT ( -150 -620 150 0 ) + NEW met3 TAPER ( 164220 207060 ) RECT ( 0 -150 390 150 ) ; - ctrl.state.out\[1\] ( _412_ Q ) ( _290_ B2 ) ( _285_ A ) + USE SIGNAL + ROUTED met2 ( 170890 205530 ) ( * 209950 ) NEW met1 ( 167670 207910 ) ( 170890 * ) From fc8d8d2be49f558c66b84b2854bf7f5448070064 Mon Sep 17 00:00:00 2001 From: luis201420 Date: Mon, 5 Aug 2024 17:15:52 +0000 Subject: [PATCH 29/37] psm: adding unit test to insert decap cells with custom pad values Signed-off-by: luis201420 --- src/psm/test/insert_decap_with_padding1.defok | 2401 +++++++++++++++++ src/psm/test/insert_decap_with_padding1.ok | 21 + src/psm/test/insert_decap_with_padding1.tcl | 25 + src/psm/test/regression_tests.tcl | 1 + 4 files changed, 2448 insertions(+) create mode 100644 src/psm/test/insert_decap_with_padding1.defok create mode 100644 src/psm/test/insert_decap_with_padding1.ok create mode 100644 src/psm/test/insert_decap_with_padding1.tcl diff --git a/src/psm/test/insert_decap_with_padding1.defok b/src/psm/test/insert_decap_with_padding1.defok new file mode 100644 index 0000000000..5a5c614736 --- /dev/null +++ b/src/psm/test/insert_decap_with_padding1.defok @@ -0,0 +1,2401 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN gcd ; +UNITS DISTANCE MICRONS 1000 ; +DIEAREA ( 0 0 ) ( 86840 86840 ) ; +ROW ROW_0 unithd 1380 2720 N DO 183 BY 1 STEP 460 0 ; +ROW ROW_1 unithd 1380 5440 FS DO 183 BY 1 STEP 460 0 ; +ROW ROW_2 unithd 1380 8160 N DO 183 BY 1 STEP 460 0 ; +ROW ROW_3 unithd 1380 10880 FS DO 183 BY 1 STEP 460 0 ; +ROW ROW_4 unithd 1380 13600 N DO 183 BY 1 STEP 460 0 ; +ROW ROW_5 unithd 1380 16320 FS DO 183 BY 1 STEP 460 0 ; +ROW ROW_6 unithd 1380 19040 N DO 183 BY 1 STEP 460 0 ; +ROW ROW_7 unithd 1380 21760 FS DO 183 BY 1 STEP 460 0 ; +ROW ROW_8 unithd 1380 24480 N DO 183 BY 1 STEP 460 0 ; +ROW ROW_9 unithd 1380 27200 FS DO 183 BY 1 STEP 460 0 ; +ROW ROW_10 unithd 1380 29920 N DO 183 BY 1 STEP 460 0 ; +ROW ROW_11 unithd 1380 32640 FS DO 183 BY 1 STEP 460 0 ; +ROW ROW_12 unithd 1380 35360 N DO 183 BY 1 STEP 460 0 ; +ROW ROW_13 unithd 1380 38080 FS DO 183 BY 1 STEP 460 0 ; +ROW ROW_14 unithd 1380 40800 N DO 183 BY 1 STEP 460 0 ; +ROW ROW_15 unithd 1380 43520 FS DO 183 BY 1 STEP 460 0 ; +ROW ROW_16 unithd 1380 46240 N DO 183 BY 1 STEP 460 0 ; +ROW ROW_17 unithd 1380 48960 FS DO 183 BY 1 STEP 460 0 ; +ROW ROW_18 unithd 1380 51680 N DO 183 BY 1 STEP 460 0 ; +ROW ROW_19 unithd 1380 54400 FS DO 183 BY 1 STEP 460 0 ; +ROW ROW_20 unithd 1380 57120 N DO 183 BY 1 STEP 460 0 ; +ROW ROW_21 unithd 1380 59840 FS DO 183 BY 1 STEP 460 0 ; +ROW ROW_22 unithd 1380 62560 N DO 183 BY 1 STEP 460 0 ; +ROW ROW_23 unithd 1380 65280 FS DO 183 BY 1 STEP 460 0 ; +ROW ROW_24 unithd 1380 68000 N DO 183 BY 1 STEP 460 0 ; +ROW ROW_25 unithd 1380 70720 FS DO 183 BY 1 STEP 460 0 ; +ROW ROW_26 unithd 1380 73440 N DO 183 BY 1 STEP 460 0 ; +ROW ROW_27 unithd 1380 76160 FS DO 183 BY 1 STEP 460 0 ; +ROW ROW_28 unithd 1380 78880 N DO 183 BY 1 STEP 460 0 ; +ROW ROW_29 unithd 1380 81600 FS DO 183 BY 1 STEP 460 0 ; +TRACKS X 230 DO 189 STEP 460 LAYER li1 ; +TRACKS Y 170 DO 255 STEP 340 LAYER li1 ; +TRACKS X 170 DO 255 STEP 340 LAYER met1 ; +TRACKS Y 170 DO 255 STEP 340 LAYER met1 ; +TRACKS X 230 DO 189 STEP 460 LAYER met2 ; +TRACKS Y 230 DO 189 STEP 460 LAYER met2 ; +TRACKS X 340 DO 127 STEP 680 LAYER met3 ; +TRACKS Y 340 DO 127 STEP 680 LAYER met3 ; +TRACKS X 460 DO 94 STEP 920 LAYER met4 ; +TRACKS Y 460 DO 94 STEP 920 LAYER met4 ; +TRACKS X 1700 DO 25 STEP 3400 LAYER met5 ; +TRACKS Y 1700 DO 25 STEP 3400 LAYER met5 ; +GCELLGRID X 0 DO 12 STEP 6900 ; +GCELLGRID Y 0 DO 12 STEP 6900 ; +VIAS 4 ; + - via2_3_1600_480_1_5_320_320 + VIARULE M1M2_PR + CUTSIZE 150 150 + LAYERS met1 via met2 + CUTSPACING 170 170 + ENCLOSURE 85 165 55 85 + ROWCOL 1 5 ; + - via3_4_1600_480_1_4_400_400 + VIARULE M2M3_PR + CUTSIZE 200 200 + LAYERS met2 via2 met3 + CUTSPACING 200 200 + ENCLOSURE 40 85 65 65 + ROWCOL 1 4 ; + - via4_5_1600_480_1_4_400_400 + VIARULE M3M4_PR + CUTSIZE 200 200 + LAYERS met3 via3 met4 + CUTSPACING 200 200 + ENCLOSURE 90 60 100 65 + ROWCOL 1 4 ; + - via5_6_1600_1600_1_1_1600_1600 + VIARULE M4M5_PR + CUTSIZE 800 800 + LAYERS met4 via4 met5 + CUTSPACING 800 800 + ENCLOSURE 400 190 310 400 ; +END VIAS +COMPONENTS 1069 ; + - DECAP_0 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 6440 29920 ) N ; + - DECAP_1 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 7820 29920 ) N ; + - DECAP_10 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 46000 35360 ) N ; + - DECAP_100 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 81880 16320 ) FS ; + - DECAP_101 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 61180 13600 ) N ; + - DECAP_102 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 62560 13600 ) N ; + - DECAP_103 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 46460 13600 ) N ; + - DECAP_104 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 47840 13600 ) N ; + - DECAP_105 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 35880 40800 ) N ; + - DECAP_106 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 37260 40800 ) N ; + - DECAP_107 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 57040 16320 ) FS ; + - DECAP_108 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 58420 16320 ) FS ; + - DECAP_109 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 59800 16320 ) FS ; + - DECAP_11 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 47380 35360 ) N ; + - DECAP_110 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 63020 46240 ) N ; + - DECAP_111 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 77740 48960 ) FS ; + - DECAP_112 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 79120 48960 ) FS ; + - DECAP_113 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 5060 54400 ) FS ; + - DECAP_114 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 6440 54400 ) FS ; + - DECAP_115 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 6440 51680 ) N ; + - DECAP_116 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 7820 51680 ) N ; + - DECAP_117 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 25300 65280 ) FS ; + - DECAP_118 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 26680 65280 ) FS ; + - DECAP_119 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 29440 65280 ) FS ; + - DECAP_12 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 48760 35360 ) N ; + - DECAP_120 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 30820 65280 ) FS ; + - DECAP_121 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 32200 65280 ) FS ; + - DECAP_122 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 31740 62560 ) N ; + - DECAP_123 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 33120 62560 ) N ; + - DECAP_124 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 34500 62560 ) N ; + - DECAP_125 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 52900 59840 ) FS ; + - DECAP_126 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 43240 57120 ) N ; + - DECAP_127 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 53820 57120 ) N ; + - DECAP_128 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 46460 5440 ) FS ; + - DECAP_129 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 47840 5440 ) FS ; + - DECAP_13 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 5060 38080 ) FS ; + - DECAP_130 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 49220 5440 ) FS ; + - DECAP_131 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 50600 5440 ) FS ; + - DECAP_132 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 51980 5440 ) FS ; + - DECAP_133 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 53360 5440 ) FS ; + - DECAP_134 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 46460 2720 ) N ; + - DECAP_135 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 47840 2720 ) N ; + - DECAP_136 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 30820 10880 ) FS ; + - DECAP_137 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 32200 10880 ) FS ; + - DECAP_138 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 43240 8160 ) N ; + - DECAP_139 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 44620 8160 ) N ; + - DECAP_14 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 6440 38080 ) FS ; + - DECAP_140 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 46000 8160 ) N ; + - DECAP_141 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 47380 8160 ) N ; + - DECAP_142 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 48760 8160 ) N ; + - DECAP_143 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 50140 8160 ) N ; + - DECAP_144 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 51520 8160 ) N ; + - DECAP_145 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 52900 8160 ) N ; + - DECAP_146 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 54280 8160 ) N ; + - DECAP_147 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 55660 8160 ) N ; + - DECAP_148 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 57040 8160 ) N ; + - DECAP_149 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 58420 8160 ) N ; + - DECAP_15 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 7820 38080 ) FS ; + - DECAP_150 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 59800 8160 ) N ; + - DECAP_151 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 61180 8160 ) N ; + - DECAP_152 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 62560 8160 ) N ; + - DECAP_153 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 63940 8160 ) N ; + - DECAP_154 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 65320 8160 ) N ; + - DECAP_155 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 66700 8160 ) N ; + - DECAP_156 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 68080 8160 ) N ; + - DECAP_157 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 35880 10880 ) FS ; + - DECAP_158 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 37260 10880 ) FS ; + - DECAP_159 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 38640 10880 ) FS ; + - DECAP_16 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 17480 24480 ) N ; + - DECAP_160 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 40020 10880 ) FS ; + - DECAP_161 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 41400 10880 ) FS ; + - DECAP_162 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 42780 10880 ) FS ; + - DECAP_163 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 44160 10880 ) FS ; + - DECAP_164 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 45540 10880 ) FS ; + - DECAP_165 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 46920 10880 ) FS ; + - DECAP_166 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 48300 10880 ) FS ; + - DECAP_167 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 52440 10880 ) FS ; + - DECAP_168 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 53820 10880 ) FS ; + - DECAP_169 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 52440 2720 ) N ; + - DECAP_17 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 18860 24480 ) N ; + - DECAP_170 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 53820 2720 ) N ; + - DECAP_171 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 80040 54400 ) FS ; + - DECAP_172 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 68080 51680 ) N ; + - DECAP_173 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 75900 51680 ) N ; + - DECAP_174 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 77280 51680 ) N ; + - DECAP_175 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 78660 51680 ) N ; + - DECAP_176 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 80040 51680 ) N ; + - DECAP_177 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 81420 51680 ) N ; + - DECAP_178 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 82800 51680 ) N ; + - DECAP_179 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 56580 29920 ) N ; + - DECAP_18 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 14260 38080 ) FS ; + - DECAP_180 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 80500 21760 ) FS ; + - DECAP_181 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 81880 21760 ) FS ; + - DECAP_182 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 70840 19040 ) N ; + - DECAP_183 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 72220 19040 ) N ; + - DECAP_184 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 73600 19040 ) N ; + - DECAP_185 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 74980 19040 ) N ; + - DECAP_186 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 76360 19040 ) N ; + - DECAP_187 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 77740 19040 ) N ; + - DECAP_188 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 79120 19040 ) N ; + - DECAP_189 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 80500 19040 ) N ; + - DECAP_19 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 15640 38080 ) FS ; + - DECAP_190 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 81880 19040 ) N ; + - DECAP_191 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 83260 19040 ) N ; + - DECAP_192 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 66700 13600 ) N ; + - DECAP_193 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 68080 13600 ) N ; + - DECAP_194 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 70840 13600 ) N ; + - DECAP_195 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 72220 13600 ) N ; + - DECAP_196 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 73600 13600 ) N ; + - DECAP_197 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 74980 13600 ) N ; + - DECAP_198 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 76360 13600 ) N ; + - DECAP_199 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 77740 13600 ) N ; + - DECAP_2 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 9200 29920 ) N ; + - DECAP_20 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 17020 38080 ) FS ; + - DECAP_200 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 79120 13600 ) N ; + - DECAP_201 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 80500 13600 ) N ; + - DECAP_202 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 81880 13600 ) N ; + - DECAP_203 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 83260 13600 ) N ; + - DECAP_204 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 57040 2720 ) N ; + - DECAP_205 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 58420 2720 ) N ; + - DECAP_206 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 59800 2720 ) N ; + - DECAP_207 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 61180 2720 ) N ; + - DECAP_208 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 62560 2720 ) N ; + - DECAP_209 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 63940 2720 ) N ; + - DECAP_21 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 18400 38080 ) FS ; + - DECAP_210 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 36340 5440 ) FS ; + - DECAP_211 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 37720 5440 ) FS ; + - DECAP_212 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 39100 5440 ) FS ; + - DECAP_213 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 40480 5440 ) FS ; + - DECAP_214 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 41860 5440 ) FS ; + - DECAP_215 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 31280 2720 ) N ; + - DECAP_216 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 32660 2720 ) N ; + - DECAP_217 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 34040 2720 ) N ; + - DECAP_218 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 35420 2720 ) N ; + - DECAP_219 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 60260 5440 ) FS ; + - DECAP_22 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 32660 38080 ) FS ; + - DECAP_220 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 61640 5440 ) FS ; + - DECAP_221 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 63020 5440 ) FS ; + - DECAP_222 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 64400 5440 ) FS ; + - DECAP_223 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 65780 5440 ) FS ; + - DECAP_224 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 67160 5440 ) FS ; + - DECAP_225 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 68540 5440 ) FS ; + - DECAP_226 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 69920 5440 ) FS ; + - DECAP_227 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 71300 5440 ) FS ; + - DECAP_228 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 72680 5440 ) FS ; + - DECAP_229 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 74060 5440 ) FS ; + - DECAP_23 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 21620 29920 ) N ; + - DECAP_230 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 75440 5440 ) FS ; + - DECAP_231 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 76820 5440 ) FS ; + - DECAP_232 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 78200 5440 ) FS ; + - DECAP_233 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 79580 5440 ) FS ; + - DECAP_234 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 80960 5440 ) FS ; + - DECAP_235 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 67620 2720 ) N ; + - DECAP_236 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 70840 8160 ) N ; + - DECAP_237 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 72220 8160 ) N ; + - DECAP_238 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 73600 8160 ) N ; + - DECAP_239 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 74980 8160 ) N ; + - DECAP_24 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 16100 48960 ) FS ; + - DECAP_240 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 76360 8160 ) N ; + - DECAP_241 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 77740 8160 ) N ; + - DECAP_242 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 79120 8160 ) N ; + - DECAP_243 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 80500 8160 ) N ; + - DECAP_244 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 81880 8160 ) N ; + - DECAP_245 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 83260 8160 ) N ; + - DECAP_246 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 29440 5440 ) FS ; + - DECAP_247 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 30820 5440 ) FS ; + - DECAP_248 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 32200 5440 ) FS ; + - DECAP_249 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 61640 21760 ) FS ; + - DECAP_25 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 25300 48960 ) FS ; + - DECAP_250 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 63020 21760 ) FS ; + - DECAP_251 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 64400 21760 ) FS ; + - DECAP_252 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 65780 21760 ) FS ; + - DECAP_253 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 67160 21760 ) FS ; + - DECAP_254 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 68540 21760 ) FS ; + - DECAP_255 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 69920 21760 ) FS ; + - DECAP_256 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 71300 21760 ) FS ; + - DECAP_257 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 72680 21760 ) FS ; + - DECAP_258 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 59800 19040 ) N ; + - DECAP_259 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 61180 19040 ) N ; + - DECAP_26 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 26680 48960 ) FS ; + - DECAP_260 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 62560 19040 ) N ; + - DECAP_261 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 70840 2720 ) N ; + - DECAP_262 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 72220 2720 ) N ; + - DECAP_263 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 73600 2720 ) N ; + - DECAP_264 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 74980 2720 ) N ; + - DECAP_265 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 76360 2720 ) N ; + - DECAP_266 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 77740 2720 ) N ; + - DECAP_267 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 79120 2720 ) N ; + - DECAP_268 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 80500 2720 ) N ; + - DECAP_269 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 81880 2720 ) N ; + - DECAP_27 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 43240 24480 ) N ; + - DECAP_270 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 63020 51680 ) N ; + - DECAP_271 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 15640 51680 ) N ; + - DECAP_272 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 17020 51680 ) N ; + - DECAP_273 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 60260 10880 ) FS ; + - DECAP_274 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 61640 10880 ) FS ; + - DECAP_275 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 63020 10880 ) FS ; + - DECAP_276 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 18860 10880 ) FS ; + - DECAP_277 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 20240 10880 ) FS ; + - DECAP_278 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 21620 10880 ) FS ; + - DECAP_279 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 15640 8160 ) N ; + - DECAP_28 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 52900 43520 ) FS ; + - DECAP_280 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 17020 8160 ) N ; + - DECAP_281 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 18400 8160 ) N ; + - DECAP_282 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 19780 8160 ) N ; + - DECAP_283 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 21160 8160 ) N ; + - DECAP_284 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 22540 8160 ) N ; + - DECAP_285 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 23920 8160 ) N ; + - DECAP_286 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 25300 8160 ) N ; + - DECAP_287 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 26680 8160 ) N ; + - DECAP_288 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 28060 8160 ) N ; + - DECAP_289 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 29440 8160 ) N ; + - DECAP_29 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 54280 43520 ) FS ; + - DECAP_290 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 30820 8160 ) N ; + - DECAP_291 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 32200 8160 ) N ; + - DECAP_292 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 33580 8160 ) N ; + - DECAP_293 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 34960 8160 ) N ; + - DECAP_294 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 36340 8160 ) N ; + - DECAP_295 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 37720 8160 ) N ; + - DECAP_296 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 39100 8160 ) N ; + - DECAP_297 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 40480 8160 ) N ; + - DECAP_298 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 43240 68000 ) N ; + - DECAP_299 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 44620 68000 ) N ; + - DECAP_3 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 10580 29920 ) N ; + - DECAP_30 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 39560 48960 ) FS ; + - DECAP_300 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 46000 68000 ) N ; + - DECAP_301 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 47380 68000 ) N ; + - DECAP_302 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 48760 68000 ) N ; + - DECAP_303 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 50140 68000 ) N ; + - DECAP_304 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 51520 68000 ) N ; + - DECAP_305 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 52900 68000 ) N ; + - DECAP_306 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sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 48760 78880 ) N ; + - DECAP_361 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 50140 78880 ) N ; + - DECAP_362 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 51520 78880 ) N ; + - DECAP_363 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 52900 78880 ) N ; + - DECAP_364 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 54280 78880 ) N ; + - DECAP_365 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 55660 78880 ) N ; + - DECAP_366 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 57040 78880 ) N ; + - DECAP_367 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 58420 78880 ) N ; + - DECAP_368 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 59800 78880 ) N ; + - DECAP_369 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 61180 78880 ) N ; + - DECAP_37 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 49680 24480 ) N ; + - DECAP_370 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 62560 78880 ) N ; + - DECAP_371 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 63940 78880 ) N ; + - DECAP_372 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 65320 78880 ) N ; + - DECAP_373 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 66700 78880 ) N ; + - DECAP_374 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 68080 78880 ) N ; + - DECAP_375 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 76820 59840 ) FS ; + - DECAP_376 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 57040 70720 ) FS ; + - DECAP_377 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 60720 70720 ) FS ; + - DECAP_378 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 62100 70720 ) FS ; + - DECAP_379 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 63480 70720 ) FS ; + - DECAP_38 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 51060 24480 ) N ; + - DECAP_380 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 80500 62560 ) N ; + - DECAP_381 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 81880 62560 ) N ; + - DECAP_382 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 83260 62560 ) N ; + - DECAP_383 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 67620 70720 ) FS ; + - DECAP_384 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 69000 70720 ) FS ; + - DECAP_385 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 70380 70720 ) FS ; + - DECAP_386 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 71760 70720 ) FS ; + - DECAP_387 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 73140 70720 ) FS ; + - DECAP_388 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 74520 70720 ) FS ; + - DECAP_389 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 75900 70720 ) FS ; + - DECAP_39 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 52440 24480 ) N ; + - DECAP_390 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 77280 70720 ) FS ; + - DECAP_391 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 78660 70720 ) FS ; + - DECAP_392 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 80040 70720 ) FS ; + - DECAP_393 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sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 81880 78880 ) N ; + - DECAP_404 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 83260 78880 ) N ; + - DECAP_405 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 15640 81600 ) FS ; + - DECAP_406 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 17020 81600 ) FS ; + - DECAP_407 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 18400 81600 ) FS ; + - DECAP_408 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 15640 78880 ) N ; + - DECAP_409 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 17020 78880 ) N ; + - DECAP_41 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 5060 65280 ) FS ; + - DECAP_410 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 18400 78880 ) N ; + - DECAP_411 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 19780 78880 ) N ; + - DECAP_412 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 21160 78880 ) N ; + - DECAP_413 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 22540 78880 ) N ; + - DECAP_414 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sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 36340 76160 ) FS ; + - DECAP_448 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 43240 73440 ) N ; + - DECAP_449 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 44620 73440 ) N ; + - DECAP_45 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 18400 19040 ) N ; + - DECAP_450 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 46000 73440 ) N ; + - DECAP_451 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 47380 73440 ) N ; + - DECAP_452 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 48760 73440 ) N ; + - DECAP_453 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 50140 73440 ) N ; + - DECAP_454 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 51520 73440 ) N ; + - DECAP_455 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 52900 73440 ) N ; + - DECAP_456 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 54280 73440 ) N ; + - DECAP_457 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 55660 73440 ) N ; + - DECAP_458 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 57040 73440 ) N ; + - DECAP_459 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 58420 73440 ) N ; + - DECAP_46 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 72680 38080 ) FS ; + - DECAP_460 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 59800 73440 ) N ; + - DECAP_461 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 61180 73440 ) N ; + - DECAP_462 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 62560 73440 ) N ; + - DECAP_463 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 63940 73440 ) N ; + - DECAP_464 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 65320 73440 ) N ; + - DECAP_465 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 66700 73440 ) N ; + - DECAP_466 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 68080 73440 ) N ; + - DECAP_467 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 67620 81600 ) FS ; + - DECAP_468 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 15640 73440 ) N ; + - DECAP_469 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 17020 73440 ) N ; + - DECAP_47 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 65320 35360 ) N ; + - DECAP_470 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 18400 73440 ) N ; + - DECAP_471 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 19780 73440 ) N ; + - DECAP_472 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 21160 73440 ) N ; + - DECAP_473 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 22540 73440 ) N ; + - DECAP_474 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 23920 73440 ) N ; + - DECAP_475 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 25300 73440 ) N ; + - DECAP_476 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 26680 73440 ) N ; + - DECAP_477 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 28060 73440 ) N ; + - DECAP_478 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 29440 73440 ) N ; + - DECAP_479 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 30820 73440 ) N ; + - DECAP_48 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 66700 35360 ) N ; + - DECAP_480 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 32200 73440 ) N ; + - DECAP_481 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 33580 73440 ) N ; + - DECAP_482 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 34960 73440 ) N ; + - DECAP_483 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 36340 73440 ) N ; + - DECAP_484 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 37720 73440 ) N ; + - DECAP_485 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 39100 73440 ) N ; + - DECAP_486 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 40480 73440 ) N ; + - DECAP_487 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 53820 81600 ) FS ; + - DECAP_488 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 60720 81600 ) FS ; + - DECAP_489 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 62100 81600 ) FS ; + - DECAP_49 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 68080 35360 ) N ; + - DECAP_490 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 63480 81600 ) FS ; + - DECAP_491 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 57040 81600 ) FS ; + - DECAP_492 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 40940 76160 ) FS ; + - DECAP_493 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 42320 76160 ) FS ; + - DECAP_494 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 43700 76160 ) FS ; + - DECAP_495 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 45080 76160 ) FS ; + - DECAP_496 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 46460 76160 ) FS ; + - DECAP_497 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 47840 76160 ) FS ; + - DECAP_498 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 49220 76160 ) FS ; + - DECAP_499 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 50600 76160 ) FS ; + - DECAP_5 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 7360 27200 ) FS ; + - DECAP_50 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 19320 21760 ) FS ; + - DECAP_500 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 51980 76160 ) FS ; + - DECAP_501 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 53360 76160 ) FS ; + - DECAP_502 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 57040 76160 ) FS ; + - DECAP_503 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 58420 76160 ) FS ; + - DECAP_504 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 59800 76160 ) FS ; + - DECAP_505 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 61180 76160 ) FS ; + - DECAP_506 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 62560 76160 ) FS ; + - DECAP_507 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 63940 76160 ) FS ; + - DECAP_508 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 65320 76160 ) FS ; + - DECAP_509 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 66700 76160 ) FS ; + - DECAP_51 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 70840 24480 ) N ; + - DECAP_510 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 68080 76160 ) FS ; + - DECAP_511 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 69460 76160 ) FS ; + - DECAP_512 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 70840 76160 ) FS ; + - DECAP_513 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 72220 76160 ) FS ; + - DECAP_514 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 73600 76160 ) FS ; + - DECAP_515 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 74980 76160 ) FS ; + - DECAP_516 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 76360 76160 ) FS ; + - DECAP_517 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 77740 76160 ) FS ; + - DECAP_518 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 79120 76160 ) FS ; + - DECAP_519 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 80500 76160 ) FS ; + - DECAP_52 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 52900 48960 ) FS ; + - DECAP_520 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 81880 76160 ) FS ; + - DECAP_521 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 70840 73440 ) N ; + - DECAP_522 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 72220 73440 ) N ; + - DECAP_523 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 73600 73440 ) N ; + - DECAP_524 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 74980 73440 ) N ; + - DECAP_525 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 76360 73440 ) N ; + - DECAP_526 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 77740 73440 ) N ; + - DECAP_527 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 79120 73440 ) N ; + - DECAP_528 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 80500 73440 ) N ; + - DECAP_529 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 81880 73440 ) N ; + - DECAP_53 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 54280 48960 ) FS ; + - DECAP_530 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 83260 73440 ) N ; + - DECAP_54 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 72680 27200 ) FS ; + - DECAP_55 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 22080 16320 ) FS ; + - DECAP_56 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 23460 16320 ) FS ; + - DECAP_57 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 24840 16320 ) FS ; + - DECAP_58 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 26220 16320 ) FS ; + - DECAP_59 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 18860 13600 ) N ; + - DECAP_6 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 13800 27200 ) FS ; + - DECAP_60 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 52900 40800 ) N ; + - DECAP_61 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 54280 40800 ) N ; + - DECAP_62 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 55660 40800 ) N ; + - DECAP_63 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 57040 40800 ) N ; + - DECAP_64 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 59800 27200 ) FS ; + - DECAP_65 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 61180 27200 ) FS ; + - DECAP_66 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 40480 16320 ) FS ; + - DECAP_67 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 41860 16320 ) FS ; + - DECAP_68 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 35420 13600 ) N ; + - DECAP_69 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 36800 13600 ) N ; + - DECAP_7 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 15180 27200 ) FS ; + - DECAP_70 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 38180 13600 ) N ; + - DECAP_71 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 39560 13600 ) N ; + - DECAP_72 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 43240 29920 ) N ; + - DECAP_73 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 29440 16320 ) FS ; + - DECAP_74 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 15640 43520 ) FS ; + - DECAP_75 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 15640 40800 ) N ; + - DECAP_76 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 17020 40800 ) N ; + - DECAP_77 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 18400 40800 ) N ; + - DECAP_78 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 19780 40800 ) N ; + - DECAP_79 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 28060 19040 ) N ; + - DECAP_8 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 43240 35360 ) N ; + - DECAP_80 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 29440 19040 ) N ; + - DECAP_81 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 30820 19040 ) N ; + - DECAP_82 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 32200 19040 ) N ; + - DECAP_83 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 33580 19040 ) N ; + - DECAP_84 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 29440 21760 ) FS ; + - DECAP_85 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 23920 40800 ) N ; + - DECAP_86 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 25300 40800 ) N ; + - DECAP_87 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 46920 16320 ) FS ; + - DECAP_88 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 48300 21760 ) FS ; + - DECAP_89 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 49680 21760 ) FS ; + - DECAP_9 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 44620 35360 ) N ; + - DECAP_90 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 51060 21760 ) FS ; + - DECAP_91 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 52440 21760 ) FS ; + - DECAP_92 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 70840 16320 ) FS ; + - DECAP_93 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 72220 16320 ) FS ; + - DECAP_94 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 73600 16320 ) FS ; + - DECAP_95 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 74980 16320 ) FS ; + - DECAP_96 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 76360 16320 ) FS ; + - DECAP_97 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 77740 16320 ) FS ; + - DECAP_98 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 79120 16320 ) FS ; + - DECAP_99 sky130_fd_sc_hd__decap_3 + SOURCE DIST + PLACED ( 80500 16320 ) FS ; + - TAP_TAPCELL_ROW_0_0 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 15180 2720 ) N ; + - TAP_TAPCELL_ROW_0_1 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 28980 2720 ) N ; + - TAP_TAPCELL_ROW_0_2 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 42780 2720 ) N ; + - TAP_TAPCELL_ROW_0_3 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 56580 2720 ) N ; + - TAP_TAPCELL_ROW_0_4 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 70380 2720 ) N ; + - TAP_TAPCELL_ROW_0_5 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 84180 2720 ) N ; + - TAP_TAPCELL_ROW_10_33 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 15180 29920 ) N ; + - TAP_TAPCELL_ROW_10_34 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 42780 29920 ) N ; + - TAP_TAPCELL_ROW_10_35 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 70380 29920 ) N ; + - TAP_TAPCELL_ROW_11_36 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 28980 32640 ) FS ; + - TAP_TAPCELL_ROW_11_37 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 56580 32640 ) FS ; + - TAP_TAPCELL_ROW_11_38 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 84180 32640 ) FS ; + - TAP_TAPCELL_ROW_12_39 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 15180 35360 ) N ; + - TAP_TAPCELL_ROW_12_40 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 42780 35360 ) N ; + - TAP_TAPCELL_ROW_12_41 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 70380 35360 ) N ; + - TAP_TAPCELL_ROW_13_42 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 28980 38080 ) FS ; + - TAP_TAPCELL_ROW_13_43 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 56580 38080 ) FS ; + - TAP_TAPCELL_ROW_13_44 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 84180 38080 ) FS ; + - TAP_TAPCELL_ROW_14_45 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 15180 40800 ) N ; + - TAP_TAPCELL_ROW_14_46 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 42780 40800 ) N ; + - TAP_TAPCELL_ROW_14_47 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 70380 40800 ) N ; + - TAP_TAPCELL_ROW_15_48 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 28980 43520 ) FS ; + - TAP_TAPCELL_ROW_15_49 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 56580 43520 ) FS ; + - TAP_TAPCELL_ROW_15_50 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 84180 43520 ) FS ; + - TAP_TAPCELL_ROW_16_51 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 15180 46240 ) N ; + - TAP_TAPCELL_ROW_16_52 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 42780 46240 ) N ; + - TAP_TAPCELL_ROW_16_53 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 70380 46240 ) N ; + - TAP_TAPCELL_ROW_17_54 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 28980 48960 ) FS ; + - TAP_TAPCELL_ROW_17_55 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 56580 48960 ) FS ; + - TAP_TAPCELL_ROW_17_56 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 84180 48960 ) FS ; + - TAP_TAPCELL_ROW_18_57 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 15180 51680 ) N ; + - TAP_TAPCELL_ROW_18_58 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 42780 51680 ) N ; + - TAP_TAPCELL_ROW_18_59 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 70380 51680 ) N ; + - TAP_TAPCELL_ROW_19_60 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 28980 54400 ) FS ; + - TAP_TAPCELL_ROW_19_61 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 56580 54400 ) FS ; + - TAP_TAPCELL_ROW_19_62 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 84180 54400 ) FS ; + - TAP_TAPCELL_ROW_1_6 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 28980 5440 ) FS ; + - TAP_TAPCELL_ROW_1_7 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 56580 5440 ) FS ; + - TAP_TAPCELL_ROW_1_8 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 84180 5440 ) FS ; + - TAP_TAPCELL_ROW_20_63 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 15180 57120 ) N ; + - TAP_TAPCELL_ROW_20_64 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 42780 57120 ) N ; + - TAP_TAPCELL_ROW_20_65 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 70380 57120 ) N ; + - TAP_TAPCELL_ROW_21_66 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 28980 59840 ) FS ; + - TAP_TAPCELL_ROW_21_67 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 56580 59840 ) FS ; + - TAP_TAPCELL_ROW_21_68 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 84180 59840 ) FS ; + - TAP_TAPCELL_ROW_22_69 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 15180 62560 ) N ; + - TAP_TAPCELL_ROW_22_70 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 42780 62560 ) N ; + - TAP_TAPCELL_ROW_22_71 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 70380 62560 ) N ; + - TAP_TAPCELL_ROW_23_72 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 28980 65280 ) FS ; + - TAP_TAPCELL_ROW_23_73 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 56580 65280 ) FS ; + - TAP_TAPCELL_ROW_23_74 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 84180 65280 ) FS ; + - TAP_TAPCELL_ROW_24_75 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 15180 68000 ) N ; + - TAP_TAPCELL_ROW_24_76 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 42780 68000 ) N ; + - TAP_TAPCELL_ROW_24_77 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 70380 68000 ) N ; + - TAP_TAPCELL_ROW_25_78 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 28980 70720 ) FS ; + - TAP_TAPCELL_ROW_25_79 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 56580 70720 ) FS ; + - TAP_TAPCELL_ROW_25_80 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 84180 70720 ) FS ; + - TAP_TAPCELL_ROW_26_81 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 15180 73440 ) N ; + - TAP_TAPCELL_ROW_26_82 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 42780 73440 ) N ; + - TAP_TAPCELL_ROW_26_83 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 70380 73440 ) N ; + - TAP_TAPCELL_ROW_27_84 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 28980 76160 ) FS ; + - TAP_TAPCELL_ROW_27_85 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 56580 76160 ) FS ; + - TAP_TAPCELL_ROW_27_86 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 84180 76160 ) FS ; + - TAP_TAPCELL_ROW_28_87 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 15180 78880 ) N ; + - TAP_TAPCELL_ROW_28_88 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 42780 78880 ) N ; + - TAP_TAPCELL_ROW_28_89 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 70380 78880 ) N ; + - TAP_TAPCELL_ROW_29_90 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 15180 81600 ) FS ; + - TAP_TAPCELL_ROW_29_91 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 28980 81600 ) FS ; + - TAP_TAPCELL_ROW_29_92 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 42780 81600 ) FS ; + - TAP_TAPCELL_ROW_29_93 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 56580 81600 ) FS ; + - TAP_TAPCELL_ROW_29_94 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 70380 81600 ) FS ; + - TAP_TAPCELL_ROW_29_95 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 84180 81600 ) FS ; + - TAP_TAPCELL_ROW_2_10 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 42780 8160 ) N ; + - TAP_TAPCELL_ROW_2_11 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 70380 8160 ) N ; + - TAP_TAPCELL_ROW_2_9 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 15180 8160 ) N ; + - TAP_TAPCELL_ROW_3_12 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 28980 10880 ) FS ; + - TAP_TAPCELL_ROW_3_13 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 56580 10880 ) FS ; + - TAP_TAPCELL_ROW_3_14 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 84180 10880 ) FS ; + - TAP_TAPCELL_ROW_4_15 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 15180 13600 ) N ; + - TAP_TAPCELL_ROW_4_16 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 42780 13600 ) N ; + - TAP_TAPCELL_ROW_4_17 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 70380 13600 ) N ; + - TAP_TAPCELL_ROW_5_18 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 28980 16320 ) FS ; + - TAP_TAPCELL_ROW_5_19 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 56580 16320 ) FS ; + - TAP_TAPCELL_ROW_5_20 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 84180 16320 ) FS ; + - TAP_TAPCELL_ROW_6_21 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 15180 19040 ) N ; + - TAP_TAPCELL_ROW_6_22 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 42780 19040 ) N ; + - TAP_TAPCELL_ROW_6_23 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 70380 19040 ) N ; + - TAP_TAPCELL_ROW_7_24 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 28980 21760 ) FS ; + - TAP_TAPCELL_ROW_7_25 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 56580 21760 ) FS ; + - TAP_TAPCELL_ROW_7_26 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 84180 21760 ) FS ; + - TAP_TAPCELL_ROW_8_27 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 15180 24480 ) N ; + - TAP_TAPCELL_ROW_8_28 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 42780 24480 ) N ; + - TAP_TAPCELL_ROW_8_29 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 70380 24480 ) N ; + - TAP_TAPCELL_ROW_9_30 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 28980 27200 ) FS ; + - TAP_TAPCELL_ROW_9_31 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 56580 27200 ) FS ; + - TAP_TAPCELL_ROW_9_32 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 84180 27200 ) FS ; + - _358_ sky130_fd_sc_hd__nor4_1 + PLACED ( 18860 46240 ) N ; + - _361_ sky130_fd_sc_hd__nor4_1 + PLACED ( 29440 32640 ) FS ; + - _364_ sky130_fd_sc_hd__nor4_1 + PLACED ( 64400 43520 ) FS ; + - _367_ sky130_fd_sc_hd__nor4_1 + PLACED ( 57040 43520 ) FS ; + - _368_ sky130_fd_sc_hd__nand4_1 + PLACED ( 36340 46240 ) N ; + - _372_ sky130_fd_sc_hd__a22oi_1 + PLACED ( 34960 65280 ) FS ; + - _373_ sky130_fd_sc_hd__nor2_1 + PLACED ( 37720 65280 ) FS ; + - _374_ sky130_fd_sc_hd__inv_8 + PLACED ( 48760 59840 ) FS ; + - _376_ sky130_fd_sc_hd__clkinv_2 + PLACED ( 46000 62560 ) N ; + - _377_ sky130_fd_sc_hd__and3_1 + PLACED ( 40480 68000 ) N ; + - _378_ sky130_fd_sc_hd__nand2_1 + PLACED ( 39560 76160 ) FS ; + - _379_ sky130_fd_sc_hd__inv_1 + PLACED ( 37260 70720 ) FS ; + - _380_ sky130_fd_sc_hd__o211ai_1 + PLACED ( 38640 70720 ) FS ; + - _382_ sky130_fd_sc_hd__nor2_1 + PLACED ( 37260 62560 ) N ; + - _383_ sky130_fd_sc_hd__a21oi_1 + PLACED ( 38640 68000 ) N ; + - _384_ sky130_fd_sc_hd__nor2_1 + PLACED ( 35880 70720 ) FS ; + - _385_ sky130_fd_sc_hd__xor2_1 + PLACED ( 11500 24480 ) N ; + - _387_ sky130_fd_sc_hd__inv_1 + PLACED ( 74060 32640 ) FS ; + - _388_ sky130_fd_sc_hd__nor2b_1 + PLACED ( 68080 46240 ) N ; + - _389_ sky130_fd_sc_hd__nor2b_1 + PLACED ( 67160 43520 ) FS ; + - _390_ sky130_fd_sc_hd__nor2b_1 + PLACED ( 73140 57120 ) N ; + - _391_ sky130_fd_sc_hd__nand2b_1 + PLACED ( 71760 54400 ) FS ; + - _392_ sky130_fd_sc_hd__nand2b_1 + PLACED ( 74060 54400 ) FS ; + - _393_ sky130_fd_sc_hd__xor2_1 + PLACED ( 79580 43520 ) FS ; + - _394_ sky130_fd_sc_hd__nor4_1 + PLACED ( 69920 43520 ) FS ; + - _395_ sky130_fd_sc_hd__xnor2_1 + PLACED ( 57960 46240 ) N ; + - _397_ sky130_fd_sc_hd__xnor2_2 + PLACED ( 57040 51680 ) N ; + - _398_ sky130_fd_sc_hd__nand2_1 + PLACED ( 61640 46240 ) N ; + - _399_ sky130_fd_sc_hd__xor2_1 + PLACED ( 57040 38080 ) FS ; + - _400_ sky130_fd_sc_hd__nand2b_1 + PLACED ( 62100 29920 ) N ; + - _401_ sky130_fd_sc_hd__nand2b_1 + PLACED ( 58880 35360 ) N ; + - _402_ sky130_fd_sc_hd__nand2_1 + PLACED ( 62100 38080 ) FS ; + - _403_ sky130_fd_sc_hd__nor3_1 + PLACED ( 60260 38080 ) FS ; + - _404_ sky130_fd_sc_hd__nand2_1 + PLACED ( 66700 38080 ) FS ; + - _405_ sky130_fd_sc_hd__clkinvlp_4 + PLACED ( 38640 24480 ) N ; + - _406_ sky130_fd_sc_hd__nor2_2 + PLACED ( 36800 32640 ) FS ; + - _407_ sky130_fd_sc_hd__inv_1 + PLACED ( 23460 27200 ) FS ; + - _408_ sky130_fd_sc_hd__nand2b_4 + PLACED ( 17480 27200 ) FS ; + - _409_ sky130_fd_sc_hd__maj3_4 + PLACED ( 29440 27200 ) FS ; + - _410_ sky130_fd_sc_hd__nor2b_1 + PLACED ( 40480 29920 ) N ; + - _411_ sky130_fd_sc_hd__nor2_1 + PLACED ( 41400 32640 ) FS ; + - _412_ sky130_fd_sc_hd__o21ai_4 + PLACED ( 36800 35360 ) N ; + - _414_ sky130_fd_sc_hd__nand2b_1 + PLACED ( 21620 54400 ) FS ; + - _415_ sky130_fd_sc_hd__nand2b_1 + PLACED ( 19320 57120 ) N ; + - _416_ sky130_fd_sc_hd__nand2_1 + PLACED ( 21620 57120 ) N ; + - _417_ sky130_fd_sc_hd__nand2b_1 + PLACED ( 30360 38080 ) FS ; + - _419_ sky130_fd_sc_hd__nor2b_2 + PLACED ( 17480 35360 ) N ; + - _420_ sky130_fd_sc_hd__nand2_1 + PLACED ( 22540 40800 ) N ; + - _421_ sky130_fd_sc_hd__inv_1 + PLACED ( 17940 43520 ) FS ; + - _422_ sky130_fd_sc_hd__o21ai_0 + PLACED ( 23000 43520 ) FS ; + - _423_ sky130_fd_sc_hd__and4b_2 + PLACED ( 24840 43520 ) FS ; + - _424_ sky130_fd_sc_hd__nand2_1 + PLACED ( 39100 32640 ) FS ; + - _425_ sky130_fd_sc_hd__o211ai_4 + PLACED ( 35420 38080 ) FS ; + - _426_ sky130_fd_sc_hd__nand2b_2 + PLACED ( 18860 32640 ) FS ; + - _427_ sky130_fd_sc_hd__maj3_1 + PLACED ( 19320 43520 ) FS ; + - _428_ sky130_fd_sc_hd__inv_1 + PLACED ( 13800 57120 ) N ; + - _429_ sky130_fd_sc_hd__nand2b_1 + PLACED ( 15180 54400 ) FS ; + - _430_ sky130_fd_sc_hd__maj3_1 + PLACED ( 15640 57120 ) N ; + - _431_ sky130_fd_sc_hd__o21ai_4 + PLACED ( 23920 46240 ) N ; + - _432_ sky130_fd_sc_hd__a31o_2 + PLACED ( 39560 40800 ) N ; + - _433_ sky130_fd_sc_hd__inv_1 + PLACED ( 76360 48960 ) FS ; + - _434_ sky130_fd_sc_hd__maj3_1 + PLACED ( 70380 48960 ) FS ; + - _435_ sky130_fd_sc_hd__a21oi_1 + PLACED ( 72680 51680 ) N ; + - _436_ sky130_fd_sc_hd__nor2b_1 + PLACED ( 59340 43520 ) FS ; + - _437_ sky130_fd_sc_hd__inv_1 + PLACED ( 49680 46240 ) N ; + - _438_ sky130_fd_sc_hd__inv_1 + PLACED ( 50600 29920 ) N ; + - _439_ sky130_fd_sc_hd__nor2b_1 + PLACED ( 54280 32640 ) FS ; + - _440_ sky130_fd_sc_hd__o31ai_4 + PLACED ( 51060 35360 ) N ; + - _441_ sky130_fd_sc_hd__maj3_1 + PLACED ( 54280 46240 ) N ; + - _442_ sky130_fd_sc_hd__nand2b_1 + PLACED ( 61640 43520 ) FS ; + - _443_ sky130_fd_sc_hd__o211ai_2 + PLACED ( 62100 40800 ) N ; + - _444_ sky130_fd_sc_hd__o211a_1 + PLACED ( 66700 40800 ) N ; + - _445_ sky130_fd_sc_hd__maj3_4 + PLACED ( 72680 35360 ) N ; + - _446_ sky130_fd_sc_hd__nand2_8 + PLACED ( 39100 59840 ) FS ; + - _448_ sky130_fd_sc_hd__mux2i_1 + PLACED ( 10120 27200 ) FS ; + - _450_ sky130_fd_sc_hd__nand2_1 + PLACED ( 2300 27200 ) FS ; + - _451_ sky130_fd_sc_hd__o21ai_0 + PLACED ( 4140 27200 ) FS ; + - _453_ sky130_fd_sc_hd__inv_1 + PLACED ( 26680 19040 ) N ; + - _454_ sky130_fd_sc_hd__inv_1 + PLACED ( 72680 29920 ) N ; + - _455_ sky130_fd_sc_hd__o211ai_2 + PLACED ( 68080 38080 ) FS ; + - _456_ sky130_fd_sc_hd__maj3_4 + PLACED ( 69000 32640 ) FS ; + - _458_ sky130_fd_sc_hd__nor3_1 + PLACED ( 21620 21760 ) FS ; + - _459_ sky130_fd_sc_hd__a21oi_1 + PLACED ( 21160 19040 ) N ; + - _460_ sky130_fd_sc_hd__nand2_1 + PLACED ( 17480 10880 ) FS ; + - _461_ sky130_fd_sc_hd__o21ai_0 + PLACED ( 17020 13600 ) N ; + - _462_ sky130_fd_sc_hd__nor3_1 + PLACED ( 31740 21760 ) FS ; + - _463_ sky130_fd_sc_hd__a21oi_1 + PLACED ( 33580 21760 ) FS ; + - _464_ sky130_fd_sc_hd__nand2_1 + PLACED ( 34500 10880 ) FS ; + - _465_ sky130_fd_sc_hd__o21ai_0 + PLACED ( 33580 13600 ) N ; + - _466_ sky130_fd_sc_hd__inv_1 + PLACED ( 30360 43520 ) FS ; + - _468_ sky130_fd_sc_hd__nor3_1 + PLACED ( 29440 48960 ) FS ; + - _469_ sky130_fd_sc_hd__a21oi_1 + PLACED ( 28980 51680 ) N ; + - _471_ sky130_fd_sc_hd__nand2_1 + PLACED ( 8740 54400 ) FS ; + - _472_ sky130_fd_sc_hd__o21ai_0 + PLACED ( 27140 51680 ) N ; + - _473_ sky130_fd_sc_hd__inv_1 + PLACED ( 11500 35360 ) N ; + - _474_ sky130_fd_sc_hd__nor3_1 + PLACED ( 12420 38080 ) FS ; + - _475_ sky130_fd_sc_hd__a21oi_1 + PLACED ( 10580 38080 ) FS ; + - _476_ sky130_fd_sc_hd__nand2_1 + PLACED ( 1380 38080 ) FS ; + - _477_ sky130_fd_sc_hd__o21ai_0 + PLACED ( 3220 38080 ) FS ; + - _478_ sky130_fd_sc_hd__inv_1 + PLACED ( 9660 46240 ) N ; + - _479_ sky130_fd_sc_hd__nor3_1 + PLACED ( 11040 48960 ) FS ; + - _480_ sky130_fd_sc_hd__a21oi_1 + PLACED ( 10580 51680 ) N ; + - _481_ sky130_fd_sc_hd__nand2_1 + PLACED ( 5060 51680 ) N ; + - _482_ sky130_fd_sc_hd__o21ai_0 + PLACED ( 3220 51680 ) N ; + - _483_ sky130_fd_sc_hd__mux2i_1 + PLACED ( 11500 54400 ) FS ; + - _484_ sky130_fd_sc_hd__nand2_1 + PLACED ( 1380 57120 ) N ; + - _485_ sky130_fd_sc_hd__o21ai_0 + PLACED ( 3220 54400 ) FS ; + - _486_ sky130_fd_sc_hd__inv_1 + PLACED ( 11500 65280 ) FS ; + - _487_ sky130_fd_sc_hd__nor3_1 + PLACED ( 11040 62560 ) N ; + - _488_ sky130_fd_sc_hd__a21oi_1 + PLACED ( 9200 62560 ) N ; + - _489_ sky130_fd_sc_hd__nand2_1 + PLACED ( 3220 62560 ) N ; + - _490_ sky130_fd_sc_hd__o21ai_0 + PLACED ( 4600 62560 ) N ; + - _491_ sky130_fd_sc_hd__nor3_1 + PLACED ( 47840 24480 ) N ; + - _492_ sky130_fd_sc_hd__a21oi_1 + PLACED ( 46460 21760 ) FS ; + - _493_ sky130_fd_sc_hd__nand2_1 + PLACED ( 45080 13600 ) N ; + - _494_ sky130_fd_sc_hd__o21ai_0 + PLACED ( 45080 16320 ) FS ; + - _495_ sky130_fd_sc_hd__mux2i_1 + PLACED ( 52900 19040 ) N ; + - _496_ sky130_fd_sc_hd__nand2_1 + PLACED ( 51060 10880 ) FS ; + - _497_ sky130_fd_sc_hd__o21ai_0 + PLACED ( 50140 13600 ) N ; + - _498_ sky130_fd_sc_hd__inv_1 + PLACED ( 53820 51680 ) N ; + - _499_ sky130_fd_sc_hd__nor3_1 + PLACED ( 44160 54400 ) FS ; + - _500_ sky130_fd_sc_hd__a21oi_1 + PLACED ( 42320 54400 ) FS ; + - _501_ sky130_fd_sc_hd__nand2_1 + PLACED ( 38640 62560 ) N ; + - _502_ sky130_fd_sc_hd__o21ai_0 + PLACED ( 38180 54400 ) FS ; + - _504_ sky130_fd_sc_hd__mux2i_1 + PLACED ( 52440 62560 ) N ; + - _505_ sky130_fd_sc_hd__nand2_1 + PLACED ( 51520 70720 ) FS ; + - _506_ sky130_fd_sc_hd__o21ai_0 + PLACED ( 50600 62560 ) N ; + - _507_ sky130_fd_sc_hd__mux2i_1 + PLACED ( 65320 19040 ) N ; + - _508_ sky130_fd_sc_hd__nand2_1 + PLACED ( 65780 10880 ) FS ; + - _509_ sky130_fd_sc_hd__o21ai_0 + PLACED ( 64860 13600 ) N ; + - _510_ sky130_fd_sc_hd__inv_1 + PLACED ( 74520 51680 ) N ; + - _511_ sky130_fd_sc_hd__nor3_1 + PLACED ( 76360 54400 ) FS ; + - _512_ sky130_fd_sc_hd__a21oi_1 + PLACED ( 75900 57120 ) N ; + - _513_ sky130_fd_sc_hd__nand2_1 + PLACED ( 80040 59840 ) FS ; + - _514_ sky130_fd_sc_hd__o21ai_0 + PLACED ( 78200 54400 ) FS ; + - _515_ sky130_fd_sc_hd__mux2i_1 + PLACED ( 73600 65280 ) FS ; + - _516_ sky130_fd_sc_hd__nand2_1 + PLACED ( 80040 65280 ) FS ; + - _517_ sky130_fd_sc_hd__o21ai_0 + PLACED ( 77280 65280 ) FS ; + - _518_ sky130_fd_sc_hd__o21ai_0 + PLACED ( 74980 27200 ) FS ; + - _519_ sky130_fd_sc_hd__nand2_1 + PLACED ( 77740 21760 ) FS ; + - _520_ sky130_fd_sc_hd__o21ai_0 + PLACED ( 75900 21760 ) FS ; + - _521_ sky130_fd_sc_hd__a21oi_1 + PLACED ( 10120 21760 ) FS ; + - _523_ sky130_fd_sc_hd__nand3_1 + PLACED ( 15640 24480 ) N ; + - _524_ sky130_fd_sc_hd__o22ai_1 + PLACED ( 13340 21760 ) FS ; + - _525_ sky130_fd_sc_hd__nand2_1 + PLACED ( 3680 21760 ) FS ; + - _526_ sky130_fd_sc_hd__o31ai_1 + PLACED ( 5980 21760 ) FS ; + - _527_ sky130_fd_sc_hd__nor2b_1 + PLACED ( 17020 21760 ) FS ; + - _529_ sky130_fd_sc_hd__o21ai_0 + PLACED ( 26220 21760 ) FS ; + - _530_ sky130_fd_sc_hd__nor2_1 + PLACED ( 24840 27200 ) FS ; + - _531_ sky130_fd_sc_hd__nor2_1 + PLACED ( 27140 24480 ) N ; + - _532_ sky130_fd_sc_hd__a21oi_1 + PLACED ( 28980 24480 ) N ; + - _533_ sky130_fd_sc_hd__a21oi_1 + PLACED ( 22080 24480 ) N ; + - _534_ sky130_fd_sc_hd__o32ai_1 + PLACED ( 23920 24480 ) N ; + - _535_ sky130_fd_sc_hd__a31oi_1 + PLACED ( 23920 21760 ) FS ; + - _536_ sky130_fd_sc_hd__nand2_1 + PLACED ( 29440 10880 ) FS ; + - _537_ sky130_fd_sc_hd__o21ai_0 + PLACED ( 24840 19040 ) N ; + - _538_ sky130_fd_sc_hd__a21oi_1 + PLACED ( 27140 27200 ) FS ; + - _539_ sky130_fd_sc_hd__or2_0 + PLACED ( 31280 24480 ) N ; + - _540_ sky130_fd_sc_hd__o21ai_0 + PLACED ( 34040 24480 ) N ; + - _541_ sky130_fd_sc_hd__nor3_1 + PLACED ( 34500 29920 ) N ; + - _542_ sky130_fd_sc_hd__a21oi_1 + PLACED ( 37720 29920 ) N ; + - _543_ sky130_fd_sc_hd__a21oi_1 + PLACED ( 34960 27200 ) FS ; + - _544_ sky130_fd_sc_hd__o32ai_1 + PLACED ( 36800 27200 ) FS ; + - _545_ sky130_fd_sc_hd__a31oi_1 + PLACED ( 35880 24480 ) N ; + - _546_ sky130_fd_sc_hd__nand2_1 + PLACED ( 39560 19040 ) N ; + - _547_ sky130_fd_sc_hd__o21ai_0 + PLACED ( 36800 19040 ) N ; + - _548_ sky130_fd_sc_hd__o21ai_2 + PLACED ( 33580 35360 ) N ; + - _549_ sky130_fd_sc_hd__a21oi_1 + PLACED ( 38640 46240 ) N ; + - _550_ sky130_fd_sc_hd__nor3_1 + PLACED ( 37720 48960 ) FS ; + - _552_ sky130_fd_sc_hd__a21oi_1 + PLACED ( 36340 43520 ) FS ; + - _553_ sky130_fd_sc_hd__nand2_1 + PLACED ( 33120 43520 ) FS ; + - _554_ sky130_fd_sc_hd__nand2_1 + PLACED ( 31740 46240 ) N ; + - _555_ sky130_fd_sc_hd__o21ai_0 + PLACED ( 33120 46240 ) N ; + - _556_ sky130_fd_sc_hd__and3_1 + PLACED ( 32200 48960 ) FS ; + - _557_ sky130_fd_sc_hd__nand2_1 + PLACED ( 8280 46240 ) N ; + - _558_ sky130_fd_sc_hd__o41ai_1 + PLACED ( 34500 48960 ) FS ; + - _559_ sky130_fd_sc_hd__nor2b_2 + PLACED ( 32660 40800 ) N ; + - _560_ sky130_fd_sc_hd__a2111oi_4 + PLACED ( 24380 29920 ) N ; + - _561_ sky130_fd_sc_hd__nand2b_1 + PLACED ( 33120 32640 ) FS ; + - _562_ sky130_fd_sc_hd__o21ai_2 + PLACED ( 28980 35360 ) N ; + - _563_ sky130_fd_sc_hd__nor2_1 + PLACED ( 27140 35360 ) N ; + - _564_ sky130_fd_sc_hd__o21ai_0 + PLACED ( 11040 32640 ) FS ; + - _565_ sky130_fd_sc_hd__inv_1 + PLACED ( 16560 29920 ) N ; + - _566_ sky130_fd_sc_hd__nand3_1 + PLACED ( 13340 35360 ) N ; + - _567_ sky130_fd_sc_hd__o21ai_0 + PLACED ( 15640 35360 ) N ; + - _568_ sky130_fd_sc_hd__nand2_1 + PLACED ( 20240 29920 ) N ; + - _569_ sky130_fd_sc_hd__nand2_1 + PLACED ( 18860 29920 ) N ; + - _570_ sky130_fd_sc_hd__a32o_1 + PLACED ( 15180 32640 ) FS ; + - _571_ sky130_fd_sc_hd__a31oi_1 + PLACED ( 12880 32640 ) FS ; + - _572_ sky130_fd_sc_hd__nand2_1 + PLACED ( 3220 29920 ) N ; + - _573_ sky130_fd_sc_hd__o21ai_0 + PLACED ( 4600 29920 ) N ; + - _574_ sky130_fd_sc_hd__o31ai_4 + PLACED ( 21160 38080 ) FS ; + - _575_ sky130_fd_sc_hd__nand2_1 + PLACED ( 11960 40800 ) N ; + - _576_ sky130_fd_sc_hd__a211oi_1 + PLACED ( 12880 43520 ) FS ; + - _577_ sky130_fd_sc_hd__nand2_1 + PLACED ( 15640 46240 ) N ; + - _578_ sky130_fd_sc_hd__nand2_1 + PLACED ( 12880 48960 ) FS ; + - _579_ sky130_fd_sc_hd__o21ai_0 + PLACED ( 14260 48960 ) FS ; + - _580_ sky130_fd_sc_hd__o21ai_0 + PLACED ( 17020 46240 ) N ; + - _581_ sky130_fd_sc_hd__a32o_1 + PLACED ( 11500 46240 ) N ; + - _582_ sky130_fd_sc_hd__nand2_1 + PLACED ( 6900 46240 ) N ; + - _583_ sky130_fd_sc_hd__o31ai_1 + PLACED ( 9660 43520 ) FS ; + - _584_ sky130_fd_sc_hd__inv_1 + PLACED ( 21620 59840 ) FS ; + - _585_ sky130_fd_sc_hd__nand2_1 + PLACED ( 21160 46240 ) N ; + - _586_ sky130_fd_sc_hd__nor2_1 + PLACED ( 22540 46240 ) N ; + - _587_ sky130_fd_sc_hd__a21oi_2 + PLACED ( 22080 48960 ) FS ; + - _588_ sky130_fd_sc_hd__nor3_1 + PLACED ( 25760 57120 ) N ; + - _589_ sky130_fd_sc_hd__a21o_1 + PLACED ( 24380 62560 ) N ; + - _590_ sky130_fd_sc_hd__nand3_1 + PLACED ( 27140 62560 ) N ; + - _591_ sky130_fd_sc_hd__a21o_1 + PLACED ( 19320 48960 ) FS ; + - _592_ sky130_fd_sc_hd__o21ai_0 + PLACED ( 23920 57120 ) N ; + - _593_ sky130_fd_sc_hd__o21ai_0 + PLACED ( 23000 59840 ) FS ; + - _594_ sky130_fd_sc_hd__a32oi_1 + PLACED ( 24840 59840 ) FS ; + - _595_ sky130_fd_sc_hd__nor2_1 + PLACED ( 29900 68000 ) N ; + - _596_ sky130_fd_sc_hd__a31oi_1 + PLACED ( 29440 62560 ) N ; + - _597_ sky130_fd_sc_hd__o21ai_0 + PLACED ( 21620 62560 ) N ; + - _598_ sky130_fd_sc_hd__nand2_1 + PLACED ( 18860 65280 ) FS ; + - _599_ sky130_fd_sc_hd__maj3_2 + PLACED ( 21160 65280 ) FS ; + - _600_ sky130_fd_sc_hd__nor4_1 + PLACED ( 18860 62560 ) N ; + - _601_ sky130_fd_sc_hd__o21ai_0 + PLACED ( 16100 59840 ) FS ; + - _602_ sky130_fd_sc_hd__a22oi_1 + PLACED ( 16100 62560 ) N ; + - _603_ sky130_fd_sc_hd__a21oi_1 + PLACED ( 13340 62560 ) N ; + - _604_ sky130_fd_sc_hd__or3_1 + PLACED ( 13800 59840 ) FS ; + - _605_ sky130_fd_sc_hd__nor2_1 + PLACED ( 19780 59840 ) FS ; + - _606_ sky130_fd_sc_hd__a21oi_1 + PLACED ( 17020 65280 ) FS ; + - _607_ sky130_fd_sc_hd__inv_1 + PLACED ( 10120 65280 ) FS ; + - _608_ sky130_fd_sc_hd__a32oi_1 + PLACED ( 13800 65280 ) FS ; + - _609_ sky130_fd_sc_hd__a21oi_1 + PLACED ( 48760 29920 ) N ; + - _610_ sky130_fd_sc_hd__a31oi_4 + PLACED ( 43240 40800 ) N ; + - _611_ sky130_fd_sc_hd__nand3_1 + PLACED ( 52440 32640 ) FS ; + - _612_ sky130_fd_sc_hd__o21ai_0 + PLACED ( 50600 32640 ) FS ; + - _613_ sky130_fd_sc_hd__o21ai_0 + PLACED ( 45540 32640 ) FS ; + - _614_ sky130_fd_sc_hd__a32oi_1 + PLACED ( 47380 32640 ) FS ; + - _615_ sky130_fd_sc_hd__o31ai_1 + PLACED ( 46000 29920 ) N ; + - _616_ sky130_fd_sc_hd__nand2_1 + PLACED ( 45080 21760 ) FS ; + - _617_ sky130_fd_sc_hd__o21ai_0 + PLACED ( 46000 24480 ) N ; + - _618_ sky130_fd_sc_hd__maj3_1 + PLACED ( 52900 29920 ) N ; + - _619_ sky130_fd_sc_hd__nand2_1 + PLACED ( 55200 21760 ) FS ; + - _620_ sky130_fd_sc_hd__a211oi_1 + PLACED ( 57040 21760 ) FS ; + - _621_ sky130_fd_sc_hd__nor2_1 + PLACED ( 57040 27200 ) FS ; + - _622_ sky130_fd_sc_hd__nor2_1 + PLACED ( 58420 27200 ) FS ; + - _623_ sky130_fd_sc_hd__nand2_1 + PLACED ( 54740 24480 ) N ; + - _624_ sky130_fd_sc_hd__mux2i_1 + PLACED ( 56120 24480 ) N ; + - _625_ sky130_fd_sc_hd__nand3_1 + PLACED ( 59800 24480 ) N ; + - _626_ sky130_fd_sc_hd__o21ai_0 + PLACED ( 59800 21760 ) FS ; + - _627_ sky130_fd_sc_hd__nand2_1 + PLACED ( 58880 10880 ) FS ; + - _628_ sky130_fd_sc_hd__o31ai_1 + PLACED ( 57040 19040 ) N ; + - _629_ sky130_fd_sc_hd__nand2_1 + PLACED ( 51520 40800 ) N ; + - _630_ sky130_fd_sc_hd__a311oi_4 + PLACED ( 43240 43520 ) FS ; + - _631_ sky130_fd_sc_hd__inv_1 + PLACED ( 54280 38080 ) FS ; + - _632_ sky130_fd_sc_hd__nand2_1 + PLACED ( 52900 38080 ) FS ; + - _633_ sky130_fd_sc_hd__a311oi_4 + PLACED ( 43240 38080 ) FS ; + - _634_ sky130_fd_sc_hd__nor4_1 + PLACED ( 51060 46240 ) N ; + - _635_ sky130_fd_sc_hd__o21ai_0 + PLACED ( 50600 51680 ) N ; + - _636_ sky130_fd_sc_hd__nor3_4 + PLACED ( 46920 48960 ) FS ; + - _637_ sky130_fd_sc_hd__o21ai_0 + PLACED ( 48760 51680 ) N ; + - _638_ sky130_fd_sc_hd__nand3_1 + PLACED ( 51980 54400 ) FS ; + - _639_ sky130_fd_sc_hd__o21ai_0 + PLACED ( 50140 54400 ) FS ; + - _640_ sky130_fd_sc_hd__nor2_1 + PLACED ( 46460 51680 ) N ; + - _641_ sky130_fd_sc_hd__a32oi_1 + PLACED ( 46920 54400 ) FS ; + - _642_ sky130_fd_sc_hd__nor2_1 + PLACED ( 47840 62560 ) N ; + - _643_ sky130_fd_sc_hd__a31oi_1 + PLACED ( 46460 59840 ) FS ; + - _644_ sky130_fd_sc_hd__maj3_1 + PLACED ( 57040 57120 ) N ; + - _645_ sky130_fd_sc_hd__a21oi_1 + PLACED ( 63480 59840 ) FS ; + - _646_ sky130_fd_sc_hd__o21a_1 + PLACED ( 60720 59840 ) FS ; + - _647_ sky130_fd_sc_hd__o32ai_1 + PLACED ( 58880 62560 ) N ; + - _648_ sky130_fd_sc_hd__inv_1 + PLACED ( 55200 59840 ) FS ; + - _649_ sky130_fd_sc_hd__nand2_1 + PLACED ( 62100 62560 ) N ; + - _650_ sky130_fd_sc_hd__mux2_1 + PLACED ( 58880 65280 ) FS ; + - _651_ sky130_fd_sc_hd__o31ai_1 + PLACED ( 56120 62560 ) N ; + - _652_ sky130_fd_sc_hd__nand2_1 + PLACED ( 59340 70720 ) FS ; + - _653_ sky130_fd_sc_hd__o21ai_0 + PLACED ( 57040 65280 ) FS ; + - _654_ sky130_fd_sc_hd__o21a_1 + PLACED ( 59340 40800 ) N ; + - _655_ sky130_fd_sc_hd__a21oi_2 + PLACED ( 63480 38080 ) FS ; + - _656_ sky130_fd_sc_hd__nor2_1 + PLACED ( 67620 32640 ) FS ; + - _657_ sky130_fd_sc_hd__nor2_1 + PLACED ( 70840 29920 ) N ; + - _658_ sky130_fd_sc_hd__nand2_1 + PLACED ( 68080 29920 ) N ; + - _659_ sky130_fd_sc_hd__mux2i_1 + PLACED ( 63940 32640 ) FS ; + - _660_ sky130_fd_sc_hd__nand3_1 + PLACED ( 63940 27200 ) FS ; + - _661_ sky130_fd_sc_hd__o21ai_0 + PLACED ( 68540 27200 ) FS ; + - _662_ sky130_fd_sc_hd__a21oi_1 + PLACED ( 64400 29920 ) N ; + - _663_ sky130_fd_sc_hd__nor3_1 + PLACED ( 66240 29920 ) N ; + - _664_ sky130_fd_sc_hd__nand2_1 + PLACED ( 71300 27200 ) FS ; + - _665_ sky130_fd_sc_hd__o31ai_1 + PLACED ( 65780 27200 ) FS ; + - _666_ sky130_fd_sc_hd__nor2_1 + PLACED ( 70840 46240 ) N ; + - _667_ sky130_fd_sc_hd__o211ai_2 + PLACED ( 57500 48960 ) FS ; + - _668_ sky130_fd_sc_hd__nand2b_1 + PLACED ( 65320 46240 ) N ; + - _669_ sky130_fd_sc_hd__nor2_1 + PLACED ( 55200 51680 ) N ; + - _670_ sky130_fd_sc_hd__maj3_1 + PLACED ( 57040 59840 ) FS ; + - _671_ sky130_fd_sc_hd__a21oi_1 + PLACED ( 68540 48960 ) FS ; + - _672_ sky130_fd_sc_hd__o21ai_2 + PLACED ( 65320 48960 ) FS ; + - _673_ sky130_fd_sc_hd__o21ai_0 + PLACED ( 74060 48960 ) FS ; + - _674_ sky130_fd_sc_hd__a21o_1 + PLACED ( 72680 43520 ) FS ; + - _675_ sky130_fd_sc_hd__a32o_1 + PLACED ( 72680 46240 ) N ; + - _676_ sky130_fd_sc_hd__nand2_1 + PLACED ( 78200 43520 ) FS ; + - _677_ sky130_fd_sc_hd__mux2_1 + PLACED ( 76360 46240 ) N ; + - _678_ sky130_fd_sc_hd__nor3_1 + PLACED ( 76360 43520 ) FS ; + - _679_ sky130_fd_sc_hd__nand2_1 + PLACED ( 78200 40800 ) N ; + - _680_ sky130_fd_sc_hd__o31ai_1 + PLACED ( 75440 40800 ) N ; + - _681_ sky130_fd_sc_hd__a211oi_1 + PLACED ( 69000 54400 ) FS ; + - _682_ sky130_fd_sc_hd__a21o_1 + PLACED ( 66240 54400 ) FS ; + - _683_ sky130_fd_sc_hd__o21ai_1 + PLACED ( 70840 51680 ) N ; + - _684_ sky130_fd_sc_hd__or2_1 + PLACED ( 70840 57120 ) N ; + - _685_ sky130_fd_sc_hd__nand2_1 + PLACED ( 65780 62560 ) N ; + - _686_ sky130_fd_sc_hd__and2_0 + PLACED ( 66700 57120 ) N ; + - _687_ sky130_fd_sc_hd__o2111ai_1 + PLACED ( 67160 59840 ) FS ; + - _688_ sky130_fd_sc_hd__nand2_1 + PLACED ( 69000 57120 ) N ; + - _689_ sky130_fd_sc_hd__or3_1 + PLACED ( 70380 59840 ) FS ; + - _690_ sky130_fd_sc_hd__o311ai_1 + PLACED ( 67160 62560 ) N ; + - _691_ sky130_fd_sc_hd__nand2_1 + PLACED ( 66240 70720 ) FS ; + - _692_ sky130_fd_sc_hd__nor2_1 + PLACED ( 71300 62560 ) N ; + - _693_ sky130_fd_sc_hd__nor2_1 + PLACED ( 72220 65280 ) FS ; + - _694_ sky130_fd_sc_hd__nor3_1 + PLACED ( 66240 65280 ) FS ; + - _695_ sky130_fd_sc_hd__a2111o_1 + PLACED ( 68080 65280 ) FS ; + - _696_ sky130_fd_sc_hd__a22oi_1 + PLACED ( 66700 68000 ) N ; + - _697_ sky130_fd_sc_hd__nand2_1 + PLACED ( 75440 32640 ) FS ; + - _698_ sky130_fd_sc_hd__nand3_1 + PLACED ( 74060 29920 ) N ; + - _699_ sky130_fd_sc_hd__o21ai_0 + PLACED ( 75900 29920 ) N ; + - _700_ sky130_fd_sc_hd__a31oi_1 + PLACED ( 76820 32640 ) FS ; + - _701_ sky130_fd_sc_hd__nand2_1 + PLACED ( 80960 24480 ) N ; + - _702_ sky130_fd_sc_hd__o21ai_0 + PLACED ( 78660 29920 ) N ; + - _703_ sky130_fd_sc_hd__xnor2_1 + PLACED ( 62100 48960 ) FS ; + - _704_ sky130_fd_sc_hd__xnor2_1 + PLACED ( 62100 54400 ) FS ; + - _705_ sky130_fd_sc_hd__xnor2_1 + PLACED ( 70840 40800 ) N ; + - _706_ sky130_fd_sc_hd__xnor2_1 + PLACED ( 80500 46240 ) N ; + - _707_ sky130_fd_sc_hd__xnor2_1 + PLACED ( 73600 59840 ) FS ; + - _708_ sky130_fd_sc_hd__xnor2_1 + PLACED ( 80040 32640 ) FS ; + - _709_ sky130_fd_sc_hd__xnor2_1 + PLACED ( 80040 35360 ) N ; + - _710_ sky130_fd_sc_hd__xnor2_1 + PLACED ( 24840 10880 ) FS ; + - _711_ sky130_fd_sc_hd__xnor2_1 + PLACED ( 28980 13600 ) N ; + - _712_ sky130_fd_sc_hd__nor2_1 + PLACED ( 42780 32640 ) FS ; + - _713_ sky130_fd_sc_hd__xnor2_1 + PLACED ( 40020 27200 ) FS ; + - _714_ sky130_fd_sc_hd__nor2_1 + PLACED ( 31740 43520 ) FS ; + - _715_ sky130_fd_sc_hd__nor2_1 + PLACED ( 31280 40800 ) N ; + - _716_ sky130_fd_sc_hd__xnor2_1 + PLACED ( 28060 40800 ) N ; + - _717_ sky130_fd_sc_hd__nor2b_1 + PLACED ( 25300 32640 ) FS ; + - _718_ sky130_fd_sc_hd__xnor2_1 + PLACED ( 22080 32640 ) FS ; + - _719_ sky130_fd_sc_hd__xnor2_1 + PLACED ( 8280 40800 ) N ; + - _720_ sky130_fd_sc_hd__xnor2_1 + PLACED ( 4600 40800 ) N ; + - _721_ sky130_fd_sc_hd__and2_0 + PLACED ( 18860 54400 ) FS ; + - _722_ sky130_fd_sc_hd__xnor2_1 + PLACED ( 20240 51680 ) N ; + - _723_ sky130_fd_sc_hd__xor2_1 + PLACED ( 16100 68000 ) N ; + - _724_ sky130_fd_sc_hd__xnor2_1 + PLACED ( 19320 68000 ) N ; + - _725_ sky130_fd_sc_hd__xnor2_1 + PLACED ( 62100 35360 ) N ; + - _726_ sky130_fd_sc_hd__xor2_1 + PLACED ( 58880 29920 ) N ; + - clkbuf_0_clk sky130_fd_sc_hd__clkbuf_8 + SOURCE TIMING + PLACED ( 38180 43520 ) FS ; + - clkbuf_2_0__f_clk sky130_fd_sc_hd__clkbuf_8 + SOURCE TIMING + PLACED ( 22080 35360 ) N ; + - clkbuf_2_1__f_clk sky130_fd_sc_hd__clkbuf_8 + SOURCE TIMING + PLACED ( 23920 54400 ) FS ; + - clkbuf_2_2__f_clk sky130_fd_sc_hd__clkbuf_8 + SOURCE TIMING + PLACED ( 58420 32640 ) FS ; + - clkbuf_2_3__f_clk sky130_fd_sc_hd__clkbuf_8 + SOURCE TIMING + PLACED ( 57040 54400 ) FS ; + - clkload0 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 20700 35360 ) N ; + - clkload1 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 57040 32640 ) FS ; + - clkload2 sky130_fd_sc_hd__clkinv_2 + SOURCE TIMING + PLACED ( 54740 54400 ) FS ; + - ctrl.state.out\[1\]$_DFF_P_ sky130_fd_sc_hd__dfxtp_1 + PLACED ( 31280 68000 ) N ; + - ctrl.state.out\[2\]$_DFF_P_ sky130_fd_sc_hd__dfxtp_4 + PLACED ( 39100 65280 ) FS ; + - dpath.a_lt_b$in0\[0\]$_DFFE_PP_ sky130_fd_sc_hd__dfxtp_2 + PLACED ( 5980 19040 ) N ; + - dpath.a_lt_b$in0\[10\]$_DFFE_PP_ sky130_fd_sc_hd__dfxtp_1 + PLACED ( 46460 57120 ) N ; + - dpath.a_lt_b$in0\[11\]$_DFFE_PP_ sky130_fd_sc_hd__dfxtp_2 + PLACED ( 56580 68000 ) N ; + - dpath.a_lt_b$in0\[12\]$_DFFE_PP_ sky130_fd_sc_hd__dfxtp_1 + PLACED ( 63020 24480 ) N ; + - dpath.a_lt_b$in0\[13\]$_DFFE_PP_ sky130_fd_sc_hd__dfxtp_1 + PLACED ( 76820 38080 ) FS ; + - dpath.a_lt_b$in0\[14\]$_DFFE_PP_ sky130_fd_sc_hd__dfxtp_1 + PLACED ( 70840 68000 ) N ; + - dpath.a_lt_b$in0\[15\]$_DFFE_PP_ sky130_fd_sc_hd__dfxtp_1 + PLACED ( 76820 27200 ) FS ; + - dpath.a_lt_b$in0\[1\]$_DFFE_PP_ sky130_fd_sc_hd__dfxtp_1 + PLACED ( 21620 13600 ) N ; + - dpath.a_lt_b$in0\[2\]$_DFFE_PP_ sky130_fd_sc_hd__dfxtp_2 + PLACED ( 36340 21760 ) FS ; + - dpath.a_lt_b$in0\[3\]$_DFFE_PP_ sky130_fd_sc_hd__dfxtp_2 + PLACED ( 34960 51680 ) N ; + - dpath.a_lt_b$in0\[4\]$_DFFE_PP_ sky130_fd_sc_hd__dfxtp_1 + PLACED ( 3220 32640 ) FS ; + - dpath.a_lt_b$in0\[5\]$_DFFE_PP_ sky130_fd_sc_hd__dfxtp_2 + PLACED ( 1840 43520 ) FS ; + - dpath.a_lt_b$in0\[6\]$_DFFE_PP_ sky130_fd_sc_hd__dfxtp_2 + PLACED ( 29440 59840 ) FS ; + - dpath.a_lt_b$in0\[7\]$_DFFE_PP_ sky130_fd_sc_hd__dfxtp_1 + PLACED ( 7820 68000 ) N ; + - dpath.a_lt_b$in0\[8\]$_DFFE_PP_ sky130_fd_sc_hd__dfxtp_1 + PLACED ( 44620 27200 ) FS ; + - dpath.a_lt_b$in0\[9\]$_DFFE_PP_ sky130_fd_sc_hd__dfxtp_1 + PLACED ( 53820 13600 ) N ; + - dpath.a_lt_b$in1\[0\]$_DFFE_PP_ sky130_fd_sc_hd__dfxtp_2 + PLACED ( 3680 24480 ) N ; + - dpath.a_lt_b$in1\[10\]$_DFFE_PP_ sky130_fd_sc_hd__dfxtp_2 + PLACED ( 34960 57120 ) N ; + - dpath.a_lt_b$in1\[11\]$_DFFE_PP_ sky130_fd_sc_hd__dfxtp_2 + PLACED ( 47840 65280 ) FS ; + - dpath.a_lt_b$in1\[12\]$_DFFE_PP_ sky130_fd_sc_hd__dfxtp_2 + PLACED ( 63020 16320 ) FS ; + - dpath.a_lt_b$in1\[13\]$_DFFE_PP_ sky130_fd_sc_hd__dfxtp_2 + PLACED ( 77740 57120 ) N ; + - dpath.a_lt_b$in1\[14\]$_DFFE_PP_ sky130_fd_sc_hd__dfxtp_2 + PLACED ( 72680 62560 ) N ; + - dpath.a_lt_b$in1\[15\]$_DFFE_PP_ sky130_fd_sc_hd__dfxtp_1 + PLACED ( 73140 24480 ) N ; + - dpath.a_lt_b$in1\[1\]$_DFFE_PP_ sky130_fd_sc_hd__dfxtp_2 + PLACED ( 14260 16320 ) FS ; + - dpath.a_lt_b$in1\[2\]$_DFFE_PP_ sky130_fd_sc_hd__dfxtp_2 + PLACED ( 32660 16320 ) FS ; + - dpath.a_lt_b$in1\[3\]$_DFFE_PP_ sky130_fd_sc_hd__dfxtp_2 + PLACED ( 29440 54400 ) FS ; + - dpath.a_lt_b$in1\[4\]$_DFFE_PP_ sky130_fd_sc_hd__dfxtp_2 + PLACED ( 3680 35360 ) N ; + - dpath.a_lt_b$in1\[5\]$_DFFE_PP_ sky130_fd_sc_hd__dfxtp_1 + PLACED ( 3220 48960 ) FS ; + - dpath.a_lt_b$in1\[6\]$_DFFE_PP_ sky130_fd_sc_hd__dfxtp_1 + PLACED ( 3220 57120 ) N ; + - dpath.a_lt_b$in1\[7\]$_DFFE_PP_ sky130_fd_sc_hd__dfxtp_1 + PLACED ( 3680 59840 ) FS ; + - dpath.a_lt_b$in1\[8\]$_DFFE_PP_ sky130_fd_sc_hd__dfxtp_2 + PLACED ( 43700 19040 ) N ; + - dpath.a_lt_b$in1\[9\]$_DFFE_PP_ sky130_fd_sc_hd__dfxtp_1 + PLACED ( 49220 16320 ) FS ; + - input1 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 1380 21760 ) FS ; + - input10 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 38640 2720 ) N ; + - input11 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 5520 46240 ) N ; + - input12 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 17480 2720 ) N ; + - input13 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 1380 29920 ) N ; + - input14 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 2760 46240 ) N ; + - input15 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 28980 78880 ) N ; + - input16 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 7360 65280 ) FS ; + - input17 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 45080 5440 ) FS ; + - input18 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 58880 5440 ) FS ; + - input19 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 47840 81600 ) FS ; + - input2 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 37260 81600 ) FS ; + - input20 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 59340 81600 ) FS ; + - input21 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 82800 24480 ) N ; + - input22 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 82800 40800 ) N ; + - input23 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 34960 5440 ) FS ; + - input24 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 66240 81600 ) FS ; + - input25 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 82800 29920 ) N ; + - input26 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 1840 54400 ) FS ; + - input27 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 1840 35360 ) N ; + - input28 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 1840 51680 ) N ; + - input29 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 1380 59840 ) FS ; + - input3 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 52440 81600 ) FS ; + - input30 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 1380 62560 ) N ; + - input31 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 45080 2720 ) N ; + - input32 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 51060 2720 ) N ; + - input33 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 37720 78880 ) N ; + - input34 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 35880 81600 ) FS ; + - input35 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 39100 81600 ) FS ; + - input4 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 66240 2720 ) N ; + - input5 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 81420 59840 ) FS ; + - input6 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 81420 65280 ) FS ; + - input7 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 79120 21760 ) FS ; + - input8 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 1840 24480 ) N ; + - input9 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 25760 2720 ) N ; + - output36 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 2300 65280 ) FS ; + - output37 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 5980 27200 ) FS ; + - output38 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 82340 48960 ) FS ; + - output39 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 82800 54400 ) FS ; + - output40 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 79580 40800 ) N ; + - output41 sky130_fd_sc_hd__clkbuf_2 + SOURCE TIMING + PLACED ( 83720 46240 ) N ; + - output42 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 82800 59840 ) FS ; + - output43 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 84180 35360 ) N ; + - output44 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 29900 2720 ) N ; + - output45 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 40020 2720 ) N ; + - output46 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 1380 40800 ) N ; + - output47 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 1380 32640 ) FS ; + - output48 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 2760 40800 ) N ; + - output49 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 13800 51680 ) N ; + - output50 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 20700 81600 ) FS ; + - output51 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 75440 38080 ) FS ; + - output52 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 80500 29920 ) N ; + - output53 sky130_fd_sc_hd__clkbuf_1 + SOURCE TIMING + PLACED ( 39100 78880 ) N ; + - rebuffer1 sky130_fd_sc_hd__clkbuf_2 + SOURCE TIMING + PLACED ( 66240 51680 ) N ; + - rebuffer2 sky130_fd_sc_hd__dlymetal6s2s_1 + SOURCE TIMING + PLACED ( 45080 46240 ) N ; + - req_rdy$_DFF_P_ sky130_fd_sc_hd__dfxtp_4 + PLACED ( 41400 70720 ) FS ; +END COMPONENTS +PINS 54 ; + - clk + NET clk + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met3 ( -400 -150 ) ( 400 150 ) + + PLACED ( 400 71060 ) N ; + - req_msg[0] + NET req_msg[0] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met3 ( -400 -150 ) ( 400 150 ) + + PLACED ( 400 24820 ) N ; + - req_msg[10] + NET req_msg[10] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met2 ( -70 -242 ) ( 70 243 ) + + PLACED ( 37950 86597 ) N ; + - req_msg[11] + NET req_msg[11] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met2 ( -70 -242 ) ( 70 243 ) + + PLACED ( 53590 86597 ) N ; + - req_msg[12] + NET req_msg[12] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met2 ( -70 -242 ) ( 70 243 ) + + PLACED ( 67390 242 ) N ; + - req_msg[13] + NET req_msg[13] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met3 ( -400 -150 ) ( 400 150 ) + + PLACED ( 86440 58820 ) N ; + - req_msg[14] + NET req_msg[14] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met3 ( -400 -150 ) ( 400 150 ) + + PLACED ( 86440 65620 ) N ; + - req_msg[15] + NET req_msg[15] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met3 ( -400 -150 ) ( 400 150 ) + + PLACED ( 86440 26180 ) N ; + - req_msg[16] + NET req_msg[16] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met3 ( -400 -150 ) ( 400 150 ) + + PLACED ( 400 23460 ) N ; + - req_msg[17] + NET req_msg[17] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met2 ( -70 -242 ) ( 70 243 ) + + PLACED ( 26910 242 ) N ; + - req_msg[18] + NET req_msg[18] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met2 ( -70 -242 ) ( 70 243 ) + + PLACED ( 38870 242 ) N ; + - req_msg[19] + NET req_msg[19] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met3 ( -400 -150 ) ( 400 150 ) + + PLACED ( 400 47940 ) N ; + - req_msg[1] + NET req_msg[1] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met2 ( -70 -242 ) ( 70 243 ) + + PLACED ( 17710 242 ) N ; + - req_msg[20] + NET req_msg[20] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met3 ( -400 -150 ) ( 400 150 ) + + PLACED ( 400 30260 ) N ; + - req_msg[21] + NET req_msg[21] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met3 ( -400 -150 ) ( 400 150 ) + + PLACED ( 400 45220 ) N ; + - req_msg[22] + NET req_msg[22] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met2 ( -70 -242 ) ( 70 243 ) + + PLACED ( 28750 86597 ) N ; + - req_msg[23] + NET req_msg[23] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met3 ( -400 -150 ) ( 400 150 ) + + PLACED ( 400 65620 ) N ; + - req_msg[24] + NET req_msg[24] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met2 ( -70 -242 ) ( 70 243 ) + + PLACED ( 47150 242 ) N ; + - req_msg[25] + NET req_msg[25] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met2 ( -70 -242 ) ( 70 243 ) + + PLACED ( 60030 242 ) N ; + - req_msg[26] + NET req_msg[26] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met2 ( -70 -242 ) ( 70 243 ) + + PLACED ( 48070 86597 ) N ; + - req_msg[27] + NET req_msg[27] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met2 ( -70 -242 ) ( 70 243 ) + + PLACED ( 59110 86597 ) N ; + - req_msg[28] + NET req_msg[28] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met3 ( -400 -150 ) ( 400 150 ) + + PLACED ( 86440 27540 ) N ; + - req_msg[29] + NET req_msg[29] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met3 ( -400 -150 ) ( 400 150 ) + + PLACED ( 86440 42500 ) N ; + - req_msg[2] + NET req_msg[2] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met2 ( -70 -242 ) ( 70 243 ) + + PLACED ( 36110 242 ) N ; + - req_msg[30] + NET req_msg[30] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met2 ( -70 -242 ) ( 70 243 ) + + PLACED ( 66470 86597 ) N ; + - req_msg[31] + NET req_msg[31] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met3 ( -400 -150 ) ( 400 150 ) + + PLACED ( 86440 28900 ) N ; + - req_msg[3] + NET req_msg[3] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met3 ( -400 -150 ) ( 400 150 ) + + PLACED ( 400 54740 ) N ; + - req_msg[4] + NET req_msg[4] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met3 ( -400 -150 ) ( 400 150 ) + + PLACED ( 400 37060 ) N ; + - req_msg[5] + NET req_msg[5] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met3 ( -400 -150 ) ( 400 150 ) + + PLACED ( 400 52020 ) N ; + - req_msg[6] + NET req_msg[6] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met3 ( -400 -150 ) ( 400 150 ) + + PLACED ( 400 56100 ) N ; + - req_msg[7] + NET req_msg[7] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met3 ( -400 -150 ) ( 400 150 ) + + PLACED ( 400 64260 ) N ; + - req_msg[8] + NET req_msg[8] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met2 ( -70 -242 ) ( 70 243 ) + + PLACED ( 46230 242 ) N ; + - req_msg[9] + NET req_msg[9] + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met2 ( -70 -242 ) ( 70 243 ) + + PLACED ( 50830 242 ) N ; + - req_rdy + NET req_rdy + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met3 ( -400 -150 ) ( 400 150 ) + + PLACED ( 400 68340 ) N ; + - req_val + NET req_val + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met2 ( -70 -242 ) ( 70 243 ) + + PLACED ( 40710 86597 ) N ; + - reset + NET reset + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met2 ( -70 -242 ) ( 70 243 ) + + PLACED ( 37030 86597 ) N ; + - resp_msg[0] + NET resp_msg[0] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met3 ( -400 -150 ) ( 400 150 ) + + PLACED ( 400 27540 ) N ; + - resp_msg[10] + NET resp_msg[10] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met3 ( -400 -150 ) ( 400 150 ) + + PLACED ( 86440 50660 ) N ; + - resp_msg[11] + NET resp_msg[11] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met3 ( -400 -150 ) ( 400 150 ) + + PLACED ( 86440 56100 ) N ; + - resp_msg[12] + NET resp_msg[12] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met3 ( -400 -150 ) ( 400 150 ) + + PLACED ( 86440 41140 ) N ; + - resp_msg[13] + NET resp_msg[13] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met3 ( -400 -150 ) ( 400 150 ) + + PLACED ( 86440 49300 ) N ; + - resp_msg[14] + NET resp_msg[14] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met3 ( -400 -150 ) ( 400 150 ) + + PLACED ( 86440 60180 ) N ; + - resp_msg[15] + NET resp_msg[15] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met3 ( -400 -150 ) ( 400 150 ) + + PLACED ( 86440 37060 ) N ; + - resp_msg[1] + NET resp_msg[1] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met2 ( -70 -242 ) ( 70 243 ) + + PLACED ( 29670 242 ) N ; + - resp_msg[2] + NET resp_msg[2] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met2 ( -70 -242 ) ( 70 243 ) + + PLACED ( 39790 242 ) N ; + - resp_msg[3] + NET resp_msg[3] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met3 ( -400 -150 ) ( 400 150 ) + + PLACED ( 400 42500 ) N ; + - resp_msg[4] + NET resp_msg[4] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met3 ( -400 -150 ) ( 400 150 ) + + PLACED ( 400 35700 ) N ; + - resp_msg[5] + NET resp_msg[5] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met3 ( -400 -150 ) ( 400 150 ) + + PLACED ( 400 43860 ) N ; + - resp_msg[6] + NET resp_msg[6] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met3 ( -400 -150 ) ( 400 150 ) + + PLACED ( 400 53380 ) N ; + - resp_msg[7] + NET resp_msg[7] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met2 ( -70 -242 ) ( 70 243 ) + + PLACED ( 21390 86597 ) N ; + - resp_msg[8] + NET resp_msg[8] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met3 ( -400 -150 ) ( 400 150 ) + + PLACED ( 86440 39780 ) N ; + - resp_msg[9] + NET resp_msg[9] + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met3 ( -400 -150 ) ( 400 150 ) + + PLACED ( 86440 31620 ) N ; + - resp_rdy + NET resp_rdy + DIRECTION INPUT + USE SIGNAL + + PORT + + LAYER met2 ( -70 -242 ) ( 70 243 ) + + PLACED ( 39790 86597 ) N ; + - resp_val + NET resp_val + DIRECTION OUTPUT + USE SIGNAL + + PORT + + LAYER met2 ( -70 -242 ) ( 70 243 ) + + PLACED ( 38870 86597 ) N ; +END PINS +SPECIALNETS 2 ; + - VDD ( * VPWR ) + USE POWER + + ROUTED met5 1600 + SHAPE STRIPE ( 27720 84320 ) ( 83600 84320 ) + NEW met5 1600 + SHAPE STRIPE ( 27720 57120 ) ( 83600 57120 ) + NEW met5 1600 + SHAPE STRIPE ( 27720 29920 ) ( 83600 29920 ) + NEW met4 1600 + SHAPE STRIPE ( 82800 5200 ) ( 82800 85120 ) + NEW met4 1600 + SHAPE STRIPE ( 55660 5200 ) ( 55660 85120 ) + NEW met4 1600 + SHAPE STRIPE ( 28520 5200 ) ( 28520 85120 ) + NEW met1 480 + SHAPE FOLLOWPIN ( 1380 81600 ) ( 85560 81600 ) + NEW met1 480 + SHAPE FOLLOWPIN ( 1380 76160 ) ( 85560 76160 ) + NEW met1 480 + SHAPE FOLLOWPIN ( 1380 70720 ) ( 85560 70720 ) + NEW met1 480 + SHAPE FOLLOWPIN ( 1380 65280 ) ( 85560 65280 ) + NEW met1 480 + SHAPE FOLLOWPIN ( 1380 59840 ) ( 85560 59840 ) + NEW met1 480 + SHAPE FOLLOWPIN ( 1380 54400 ) ( 85560 54400 ) + NEW met1 480 + SHAPE FOLLOWPIN ( 1380 48960 ) ( 85560 48960 ) + NEW met1 480 + SHAPE FOLLOWPIN ( 1380 43520 ) ( 85560 43520 ) + NEW met1 480 + SHAPE FOLLOWPIN ( 1380 38080 ) ( 85560 38080 ) + NEW met1 480 + SHAPE FOLLOWPIN ( 1380 32640 ) ( 85560 32640 ) + NEW met1 480 + SHAPE FOLLOWPIN ( 1380 27200 ) ( 85560 27200 ) + NEW met1 480 + SHAPE FOLLOWPIN ( 1380 21760 ) ( 85560 21760 ) + NEW met1 480 + SHAPE FOLLOWPIN ( 1380 16320 ) ( 85560 16320 ) + NEW met1 480 + SHAPE FOLLOWPIN ( 1380 10880 ) ( 85560 10880 ) + NEW met1 480 + SHAPE FOLLOWPIN ( 1380 5440 ) ( 85560 5440 ) + NEW met4 0 + SHAPE STRIPE ( 82800 84320 ) via5_6_1600_1600_1_1_1600_1600 + NEW met4 0 + SHAPE STRIPE ( 82800 57120 ) via5_6_1600_1600_1_1_1600_1600 + NEW met4 0 + SHAPE STRIPE ( 82800 29920 ) via5_6_1600_1600_1_1_1600_1600 + NEW met4 0 + SHAPE STRIPE ( 55660 84320 ) via5_6_1600_1600_1_1_1600_1600 + NEW met4 0 + SHAPE STRIPE ( 55660 57120 ) via5_6_1600_1600_1_1_1600_1600 + NEW met4 0 + SHAPE STRIPE ( 55660 29920 ) via5_6_1600_1600_1_1_1600_1600 + NEW met4 0 + SHAPE STRIPE ( 28520 84320 ) via5_6_1600_1600_1_1_1600_1600 + NEW met4 0 + SHAPE STRIPE ( 28520 57120 ) via5_6_1600_1600_1_1_1600_1600 + NEW met4 0 + SHAPE STRIPE ( 28520 29920 ) via5_6_1600_1600_1_1_1600_1600 + NEW met3 330 + SHAPE STRIPE ( 82010 81600 ) ( 83590 81600 ) + NEW met3 0 + SHAPE STRIPE ( 82800 81600 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 82030 81600 ) ( 83570 81600 ) + NEW met2 0 + SHAPE STRIPE ( 82800 81600 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 82800 81600 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 82010 76160 ) ( 83590 76160 ) + NEW met3 0 + SHAPE STRIPE ( 82800 76160 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 82030 76160 ) ( 83570 76160 ) + NEW met2 0 + SHAPE STRIPE ( 82800 76160 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 82800 76160 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 82010 70720 ) ( 83590 70720 ) + NEW met3 0 + SHAPE STRIPE ( 82800 70720 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 82030 70720 ) ( 83570 70720 ) + NEW met2 0 + SHAPE STRIPE ( 82800 70720 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 82800 70720 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 82010 65280 ) ( 83590 65280 ) + NEW met3 0 + SHAPE STRIPE ( 82800 65280 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 82030 65280 ) ( 83570 65280 ) + NEW met2 0 + SHAPE STRIPE ( 82800 65280 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 82800 65280 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 82010 59840 ) ( 83590 59840 ) + NEW met3 0 + SHAPE STRIPE ( 82800 59840 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 82030 59840 ) ( 83570 59840 ) + NEW met2 0 + SHAPE STRIPE ( 82800 59840 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 82800 59840 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 82010 54400 ) ( 83590 54400 ) + NEW met3 0 + SHAPE STRIPE ( 82800 54400 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 82030 54400 ) ( 83570 54400 ) + NEW met2 0 + SHAPE STRIPE ( 82800 54400 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 82800 54400 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 82010 48960 ) ( 83590 48960 ) + NEW met3 0 + SHAPE STRIPE ( 82800 48960 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 82030 48960 ) ( 83570 48960 ) + NEW met2 0 + SHAPE STRIPE ( 82800 48960 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 82800 48960 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 82010 43520 ) ( 83590 43520 ) + NEW met3 0 + SHAPE STRIPE ( 82800 43520 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 82030 43520 ) ( 83570 43520 ) + NEW met2 0 + SHAPE STRIPE ( 82800 43520 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 82800 43520 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 82010 38080 ) ( 83590 38080 ) + NEW met3 0 + SHAPE STRIPE ( 82800 38080 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 82030 38080 ) ( 83570 38080 ) + NEW met2 0 + SHAPE STRIPE ( 82800 38080 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 82800 38080 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 82010 32640 ) ( 83590 32640 ) + NEW met3 0 + SHAPE STRIPE ( 82800 32640 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 82030 32640 ) ( 83570 32640 ) + NEW met2 0 + SHAPE STRIPE ( 82800 32640 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 82800 32640 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 82010 27200 ) ( 83590 27200 ) + NEW met3 0 + SHAPE STRIPE ( 82800 27200 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 82030 27200 ) ( 83570 27200 ) + NEW met2 0 + SHAPE STRIPE ( 82800 27200 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 82800 27200 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 82010 21760 ) ( 83590 21760 ) + NEW met3 0 + SHAPE STRIPE ( 82800 21760 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 82030 21760 ) ( 83570 21760 ) + NEW met2 0 + SHAPE STRIPE ( 82800 21760 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 82800 21760 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 82010 16320 ) ( 83590 16320 ) + NEW met3 0 + SHAPE STRIPE ( 82800 16320 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 82030 16320 ) ( 83570 16320 ) + NEW met2 0 + SHAPE STRIPE ( 82800 16320 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 82800 16320 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 82010 10880 ) ( 83590 10880 ) + NEW met3 0 + SHAPE STRIPE ( 82800 10880 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 82030 10880 ) ( 83570 10880 ) + NEW met2 0 + SHAPE STRIPE ( 82800 10880 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 82800 10880 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 82010 5440 ) ( 83590 5440 ) + NEW met3 0 + SHAPE STRIPE ( 82800 5440 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 82030 5440 ) ( 83570 5440 ) + NEW met2 0 + SHAPE STRIPE ( 82800 5440 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 82800 5440 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 54870 81600 ) ( 56450 81600 ) + NEW met3 0 + SHAPE STRIPE ( 55660 81600 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 54890 81600 ) ( 56430 81600 ) + NEW met2 0 + SHAPE STRIPE ( 55660 81600 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 55660 81600 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 54870 76160 ) ( 56450 76160 ) + NEW met3 0 + SHAPE STRIPE ( 55660 76160 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 54890 76160 ) ( 56430 76160 ) + NEW met2 0 + SHAPE STRIPE ( 55660 76160 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 55660 76160 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 54870 70720 ) ( 56450 70720 ) + NEW met3 0 + SHAPE STRIPE ( 55660 70720 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 54890 70720 ) ( 56430 70720 ) + NEW met2 0 + SHAPE STRIPE ( 55660 70720 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 55660 70720 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 54870 65280 ) ( 56450 65280 ) + NEW met3 0 + SHAPE STRIPE ( 55660 65280 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 54890 65280 ) ( 56430 65280 ) + NEW met2 0 + SHAPE STRIPE ( 55660 65280 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 55660 65280 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 54870 59840 ) ( 56450 59840 ) + NEW met3 0 + SHAPE STRIPE ( 55660 59840 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 54890 59840 ) ( 56430 59840 ) + NEW met2 0 + SHAPE STRIPE ( 55660 59840 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 55660 59840 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 54870 54400 ) ( 56450 54400 ) + NEW met3 0 + SHAPE STRIPE ( 55660 54400 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 54890 54400 ) ( 56430 54400 ) + NEW met2 0 + SHAPE STRIPE ( 55660 54400 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 55660 54400 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 54870 48960 ) ( 56450 48960 ) + NEW met3 0 + SHAPE STRIPE ( 55660 48960 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 54890 48960 ) ( 56430 48960 ) + NEW met2 0 + SHAPE STRIPE ( 55660 48960 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 55660 48960 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 54870 43520 ) ( 56450 43520 ) + NEW met3 0 + SHAPE STRIPE ( 55660 43520 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 54890 43520 ) ( 56430 43520 ) + NEW met2 0 + SHAPE STRIPE ( 55660 43520 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 55660 43520 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 54870 38080 ) ( 56450 38080 ) + NEW met3 0 + SHAPE STRIPE ( 55660 38080 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 54890 38080 ) ( 56430 38080 ) + NEW met2 0 + SHAPE STRIPE ( 55660 38080 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 55660 38080 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 54870 32640 ) ( 56450 32640 ) + NEW met3 0 + SHAPE STRIPE ( 55660 32640 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 54890 32640 ) ( 56430 32640 ) + NEW met2 0 + SHAPE STRIPE ( 55660 32640 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 55660 32640 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 54870 27200 ) ( 56450 27200 ) + NEW met3 0 + SHAPE STRIPE ( 55660 27200 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 54890 27200 ) ( 56430 27200 ) + NEW met2 0 + SHAPE STRIPE ( 55660 27200 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 55660 27200 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 54870 21760 ) ( 56450 21760 ) + NEW met3 0 + SHAPE STRIPE ( 55660 21760 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 54890 21760 ) ( 56430 21760 ) + NEW met2 0 + SHAPE STRIPE ( 55660 21760 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 55660 21760 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 54870 16320 ) ( 56450 16320 ) + NEW met3 0 + SHAPE STRIPE ( 55660 16320 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 54890 16320 ) ( 56430 16320 ) + NEW met2 0 + SHAPE STRIPE ( 55660 16320 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 55660 16320 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 54870 10880 ) ( 56450 10880 ) + NEW met3 0 + SHAPE STRIPE ( 55660 10880 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 54890 10880 ) ( 56430 10880 ) + NEW met2 0 + SHAPE STRIPE ( 55660 10880 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 55660 10880 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 54870 5440 ) ( 56450 5440 ) + NEW met3 0 + SHAPE STRIPE ( 55660 5440 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 54890 5440 ) ( 56430 5440 ) + NEW met2 0 + SHAPE STRIPE ( 55660 5440 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 55660 5440 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 27730 81600 ) ( 29310 81600 ) + NEW met3 0 + SHAPE STRIPE ( 28520 81600 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 27750 81600 ) ( 29290 81600 ) + NEW met2 0 + SHAPE STRIPE ( 28520 81600 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 28520 81600 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 27730 76160 ) ( 29310 76160 ) + NEW met3 0 + SHAPE STRIPE ( 28520 76160 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 27750 76160 ) ( 29290 76160 ) + NEW met2 0 + SHAPE STRIPE ( 28520 76160 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 28520 76160 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 27730 70720 ) ( 29310 70720 ) + NEW met3 0 + SHAPE STRIPE ( 28520 70720 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 27750 70720 ) ( 29290 70720 ) + NEW met2 0 + SHAPE STRIPE ( 28520 70720 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 28520 70720 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 27730 65280 ) ( 29310 65280 ) + NEW met3 0 + SHAPE STRIPE ( 28520 65280 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 27750 65280 ) ( 29290 65280 ) + NEW met2 0 + SHAPE STRIPE ( 28520 65280 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 28520 65280 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 27730 59840 ) ( 29310 59840 ) + NEW met3 0 + SHAPE STRIPE ( 28520 59840 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 27750 59840 ) ( 29290 59840 ) + NEW met2 0 + SHAPE STRIPE ( 28520 59840 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 28520 59840 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 27730 54400 ) ( 29310 54400 ) + NEW met3 0 + SHAPE STRIPE ( 28520 54400 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 27750 54400 ) ( 29290 54400 ) + NEW met2 0 + SHAPE STRIPE ( 28520 54400 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 28520 54400 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 27730 48960 ) ( 29310 48960 ) + NEW met3 0 + SHAPE STRIPE ( 28520 48960 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 27750 48960 ) ( 29290 48960 ) + NEW met2 0 + SHAPE STRIPE ( 28520 48960 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 28520 48960 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 27730 43520 ) ( 29310 43520 ) + NEW met3 0 + SHAPE STRIPE ( 28520 43520 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 27750 43520 ) ( 29290 43520 ) + NEW met2 0 + SHAPE STRIPE ( 28520 43520 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 28520 43520 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 27730 38080 ) ( 29310 38080 ) + NEW met3 0 + SHAPE STRIPE ( 28520 38080 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 27750 38080 ) ( 29290 38080 ) + NEW met2 0 + SHAPE STRIPE ( 28520 38080 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 28520 38080 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 27730 32640 ) ( 29310 32640 ) + NEW met3 0 + SHAPE STRIPE ( 28520 32640 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 27750 32640 ) ( 29290 32640 ) + NEW met2 0 + SHAPE STRIPE ( 28520 32640 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 28520 32640 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 27730 27200 ) ( 29310 27200 ) + NEW met3 0 + SHAPE STRIPE ( 28520 27200 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 27750 27200 ) ( 29290 27200 ) + NEW met2 0 + SHAPE STRIPE ( 28520 27200 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 28520 27200 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 27730 21760 ) ( 29310 21760 ) + NEW met3 0 + SHAPE STRIPE ( 28520 21760 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 27750 21760 ) ( 29290 21760 ) + NEW met2 0 + SHAPE STRIPE ( 28520 21760 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 28520 21760 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 27730 16320 ) ( 29310 16320 ) + NEW met3 0 + SHAPE STRIPE ( 28520 16320 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 27750 16320 ) ( 29290 16320 ) + NEW met2 0 + SHAPE STRIPE ( 28520 16320 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 28520 16320 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 27730 10880 ) ( 29310 10880 ) + NEW met3 0 + SHAPE STRIPE ( 28520 10880 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 27750 10880 ) ( 29290 10880 ) + NEW met2 0 + SHAPE STRIPE ( 28520 10880 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 28520 10880 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 27730 5440 ) ( 29310 5440 ) + NEW met3 0 + SHAPE STRIPE ( 28520 5440 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 27750 5440 ) ( 29290 5440 ) + NEW met2 0 + SHAPE STRIPE ( 28520 5440 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 28520 5440 ) via2_3_1600_480_1_5_320_320 ; + - VSS ( * VGND ) + USE GROUND + + ROUTED met5 1600 + SHAPE STRIPE ( 14150 70720 ) ( 70030 70720 ) + NEW met5 1600 + SHAPE STRIPE ( 14150 43520 ) ( 70030 43520 ) + NEW met5 1600 + SHAPE STRIPE ( 14150 16320 ) ( 70030 16320 ) + NEW met4 1600 + SHAPE STRIPE ( 69230 2480 ) ( 69230 84560 ) + NEW met4 1600 + SHAPE STRIPE ( 42090 2480 ) ( 42090 84560 ) + NEW met4 1600 + SHAPE STRIPE ( 14950 2480 ) ( 14950 84560 ) + NEW met1 480 + SHAPE FOLLOWPIN ( 1380 84320 ) ( 85560 84320 ) + NEW met1 480 + SHAPE FOLLOWPIN ( 1380 78880 ) ( 85560 78880 ) + NEW met1 480 + SHAPE FOLLOWPIN ( 1380 73440 ) ( 85560 73440 ) + NEW met1 480 + SHAPE FOLLOWPIN ( 1380 68000 ) ( 85560 68000 ) + NEW met1 480 + SHAPE FOLLOWPIN ( 1380 62560 ) ( 85560 62560 ) + NEW met1 480 + SHAPE FOLLOWPIN ( 1380 57120 ) ( 85560 57120 ) + NEW met1 480 + SHAPE FOLLOWPIN ( 1380 51680 ) ( 85560 51680 ) + NEW met1 480 + SHAPE FOLLOWPIN ( 1380 46240 ) ( 85560 46240 ) + NEW met1 480 + SHAPE FOLLOWPIN ( 1380 40800 ) ( 85560 40800 ) + NEW met1 480 + SHAPE FOLLOWPIN ( 1380 35360 ) ( 85560 35360 ) + NEW met1 480 + SHAPE FOLLOWPIN ( 1380 29920 ) ( 85560 29920 ) + NEW met1 480 + SHAPE FOLLOWPIN ( 1380 24480 ) ( 85560 24480 ) + NEW met1 480 + SHAPE FOLLOWPIN ( 1380 19040 ) ( 85560 19040 ) + NEW met1 480 + SHAPE FOLLOWPIN ( 1380 13600 ) ( 85560 13600 ) + NEW met1 480 + SHAPE FOLLOWPIN ( 1380 8160 ) ( 85560 8160 ) + NEW met1 480 + SHAPE FOLLOWPIN ( 1380 2720 ) ( 85560 2720 ) + NEW met4 0 + SHAPE STRIPE ( 69230 70720 ) via5_6_1600_1600_1_1_1600_1600 + NEW met4 0 + SHAPE STRIPE ( 69230 43520 ) via5_6_1600_1600_1_1_1600_1600 + NEW met4 0 + SHAPE STRIPE ( 69230 16320 ) via5_6_1600_1600_1_1_1600_1600 + NEW met4 0 + SHAPE STRIPE ( 42090 70720 ) via5_6_1600_1600_1_1_1600_1600 + NEW met4 0 + SHAPE STRIPE ( 42090 43520 ) via5_6_1600_1600_1_1_1600_1600 + NEW met4 0 + SHAPE STRIPE ( 42090 16320 ) via5_6_1600_1600_1_1_1600_1600 + NEW met4 0 + SHAPE STRIPE ( 14950 70720 ) via5_6_1600_1600_1_1_1600_1600 + NEW met4 0 + SHAPE STRIPE ( 14950 43520 ) via5_6_1600_1600_1_1_1600_1600 + NEW met4 0 + SHAPE STRIPE ( 14950 16320 ) via5_6_1600_1600_1_1_1600_1600 + NEW met3 330 + SHAPE STRIPE ( 68440 84320 ) ( 70020 84320 ) + NEW met3 0 + SHAPE STRIPE ( 69230 84320 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 68460 84320 ) ( 70000 84320 ) + NEW met2 0 + SHAPE STRIPE ( 69230 84320 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 69230 84320 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 68440 78880 ) ( 70020 78880 ) + NEW met3 0 + SHAPE STRIPE ( 69230 78880 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 68460 78880 ) ( 70000 78880 ) + NEW met2 0 + SHAPE STRIPE ( 69230 78880 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 69230 78880 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 68440 73440 ) ( 70020 73440 ) + NEW met3 0 + SHAPE STRIPE ( 69230 73440 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 68460 73440 ) ( 70000 73440 ) + NEW met2 0 + SHAPE STRIPE ( 69230 73440 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 69230 73440 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 68440 68000 ) ( 70020 68000 ) + NEW met3 0 + SHAPE STRIPE ( 69230 68000 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 68460 68000 ) ( 70000 68000 ) + NEW met2 0 + SHAPE STRIPE ( 69230 68000 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 69230 68000 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 68440 62560 ) ( 70020 62560 ) + NEW met3 0 + SHAPE STRIPE ( 69230 62560 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 68460 62560 ) ( 70000 62560 ) + NEW met2 0 + SHAPE STRIPE ( 69230 62560 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 69230 62560 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 68440 57120 ) ( 70020 57120 ) + NEW met3 0 + SHAPE STRIPE ( 69230 57120 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 68460 57120 ) ( 70000 57120 ) + NEW met2 0 + SHAPE STRIPE ( 69230 57120 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 69230 57120 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 68440 51680 ) ( 70020 51680 ) + NEW met3 0 + SHAPE STRIPE ( 69230 51680 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 68460 51680 ) ( 70000 51680 ) + NEW met2 0 + SHAPE STRIPE ( 69230 51680 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 69230 51680 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 68440 46240 ) ( 70020 46240 ) + NEW met3 0 + SHAPE STRIPE ( 69230 46240 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 68460 46240 ) ( 70000 46240 ) + NEW met2 0 + SHAPE STRIPE ( 69230 46240 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 69230 46240 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 68440 40800 ) ( 70020 40800 ) + NEW met3 0 + SHAPE STRIPE ( 69230 40800 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 68460 40800 ) ( 70000 40800 ) + NEW met2 0 + SHAPE STRIPE ( 69230 40800 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 69230 40800 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 68440 35360 ) ( 70020 35360 ) + NEW met3 0 + SHAPE STRIPE ( 69230 35360 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 68460 35360 ) ( 70000 35360 ) + NEW met2 0 + SHAPE STRIPE ( 69230 35360 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 69230 35360 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 68440 29920 ) ( 70020 29920 ) + NEW met3 0 + SHAPE STRIPE ( 69230 29920 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 68460 29920 ) ( 70000 29920 ) + NEW met2 0 + SHAPE STRIPE ( 69230 29920 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 69230 29920 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 68440 24480 ) ( 70020 24480 ) + NEW met3 0 + SHAPE STRIPE ( 69230 24480 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 68460 24480 ) ( 70000 24480 ) + NEW met2 0 + SHAPE STRIPE ( 69230 24480 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 69230 24480 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 68440 19040 ) ( 70020 19040 ) + NEW met3 0 + SHAPE STRIPE ( 69230 19040 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 68460 19040 ) ( 70000 19040 ) + NEW met2 0 + SHAPE STRIPE ( 69230 19040 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 69230 19040 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 68440 13600 ) ( 70020 13600 ) + NEW met3 0 + SHAPE STRIPE ( 69230 13600 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 68460 13600 ) ( 70000 13600 ) + NEW met2 0 + SHAPE STRIPE ( 69230 13600 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 69230 13600 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 68440 8160 ) ( 70020 8160 ) + NEW met3 0 + SHAPE STRIPE ( 69230 8160 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 68460 8160 ) ( 70000 8160 ) + NEW met2 0 + SHAPE STRIPE ( 69230 8160 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 69230 8160 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 68440 2720 ) ( 70020 2720 ) + NEW met3 0 + SHAPE STRIPE ( 69230 2720 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 68460 2720 ) ( 70000 2720 ) + NEW met2 0 + SHAPE STRIPE ( 69230 2720 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 69230 2720 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 41300 84320 ) ( 42880 84320 ) + NEW met3 0 + SHAPE STRIPE ( 42090 84320 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 41320 84320 ) ( 42860 84320 ) + NEW met2 0 + SHAPE STRIPE ( 42090 84320 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 42090 84320 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 41300 78880 ) ( 42880 78880 ) + NEW met3 0 + SHAPE STRIPE ( 42090 78880 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 41320 78880 ) ( 42860 78880 ) + NEW met2 0 + SHAPE STRIPE ( 42090 78880 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 42090 78880 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 41300 73440 ) ( 42880 73440 ) + NEW met3 0 + SHAPE STRIPE ( 42090 73440 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 41320 73440 ) ( 42860 73440 ) + NEW met2 0 + SHAPE STRIPE ( 42090 73440 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 42090 73440 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 41300 68000 ) ( 42880 68000 ) + NEW met3 0 + SHAPE STRIPE ( 42090 68000 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 41320 68000 ) ( 42860 68000 ) + NEW met2 0 + SHAPE STRIPE ( 42090 68000 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 42090 68000 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 41300 62560 ) ( 42880 62560 ) + NEW met3 0 + SHAPE STRIPE ( 42090 62560 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 41320 62560 ) ( 42860 62560 ) + NEW met2 0 + SHAPE STRIPE ( 42090 62560 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 42090 62560 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 41300 57120 ) ( 42880 57120 ) + NEW met3 0 + SHAPE STRIPE ( 42090 57120 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 41320 57120 ) ( 42860 57120 ) + NEW met2 0 + SHAPE STRIPE ( 42090 57120 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 42090 57120 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 41300 51680 ) ( 42880 51680 ) + NEW met3 0 + SHAPE STRIPE ( 42090 51680 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 41320 51680 ) ( 42860 51680 ) + NEW met2 0 + SHAPE STRIPE ( 42090 51680 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 42090 51680 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 41300 46240 ) ( 42880 46240 ) + NEW met3 0 + SHAPE STRIPE ( 42090 46240 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 41320 46240 ) ( 42860 46240 ) + NEW met2 0 + SHAPE STRIPE ( 42090 46240 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 42090 46240 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 41300 40800 ) ( 42880 40800 ) + NEW met3 0 + SHAPE STRIPE ( 42090 40800 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 41320 40800 ) ( 42860 40800 ) + NEW met2 0 + SHAPE STRIPE ( 42090 40800 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 42090 40800 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 41300 35360 ) ( 42880 35360 ) + NEW met3 0 + SHAPE STRIPE ( 42090 35360 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 41320 35360 ) ( 42860 35360 ) + NEW met2 0 + SHAPE STRIPE ( 42090 35360 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 42090 35360 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 41300 29920 ) ( 42880 29920 ) + NEW met3 0 + SHAPE STRIPE ( 42090 29920 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 41320 29920 ) ( 42860 29920 ) + NEW met2 0 + SHAPE STRIPE ( 42090 29920 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 42090 29920 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 41300 24480 ) ( 42880 24480 ) + NEW met3 0 + SHAPE STRIPE ( 42090 24480 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 41320 24480 ) ( 42860 24480 ) + NEW met2 0 + SHAPE STRIPE ( 42090 24480 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 42090 24480 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 41300 19040 ) ( 42880 19040 ) + NEW met3 0 + SHAPE STRIPE ( 42090 19040 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 41320 19040 ) ( 42860 19040 ) + NEW met2 0 + SHAPE STRIPE ( 42090 19040 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 42090 19040 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 41300 13600 ) ( 42880 13600 ) + NEW met3 0 + SHAPE STRIPE ( 42090 13600 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 41320 13600 ) ( 42860 13600 ) + NEW met2 0 + SHAPE STRIPE ( 42090 13600 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 42090 13600 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 41300 8160 ) ( 42880 8160 ) + NEW met3 0 + SHAPE STRIPE ( 42090 8160 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 41320 8160 ) ( 42860 8160 ) + NEW met2 0 + SHAPE STRIPE ( 42090 8160 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 42090 8160 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 41300 2720 ) ( 42880 2720 ) + NEW met3 0 + SHAPE STRIPE ( 42090 2720 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 41320 2720 ) ( 42860 2720 ) + NEW met2 0 + SHAPE STRIPE ( 42090 2720 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 42090 2720 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 14160 84320 ) ( 15740 84320 ) + NEW met3 0 + SHAPE STRIPE ( 14950 84320 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 14180 84320 ) ( 15720 84320 ) + NEW met2 0 + SHAPE STRIPE ( 14950 84320 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 14950 84320 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 14160 78880 ) ( 15740 78880 ) + NEW met3 0 + SHAPE STRIPE ( 14950 78880 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 14180 78880 ) ( 15720 78880 ) + NEW met2 0 + SHAPE STRIPE ( 14950 78880 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 14950 78880 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 14160 73440 ) ( 15740 73440 ) + NEW met3 0 + SHAPE STRIPE ( 14950 73440 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 14180 73440 ) ( 15720 73440 ) + NEW met2 0 + SHAPE STRIPE ( 14950 73440 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 14950 73440 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 14160 68000 ) ( 15740 68000 ) + NEW met3 0 + SHAPE STRIPE ( 14950 68000 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 14180 68000 ) ( 15720 68000 ) + NEW met2 0 + SHAPE STRIPE ( 14950 68000 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 14950 68000 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 14160 62560 ) ( 15740 62560 ) + NEW met3 0 + SHAPE STRIPE ( 14950 62560 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 14180 62560 ) ( 15720 62560 ) + NEW met2 0 + SHAPE STRIPE ( 14950 62560 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 14950 62560 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 14160 57120 ) ( 15740 57120 ) + NEW met3 0 + SHAPE STRIPE ( 14950 57120 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 14180 57120 ) ( 15720 57120 ) + NEW met2 0 + SHAPE STRIPE ( 14950 57120 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 14950 57120 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 14160 51680 ) ( 15740 51680 ) + NEW met3 0 + SHAPE STRIPE ( 14950 51680 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 14180 51680 ) ( 15720 51680 ) + NEW met2 0 + SHAPE STRIPE ( 14950 51680 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 14950 51680 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 14160 46240 ) ( 15740 46240 ) + NEW met3 0 + SHAPE STRIPE ( 14950 46240 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 14180 46240 ) ( 15720 46240 ) + NEW met2 0 + SHAPE STRIPE ( 14950 46240 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 14950 46240 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 14160 40800 ) ( 15740 40800 ) + NEW met3 0 + SHAPE STRIPE ( 14950 40800 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 14180 40800 ) ( 15720 40800 ) + NEW met2 0 + SHAPE STRIPE ( 14950 40800 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 14950 40800 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 14160 35360 ) ( 15740 35360 ) + NEW met3 0 + SHAPE STRIPE ( 14950 35360 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 14180 35360 ) ( 15720 35360 ) + NEW met2 0 + SHAPE STRIPE ( 14950 35360 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 14950 35360 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 14160 29920 ) ( 15740 29920 ) + NEW met3 0 + SHAPE STRIPE ( 14950 29920 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 14180 29920 ) ( 15720 29920 ) + NEW met2 0 + SHAPE STRIPE ( 14950 29920 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 14950 29920 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 14160 24480 ) ( 15740 24480 ) + NEW met3 0 + SHAPE STRIPE ( 14950 24480 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 14180 24480 ) ( 15720 24480 ) + NEW met2 0 + SHAPE STRIPE ( 14950 24480 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 14950 24480 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 14160 19040 ) ( 15740 19040 ) + NEW met3 0 + SHAPE STRIPE ( 14950 19040 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 14180 19040 ) ( 15720 19040 ) + NEW met2 0 + SHAPE STRIPE ( 14950 19040 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 14950 19040 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 14160 13600 ) ( 15740 13600 ) + NEW met3 0 + SHAPE STRIPE ( 14950 13600 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 14180 13600 ) ( 15720 13600 ) + NEW met2 0 + SHAPE STRIPE ( 14950 13600 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 14950 13600 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 14160 8160 ) ( 15740 8160 ) + NEW met3 0 + SHAPE STRIPE ( 14950 8160 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 14180 8160 ) ( 15720 8160 ) + NEW met2 0 + SHAPE STRIPE ( 14950 8160 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 14950 8160 ) via2_3_1600_480_1_5_320_320 + NEW met3 330 + SHAPE STRIPE ( 14160 2720 ) ( 15740 2720 ) + NEW met3 0 + SHAPE STRIPE ( 14950 2720 ) via4_5_1600_480_1_4_400_400 + NEW met2 370 + SHAPE STRIPE ( 14180 2720 ) ( 15720 2720 ) + NEW met2 0 + SHAPE STRIPE ( 14950 2720 ) via3_4_1600_480_1_4_400_400 + NEW met1 0 + SHAPE STRIPE ( 14950 2720 ) via2_3_1600_480_1_5_320_320 ; +END SPECIALNETS +NETS 475 ; + - _000_ ( req_rdy$_DFF_P_ D ) ( _380_ Y ) + USE SIGNAL ; + - _001_ ( ctrl.state.out\[1\]$_DFF_P_ D ) ( _384_ Y ) + USE SIGNAL ; + - _002_ ( ctrl.state.out\[2\]$_DFF_P_ D ) ( _373_ Y ) + USE SIGNAL ; + - _003_ ( dpath.a_lt_b$in1\[0\]$_DFFE_PP_ D ) ( _451_ Y ) + USE SIGNAL ; + - _004_ ( dpath.a_lt_b$in1\[1\]$_DFFE_PP_ D ) ( _461_ Y ) + USE SIGNAL ; + - _005_ ( dpath.a_lt_b$in1\[2\]$_DFFE_PP_ D ) ( _465_ Y ) + USE SIGNAL ; + - _006_ ( dpath.a_lt_b$in1\[3\]$_DFFE_PP_ D ) ( _472_ Y ) + USE SIGNAL ; + - _007_ ( dpath.a_lt_b$in1\[4\]$_DFFE_PP_ D ) ( _477_ Y ) + USE SIGNAL ; + - _008_ ( dpath.a_lt_b$in1\[5\]$_DFFE_PP_ D ) ( _482_ Y ) + USE SIGNAL ; + - _009_ ( dpath.a_lt_b$in1\[6\]$_DFFE_PP_ D ) ( _485_ Y ) + USE SIGNAL ; + - _010_ ( dpath.a_lt_b$in1\[7\]$_DFFE_PP_ D ) ( _490_ Y ) + USE SIGNAL ; + - _011_ ( dpath.a_lt_b$in1\[8\]$_DFFE_PP_ D ) ( _494_ Y ) + USE SIGNAL ; + - _012_ ( dpath.a_lt_b$in1\[9\]$_DFFE_PP_ D ) ( _497_ Y ) + USE SIGNAL ; + - _013_ ( dpath.a_lt_b$in1\[10\]$_DFFE_PP_ D ) ( _502_ Y ) + USE SIGNAL ; + - _014_ ( dpath.a_lt_b$in1\[11\]$_DFFE_PP_ D ) ( _506_ Y ) + USE SIGNAL ; + - _015_ ( dpath.a_lt_b$in1\[12\]$_DFFE_PP_ D ) ( _509_ Y ) + USE SIGNAL ; + - _016_ ( dpath.a_lt_b$in1\[13\]$_DFFE_PP_ D ) ( _514_ Y ) + USE SIGNAL ; + - _017_ ( dpath.a_lt_b$in1\[14\]$_DFFE_PP_ D ) ( _517_ Y ) + USE SIGNAL ; + - _018_ ( dpath.a_lt_b$in1\[15\]$_DFFE_PP_ D ) ( _520_ Y ) + USE SIGNAL ; + - _019_ ( dpath.a_lt_b$in0\[0\]$_DFFE_PP_ D ) ( _526_ Y ) + USE SIGNAL ; + - _020_ ( dpath.a_lt_b$in0\[1\]$_DFFE_PP_ D ) ( _537_ Y ) + USE SIGNAL ; + - _021_ ( dpath.a_lt_b$in0\[2\]$_DFFE_PP_ D ) ( _547_ Y ) + USE SIGNAL ; + - _022_ ( dpath.a_lt_b$in0\[3\]$_DFFE_PP_ D ) ( _558_ Y ) + USE SIGNAL ; + - _023_ ( dpath.a_lt_b$in0\[4\]$_DFFE_PP_ D ) ( _573_ Y ) + USE SIGNAL ; + - _024_ ( dpath.a_lt_b$in0\[5\]$_DFFE_PP_ D ) ( _583_ Y ) + USE SIGNAL ; + - _025_ ( dpath.a_lt_b$in0\[6\]$_DFFE_PP_ D ) ( _596_ Y ) + USE SIGNAL ; + - _026_ ( dpath.a_lt_b$in0\[7\]$_DFFE_PP_ D ) ( _608_ Y ) + USE SIGNAL ; + - _027_ ( dpath.a_lt_b$in0\[8\]$_DFFE_PP_ D ) ( _617_ Y ) + USE SIGNAL ; + - _028_ ( dpath.a_lt_b$in0\[9\]$_DFFE_PP_ D ) ( _628_ Y ) + USE SIGNAL ; + - _029_ ( dpath.a_lt_b$in0\[10\]$_DFFE_PP_ D ) ( _643_ Y ) + USE SIGNAL ; + - _030_ ( dpath.a_lt_b$in0\[11\]$_DFFE_PP_ D ) ( _653_ Y ) + USE SIGNAL ; + - _031_ ( dpath.a_lt_b$in0\[12\]$_DFFE_PP_ D ) ( _665_ Y ) + USE SIGNAL ; + - _032_ ( dpath.a_lt_b$in0\[13\]$_DFFE_PP_ D ) ( _680_ Y ) + USE SIGNAL ; + - _033_ ( dpath.a_lt_b$in0\[14\]$_DFFE_PP_ D ) ( _696_ Y ) + USE SIGNAL ; + - _034_ ( dpath.a_lt_b$in0\[15\]$_DFFE_PP_ D ) ( _702_ Y ) + USE SIGNAL ; + - _038_ ( _368_ A ) ( _358_ Y ) + USE SIGNAL ; + - _041_ ( _368_ B ) ( _361_ Y ) + USE SIGNAL ; + - _044_ ( _368_ C ) ( _364_ Y ) + USE SIGNAL ; + - _047_ ( _368_ D ) ( _367_ Y ) + USE SIGNAL ; + - _048_ ( _382_ B ) ( _372_ B1 ) ( _368_ Y ) + USE SIGNAL ; + - _052_ ( _373_ B ) ( _372_ Y ) + USE SIGNAL ; + - _053_ ( _468_ B ) ( _474_ B ) ( _479_ B ) ( _487_ B ) ( _491_ B ) ( _499_ B ) ( _511_ B ) + ( _550_ B ) ( _622_ A ) ( _657_ A ) ( _382_ A ) ( _458_ B ) ( _462_ B ) ( _518_ A2 ) ( _576_ C1 ) + ( _615_ A2 ) ( _620_ C1 ) ( _635_ A1 ) ( _647_ A2 ) ( _663_ B ) ( _377_ A ) ( _533_ B1 ) ( _543_ B1 ) + ( _588_ B ) ( _600_ B ) ( _604_ B ) ( _674_ B1 ) ( _694_ B ) ( _541_ B ) ( _374_ Y ) + USE SIGNAL ; + - _055_ ( _696_ A1 ) ( _651_ B1 ) ( _643_ A1 ) ( _642_ A ) ( _596_ A1 ) ( _595_ A ) ( _380_ A1 ) + ( _377_ B ) ( _376_ Y ) + USE SIGNAL ; + - _056_ ( _383_ A2 ) ( _380_ B1 ) ( _378_ Y ) + USE SIGNAL ; + - _057_ ( _380_ C1 ) ( _379_ Y ) + USE SIGNAL ; + - _059_ ( _383_ B1 ) ( _382_ Y ) + USE SIGNAL ; + - _060_ ( _384_ B ) ( _383_ Y ) + USE SIGNAL ; + - _062_ ( _699_ A1 ) ( _445_ B ) ( _387_ Y ) + USE SIGNAL ; + - _063_ ( _671_ B1 ) ( _666_ A ) ( _434_ C ) ( _394_ A ) ( _388_ Y ) + USE SIGNAL ; + - _064_ ( _666_ B ) ( _394_ B ) ( _389_ Y ) + USE SIGNAL ; + - _065_ ( _688_ B ) ( _435_ B1 ) ( _392_ A_N ) ( _390_ Y ) + USE SIGNAL ; + - _066_ ( _435_ A1 ) ( _392_ B ) ( _391_ Y ) + USE SIGNAL ; + - _067_ ( _707_ A ) ( _394_ C ) ( _392_ Y ) + USE SIGNAL ; + - _068_ ( _706_ A ) ( _394_ D ) ( _393_ X ) + USE SIGNAL ; + - _069_ ( _443_ C1 ) ( _404_ A ) ( _394_ Y ) + USE SIGNAL ; + - _070_ ( _703_ A ) ( _398_ A ) ( _395_ Y ) + USE SIGNAL ; + - _072_ ( _704_ A ) ( _667_ C1 ) ( _398_ B ) ( _397_ Y ) + USE SIGNAL ; + - _073_ ( _403_ A ) ( _398_ Y ) + USE SIGNAL ; + - _074_ ( _725_ A ) ( _403_ B ) ( _399_ X ) + USE SIGNAL ; + - _075_ ( _440_ B1 ) ( _402_ A ) ( _400_ Y ) + USE SIGNAL ; + - _076_ ( _632_ B ) ( _629_ B ) ( _402_ B ) ( _401_ Y ) + USE SIGNAL ; + - _077_ ( _726_ A ) ( _403_ C ) ( _402_ Y ) + USE SIGNAL ; + - _078_ ( _655_ A1 ) ( _404_ B ) ( _403_ Y ) + USE SIGNAL ; + - _079_ ( _455_ A1 ) ( _444_ A1 ) ( _404_ Y ) + USE SIGNAL ; + - _080_ ( _560_ A2 ) ( _544_ B2 ) ( _462_ A ) ( _424_ B ) ( _406_ B ) ( _405_ Y ) + USE SIGNAL ; + - _081_ ( _425_ A2 ) ( _712_ A ) ( _548_ A1 ) ( _412_ A1 ) ( _406_ Y ) + USE SIGNAL ; + - _082_ ( _538_ B1 ) ( _409_ A ) ( _407_ Y ) + USE SIGNAL ; + - _083_ ( _538_ A2 ) ( _530_ B ) ( _409_ C ) ( _408_ Y ) + USE SIGNAL ; + - _084_ ( _425_ A1 ) ( _548_ A2 ) ( _542_ A2 ) ( _541_ C ) ( _412_ A2 ) ( _409_ X ) + USE SIGNAL ; + - _085_ ( _712_ B ) ( _411_ B ) ( _410_ Y ) + USE SIGNAL ; + - _086_ ( _412_ B1 ) ( _411_ Y ) + USE SIGNAL ; + - _087_ ( _633_ A1 ) ( _630_ A1 ) ( _610_ A1 ) ( _552_ A2 ) ( _432_ A1 ) ( _412_ Y ) + USE SIGNAL ; + - _089_ ( _721_ A ) ( _416_ A ) ( _414_ Y ) + USE SIGNAL ; + - _090_ ( _605_ A ) ( _416_ B ) ( _415_ Y ) + USE SIGNAL ; + - _091_ ( _431_ A2 ) ( _423_ A_N ) ( _416_ Y ) + USE SIGNAL ; + - _092_ ( _562_ B1 ) ( _423_ B ) ( _417_ Y ) + USE SIGNAL ; + - _094_ ( _717_ A ) ( _574_ A1 ) ( _422_ A2 ) ( _420_ B ) ( _419_ Y ) + USE SIGNAL ; + - _095_ ( _423_ C ) ( _420_ Y ) + USE SIGNAL ; + - _096_ ( _586_ A ) ( _585_ A ) ( _427_ A ) ( _422_ B1 ) ( _421_ Y ) + USE SIGNAL ; + - _097_ ( _423_ D ) ( _422_ Y ) + USE SIGNAL ; + - _098_ ( _633_ A2 ) ( _630_ A2 ) ( _610_ A2 ) ( _432_ A2 ) ( _423_ X ) + USE SIGNAL ; + - _099_ ( _548_ B1 ) ( _425_ B1 ) ( _424_ Y ) + USE SIGNAL ; + - _100_ ( rebuffer2 A ) ( _633_ A3 ) ( _630_ A3 ) ( _610_ A3 ) ( _425_ Y ) + USE SIGNAL ; + - _101_ ( _717_ B_N ) ( _574_ B1 ) ( _427_ C ) ( _426_ Y ) + USE SIGNAL ; + - _102_ ( _431_ A1 ) ( _427_ X ) + USE SIGNAL ; + - _103_ ( _604_ A ) ( _601_ A1 ) ( _430_ A ) ( _428_ Y ) + USE SIGNAL ; + - _104_ ( _721_ B ) ( _430_ C ) ( _429_ Y ) + USE SIGNAL ; + - _105_ ( _431_ B1 ) ( _430_ X ) + USE SIGNAL ; + - _106_ ( _633_ B1 ) ( _630_ B1 ) ( _610_ B1 ) ( _432_ B1 ) ( _431_ Y ) + USE SIGNAL ; + - _107_ ( _618_ C ) ( _613_ A2 ) ( _609_ A2 ) ( _455_ A2 ) ( _444_ A2 ) ( _432_ X ) + USE SIGNAL ; + - _108_ ( _678_ A ) ( _675_ A1 ) ( _674_ A1 ) ( _434_ A ) ( _433_ Y ) + USE SIGNAL ; + - _109_ ( _435_ A2 ) ( _434_ X ) + USE SIGNAL ; + - _110_ ( _455_ B1 ) ( _444_ B1 ) ( _435_ Y ) + USE SIGNAL ; + - _111_ ( _654_ A1 ) ( _443_ A1 ) ( _436_ Y ) + USE SIGNAL ; + - _112_ ( _667_ A1 ) ( _634_ A ) ( _441_ A ) ( _437_ Y ) + USE SIGNAL ; + - _113_ ( _618_ B ) ( _614_ B2 ) ( _491_ A ) ( _440_ A2 ) ( _438_ Y ) + USE SIGNAL ; + - _114_ ( _440_ A3 ) ( _439_ Y ) + USE SIGNAL ; + - _115_ ( _636_ A ) ( _634_ B ) ( _441_ C ) ( _440_ Y ) + USE SIGNAL ; + - _116_ ( _654_ A2 ) ( _443_ A2 ) ( _441_ X ) + USE SIGNAL ; + - _117_ ( _654_ B1 ) ( _443_ B1 ) ( _442_ Y ) + USE SIGNAL ; + - _118_ ( _455_ C1 ) ( _444_ C1 ) ( _443_ Y ) + USE SIGNAL ; + - _119_ ( _709_ A ) ( _445_ C ) ( _444_ X ) + USE SIGNAL ; + - _120_ ( _524_ B1 ) ( _534_ A2 ) ( _544_ A2 ) ( _605_ B ) ( _609_ B1 ) ( _640_ B ) ( _645_ B1 ) + ( _651_ A2 ) ( _662_ B1 ) ( _678_ B ) ( _603_ B1 ) ( _600_ C ) ( _549_ B1 ) ( _446_ B ) ( _445_ X ) + USE SIGNAL ; + - _121_ ( _448_ S ) ( _459_ A2 ) ( _463_ A2 ) ( _469_ A2 ) ( _475_ A2 ) ( _480_ A2 ) ( _488_ A2 ) + ( _492_ A2 ) ( _500_ A2 ) ( _512_ A2 ) ( _521_ A2 ) ( _515_ S ) ( _507_ S ) ( _504_ S ) ( _495_ S ) + ( _483_ S ) ( _446_ Y ) + USE SIGNAL ; + - _123_ ( _451_ A2 ) ( _448_ Y ) + USE SIGNAL ; + - _125_ ( _451_ B1 ) ( _450_ Y ) + USE SIGNAL ; + - _127_ ( _534_ B2 ) ( _531_ A ) ( _458_ A ) ( _453_ Y ) + USE SIGNAL ; + - _128_ ( _698_ A ) ( _456_ A ) ( _454_ Y ) + USE SIGNAL ; + - _129_ ( _698_ C ) ( _697_ B ) ( _456_ C ) ( _455_ Y ) + USE SIGNAL ; + - _130_ ( _529_ B1 ) ( _540_ B1 ) ( _564_ B1 ) ( _576_ A1 ) ( _592_ B1 ) ( _614_ A2 ) ( _620_ A1 ) + ( _625_ B ) ( _660_ B ) ( _687_ C1 ) ( _458_ C ) ( _462_ C ) ( _468_ C ) ( _474_ C ) ( _479_ C ) + ( _487_ C ) ( _491_ C ) ( _499_ C ) ( _511_ C ) ( _590_ B ) ( _694_ C ) ( _685_ B ) ( _673_ B1 ) + ( _637_ B1 ) ( _581_ A2 ) ( _570_ A2 ) ( _556_ B ) ( _456_ X ) + USE SIGNAL ; + - _132_ ( _459_ B1 ) ( _458_ Y ) + USE SIGNAL ; + - _133_ ( _461_ A2 ) ( _459_ Y ) + USE SIGNAL ; + - _134_ ( _461_ B1 ) ( _460_ Y ) + USE SIGNAL ; + - _135_ ( _463_ B1 ) ( _462_ Y ) + USE SIGNAL ; + - _136_ ( _465_ A2 ) ( _463_ Y ) + USE SIGNAL ; + - _137_ ( _465_ B1 ) ( _464_ Y ) + USE SIGNAL ; + - _138_ ( _714_ B ) ( _554_ A ) ( _468_ A ) ( _466_ Y ) + USE SIGNAL ; + - _140_ ( _469_ B1 ) ( _468_ Y ) + USE SIGNAL ; + - _141_ ( _472_ A2 ) ( _469_ Y ) + USE SIGNAL ; + - _143_ ( _472_ B1 ) ( _471_ Y ) + USE SIGNAL ; + - _144_ ( _567_ A1 ) ( _566_ A ) ( _474_ A ) ( _473_ Y ) + USE SIGNAL ; + - _145_ ( _475_ B1 ) ( _474_ Y ) + USE SIGNAL ; + - _146_ ( _477_ A2 ) ( _475_ Y ) + USE SIGNAL ; + - _147_ ( _477_ B1 ) ( _476_ Y ) + USE SIGNAL ; + - _148_ ( _581_ B2 ) ( _578_ A ) ( _479_ A ) ( _478_ Y ) + USE SIGNAL ; + - _149_ ( _480_ B1 ) ( _479_ Y ) + USE SIGNAL ; + - _150_ ( _482_ A2 ) ( _480_ Y ) + USE SIGNAL ; + - _151_ ( _482_ B1 ) ( _481_ Y ) + USE SIGNAL ; + - _152_ ( _485_ A2 ) ( _483_ Y ) + USE SIGNAL ; + - _153_ ( _485_ B1 ) ( _484_ Y ) + USE SIGNAL ; + - _154_ ( _603_ A1 ) ( _487_ A ) ( _486_ Y ) + USE SIGNAL ; + - _155_ ( _488_ B1 ) ( _487_ Y ) + USE SIGNAL ; + - _156_ ( _490_ A2 ) ( _488_ Y ) + USE SIGNAL ; + - _157_ ( _490_ B1 ) ( _489_ Y ) + USE SIGNAL ; + - _158_ ( _492_ B1 ) ( _491_ Y ) + USE SIGNAL ; + - _159_ ( _494_ A2 ) ( _492_ Y ) + USE SIGNAL ; + - _160_ ( _494_ B1 ) ( _493_ Y ) + USE SIGNAL ; + - _161_ ( _497_ A2 ) ( _495_ Y ) + USE SIGNAL ; + - _162_ ( _497_ B1 ) ( _496_ Y ) + USE SIGNAL ; + - _163_ ( _669_ B ) ( _644_ B ) ( _639_ A1 ) ( _638_ A ) ( _499_ A ) ( _498_ Y ) + USE SIGNAL ; + - _164_ ( _500_ B1 ) ( _499_ Y ) + USE SIGNAL ; + - _165_ ( _502_ A2 ) ( _500_ Y ) + USE SIGNAL ; + - _166_ ( _502_ B1 ) ( _501_ Y ) + USE SIGNAL ; + - _168_ ( _506_ A2 ) ( _504_ Y ) + USE SIGNAL ; + - _169_ ( _506_ B1 ) ( _505_ Y ) + USE SIGNAL ; + - _170_ ( _509_ A2 ) ( _507_ Y ) + USE SIGNAL ; + - _171_ ( _509_ B1 ) ( _508_ Y ) + USE SIGNAL ; + - _172_ ( _683_ A2 ) ( _682_ A2 ) ( _681_ A2 ) ( _675_ B2 ) ( _673_ A1 ) ( _511_ A ) ( _510_ Y ) + USE SIGNAL ; + - _173_ ( _512_ B1 ) ( _511_ Y ) + USE SIGNAL ; + - _174_ ( _514_ A2 ) ( _512_ Y ) + USE SIGNAL ; + - _175_ ( _514_ B1 ) ( _513_ Y ) + USE SIGNAL ; + - _176_ ( _517_ A2 ) ( _515_ Y ) + USE SIGNAL ; + - _177_ ( _517_ B1 ) ( _516_ Y ) + USE SIGNAL ; + - _178_ ( _520_ A2 ) ( _518_ Y ) + USE SIGNAL ; + - _179_ ( _520_ B1 ) ( _519_ Y ) + USE SIGNAL ; + - _180_ ( _526_ A2 ) ( _521_ Y ) + USE SIGNAL ; + - _182_ ( _524_ B2 ) ( _523_ Y ) + USE SIGNAL ; + - _183_ ( _526_ A3 ) ( _524_ Y ) + USE SIGNAL ; + - _184_ ( _526_ B1 ) ( _525_ Y ) + USE SIGNAL ; + - _185_ ( _711_ A ) ( _533_ A2 ) ( _531_ B ) ( _529_ A2 ) ( _527_ Y ) + USE SIGNAL ; + - _187_ ( _535_ A3 ) ( _529_ Y ) + USE SIGNAL ; + - _188_ ( _560_ C1 ) ( _539_ B ) ( _532_ A2 ) ( _530_ Y ) + USE SIGNAL ; + - _189_ ( _532_ B1 ) ( _531_ Y ) + USE SIGNAL ; + - _190_ ( _534_ A3 ) ( _532_ Y ) + USE SIGNAL ; + - _191_ ( _534_ B1 ) ( _533_ Y ) + USE SIGNAL ; + - _192_ ( _535_ B1 ) ( _534_ Y ) + USE SIGNAL ; + - _193_ ( _537_ A2 ) ( _535_ Y ) + USE SIGNAL ; + - _194_ ( _537_ B1 ) ( _536_ Y ) + USE SIGNAL ; + - _195_ ( _560_ B1 ) ( _539_ A ) ( _538_ Y ) + USE SIGNAL ; + - _196_ ( _713_ A ) ( _543_ A2 ) ( _540_ A2 ) ( _539_ X ) + USE SIGNAL ; + - _197_ ( _545_ A3 ) ( _540_ Y ) + USE SIGNAL ; + - _198_ ( _542_ B1 ) ( _541_ Y ) + USE SIGNAL ; + - _199_ ( _544_ A3 ) ( _542_ Y ) + USE SIGNAL ; + - _200_ ( _544_ B1 ) ( _543_ Y ) + USE SIGNAL ; + - _201_ ( _545_ B1 ) ( _544_ Y ) + USE SIGNAL ; + - _202_ ( _547_ A2 ) ( _545_ Y ) + USE SIGNAL ; + - _203_ ( _547_ B1 ) ( _546_ Y ) + USE SIGNAL ; + - _204_ ( _716_ A ) ( _555_ A1 ) ( _554_ B ) ( _549_ A2 ) ( _548_ Y ) + USE SIGNAL ; + - _205_ ( _550_ C ) ( _549_ Y ) + USE SIGNAL ; + - _206_ ( _558_ A2 ) ( _550_ Y ) + USE SIGNAL ; + - _208_ ( _558_ A3 ) ( _552_ Y ) + USE SIGNAL ; + - _209_ ( _555_ A2 ) ( _553_ Y ) + USE SIGNAL ; + - _210_ ( _555_ B1 ) ( _554_ Y ) + USE SIGNAL ; + - _211_ ( _556_ C ) ( _555_ Y ) + USE SIGNAL ; + - _212_ ( _558_ A4 ) ( _556_ X ) + USE SIGNAL ; + - _213_ ( _558_ B1 ) ( _557_ Y ) + USE SIGNAL ; + - _214_ ( _715_ B ) ( _562_ A2 ) ( _560_ D1 ) ( _559_ Y ) + USE SIGNAL ; + - _215_ ( _574_ A2 ) ( _563_ A ) ( _560_ Y ) + USE SIGNAL ; + - _216_ ( _562_ A1 ) ( _561_ Y ) + USE SIGNAL ; + - _217_ ( _574_ A3 ) ( _563_ B ) ( _562_ Y ) + USE SIGNAL ; + - _218_ ( _718_ A ) ( _568_ B ) ( _567_ A2 ) ( _566_ C ) ( _564_ A2 ) ( _563_ Y ) + USE SIGNAL ; + - _219_ ( _571_ A3 ) ( _564_ Y ) + USE SIGNAL ; + - _220_ ( _570_ A1 ) ( _565_ Y ) + USE SIGNAL ; + - _221_ ( _567_ B1 ) ( _566_ Y ) + USE SIGNAL ; + - _222_ ( _570_ A3 ) ( _567_ Y ) + USE SIGNAL ; + - _223_ ( _569_ B ) ( _568_ Y ) + USE SIGNAL ; + - _224_ ( _570_ B1 ) ( _569_ Y ) + USE SIGNAL ; + - _225_ ( _571_ B1 ) ( _570_ X ) + USE SIGNAL ; + - _226_ ( _573_ A2 ) ( _571_ Y ) + USE SIGNAL ; + - _227_ ( _573_ B1 ) ( _572_ Y ) + USE SIGNAL ; + - _228_ ( _720_ A ) ( _591_ A1 ) ( _587_ A1 ) ( _580_ A2 ) ( _579_ A1 ) ( _578_ B ) ( _575_ B ) + ( _574_ Y ) + USE SIGNAL ; + - _229_ ( _576_ A2 ) ( _575_ Y ) + USE SIGNAL ; + - _230_ ( _583_ A2 ) ( _576_ Y ) + USE SIGNAL ; + - _231_ ( _579_ A2 ) ( _577_ Y ) + USE SIGNAL ; + - _232_ ( _579_ B1 ) ( _578_ Y ) + USE SIGNAL ; + - _233_ ( _581_ A3 ) ( _579_ Y ) + USE SIGNAL ; + - _234_ ( _581_ B1 ) ( _580_ Y ) + USE SIGNAL ; + - _235_ ( _583_ A3 ) ( _581_ X ) + USE SIGNAL ; + - _236_ ( _583_ B1 ) ( _582_ Y ) + USE SIGNAL ; + - _237_ ( _599_ A ) ( _597_ B1 ) ( _593_ A1 ) ( _590_ A ) ( _584_ Y ) + USE SIGNAL ; + - _238_ ( _591_ A2 ) ( _587_ A2 ) ( _585_ Y ) + USE SIGNAL ; + - _239_ ( _591_ B1 ) ( _587_ B1 ) ( _586_ Y ) + USE SIGNAL ; + - _240_ ( _599_ C ) ( _597_ A2 ) ( _593_ A2 ) ( _589_ A2 ) ( _588_ C ) ( _587_ Y ) + USE SIGNAL ; + - _241_ ( _589_ B1 ) ( _588_ Y ) + USE SIGNAL ; + - _242_ ( _590_ C ) ( _589_ X ) + USE SIGNAL ; + - _243_ ( _596_ A2 ) ( _590_ Y ) + USE SIGNAL ; + - _244_ ( _722_ A ) ( _592_ A2 ) ( _591_ X ) + USE SIGNAL ; + - _245_ ( _594_ A3 ) ( _592_ Y ) + USE SIGNAL ; + - _246_ ( _594_ B1 ) ( _593_ Y ) + USE SIGNAL ; + - _247_ ( _596_ A3 ) ( _594_ Y ) + USE SIGNAL ; + - _248_ ( _596_ B1 ) ( _595_ Y ) + USE SIGNAL ; + - _249_ ( _598_ B ) ( _597_ Y ) + USE SIGNAL ; + - _250_ ( _602_ A1 ) ( _598_ Y ) + USE SIGNAL ; + - _251_ ( _724_ A ) ( _606_ A1 ) ( _603_ A2 ) ( _601_ A2 ) ( _600_ D ) ( _599_ X ) + USE SIGNAL ; + - _252_ ( _602_ A2 ) ( _600_ Y ) + USE SIGNAL ; + - _253_ ( _602_ B1 ) ( _601_ Y ) + USE SIGNAL ; + - _254_ ( _608_ A1 ) ( _602_ Y ) + USE SIGNAL ; + - _255_ ( _604_ C ) ( _603_ Y ) + USE SIGNAL ; + - _256_ ( _608_ A2 ) ( _604_ X ) + USE SIGNAL ; + - _257_ ( _606_ A2 ) ( _605_ Y ) + USE SIGNAL ; + - _258_ ( _608_ A3 ) ( _606_ Y ) + USE SIGNAL ; + - _259_ ( _608_ B1 ) ( _607_ Y ) + USE SIGNAL ; + - _260_ ( _615_ A3 ) ( _609_ Y ) + USE SIGNAL ; + - _261_ ( _725_ B ) ( _655_ A2 ) ( _612_ A2 ) ( _611_ C ) ( _610_ Y ) + USE SIGNAL ; + - _262_ ( _612_ B1 ) ( _611_ Y ) + USE SIGNAL ; + - _263_ ( _614_ A3 ) ( _612_ Y ) + USE SIGNAL ; + - _264_ ( _614_ B1 ) ( _613_ Y ) + USE SIGNAL ; + - _265_ ( _615_ B1 ) ( _614_ Y ) + USE SIGNAL ; + - _266_ ( _617_ A2 ) ( _615_ Y ) + USE SIGNAL ; + - _267_ ( _617_ B1 ) ( _616_ Y ) + USE SIGNAL ; + - _268_ ( _726_ B ) ( _624_ S ) ( _621_ B ) ( _619_ B ) ( _618_ X ) + USE SIGNAL ; + - _269_ ( _620_ A2 ) ( _619_ Y ) + USE SIGNAL ; + - _270_ ( _628_ A2 ) ( _620_ Y ) + USE SIGNAL ; + - _271_ ( _622_ B ) ( _621_ Y ) + USE SIGNAL ; + - _272_ ( _626_ A2 ) ( _622_ Y ) + USE SIGNAL ; + - _273_ ( _624_ A0 ) ( _623_ Y ) + USE SIGNAL ; + - _274_ ( _625_ C ) ( _624_ Y ) + USE SIGNAL ; + - _275_ ( _626_ B1 ) ( _625_ Y ) + USE SIGNAL ; + - _276_ ( _628_ A3 ) ( _626_ Y ) + USE SIGNAL ; + - _277_ ( _628_ B1 ) ( _627_ Y ) + USE SIGNAL ; + - _278_ ( _630_ C1 ) ( _629_ Y ) + USE SIGNAL ; + - _279_ ( _636_ B ) ( _634_ C ) ( _630_ Y ) + USE SIGNAL ; + - _280_ ( _632_ A ) ( _631_ Y ) + USE SIGNAL ; + - _281_ ( _633_ C1 ) ( _632_ Y ) + USE SIGNAL ; + - _282_ ( _636_ C ) ( _634_ D ) ( _633_ Y ) + USE SIGNAL ; + - _283_ ( _635_ A2 ) ( _634_ Y ) + USE SIGNAL ; + - _284_ ( _643_ A2 ) ( _635_ Y ) + USE SIGNAL ; + - _285_ ( rebuffer1 A ) ( _703_ B ) ( _681_ B1 ) ( _644_ C ) ( _639_ A2 ) ( _638_ C ) ( _637_ A2 ) + ( _636_ Y ) + USE SIGNAL ; + - _286_ ( _641_ A3 ) ( _637_ Y ) + USE SIGNAL ; + - _287_ ( _639_ B1 ) ( _638_ Y ) + USE SIGNAL ; + - _288_ ( _641_ B1 ) ( _639_ Y ) + USE SIGNAL ; + - _289_ ( _641_ B2 ) ( _640_ Y ) + USE SIGNAL ; + - _290_ ( _643_ A3 ) ( _641_ Y ) + USE SIGNAL ; + - _291_ ( _643_ B1 ) ( _642_ Y ) + USE SIGNAL ; + - _292_ ( _704_ B ) ( _650_ S ) ( _646_ A2 ) ( _645_ A2 ) ( _644_ X ) + USE SIGNAL ; + - _293_ ( _647_ A3 ) ( _645_ Y ) + USE SIGNAL ; + - _294_ ( _647_ B1 ) ( _646_ X ) + USE SIGNAL ; + - _295_ ( _653_ A1 ) ( _647_ Y ) + USE SIGNAL ; + - _296_ ( _670_ A ) ( _651_ A1 ) ( _648_ Y ) + USE SIGNAL ; + - _297_ ( _650_ A0 ) ( _649_ Y ) + USE SIGNAL ; + - _298_ ( _651_ A3 ) ( _650_ X ) + USE SIGNAL ; + - _299_ ( _653_ A2 ) ( _651_ Y ) + USE SIGNAL ; + - _300_ ( _653_ B1 ) ( _652_ Y ) + USE SIGNAL ; + - _301_ ( _655_ B1 ) ( _654_ X ) + USE SIGNAL ; + - _302_ ( _705_ B ) ( _662_ A2 ) ( _659_ S ) ( _656_ B ) ( _655_ Y ) + USE SIGNAL ; + - _303_ ( _657_ B ) ( _656_ Y ) + USE SIGNAL ; + - _304_ ( _661_ A2 ) ( _657_ Y ) + USE SIGNAL ; + - _305_ ( _659_ A0 ) ( _658_ Y ) + USE SIGNAL ; + - _306_ ( _660_ C ) ( _659_ Y ) + USE SIGNAL ; + - _307_ ( _661_ B1 ) ( _660_ Y ) + USE SIGNAL ; + - _308_ ( _665_ A2 ) ( _661_ Y ) + USE SIGNAL ; + - _309_ ( _663_ C ) ( _662_ Y ) + USE SIGNAL ; + - _310_ ( _665_ A3 ) ( _663_ Y ) + USE SIGNAL ; + - _311_ ( _665_ B1 ) ( _664_ Y ) + USE SIGNAL ; + - _312_ ( _705_ A ) ( _667_ B1 ) ( _666_ Y ) + USE SIGNAL ; + - _313_ ( _681_ C1 ) ( _672_ A2 ) ( _667_ Y ) + USE SIGNAL ; + - _314_ ( _671_ A1 ) ( _668_ Y ) + USE SIGNAL ; + - _315_ ( _670_ C ) ( _669_ Y ) + USE SIGNAL ; + - _316_ ( _671_ A2 ) ( _670_ X ) + USE SIGNAL ; + - _317_ ( _682_ B1 ) ( _672_ B1 ) ( _671_ Y ) + USE SIGNAL ; + - _318_ ( _706_ B ) ( _677_ S ) ( _674_ A2 ) ( _673_ A2 ) ( _672_ Y ) + USE SIGNAL ; + - _319_ ( _675_ A3 ) ( _673_ Y ) + USE SIGNAL ; + - _320_ ( _675_ B1 ) ( _674_ X ) + USE SIGNAL ; + - _321_ ( _680_ A2 ) ( _675_ X ) + USE SIGNAL ; + - _322_ ( _677_ A1 ) ( _676_ Y ) + USE SIGNAL ; + - _323_ ( _678_ C ) ( _677_ X ) + USE SIGNAL ; + - _324_ ( _680_ A3 ) ( _678_ Y ) + USE SIGNAL ; + - _325_ ( _680_ B1 ) ( _679_ Y ) + USE SIGNAL ; + - _326_ ( _689_ A ) ( _687_ A1 ) ( _684_ A ) ( _681_ Y ) + USE SIGNAL ; + - _327_ ( _683_ B1 ) ( _682_ X ) + USE SIGNAL ; + - _328_ ( _689_ B ) ( _687_ A2 ) ( _684_ B ) ( _683_ Y ) + USE SIGNAL ; + - _329_ ( _707_ B ) ( _695_ A1 ) ( _690_ A2 ) ( _684_ X ) + USE SIGNAL ; + - _330_ ( _690_ A3 ) ( _685_ Y ) + USE SIGNAL ; + - _331_ ( _687_ B1 ) ( _686_ X ) + USE SIGNAL ; + - _332_ ( _690_ B1 ) ( _687_ Y ) + USE SIGNAL ; + - _333_ ( _689_ C ) ( _688_ Y ) + USE SIGNAL ; + - _334_ ( _690_ C1 ) ( _689_ X ) + USE SIGNAL ; + - _335_ ( _696_ A2 ) ( _690_ Y ) + USE SIGNAL ; + - _336_ ( _696_ B1 ) ( _691_ Y ) + USE SIGNAL ; + - _337_ ( _695_ A2 ) ( _692_ Y ) + USE SIGNAL ; + - _338_ ( _695_ B1 ) ( _693_ Y ) + USE SIGNAL ; + - _339_ ( _695_ D1 ) ( _694_ Y ) + USE SIGNAL ; + - _340_ ( _696_ B2 ) ( _695_ X ) + USE SIGNAL ; + - _341_ ( _700_ A3 ) ( _697_ Y ) + USE SIGNAL ; + - _342_ ( _699_ B1 ) ( _698_ Y ) + USE SIGNAL ; + - _343_ ( _700_ B1 ) ( _699_ Y ) + USE SIGNAL ; + - _344_ ( _702_ A2 ) ( _700_ Y ) + USE SIGNAL ; + - _345_ ( _702_ B1 ) ( _701_ Y ) + USE SIGNAL ; + - _346_ ( _709_ B ) ( _708_ Y ) + USE SIGNAL ; + - _347_ ( _711_ B ) ( _710_ Y ) + USE SIGNAL ; + - _348_ ( _713_ B ) ( _712_ Y ) + USE SIGNAL ; + - _349_ ( _715_ A ) ( _714_ Y ) + USE SIGNAL ; + - _350_ ( _716_ B ) ( _715_ Y ) + USE SIGNAL ; + - _351_ ( _718_ B ) ( _717_ Y ) + USE SIGNAL ; + - _352_ ( _720_ B ) ( _719_ Y ) + USE SIGNAL ; + - _353_ ( _722_ B ) ( _721_ X ) + USE SIGNAL ; + - _354_ ( _724_ B ) ( _723_ X ) + USE SIGNAL ; + - clk ( PIN clk ) ( clkbuf_0_clk A ) + USE CLOCK ; + - clknet_0_clk ( clkbuf_2_3__f_clk A ) ( clkbuf_2_2__f_clk A ) ( clkbuf_2_1__f_clk A ) ( clkbuf_2_0__f_clk A ) ( clkbuf_0_clk X ) + USE CLOCK ; + - clknet_2_0__leaf_clk ( clkload0 A ) ( dpath.a_lt_b$in0\[0\]$_DFFE_PP_ CLK ) ( dpath.a_lt_b$in0\[1\]$_DFFE_PP_ CLK ) ( dpath.a_lt_b$in0\[2\]$_DFFE_PP_ CLK ) ( dpath.a_lt_b$in0\[4\]$_DFFE_PP_ CLK ) ( dpath.a_lt_b$in0\[5\]$_DFFE_PP_ CLK ) ( dpath.a_lt_b$in1\[0\]$_DFFE_PP_ CLK ) + ( dpath.a_lt_b$in1\[1\]$_DFFE_PP_ CLK ) ( dpath.a_lt_b$in1\[2\]$_DFFE_PP_ CLK ) ( dpath.a_lt_b$in1\[4\]$_DFFE_PP_ CLK ) ( clkbuf_2_0__f_clk X ) + USE CLOCK ; + - clknet_2_1__leaf_clk ( ctrl.state.out\[1\]$_DFF_P_ CLK ) ( ctrl.state.out\[2\]$_DFF_P_ CLK ) ( dpath.a_lt_b$in0\[3\]$_DFFE_PP_ CLK ) ( dpath.a_lt_b$in0\[6\]$_DFFE_PP_ CLK ) ( dpath.a_lt_b$in0\[7\]$_DFFE_PP_ CLK ) ( dpath.a_lt_b$in1\[10\]$_DFFE_PP_ CLK ) ( dpath.a_lt_b$in1\[3\]$_DFFE_PP_ CLK ) + ( dpath.a_lt_b$in1\[5\]$_DFFE_PP_ CLK ) ( dpath.a_lt_b$in1\[6\]$_DFFE_PP_ CLK ) ( dpath.a_lt_b$in1\[7\]$_DFFE_PP_ CLK ) ( clkbuf_2_1__f_clk X ) + USE CLOCK ; + - clknet_2_2__leaf_clk ( clkload1 A ) ( dpath.a_lt_b$in0\[12\]$_DFFE_PP_ CLK ) ( dpath.a_lt_b$in0\[13\]$_DFFE_PP_ CLK ) ( dpath.a_lt_b$in0\[15\]$_DFFE_PP_ CLK ) ( dpath.a_lt_b$in0\[8\]$_DFFE_PP_ CLK ) ( dpath.a_lt_b$in0\[9\]$_DFFE_PP_ CLK ) ( dpath.a_lt_b$in1\[12\]$_DFFE_PP_ CLK ) + ( dpath.a_lt_b$in1\[15\]$_DFFE_PP_ CLK ) ( dpath.a_lt_b$in1\[8\]$_DFFE_PP_ CLK ) ( dpath.a_lt_b$in1\[9\]$_DFFE_PP_ CLK ) ( clkbuf_2_2__f_clk X ) + USE CLOCK ; + - clknet_2_3__leaf_clk ( clkload2 A ) ( dpath.a_lt_b$in0\[10\]$_DFFE_PP_ CLK ) ( dpath.a_lt_b$in0\[11\]$_DFFE_PP_ CLK ) ( dpath.a_lt_b$in0\[14\]$_DFFE_PP_ CLK ) ( dpath.a_lt_b$in1\[11\]$_DFFE_PP_ CLK ) ( dpath.a_lt_b$in1\[13\]$_DFFE_PP_ CLK ) ( dpath.a_lt_b$in1\[14\]$_DFFE_PP_ CLK ) + ( req_rdy$_DFF_P_ CLK ) ( clkbuf_2_3__f_clk X ) + USE CLOCK ; + - ctrl.state.out\[1\] ( ctrl.state.out\[1\]$_DFF_P_ Q ) ( _383_ A1 ) ( _377_ C ) + USE SIGNAL ; + - ctrl.state.out\[2\] ( _552_ A1 ) ( _569_ A ) ( _580_ B1 ) ( _601_ B1 ) ( _613_ B1 ) ( _638_ B ) ( _646_ B1 ) + ( _675_ A2 ) ( _693_ B ) ( _699_ A2 ) ( _372_ B2 ) ( _523_ C ) ( _524_ A2 ) ( _535_ A2 ) ( _545_ A2 ) + ( _571_ A2 ) ( _593_ B1 ) ( _594_ A2 ) ( _641_ A2 ) ( _700_ A2 ) ( _532_ A1 ) ( _553_ B ) ( _577_ B ) + ( _611_ B ) ( _623_ B ) ( _649_ B ) ( _658_ B ) ( _676_ B ) ( _686_ B ) ( _374_ A ) ( _446_ A ) + ( _566_ B ) ( _688_ A ) ( ctrl.state.out\[2\]$_DFF_P_ Q ) + USE SIGNAL ; + - dpath.a_lt_b$in0\[0\] ( dpath.a_lt_b$in0\[0\]$_DFFE_PP_ Q ) ( _527_ A ) ( _524_ A1 ) ( _523_ B ) ( _521_ A1 ) ( _448_ A0 ) ( _408_ A_N ) + ( _385_ B ) + USE SIGNAL ; + - dpath.a_lt_b$in0\[10\] ( dpath.a_lt_b$in0\[10\]$_DFFE_PP_ Q ) ( _667_ A2 ) ( _637_ A1 ) ( _635_ B1 ) ( _498_ A ) ( _441_ B ) ( _395_ B ) + USE SIGNAL ; + - dpath.a_lt_b$in0\[11\] ( _397_ B ) ( _436_ B_N ) ( _442_ A_N ) ( _504_ A0 ) ( _645_ A1 ) ( _647_ B2 ) ( _649_ A ) + ( _650_ A1 ) ( _670_ B ) ( dpath.a_lt_b$in0\[11\]$_DFFE_PP_ Q ) + USE SIGNAL ; + - dpath.a_lt_b$in0\[12\] ( dpath.a_lt_b$in0\[12\]$_DFFE_PP_ Q ) ( _668_ A_N ) ( _662_ A1 ) ( _661_ A1 ) ( _659_ A1 ) ( _658_ A ) ( _507_ A0 ) + ( _389_ A ) ( _388_ B_N ) + USE SIGNAL ; + - dpath.a_lt_b$in0\[13\] ( dpath.a_lt_b$in0\[13\]$_DFFE_PP_ Q ) ( _677_ A0 ) ( _676_ A ) ( _510_ A ) ( _434_ B ) ( _393_ B ) + USE SIGNAL ; + - dpath.a_lt_b$in0\[14\] ( dpath.a_lt_b$in0\[14\]$_DFFE_PP_ Q ) ( _693_ A ) ( _692_ B ) ( _690_ A1 ) ( _686_ A ) ( _515_ A0 ) ( _391_ A_N ) + ( _390_ B_N ) + USE SIGNAL ; + - dpath.a_lt_b$in0\[15\] ( dpath.a_lt_b$in0\[15\]$_DFFE_PP_ Q ) ( _708_ B ) ( _698_ B ) ( _697_ A ) ( _518_ A1 ) ( _456_ B ) ( _387_ A ) + USE SIGNAL ; + - dpath.a_lt_b$in0\[1\] ( dpath.a_lt_b$in0\[1\]$_DFFE_PP_ Q ) ( _710_ B ) ( _538_ A1 ) ( _530_ A ) ( _529_ A1 ) ( _453_ A ) ( _409_ B ) + USE SIGNAL ; + - dpath.a_lt_b$in0\[2\] ( dpath.a_lt_b$in0\[2\]$_DFFE_PP_ Q ) ( _561_ B ) ( _542_ A1 ) ( _541_ A ) ( _540_ A1 ) ( _410_ A ) ( _405_ A ) + USE SIGNAL ; + - dpath.a_lt_b$in0\[3\] ( dpath.a_lt_b$in0\[3\]$_DFFE_PP_ Q ) ( _559_ A ) ( _553_ A ) ( _552_ B1 ) ( _549_ A1 ) ( _466_ A ) ( _425_ C1 ) + ( _417_ B ) + USE SIGNAL ; + - dpath.a_lt_b$in0\[4\] ( dpath.a_lt_b$in0\[4\]$_DFFE_PP_ Q ) ( _570_ B2 ) ( _564_ A1 ) ( _473_ A ) ( _426_ A_N ) ( _419_ B_N ) + USE SIGNAL ; + - dpath.a_lt_b$in0\[5\] ( _420_ A ) ( _422_ A1 ) ( _427_ B ) ( _478_ A ) ( _575_ A ) ( _577_ A ) ( _585_ B ) + ( _586_ B ) ( _719_ B ) ( dpath.a_lt_b$in0\[5\]$_DFFE_PP_ Q ) + USE SIGNAL ; + - dpath.a_lt_b$in0\[6\] ( _414_ B ) ( _429_ A_N ) ( _483_ A0 ) ( _588_ A ) ( _589_ A1 ) ( _592_ A1 ) ( _594_ B2 ) + ( _597_ A1 ) ( _599_ B ) ( dpath.a_lt_b$in0\[6\]$_DFFE_PP_ Q ) + USE SIGNAL ; + - dpath.a_lt_b$in0\[7\] ( dpath.a_lt_b$in0\[7\]$_DFFE_PP_ Q ) ( _723_ B ) ( _602_ B2 ) ( _598_ A ) ( _486_ A ) ( _430_ B ) ( _415_ B ) + USE SIGNAL ; + - dpath.a_lt_b$in0\[8\] ( dpath.a_lt_b$in0\[8\]$_DFFE_PP_ Q ) ( _629_ A ) ( _612_ A1 ) ( _611_ A ) ( _609_ A1 ) ( _438_ A ) ( _399_ B ) + USE SIGNAL ; + - dpath.a_lt_b$in0\[9\] ( dpath.a_lt_b$in0\[9\]$_DFFE_PP_ Q ) ( _626_ A1 ) ( _624_ A1 ) ( _623_ A ) ( _619_ A ) ( _495_ A0 ) ( _439_ A ) + ( _401_ A_N ) ( _400_ B ) + USE SIGNAL ; + - dpath.a_lt_b$in1\[0\] ( dpath.a_lt_b$in1\[0\]$_DFFE_PP_ Q ) ( _527_ B_N ) ( _523_ A ) ( _521_ B1 ) ( _448_ A1 ) ( _408_ B ) ( _385_ A ) + ( _358_ D ) + USE SIGNAL ; + - dpath.a_lt_b$in1\[10\] ( _367_ C ) ( _395_ A ) ( _437_ A ) ( _500_ A1 ) ( _640_ A ) ( _641_ A1 ) ( _644_ A ) + ( _669_ A ) ( dpath.a_lt_b$in1\[10\]$_DFFE_PP_ Q ) + USE SIGNAL ; + - dpath.a_lt_b$in1\[11\] ( _367_ B ) ( _397_ A ) ( _436_ A ) ( _442_ B ) ( _504_ A1 ) ( _646_ A1 ) ( _647_ A1 ) + ( _648_ A ) ( dpath.a_lt_b$in1\[11\]$_DFFE_PP_ Q ) + USE SIGNAL ; + - dpath.a_lt_b$in1\[12\] ( dpath.a_lt_b$in1\[12\]$_DFFE_PP_ Q ) ( _668_ B ) ( _663_ A ) ( _660_ A ) ( _656_ A ) ( _507_ A1 ) ( _389_ B_N ) + ( _388_ A ) ( _367_ A ) + USE SIGNAL ; + - dpath.a_lt_b$in1\[13\] ( _364_ C ) ( _393_ A ) ( _433_ A ) ( _512_ A1 ) ( _681_ A1 ) ( _682_ A1 ) ( _683_ A1 ) + ( dpath.a_lt_b$in1\[13\]$_DFFE_PP_ Q ) + USE SIGNAL ; + - dpath.a_lt_b$in1\[14\] ( dpath.a_lt_b$in1\[14\]$_DFFE_PP_ Q ) ( _694_ A ) ( _692_ A ) ( _687_ D1 ) ( _685_ A ) ( _515_ A1 ) ( _391_ B ) + ( _390_ A ) ( _364_ B ) + USE SIGNAL ; + - dpath.a_lt_b$in1\[15\] ( dpath.a_lt_b$in1\[15\]$_DFFE_PP_ Q ) ( _708_ A ) ( _700_ A1 ) ( _518_ B1 ) ( _454_ A ) ( _445_ A ) ( _364_ A ) + USE SIGNAL ; + - dpath.a_lt_b$in1\[1\] ( _361_ D ) ( _407_ A ) ( _459_ A1 ) ( _533_ A1 ) ( _534_ A1 ) ( _535_ A1 ) ( _710_ A ) + ( dpath.a_lt_b$in1\[1\]$_DFFE_PP_ Q ) + USE SIGNAL ; + - dpath.a_lt_b$in1\[2\] ( _361_ C ) ( _406_ A ) ( _410_ B_N ) ( _424_ A ) ( _463_ A1 ) ( _543_ A1 ) ( _544_ A1 ) + ( _545_ A1 ) ( _560_ A1 ) ( _561_ A_N ) ( dpath.a_lt_b$in1\[2\]$_DFFE_PP_ Q ) + USE SIGNAL ; + - dpath.a_lt_b$in1\[3\] ( dpath.a_lt_b$in1\[3\]$_DFFE_PP_ Q ) ( _714_ A ) ( _559_ B_N ) ( _556_ A ) ( _550_ A ) ( _469_ A1 ) ( _417_ A_N ) + ( _411_ A ) ( _361_ B ) + USE SIGNAL ; + - dpath.a_lt_b$in1\[4\] ( dpath.a_lt_b$in1\[4\]$_DFFE_PP_ Q ) ( _571_ A1 ) ( _568_ A ) ( _565_ A ) ( _475_ A1 ) ( _426_ B ) ( _419_ A ) + ( _361_ A ) + USE SIGNAL ; + - dpath.a_lt_b$in1\[5\] ( _358_ C ) ( _421_ A ) ( _480_ A1 ) ( _576_ B1 ) ( _580_ A1 ) ( _581_ A1 ) ( _719_ A ) + ( dpath.a_lt_b$in1\[5\]$_DFFE_PP_ Q ) + USE SIGNAL ; + - dpath.a_lt_b$in1\[6\] ( dpath.a_lt_b$in1\[6\]$_DFFE_PP_ Q ) ( _594_ A1 ) ( _584_ A ) ( _483_ A1 ) ( _429_ B ) ( _414_ A_N ) ( _358_ B ) + USE SIGNAL ; + - dpath.a_lt_b$in1\[7\] ( dpath.a_lt_b$in1\[7\]$_DFFE_PP_ Q ) ( _723_ A ) ( _600_ A ) ( _488_ A1 ) ( _428_ A ) ( _415_ A_N ) ( _358_ A ) + USE SIGNAL ; + - dpath.a_lt_b$in1\[8\] ( _364_ D ) ( _399_ A ) ( _440_ A1 ) ( _492_ A1 ) ( _613_ A1 ) ( _614_ A1 ) ( _615_ A1 ) + ( _618_ A ) ( _631_ A ) ( dpath.a_lt_b$in1\[8\]$_DFFE_PP_ Q ) + USE SIGNAL ; + - dpath.a_lt_b$in1\[9\] ( dpath.a_lt_b$in1\[9\]$_DFFE_PP_ Q ) ( _625_ A ) ( _621_ A ) ( _620_ B1 ) ( _495_ A1 ) ( _439_ B_N ) ( _401_ B ) + ( _400_ A_N ) ( _367_ D ) + USE SIGNAL ; + - net1 ( input1 X ) ( _450_ B ) + USE SIGNAL ; + - net10 ( input10 X ) ( _546_ B ) + USE SIGNAL ; + - net11 ( input11 X ) ( _557_ B ) + USE SIGNAL ; + - net12 ( input12 X ) ( _460_ B ) + USE SIGNAL ; + - net13 ( input13 X ) ( _572_ B ) + USE SIGNAL ; + - net14 ( input14 X ) ( _582_ B ) + USE SIGNAL ; + - net15 ( input15 X ) ( _595_ B ) + USE SIGNAL ; + - net16 ( input16 X ) ( _607_ A ) + USE SIGNAL ; + - net17 ( input17 X ) ( _616_ B ) + USE SIGNAL ; + - net18 ( input18 X ) ( _627_ B ) + USE SIGNAL ; + - net19 ( input19 X ) ( _642_ B ) + USE SIGNAL ; + - net2 ( input2 X ) ( _501_ B ) + USE SIGNAL ; + - net20 ( input20 X ) ( _652_ B ) + USE SIGNAL ; + - net21 ( input21 X ) ( _664_ B ) + USE SIGNAL ; + - net22 ( input22 X ) ( _679_ B ) + USE SIGNAL ; + - net23 ( input23 X ) ( _464_ B ) + USE SIGNAL ; + - net24 ( input24 X ) ( _691_ B ) + USE SIGNAL ; + - net25 ( input25 X ) ( _701_ B ) + USE SIGNAL ; + - net26 ( input26 X ) ( _471_ B ) + USE SIGNAL ; + - net27 ( input27 X ) ( _476_ B ) + USE SIGNAL ; + - net28 ( input28 X ) ( _481_ B ) + USE SIGNAL ; + - net29 ( input29 X ) ( _484_ B ) + USE SIGNAL ; + - net3 ( input3 X ) ( _505_ B ) + USE SIGNAL ; + - net30 ( input30 X ) ( _489_ B ) + USE SIGNAL ; + - net31 ( input31 X ) ( _493_ B ) + USE SIGNAL ; + - net32 ( input32 X ) ( _496_ B ) + USE SIGNAL ; + - net33 ( input33 X ) ( _380_ A2 ) ( _372_ A2 ) + USE SIGNAL ; + - net34 ( input34 X ) ( _384_ A ) ( _379_ A ) ( _373_ A ) + USE SIGNAL ; + - net35 ( input35 X ) ( _378_ A ) + USE SIGNAL ; + - net36 ( output36 A ) ( req_rdy$_DFF_P_ Q ) ( _702_ A1 ) ( _701_ A ) ( _695_ C1 ) ( _691_ A ) ( _680_ A1 ) + ( _679_ A ) ( _665_ A1 ) ( _664_ A ) ( _652_ A ) ( _628_ A1 ) ( _627_ A ) ( _617_ A1 ) ( _616_ A ) + ( _608_ B2 ) ( _606_ B1 ) ( _583_ A1 ) ( _582_ A ) ( _573_ A1 ) ( _572_ A ) ( _558_ A1 ) ( _557_ A ) + ( _547_ A1 ) ( _546_ A ) ( _537_ A1 ) ( _536_ A ) ( _526_ A1 ) ( _525_ A ) ( _520_ A1 ) ( _519_ A ) + ( _517_ A1 ) ( _516_ A ) ( _514_ A1 ) ( _513_ A ) ( _509_ A1 ) ( _508_ A ) ( _506_ A1 ) ( _505_ A ) + ( _502_ A1 ) ( _501_ A ) ( _497_ A1 ) ( _496_ A ) ( _494_ A1 ) ( _493_ A ) ( _490_ A1 ) ( _489_ A ) + ( _485_ A1 ) ( _484_ A ) ( _482_ A1 ) ( _481_ A ) ( _477_ A1 ) ( _476_ A ) ( _472_ A1 ) ( _471_ A ) + ( _465_ A1 ) ( _464_ A ) ( _461_ A1 ) ( _460_ A ) ( _451_ A1 ) ( _450_ A ) ( _376_ A ) ( _372_ A1 ) + USE SIGNAL ; + - net37 ( output37 A ) ( _385_ X ) + USE SIGNAL ; + - net38 ( output38 A ) ( _703_ Y ) + USE SIGNAL ; + - net39 ( output39 A ) ( _704_ Y ) + USE SIGNAL ; + - net4 ( input4 X ) ( _508_ B ) + USE SIGNAL ; + - net40 ( output40 A ) ( _705_ Y ) + USE SIGNAL ; + - net41 ( output41 A ) ( _706_ Y ) + USE SIGNAL ; + - net42 ( output42 A ) ( _707_ Y ) + USE SIGNAL ; + - net43 ( output43 A ) ( _709_ Y ) + USE SIGNAL ; + - net44 ( output44 A ) ( _711_ Y ) + USE SIGNAL ; + - net45 ( output45 A ) ( _713_ Y ) + USE SIGNAL ; + - net46 ( output46 A ) ( _716_ Y ) + USE SIGNAL ; + - net47 ( output47 A ) ( _718_ Y ) + USE SIGNAL ; + - net48 ( output48 A ) ( _720_ Y ) + USE SIGNAL ; + - net49 ( output49 A ) ( _722_ Y ) + USE SIGNAL ; + - net5 ( input5 X ) ( _513_ B ) + USE SIGNAL ; + - net50 ( output50 A ) ( _724_ Y ) + USE SIGNAL ; + - net51 ( output51 A ) ( _725_ Y ) + USE SIGNAL ; + - net52 ( output52 A ) ( _726_ X ) + USE SIGNAL ; + - net53 ( output53 A ) ( _378_ B ) ( _377_ X ) + USE SIGNAL ; + - net54 ( _672_ A1 ) ( rebuffer1 X ) + USE SIGNAL ; + - net55 ( _432_ A3 ) ( rebuffer2 X ) + USE SIGNAL ; + - net6 ( input6 X ) ( _516_ B ) + USE SIGNAL ; + - net7 ( input7 X ) ( _519_ B ) + USE SIGNAL ; + - net8 ( input8 X ) ( _525_ B ) + USE SIGNAL ; + - net9 ( input9 X ) ( _536_ B ) + USE SIGNAL ; + - req_msg[0] ( PIN req_msg[0] ) ( input1 A ) + USE SIGNAL ; + - req_msg[10] ( PIN req_msg[10] ) ( input2 A ) + USE SIGNAL ; + - req_msg[11] ( PIN req_msg[11] ) ( input3 A ) + USE SIGNAL ; + - req_msg[12] ( PIN req_msg[12] ) ( input4 A ) + USE SIGNAL ; + - req_msg[13] ( PIN req_msg[13] ) ( input5 A ) + USE SIGNAL ; + - req_msg[14] ( PIN req_msg[14] ) ( input6 A ) + USE SIGNAL ; + - req_msg[15] ( PIN req_msg[15] ) ( input7 A ) + USE SIGNAL ; + - req_msg[16] ( PIN req_msg[16] ) ( input8 A ) + USE SIGNAL ; + - req_msg[17] ( PIN req_msg[17] ) ( input9 A ) + USE SIGNAL ; + - req_msg[18] ( PIN req_msg[18] ) ( input10 A ) + USE SIGNAL ; + - req_msg[19] ( PIN req_msg[19] ) ( input11 A ) + USE SIGNAL ; + - req_msg[1] ( PIN req_msg[1] ) ( input12 A ) + USE SIGNAL ; + - req_msg[20] ( PIN req_msg[20] ) ( input13 A ) + USE SIGNAL ; + - req_msg[21] ( PIN req_msg[21] ) ( input14 A ) + USE SIGNAL ; + - req_msg[22] ( PIN req_msg[22] ) ( input15 A ) + USE SIGNAL ; + - req_msg[23] ( PIN req_msg[23] ) ( input16 A ) + USE SIGNAL ; + - req_msg[24] ( PIN req_msg[24] ) ( input17 A ) + USE SIGNAL ; + - req_msg[25] ( PIN req_msg[25] ) ( input18 A ) + USE SIGNAL ; + - req_msg[26] ( PIN req_msg[26] ) ( input19 A ) + USE SIGNAL ; + - req_msg[27] ( PIN req_msg[27] ) ( input20 A ) + USE SIGNAL ; + - req_msg[28] ( PIN req_msg[28] ) ( input21 A ) + USE SIGNAL ; + - req_msg[29] ( PIN req_msg[29] ) ( input22 A ) + USE SIGNAL ; + - req_msg[2] ( PIN req_msg[2] ) ( input23 A ) + USE SIGNAL ; + - req_msg[30] ( PIN req_msg[30] ) ( input24 A ) + USE SIGNAL ; + - req_msg[31] ( PIN req_msg[31] ) ( input25 A ) + USE SIGNAL ; + - req_msg[3] ( PIN req_msg[3] ) ( input26 A ) + USE SIGNAL ; + - req_msg[4] ( PIN req_msg[4] ) ( input27 A ) + USE SIGNAL ; + - req_msg[5] ( PIN req_msg[5] ) ( input28 A ) + USE SIGNAL ; + - req_msg[6] ( PIN req_msg[6] ) ( input29 A ) + USE SIGNAL ; + - req_msg[7] ( PIN req_msg[7] ) ( input30 A ) + USE SIGNAL ; + - req_msg[8] ( PIN req_msg[8] ) ( input31 A ) + USE SIGNAL ; + - req_msg[9] ( PIN req_msg[9] ) ( input32 A ) + USE SIGNAL ; + - req_rdy ( PIN req_rdy ) ( output36 X ) + USE SIGNAL ; + - req_val ( PIN req_val ) ( input33 A ) + USE SIGNAL ; + - reset ( PIN reset ) ( input34 A ) + USE SIGNAL ; + - resp_msg[0] ( PIN resp_msg[0] ) ( output37 X ) + USE SIGNAL ; + - resp_msg[10] ( PIN resp_msg[10] ) ( output38 X ) + USE SIGNAL ; + - resp_msg[11] ( PIN resp_msg[11] ) ( output39 X ) + USE SIGNAL ; + - resp_msg[12] ( PIN resp_msg[12] ) ( output40 X ) + USE SIGNAL ; + - resp_msg[13] ( PIN resp_msg[13] ) ( output41 X ) + USE SIGNAL ; + - resp_msg[14] ( PIN resp_msg[14] ) ( output42 X ) + USE SIGNAL ; + - resp_msg[15] ( PIN resp_msg[15] ) ( output43 X ) + USE SIGNAL ; + - resp_msg[1] ( PIN resp_msg[1] ) ( output44 X ) + USE SIGNAL ; + - resp_msg[2] ( PIN resp_msg[2] ) ( output45 X ) + USE SIGNAL ; + - resp_msg[3] ( PIN resp_msg[3] ) ( output46 X ) + USE SIGNAL ; + - resp_msg[4] ( PIN resp_msg[4] ) ( output47 X ) + USE SIGNAL ; + - resp_msg[5] ( PIN resp_msg[5] ) ( output48 X ) + USE SIGNAL ; + - resp_msg[6] ( PIN resp_msg[6] ) ( output49 X ) + USE SIGNAL ; + - resp_msg[7] ( PIN resp_msg[7] ) ( output50 X ) + USE SIGNAL ; + - resp_msg[8] ( PIN resp_msg[8] ) ( output51 X ) + USE SIGNAL ; + - resp_msg[9] ( PIN resp_msg[9] ) ( output52 X ) + USE SIGNAL ; + - resp_rdy ( PIN resp_rdy ) ( input35 A ) + USE SIGNAL ; + - resp_val ( PIN resp_val ) ( output53 X ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/src/psm/test/insert_decap_with_padding1.ok b/src/psm/test/insert_decap_with_padding1.ok new file mode 100644 index 0000000000..8840cb6f54 --- /dev/null +++ b/src/psm/test/insert_decap_with_padding1.ok @@ -0,0 +1,21 @@ +[INFO ODB-0227] LEF file: sky130hd/sky130hd.tlef, created 13 layers, 25 vias +[INFO ODB-0227] LEF file: sky130hd/sky130hd_std_cell.lef, created 437 library cells +[INFO ODB-0128] Design: gcd +[INFO ODB-0130] Created 54 pins. +[INFO ODB-0131] Created 538 components and 2577 component-terminals. +[INFO ODB-0132] Created 2 special nets and 1076 connections. +[INFO ODB-0133] Created 475 nets and 1498 connections. +[INFO PSM-0040] All shapes on net VDD are connected. +[INFO PSM-0073] Using bump pattern with x-pitch 140.0000um, y-pitch 140.0000um, and size 70.0000um with an reduction factor of 3x. +########## IR report ################# +Net : VDD +Corner : default +Supply voltage : 1.40e+00 V +Worstcase voltage: 1.40e+00 V +Average voltage : 1.40e+00 V +Average IR drop : 1.25e-11 V +Worstcase IR drop: 2.85e-11 V +Percentage drop : 0.00 % +###################################### +[INFO DPL-0056] Placed 531 decap cells. Total capacitance: 0.000494 +No differences found. diff --git a/src/psm/test/insert_decap_with_padding1.tcl b/src/psm/test/insert_decap_with_padding1.tcl new file mode 100644 index 0000000000..af26d6e1fc --- /dev/null +++ b/src/psm/test/insert_decap_with_padding1.tcl @@ -0,0 +1,25 @@ +# insert_decap for sky130hd/gcd +source "helpers.tcl" + +read_liberty sky130hd/sky130_fd_sc_hd__ss_n40C_1v40.lib +read_lef "sky130hd/sky130hd.tlef" +read_lef "sky130hd/sky130hd_std_cell.lef" +read_def "sky130hd_data/insert_decap_gcd.def" + +source sky130hd/sky130hd.rc + +analyze_power_grid -net {VDD} + +# Set padding before insert decap cells +set_placement_padding -global -left 1 -right 1 + +insert_decap -target_cap 1000.5 -cells {"sky130_fd_sc_hd__decap_3" 0.93 "sky130_fd_sc_hd__decap_4" 0.124 "sky130_fd_sc_hd__decap_6" 0.186 "sky130_fd_sc_hd__decap_8" 0.248 "sky130_fd_sc_hd__decap_12" 0.362} + +# Reset padding to check placement +set_placement_padding -global -left 0 -right 0 + +check_placement + +set def_file [make_result_file insert_decap_with_padding1.def] +write_def $def_file +diff_file $def_file insert_decap_with_padding1.defok diff --git a/src/psm/test/regression_tests.tcl b/src/psm/test/regression_tests.tcl index f403fe3292..a4e7481508 100644 --- a/src/psm/test/regression_tests.tcl +++ b/src/psm/test/regression_tests.tcl @@ -26,6 +26,7 @@ record_tests { top_grid_settings insert_decap1 insert_decap2 + insert_decap_with_padding1 #psm_man_tcl_check #psm_readme_msgs_check } From bfea522af9cd99d328d578773b6e165f441f40a0 Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Mon, 5 Aug 2024 13:45:12 -0400 Subject: [PATCH 30/37] pad: dont check cover cells for overlap in placing padring Signed-off-by: Peter Gadfort --- src/pad/src/ICeWall.cpp | 3 + src/pad/test/place_pad_with_bumps.defok | 820 ++++++++++++++++++++++++ src/pad/test/place_pad_with_bumps.ok | 7 + src/pad/test/place_pad_with_bumps.tcl | 19 + src/pad/test/regression_tests.tcl | 1 + 5 files changed, 850 insertions(+) create mode 100644 src/pad/test/place_pad_with_bumps.defok create mode 100644 src/pad/test/place_pad_with_bumps.ok create mode 100644 src/pad/test/place_pad_with_bumps.tcl diff --git a/src/pad/src/ICeWall.cpp b/src/pad/src/ICeWall.cpp index 557ba3904c..b24966c526 100644 --- a/src/pad/src/ICeWall.cpp +++ b/src/pad/src/ICeWall.cpp @@ -707,6 +707,9 @@ void ICeWall::placeInstance(odb::dbRow* row, if (!check_inst->isFixed()) { continue; } + if (check_inst->getMaster()->isCover()) { + continue; + } const odb::Rect check_rect = check_inst->getBBox()->getBox(); if (!allow_overlap && inst_rect.overlaps(check_rect)) { logger_->error(utl::PAD, diff --git a/src/pad/test/place_pad_with_bumps.defok b/src/pad/test/place_pad_with_bumps.defok new file mode 100644 index 0000000000..c14b472295 --- /dev/null +++ b/src/pad/test/place_pad_with_bumps.defok @@ -0,0 +1,820 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN soc_bsg_black_parrot ; +UNITS DISTANCE MICRONS 2000 ; +DIEAREA ( 0 0 ) ( 6000000 6000000 ) ; +ROW IO_CORNER_NORTH_WEST IOSITE 30000 5690000 FS DO 140 BY 1 STEP 2000 0 ; +ROW IO_CORNER_NORTH_EAST IOSITE 5690000 5690000 S DO 140 BY 1 STEP 2000 0 ; +ROW IO_CORNER_SOUTH_EAST IOSITE 5690000 30000 FN DO 140 BY 1 STEP 2000 0 ; +ROW IO_CORNER_SOUTH_WEST IOSITE 30000 30000 N DO 140 BY 1 STEP 2000 0 ; +ROW IO_NORTH IOSITE 310000 5690000 FS DO 2690 BY 1 STEP 2000 0 ; +ROW IO_EAST IOSITE 5690000 310000 W DO 1 BY 2690 STEP 0 2000 ; +ROW IO_SOUTH IOSITE 310000 30000 N DO 2690 BY 1 STEP 2000 0 ; +ROW IO_WEST IOSITE 30000 310000 FW DO 1 BY 2690 STEP 0 2000 ; +TRACKS X 190 DO 21428 STEP 280 LAYER metal1 ; +TRACKS Y 140 DO 21428 STEP 280 LAYER metal1 ; +TRACKS X 190 DO 15789 STEP 380 LAYER metal2 ; +TRACKS Y 140 DO 15789 STEP 380 LAYER metal2 ; +TRACKS X 190 DO 21428 STEP 280 LAYER metal3 ; +TRACKS Y 140 DO 21428 STEP 280 LAYER metal3 ; +TRACKS X 190 DO 10714 STEP 560 LAYER metal4 ; +TRACKS Y 140 DO 10714 STEP 560 LAYER metal4 ; +TRACKS X 190 DO 10714 STEP 560 LAYER metal5 ; +TRACKS Y 140 DO 10714 STEP 560 LAYER metal5 ; +TRACKS X 190 DO 10714 STEP 560 LAYER metal6 ; +TRACKS Y 140 DO 10714 STEP 560 LAYER metal6 ; +TRACKS X 1790 DO 3749 STEP 1600 LAYER metal7 ; +TRACKS Y 1740 DO 3749 STEP 1600 LAYER metal7 ; +TRACKS X 1790 DO 3749 STEP 1600 LAYER metal8 ; +TRACKS Y 1740 DO 3749 STEP 1600 LAYER metal8 ; +TRACKS X 3390 DO 1874 STEP 3200 LAYER metal9 ; +TRACKS Y 3340 DO 1874 STEP 3200 LAYER metal9 ; +TRACKS X 3390 DO 1874 STEP 3200 LAYER metal10 ; +TRACKS Y 3340 DO 1874 STEP 3200 LAYER metal10 ; +COMPONENTS 294 ; + - BUMP_0_0 DUMMY_BUMP + FIXED ( 200000 1000000 ) N ; + - BUMP_0_1 DUMMY_BUMP + FIXED ( 200000 1110000 ) N ; + - BUMP_0_2 DUMMY_BUMP + FIXED ( 200000 1220000 ) N ; + - BUMP_0_3 DUMMY_BUMP + FIXED ( 200000 1330000 ) N ; + - BUMP_0_4 DUMMY_BUMP + FIXED ( 200000 1440000 ) N ; + - BUMP_1_0 DUMMY_BUMP + FIXED ( 310000 1000000 ) N ; + - BUMP_1_1 DUMMY_BUMP + FIXED ( 310000 1110000 ) N ; + - BUMP_1_2 DUMMY_BUMP + FIXED ( 310000 1220000 ) N ; + - BUMP_1_3 DUMMY_BUMP + FIXED ( 310000 1330000 ) N ; + - BUMP_1_4 DUMMY_BUMP + FIXED ( 310000 1440000 ) N ; + - BUMP_2_0 DUMMY_BUMP + FIXED ( 420000 1000000 ) N ; + - BUMP_2_1 DUMMY_BUMP + FIXED ( 420000 1110000 ) N ; + - BUMP_2_2 DUMMY_BUMP + FIXED ( 420000 1220000 ) N ; + - BUMP_2_3 DUMMY_BUMP + FIXED ( 420000 1330000 ) N ; + - BUMP_2_4 DUMMY_BUMP + FIXED ( 420000 1440000 ) N ; + - BUMP_3_0 DUMMY_BUMP + FIXED ( 530000 1000000 ) N ; + - BUMP_3_1 DUMMY_BUMP + FIXED ( 530000 1110000 ) N ; + - BUMP_3_2 DUMMY_BUMP + FIXED ( 530000 1220000 ) N ; + - BUMP_3_3 DUMMY_BUMP + FIXED ( 530000 1330000 ) N ; + - BUMP_3_4 DUMMY_BUMP + FIXED ( 530000 1440000 ) N ; + - BUMP_4_0 DUMMY_BUMP + FIXED ( 640000 1000000 ) N ; + - BUMP_4_1 DUMMY_BUMP + FIXED ( 640000 1110000 ) N ; + - BUMP_4_2 DUMMY_BUMP + FIXED ( 640000 1220000 ) N ; + - BUMP_4_3 DUMMY_BUMP + FIXED ( 640000 1330000 ) N ; + - BUMP_4_4 DUMMY_BUMP + FIXED ( 640000 1440000 ) N ; + - IO_EAST_SIDE PADCELL_SIG_V + FIXED ( 5690000 1000000 ) W ; + - IO_WEST_SIDE PADCELL_SIG_V + FIXED ( 30000 1000000 ) FW ; + - u_bsg_tag_clk_i PADCELL_SIG_H ; + - u_bsg_tag_clk_o PADCELL_SIG_H ; + - u_bsg_tag_data_i PADCELL_SIG_H ; + - u_bsg_tag_data_o PADCELL_SIG_H ; + - u_bsg_tag_en_i PADCELL_SIG_H ; + - u_ci2_0_o PADCELL_SIG_V ; + - u_ci2_1_o PADCELL_SIG_V ; + - u_ci2_2_o PADCELL_SIG_V ; + - u_ci2_3_o PADCELL_SIG_V ; + - u_ci2_4_o PADCELL_SIG_V ; + - u_ci2_5_o PADCELL_SIG_V ; + - u_ci2_6_o PADCELL_SIG_V ; + - u_ci2_7_o PADCELL_SIG_V ; + - u_ci2_8_o PADCELL_SIG_V ; + - u_ci2_clk_o PADCELL_SIG_V ; + - u_ci2_tkn_i PADCELL_SIG_V ; + - u_ci2_v_o PADCELL_SIG_V ; + - u_ci_0_i PADCELL_SIG_H ; + - u_ci_1_i PADCELL_SIG_H ; + - u_ci_2_i PADCELL_SIG_H ; + - u_ci_3_i PADCELL_SIG_H ; + - u_ci_4_i PADCELL_SIG_H ; + - u_ci_5_i PADCELL_SIG_H ; + - u_ci_6_i PADCELL_SIG_H ; + - u_ci_7_i PADCELL_SIG_H ; + - u_ci_8_i PADCELL_SIG_H ; + - u_ci_clk_i PADCELL_SIG_H ; + - u_ci_tkn_o PADCELL_SIG_H ; + - u_ci_v_i PADCELL_SIG_H ; + - u_clk_A_i PADCELL_SIG_V ; + - u_clk_B_i PADCELL_SIG_V ; + - u_clk_C_i PADCELL_SIG_V ; + - u_clk_async_reset_i PADCELL_SIG_V ; + - u_clk_o PADCELL_SIG_V ; + - u_co2_0_o PADCELL_SIG_H ; + - u_co2_1_o PADCELL_SIG_H ; + - u_co2_2_o PADCELL_SIG_H ; + - u_co2_3_o PADCELL_SIG_H ; + - u_co2_4_o PADCELL_SIG_H ; + - u_co2_5_o PADCELL_SIG_H ; + - u_co2_6_o PADCELL_SIG_H ; + - u_co2_7_o PADCELL_SIG_H ; + - u_co2_8_o PADCELL_SIG_H ; + - u_co2_clk_o PADCELL_SIG_H ; + - u_co2_tkn_i PADCELL_SIG_H ; + - u_co2_v_o PADCELL_SIG_H ; + - u_co_0_i PADCELL_SIG_V ; + - u_co_1_i PADCELL_SIG_V ; + - u_co_2_i PADCELL_SIG_V ; + - u_co_3_i PADCELL_SIG_V ; + - u_co_4_i PADCELL_SIG_V ; + - u_co_5_i PADCELL_SIG_V ; + - u_co_6_i PADCELL_SIG_V ; + - u_co_7_i PADCELL_SIG_V ; + - u_co_8_i PADCELL_SIG_V ; + - u_co_clk_i PADCELL_SIG_V ; + - u_co_tkn_o PADCELL_SIG_V ; + - u_co_v_i PADCELL_SIG_V ; + - u_core_async_reset_i PADCELL_SIG_V ; + - u_ddr_addr_0_o PADCELL_SIG_V ; + - u_ddr_addr_10_o PADCELL_SIG_V ; + - u_ddr_addr_11_o PADCELL_SIG_V ; + - u_ddr_addr_12_o PADCELL_SIG_V ; + - u_ddr_addr_13_o PADCELL_SIG_V ; + - u_ddr_addr_14_o PADCELL_SIG_V ; + - u_ddr_addr_15_o PADCELL_SIG_V ; + - u_ddr_addr_1_o PADCELL_SIG_V ; + - u_ddr_addr_2_o PADCELL_SIG_V ; + - u_ddr_addr_3_o PADCELL_SIG_V ; + - u_ddr_addr_4_o PADCELL_SIG_V ; + - u_ddr_addr_5_o PADCELL_SIG_V ; + - u_ddr_addr_6_o PADCELL_SIG_V ; + - u_ddr_addr_7_o PADCELL_SIG_V ; + - u_ddr_addr_8_o PADCELL_SIG_V ; + - u_ddr_addr_9_o PADCELL_SIG_V ; + - u_ddr_ba_0_o PADCELL_SIG_V ; + - u_ddr_ba_1_o PADCELL_SIG_V ; + - u_ddr_ba_2_o PADCELL_SIG_V ; + - u_ddr_cas_n_o PADCELL_SIG_V ; + - u_ddr_ck_n_o PADCELL_SIG_V ; + - u_ddr_ck_p_o PADCELL_SIG_V ; + - u_ddr_cke_o PADCELL_SIG_V ; + - u_ddr_cs_n_o PADCELL_SIG_V ; + - u_ddr_dm_0_o PADCELL_SIG_H ; + - u_ddr_dm_1_o PADCELL_SIG_V ; + - u_ddr_dm_2_o PADCELL_SIG_V ; + - u_ddr_dm_3_o PADCELL_SIG_H ; + - u_ddr_dq_0_io PADCELL_SIG_H ; + - u_ddr_dq_10_io PADCELL_SIG_H ; + - u_ddr_dq_11_io PADCELL_SIG_H ; + - u_ddr_dq_12_io PADCELL_SIG_H ; + - u_ddr_dq_13_io PADCELL_SIG_H ; + - u_ddr_dq_14_io PADCELL_SIG_H ; + - u_ddr_dq_15_io PADCELL_SIG_H ; + - u_ddr_dq_16_io PADCELL_SIG_H ; + - u_ddr_dq_17_io PADCELL_SIG_H ; + - u_ddr_dq_18_io PADCELL_SIG_H ; + - u_ddr_dq_19_io PADCELL_SIG_H ; + - u_ddr_dq_1_io PADCELL_SIG_H ; + - u_ddr_dq_20_io PADCELL_SIG_H ; + - u_ddr_dq_21_io PADCELL_SIG_H ; + - u_ddr_dq_22_io PADCELL_SIG_H ; + - u_ddr_dq_23_io PADCELL_SIG_H ; + - u_ddr_dq_24_io PADCELL_SIG_H ; + - u_ddr_dq_25_io PADCELL_SIG_H ; + - u_ddr_dq_26_io PADCELL_SIG_H ; + - u_ddr_dq_27_io PADCELL_SIG_H ; + - u_ddr_dq_28_io PADCELL_SIG_H ; + - u_ddr_dq_29_io PADCELL_SIG_H ; + - u_ddr_dq_2_io PADCELL_SIG_H ; + - u_ddr_dq_30_io PADCELL_SIG_H ; + - u_ddr_dq_31_io PADCELL_SIG_H ; + - u_ddr_dq_3_io PADCELL_SIG_H ; + - u_ddr_dq_4_io PADCELL_SIG_H ; + - u_ddr_dq_5_io PADCELL_SIG_H ; + - u_ddr_dq_6_io PADCELL_SIG_H ; + - u_ddr_dq_7_io PADCELL_SIG_H ; + - u_ddr_dq_8_io PADCELL_SIG_H ; + - u_ddr_dq_9_io PADCELL_SIG_H ; + - u_ddr_dqs_n_0_io PADCELL_SIG_H ; + - u_ddr_dqs_n_1_io PADCELL_SIG_V ; + - u_ddr_dqs_n_2_io PADCELL_SIG_V ; + - u_ddr_dqs_n_3_io PADCELL_SIG_H ; + - u_ddr_dqs_p_0_io PADCELL_SIG_H ; + - u_ddr_dqs_p_1_io PADCELL_SIG_V ; + - u_ddr_dqs_p_2_io PADCELL_SIG_V ; + - u_ddr_dqs_p_3_io PADCELL_SIG_H ; + - u_ddr_odt_o PADCELL_SIG_V ; + - u_ddr_ras_n_o PADCELL_SIG_V ; + - u_ddr_reset_n_o PADCELL_SIG_V ; + - u_ddr_we_n_o PADCELL_SIG_V ; + - u_misc_o PADCELL_SIG_V ; + - u_sel_0_i PADCELL_SIG_V ; + - u_sel_1_i PADCELL_SIG_V ; + - u_sel_2_i PADCELL_SIG_V ; + - u_v18_1 PADCELL_VDDIO_V ; + - u_v18_10 PADCELL_VDDIO_H ; + - u_v18_11 PADCELL_VDDIO_H ; + - u_v18_12 PADCELL_VDDIO_H ; + - u_v18_13 PADCELL_VDDIO_H ; + - u_v18_14 PADCELL_VDDIO_H ; + - u_v18_15 PADCELL_VDDIO_H ; + - u_v18_16 PADCELL_VDDIO_H ; + - u_v18_17 PADCELL_VDDIO_V ; + - u_v18_18 PADCELL_VDDIO_V ; + - u_v18_19 PADCELL_VDDIO_V ; + - u_v18_2 PADCELL_VDDIO_V ; + - u_v18_20 PADCELL_VDDIO_V ; + - u_v18_21 PADCELL_VDDIO_V ; + - u_v18_22 PADCELL_VDDIO_V ; + - u_v18_23 PADCELL_VDDIO_V ; + - u_v18_24 PADCELL_VDDIO_V ; + - u_v18_25 PADCELL_VDDIO_H ; + - u_v18_26 PADCELL_VDDIO_H ; + - u_v18_27 PADCELL_VDDIO_H ; + - u_v18_28 PADCELL_VDDIO_H ; + - u_v18_29 PADCELL_VDDIO_H ; + - u_v18_3 PADCELL_VDDIO_V ; + - u_v18_30 PADCELL_VDDIO_H ; + - u_v18_31 PADCELL_VDDIO_H ; + - u_v18_32 PADCELL_VDDIO_H ; + - u_v18_4 PADCELL_VDDIO_V ; + - u_v18_5 PADCELL_VDDIO_V ; + - u_v18_6 PADCELL_VDDIO_V ; + - u_v18_7 PADCELL_VDDIO_V ; + - u_v18_8 PADCELL_VDDIO_V ; + - u_v18_9 PADCELL_VDDIO_H ; + - u_vdd_1 PADCELL_VDD_V ; + - u_vdd_10 PADCELL_VDD_H ; + - u_vdd_11 PADCELL_VDD_H ; + - u_vdd_12 PADCELL_VDD_H ; + - u_vdd_13 PADCELL_VDD_H ; + - u_vdd_14 PADCELL_VDD_H ; + - u_vdd_15 PADCELL_VDD_H ; + - u_vdd_16 PADCELL_VDD_H ; + - u_vdd_17 PADCELL_VDD_V ; + - u_vdd_18 PADCELL_VDD_V ; + - u_vdd_19 PADCELL_VDD_V ; + - u_vdd_2 PADCELL_VDD_V ; + - u_vdd_20 PADCELL_VDD_V ; + - u_vdd_21 PADCELL_VDD_V ; + - u_vdd_22 PADCELL_VDD_V ; + - u_vdd_23 PADCELL_VDD_V ; + - u_vdd_24 PADCELL_VDD_V ; + - u_vdd_25 PADCELL_VDD_H ; + - u_vdd_26 PADCELL_VDD_H ; + - u_vdd_27 PADCELL_VDD_H ; + - u_vdd_28 PADCELL_VDD_H ; + - u_vdd_29 PADCELL_VDD_H ; + - u_vdd_3 PADCELL_VDD_V ; + - u_vdd_30 PADCELL_VDD_H ; + - u_vdd_31 PADCELL_VDD_H ; + - u_vdd_32 PADCELL_VDD_H ; + - u_vdd_4 PADCELL_VDD_V ; + - u_vdd_5 PADCELL_VDD_V ; + - u_vdd_6 PADCELL_VDD_V ; + - u_vdd_7 PADCELL_VDD_V ; + - u_vdd_8 PADCELL_VDD_H ; + - u_vdd_9 PADCELL_VDD_H ; + - u_vdd_pll PADCELL_VDD_V ; + - u_vss_0 PADCELL_VSS_V ; + - u_vss_1 PADCELL_VSS_V ; + - u_vss_10 PADCELL_VSS_H ; + - u_vss_11 PADCELL_VSS_H ; + - u_vss_12 PADCELL_VSS_H ; + - u_vss_13 PADCELL_VSS_H ; + - u_vss_14 PADCELL_VSS_H ; + - u_vss_15 PADCELL_VSS_H ; + - u_vss_16 PADCELL_VSS_H ; + - u_vss_17 PADCELL_VSS_V ; + - u_vss_18 PADCELL_VSS_V ; + - u_vss_19 PADCELL_VSS_V ; + - u_vss_2 PADCELL_VSS_V ; + - u_vss_20 PADCELL_VSS_V ; + - u_vss_21 PADCELL_VSS_V ; + - u_vss_22 PADCELL_VSS_V ; + - u_vss_23 PADCELL_VSS_V ; + - u_vss_24 PADCELL_VSS_V ; + - u_vss_25 PADCELL_VSS_H ; + - u_vss_26 PADCELL_VSS_H ; + - u_vss_27 PADCELL_VSS_H ; + - u_vss_28 PADCELL_VSS_H ; + - u_vss_29 PADCELL_VSS_H ; + - u_vss_3 PADCELL_VSS_V ; + - u_vss_30 PADCELL_VSS_H ; + - u_vss_31 PADCELL_VSS_H ; + - u_vss_32 PADCELL_VSS_H ; + - u_vss_4 PADCELL_VSS_V ; + - u_vss_5 PADCELL_VSS_V ; + - u_vss_6 PADCELL_VSS_V ; + - u_vss_7 PADCELL_VSS_V ; + - u_vss_8 PADCELL_VSS_H ; + - u_vss_9 PADCELL_VSS_H ; + - u_vss_pll PADCELL_VSS_V ; + - u_vzz_0 PADCELL_VSSIO_V ; + - u_vzz_1 PADCELL_VSSIO_V ; + - u_vzz_10 PADCELL_VSSIO_H ; + - u_vzz_11 PADCELL_VSSIO_H ; + - u_vzz_12 PADCELL_VSSIO_H ; + - u_vzz_13 PADCELL_VSSIO_H ; + - u_vzz_14 PADCELL_VSSIO_H ; + - u_vzz_15 PADCELL_VSSIO_H ; + - u_vzz_16 PADCELL_VSSIO_H ; + - u_vzz_17 PADCELL_VSSIO_V ; + - u_vzz_18 PADCELL_VSSIO_V ; + - u_vzz_19 PADCELL_VSSIO_V ; + - u_vzz_2 PADCELL_VSSIO_V ; + - u_vzz_20 PADCELL_VSSIO_V ; + - u_vzz_21 PADCELL_VSSIO_V ; + - u_vzz_22 PADCELL_VSSIO_V ; + - u_vzz_23 PADCELL_VSSIO_V ; + - u_vzz_24 PADCELL_VSSIO_V ; + - u_vzz_25 PADCELL_VSSIO_H ; + - u_vzz_26 PADCELL_VSSIO_H ; + - u_vzz_27 PADCELL_VSSIO_H ; + - u_vzz_28 PADCELL_VSSIO_H ; + - u_vzz_29 PADCELL_VSSIO_H ; + - u_vzz_3 PADCELL_VSSIO_V ; + - u_vzz_30 PADCELL_VSSIO_H ; + - u_vzz_31 PADCELL_VSSIO_H ; + - u_vzz_32 PADCELL_VSSIO_H ; + - u_vzz_4 PADCELL_VSSIO_V ; + - u_vzz_5 PADCELL_VSSIO_V ; + - u_vzz_6 PADCELL_VSSIO_V ; + - u_vzz_7 PADCELL_VSSIO_V ; + - u_vzz_8 PADCELL_VSSIO_V ; + - u_vzz_9 PADCELL_VSSIO_H ; +END COMPONENTS +PINS 135 ; + - p_bsg_tag_clk_i + NET p_bsg_tag_clk_i + DIRECTION INPUT + USE SIGNAL ; + - p_bsg_tag_clk_o + NET p_bsg_tag_clk_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_bsg_tag_data_i + NET p_bsg_tag_data_i + DIRECTION INPUT + USE SIGNAL ; + - p_bsg_tag_data_o + NET p_bsg_tag_data_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_bsg_tag_en_i + NET p_bsg_tag_en_i + DIRECTION INPUT + USE SIGNAL ; + - p_ci2_0_o + NET p_ci2_0_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ci2_1_o + NET p_ci2_1_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ci2_2_o + NET p_ci2_2_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ci2_3_o + NET p_ci2_3_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ci2_4_o + NET p_ci2_4_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ci2_5_o + NET p_ci2_5_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ci2_6_o + NET p_ci2_6_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ci2_7_o + NET p_ci2_7_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ci2_8_o + NET p_ci2_8_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ci2_clk_o + NET p_ci2_clk_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ci2_tkn_i + NET p_ci2_tkn_i + DIRECTION INPUT + USE SIGNAL ; + - p_ci2_v_o + NET p_ci2_v_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ci_0_i + NET p_ci_0_i + DIRECTION INPUT + USE SIGNAL ; + - p_ci_1_i + NET p_ci_1_i + DIRECTION INPUT + USE SIGNAL ; + - p_ci_2_i + NET p_ci_2_i + DIRECTION INPUT + USE SIGNAL ; + - p_ci_3_i + NET p_ci_3_i + DIRECTION INPUT + USE SIGNAL ; + - p_ci_4_i + NET p_ci_4_i + DIRECTION INPUT + USE SIGNAL ; + - p_ci_5_i + NET p_ci_5_i + DIRECTION INPUT + USE SIGNAL ; + - p_ci_6_i + NET p_ci_6_i + DIRECTION INPUT + USE SIGNAL ; + - p_ci_7_i + NET p_ci_7_i + DIRECTION INPUT + USE SIGNAL ; + - p_ci_8_i + NET p_ci_8_i + DIRECTION INPUT + USE SIGNAL ; + - p_ci_clk_i + NET p_ci_clk_i + DIRECTION INPUT + USE SIGNAL ; + - p_ci_tkn_o + NET p_ci_tkn_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ci_v_i + NET p_ci_v_i + DIRECTION INPUT + USE SIGNAL ; + - p_clk_A_i + NET p_clk_A_i + DIRECTION INPUT + USE SIGNAL ; + - p_clk_B_i + NET p_clk_B_i + DIRECTION INPUT + USE SIGNAL ; + - p_clk_C_i + NET p_clk_C_i + DIRECTION INPUT + USE SIGNAL ; + - p_clk_async_reset_i + NET p_clk_async_reset_i + DIRECTION INPUT + USE SIGNAL ; + - p_clk_o + NET p_clk_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co2_0_o + NET p_co2_0_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co2_1_o + NET p_co2_1_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co2_2_o + NET p_co2_2_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co2_3_o + NET p_co2_3_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co2_4_o + NET p_co2_4_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co2_5_o + NET p_co2_5_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co2_6_o + NET p_co2_6_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co2_7_o + NET p_co2_7_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co2_8_o + NET p_co2_8_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co2_clk_o + NET p_co2_clk_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co2_tkn_i + NET p_co2_tkn_i + DIRECTION INPUT + USE SIGNAL ; + - p_co2_v_o + NET p_co2_v_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co_0_i + NET p_co_0_i + DIRECTION INPUT + USE SIGNAL ; + - p_co_1_i + NET p_co_1_i + DIRECTION INPUT + USE SIGNAL ; + - p_co_2_i + NET p_co_2_i + DIRECTION INPUT + USE SIGNAL ; + - p_co_3_i + NET p_co_3_i + DIRECTION INPUT + USE SIGNAL ; + - p_co_4_i + NET p_co_4_i + DIRECTION INPUT + USE SIGNAL ; + - p_co_5_i + NET p_co_5_i + DIRECTION INPUT + USE SIGNAL ; + - p_co_6_i + NET p_co_6_i + DIRECTION INPUT + USE SIGNAL ; + - p_co_7_i + NET p_co_7_i + DIRECTION INPUT + USE SIGNAL ; + - p_co_8_i + NET p_co_8_i + DIRECTION INPUT + USE SIGNAL ; + - p_co_clk_i + NET p_co_clk_i + DIRECTION INPUT + USE SIGNAL ; + - p_co_tkn_o + NET p_co_tkn_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co_v_i + NET p_co_v_i + DIRECTION INPUT + USE SIGNAL ; + - p_core_async_reset_i + NET p_core_async_reset_i + DIRECTION INPUT + USE SIGNAL ; + - p_ddr_addr_0_o + NET p_ddr_addr_0_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_10_o + NET p_ddr_addr_10_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_11_o + NET p_ddr_addr_11_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_12_o + NET p_ddr_addr_12_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_13_o + NET p_ddr_addr_13_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_14_o + NET p_ddr_addr_14_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_15_o + NET p_ddr_addr_15_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_1_o + NET p_ddr_addr_1_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_2_o + NET p_ddr_addr_2_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_3_o + NET p_ddr_addr_3_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_4_o + NET p_ddr_addr_4_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_5_o + NET p_ddr_addr_5_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_6_o + NET p_ddr_addr_6_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_7_o + NET p_ddr_addr_7_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_8_o + NET p_ddr_addr_8_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_9_o + NET p_ddr_addr_9_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_ba_0_o + NET p_ddr_ba_0_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_ba_1_o + NET p_ddr_ba_1_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_ba_2_o + NET p_ddr_ba_2_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_cas_n_o + NET p_ddr_cas_n_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_ck_n_o + NET p_ddr_ck_n_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_ck_p_o + NET p_ddr_ck_p_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_cke_o + NET p_ddr_cke_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_cs_n_o + NET p_ddr_cs_n_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_dm_0_o + NET p_ddr_dm_0_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_dm_1_o + NET p_ddr_dm_1_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_dm_2_o + NET p_ddr_dm_2_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_dm_3_o + NET p_ddr_dm_3_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_dq_0_io + NET p_ddr_dq_0_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_10_io + NET p_ddr_dq_10_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_11_io + NET p_ddr_dq_11_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_12_io + NET p_ddr_dq_12_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_13_io + NET p_ddr_dq_13_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_14_io + NET p_ddr_dq_14_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_15_io + NET p_ddr_dq_15_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_16_io + NET p_ddr_dq_16_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_17_io + NET p_ddr_dq_17_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_18_io + NET p_ddr_dq_18_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_19_io + NET p_ddr_dq_19_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_1_io + NET p_ddr_dq_1_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_20_io + NET p_ddr_dq_20_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_21_io + NET p_ddr_dq_21_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_22_io + NET p_ddr_dq_22_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_23_io + NET p_ddr_dq_23_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_24_io + NET p_ddr_dq_24_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_25_io + NET p_ddr_dq_25_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_26_io + NET p_ddr_dq_26_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_27_io + NET p_ddr_dq_27_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_28_io + NET p_ddr_dq_28_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_29_io + NET p_ddr_dq_29_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_2_io + NET p_ddr_dq_2_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_30_io + NET p_ddr_dq_30_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_31_io + NET p_ddr_dq_31_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_3_io + NET p_ddr_dq_3_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_4_io + NET p_ddr_dq_4_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_5_io + NET p_ddr_dq_5_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_6_io + NET p_ddr_dq_6_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_7_io + NET p_ddr_dq_7_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_8_io + NET p_ddr_dq_8_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_9_io + NET p_ddr_dq_9_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dqs_n_0_io + NET p_ddr_dqs_n_0_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dqs_n_1_io + NET p_ddr_dqs_n_1_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dqs_n_2_io + NET p_ddr_dqs_n_2_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dqs_n_3_io + NET p_ddr_dqs_n_3_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dqs_p_0_io + NET p_ddr_dqs_p_0_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dqs_p_1_io + NET p_ddr_dqs_p_1_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dqs_p_2_io + NET p_ddr_dqs_p_2_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dqs_p_3_io + NET p_ddr_dqs_p_3_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_odt_o + NET p_ddr_odt_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_ras_n_o + NET p_ddr_ras_n_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_reset_n_o + NET p_ddr_reset_n_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_we_n_o + NET p_ddr_we_n_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_misc_o + NET p_misc_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_sel_0_i + NET p_sel_0_i + DIRECTION INPUT + USE SIGNAL ; + - p_sel_1_i + NET p_sel_1_i + DIRECTION INPUT + USE SIGNAL ; + - p_sel_2_i + NET p_sel_2_i + DIRECTION INPUT + USE SIGNAL ; +END PINS +NETS 350 ; + - core_bsg_tag_clk_i ( u_bsg_tag_clk_i Y ) + USE SIGNAL ; + - core_bsg_tag_clk_o ( u_bsg_tag_clk_o A ) + USE SIGNAL ; + - core_bsg_tag_data_i ( u_bsg_tag_data_i Y ) + USE SIGNAL ; + - core_bsg_tag_data_o ( u_bsg_tag_data_o A ) + USE SIGNAL ; + - core_bsg_tag_en_i ( u_bsg_tag_en_i Y ) + USE SIGNAL ; + - core_ci2_0_o ( u_ci2_0_o A ) + USE SIGNAL ; + - core_ci2_1_o ( u_ci2_1_o A ) + USE SIGNAL ; + - core_ci2_2_o ( u_ci2_2_o A ) + USE SIGNAL ; + - core_ci2_3_o ( u_ci2_3_o A ) + USE SIGNAL ; + - core_ci2_4_o ( u_ci2_4_o A ) + USE SIGNAL ; + - core_ci2_5_o ( u_ci2_5_o A ) + USE SIGNAL ; + - core_ci2_6_o ( u_ci2_6_o A ) + USE SIGNAL ; + - core_ci2_7_o ( u_ci2_7_o A ) + USE SIGNAL ; + - core_ci2_8_o ( u_ci2_8_o A ) + USE SIGNAL ; + - core_ci2_clk_o ( u_ci2_clk_o A ) + USE SIGNAL ; + - core_ci2_tkn_i ( u_ci2_tkn_i Y ) + USE SIGNAL ; + - core_ci2_v_o ( u_ci2_v_o A ) + USE SIGNAL ; + - core_ci_0_i ( u_ci_0_i Y ) + USE SIGNAL ; + - core_ci_1_i ( u_ci_1_i Y ) + USE SIGNAL ; + - core_ci_2_i ( u_ci_2_i Y ) + USE SIGNAL ; + - core_ci_3_i ( u_ci_3_i Y ) + USE SIGNAL ; + - core_ci_4_i ( u_ci_4_i Y ) + USE SIGNAL ; + - core_ci_5_i ( u_ci_5_i Y ) + USE SIGNAL ; + - core_ci_6_i ( u_ci_6_i Y ) + USE SIGNAL ; + - core_ci_7_i ( u_ci_7_i Y ) + USE SIGNAL ; + - core_ci_8_i ( u_ci_8_i Y ) + USE SIGNAL ; + - core_ci_clk_i ( u_ci_clk_i Y ) + USE SIGNAL ; + - core_ci_tkn_o ( u_ci_tkn_o A ) + USE SIGNAL ; + - core_ci_v_i ( u_ci_v_i Y ) + USE SIGNAL ; + - core_clk_A_i ( u_clk_A_i Y ) + USE SIGNAL ; + - core_clk_B_i ( u_clk_B_i Y ) + USE SIGNAL ; + - core_clk_C_i ( u_clk_C_i Y ) + USE SIGNAL ; + - core_clk_async_reset_i ( u_clk_async_reset_i Y ) + USE SIGNAL ; + - core_clk_o ( u_clk_o A ) + USE SIGNAL ; + - core_co2_0_o ( u_co2_0_o A ) + USE SIGNAL ; + - core_co2_1_o ( u_co2_1_o A ) + USE SIGNAL ; + - core_co2_2_o ( u_co2_2_o A ) + USE SIGNAL ; + - core_co2_3_o ( u_co2_3_o A ) + USE SIGNAL ; + - core_co2_4_o ( u_co2_4_o A ) + USE SIGNAL ; + - core_co2_5_o ( u_co2_5_o A ) + USE SIGNAL ; + - core_co2_6_o ( u_co2_6_o A ) + USE SIGNAL ; + - core_co2_7_o ( u_co2_7_o A ) + USE SIGNAL ; + - core_co2_8_o ( u_co2_8_o A ) + USE SIGNAL ; + - core_co2_clk_o ( u_co2_clk_o A ) + USE SIGNAL ; + - core_co2_tkn_i ( u_co2_tkn_i Y ) + USE SIGNAL ; + - core_co2_v_o ( u_co2_v_o A ) + USE SIGNAL ; + - core_co_0_i ( u_co_0_i Y ) + USE SIGNAL ; + - core_co_1_i ( u_co_1_i Y ) + USE SIGNAL ; + - core_co_2_i ( u_co_2_i Y ) + USE SIGNAL ; + - core_co_3_i ( u_co_3_i Y ) + USE SIGNAL ; + - core_co_4_i ( u_co_4_i Y ) + USE SIGNAL ; + - core_co_5_i ( u_co_5_i Y ) + USE SIGNAL ; + - core_co_6_i ( u_co_6_i Y ) + USE SIGNAL ; + - core_co_7_i ( u_co_7_i Y ) + USE SIGNAL ; + - core_co_8_i ( u_co_8_i Y ) + USE SIGNAL ; + - core_co_clk_i ( u_co_clk_i Y ) + USE SIGNAL ; + - core_co_tkn_o ( u_co_tkn_o A ) + USE SIGNAL ; + - core_co_v_i ( u_co_v_i Y ) + USE SIGNAL ; + - core_core_async_reset_i ( u_core_async_reset_i Y ) + USE SIGNAL ; + - core_ddr_addr_0_o ( u_ddr_addr_0_o A ) + USE SIGNAL ; + - core_ddr_addr_10_o ( u_ddr_addr_10_o A ) + USE SIGNAL ; + - core_ddr_addr_11_o ( u_ddr_addr_11_o A ) + USE SIGNAL ; + - core_ddr_addr_12_o ( u_ddr_addr_12_o A ) + USE SIGNAL ; + - core_ddr_addr_13_o ( u_ddr_addr_13_o A ) + USE SIGNAL ; + - core_ddr_addr_14_o ( u_ddr_addr_14_o A ) + USE SIGNAL ; + - core_ddr_addr_15_o ( u_ddr_addr_15_o A ) + USE SIGNAL ; + - core_ddr_addr_1_o ( u_ddr_addr_1_o A ) + USE SIGNAL ; + - core_ddr_addr_2_o ( u_ddr_addr_2_o A ) + USE SIGNAL ; + - core_ddr_addr_3_o ( u_ddr_addr_3_o A ) + USE SIGNAL ; + - core_ddr_addr_4_o ( u_ddr_addr_4_o A ) + USE SIGNAL ; + - core_ddr_addr_5_o ( u_ddr_addr_5_o A ) + USE SIGNAL ; + - core_ddr_addr_6_o ( u_ddr_addr_6_o A ) + USE SIGNAL ; + - core_ddr_addr_7_o ( u_ddr_addr_7_o A ) + USE SIGNAL ; + - core_ddr_addr_8_o ( u_ddr_addr_8_o A ) + USE SIGNAL ; + - core_ddr_addr_9_o ( u_ddr_addr_9_o A ) + USE SIGNAL ; + - core_ddr_ba_0_o ( u_ddr_ba_0_o A ) + USE SIGNAL ; + - core_ddr_ba_1_o ( u_ddr_ba_1_o A ) + USE SIGNAL ; + - core_ddr_ba_2_o ( u_ddr_ba_2_o A ) + USE SIGNAL ; + - core_ddr_cas_n_o ( u_ddr_cas_n_o A ) + USE SIGNAL ; + - core_ddr_ck_n_o ( u_ddr_ck_n_o A ) + USE SIGNAL ; + - core_ddr_ck_p_o ( u_ddr_ck_p_o A ) + USE SIGNAL ; + - core_ddr_cke_o ( u_ddr_cke_o A ) + USE SIGNAL ; + - core_ddr_cs_n_o ( u_ddr_cs_n_o A ) + USE SIGNAL ; + - core_ddr_dm_0_o ( u_ddr_dm_0_o A ) + USE SIGNAL ; + - core_ddr_dm_1_o ( u_ddr_dm_1_o A ) + USE SIGNAL ; + - core_ddr_dm_2_o ( u_ddr_dm_2_o A ) + USE SIGNAL ; + - core_ddr_dm_3_o ( u_ddr_dm_3_o A ) + USE SIGNAL ; + - core_ddr_dq_0_i ( u_ddr_dq_0_io Y ) + USE SIGNAL ; + - core_ddr_dq_0_o ( u_ddr_dq_0_io A ) + USE SIGNAL ; + - core_ddr_dq_0_sel ( u_ddr_dq_0_io PU ) ( u_ddr_dq_0_io OE ) + USE SIGNAL ; + - core_ddr_dq_10_i ( u_ddr_dq_10_io Y ) + USE SIGNAL ; + - core_ddr_dq_10_o ( u_ddr_dq_10_io A ) + USE SIGNAL ; + - core_ddr_dq_10_sel ( u_ddr_dq_10_io PU ) ( u_ddr_dq_10_io OE ) + USE SIGNAL ; + - core_ddr_dq_11_i ( u_ddr_dq_11_io Y ) + USE SIGNAL ; + - core_ddr_dq_11_o ( u_ddr_dq_11_io A ) + USE SIGNAL ; + - core_ddr_dq_11_sel ( u_ddr_dq_11_io PU ) ( u_ddr_dq_11_io OE ) + USE SIGNAL ; + - core_ddr_dq_12_i ( u_ddr_dq_12_io Y ) + USE SIGNAL ; + - core_ddr_dq_12_o ( u_ddr_dq_12_io A ) + USE SIGNAL ; + - core_ddr_dq_12_sel ( u_ddr_dq_12_io PU ) ( u_ddr_dq_12_io OE ) + USE SIGNAL ; + - core_ddr_dq_13_i ( u_ddr_dq_13_io Y ) + USE SIGNAL ; + - core_ddr_dq_13_o ( u_ddr_dq_13_io A ) + USE SIGNAL ; + - core_ddr_dq_13_sel ( u_ddr_dq_13_io PU ) ( u_ddr_dq_13_io OE ) + USE SIGNAL ; + - core_ddr_dq_14_i ( u_ddr_dq_14_io Y ) + USE SIGNAL ; + - core_ddr_dq_14_o ( u_ddr_dq_14_io A ) + USE SIGNAL ; + - core_ddr_dq_14_sel ( u_ddr_dq_14_io PU ) ( u_ddr_dq_14_io OE ) + USE SIGNAL ; + - core_ddr_dq_15_i ( u_ddr_dq_15_io Y ) + USE SIGNAL ; + - core_ddr_dq_15_o ( u_ddr_dq_15_io A ) + USE SIGNAL ; + - core_ddr_dq_15_sel ( u_ddr_dq_15_io PU ) ( u_ddr_dq_15_io OE ) + USE SIGNAL ; + - core_ddr_dq_16_i ( u_ddr_dq_16_io Y ) + USE SIGNAL ; + - core_ddr_dq_16_o ( u_ddr_dq_16_io A ) + USE SIGNAL ; + - core_ddr_dq_16_sel ( u_ddr_dq_16_io PU ) ( u_ddr_dq_16_io OE ) + USE SIGNAL ; + - core_ddr_dq_17_i ( u_ddr_dq_17_io Y ) + USE SIGNAL ; + - core_ddr_dq_17_o ( u_ddr_dq_17_io A ) + USE SIGNAL ; + - core_ddr_dq_17_sel ( u_ddr_dq_17_io PU ) ( u_ddr_dq_17_io OE ) + USE SIGNAL ; + - core_ddr_dq_18_i ( u_ddr_dq_18_io Y ) + USE SIGNAL ; + - core_ddr_dq_18_o ( u_ddr_dq_18_io A ) + USE SIGNAL ; + - core_ddr_dq_18_sel ( u_ddr_dq_18_io PU ) ( u_ddr_dq_18_io OE ) + USE SIGNAL ; + - core_ddr_dq_19_i ( u_ddr_dq_19_io Y ) + USE SIGNAL ; + - core_ddr_dq_19_o ( u_ddr_dq_19_io A ) + USE SIGNAL ; + - core_ddr_dq_19_sel ( u_ddr_dq_19_io PU ) ( u_ddr_dq_19_io OE ) + USE SIGNAL ; + - core_ddr_dq_1_i ( u_ddr_dq_1_io Y ) + USE SIGNAL ; + - core_ddr_dq_1_o ( u_ddr_dq_1_io A ) + USE SIGNAL ; + - core_ddr_dq_1_sel ( u_ddr_dq_1_io PU ) ( u_ddr_dq_1_io OE ) + USE SIGNAL ; + - core_ddr_dq_20_i ( u_ddr_dq_20_io Y ) + USE SIGNAL ; + - core_ddr_dq_20_o ( u_ddr_dq_20_io A ) + USE SIGNAL ; + - core_ddr_dq_20_sel ( u_ddr_dq_20_io PU ) ( u_ddr_dq_20_io OE ) + USE SIGNAL ; + - core_ddr_dq_21_i ( u_ddr_dq_21_io Y ) + USE SIGNAL ; + - core_ddr_dq_21_o ( u_ddr_dq_21_io A ) + USE SIGNAL ; + - core_ddr_dq_21_sel ( u_ddr_dq_21_io PU ) ( u_ddr_dq_21_io OE ) + USE SIGNAL ; + - core_ddr_dq_22_i ( u_ddr_dq_22_io Y ) + USE SIGNAL ; + - core_ddr_dq_22_o ( u_ddr_dq_22_io A ) + USE SIGNAL ; + - core_ddr_dq_22_sel ( u_ddr_dq_22_io PU ) ( u_ddr_dq_22_io OE ) + USE SIGNAL ; + - core_ddr_dq_23_i ( u_ddr_dq_23_io Y ) + USE SIGNAL ; + - core_ddr_dq_23_o ( u_ddr_dq_23_io A ) + USE SIGNAL ; + - core_ddr_dq_23_sel ( u_ddr_dq_23_io PU ) ( u_ddr_dq_23_io OE ) + USE SIGNAL ; + - core_ddr_dq_24_i ( u_ddr_dq_24_io Y ) + USE SIGNAL ; + - core_ddr_dq_24_o ( u_ddr_dq_24_io A ) + USE SIGNAL ; + - core_ddr_dq_24_sel ( u_ddr_dq_24_io PU ) ( u_ddr_dq_24_io OE ) + USE SIGNAL ; + - core_ddr_dq_25_i ( u_ddr_dq_25_io Y ) + USE SIGNAL ; + - core_ddr_dq_25_o ( u_ddr_dq_25_io A ) + USE SIGNAL ; + - core_ddr_dq_25_sel ( u_ddr_dq_25_io PU ) ( u_ddr_dq_25_io OE ) + USE SIGNAL ; + - core_ddr_dq_26_i ( u_ddr_dq_26_io Y ) + USE SIGNAL ; + - core_ddr_dq_26_o ( u_ddr_dq_26_io A ) + USE SIGNAL ; + - core_ddr_dq_26_sel ( u_ddr_dq_26_io PU ) ( u_ddr_dq_26_io OE ) + USE SIGNAL ; + - core_ddr_dq_27_i ( u_ddr_dq_27_io Y ) + USE SIGNAL ; + - core_ddr_dq_27_o ( u_ddr_dq_27_io A ) + USE SIGNAL ; + - core_ddr_dq_27_sel ( u_ddr_dq_27_io PU ) ( u_ddr_dq_27_io OE ) + USE SIGNAL ; + - core_ddr_dq_28_i ( u_ddr_dq_28_io Y ) + USE SIGNAL ; + - core_ddr_dq_28_o ( u_ddr_dq_28_io A ) + USE SIGNAL ; + - core_ddr_dq_28_sel ( u_ddr_dq_28_io PU ) ( u_ddr_dq_28_io OE ) + USE SIGNAL ; + - core_ddr_dq_29_i ( u_ddr_dq_29_io Y ) + USE SIGNAL ; + - core_ddr_dq_29_o ( u_ddr_dq_29_io A ) + USE SIGNAL ; + - core_ddr_dq_29_sel ( u_ddr_dq_29_io PU ) ( u_ddr_dq_29_io OE ) + USE SIGNAL ; + - core_ddr_dq_2_i ( u_ddr_dq_2_io Y ) + USE SIGNAL ; + - core_ddr_dq_2_o ( u_ddr_dq_2_io A ) + USE SIGNAL ; + - core_ddr_dq_2_sel ( u_ddr_dq_2_io PU ) ( u_ddr_dq_2_io OE ) + USE SIGNAL ; + - core_ddr_dq_30_i ( u_ddr_dq_30_io Y ) + USE SIGNAL ; + - core_ddr_dq_30_o ( u_ddr_dq_30_io A ) + USE SIGNAL ; + - core_ddr_dq_30_sel ( u_ddr_dq_30_io PU ) ( u_ddr_dq_30_io OE ) + USE SIGNAL ; + - core_ddr_dq_31_i ( u_ddr_dq_31_io Y ) + USE SIGNAL ; + - core_ddr_dq_31_o ( u_ddr_dq_31_io A ) + USE SIGNAL ; + - core_ddr_dq_31_sel ( u_ddr_dq_31_io PU ) ( u_ddr_dq_31_io OE ) + USE SIGNAL ; + - core_ddr_dq_3_i ( u_ddr_dq_3_io Y ) + USE SIGNAL ; + - core_ddr_dq_3_o ( u_ddr_dq_3_io A ) + USE SIGNAL ; + - core_ddr_dq_3_sel ( u_ddr_dq_3_io PU ) ( u_ddr_dq_3_io OE ) + USE SIGNAL ; + - core_ddr_dq_4_i ( u_ddr_dq_4_io Y ) + USE SIGNAL ; + - core_ddr_dq_4_o ( u_ddr_dq_4_io A ) + USE SIGNAL ; + - core_ddr_dq_4_sel ( u_ddr_dq_4_io PU ) ( u_ddr_dq_4_io OE ) + USE SIGNAL ; + - core_ddr_dq_5_i ( u_ddr_dq_5_io Y ) + USE SIGNAL ; + - core_ddr_dq_5_o ( u_ddr_dq_5_io A ) + USE SIGNAL ; + - core_ddr_dq_5_sel ( u_ddr_dq_5_io PU ) ( u_ddr_dq_5_io OE ) + USE SIGNAL ; + - core_ddr_dq_6_i ( u_ddr_dq_6_io Y ) + USE SIGNAL ; + - core_ddr_dq_6_o ( u_ddr_dq_6_io A ) + USE SIGNAL ; + - core_ddr_dq_6_sel ( u_ddr_dq_6_io PU ) ( u_ddr_dq_6_io OE ) + USE SIGNAL ; + - core_ddr_dq_7_i ( u_ddr_dq_7_io Y ) + USE SIGNAL ; + - core_ddr_dq_7_o ( u_ddr_dq_7_io A ) + USE SIGNAL ; + - core_ddr_dq_7_sel ( u_ddr_dq_7_io PU ) ( u_ddr_dq_7_io OE ) + USE SIGNAL ; + - core_ddr_dq_8_i ( u_ddr_dq_8_io Y ) + USE SIGNAL ; + - core_ddr_dq_8_o ( u_ddr_dq_8_io A ) + USE SIGNAL ; + - core_ddr_dq_8_sel ( u_ddr_dq_8_io PU ) ( u_ddr_dq_8_io OE ) + USE SIGNAL ; + - core_ddr_dq_9_i ( u_ddr_dq_9_io Y ) + USE SIGNAL ; + - core_ddr_dq_9_o ( u_ddr_dq_9_io A ) + USE SIGNAL ; + - core_ddr_dq_9_sel ( u_ddr_dq_9_io PU ) ( u_ddr_dq_9_io OE ) + USE SIGNAL ; + - core_ddr_dqs_n_0_i ( u_ddr_dqs_n_0_io Y ) + USE SIGNAL ; + - core_ddr_dqs_n_0_o ( u_ddr_dqs_n_0_io A ) + USE SIGNAL ; + - core_ddr_dqs_n_0_sel ( u_ddr_dqs_n_0_io PU ) ( u_ddr_dqs_n_0_io OE ) + USE SIGNAL ; + - core_ddr_dqs_n_1_i ( u_ddr_dqs_n_1_io Y ) + USE SIGNAL ; + - core_ddr_dqs_n_1_o ( u_ddr_dqs_n_1_io A ) + USE SIGNAL ; + - core_ddr_dqs_n_1_sel ( u_ddr_dqs_n_1_io PU ) ( u_ddr_dqs_n_1_io OE ) + USE SIGNAL ; + - core_ddr_dqs_n_2_i ( u_ddr_dqs_n_2_io Y ) + USE SIGNAL ; + - core_ddr_dqs_n_2_o ( u_ddr_dqs_n_2_io A ) + USE SIGNAL ; + - core_ddr_dqs_n_2_sel ( u_ddr_dqs_n_2_io PU ) ( u_ddr_dqs_n_2_io OE ) + USE SIGNAL ; + - core_ddr_dqs_n_3_i ( u_ddr_dqs_n_3_io Y ) + USE SIGNAL ; + - core_ddr_dqs_n_3_o ( u_ddr_dqs_n_3_io A ) + USE SIGNAL ; + - core_ddr_dqs_n_3_sel ( u_ddr_dqs_n_3_io PU ) ( u_ddr_dqs_n_3_io OE ) + USE SIGNAL ; + - core_ddr_dqs_p_0_i ( u_ddr_dqs_p_0_io Y ) + USE SIGNAL ; + - core_ddr_dqs_p_0_o ( u_ddr_dqs_p_0_io A ) + USE SIGNAL ; + - core_ddr_dqs_p_0_sel ( u_ddr_dqs_p_0_io PU ) ( u_ddr_dqs_p_0_io OE ) + USE SIGNAL ; + - core_ddr_dqs_p_1_i ( u_ddr_dqs_p_1_io Y ) + USE SIGNAL ; + - core_ddr_dqs_p_1_o ( u_ddr_dqs_p_1_io A ) + USE SIGNAL ; + - core_ddr_dqs_p_1_sel ( u_ddr_dqs_p_1_io PU ) ( u_ddr_dqs_p_1_io OE ) + USE SIGNAL ; + - core_ddr_dqs_p_2_i ( u_ddr_dqs_p_2_io Y ) + USE SIGNAL ; + - core_ddr_dqs_p_2_o ( u_ddr_dqs_p_2_io A ) + USE SIGNAL ; + - core_ddr_dqs_p_2_sel ( u_ddr_dqs_p_2_io PU ) ( u_ddr_dqs_p_2_io OE ) + USE SIGNAL ; + - core_ddr_dqs_p_3_i ( u_ddr_dqs_p_3_io Y ) + USE SIGNAL ; + - core_ddr_dqs_p_3_o ( u_ddr_dqs_p_3_io A ) + USE SIGNAL ; + - core_ddr_dqs_p_3_sel ( u_ddr_dqs_p_3_io PU ) ( u_ddr_dqs_p_3_io OE ) + USE SIGNAL ; + - core_ddr_odt_o ( u_ddr_odt_o A ) + USE SIGNAL ; + - core_ddr_ras_n_o ( u_ddr_ras_n_o A ) + USE SIGNAL ; + - core_ddr_reset_n_o ( u_ddr_reset_n_o A ) + USE SIGNAL ; + - core_ddr_we_n_o ( u_ddr_we_n_o A ) + USE SIGNAL ; + - core_misc_o ( u_misc_o A ) + USE SIGNAL ; + - core_sel_0_i ( u_sel_0_i Y ) + USE SIGNAL ; + - core_sel_1_i ( u_sel_1_i Y ) + USE SIGNAL ; + - core_sel_2_i ( u_sel_2_i Y ) + USE SIGNAL ; + - p_bsg_tag_clk_i ( PIN p_bsg_tag_clk_i ) ( u_bsg_tag_clk_i PAD ) + USE SIGNAL ; + - p_bsg_tag_clk_o ( PIN p_bsg_tag_clk_o ) ( u_bsg_tag_clk_o PAD ) + USE SIGNAL ; + - p_bsg_tag_data_i ( PIN p_bsg_tag_data_i ) ( u_bsg_tag_data_i PAD ) + USE SIGNAL ; + - p_bsg_tag_data_o ( PIN p_bsg_tag_data_o ) ( u_bsg_tag_data_o PAD ) + USE SIGNAL ; + - p_bsg_tag_en_i ( PIN p_bsg_tag_en_i ) ( u_bsg_tag_en_i PAD ) + USE SIGNAL ; + - p_ci2_0_o ( PIN p_ci2_0_o ) ( u_ci2_0_o PAD ) + USE SIGNAL ; + - p_ci2_1_o ( PIN p_ci2_1_o ) ( u_ci2_1_o PAD ) + USE SIGNAL ; + - p_ci2_2_o ( PIN p_ci2_2_o ) ( u_ci2_2_o PAD ) + USE SIGNAL ; + - p_ci2_3_o ( PIN p_ci2_3_o ) ( u_ci2_3_o PAD ) + USE SIGNAL ; + - p_ci2_4_o ( PIN p_ci2_4_o ) ( u_ci2_4_o PAD ) + USE SIGNAL ; + - p_ci2_5_o ( PIN p_ci2_5_o ) ( u_ci2_5_o PAD ) + USE SIGNAL ; + - p_ci2_6_o ( PIN p_ci2_6_o ) ( u_ci2_6_o PAD ) + USE SIGNAL ; + - p_ci2_7_o ( PIN p_ci2_7_o ) ( u_ci2_7_o PAD ) + USE SIGNAL ; + - p_ci2_8_o ( PIN p_ci2_8_o ) ( u_ci2_8_o PAD ) + USE SIGNAL ; + - p_ci2_clk_o ( PIN p_ci2_clk_o ) ( u_ci2_clk_o PAD ) + USE SIGNAL ; + - p_ci2_tkn_i ( PIN p_ci2_tkn_i ) ( u_ci2_tkn_i PAD ) + USE SIGNAL ; + - p_ci2_v_o ( PIN p_ci2_v_o ) ( u_ci2_v_o PAD ) + USE SIGNAL ; + - p_ci_0_i ( PIN p_ci_0_i ) ( u_ci_0_i PAD ) + USE SIGNAL ; + - p_ci_1_i ( PIN p_ci_1_i ) ( u_ci_1_i PAD ) + USE SIGNAL ; + - p_ci_2_i ( PIN p_ci_2_i ) ( u_ci_2_i PAD ) + USE SIGNAL ; + - p_ci_3_i ( PIN p_ci_3_i ) ( u_ci_3_i PAD ) + USE SIGNAL ; + - p_ci_4_i ( PIN p_ci_4_i ) ( u_ci_4_i PAD ) + USE SIGNAL ; + - p_ci_5_i ( PIN p_ci_5_i ) ( u_ci_5_i PAD ) + USE SIGNAL ; + - p_ci_6_i ( PIN p_ci_6_i ) ( u_ci_6_i PAD ) + USE SIGNAL ; + - p_ci_7_i ( PIN p_ci_7_i ) ( u_ci_7_i PAD ) + USE SIGNAL ; + - p_ci_8_i ( PIN p_ci_8_i ) ( u_ci_8_i PAD ) + USE SIGNAL ; + - p_ci_clk_i ( PIN p_ci_clk_i ) ( u_ci_clk_i PAD ) + USE SIGNAL ; + - p_ci_tkn_o ( PIN p_ci_tkn_o ) ( u_ci_tkn_o PAD ) + USE SIGNAL ; + - p_ci_v_i ( PIN p_ci_v_i ) ( u_ci_v_i PAD ) + USE SIGNAL ; + - p_clk_A_i ( PIN p_clk_A_i ) ( u_clk_A_i PAD ) + USE SIGNAL ; + - p_clk_B_i ( PIN p_clk_B_i ) ( u_clk_B_i PAD ) + USE SIGNAL ; + - p_clk_C_i ( PIN p_clk_C_i ) ( u_clk_C_i PAD ) + USE SIGNAL ; + - p_clk_async_reset_i ( PIN p_clk_async_reset_i ) ( u_clk_async_reset_i PAD ) + USE SIGNAL ; + - p_clk_o ( PIN p_clk_o ) ( u_clk_o PAD ) + USE SIGNAL ; + - p_co2_0_o ( PIN p_co2_0_o ) ( u_co2_0_o PAD ) + USE SIGNAL ; + - p_co2_1_o ( PIN p_co2_1_o ) ( u_co2_1_o PAD ) + USE SIGNAL ; + - p_co2_2_o ( PIN p_co2_2_o ) ( u_co2_2_o PAD ) + USE SIGNAL ; + - p_co2_3_o ( PIN p_co2_3_o ) ( u_co2_3_o PAD ) + USE SIGNAL ; + - p_co2_4_o ( PIN p_co2_4_o ) ( u_co2_4_o PAD ) + USE SIGNAL ; + - p_co2_5_o ( PIN p_co2_5_o ) ( u_co2_5_o PAD ) + USE SIGNAL ; + - p_co2_6_o ( PIN p_co2_6_o ) ( u_co2_6_o PAD ) + USE SIGNAL ; + - p_co2_7_o ( PIN p_co2_7_o ) ( u_co2_7_o PAD ) + USE SIGNAL ; + - p_co2_8_o ( PIN p_co2_8_o ) ( u_co2_8_o PAD ) + USE SIGNAL ; + - p_co2_clk_o ( PIN p_co2_clk_o ) ( u_co2_clk_o PAD ) + USE SIGNAL ; + - p_co2_tkn_i ( PIN p_co2_tkn_i ) ( u_co2_tkn_i PAD ) + USE SIGNAL ; + - p_co2_v_o ( PIN p_co2_v_o ) ( u_co2_v_o PAD ) + USE SIGNAL ; + - p_co_0_i ( PIN p_co_0_i ) ( u_co_0_i PAD ) + USE SIGNAL ; + - p_co_1_i ( PIN p_co_1_i ) ( u_co_1_i PAD ) + USE SIGNAL ; + - p_co_2_i ( PIN p_co_2_i ) ( u_co_2_i PAD ) + USE SIGNAL ; + - p_co_3_i ( PIN p_co_3_i ) ( u_co_3_i PAD ) + USE SIGNAL ; + - p_co_4_i ( PIN p_co_4_i ) ( u_co_4_i PAD ) + USE SIGNAL ; + - p_co_5_i ( PIN p_co_5_i ) ( u_co_5_i PAD ) + USE SIGNAL ; + - p_co_6_i ( PIN p_co_6_i ) ( u_co_6_i PAD ) + USE SIGNAL ; + - p_co_7_i ( PIN p_co_7_i ) ( u_co_7_i PAD ) + USE SIGNAL ; + - p_co_8_i ( PIN p_co_8_i ) ( u_co_8_i PAD ) + USE SIGNAL ; + - p_co_clk_i ( PIN p_co_clk_i ) ( u_co_clk_i PAD ) + USE SIGNAL ; + - p_co_tkn_o ( PIN p_co_tkn_o ) ( u_co_tkn_o PAD ) + USE SIGNAL ; + - p_co_v_i ( PIN p_co_v_i ) ( u_co_v_i PAD ) + USE SIGNAL ; + - p_core_async_reset_i ( PIN p_core_async_reset_i ) ( u_core_async_reset_i PAD ) + USE SIGNAL ; + - p_ddr_addr_0_o ( PIN p_ddr_addr_0_o ) ( u_ddr_addr_0_o PAD ) + USE SIGNAL ; + - p_ddr_addr_10_o ( PIN p_ddr_addr_10_o ) ( u_ddr_addr_10_o PAD ) + USE SIGNAL ; + - p_ddr_addr_11_o ( PIN p_ddr_addr_11_o ) ( u_ddr_addr_11_o PAD ) + USE SIGNAL ; + - p_ddr_addr_12_o ( PIN p_ddr_addr_12_o ) ( u_ddr_addr_12_o PAD ) + USE SIGNAL ; + - p_ddr_addr_13_o ( PIN p_ddr_addr_13_o ) ( u_ddr_addr_13_o PAD ) + USE SIGNAL ; + - p_ddr_addr_14_o ( PIN p_ddr_addr_14_o ) ( u_ddr_addr_14_o PAD ) + USE SIGNAL ; + - p_ddr_addr_15_o ( PIN p_ddr_addr_15_o ) ( u_ddr_addr_15_o PAD ) + USE SIGNAL ; + - p_ddr_addr_1_o ( PIN p_ddr_addr_1_o ) ( u_ddr_addr_1_o PAD ) + USE SIGNAL ; + - p_ddr_addr_2_o ( PIN p_ddr_addr_2_o ) ( u_ddr_addr_2_o PAD ) + USE SIGNAL ; + - p_ddr_addr_3_o ( PIN p_ddr_addr_3_o ) ( u_ddr_addr_3_o PAD ) + USE SIGNAL ; + - p_ddr_addr_4_o ( PIN p_ddr_addr_4_o ) ( u_ddr_addr_4_o PAD ) + USE SIGNAL ; + - p_ddr_addr_5_o ( PIN p_ddr_addr_5_o ) ( u_ddr_addr_5_o PAD ) + USE SIGNAL ; + - p_ddr_addr_6_o ( PIN p_ddr_addr_6_o ) ( u_ddr_addr_6_o PAD ) + USE SIGNAL ; + - p_ddr_addr_7_o ( PIN p_ddr_addr_7_o ) ( u_ddr_addr_7_o PAD ) + USE SIGNAL ; + - p_ddr_addr_8_o ( PIN p_ddr_addr_8_o ) ( u_ddr_addr_8_o PAD ) + USE SIGNAL ; + - p_ddr_addr_9_o ( PIN p_ddr_addr_9_o ) ( u_ddr_addr_9_o PAD ) + USE SIGNAL ; + - p_ddr_ba_0_o ( PIN p_ddr_ba_0_o ) ( u_ddr_ba_0_o PAD ) + USE SIGNAL ; + - p_ddr_ba_1_o ( PIN p_ddr_ba_1_o ) ( u_ddr_ba_1_o PAD ) + USE SIGNAL ; + - p_ddr_ba_2_o ( PIN p_ddr_ba_2_o ) ( u_ddr_ba_2_o PAD ) + USE SIGNAL ; + - p_ddr_cas_n_o ( PIN p_ddr_cas_n_o ) ( u_ddr_cas_n_o PAD ) + USE SIGNAL ; + - p_ddr_ck_n_o ( PIN p_ddr_ck_n_o ) ( u_ddr_ck_n_o PAD ) + USE SIGNAL ; + - p_ddr_ck_p_o ( PIN p_ddr_ck_p_o ) ( u_ddr_ck_p_o PAD ) + USE SIGNAL ; + - p_ddr_cke_o ( PIN p_ddr_cke_o ) ( u_ddr_cke_o PAD ) + USE SIGNAL ; + - p_ddr_cs_n_o ( PIN p_ddr_cs_n_o ) ( u_ddr_cs_n_o PAD ) + USE SIGNAL ; + - p_ddr_dm_0_o ( PIN p_ddr_dm_0_o ) ( u_ddr_dm_0_o PAD ) + USE SIGNAL ; + - p_ddr_dm_1_o ( PIN p_ddr_dm_1_o ) ( u_ddr_dm_1_o PAD ) + USE SIGNAL ; + - p_ddr_dm_2_o ( PIN p_ddr_dm_2_o ) ( u_ddr_dm_2_o PAD ) + USE SIGNAL ; + - p_ddr_dm_3_o ( PIN p_ddr_dm_3_o ) ( u_ddr_dm_3_o PAD ) + USE SIGNAL ; + - p_ddr_dq_0_io ( PIN p_ddr_dq_0_io ) ( u_ddr_dq_0_io PAD ) + USE SIGNAL ; + - p_ddr_dq_10_io ( PIN p_ddr_dq_10_io ) ( u_ddr_dq_10_io PAD ) + USE SIGNAL ; + - p_ddr_dq_11_io ( PIN p_ddr_dq_11_io ) ( u_ddr_dq_11_io PAD ) + USE SIGNAL ; + - p_ddr_dq_12_io ( PIN p_ddr_dq_12_io ) ( u_ddr_dq_12_io PAD ) + USE SIGNAL ; + - p_ddr_dq_13_io ( PIN p_ddr_dq_13_io ) ( u_ddr_dq_13_io PAD ) + USE SIGNAL ; + - p_ddr_dq_14_io ( PIN p_ddr_dq_14_io ) ( u_ddr_dq_14_io PAD ) + USE SIGNAL ; + - p_ddr_dq_15_io ( PIN p_ddr_dq_15_io ) ( u_ddr_dq_15_io PAD ) + USE SIGNAL ; + - p_ddr_dq_16_io ( PIN p_ddr_dq_16_io ) ( u_ddr_dq_16_io PAD ) + USE SIGNAL ; + - p_ddr_dq_17_io ( PIN p_ddr_dq_17_io ) ( u_ddr_dq_17_io PAD ) + USE SIGNAL ; + - p_ddr_dq_18_io ( PIN p_ddr_dq_18_io ) ( u_ddr_dq_18_io PAD ) + USE SIGNAL ; + - p_ddr_dq_19_io ( PIN p_ddr_dq_19_io ) ( u_ddr_dq_19_io PAD ) + USE SIGNAL ; + - p_ddr_dq_1_io ( PIN p_ddr_dq_1_io ) ( u_ddr_dq_1_io PAD ) + USE SIGNAL ; + - p_ddr_dq_20_io ( PIN p_ddr_dq_20_io ) ( u_ddr_dq_20_io PAD ) + USE SIGNAL ; + - p_ddr_dq_21_io ( PIN p_ddr_dq_21_io ) ( u_ddr_dq_21_io PAD ) + USE SIGNAL ; + - p_ddr_dq_22_io ( PIN p_ddr_dq_22_io ) ( u_ddr_dq_22_io PAD ) + USE SIGNAL ; + - p_ddr_dq_23_io ( PIN p_ddr_dq_23_io ) ( u_ddr_dq_23_io PAD ) + USE SIGNAL ; + - p_ddr_dq_24_io ( PIN p_ddr_dq_24_io ) ( u_ddr_dq_24_io PAD ) + USE SIGNAL ; + - p_ddr_dq_25_io ( PIN p_ddr_dq_25_io ) ( u_ddr_dq_25_io PAD ) + USE SIGNAL ; + - p_ddr_dq_26_io ( PIN p_ddr_dq_26_io ) ( u_ddr_dq_26_io PAD ) + USE SIGNAL ; + - p_ddr_dq_27_io ( PIN p_ddr_dq_27_io ) ( u_ddr_dq_27_io PAD ) + USE SIGNAL ; + - p_ddr_dq_28_io ( PIN p_ddr_dq_28_io ) ( u_ddr_dq_28_io PAD ) + USE SIGNAL ; + - p_ddr_dq_29_io ( PIN p_ddr_dq_29_io ) ( u_ddr_dq_29_io PAD ) + USE SIGNAL ; + - p_ddr_dq_2_io ( PIN p_ddr_dq_2_io ) ( u_ddr_dq_2_io PAD ) + USE SIGNAL ; + - p_ddr_dq_30_io ( PIN p_ddr_dq_30_io ) ( u_ddr_dq_30_io PAD ) + USE SIGNAL ; + - p_ddr_dq_31_io ( PIN p_ddr_dq_31_io ) ( u_ddr_dq_31_io PAD ) + USE SIGNAL ; + - p_ddr_dq_3_io ( PIN p_ddr_dq_3_io ) ( u_ddr_dq_3_io PAD ) + USE SIGNAL ; + - p_ddr_dq_4_io ( PIN p_ddr_dq_4_io ) ( u_ddr_dq_4_io PAD ) + USE SIGNAL ; + - p_ddr_dq_5_io ( PIN p_ddr_dq_5_io ) ( u_ddr_dq_5_io PAD ) + USE SIGNAL ; + - p_ddr_dq_6_io ( PIN p_ddr_dq_6_io ) ( u_ddr_dq_6_io PAD ) + USE SIGNAL ; + - p_ddr_dq_7_io ( PIN p_ddr_dq_7_io ) ( u_ddr_dq_7_io PAD ) + USE SIGNAL ; + - p_ddr_dq_8_io ( PIN p_ddr_dq_8_io ) ( u_ddr_dq_8_io PAD ) + USE SIGNAL ; + - p_ddr_dq_9_io ( PIN p_ddr_dq_9_io ) ( u_ddr_dq_9_io PAD ) + USE SIGNAL ; + - p_ddr_dqs_n_0_io ( PIN p_ddr_dqs_n_0_io ) ( u_ddr_dqs_n_0_io PAD ) + USE SIGNAL ; + - p_ddr_dqs_n_1_io ( PIN p_ddr_dqs_n_1_io ) ( u_ddr_dqs_n_1_io PAD ) + USE SIGNAL ; + - p_ddr_dqs_n_2_io ( PIN p_ddr_dqs_n_2_io ) ( u_ddr_dqs_n_2_io PAD ) + USE SIGNAL ; + - p_ddr_dqs_n_3_io ( PIN p_ddr_dqs_n_3_io ) ( u_ddr_dqs_n_3_io PAD ) + USE SIGNAL ; + - p_ddr_dqs_p_0_io ( PIN p_ddr_dqs_p_0_io ) ( u_ddr_dqs_p_0_io PAD ) + USE SIGNAL ; + - p_ddr_dqs_p_1_io ( PIN p_ddr_dqs_p_1_io ) ( u_ddr_dqs_p_1_io PAD ) + USE SIGNAL ; + - p_ddr_dqs_p_2_io ( PIN p_ddr_dqs_p_2_io ) ( u_ddr_dqs_p_2_io PAD ) + USE SIGNAL ; + - p_ddr_dqs_p_3_io ( PIN p_ddr_dqs_p_3_io ) ( u_ddr_dqs_p_3_io PAD ) + USE SIGNAL ; + - p_ddr_odt_o ( PIN p_ddr_odt_o ) ( u_ddr_odt_o PAD ) + USE SIGNAL ; + - p_ddr_ras_n_o ( PIN p_ddr_ras_n_o ) ( u_ddr_ras_n_o PAD ) + USE SIGNAL ; + - p_ddr_reset_n_o ( PIN p_ddr_reset_n_o ) ( u_ddr_reset_n_o PAD ) + USE SIGNAL ; + - p_ddr_we_n_o ( PIN p_ddr_we_n_o ) ( u_ddr_we_n_o PAD ) + USE SIGNAL ; + - p_misc_o ( PIN p_misc_o ) ( u_misc_o PAD ) + USE SIGNAL ; + - p_sel_0_i ( PIN p_sel_0_i ) ( u_sel_0_i PAD ) + USE SIGNAL ; + - p_sel_1_i ( PIN p_sel_1_i ) ( u_sel_1_i PAD ) + USE SIGNAL ; + - p_sel_2_i ( PIN p_sel_2_i ) ( u_sel_2_i PAD ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/src/pad/test/place_pad_with_bumps.ok b/src/pad/test/place_pad_with_bumps.ok new file mode 100644 index 0000000000..b136b8e200 --- /dev/null +++ b/src/pad/test/place_pad_with_bumps.ok @@ -0,0 +1,7 @@ +[INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells +[INFO ODB-0227] LEF file: Nangate45_io/dummy_pads.lef, created 24 library cells +[INFO ODB-0128] Design: soc_bsg_black_parrot +[INFO ODB-0130] Created 135 pins. +[INFO ODB-0131] Created 267 components and 2277 component-terminals. +[INFO ODB-0133] Created 350 nets and 390 connections. +No differences found. diff --git a/src/pad/test/place_pad_with_bumps.tcl b/src/pad/test/place_pad_with_bumps.tcl new file mode 100644 index 0000000000..939d72270a --- /dev/null +++ b/src/pad/test/place_pad_with_bumps.tcl @@ -0,0 +1,19 @@ +# Test for placing pads when bumps have been placed +source "helpers.tcl" + +# Init chip +read_lef Nangate45/Nangate45.lef +read_lef Nangate45_io/dummy_pads.lef + +read_def Nangate45_blackparrot/floorplan.def + +# Test place_pad +make_io_sites -horizontal_site IOSITE -vertical_site IOSITE -corner_site IOSITE -offset 15 + +make_io_bump_array -bump DUMMY_BUMP -origin "100 500" -rows 5 -columns 5 -pitch "55 55" +place_pad -master PADCELL_SIG_V -row IO_EAST -location 500 "IO_EAST_SIDE" +place_pad -master PADCELL_SIG_V -row IO_WEST -location 500 "IO_WEST_SIDE" + +set def_file [make_result_file "place_pad_with_bumps.def"] +write_def $def_file +diff_files $def_file "place_pad_with_bumps.defok" diff --git a/src/pad/test/regression_tests.tcl b/src/pad/test/regression_tests.tcl index 335f28c9d3..cdf3b9f325 100644 --- a/src/pad/test/regression_tests.tcl +++ b/src/pad/test/regression_tests.tcl @@ -8,6 +8,7 @@ record_tests { make_io_sites_different_sites non_top_layer place_pad + place_pad_with_bumps place_pad_outsideofrow place_bondpad place_bondpad_stagger From 641453a515e815d4f064778dafd4c37ec0911019 Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Mon, 5 Aug 2024 14:03:19 -0400 Subject: [PATCH 31/37] pad: do error checking on origin and pitch and allow for single value pitch Signed-off-by: Peter Gadfort --- src/pad/src/pad.tcl | 10 + src/pad/test/bump_array_make_error.ok | 14 + src/pad/test/bump_array_make_error.tcl | 20 + .../test/bump_array_make_single_pitch.defok | 981 ++++++++++++++++++ src/pad/test/bump_array_make_single_pitch.ok | 7 + src/pad/test/bump_array_make_single_pitch.tcl | 15 + src/pad/test/regression_tests.tcl | 2 + 7 files changed, 1049 insertions(+) create mode 100644 src/pad/test/bump_array_make_error.ok create mode 100644 src/pad/test/bump_array_make_error.tcl create mode 100644 src/pad/test/bump_array_make_single_pitch.defok create mode 100644 src/pad/test/bump_array_make_single_pitch.ok create mode 100644 src/pad/test/bump_array_make_single_pitch.tcl diff --git a/src/pad/src/pad.tcl b/src/pad/src/pad.tcl index c4f213d487..1b1fcf50ff 100644 --- a/src/pad/src/pad.tcl +++ b/src/pad/src/pad.tcl @@ -58,6 +58,16 @@ proc make_io_bump_array {args} { lappend cmd_args $keys(-prefix) } + if { [llength $origin] != 2 } { + utl::error PAD 17 "-origin must be specified as {x y}" + } + + if { [llength $pitch] == 1 } { + lappend pitch $pitch + } elseif { [llength $pitch] != 2 } { + utl::error PAD 38 "-pitch must be specified as {deltax deltay} or {delta}" + } + pad::make_bump_array \ $master \ [ord::microns_to_dbu [lindex $origin 0]] \ diff --git a/src/pad/test/bump_array_make_error.ok b/src/pad/test/bump_array_make_error.ok new file mode 100644 index 0000000000..fe152d81be --- /dev/null +++ b/src/pad/test/bump_array_make_error.ok @@ -0,0 +1,14 @@ +[INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells +[INFO ODB-0227] LEF file: Nangate45_io/dummy_pads.lef, created 24 library cells +[INFO ODB-0128] Design: soc_bsg_black_parrot +[INFO ODB-0130] Created 135 pins. +[INFO ODB-0131] Created 267 components and 2277 component-terminals. +[INFO ODB-0133] Created 350 nets and 390 connections. +[ERROR PAD-0017] -origin must be specified as {x y} +PAD-0017 +[ERROR PAD-0017] -origin must be specified as {x y} +PAD-0017 +[ERROR PAD-0038] -pitch must be specified as {deltax deltay} or {delta} +PAD-0038 +[ERROR PAD-0038] -pitch must be specified as {deltax deltay} or {delta} +PAD-0038 diff --git a/src/pad/test/bump_array_make_error.tcl b/src/pad/test/bump_array_make_error.tcl new file mode 100644 index 0000000000..7546aba27c --- /dev/null +++ b/src/pad/test/bump_array_make_error.tcl @@ -0,0 +1,20 @@ +# Test for building bump array +source "helpers.tcl" + +# Init chip +read_lef Nangate45/Nangate45.lef +read_lef Nangate45_io/dummy_pads.lef + +read_def Nangate45_blackparrot/floorplan.def + +catch {[make_io_bump_array -bump DUMMY_BUMP -origin "200" -rows 14 -columns 14 -pitch "200 200"]} err +puts $err + +catch {[make_io_bump_array -bump DUMMY_BUMP -origin "200 200 200" -rows 14 -columns 14 -pitch "200 200"]} err +puts $err + +catch {[make_io_bump_array -bump DUMMY_BUMP -origin "200 200" -rows 14 -columns 14 -pitch "200 200 200"]} err +puts $err + +catch {[make_io_bump_array -bump DUMMY_BUMP -origin "200 200" -rows 14 -columns 14 -pitch ""]} err +puts $err diff --git a/src/pad/test/bump_array_make_single_pitch.defok b/src/pad/test/bump_array_make_single_pitch.defok new file mode 100644 index 0000000000..52ef9d317e --- /dev/null +++ b/src/pad/test/bump_array_make_single_pitch.defok @@ -0,0 +1,981 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN soc_bsg_black_parrot ; +UNITS DISTANCE MICRONS 2000 ; +DIEAREA ( 0 0 ) ( 6000000 6000000 ) ; +TRACKS X 190 DO 21428 STEP 280 LAYER metal1 ; +TRACKS Y 140 DO 21428 STEP 280 LAYER metal1 ; +TRACKS X 190 DO 15789 STEP 380 LAYER metal2 ; +TRACKS Y 140 DO 15789 STEP 380 LAYER metal2 ; +TRACKS X 190 DO 21428 STEP 280 LAYER metal3 ; +TRACKS Y 140 DO 21428 STEP 280 LAYER metal3 ; +TRACKS X 190 DO 10714 STEP 560 LAYER metal4 ; +TRACKS Y 140 DO 10714 STEP 560 LAYER metal4 ; +TRACKS X 190 DO 10714 STEP 560 LAYER metal5 ; +TRACKS Y 140 DO 10714 STEP 560 LAYER metal5 ; +TRACKS X 190 DO 10714 STEP 560 LAYER metal6 ; +TRACKS Y 140 DO 10714 STEP 560 LAYER metal6 ; +TRACKS X 1790 DO 3749 STEP 1600 LAYER metal7 ; +TRACKS Y 1740 DO 3749 STEP 1600 LAYER metal7 ; +TRACKS X 1790 DO 3749 STEP 1600 LAYER metal8 ; +TRACKS Y 1740 DO 3749 STEP 1600 LAYER metal8 ; +TRACKS X 3390 DO 1874 STEP 3200 LAYER metal9 ; +TRACKS Y 3340 DO 1874 STEP 3200 LAYER metal9 ; +TRACKS X 3390 DO 1874 STEP 3200 LAYER metal10 ; +TRACKS Y 3340 DO 1874 STEP 3200 LAYER metal10 ; +COMPONENTS 463 ; + - BUMP_0_0 DUMMY_BUMP + FIXED ( 400000 400000 ) N ; + - BUMP_0_1 DUMMY_BUMP + FIXED ( 400000 800000 ) N ; + - BUMP_0_10 DUMMY_BUMP + FIXED ( 400000 4400000 ) N ; + - BUMP_0_11 DUMMY_BUMP + FIXED ( 400000 4800000 ) N ; + - BUMP_0_12 DUMMY_BUMP + FIXED ( 400000 5200000 ) N ; + - BUMP_0_13 DUMMY_BUMP + FIXED ( 400000 5600000 ) N ; + - BUMP_0_2 DUMMY_BUMP + FIXED ( 400000 1200000 ) N ; + - BUMP_0_3 DUMMY_BUMP + FIXED ( 400000 1600000 ) N ; + - BUMP_0_4 DUMMY_BUMP + FIXED ( 400000 2000000 ) N ; + - BUMP_0_5 DUMMY_BUMP + FIXED ( 400000 2400000 ) N ; + - BUMP_0_6 DUMMY_BUMP + FIXED ( 400000 2800000 ) N ; + - BUMP_0_7 DUMMY_BUMP + FIXED ( 400000 3200000 ) N ; + - BUMP_0_8 DUMMY_BUMP + FIXED ( 400000 3600000 ) N ; + - BUMP_0_9 DUMMY_BUMP + FIXED ( 400000 4000000 ) N ; + - BUMP_10_0 DUMMY_BUMP + FIXED ( 4400000 400000 ) N ; + - BUMP_10_1 DUMMY_BUMP + FIXED ( 4400000 800000 ) N ; + - BUMP_10_10 DUMMY_BUMP + FIXED ( 4400000 4400000 ) N ; + - BUMP_10_11 DUMMY_BUMP + FIXED ( 4400000 4800000 ) N ; + - BUMP_10_12 DUMMY_BUMP + FIXED ( 4400000 5200000 ) N ; + - BUMP_10_13 DUMMY_BUMP + FIXED ( 4400000 5600000 ) N ; + - BUMP_10_2 DUMMY_BUMP + FIXED ( 4400000 1200000 ) N ; + - BUMP_10_3 DUMMY_BUMP + FIXED ( 4400000 1600000 ) N ; + - BUMP_10_4 DUMMY_BUMP + FIXED ( 4400000 2000000 ) N ; + - BUMP_10_5 DUMMY_BUMP + FIXED ( 4400000 2400000 ) N ; + - BUMP_10_6 DUMMY_BUMP + FIXED ( 4400000 2800000 ) N ; + - BUMP_10_7 DUMMY_BUMP + FIXED ( 4400000 3200000 ) N ; + - BUMP_10_8 DUMMY_BUMP + FIXED ( 4400000 3600000 ) N ; + - BUMP_10_9 DUMMY_BUMP + FIXED ( 4400000 4000000 ) N ; + - BUMP_11_0 DUMMY_BUMP + FIXED ( 4800000 400000 ) N ; + - BUMP_11_1 DUMMY_BUMP + FIXED ( 4800000 800000 ) N ; + - BUMP_11_10 DUMMY_BUMP + FIXED ( 4800000 4400000 ) N ; + - BUMP_11_11 DUMMY_BUMP + FIXED ( 4800000 4800000 ) N ; + - BUMP_11_12 DUMMY_BUMP + FIXED ( 4800000 5200000 ) N ; + - BUMP_11_13 DUMMY_BUMP + FIXED ( 4800000 5600000 ) N ; + - BUMP_11_2 DUMMY_BUMP + FIXED ( 4800000 1200000 ) N ; + - BUMP_11_3 DUMMY_BUMP + FIXED ( 4800000 1600000 ) N ; + - BUMP_11_4 DUMMY_BUMP + FIXED ( 4800000 2000000 ) N ; + - BUMP_11_5 DUMMY_BUMP + FIXED ( 4800000 2400000 ) N ; + - BUMP_11_6 DUMMY_BUMP + FIXED ( 4800000 2800000 ) N ; + - BUMP_11_7 DUMMY_BUMP + FIXED ( 4800000 3200000 ) N ; + - BUMP_11_8 DUMMY_BUMP + FIXED ( 4800000 3600000 ) N ; + - BUMP_11_9 DUMMY_BUMP + FIXED ( 4800000 4000000 ) N ; + - BUMP_12_0 DUMMY_BUMP + FIXED ( 5200000 400000 ) N ; + - BUMP_12_1 DUMMY_BUMP + FIXED ( 5200000 800000 ) N ; + - BUMP_12_10 DUMMY_BUMP + FIXED ( 5200000 4400000 ) N ; + - BUMP_12_11 DUMMY_BUMP + FIXED ( 5200000 4800000 ) N ; + - BUMP_12_12 DUMMY_BUMP + FIXED ( 5200000 5200000 ) N ; + - BUMP_12_13 DUMMY_BUMP + FIXED ( 5200000 5600000 ) N ; + - BUMP_12_2 DUMMY_BUMP + FIXED ( 5200000 1200000 ) N ; + - BUMP_12_3 DUMMY_BUMP + FIXED ( 5200000 1600000 ) N ; + - BUMP_12_4 DUMMY_BUMP + FIXED ( 5200000 2000000 ) N ; + - BUMP_12_5 DUMMY_BUMP + FIXED ( 5200000 2400000 ) N ; + - BUMP_12_6 DUMMY_BUMP + FIXED ( 5200000 2800000 ) N ; + - BUMP_12_7 DUMMY_BUMP + FIXED ( 5200000 3200000 ) N ; + - BUMP_12_8 DUMMY_BUMP + FIXED ( 5200000 3600000 ) N ; + - BUMP_12_9 DUMMY_BUMP + FIXED ( 5200000 4000000 ) N ; + - BUMP_13_0 DUMMY_BUMP + FIXED ( 5600000 400000 ) N ; + - BUMP_13_1 DUMMY_BUMP + FIXED ( 5600000 800000 ) N ; + - BUMP_13_10 DUMMY_BUMP + FIXED ( 5600000 4400000 ) N ; + - BUMP_13_11 DUMMY_BUMP + FIXED ( 5600000 4800000 ) N ; + - BUMP_13_12 DUMMY_BUMP + FIXED ( 5600000 5200000 ) N ; + - BUMP_13_13 DUMMY_BUMP + FIXED ( 5600000 5600000 ) N ; + - BUMP_13_2 DUMMY_BUMP + FIXED ( 5600000 1200000 ) N ; + - BUMP_13_3 DUMMY_BUMP + FIXED ( 5600000 1600000 ) N ; + - BUMP_13_4 DUMMY_BUMP + FIXED ( 5600000 2000000 ) N ; + - BUMP_13_5 DUMMY_BUMP + FIXED ( 5600000 2400000 ) N ; + - BUMP_13_6 DUMMY_BUMP + FIXED ( 5600000 2800000 ) N ; + - BUMP_13_7 DUMMY_BUMP + FIXED ( 5600000 3200000 ) N ; + - BUMP_13_8 DUMMY_BUMP + FIXED ( 5600000 3600000 ) N ; + - BUMP_13_9 DUMMY_BUMP + FIXED ( 5600000 4000000 ) N ; + - BUMP_1_0 DUMMY_BUMP + FIXED ( 800000 400000 ) N ; + - BUMP_1_1 DUMMY_BUMP + FIXED ( 800000 800000 ) N ; + - BUMP_1_10 DUMMY_BUMP + FIXED ( 800000 4400000 ) N ; + - BUMP_1_11 DUMMY_BUMP + FIXED ( 800000 4800000 ) N ; + - BUMP_1_12 DUMMY_BUMP + FIXED ( 800000 5200000 ) N ; + - BUMP_1_13 DUMMY_BUMP + FIXED ( 800000 5600000 ) N ; + - BUMP_1_2 DUMMY_BUMP + FIXED ( 800000 1200000 ) N ; + - BUMP_1_3 DUMMY_BUMP + FIXED ( 800000 1600000 ) N ; + - BUMP_1_4 DUMMY_BUMP + FIXED ( 800000 2000000 ) N ; + - BUMP_1_5 DUMMY_BUMP + FIXED ( 800000 2400000 ) N ; + - BUMP_1_6 DUMMY_BUMP + FIXED ( 800000 2800000 ) N ; + - BUMP_1_7 DUMMY_BUMP + FIXED ( 800000 3200000 ) N ; + - BUMP_1_8 DUMMY_BUMP + FIXED ( 800000 3600000 ) N ; + - BUMP_1_9 DUMMY_BUMP + FIXED ( 800000 4000000 ) N ; + - BUMP_2_0 DUMMY_BUMP + FIXED ( 1200000 400000 ) N ; + - BUMP_2_1 DUMMY_BUMP + FIXED ( 1200000 800000 ) N ; + - BUMP_2_10 DUMMY_BUMP + FIXED ( 1200000 4400000 ) N ; + - BUMP_2_11 DUMMY_BUMP + FIXED ( 1200000 4800000 ) N ; + - BUMP_2_12 DUMMY_BUMP + FIXED ( 1200000 5200000 ) N ; + - BUMP_2_13 DUMMY_BUMP + FIXED ( 1200000 5600000 ) N ; + - BUMP_2_2 DUMMY_BUMP + FIXED ( 1200000 1200000 ) N ; + - BUMP_2_3 DUMMY_BUMP + FIXED ( 1200000 1600000 ) N ; + - BUMP_2_4 DUMMY_BUMP + FIXED ( 1200000 2000000 ) N ; + - BUMP_2_5 DUMMY_BUMP + FIXED ( 1200000 2400000 ) N ; + - BUMP_2_6 DUMMY_BUMP + FIXED ( 1200000 2800000 ) N ; + - BUMP_2_7 DUMMY_BUMP + FIXED ( 1200000 3200000 ) N ; + - BUMP_2_8 DUMMY_BUMP + FIXED ( 1200000 3600000 ) N ; + - BUMP_2_9 DUMMY_BUMP + FIXED ( 1200000 4000000 ) N ; + - BUMP_3_0 DUMMY_BUMP + FIXED ( 1600000 400000 ) N ; + - BUMP_3_1 DUMMY_BUMP + FIXED ( 1600000 800000 ) N ; + - BUMP_3_10 DUMMY_BUMP + FIXED ( 1600000 4400000 ) N ; + - BUMP_3_11 DUMMY_BUMP + FIXED ( 1600000 4800000 ) N ; + - BUMP_3_12 DUMMY_BUMP + FIXED ( 1600000 5200000 ) N ; + - BUMP_3_13 DUMMY_BUMP + FIXED ( 1600000 5600000 ) N ; + - BUMP_3_2 DUMMY_BUMP + FIXED ( 1600000 1200000 ) N ; + - BUMP_3_3 DUMMY_BUMP + FIXED ( 1600000 1600000 ) N ; + - BUMP_3_4 DUMMY_BUMP + FIXED ( 1600000 2000000 ) N ; + - BUMP_3_5 DUMMY_BUMP + FIXED ( 1600000 2400000 ) N ; + - BUMP_3_6 DUMMY_BUMP + FIXED ( 1600000 2800000 ) N ; + - BUMP_3_7 DUMMY_BUMP + FIXED ( 1600000 3200000 ) N ; + - BUMP_3_8 DUMMY_BUMP + FIXED ( 1600000 3600000 ) N ; + - BUMP_3_9 DUMMY_BUMP + FIXED ( 1600000 4000000 ) N ; + - BUMP_4_0 DUMMY_BUMP + FIXED ( 2000000 400000 ) N ; + - BUMP_4_1 DUMMY_BUMP + FIXED ( 2000000 800000 ) N ; + - BUMP_4_10 DUMMY_BUMP + FIXED ( 2000000 4400000 ) N ; + - BUMP_4_11 DUMMY_BUMP + FIXED ( 2000000 4800000 ) N ; + - BUMP_4_12 DUMMY_BUMP + FIXED ( 2000000 5200000 ) N ; + - BUMP_4_13 DUMMY_BUMP + FIXED ( 2000000 5600000 ) N ; + - BUMP_4_2 DUMMY_BUMP + FIXED ( 2000000 1200000 ) N ; + - BUMP_4_3 DUMMY_BUMP + FIXED ( 2000000 1600000 ) N ; + - BUMP_4_4 DUMMY_BUMP + FIXED ( 2000000 2000000 ) N ; + - BUMP_4_5 DUMMY_BUMP + FIXED ( 2000000 2400000 ) N ; + - BUMP_4_6 DUMMY_BUMP + FIXED ( 2000000 2800000 ) N ; + - BUMP_4_7 DUMMY_BUMP + FIXED ( 2000000 3200000 ) N ; + - BUMP_4_8 DUMMY_BUMP + FIXED ( 2000000 3600000 ) N ; + - BUMP_4_9 DUMMY_BUMP + FIXED ( 2000000 4000000 ) N ; + - BUMP_5_0 DUMMY_BUMP + FIXED ( 2400000 400000 ) N ; + - BUMP_5_1 DUMMY_BUMP + FIXED ( 2400000 800000 ) N ; + - BUMP_5_10 DUMMY_BUMP + FIXED ( 2400000 4400000 ) N ; + - BUMP_5_11 DUMMY_BUMP + FIXED ( 2400000 4800000 ) N ; + - BUMP_5_12 DUMMY_BUMP + FIXED ( 2400000 5200000 ) N ; + - BUMP_5_13 DUMMY_BUMP + FIXED ( 2400000 5600000 ) N ; + - BUMP_5_2 DUMMY_BUMP + FIXED ( 2400000 1200000 ) N ; + - BUMP_5_3 DUMMY_BUMP + FIXED ( 2400000 1600000 ) N ; + - BUMP_5_4 DUMMY_BUMP + FIXED ( 2400000 2000000 ) N ; + - BUMP_5_5 DUMMY_BUMP + FIXED ( 2400000 2400000 ) N ; + - BUMP_5_6 DUMMY_BUMP + FIXED ( 2400000 2800000 ) N ; + - BUMP_5_7 DUMMY_BUMP + FIXED ( 2400000 3200000 ) N ; + - BUMP_5_8 DUMMY_BUMP + FIXED ( 2400000 3600000 ) N ; + - BUMP_5_9 DUMMY_BUMP + FIXED ( 2400000 4000000 ) N ; + - BUMP_6_0 DUMMY_BUMP + FIXED ( 2800000 400000 ) N ; + - BUMP_6_1 DUMMY_BUMP + FIXED ( 2800000 800000 ) N ; + - BUMP_6_10 DUMMY_BUMP + FIXED ( 2800000 4400000 ) N ; + - BUMP_6_11 DUMMY_BUMP + FIXED ( 2800000 4800000 ) N ; + - BUMP_6_12 DUMMY_BUMP + FIXED ( 2800000 5200000 ) N ; + - BUMP_6_13 DUMMY_BUMP + FIXED ( 2800000 5600000 ) N ; + - BUMP_6_2 DUMMY_BUMP + FIXED ( 2800000 1200000 ) N ; + - BUMP_6_3 DUMMY_BUMP + FIXED ( 2800000 1600000 ) N ; + - BUMP_6_4 DUMMY_BUMP + FIXED ( 2800000 2000000 ) N ; + - BUMP_6_5 DUMMY_BUMP + FIXED ( 2800000 2400000 ) N ; + - BUMP_6_6 DUMMY_BUMP + FIXED ( 2800000 2800000 ) N ; + - BUMP_6_7 DUMMY_BUMP + FIXED ( 2800000 3200000 ) N ; + - BUMP_6_8 DUMMY_BUMP + FIXED ( 2800000 3600000 ) N ; + - BUMP_6_9 DUMMY_BUMP + FIXED ( 2800000 4000000 ) N ; + - BUMP_7_0 DUMMY_BUMP + FIXED ( 3200000 400000 ) N ; + - BUMP_7_1 DUMMY_BUMP + FIXED ( 3200000 800000 ) N ; + - BUMP_7_10 DUMMY_BUMP + FIXED ( 3200000 4400000 ) N ; + - BUMP_7_11 DUMMY_BUMP + FIXED ( 3200000 4800000 ) N ; + - BUMP_7_12 DUMMY_BUMP + FIXED ( 3200000 5200000 ) N ; + - BUMP_7_13 DUMMY_BUMP + FIXED ( 3200000 5600000 ) N ; + - BUMP_7_2 DUMMY_BUMP + FIXED ( 3200000 1200000 ) N ; + - BUMP_7_3 DUMMY_BUMP + FIXED ( 3200000 1600000 ) N ; + - BUMP_7_4 DUMMY_BUMP + FIXED ( 3200000 2000000 ) N ; + - BUMP_7_5 DUMMY_BUMP + FIXED ( 3200000 2400000 ) N ; + - BUMP_7_6 DUMMY_BUMP + FIXED ( 3200000 2800000 ) N ; + - BUMP_7_7 DUMMY_BUMP + FIXED ( 3200000 3200000 ) N ; + - BUMP_7_8 DUMMY_BUMP + FIXED ( 3200000 3600000 ) N ; + - BUMP_7_9 DUMMY_BUMP + FIXED ( 3200000 4000000 ) N ; + - BUMP_8_0 DUMMY_BUMP + FIXED ( 3600000 400000 ) N ; + - BUMP_8_1 DUMMY_BUMP + FIXED ( 3600000 800000 ) N ; + - BUMP_8_10 DUMMY_BUMP + FIXED ( 3600000 4400000 ) N ; + - BUMP_8_11 DUMMY_BUMP + FIXED ( 3600000 4800000 ) N ; + - BUMP_8_12 DUMMY_BUMP + FIXED ( 3600000 5200000 ) N ; + - BUMP_8_13 DUMMY_BUMP + FIXED ( 3600000 5600000 ) N ; + - BUMP_8_2 DUMMY_BUMP + FIXED ( 3600000 1200000 ) N ; + - BUMP_8_3 DUMMY_BUMP + FIXED ( 3600000 1600000 ) N ; + - BUMP_8_4 DUMMY_BUMP + FIXED ( 3600000 2000000 ) N ; + - BUMP_8_5 DUMMY_BUMP + FIXED ( 3600000 2400000 ) N ; + - BUMP_8_6 DUMMY_BUMP + FIXED ( 3600000 2800000 ) N ; + - BUMP_8_7 DUMMY_BUMP + FIXED ( 3600000 3200000 ) N ; + - BUMP_8_8 DUMMY_BUMP + FIXED ( 3600000 3600000 ) N ; + - BUMP_8_9 DUMMY_BUMP + FIXED ( 3600000 4000000 ) N ; + - BUMP_9_0 DUMMY_BUMP + FIXED ( 4000000 400000 ) N ; + - BUMP_9_1 DUMMY_BUMP + FIXED ( 4000000 800000 ) N ; + - BUMP_9_10 DUMMY_BUMP + FIXED ( 4000000 4400000 ) N ; + - BUMP_9_11 DUMMY_BUMP + FIXED ( 4000000 4800000 ) N ; + - BUMP_9_12 DUMMY_BUMP + FIXED ( 4000000 5200000 ) N ; + - BUMP_9_13 DUMMY_BUMP + FIXED ( 4000000 5600000 ) N ; + - BUMP_9_2 DUMMY_BUMP + FIXED ( 4000000 1200000 ) N ; + - BUMP_9_3 DUMMY_BUMP + FIXED ( 4000000 1600000 ) N ; + - BUMP_9_4 DUMMY_BUMP + FIXED ( 4000000 2000000 ) N ; + - BUMP_9_5 DUMMY_BUMP + FIXED ( 4000000 2400000 ) N ; + - BUMP_9_6 DUMMY_BUMP + FIXED ( 4000000 2800000 ) N ; + - BUMP_9_7 DUMMY_BUMP + FIXED ( 4000000 3200000 ) N ; + - BUMP_9_8 DUMMY_BUMP + FIXED ( 4000000 3600000 ) N ; + - BUMP_9_9 DUMMY_BUMP + FIXED ( 4000000 4000000 ) N ; + - u_bsg_tag_clk_i PADCELL_SIG_H ; + - u_bsg_tag_clk_o PADCELL_SIG_H ; + - u_bsg_tag_data_i PADCELL_SIG_H ; + - u_bsg_tag_data_o PADCELL_SIG_H ; + - u_bsg_tag_en_i PADCELL_SIG_H ; + - u_ci2_0_o PADCELL_SIG_V ; + - u_ci2_1_o PADCELL_SIG_V ; + - u_ci2_2_o PADCELL_SIG_V ; + - u_ci2_3_o PADCELL_SIG_V ; + - u_ci2_4_o PADCELL_SIG_V ; + - u_ci2_5_o PADCELL_SIG_V ; + - u_ci2_6_o PADCELL_SIG_V ; + - u_ci2_7_o PADCELL_SIG_V ; + - u_ci2_8_o PADCELL_SIG_V ; + - u_ci2_clk_o PADCELL_SIG_V ; + - u_ci2_tkn_i PADCELL_SIG_V ; + - u_ci2_v_o PADCELL_SIG_V ; + - u_ci_0_i PADCELL_SIG_H ; + - u_ci_1_i PADCELL_SIG_H ; + - u_ci_2_i PADCELL_SIG_H ; + - u_ci_3_i PADCELL_SIG_H ; + - u_ci_4_i PADCELL_SIG_H ; + - u_ci_5_i PADCELL_SIG_H ; + - u_ci_6_i PADCELL_SIG_H ; + - u_ci_7_i PADCELL_SIG_H ; + - u_ci_8_i PADCELL_SIG_H ; + - u_ci_clk_i PADCELL_SIG_H ; + - u_ci_tkn_o PADCELL_SIG_H ; + - u_ci_v_i PADCELL_SIG_H ; + - u_clk_A_i PADCELL_SIG_V ; + - u_clk_B_i PADCELL_SIG_V ; + - u_clk_C_i PADCELL_SIG_V ; + - u_clk_async_reset_i PADCELL_SIG_V ; + - u_clk_o PADCELL_SIG_V ; + - u_co2_0_o PADCELL_SIG_H ; + - u_co2_1_o PADCELL_SIG_H ; + - u_co2_2_o PADCELL_SIG_H ; + - u_co2_3_o PADCELL_SIG_H ; + - u_co2_4_o PADCELL_SIG_H ; + - u_co2_5_o PADCELL_SIG_H ; + - u_co2_6_o PADCELL_SIG_H ; + - u_co2_7_o PADCELL_SIG_H ; + - u_co2_8_o PADCELL_SIG_H ; + - u_co2_clk_o PADCELL_SIG_H ; + - u_co2_tkn_i PADCELL_SIG_H ; + - u_co2_v_o PADCELL_SIG_H ; + - u_co_0_i PADCELL_SIG_V ; + - u_co_1_i PADCELL_SIG_V ; + - u_co_2_i PADCELL_SIG_V ; + - u_co_3_i PADCELL_SIG_V ; + - u_co_4_i PADCELL_SIG_V ; + - u_co_5_i PADCELL_SIG_V ; + - u_co_6_i PADCELL_SIG_V ; + - u_co_7_i PADCELL_SIG_V ; + - u_co_8_i PADCELL_SIG_V ; + - u_co_clk_i PADCELL_SIG_V ; + - u_co_tkn_o PADCELL_SIG_V ; + - u_co_v_i PADCELL_SIG_V ; + - u_core_async_reset_i PADCELL_SIG_V ; + - u_ddr_addr_0_o PADCELL_SIG_V ; + - u_ddr_addr_10_o PADCELL_SIG_V ; + - u_ddr_addr_11_o PADCELL_SIG_V ; + - u_ddr_addr_12_o PADCELL_SIG_V ; + - u_ddr_addr_13_o PADCELL_SIG_V ; + - u_ddr_addr_14_o PADCELL_SIG_V ; + - u_ddr_addr_15_o PADCELL_SIG_V ; + - u_ddr_addr_1_o PADCELL_SIG_V ; + - u_ddr_addr_2_o PADCELL_SIG_V ; + - u_ddr_addr_3_o PADCELL_SIG_V ; + - u_ddr_addr_4_o PADCELL_SIG_V ; + - u_ddr_addr_5_o PADCELL_SIG_V ; + - u_ddr_addr_6_o PADCELL_SIG_V ; + - u_ddr_addr_7_o PADCELL_SIG_V ; + - u_ddr_addr_8_o PADCELL_SIG_V ; + - u_ddr_addr_9_o PADCELL_SIG_V ; + - u_ddr_ba_0_o PADCELL_SIG_V ; + - u_ddr_ba_1_o PADCELL_SIG_V ; + - u_ddr_ba_2_o PADCELL_SIG_V ; + - u_ddr_cas_n_o PADCELL_SIG_V ; + - u_ddr_ck_n_o PADCELL_SIG_V ; + - u_ddr_ck_p_o PADCELL_SIG_V ; + - u_ddr_cke_o PADCELL_SIG_V ; + - u_ddr_cs_n_o PADCELL_SIG_V ; + - u_ddr_dm_0_o PADCELL_SIG_H ; + - u_ddr_dm_1_o PADCELL_SIG_V ; + - u_ddr_dm_2_o PADCELL_SIG_V ; + - u_ddr_dm_3_o PADCELL_SIG_H ; + - u_ddr_dq_0_io PADCELL_SIG_H ; + - u_ddr_dq_10_io PADCELL_SIG_H ; + - u_ddr_dq_11_io PADCELL_SIG_H ; + - u_ddr_dq_12_io PADCELL_SIG_H ; + - u_ddr_dq_13_io PADCELL_SIG_H ; + - u_ddr_dq_14_io PADCELL_SIG_H ; + - u_ddr_dq_15_io PADCELL_SIG_H ; + - u_ddr_dq_16_io PADCELL_SIG_H ; + - u_ddr_dq_17_io PADCELL_SIG_H ; + - u_ddr_dq_18_io PADCELL_SIG_H ; + - u_ddr_dq_19_io PADCELL_SIG_H ; + - u_ddr_dq_1_io PADCELL_SIG_H ; + - u_ddr_dq_20_io PADCELL_SIG_H ; + - u_ddr_dq_21_io PADCELL_SIG_H ; + - u_ddr_dq_22_io PADCELL_SIG_H ; + - u_ddr_dq_23_io PADCELL_SIG_H ; + - u_ddr_dq_24_io PADCELL_SIG_H ; + - u_ddr_dq_25_io PADCELL_SIG_H ; + - u_ddr_dq_26_io PADCELL_SIG_H ; + - u_ddr_dq_27_io PADCELL_SIG_H ; + - u_ddr_dq_28_io PADCELL_SIG_H ; + - u_ddr_dq_29_io PADCELL_SIG_H ; + - u_ddr_dq_2_io PADCELL_SIG_H ; + - u_ddr_dq_30_io PADCELL_SIG_H ; + - u_ddr_dq_31_io PADCELL_SIG_H ; + - u_ddr_dq_3_io PADCELL_SIG_H ; + - u_ddr_dq_4_io PADCELL_SIG_H ; + - u_ddr_dq_5_io PADCELL_SIG_H ; + - u_ddr_dq_6_io PADCELL_SIG_H ; + - u_ddr_dq_7_io PADCELL_SIG_H ; + - u_ddr_dq_8_io PADCELL_SIG_H ; + - u_ddr_dq_9_io PADCELL_SIG_H ; + - u_ddr_dqs_n_0_io PADCELL_SIG_H ; + - u_ddr_dqs_n_1_io PADCELL_SIG_V ; + - u_ddr_dqs_n_2_io PADCELL_SIG_V ; + - u_ddr_dqs_n_3_io PADCELL_SIG_H ; + - u_ddr_dqs_p_0_io PADCELL_SIG_H ; + - u_ddr_dqs_p_1_io PADCELL_SIG_V ; + - u_ddr_dqs_p_2_io PADCELL_SIG_V ; + - u_ddr_dqs_p_3_io PADCELL_SIG_H ; + - u_ddr_odt_o PADCELL_SIG_V ; + - u_ddr_ras_n_o PADCELL_SIG_V ; + - u_ddr_reset_n_o PADCELL_SIG_V ; + - u_ddr_we_n_o PADCELL_SIG_V ; + - u_misc_o PADCELL_SIG_V ; + - u_sel_0_i PADCELL_SIG_V ; + - u_sel_1_i PADCELL_SIG_V ; + - u_sel_2_i PADCELL_SIG_V ; + - u_v18_1 PADCELL_VDDIO_V ; + - u_v18_10 PADCELL_VDDIO_H ; + - u_v18_11 PADCELL_VDDIO_H ; + - u_v18_12 PADCELL_VDDIO_H ; + - u_v18_13 PADCELL_VDDIO_H ; + - u_v18_14 PADCELL_VDDIO_H ; + - u_v18_15 PADCELL_VDDIO_H ; + - u_v18_16 PADCELL_VDDIO_H ; + - u_v18_17 PADCELL_VDDIO_V ; + - u_v18_18 PADCELL_VDDIO_V ; + - u_v18_19 PADCELL_VDDIO_V ; + - u_v18_2 PADCELL_VDDIO_V ; + - u_v18_20 PADCELL_VDDIO_V ; + - u_v18_21 PADCELL_VDDIO_V ; + - u_v18_22 PADCELL_VDDIO_V ; + - u_v18_23 PADCELL_VDDIO_V ; + - u_v18_24 PADCELL_VDDIO_V ; + - u_v18_25 PADCELL_VDDIO_H ; + - u_v18_26 PADCELL_VDDIO_H ; + - u_v18_27 PADCELL_VDDIO_H ; + - u_v18_28 PADCELL_VDDIO_H ; + - u_v18_29 PADCELL_VDDIO_H ; + - u_v18_3 PADCELL_VDDIO_V ; + - u_v18_30 PADCELL_VDDIO_H ; + - u_v18_31 PADCELL_VDDIO_H ; + - u_v18_32 PADCELL_VDDIO_H ; + - u_v18_4 PADCELL_VDDIO_V ; + - u_v18_5 PADCELL_VDDIO_V ; + - u_v18_6 PADCELL_VDDIO_V ; + - u_v18_7 PADCELL_VDDIO_V ; + - u_v18_8 PADCELL_VDDIO_V ; + - u_v18_9 PADCELL_VDDIO_H ; + - u_vdd_1 PADCELL_VDD_V ; + - u_vdd_10 PADCELL_VDD_H ; + - u_vdd_11 PADCELL_VDD_H ; + - u_vdd_12 PADCELL_VDD_H ; + - u_vdd_13 PADCELL_VDD_H ; + - u_vdd_14 PADCELL_VDD_H ; + - u_vdd_15 PADCELL_VDD_H ; + - u_vdd_16 PADCELL_VDD_H ; + - u_vdd_17 PADCELL_VDD_V ; + - u_vdd_18 PADCELL_VDD_V ; + - u_vdd_19 PADCELL_VDD_V ; + - u_vdd_2 PADCELL_VDD_V ; + - u_vdd_20 PADCELL_VDD_V ; + - u_vdd_21 PADCELL_VDD_V ; + - u_vdd_22 PADCELL_VDD_V ; + - u_vdd_23 PADCELL_VDD_V ; + - u_vdd_24 PADCELL_VDD_V ; + - u_vdd_25 PADCELL_VDD_H ; + - u_vdd_26 PADCELL_VDD_H ; + - u_vdd_27 PADCELL_VDD_H ; + - u_vdd_28 PADCELL_VDD_H ; + - u_vdd_29 PADCELL_VDD_H ; + - u_vdd_3 PADCELL_VDD_V ; + - u_vdd_30 PADCELL_VDD_H ; + - u_vdd_31 PADCELL_VDD_H ; + - u_vdd_32 PADCELL_VDD_H ; + - u_vdd_4 PADCELL_VDD_V ; + - u_vdd_5 PADCELL_VDD_V ; + - u_vdd_6 PADCELL_VDD_V ; + - u_vdd_7 PADCELL_VDD_V ; + - u_vdd_8 PADCELL_VDD_H ; + - u_vdd_9 PADCELL_VDD_H ; + - u_vdd_pll PADCELL_VDD_V ; + - u_vss_0 PADCELL_VSS_V ; + - u_vss_1 PADCELL_VSS_V ; + - u_vss_10 PADCELL_VSS_H ; + - u_vss_11 PADCELL_VSS_H ; + - u_vss_12 PADCELL_VSS_H ; + - u_vss_13 PADCELL_VSS_H ; + - u_vss_14 PADCELL_VSS_H ; + - u_vss_15 PADCELL_VSS_H ; + - u_vss_16 PADCELL_VSS_H ; + - u_vss_17 PADCELL_VSS_V ; + - u_vss_18 PADCELL_VSS_V ; + - u_vss_19 PADCELL_VSS_V ; + - u_vss_2 PADCELL_VSS_V ; + - u_vss_20 PADCELL_VSS_V ; + - u_vss_21 PADCELL_VSS_V ; + - u_vss_22 PADCELL_VSS_V ; + - u_vss_23 PADCELL_VSS_V ; + - u_vss_24 PADCELL_VSS_V ; + - u_vss_25 PADCELL_VSS_H ; + - u_vss_26 PADCELL_VSS_H ; + - u_vss_27 PADCELL_VSS_H ; + - u_vss_28 PADCELL_VSS_H ; + - u_vss_29 PADCELL_VSS_H ; + - u_vss_3 PADCELL_VSS_V ; + - u_vss_30 PADCELL_VSS_H ; + - u_vss_31 PADCELL_VSS_H ; + - u_vss_32 PADCELL_VSS_H ; + - u_vss_4 PADCELL_VSS_V ; + - u_vss_5 PADCELL_VSS_V ; + - u_vss_6 PADCELL_VSS_V ; + - u_vss_7 PADCELL_VSS_V ; + - u_vss_8 PADCELL_VSS_H ; + - u_vss_9 PADCELL_VSS_H ; + - u_vss_pll PADCELL_VSS_V ; + - u_vzz_0 PADCELL_VSSIO_V ; + - u_vzz_1 PADCELL_VSSIO_V ; + - u_vzz_10 PADCELL_VSSIO_H ; + - u_vzz_11 PADCELL_VSSIO_H ; + - u_vzz_12 PADCELL_VSSIO_H ; + - u_vzz_13 PADCELL_VSSIO_H ; + - u_vzz_14 PADCELL_VSSIO_H ; + - u_vzz_15 PADCELL_VSSIO_H ; + - u_vzz_16 PADCELL_VSSIO_H ; + - u_vzz_17 PADCELL_VSSIO_V ; + - u_vzz_18 PADCELL_VSSIO_V ; + - u_vzz_19 PADCELL_VSSIO_V ; + - u_vzz_2 PADCELL_VSSIO_V ; + - u_vzz_20 PADCELL_VSSIO_V ; + - u_vzz_21 PADCELL_VSSIO_V ; + - u_vzz_22 PADCELL_VSSIO_V ; + - u_vzz_23 PADCELL_VSSIO_V ; + - u_vzz_24 PADCELL_VSSIO_V ; + - u_vzz_25 PADCELL_VSSIO_H ; + - u_vzz_26 PADCELL_VSSIO_H ; + - u_vzz_27 PADCELL_VSSIO_H ; + - u_vzz_28 PADCELL_VSSIO_H ; + - u_vzz_29 PADCELL_VSSIO_H ; + - u_vzz_3 PADCELL_VSSIO_V ; + - u_vzz_30 PADCELL_VSSIO_H ; + - u_vzz_31 PADCELL_VSSIO_H ; + - u_vzz_32 PADCELL_VSSIO_H ; + - u_vzz_4 PADCELL_VSSIO_V ; + - u_vzz_5 PADCELL_VSSIO_V ; + - u_vzz_6 PADCELL_VSSIO_V ; + - u_vzz_7 PADCELL_VSSIO_V ; + - u_vzz_8 PADCELL_VSSIO_V ; + - u_vzz_9 PADCELL_VSSIO_H ; +END COMPONENTS +PINS 135 ; + - p_bsg_tag_clk_i + NET p_bsg_tag_clk_i + DIRECTION INPUT + USE SIGNAL ; + - p_bsg_tag_clk_o + NET p_bsg_tag_clk_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_bsg_tag_data_i + NET p_bsg_tag_data_i + DIRECTION INPUT + USE SIGNAL ; + - p_bsg_tag_data_o + NET p_bsg_tag_data_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_bsg_tag_en_i + NET p_bsg_tag_en_i + DIRECTION INPUT + USE SIGNAL ; + - p_ci2_0_o + NET p_ci2_0_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ci2_1_o + NET p_ci2_1_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ci2_2_o + NET p_ci2_2_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ci2_3_o + NET p_ci2_3_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ci2_4_o + NET p_ci2_4_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ci2_5_o + NET p_ci2_5_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ci2_6_o + NET p_ci2_6_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ci2_7_o + NET p_ci2_7_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ci2_8_o + NET p_ci2_8_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ci2_clk_o + NET p_ci2_clk_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ci2_tkn_i + NET p_ci2_tkn_i + DIRECTION INPUT + USE SIGNAL ; + - p_ci2_v_o + NET p_ci2_v_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ci_0_i + NET p_ci_0_i + DIRECTION INPUT + USE SIGNAL ; + - p_ci_1_i + NET p_ci_1_i + DIRECTION INPUT + USE SIGNAL ; + - p_ci_2_i + NET p_ci_2_i + DIRECTION INPUT + USE SIGNAL ; + - p_ci_3_i + NET p_ci_3_i + DIRECTION INPUT + USE SIGNAL ; + - p_ci_4_i + NET p_ci_4_i + DIRECTION INPUT + USE SIGNAL ; + - p_ci_5_i + NET p_ci_5_i + DIRECTION INPUT + USE SIGNAL ; + - p_ci_6_i + NET p_ci_6_i + DIRECTION INPUT + USE SIGNAL ; + - p_ci_7_i + NET p_ci_7_i + DIRECTION INPUT + USE SIGNAL ; + - p_ci_8_i + NET p_ci_8_i + DIRECTION INPUT + USE SIGNAL ; + - p_ci_clk_i + NET p_ci_clk_i + DIRECTION INPUT + USE SIGNAL ; + - p_ci_tkn_o + NET p_ci_tkn_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ci_v_i + NET p_ci_v_i + DIRECTION INPUT + USE SIGNAL ; + - p_clk_A_i + NET p_clk_A_i + DIRECTION INPUT + USE SIGNAL ; + - p_clk_B_i + NET p_clk_B_i + DIRECTION INPUT + USE SIGNAL ; + - p_clk_C_i + NET p_clk_C_i + DIRECTION INPUT + USE SIGNAL ; + - p_clk_async_reset_i + NET p_clk_async_reset_i + DIRECTION INPUT + USE SIGNAL ; + - p_clk_o + NET p_clk_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co2_0_o + NET p_co2_0_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co2_1_o + NET p_co2_1_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co2_2_o + NET p_co2_2_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co2_3_o + NET p_co2_3_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co2_4_o + NET p_co2_4_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co2_5_o + NET p_co2_5_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co2_6_o + NET p_co2_6_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co2_7_o + NET p_co2_7_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co2_8_o + NET p_co2_8_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co2_clk_o + NET p_co2_clk_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co2_tkn_i + NET p_co2_tkn_i + DIRECTION INPUT + USE SIGNAL ; + - p_co2_v_o + NET p_co2_v_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co_0_i + NET p_co_0_i + DIRECTION INPUT + USE SIGNAL ; + - p_co_1_i + NET p_co_1_i + DIRECTION INPUT + USE SIGNAL ; + - p_co_2_i + NET p_co_2_i + DIRECTION INPUT + USE SIGNAL ; + - p_co_3_i + NET p_co_3_i + DIRECTION INPUT + USE SIGNAL ; + - p_co_4_i + NET p_co_4_i + DIRECTION INPUT + USE SIGNAL ; + - p_co_5_i + NET p_co_5_i + DIRECTION INPUT + USE SIGNAL ; + - p_co_6_i + NET p_co_6_i + DIRECTION INPUT + USE SIGNAL ; + - p_co_7_i + NET p_co_7_i + DIRECTION INPUT + USE SIGNAL ; + - p_co_8_i + NET p_co_8_i + DIRECTION INPUT + USE SIGNAL ; + - p_co_clk_i + NET p_co_clk_i + DIRECTION INPUT + USE SIGNAL ; + - p_co_tkn_o + NET p_co_tkn_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co_v_i + NET p_co_v_i + DIRECTION INPUT + USE SIGNAL ; + - p_core_async_reset_i + NET p_core_async_reset_i + DIRECTION INPUT + USE SIGNAL ; + - p_ddr_addr_0_o + NET p_ddr_addr_0_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_10_o + NET p_ddr_addr_10_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_11_o + NET p_ddr_addr_11_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_12_o + NET p_ddr_addr_12_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_13_o + NET p_ddr_addr_13_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_14_o + NET p_ddr_addr_14_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_15_o + NET p_ddr_addr_15_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_1_o + NET p_ddr_addr_1_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_2_o + NET p_ddr_addr_2_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_3_o + NET p_ddr_addr_3_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_4_o + NET p_ddr_addr_4_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_5_o + NET p_ddr_addr_5_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_6_o + NET p_ddr_addr_6_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_7_o + NET p_ddr_addr_7_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_8_o + NET p_ddr_addr_8_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_9_o + NET p_ddr_addr_9_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_ba_0_o + NET p_ddr_ba_0_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_ba_1_o + NET p_ddr_ba_1_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_ba_2_o + NET p_ddr_ba_2_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_cas_n_o + NET p_ddr_cas_n_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_ck_n_o + NET p_ddr_ck_n_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_ck_p_o + NET p_ddr_ck_p_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_cke_o + NET p_ddr_cke_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_cs_n_o + NET p_ddr_cs_n_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_dm_0_o + NET p_ddr_dm_0_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_dm_1_o + NET p_ddr_dm_1_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_dm_2_o + NET p_ddr_dm_2_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_dm_3_o + NET p_ddr_dm_3_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_dq_0_io + NET p_ddr_dq_0_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_10_io + NET p_ddr_dq_10_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_11_io + NET p_ddr_dq_11_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_12_io + NET p_ddr_dq_12_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_13_io + NET p_ddr_dq_13_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_14_io + NET p_ddr_dq_14_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_15_io + NET p_ddr_dq_15_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_16_io + NET p_ddr_dq_16_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_17_io + NET p_ddr_dq_17_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_18_io + NET p_ddr_dq_18_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_19_io + NET p_ddr_dq_19_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_1_io + NET p_ddr_dq_1_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_20_io + NET p_ddr_dq_20_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_21_io + NET p_ddr_dq_21_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_22_io + NET p_ddr_dq_22_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_23_io + NET p_ddr_dq_23_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_24_io + NET p_ddr_dq_24_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_25_io + NET p_ddr_dq_25_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_26_io + NET p_ddr_dq_26_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_27_io + NET p_ddr_dq_27_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_28_io + NET p_ddr_dq_28_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_29_io + NET p_ddr_dq_29_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_2_io + NET p_ddr_dq_2_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_30_io + NET p_ddr_dq_30_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_31_io + NET p_ddr_dq_31_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_3_io + NET p_ddr_dq_3_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_4_io + NET p_ddr_dq_4_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_5_io + NET p_ddr_dq_5_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_6_io + NET p_ddr_dq_6_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_7_io + NET p_ddr_dq_7_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_8_io + NET p_ddr_dq_8_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_9_io + NET p_ddr_dq_9_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dqs_n_0_io + NET p_ddr_dqs_n_0_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dqs_n_1_io + NET p_ddr_dqs_n_1_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dqs_n_2_io + NET p_ddr_dqs_n_2_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dqs_n_3_io + NET p_ddr_dqs_n_3_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dqs_p_0_io + NET p_ddr_dqs_p_0_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dqs_p_1_io + NET p_ddr_dqs_p_1_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dqs_p_2_io + NET p_ddr_dqs_p_2_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dqs_p_3_io + NET p_ddr_dqs_p_3_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_odt_o + NET p_ddr_odt_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_ras_n_o + NET p_ddr_ras_n_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_reset_n_o + NET p_ddr_reset_n_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_we_n_o + NET p_ddr_we_n_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_misc_o + NET p_misc_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_sel_0_i + NET p_sel_0_i + DIRECTION INPUT + USE SIGNAL ; + - p_sel_1_i + NET p_sel_1_i + DIRECTION INPUT + USE SIGNAL ; + - p_sel_2_i + NET p_sel_2_i + DIRECTION INPUT + USE SIGNAL ; +END PINS +NETS 350 ; + - core_bsg_tag_clk_i ( u_bsg_tag_clk_i Y ) + USE SIGNAL ; + - core_bsg_tag_clk_o ( u_bsg_tag_clk_o A ) + USE SIGNAL ; + - core_bsg_tag_data_i ( u_bsg_tag_data_i Y ) + USE SIGNAL ; + - core_bsg_tag_data_o ( u_bsg_tag_data_o A ) + USE SIGNAL ; + - core_bsg_tag_en_i ( u_bsg_tag_en_i Y ) + USE SIGNAL ; + - core_ci2_0_o ( u_ci2_0_o A ) + USE SIGNAL ; + - core_ci2_1_o ( u_ci2_1_o A ) + USE SIGNAL ; + - core_ci2_2_o ( u_ci2_2_o A ) + USE SIGNAL ; + - core_ci2_3_o ( u_ci2_3_o A ) + USE SIGNAL ; + - core_ci2_4_o ( u_ci2_4_o A ) + USE SIGNAL ; + - core_ci2_5_o ( u_ci2_5_o A ) + USE SIGNAL ; + - core_ci2_6_o ( u_ci2_6_o A ) + USE SIGNAL ; + - core_ci2_7_o ( u_ci2_7_o A ) + USE SIGNAL ; + - core_ci2_8_o ( u_ci2_8_o A ) + USE SIGNAL ; + - core_ci2_clk_o ( u_ci2_clk_o A ) + USE SIGNAL ; + - core_ci2_tkn_i ( u_ci2_tkn_i Y ) + USE SIGNAL ; + - core_ci2_v_o ( u_ci2_v_o A ) + USE SIGNAL ; + - core_ci_0_i ( u_ci_0_i Y ) + USE SIGNAL ; + - core_ci_1_i ( u_ci_1_i Y ) + USE SIGNAL ; + - core_ci_2_i ( u_ci_2_i Y ) + USE SIGNAL ; + - core_ci_3_i ( u_ci_3_i Y ) + USE SIGNAL ; + - core_ci_4_i ( u_ci_4_i Y ) + USE SIGNAL ; + - core_ci_5_i ( u_ci_5_i Y ) + USE SIGNAL ; + - core_ci_6_i ( u_ci_6_i Y ) + USE SIGNAL ; + - core_ci_7_i ( u_ci_7_i Y ) + USE SIGNAL ; + - core_ci_8_i ( u_ci_8_i Y ) + USE SIGNAL ; + - core_ci_clk_i ( u_ci_clk_i Y ) + USE SIGNAL ; + - core_ci_tkn_o ( u_ci_tkn_o A ) + USE SIGNAL ; + - core_ci_v_i ( u_ci_v_i Y ) + USE SIGNAL ; + - core_clk_A_i ( u_clk_A_i Y ) + USE SIGNAL ; + - core_clk_B_i ( u_clk_B_i Y ) + USE SIGNAL ; + - core_clk_C_i ( u_clk_C_i Y ) + USE SIGNAL ; + - core_clk_async_reset_i ( u_clk_async_reset_i Y ) + USE SIGNAL ; + - core_clk_o ( u_clk_o A ) + USE SIGNAL ; + - core_co2_0_o ( u_co2_0_o A ) + USE SIGNAL ; + - core_co2_1_o ( u_co2_1_o A ) + USE SIGNAL ; + - core_co2_2_o ( u_co2_2_o A ) + USE SIGNAL ; + - core_co2_3_o ( u_co2_3_o A ) + USE SIGNAL ; + - core_co2_4_o ( u_co2_4_o A ) + USE SIGNAL ; + - core_co2_5_o ( u_co2_5_o A ) + USE SIGNAL ; + - core_co2_6_o ( u_co2_6_o A ) + USE SIGNAL ; + - core_co2_7_o ( u_co2_7_o A ) + USE SIGNAL ; + - core_co2_8_o ( u_co2_8_o A ) + USE SIGNAL ; + - core_co2_clk_o ( u_co2_clk_o A ) + USE SIGNAL ; + - core_co2_tkn_i ( u_co2_tkn_i Y ) + USE SIGNAL ; + - core_co2_v_o ( u_co2_v_o A ) + USE SIGNAL ; + - core_co_0_i ( u_co_0_i Y ) + USE SIGNAL ; + - core_co_1_i ( u_co_1_i Y ) + USE SIGNAL ; + - core_co_2_i ( u_co_2_i Y ) + USE SIGNAL ; + - core_co_3_i ( u_co_3_i Y ) + USE SIGNAL ; + - core_co_4_i ( u_co_4_i Y ) + USE SIGNAL ; + - core_co_5_i ( u_co_5_i Y ) + USE SIGNAL ; + - core_co_6_i ( u_co_6_i Y ) + USE SIGNAL ; + - core_co_7_i ( u_co_7_i Y ) + USE SIGNAL ; + - core_co_8_i ( u_co_8_i Y ) + USE SIGNAL ; + - core_co_clk_i ( u_co_clk_i Y ) + USE SIGNAL ; + - core_co_tkn_o ( u_co_tkn_o A ) + USE SIGNAL ; + - core_co_v_i ( u_co_v_i Y ) + USE SIGNAL ; + - core_core_async_reset_i ( u_core_async_reset_i Y ) + USE SIGNAL ; + - core_ddr_addr_0_o ( u_ddr_addr_0_o A ) + USE SIGNAL ; + - core_ddr_addr_10_o ( u_ddr_addr_10_o A ) + USE SIGNAL ; + - core_ddr_addr_11_o ( u_ddr_addr_11_o A ) + USE SIGNAL ; + - core_ddr_addr_12_o ( u_ddr_addr_12_o A ) + USE SIGNAL ; + - core_ddr_addr_13_o ( u_ddr_addr_13_o A ) + USE SIGNAL ; + - core_ddr_addr_14_o ( u_ddr_addr_14_o A ) + USE SIGNAL ; + - core_ddr_addr_15_o ( u_ddr_addr_15_o A ) + USE SIGNAL ; + - core_ddr_addr_1_o ( u_ddr_addr_1_o A ) + USE SIGNAL ; + - core_ddr_addr_2_o ( u_ddr_addr_2_o A ) + USE SIGNAL ; + - core_ddr_addr_3_o ( u_ddr_addr_3_o A ) + USE SIGNAL ; + - core_ddr_addr_4_o ( u_ddr_addr_4_o A ) + USE SIGNAL ; + - core_ddr_addr_5_o ( u_ddr_addr_5_o A ) + USE SIGNAL ; + - core_ddr_addr_6_o ( u_ddr_addr_6_o A ) + USE SIGNAL ; + - core_ddr_addr_7_o ( u_ddr_addr_7_o A ) + USE SIGNAL ; + - core_ddr_addr_8_o ( u_ddr_addr_8_o A ) + USE SIGNAL ; + - core_ddr_addr_9_o ( u_ddr_addr_9_o A ) + USE SIGNAL ; + - core_ddr_ba_0_o ( u_ddr_ba_0_o A ) + USE SIGNAL ; + - core_ddr_ba_1_o ( u_ddr_ba_1_o A ) + USE SIGNAL ; + - core_ddr_ba_2_o ( u_ddr_ba_2_o A ) + USE SIGNAL ; + - core_ddr_cas_n_o ( u_ddr_cas_n_o A ) + USE SIGNAL ; + - core_ddr_ck_n_o ( u_ddr_ck_n_o A ) + USE SIGNAL ; + - core_ddr_ck_p_o ( u_ddr_ck_p_o A ) + USE SIGNAL ; + - core_ddr_cke_o ( u_ddr_cke_o A ) + USE SIGNAL ; + - core_ddr_cs_n_o ( u_ddr_cs_n_o A ) + USE SIGNAL ; + - core_ddr_dm_0_o ( u_ddr_dm_0_o A ) + USE SIGNAL ; + - core_ddr_dm_1_o ( u_ddr_dm_1_o A ) + USE SIGNAL ; + - core_ddr_dm_2_o ( u_ddr_dm_2_o A ) + USE SIGNAL ; + - core_ddr_dm_3_o ( u_ddr_dm_3_o A ) + USE SIGNAL ; + - core_ddr_dq_0_i ( u_ddr_dq_0_io Y ) + USE SIGNAL ; + - core_ddr_dq_0_o ( u_ddr_dq_0_io A ) + USE SIGNAL ; + - core_ddr_dq_0_sel ( u_ddr_dq_0_io PU ) ( u_ddr_dq_0_io OE ) + USE SIGNAL ; + - core_ddr_dq_10_i ( u_ddr_dq_10_io Y ) + USE SIGNAL ; + - core_ddr_dq_10_o ( u_ddr_dq_10_io A ) + USE SIGNAL ; + - core_ddr_dq_10_sel ( u_ddr_dq_10_io PU ) ( u_ddr_dq_10_io OE ) + USE SIGNAL ; + - core_ddr_dq_11_i ( u_ddr_dq_11_io Y ) + USE SIGNAL ; + - core_ddr_dq_11_o ( u_ddr_dq_11_io A ) + USE SIGNAL ; + - core_ddr_dq_11_sel ( u_ddr_dq_11_io PU ) ( u_ddr_dq_11_io OE ) + USE SIGNAL ; + - core_ddr_dq_12_i ( u_ddr_dq_12_io Y ) + USE SIGNAL ; + - core_ddr_dq_12_o ( u_ddr_dq_12_io A ) + USE SIGNAL ; + - core_ddr_dq_12_sel ( u_ddr_dq_12_io PU ) ( u_ddr_dq_12_io OE ) + USE SIGNAL ; + - core_ddr_dq_13_i ( u_ddr_dq_13_io Y ) + USE SIGNAL ; + - core_ddr_dq_13_o ( u_ddr_dq_13_io A ) + USE SIGNAL ; + - core_ddr_dq_13_sel ( u_ddr_dq_13_io PU ) ( u_ddr_dq_13_io OE ) + USE SIGNAL ; + - core_ddr_dq_14_i ( u_ddr_dq_14_io Y ) + USE SIGNAL ; + - core_ddr_dq_14_o ( u_ddr_dq_14_io A ) + USE SIGNAL ; + - core_ddr_dq_14_sel ( u_ddr_dq_14_io PU ) ( u_ddr_dq_14_io OE ) + USE SIGNAL ; + - core_ddr_dq_15_i ( u_ddr_dq_15_io Y ) + USE SIGNAL ; + - core_ddr_dq_15_o ( u_ddr_dq_15_io A ) + USE SIGNAL ; + - core_ddr_dq_15_sel ( u_ddr_dq_15_io PU ) ( u_ddr_dq_15_io OE ) + USE SIGNAL ; + - core_ddr_dq_16_i ( u_ddr_dq_16_io Y ) + USE SIGNAL ; + - core_ddr_dq_16_o ( u_ddr_dq_16_io A ) + USE SIGNAL ; + - core_ddr_dq_16_sel ( u_ddr_dq_16_io PU ) ( u_ddr_dq_16_io OE ) + USE SIGNAL ; + - core_ddr_dq_17_i ( u_ddr_dq_17_io Y ) + USE SIGNAL ; + - core_ddr_dq_17_o ( u_ddr_dq_17_io A ) + USE SIGNAL ; + - core_ddr_dq_17_sel ( u_ddr_dq_17_io PU ) ( u_ddr_dq_17_io OE ) + USE SIGNAL ; + - core_ddr_dq_18_i ( u_ddr_dq_18_io Y ) + USE SIGNAL ; + - core_ddr_dq_18_o ( u_ddr_dq_18_io A ) + USE SIGNAL ; + - core_ddr_dq_18_sel ( u_ddr_dq_18_io PU ) ( u_ddr_dq_18_io OE ) + USE SIGNAL ; + - core_ddr_dq_19_i ( u_ddr_dq_19_io Y ) + USE SIGNAL ; + - core_ddr_dq_19_o ( u_ddr_dq_19_io A ) + USE SIGNAL ; + - core_ddr_dq_19_sel ( u_ddr_dq_19_io PU ) ( u_ddr_dq_19_io OE ) + USE SIGNAL ; + - core_ddr_dq_1_i ( u_ddr_dq_1_io Y ) + USE SIGNAL ; + - core_ddr_dq_1_o ( u_ddr_dq_1_io A ) + USE SIGNAL ; + - core_ddr_dq_1_sel ( u_ddr_dq_1_io PU ) ( u_ddr_dq_1_io OE ) + USE SIGNAL ; + - core_ddr_dq_20_i ( u_ddr_dq_20_io Y ) + USE SIGNAL ; + - core_ddr_dq_20_o ( u_ddr_dq_20_io A ) + USE SIGNAL ; + - core_ddr_dq_20_sel ( u_ddr_dq_20_io PU ) ( u_ddr_dq_20_io OE ) + USE SIGNAL ; + - core_ddr_dq_21_i ( u_ddr_dq_21_io Y ) + USE SIGNAL ; + - core_ddr_dq_21_o ( u_ddr_dq_21_io A ) + USE SIGNAL ; + - core_ddr_dq_21_sel ( u_ddr_dq_21_io PU ) ( u_ddr_dq_21_io OE ) + USE SIGNAL ; + - core_ddr_dq_22_i ( u_ddr_dq_22_io Y ) + USE SIGNAL ; + - core_ddr_dq_22_o ( u_ddr_dq_22_io A ) + USE SIGNAL ; + - core_ddr_dq_22_sel ( u_ddr_dq_22_io PU ) ( u_ddr_dq_22_io OE ) + USE SIGNAL ; + - core_ddr_dq_23_i ( u_ddr_dq_23_io Y ) + USE SIGNAL ; + - core_ddr_dq_23_o ( u_ddr_dq_23_io A ) + USE SIGNAL ; + - core_ddr_dq_23_sel ( u_ddr_dq_23_io PU ) ( u_ddr_dq_23_io OE ) + USE SIGNAL ; + - core_ddr_dq_24_i ( u_ddr_dq_24_io Y ) + USE SIGNAL ; + - core_ddr_dq_24_o ( u_ddr_dq_24_io A ) + USE SIGNAL ; + - core_ddr_dq_24_sel ( u_ddr_dq_24_io PU ) ( u_ddr_dq_24_io OE ) + USE SIGNAL ; + - core_ddr_dq_25_i ( u_ddr_dq_25_io Y ) + USE SIGNAL ; + - core_ddr_dq_25_o ( u_ddr_dq_25_io A ) + USE SIGNAL ; + - core_ddr_dq_25_sel ( u_ddr_dq_25_io PU ) ( u_ddr_dq_25_io OE ) + USE SIGNAL ; + - core_ddr_dq_26_i ( u_ddr_dq_26_io Y ) + USE SIGNAL ; + - core_ddr_dq_26_o ( u_ddr_dq_26_io A ) + USE SIGNAL ; + - core_ddr_dq_26_sel ( u_ddr_dq_26_io PU ) ( u_ddr_dq_26_io OE ) + USE SIGNAL ; + - core_ddr_dq_27_i ( u_ddr_dq_27_io Y ) + USE SIGNAL ; + - core_ddr_dq_27_o ( u_ddr_dq_27_io A ) + USE SIGNAL ; + - core_ddr_dq_27_sel ( u_ddr_dq_27_io PU ) ( u_ddr_dq_27_io OE ) + USE SIGNAL ; + - core_ddr_dq_28_i ( u_ddr_dq_28_io Y ) + USE SIGNAL ; + - core_ddr_dq_28_o ( u_ddr_dq_28_io A ) + USE SIGNAL ; + - core_ddr_dq_28_sel ( u_ddr_dq_28_io PU ) ( u_ddr_dq_28_io OE ) + USE SIGNAL ; + - core_ddr_dq_29_i ( u_ddr_dq_29_io Y ) + USE SIGNAL ; + - core_ddr_dq_29_o ( u_ddr_dq_29_io A ) + USE SIGNAL ; + - core_ddr_dq_29_sel ( u_ddr_dq_29_io PU ) ( u_ddr_dq_29_io OE ) + USE SIGNAL ; + - core_ddr_dq_2_i ( u_ddr_dq_2_io Y ) + USE SIGNAL ; + - core_ddr_dq_2_o ( u_ddr_dq_2_io A ) + USE SIGNAL ; + - core_ddr_dq_2_sel ( u_ddr_dq_2_io PU ) ( u_ddr_dq_2_io OE ) + USE SIGNAL ; + - core_ddr_dq_30_i ( u_ddr_dq_30_io Y ) + USE SIGNAL ; + - core_ddr_dq_30_o ( u_ddr_dq_30_io A ) + USE SIGNAL ; + - core_ddr_dq_30_sel ( u_ddr_dq_30_io PU ) ( u_ddr_dq_30_io OE ) + USE SIGNAL ; + - core_ddr_dq_31_i ( u_ddr_dq_31_io Y ) + USE SIGNAL ; + - core_ddr_dq_31_o ( u_ddr_dq_31_io A ) + USE SIGNAL ; + - core_ddr_dq_31_sel ( u_ddr_dq_31_io PU ) ( u_ddr_dq_31_io OE ) + USE SIGNAL ; + - core_ddr_dq_3_i ( u_ddr_dq_3_io Y ) + USE SIGNAL ; + - core_ddr_dq_3_o ( u_ddr_dq_3_io A ) + USE SIGNAL ; + - core_ddr_dq_3_sel ( u_ddr_dq_3_io PU ) ( u_ddr_dq_3_io OE ) + USE SIGNAL ; + - core_ddr_dq_4_i ( u_ddr_dq_4_io Y ) + USE SIGNAL ; + - core_ddr_dq_4_o ( u_ddr_dq_4_io A ) + USE SIGNAL ; + - core_ddr_dq_4_sel ( u_ddr_dq_4_io PU ) ( u_ddr_dq_4_io OE ) + USE SIGNAL ; + - core_ddr_dq_5_i ( u_ddr_dq_5_io Y ) + USE SIGNAL ; + - core_ddr_dq_5_o ( u_ddr_dq_5_io A ) + USE SIGNAL ; + - core_ddr_dq_5_sel ( u_ddr_dq_5_io PU ) ( u_ddr_dq_5_io OE ) + USE SIGNAL ; + - core_ddr_dq_6_i ( u_ddr_dq_6_io Y ) + USE SIGNAL ; + - core_ddr_dq_6_o ( u_ddr_dq_6_io A ) + USE SIGNAL ; + - core_ddr_dq_6_sel ( u_ddr_dq_6_io PU ) ( u_ddr_dq_6_io OE ) + USE SIGNAL ; + - core_ddr_dq_7_i ( u_ddr_dq_7_io Y ) + USE SIGNAL ; + - core_ddr_dq_7_o ( u_ddr_dq_7_io A ) + USE SIGNAL ; + - core_ddr_dq_7_sel ( u_ddr_dq_7_io PU ) ( u_ddr_dq_7_io OE ) + USE SIGNAL ; + - core_ddr_dq_8_i ( u_ddr_dq_8_io Y ) + USE SIGNAL ; + - core_ddr_dq_8_o ( u_ddr_dq_8_io A ) + USE SIGNAL ; + - core_ddr_dq_8_sel ( u_ddr_dq_8_io PU ) ( u_ddr_dq_8_io OE ) + USE SIGNAL ; + - core_ddr_dq_9_i ( u_ddr_dq_9_io Y ) + USE SIGNAL ; + - core_ddr_dq_9_o ( u_ddr_dq_9_io A ) + USE SIGNAL ; + - core_ddr_dq_9_sel ( u_ddr_dq_9_io PU ) ( u_ddr_dq_9_io OE ) + USE SIGNAL ; + - core_ddr_dqs_n_0_i ( u_ddr_dqs_n_0_io Y ) + USE SIGNAL ; + - core_ddr_dqs_n_0_o ( u_ddr_dqs_n_0_io A ) + USE SIGNAL ; + - core_ddr_dqs_n_0_sel ( u_ddr_dqs_n_0_io PU ) ( u_ddr_dqs_n_0_io OE ) + USE SIGNAL ; + - core_ddr_dqs_n_1_i ( u_ddr_dqs_n_1_io Y ) + USE SIGNAL ; + - core_ddr_dqs_n_1_o ( u_ddr_dqs_n_1_io A ) + USE SIGNAL ; + - core_ddr_dqs_n_1_sel ( u_ddr_dqs_n_1_io PU ) ( u_ddr_dqs_n_1_io OE ) + USE SIGNAL ; + - core_ddr_dqs_n_2_i ( u_ddr_dqs_n_2_io Y ) + USE SIGNAL ; + - core_ddr_dqs_n_2_o ( u_ddr_dqs_n_2_io A ) + USE SIGNAL ; + - core_ddr_dqs_n_2_sel ( u_ddr_dqs_n_2_io PU ) ( u_ddr_dqs_n_2_io OE ) + USE SIGNAL ; + - core_ddr_dqs_n_3_i ( u_ddr_dqs_n_3_io Y ) + USE SIGNAL ; + - core_ddr_dqs_n_3_o ( u_ddr_dqs_n_3_io A ) + USE SIGNAL ; + - core_ddr_dqs_n_3_sel ( u_ddr_dqs_n_3_io PU ) ( u_ddr_dqs_n_3_io OE ) + USE SIGNAL ; + - core_ddr_dqs_p_0_i ( u_ddr_dqs_p_0_io Y ) + USE SIGNAL ; + - core_ddr_dqs_p_0_o ( u_ddr_dqs_p_0_io A ) + USE SIGNAL ; + - core_ddr_dqs_p_0_sel ( u_ddr_dqs_p_0_io PU ) ( u_ddr_dqs_p_0_io OE ) + USE SIGNAL ; + - core_ddr_dqs_p_1_i ( u_ddr_dqs_p_1_io Y ) + USE SIGNAL ; + - core_ddr_dqs_p_1_o ( u_ddr_dqs_p_1_io A ) + USE SIGNAL ; + - core_ddr_dqs_p_1_sel ( u_ddr_dqs_p_1_io PU ) ( u_ddr_dqs_p_1_io OE ) + USE SIGNAL ; + - core_ddr_dqs_p_2_i ( u_ddr_dqs_p_2_io Y ) + USE SIGNAL ; + - core_ddr_dqs_p_2_o ( u_ddr_dqs_p_2_io A ) + USE SIGNAL ; + - core_ddr_dqs_p_2_sel ( u_ddr_dqs_p_2_io PU ) ( u_ddr_dqs_p_2_io OE ) + USE SIGNAL ; + - core_ddr_dqs_p_3_i ( u_ddr_dqs_p_3_io Y ) + USE SIGNAL ; + - core_ddr_dqs_p_3_o ( u_ddr_dqs_p_3_io A ) + USE SIGNAL ; + - core_ddr_dqs_p_3_sel ( u_ddr_dqs_p_3_io PU ) ( u_ddr_dqs_p_3_io OE ) + USE SIGNAL ; + - core_ddr_odt_o ( u_ddr_odt_o A ) + USE SIGNAL ; + - core_ddr_ras_n_o ( u_ddr_ras_n_o A ) + USE SIGNAL ; + - core_ddr_reset_n_o ( u_ddr_reset_n_o A ) + USE SIGNAL ; + - core_ddr_we_n_o ( u_ddr_we_n_o A ) + USE SIGNAL ; + - core_misc_o ( u_misc_o A ) + USE SIGNAL ; + - core_sel_0_i ( u_sel_0_i Y ) + USE SIGNAL ; + - core_sel_1_i ( u_sel_1_i Y ) + USE SIGNAL ; + - core_sel_2_i ( u_sel_2_i Y ) + USE SIGNAL ; + - p_bsg_tag_clk_i ( PIN p_bsg_tag_clk_i ) ( u_bsg_tag_clk_i PAD ) + USE SIGNAL ; + - p_bsg_tag_clk_o ( PIN p_bsg_tag_clk_o ) ( u_bsg_tag_clk_o PAD ) + USE SIGNAL ; + - p_bsg_tag_data_i ( PIN p_bsg_tag_data_i ) ( u_bsg_tag_data_i PAD ) + USE SIGNAL ; + - p_bsg_tag_data_o ( PIN p_bsg_tag_data_o ) ( u_bsg_tag_data_o PAD ) + USE SIGNAL ; + - p_bsg_tag_en_i ( PIN p_bsg_tag_en_i ) ( u_bsg_tag_en_i PAD ) + USE SIGNAL ; + - p_ci2_0_o ( PIN p_ci2_0_o ) ( u_ci2_0_o PAD ) + USE SIGNAL ; + - p_ci2_1_o ( PIN p_ci2_1_o ) ( u_ci2_1_o PAD ) + USE SIGNAL ; + - p_ci2_2_o ( PIN p_ci2_2_o ) ( u_ci2_2_o PAD ) + USE SIGNAL ; + - p_ci2_3_o ( PIN p_ci2_3_o ) ( u_ci2_3_o PAD ) + USE SIGNAL ; + - p_ci2_4_o ( PIN p_ci2_4_o ) ( u_ci2_4_o PAD ) + USE SIGNAL ; + - p_ci2_5_o ( PIN p_ci2_5_o ) ( u_ci2_5_o PAD ) + USE SIGNAL ; + - p_ci2_6_o ( PIN p_ci2_6_o ) ( u_ci2_6_o PAD ) + USE SIGNAL ; + - p_ci2_7_o ( PIN p_ci2_7_o ) ( u_ci2_7_o PAD ) + USE SIGNAL ; + - p_ci2_8_o ( PIN p_ci2_8_o ) ( u_ci2_8_o PAD ) + USE SIGNAL ; + - p_ci2_clk_o ( PIN p_ci2_clk_o ) ( u_ci2_clk_o PAD ) + USE SIGNAL ; + - p_ci2_tkn_i ( PIN p_ci2_tkn_i ) ( u_ci2_tkn_i PAD ) + USE SIGNAL ; + - p_ci2_v_o ( PIN p_ci2_v_o ) ( u_ci2_v_o PAD ) + USE SIGNAL ; + - p_ci_0_i ( PIN p_ci_0_i ) ( u_ci_0_i PAD ) + USE SIGNAL ; + - p_ci_1_i ( PIN p_ci_1_i ) ( u_ci_1_i PAD ) + USE SIGNAL ; + - p_ci_2_i ( PIN p_ci_2_i ) ( u_ci_2_i PAD ) + USE SIGNAL ; + - p_ci_3_i ( PIN p_ci_3_i ) ( u_ci_3_i PAD ) + USE SIGNAL ; + - p_ci_4_i ( PIN p_ci_4_i ) ( u_ci_4_i PAD ) + USE SIGNAL ; + - p_ci_5_i ( PIN p_ci_5_i ) ( u_ci_5_i PAD ) + USE SIGNAL ; + - p_ci_6_i ( PIN p_ci_6_i ) ( u_ci_6_i PAD ) + USE SIGNAL ; + - p_ci_7_i ( PIN p_ci_7_i ) ( u_ci_7_i PAD ) + USE SIGNAL ; + - p_ci_8_i ( PIN p_ci_8_i ) ( u_ci_8_i PAD ) + USE SIGNAL ; + - p_ci_clk_i ( PIN p_ci_clk_i ) ( u_ci_clk_i PAD ) + USE SIGNAL ; + - p_ci_tkn_o ( PIN p_ci_tkn_o ) ( u_ci_tkn_o PAD ) + USE SIGNAL ; + - p_ci_v_i ( PIN p_ci_v_i ) ( u_ci_v_i PAD ) + USE SIGNAL ; + - p_clk_A_i ( PIN p_clk_A_i ) ( u_clk_A_i PAD ) + USE SIGNAL ; + - p_clk_B_i ( PIN p_clk_B_i ) ( u_clk_B_i PAD ) + USE SIGNAL ; + - p_clk_C_i ( PIN p_clk_C_i ) ( u_clk_C_i PAD ) + USE SIGNAL ; + - p_clk_async_reset_i ( PIN p_clk_async_reset_i ) ( u_clk_async_reset_i PAD ) + USE SIGNAL ; + - p_clk_o ( PIN p_clk_o ) ( u_clk_o PAD ) + USE SIGNAL ; + - p_co2_0_o ( PIN p_co2_0_o ) ( u_co2_0_o PAD ) + USE SIGNAL ; + - p_co2_1_o ( PIN p_co2_1_o ) ( u_co2_1_o PAD ) + USE SIGNAL ; + - p_co2_2_o ( PIN p_co2_2_o ) ( u_co2_2_o PAD ) + USE SIGNAL ; + - p_co2_3_o ( PIN p_co2_3_o ) ( u_co2_3_o PAD ) + USE SIGNAL ; + - p_co2_4_o ( PIN p_co2_4_o ) ( u_co2_4_o PAD ) + USE SIGNAL ; + - p_co2_5_o ( PIN p_co2_5_o ) ( u_co2_5_o PAD ) + USE SIGNAL ; + - p_co2_6_o ( PIN p_co2_6_o ) ( u_co2_6_o PAD ) + USE SIGNAL ; + - p_co2_7_o ( PIN p_co2_7_o ) ( u_co2_7_o PAD ) + USE SIGNAL ; + - p_co2_8_o ( PIN p_co2_8_o ) ( u_co2_8_o PAD ) + USE SIGNAL ; + - p_co2_clk_o ( PIN p_co2_clk_o ) ( u_co2_clk_o PAD ) + USE SIGNAL ; + - p_co2_tkn_i ( PIN p_co2_tkn_i ) ( u_co2_tkn_i PAD ) + USE SIGNAL ; + - p_co2_v_o ( PIN p_co2_v_o ) ( u_co2_v_o PAD ) + USE SIGNAL ; + - p_co_0_i ( PIN p_co_0_i ) ( u_co_0_i PAD ) + USE SIGNAL ; + - p_co_1_i ( PIN p_co_1_i ) ( u_co_1_i PAD ) + USE SIGNAL ; + - p_co_2_i ( PIN p_co_2_i ) ( u_co_2_i PAD ) + USE SIGNAL ; + - p_co_3_i ( PIN p_co_3_i ) ( u_co_3_i PAD ) + USE SIGNAL ; + - p_co_4_i ( PIN p_co_4_i ) ( u_co_4_i PAD ) + USE SIGNAL ; + - p_co_5_i ( PIN p_co_5_i ) ( u_co_5_i PAD ) + USE SIGNAL ; + - p_co_6_i ( PIN p_co_6_i ) ( u_co_6_i PAD ) + USE SIGNAL ; + - p_co_7_i ( PIN p_co_7_i ) ( u_co_7_i PAD ) + USE SIGNAL ; + - p_co_8_i ( PIN p_co_8_i ) ( u_co_8_i PAD ) + USE SIGNAL ; + - p_co_clk_i ( PIN p_co_clk_i ) ( u_co_clk_i PAD ) + USE SIGNAL ; + - p_co_tkn_o ( PIN p_co_tkn_o ) ( u_co_tkn_o PAD ) + USE SIGNAL ; + - p_co_v_i ( PIN p_co_v_i ) ( u_co_v_i PAD ) + USE SIGNAL ; + - p_core_async_reset_i ( PIN p_core_async_reset_i ) ( u_core_async_reset_i PAD ) + USE SIGNAL ; + - p_ddr_addr_0_o ( PIN p_ddr_addr_0_o ) ( u_ddr_addr_0_o PAD ) + USE SIGNAL ; + - p_ddr_addr_10_o ( PIN p_ddr_addr_10_o ) ( u_ddr_addr_10_o PAD ) + USE SIGNAL ; + - p_ddr_addr_11_o ( PIN p_ddr_addr_11_o ) ( u_ddr_addr_11_o PAD ) + USE SIGNAL ; + - p_ddr_addr_12_o ( PIN p_ddr_addr_12_o ) ( u_ddr_addr_12_o PAD ) + USE SIGNAL ; + - p_ddr_addr_13_o ( PIN p_ddr_addr_13_o ) ( u_ddr_addr_13_o PAD ) + USE SIGNAL ; + - p_ddr_addr_14_o ( PIN p_ddr_addr_14_o ) ( u_ddr_addr_14_o PAD ) + USE SIGNAL ; + - p_ddr_addr_15_o ( PIN p_ddr_addr_15_o ) ( u_ddr_addr_15_o PAD ) + USE SIGNAL ; + - p_ddr_addr_1_o ( PIN p_ddr_addr_1_o ) ( u_ddr_addr_1_o PAD ) + USE SIGNAL ; + - p_ddr_addr_2_o ( PIN p_ddr_addr_2_o ) ( u_ddr_addr_2_o PAD ) + USE SIGNAL ; + - p_ddr_addr_3_o ( PIN p_ddr_addr_3_o ) ( u_ddr_addr_3_o PAD ) + USE SIGNAL ; + - p_ddr_addr_4_o ( PIN p_ddr_addr_4_o ) ( u_ddr_addr_4_o PAD ) + USE SIGNAL ; + - p_ddr_addr_5_o ( PIN p_ddr_addr_5_o ) ( u_ddr_addr_5_o PAD ) + USE SIGNAL ; + - p_ddr_addr_6_o ( PIN p_ddr_addr_6_o ) ( u_ddr_addr_6_o PAD ) + USE SIGNAL ; + - p_ddr_addr_7_o ( PIN p_ddr_addr_7_o ) ( u_ddr_addr_7_o PAD ) + USE SIGNAL ; + - p_ddr_addr_8_o ( PIN p_ddr_addr_8_o ) ( u_ddr_addr_8_o PAD ) + USE SIGNAL ; + - p_ddr_addr_9_o ( PIN p_ddr_addr_9_o ) ( u_ddr_addr_9_o PAD ) + USE SIGNAL ; + - p_ddr_ba_0_o ( PIN p_ddr_ba_0_o ) ( u_ddr_ba_0_o PAD ) + USE SIGNAL ; + - p_ddr_ba_1_o ( PIN p_ddr_ba_1_o ) ( u_ddr_ba_1_o PAD ) + USE SIGNAL ; + - p_ddr_ba_2_o ( PIN p_ddr_ba_2_o ) ( u_ddr_ba_2_o PAD ) + USE SIGNAL ; + - p_ddr_cas_n_o ( PIN p_ddr_cas_n_o ) ( u_ddr_cas_n_o PAD ) + USE SIGNAL ; + - p_ddr_ck_n_o ( PIN p_ddr_ck_n_o ) ( u_ddr_ck_n_o PAD ) + USE SIGNAL ; + - p_ddr_ck_p_o ( PIN p_ddr_ck_p_o ) ( u_ddr_ck_p_o PAD ) + USE SIGNAL ; + - p_ddr_cke_o ( PIN p_ddr_cke_o ) ( u_ddr_cke_o PAD ) + USE SIGNAL ; + - p_ddr_cs_n_o ( PIN p_ddr_cs_n_o ) ( u_ddr_cs_n_o PAD ) + USE SIGNAL ; + - p_ddr_dm_0_o ( PIN p_ddr_dm_0_o ) ( u_ddr_dm_0_o PAD ) + USE SIGNAL ; + - p_ddr_dm_1_o ( PIN p_ddr_dm_1_o ) ( u_ddr_dm_1_o PAD ) + USE SIGNAL ; + - p_ddr_dm_2_o ( PIN p_ddr_dm_2_o ) ( u_ddr_dm_2_o PAD ) + USE SIGNAL ; + - p_ddr_dm_3_o ( PIN p_ddr_dm_3_o ) ( u_ddr_dm_3_o PAD ) + USE SIGNAL ; + - p_ddr_dq_0_io ( PIN p_ddr_dq_0_io ) ( u_ddr_dq_0_io PAD ) + USE SIGNAL ; + - p_ddr_dq_10_io ( PIN p_ddr_dq_10_io ) ( u_ddr_dq_10_io PAD ) + USE SIGNAL ; + - p_ddr_dq_11_io ( PIN p_ddr_dq_11_io ) ( u_ddr_dq_11_io PAD ) + USE SIGNAL ; + - p_ddr_dq_12_io ( PIN p_ddr_dq_12_io ) ( u_ddr_dq_12_io PAD ) + USE SIGNAL ; + - p_ddr_dq_13_io ( PIN p_ddr_dq_13_io ) ( u_ddr_dq_13_io PAD ) + USE SIGNAL ; + - p_ddr_dq_14_io ( PIN p_ddr_dq_14_io ) ( u_ddr_dq_14_io PAD ) + USE SIGNAL ; + - p_ddr_dq_15_io ( PIN p_ddr_dq_15_io ) ( u_ddr_dq_15_io PAD ) + USE SIGNAL ; + - p_ddr_dq_16_io ( PIN p_ddr_dq_16_io ) ( u_ddr_dq_16_io PAD ) + USE SIGNAL ; + - p_ddr_dq_17_io ( PIN p_ddr_dq_17_io ) ( u_ddr_dq_17_io PAD ) + USE SIGNAL ; + - p_ddr_dq_18_io ( PIN p_ddr_dq_18_io ) ( u_ddr_dq_18_io PAD ) + USE SIGNAL ; + - p_ddr_dq_19_io ( PIN p_ddr_dq_19_io ) ( u_ddr_dq_19_io PAD ) + USE SIGNAL ; + - p_ddr_dq_1_io ( PIN p_ddr_dq_1_io ) ( u_ddr_dq_1_io PAD ) + USE SIGNAL ; + - p_ddr_dq_20_io ( PIN p_ddr_dq_20_io ) ( u_ddr_dq_20_io PAD ) + USE SIGNAL ; + - p_ddr_dq_21_io ( PIN p_ddr_dq_21_io ) ( u_ddr_dq_21_io PAD ) + USE SIGNAL ; + - p_ddr_dq_22_io ( PIN p_ddr_dq_22_io ) ( u_ddr_dq_22_io PAD ) + USE SIGNAL ; + - p_ddr_dq_23_io ( PIN p_ddr_dq_23_io ) ( u_ddr_dq_23_io PAD ) + USE SIGNAL ; + - p_ddr_dq_24_io ( PIN p_ddr_dq_24_io ) ( u_ddr_dq_24_io PAD ) + USE SIGNAL ; + - p_ddr_dq_25_io ( PIN p_ddr_dq_25_io ) ( u_ddr_dq_25_io PAD ) + USE SIGNAL ; + - p_ddr_dq_26_io ( PIN p_ddr_dq_26_io ) ( u_ddr_dq_26_io PAD ) + USE SIGNAL ; + - p_ddr_dq_27_io ( PIN p_ddr_dq_27_io ) ( u_ddr_dq_27_io PAD ) + USE SIGNAL ; + - p_ddr_dq_28_io ( PIN p_ddr_dq_28_io ) ( u_ddr_dq_28_io PAD ) + USE SIGNAL ; + - p_ddr_dq_29_io ( PIN p_ddr_dq_29_io ) ( u_ddr_dq_29_io PAD ) + USE SIGNAL ; + - p_ddr_dq_2_io ( PIN p_ddr_dq_2_io ) ( u_ddr_dq_2_io PAD ) + USE SIGNAL ; + - p_ddr_dq_30_io ( PIN p_ddr_dq_30_io ) ( u_ddr_dq_30_io PAD ) + USE SIGNAL ; + - p_ddr_dq_31_io ( PIN p_ddr_dq_31_io ) ( u_ddr_dq_31_io PAD ) + USE SIGNAL ; + - p_ddr_dq_3_io ( PIN p_ddr_dq_3_io ) ( u_ddr_dq_3_io PAD ) + USE SIGNAL ; + - p_ddr_dq_4_io ( PIN p_ddr_dq_4_io ) ( u_ddr_dq_4_io PAD ) + USE SIGNAL ; + - p_ddr_dq_5_io ( PIN p_ddr_dq_5_io ) ( u_ddr_dq_5_io PAD ) + USE SIGNAL ; + - p_ddr_dq_6_io ( PIN p_ddr_dq_6_io ) ( u_ddr_dq_6_io PAD ) + USE SIGNAL ; + - p_ddr_dq_7_io ( PIN p_ddr_dq_7_io ) ( u_ddr_dq_7_io PAD ) + USE SIGNAL ; + - p_ddr_dq_8_io ( PIN p_ddr_dq_8_io ) ( u_ddr_dq_8_io PAD ) + USE SIGNAL ; + - p_ddr_dq_9_io ( PIN p_ddr_dq_9_io ) ( u_ddr_dq_9_io PAD ) + USE SIGNAL ; + - p_ddr_dqs_n_0_io ( PIN p_ddr_dqs_n_0_io ) ( u_ddr_dqs_n_0_io PAD ) + USE SIGNAL ; + - p_ddr_dqs_n_1_io ( PIN p_ddr_dqs_n_1_io ) ( u_ddr_dqs_n_1_io PAD ) + USE SIGNAL ; + - p_ddr_dqs_n_2_io ( PIN p_ddr_dqs_n_2_io ) ( u_ddr_dqs_n_2_io PAD ) + USE SIGNAL ; + - p_ddr_dqs_n_3_io ( PIN p_ddr_dqs_n_3_io ) ( u_ddr_dqs_n_3_io PAD ) + USE SIGNAL ; + - p_ddr_dqs_p_0_io ( PIN p_ddr_dqs_p_0_io ) ( u_ddr_dqs_p_0_io PAD ) + USE SIGNAL ; + - p_ddr_dqs_p_1_io ( PIN p_ddr_dqs_p_1_io ) ( u_ddr_dqs_p_1_io PAD ) + USE SIGNAL ; + - p_ddr_dqs_p_2_io ( PIN p_ddr_dqs_p_2_io ) ( u_ddr_dqs_p_2_io PAD ) + USE SIGNAL ; + - p_ddr_dqs_p_3_io ( PIN p_ddr_dqs_p_3_io ) ( u_ddr_dqs_p_3_io PAD ) + USE SIGNAL ; + - p_ddr_odt_o ( PIN p_ddr_odt_o ) ( u_ddr_odt_o PAD ) + USE SIGNAL ; + - p_ddr_ras_n_o ( PIN p_ddr_ras_n_o ) ( u_ddr_ras_n_o PAD ) + USE SIGNAL ; + - p_ddr_reset_n_o ( PIN p_ddr_reset_n_o ) ( u_ddr_reset_n_o PAD ) + USE SIGNAL ; + - p_ddr_we_n_o ( PIN p_ddr_we_n_o ) ( u_ddr_we_n_o PAD ) + USE SIGNAL ; + - p_misc_o ( PIN p_misc_o ) ( u_misc_o PAD ) + USE SIGNAL ; + - p_sel_0_i ( PIN p_sel_0_i ) ( u_sel_0_i PAD ) + USE SIGNAL ; + - p_sel_1_i ( PIN p_sel_1_i ) ( u_sel_1_i PAD ) + USE SIGNAL ; + - p_sel_2_i ( PIN p_sel_2_i ) ( u_sel_2_i PAD ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/src/pad/test/bump_array_make_single_pitch.ok b/src/pad/test/bump_array_make_single_pitch.ok new file mode 100644 index 0000000000..b136b8e200 --- /dev/null +++ b/src/pad/test/bump_array_make_single_pitch.ok @@ -0,0 +1,7 @@ +[INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells +[INFO ODB-0227] LEF file: Nangate45_io/dummy_pads.lef, created 24 library cells +[INFO ODB-0128] Design: soc_bsg_black_parrot +[INFO ODB-0130] Created 135 pins. +[INFO ODB-0131] Created 267 components and 2277 component-terminals. +[INFO ODB-0133] Created 350 nets and 390 connections. +No differences found. diff --git a/src/pad/test/bump_array_make_single_pitch.tcl b/src/pad/test/bump_array_make_single_pitch.tcl new file mode 100644 index 0000000000..47138a70cd --- /dev/null +++ b/src/pad/test/bump_array_make_single_pitch.tcl @@ -0,0 +1,15 @@ +# Test for building bump array with a gingle pitch defined +source "helpers.tcl" + +# Init chip +read_lef Nangate45/Nangate45.lef +read_lef Nangate45_io/dummy_pads.lef + +read_def Nangate45_blackparrot/floorplan.def + +# Test make_io_bump_array +make_io_bump_array -bump DUMMY_BUMP -origin "200 200" -rows 14 -columns 14 -pitch "200" + +set def_file [make_result_file "bump_array_make_single_pitch.def"] +write_def $def_file +diff_files $def_file "bump_array_make_single_pitch.defok" diff --git a/src/pad/test/regression_tests.tcl b/src/pad/test/regression_tests.tcl index 335f28c9d3..5566933068 100644 --- a/src/pad/test/regression_tests.tcl +++ b/src/pad/test/regression_tests.tcl @@ -2,6 +2,8 @@ record_tests { bump_array_make bump_array_remove bump_array_remove_single + bump_array_make_single_pitch + bump_array_make_error make_corner_sites make_io_sites From f3aaa4f48c83b6afdc62801d07c35fc9e6247323 Mon Sep 17 00:00:00 2001 From: Matt Liberty Date: Mon, 5 Aug 2024 11:57:57 -0700 Subject: [PATCH 32/37] gpl: misc update to debug graphic - Draw all of nbVec & pbVec elements, not just the first or common - Draw out of range bins in orange - Hide force lines when zoomed far out Signed-off-by: Matt Liberty --- src/gpl/src/graphics.cpp | 111 +++++++++++++++++++++++++-------------- src/gpl/src/graphics.h | 3 ++ 2 files changed, 75 insertions(+), 39 deletions(-) diff --git a/src/gpl/src/graphics.cpp b/src/gpl/src/graphics.cpp index b785d836b1..76095cbdd3 100644 --- a/src/gpl/src/graphics.cpp +++ b/src/gpl/src/graphics.cpp @@ -155,28 +155,47 @@ void Graphics::drawInitial(gui::Painter& painter) } } -void Graphics::drawNesterov(gui::Painter& painter) +void Graphics::drawForce(gui::Painter& painter) { - // TODO: Support graphics for multiple Nesterov instances - drawBounds(painter); - if (draw_bins_) { - // Draw the bins - painter.setPen(gui::Painter::white, /* cosmetic */ true); + for (const auto& nb : nbVec_) { + const auto& bins = nb->bins(); + if (bins.empty()) { + continue; + } + const auto& bin = *bins.begin(); + const auto size = std::max(bin.dx(), bin.dy()); + if (size * painter.getPixelsPerDBU() < 10) { // too small + return; + } + float efMax = 0; + int max_len = std::numeric_limits::max(); + for (auto& bin : bins) { + efMax = std::max(efMax, + std::hypot(bin.electroForceX(), bin.electroForceY())); + max_len = std::min({max_len, bin.dx(), bin.dy()}); + } - for (auto& bin : nbVec_[0]->bins()) { - int color = bin.density() * 50 + 20; + for (auto& bin : bins) { + float fx = bin.electroForceX(); + float fy = bin.electroForceY(); + float f = std::hypot(fx, fy); + float ratio = f / efMax; + float dx = fx / f * max_len * ratio; + float dy = fy / f * max_len * ratio; - color = (color > 255) ? 255 : (color < 20) ? 20 : color; - color = 255 - color; + int cx = bin.cx(); + int cy = bin.cy(); - painter.setBrush({color, color, color, 180}); - painter.drawRect({bin.lx(), bin.ly(), bin.ux(), bin.uy()}); + painter.setPen(gui::Painter::red, true); + painter.drawLine(cx, cy, cx + dx, cy + dy); } } +} - // Draw the placeable objects - painter.setPen(gui::Painter::white); - for (auto* gCell : nbc_->gCells()) { +void Graphics::drawCells(const std::vector& cells, + gui::Painter& painter) +{ + for (auto* gCell : cells) { const int gcx = gCell->dCx(); const int gcy = gCell->dCy(); @@ -192,6 +211,7 @@ void Graphics::drawNesterov(gui::Painter& painter) } else if (gCell->isFiller()) { color = gui::Painter::dark_magenta; } + if (gCell == selected_) { color = gui::Painter::yellow; } @@ -200,10 +220,44 @@ void Graphics::drawNesterov(gui::Painter& painter) painter.setBrush(color); painter.drawRect({xl, yl, xh, yh}); } +} + +void Graphics::drawNesterov(gui::Painter& painter) +{ + drawBounds(painter); + if (draw_bins_) { + // Draw the bins + painter.setPen(gui::Painter::transparent); + + for (const auto& nb : nbVec_) { + for (auto& bin : nb->bins()) { + int density = bin.density() * 50 + 20; + gui::Painter::Color color; + if (density > 255) { + color = {255, 165, 0, 180}; // orange = out of the range + } else { + density = 255 - std::max(density, 20); + color = {density, density, density, 180}; + } + + painter.setBrush(color); + painter.drawRect({bin.lx(), bin.ly(), bin.ux(), bin.uy()}); + } + } + } + + // Draw the placeable objects + painter.setPen(gui::Painter::white); + drawCells(nbc_->gCells(), painter); + for (const auto& nb : nbVec_) { + drawCells(nb->gCells(), painter); + } painter.setBrush(gui::Painter::Color(gui::Painter::light_gray, 50)); - for (auto& inst : pbVec_[0]->nonPlaceInsts()) { - painter.drawRect({inst->lx(), inst->ly(), inst->ux(), inst->uy()}); + for (const auto& pb : pbVec_) { + for (auto& inst : pb->nonPlaceInsts()) { + painter.drawRect({inst->lx(), inst->ly(), inst->ux(), inst->uy()}); + } } // Draw lines to neighbors @@ -227,28 +281,7 @@ void Graphics::drawNesterov(gui::Painter& painter) // Draw force direction lines if (draw_bins_) { - float efMax = 0; - int max_len = std::numeric_limits::max(); - for (auto& bin : nbVec_[0]->bins()) { - efMax = std::max(efMax, - std::hypot(bin.electroForceX(), bin.electroForceY())); - max_len = std::min({max_len, bin.dx(), bin.dy()}); - } - - for (auto& bin : nbVec_[0]->bins()) { - float fx = bin.electroForceX(); - float fy = bin.electroForceY(); - float f = std::hypot(fx, fy); - float ratio = f / efMax; - float dx = fx / f * max_len * ratio; - float dy = fy / f * max_len * ratio; - - int cx = bin.cx(); - int cy = bin.cy(); - - painter.setPen(gui::Painter::red, true); - painter.drawLine(cx, cy, cx + dx, cy + dy); - } + drawForce(painter); } } diff --git a/src/gpl/src/graphics.h b/src/gpl/src/graphics.h index 175463004a..c317c71c02 100644 --- a/src/gpl/src/graphics.h +++ b/src/gpl/src/graphics.h @@ -121,6 +121,9 @@ class Graphics : public gui::Renderer, public gui::HeatMapDataSource Nesterov }; + void drawForce(gui::Painter& painter); + void drawCells(const std::vector& cells, gui::Painter& painter); + std::shared_ptr pbc_; std::shared_ptr nbc_; std::vector> pbVec_; From 5172fe49f25526e9a6f124b499950748511e3b47 Mon Sep 17 00:00:00 2001 From: osamahammad21 Date: Mon, 5 Aug 2024 22:02:37 +0300 Subject: [PATCH 33/37] drt: clarification Signed-off-by: osamahammad21 --- src/drt/src/io/io.cpp | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/src/drt/src/io/io.cpp b/src/drt/src/io/io.cpp index 56ab2c53dc..ea76dbeefe 100644 --- a/src/drt/src/io/io.cpp +++ b/src/drt/src/io/io.cpp @@ -387,6 +387,15 @@ void io::Parser::setVias(odb::dbBlock* block) } } +namespace { +// Convert frLayerNum to zero-based routing layer index.(ignoring non-routing +// layers) +inline frMIdx getZIdx(frLayerNum lNum) +{ + return lNum / 2 - 1; +} +} // namespace + void io::Parser::createNDR(odb::dbTechNonDefaultRule* ndr) { if (design_->tech_->getNondefaultRule(ndr->getName())) { @@ -408,8 +417,8 @@ void io::Parser::createNDR(odb::dbTechNonDefaultRule* ndr) std::vector lr; ndr->getLayerRules(lr); for (auto& l : lr) { - z = design_->tech_->getLayer(l->getLayer()->getName())->getLayerNum() / 2 - - 1; + auto layer = tech_->getLayer(l->getLayer()->getName()); + z = getZIdx(layer->getLayerNum()); fnd->setWidth(l->getWidth(), z); fnd->setSpacing(l->getSpacing(), z); fnd->setWireExtension(l->getWireExtension(), z); @@ -417,11 +426,9 @@ void io::Parser::createNDR(odb::dbTechNonDefaultRule* ndr) std::vector vias; ndr->getUseVias(vias); for (auto via : vias) { - z = design_->tech_->getLayer(via->getBottomLayer()->getName()) - ->getLayerNum() - / 2 - - 1; - fnd->addVia(design_->getTech()->getVia(via->getName()), z); + auto layer = tech_->getLayer(via->getBottomLayer()->getName()); + z = getZIdx(layer->getLayerNum()); + fnd->addVia(tech_->getVia(via->getName()), z); } std::vector viaRules; ndr->getUseViaRules(viaRules); @@ -454,7 +461,7 @@ void io::Parser::setNDRs(odb::dbDatabase* db) } MTSAFEDIST = std::max(MTSAFEDIST, design_->getTech()->getMaxNondefaultSpacing( - layer->getLayerNum() / 2 - 1)); + getZIdx(layer->getLayerNum()))); } } From 3cef027826a2219966cc7a4fe0d9252988b682ce Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Mon, 5 Aug 2024 15:12:28 -0400 Subject: [PATCH 34/37] dft: correct test to avoid generating stray file Signed-off-by: Peter Gadfort --- src/dft/test/scandef_core_sky130.tcl | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/dft/test/scandef_core_sky130.tcl b/src/dft/test/scandef_core_sky130.tcl index 0cf628e310..99f72acc64 100644 --- a/src/dft/test/scandef_core_sky130.tcl +++ b/src/dft/test/scandef_core_sky130.tcl @@ -9,5 +9,7 @@ read_verilog scan_inserted_register_bank.v link_design top -hier read_def -incremental scandef_core_sky130.scandef -write_def scandef_core_sky130.out.def -diff_files scandef_core_sky130.out.def scandef_core_sky130.defok + +set def_file [make_result_file scandef_core_sky130.out.def] +write_def $def_file +diff_files $def_file scandef_core_sky130.defok From 7d7cc3511ff476d84adffeecebeb3f5efb9e515a Mon Sep 17 00:00:00 2001 From: andyfox-rushc Date: Mon, 5 Aug 2024 17:22:13 -0700 Subject: [PATCH 35/37] Removed next/prev interface from dbModBTerm, reduced to just next. Signed-off-by: Andy Fox. andy@rushc.com Signed-off-by: andyfox-rushc --- src/odb/include/odb/db.h | 6 +-- .../codeGenerator/schema/chip/dbModBterm.json | 7 ---- src/odb/src/db/dbBusPort.cpp | 14 +++---- src/odb/src/db/dbModBTerm.cpp | 39 ------------------- src/odb/src/db/dbModBTerm.h | 1 - 5 files changed, 8 insertions(+), 59 deletions(-) diff --git a/src/odb/include/odb/db.h b/src/odb/include/odb/db.h index 61cc66f6d0..04b4ef0fdb 100644 --- a/src/odb/include/odb/db.h +++ b/src/odb/include/odb/db.h @@ -7168,10 +7168,9 @@ class dbBusPort : public dbObject // User Code Begin dbBusPort // get element by bit index in bus (allows for up/down) // linear access - dbModBTerm* getBusIndexedElement(int index) const; + dbModBTerm* getBusIndexedElement(int index); void setFirstMember(dbModBTerm*); dbModBTerm* getFirstMember(); - dbSet getBusPortMembers(); int getSize() const; bool getUpdown() const; @@ -7605,9 +7604,6 @@ class dbModBTerm : public dbObject bool isBusPort() const; void setBusPort(dbBusPort*); dbBusPort* getBusPort() const; - dbModBTerm* getNext() const; - dbModBTerm* getPrev() const; - static dbModBTerm* create(dbModule* parentModule, const char* name); private: diff --git a/src/odb/src/codeGenerator/schema/chip/dbModBterm.json b/src/odb/src/codeGenerator/schema/chip/dbModBterm.json index ec040a9ed9..e6d9c974f4 100644 --- a/src/odb/src/codeGenerator/schema/chip/dbModBterm.json +++ b/src/odb/src/codeGenerator/schema/chip/dbModBterm.json @@ -64,13 +64,6 @@ "flags":["private"], "schema":"db_schema_update_hierarchy", "parent":"dbBlock" - }, - { - "name":"_prev_entry", - "type":"dbId<_dbModBTerm>", - "flags":["private"], - "schema":"db_schema_odb_busport", - "parent":"dbBlock" } ], "constructors":[], diff --git a/src/odb/src/db/dbBusPort.cpp b/src/odb/src/db/dbBusPort.cpp index bf26c1670b..af30027235 100644 --- a/src/odb/src/db/dbBusPort.cpp +++ b/src/odb/src/db/dbBusPort.cpp @@ -267,7 +267,7 @@ dbModule* dbBusPort::getParent() const element is at offset 1 in the array b[5:1] element is at offset 4 in the array */ -dbModBTerm* dbBusPort::getBusIndexedElement(int index) const +dbModBTerm* dbBusPort::getBusIndexedElement(int index) { _dbBusPort* obj = (_dbBusPort*) this; _dbBlock* block_ = (_dbBlock*) obj->getOwner(); @@ -290,13 +290,13 @@ dbModBTerm* dbBusPort::getBusIndexedElement(int index) const return (dbModBTerm*) (block_->_modbterm_tbl->getPtr(obj->getId() + offset + 1)); } - dbModBTerm* cur = (dbModBTerm*) (block_->_modbterm_tbl->getPtr(obj->_port)); - if (cur != nullptr) { - cur = cur->getPrev(); - for (int i = 0; i < offset; i++) { - cur = cur->getPrev(); + int i = 0; + dbSet busport_members = getBusPortMembers(); + for (auto cur : busport_members) { + if (i == offset) { + return cur; } - return cur; + i++; } } return nullptr; diff --git a/src/odb/src/db/dbModBTerm.cpp b/src/odb/src/db/dbModBTerm.cpp index 650e9eccc0..0423deee57 100644 --- a/src/odb/src/db/dbModBTerm.cpp +++ b/src/odb/src/db/dbModBTerm.cpp @@ -76,9 +76,6 @@ bool _dbModBTerm::operator==(const _dbModBTerm& rhs) const if (_next_entry != rhs._next_entry) { return false; } - if (_prev_entry != rhs._prev_entry) { - return false; - } return true; } @@ -102,7 +99,6 @@ void _dbModBTerm::differences(dbDiff& diff, DIFF_FIELD(_prev_net_modbterm); DIFF_FIELD(_busPort); DIFF_FIELD(_next_entry); - DIFF_FIELD(_prev_entry); DIFF_END } @@ -118,7 +114,6 @@ void _dbModBTerm::out(dbDiff& diff, char side, const char* field) const DIFF_OUT_FIELD(_prev_net_modbterm); DIFF_OUT_FIELD(_busPort); DIFF_OUT_FIELD(_next_entry); - DIFF_OUT_FIELD(_prev_entry); DIFF_END } @@ -140,7 +135,6 @@ _dbModBTerm::_dbModBTerm(_dbDatabase* db, const _dbModBTerm& r) _prev_net_modbterm = r._prev_net_modbterm; _busPort = r._busPort; _next_entry = r._next_entry; - _prev_entry = r._prev_entry; } dbIStream& operator>>(dbIStream& stream, _dbModBTerm& obj) @@ -172,9 +166,6 @@ dbIStream& operator>>(dbIStream& stream, _dbModBTerm& obj) if (obj.getDatabase()->isSchema(db_schema_update_hierarchy)) { stream >> obj._next_entry; } - if (obj.getDatabase()->isSchema(db_schema_odb_busport)) { - stream >> obj._prev_entry; - } return stream; } @@ -207,9 +198,6 @@ dbOStream& operator<<(dbOStream& stream, const _dbModBTerm& obj) if (obj.getDatabase()->isSchema(db_schema_update_hierarchy)) { stream << obj._next_entry; } - if (obj.getDatabase()->isSchema(db_schema_odb_busport)) { - stream << obj._prev_entry; - } return stream; } @@ -348,14 +336,7 @@ dbModBTerm* dbModBTerm::create(dbModule* parentModule, const char* name) ZALLOCATED(modbterm->_name); modbterm->_parent = module->getOID(); modbterm->_next_entry = module->_modbterms; - // set back pointer. - if (module->_modbterms != 0) { - _dbModBTerm* head_entry = block->_modbterm_tbl->getPtr(module->_modbterms); - head_entry->_prev_entry = modbterm->getOID(); - } - modbterm->_prev_entry = 0; module->_modbterms = modbterm->getOID(); - return (dbModBTerm*) modbterm; } @@ -439,26 +420,6 @@ void dbModBTerm::setBusPort(dbBusPort* bus_port) _modbterm->_busPort = bus_port->getId(); } -dbModBTerm* dbModBTerm::getNext() const -{ - _dbModBTerm* _modbterm = (_dbModBTerm*) this; - if (_modbterm->_next_entry != 0) { - _dbBlock* block_ = (_dbBlock*) _modbterm->getOwner(); - return (dbModBTerm*) block_->_modbterm_tbl->getPtr(_modbterm->_next_entry); - } - return nullptr; -} - -dbModBTerm* dbModBTerm::getPrev() const -{ - _dbModBTerm* _modbterm = (_dbModBTerm*) this; - if (_modbterm->_prev_entry != 0) { - _dbBlock* block_ = (_dbBlock*) _modbterm->getOwner(); - return (dbModBTerm*) block_->_modbterm_tbl->getPtr(_modbterm->_prev_entry); - } - return nullptr; -} - // User Code End dbModBTermPublicMethods } // namespace odb // Generator Code End Cpp diff --git a/src/odb/src/db/dbModBTerm.h b/src/odb/src/db/dbModBTerm.h index 4512c07635..a52a455ee3 100644 --- a/src/odb/src/db/dbModBTerm.h +++ b/src/odb/src/db/dbModBTerm.h @@ -71,7 +71,6 @@ class _dbModBTerm : public _dbObject dbId<_dbModBTerm> _prev_net_modbterm; dbId<_dbBusPort> _busPort; dbId<_dbModBTerm> _next_entry; - dbId<_dbModBTerm> _prev_entry; // User Code Begin Fields void* _sta_port = nullptr; From fdcb385c5d60ebaf415ba75244afbd53b102cc3c Mon Sep 17 00:00:00 2001 From: andyfox-rushc Date: Mon, 5 Aug 2024 18:41:08 -0700 Subject: [PATCH 36/37] Removed redundant accessor functions. Signed-off-by: Andy Fox. andy@rushc.com Signed-off-by: andyfox-rushc --- src/dbSta/src/dbReadVerilog.cc | 2 +- src/odb/include/odb/db.h | 2 -- src/odb/src/db/dbBusPort.cpp | 21 --------------------- 3 files changed, 1 insertion(+), 24 deletions(-) diff --git a/src/dbSta/src/dbReadVerilog.cc b/src/dbSta/src/dbReadVerilog.cc index b2c7b4fd0f..eff27a5b60 100644 --- a/src/dbSta/src/dbReadVerilog.cc +++ b/src/dbSta/src/dbReadVerilog.cc @@ -402,7 +402,7 @@ void Verilog2db::makeDbModule( dbModBTerm* modbterm = dbModBTerm::create(module, bus_bit_port.c_str()); if (i == 0) { - dbbusport->setFirstMember(modbterm); + dbbusport->setMembers(modbterm); } if (i == size - 1) { dbbusport->setLast(modbterm); diff --git a/src/odb/include/odb/db.h b/src/odb/include/odb/db.h index 04b4ef0fdb..457b6bbe06 100644 --- a/src/odb/include/odb/db.h +++ b/src/odb/include/odb/db.h @@ -7169,8 +7169,6 @@ class dbBusPort : public dbObject // get element by bit index in bus (allows for up/down) // linear access dbModBTerm* getBusIndexedElement(int index); - void setFirstMember(dbModBTerm*); - dbModBTerm* getFirstMember(); dbSet getBusPortMembers(); int getSize() const; bool getUpdown() const; diff --git a/src/odb/src/db/dbBusPort.cpp b/src/odb/src/db/dbBusPort.cpp index af30027235..182329ab3d 100644 --- a/src/odb/src/db/dbBusPort.cpp +++ b/src/odb/src/db/dbBusPort.cpp @@ -302,27 +302,6 @@ dbModBTerm* dbBusPort::getBusIndexedElement(int index) return nullptr; } -void dbBusPort::setFirstMember(dbModBTerm* modbterm) -{ - if (modbterm) { - _dbBusPort* obj = (_dbBusPort*) this; - _dbModBTerm* mbt = (_dbModBTerm*) modbterm; - obj->_members = mbt->getId(); - } -} - -dbModBTerm* dbBusPort::getFirstMember() -{ - _dbBusPort* obj = (_dbBusPort*) this; - _dbBlock* block = (_dbBlock*) obj->getOwner(); - if (obj->_members != 0) { - dbModBTerm* ret - = (dbModBTerm*) (block->_modbterm_tbl->getPtr(obj->_members)); - return ret; - } - return nullptr; -} - int dbBusPort::getSize() const { _dbBusPort* obj = (_dbBusPort*) this; From e66548762d1522d80ab9a90bcfdacbf87193d0a5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Tue, 6 Aug 2024 09:33:09 +0200 Subject: [PATCH 37/37] timing report: add a more elaborate tooltip MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If there was a f1/help button for all menus, then some of this tooltip would be moved in there. Meanwhile, best that can be done is a slightly verbose tooltip. Signed-off-by: Øyvind Harboe --- src/gui/src/staGui.cpp | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/gui/src/staGui.cpp b/src/gui/src/staGui.cpp index c14aeda695..873f1a5fda 100644 --- a/src/gui/src/staGui.cpp +++ b/src/gui/src/staGui.cpp @@ -181,7 +181,13 @@ QVariant TimingPathsModel::headerData(int section, // to a header item that doesn't. return ""; case Skew: - return "Path clock skew (crpr corrected)"; + // A rather verbose tooltip, move some of this to a help/documentation + // file when one is introduced into OpenROAD. Meanwhile, this is the + // best that can be done. + return "The difference in arrival times between\n" + "source and destination clock pins of a macro/register,\n" + "adjusted for CRPR and subtracting a clock period.\n" + "Setup and hold times account for internal clock delays."; case LogicDelay: return "Path delay from instances (excluding buffers and consecutive " "inverter pairs)";