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and8bit.cmd_log
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xst -intstyle ise -ifn "C:/Users/Vipul/ALUproject/and8bit.xst" -ofn "C:/Users/Vipul/ALUproject/and8bit.syr"
xst -intstyle ise -ifn "C:/Users/Vipul/ALUproject/and8bit.xst" -ofn "C:/Users/Vipul/ALUproject/and8bit.syr"
xst -intstyle ise -ifn "C:/Users/Vipul/ALUproject/and8bit.xst" -ofn "C:/Users/Vipul/ALUproject/and8bit.syr"
xst -intstyle ise -ifn "C:/Users/Vipul/ALUproject/and8bit.xst" -ofn "C:/Users/Vipul/ALUproject/and8bit.syr"
xst -intstyle ise -ifn "C:/Users/Vipul/ALUproject/and8bit.xst" -ofn "C:/Users/Vipul/ALUproject/and8bit.syr"
xst -intstyle ise -ifn "C:/Users/Vipul/ALUproject/and8bit.xst" -ofn "C:/Users/Vipul/ALUproject/and8bit.syr"
xst -intstyle ise -ifn "C:/Users/Vipul/ALUproject/and8bit.xst" -ofn "C:/Users/Vipul/ALUproject/and8bit.syr"
xst -intstyle ise -ifn "C:/Users/Vipul/ALUproject/and8bit.xst" -ofn "C:/Users/Vipul/ALUproject/and8bit.syr"
xst -intstyle ise -ifn "C:/Users/Vipul/ALUproject/and8bit.xst" -ofn "C:/Users/Vipul/ALUproject/and8bit.syr"
vhdtdtfi -lib work C:/Users/Vipul/ALUproject/and8bit.v -lang verilog -prj ALUproject -o and8bit.spl -module and8bit -template C:/Xilinx/14.7/ISE_DS/ISE//data/splveri.tft -deleteonerror
spl2sym -intstyle ise -family artix7 and8bit.spl C:/Users/Vipul/ALUproject/and8bit.sym
vhdtdtfi -lib work C:/Users/Vipul/ALUproject/and8bit.v -lang verilog -prj ALUproject -o and8bit.spl -module and8bit -template C:/Xilinx/14.7/ISE_DS/ISE//data/splveri.tft -deleteonerror
spl2sym -intstyle ise -family artix7 and8bit.spl C:/Users/Vipul/ALUproject/and8bit.sym