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ALU.syr
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Release 14.7 - xst P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.15 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.15 secs
--> Reading design: ALU.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Parsing
3) HDL Elaboration
4) HDL Synthesis
4.1) HDL Synthesis Report
5) Advanced HDL Synthesis
5.1) Advanced HDL Synthesis Report
6) Low Level Synthesis
7) Partition Report
8) Design Summary
8.1) Primitive and Black Box Usage
8.2) Device utilization summary
8.3) Partition Resource Summary
8.4) Timing Report
8.4.1) Clock Information
8.4.2) Asynchronous Control Signals Information
8.4.3) Timing Summary
8.4.4) Timing Details
8.4.5) Cross Clock Domains Report
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "ALU.prj"
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "ALU"
Output Format : NGC
Target Device : xc7a100t-3-csg324
---- Source Options
Top Module Name : ALU
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : LUT
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Shift Register Extraction : YES
ROM Style : Auto
Resource Sharing : YES
Asynchronous To Synchronous : NO
Shift Register Minimum Size : 2
Use DSP Block : Auto
Automatic Register Balancing : No
---- Target Options
LUT Combining : Auto
Reduce Control Sets : Auto
Add IO Buffers : YES
Global Maximum Fanout : 100000
Add Generic Clock Buffer(BUFG) : 32
Register Duplication : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Auto
Use Synchronous Set : Auto
Use Synchronous Reset : Auto
Pack IO Registers into IOBs : Auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Power Reduction : NO
Keep Hierarchy : No
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
DSP48 Utilization Ratio : 100
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
=========================================================================
=========================================================================
* HDL Parsing *
=========================================================================
Analyzing Verilog file "C:\Users\Vipul\ALUproject\fulladder.v" into library work
Parsing module <fulladder>.
Analyzing Verilog file "C:\Users\Vipul\ALUproject\booth_step_mult.v" into library work
Parsing module <booth_step_mult>.
Analyzing Verilog file "C:\Users\Vipul\ALUproject\xor8bit.v" into library work
Parsing module <xor8bit>.
Analyzing Verilog file "C:\Users\Vipul\ALUproject\ripple8bit.v" into library work
Parsing module <ripple8bit>.
WARNING:HDLCompiler:751 - "C:\Users\Vipul\ALUproject\ripple8bit.v" Line 13: Redeclaration of ansi port sum_out is not allowed
WARNING:HDLCompiler:751 - "C:\Users\Vipul\ALUproject\ripple8bit.v" Line 14: Redeclaration of ansi port c_out is not allowed
WARNING:HDLCompiler:751 - "C:\Users\Vipul\ALUproject\ripple8bit.v" Line 16: Redeclaration of ansi port overflow is not allowed
WARNING:HDLCompiler:751 - "C:\Users\Vipul\ALUproject\ripple8bit.v" Line 17: Redeclaration of ansi port in_a is not allowed
WARNING:HDLCompiler:751 - "C:\Users\Vipul\ALUproject\ripple8bit.v" Line 18: Redeclaration of ansi port in_b is not allowed
WARNING:HDLCompiler:751 - "C:\Users\Vipul\ALUproject\ripple8bit.v" Line 19: Redeclaration of ansi port in_c is not allowed
Analyzing Verilog file "C:\Users\Vipul\ALUproject\mult8bit.v" into library work
Parsing module <mult8bit>.
WARNING:HDLCompiler:751 - "C:\Users\Vipul\ALUproject\mult8bit.v" Line 9: Redeclaration of ansi port out_c is not allowed
WARNING:HDLCompiler:751 - "C:\Users\Vipul\ALUproject\mult8bit.v" Line 10: Redeclaration of ansi port in_a is not allowed
WARNING:HDLCompiler:751 - "C:\Users\Vipul\ALUproject\mult8bit.v" Line 11: Redeclaration of ansi port in_b is not allowed
Analyzing Verilog file "C:\Users\Vipul\ALUproject\and8bit.v" into library work
Parsing module <and8bit>.
Analyzing Verilog file "C:\Users\Vipul\ALUproject\ALU.v" into library work
Parsing module <ALU>.
WARNING:HDLCompiler:751 - "C:\Users\Vipul\ALUproject\ALU.v" Line 13: Redeclaration of ansi port opcode is not allowed
WARNING:HDLCompiler:751 - "C:\Users\Vipul\ALUproject\ALU.v" Line 14: Redeclaration of ansi port intop1 is not allowed
WARNING:HDLCompiler:751 - "C:\Users\Vipul\ALUproject\ALU.v" Line 15: Redeclaration of ansi port intop2 is not allowed
WARNING:HDLCompiler:751 - "C:\Users\Vipul\ALUproject\ALU.v" Line 16: Redeclaration of ansi port overflow is not allowed
WARNING:HDLCompiler:751 - "C:\Users\Vipul\ALUproject\ALU.v" Line 17: Redeclaration of ansi port carry is not allowed
WARNING:HDLCompiler:751 - "C:\Users\Vipul\ALUproject\ALU.v" Line 18: Redeclaration of ansi port result is not allowed
WARNING:HDLCompiler:751 - "C:\Users\Vipul\ALUproject\ALU.v" Line 19: Redeclaration of ansi port product is not allowed
=========================================================================
* HDL Elaboration *
=========================================================================
Elaborating module <ALU>.
Elaborating module <ripple8bit>.
Elaborating module <fulladder>.
"C:\Users\Vipul\ALUproject\ripple8bit.v" Line 32. $display 1'b.
Elaborating module <and8bit>.
Elaborating module <xor8bit>.
Elaborating module <mult8bit>.
Elaborating module <booth_step_mult>.
"C:\Users\Vipul\ALUproject\mult8bit.v" Line 46. $display value1 of out_c is:0
"C:\Users\Vipul\ALUproject\mult8bit.v" Line 47. $display out_c = 16'b................
"C:\Users\Vipul\ALUproject\ALU.v" Line 43. $display executing addition result = 8'b........
"C:\Users\Vipul\ALUproject\ALU.v" Line 44. $display result= 0
"C:\Users\Vipul\ALUproject\ALU.v" Line 51. $display executing and result = 8'b........
"C:\Users\Vipul\ALUproject\ALU.v" Line 52. $display result= 0
"C:\Users\Vipul\ALUproject\ALU.v" Line 59. $display executing xor result = 8'b........
"C:\Users\Vipul\ALUproject\ALU.v" Line 60. $display result= 0
"C:\Users\Vipul\ALUproject\ALU.v" Line 67. $display executing multiplication result = 16'b................
"C:\Users\Vipul\ALUproject\ALU.v" Line 68. $display result= 0
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <ALU>.
Related source file is "C:\Users\Vipul\ALUproject\ALU.v".
Found 8-bit 4-to-1 multiplexer for signal <result> created at line 35.
Summary:
inferred 5 Multiplexer(s).
Unit <ALU> synthesized.
Synthesizing Unit <ripple8bit>.
Related source file is "C:\Users\Vipul\ALUproject\ripple8bit.v".
Summary:
Unit <ripple8bit> synthesized.
Synthesizing Unit <fulladder>.
Related source file is "C:\Users\Vipul\ALUproject\fulladder.v".
Summary:
Unit <fulladder> synthesized.
Synthesizing Unit <and8bit>.
Related source file is "C:\Users\Vipul\ALUproject\and8bit.v".
Summary:
no macro.
Unit <and8bit> synthesized.
Synthesizing Unit <xor8bit>.
Related source file is "C:\Users\Vipul\ALUproject\xor8bit.v".
Summary:
Unit <xor8bit> synthesized.
Synthesizing Unit <mult8bit>.
Related source file is "C:\Users\Vipul\ALUproject\mult8bit.v".
Summary:
no macro.
Unit <mult8bit> synthesized.
Synthesizing Unit <booth_step_mult>.
Related source file is "C:\Users\Vipul\ALUproject\booth_step_mult.v".
Found 8-bit adder for signal <A_sum> created at line 32.
Found 32-bit adder for signal <n0039> created at line 33.
Found 32-bit adder for signal <n0023> created at line 33.
Found 8-bit 4-to-1 multiplexer for signal <A_temp> created at line 36.
Found 1-bit 4-to-1 multiplexer for signal <Q_temp<8>> created at line 36.
Summary:
inferred 3 Adder/Subtractor(s).
inferred 2 Multiplexer(s).
Unit <booth_step_mult> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Adders/Subtractors : 24
32-bit adder : 16
8-bit adder : 8
# Multiplexers : 21
1-bit 2-to-1 multiplexer : 2
1-bit 4-to-1 multiplexer : 8
16-bit 2-to-1 multiplexer : 1
8-bit 2-to-1 multiplexer : 1
8-bit 4-to-1 multiplexer : 9
# Xors : 25
1-bit xor2 : 25
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# Adders/Subtractors : 16
8-bit adder : 8
8-bit adder carry in : 8
# Multiplexers : 21
1-bit 2-to-1 multiplexer : 2
1-bit 4-to-1 multiplexer : 8
16-bit 2-to-1 multiplexer : 1
8-bit 2-to-1 multiplexer : 1
8-bit 4-to-1 multiplexer : 9
# Xors : 25
1-bit xor2 : 25
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <ALU> ...
Optimizing unit <booth_step_mult> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block ALU, actual ratio is 0.
Final Macro Processing ...
=========================================================================
Final Register Report
Found no macro
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Design Summary *
=========================================================================
Top Level Output File Name : ALU.ngc
Primitive and Black Box Usage:
------------------------------
# BELS : 432
# GND : 1
# INV : 8
# LUT2 : 9
# LUT3 : 19
# LUT4 : 3
# LUT5 : 50
# LUT6 : 116
# MUXCY : 105
# VCC : 1
# XORCY : 120
# IO Buffers : 44
# IBUF : 18
# OBUF : 26
Device utilization summary:
---------------------------
Selected Device : 7a100tcsg324-3
Slice Logic Utilization:
Number of Slice LUTs: 205 out of 63400 0%
Number used as Logic: 205 out of 63400 0%
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 205
Number with an unused Flip Flop: 205 out of 205 100%
Number with an unused LUT: 0 out of 205 0%
Number of fully used LUT-FF pairs: 0 out of 205 0%
Number of unique control sets: 0
IO Utilization:
Number of IOs: 44
Number of bonded IOBs: 44 out of 210 20%
Specific Feature Utilization:
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=========================================================================
Timing Report
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
No clock signals found in this design
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -3
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 13.279ns
Timing Details:
---------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 7896972940 / 26
-------------------------------------------------------------------------
Delay: 13.279ns (Levels of Logic = 34)
Source: intop2<0> (PAD)
Destination: product<15> (PAD)
Data Path: intop2<0> to product<15>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 19 0.001 0.363 intop2_0_IBUF (intop2_0_IBUF)
INV:I->O 1 0.113 0.000 a4/b1/n0037<0>11_INV_0 (a4/b1/n0037<0>1)
MUXCY:S->O 1 0.353 0.000 a4/b1/Madd_n0023_Madd_Madd_cy<0> (a4/b1/Madd_n0023_Madd_Madd_cy<0>)
MUXCY:CI->O 1 0.023 0.000 a4/b1/Madd_n0023_Madd_Madd_cy<1> (a4/b1/Madd_n0023_Madd_Madd_cy<1>)
MUXCY:CI->O 1 0.023 0.000 a4/b1/Madd_n0023_Madd_Madd_cy<2> (a4/b1/Madd_n0023_Madd_Madd_cy<2>)
MUXCY:CI->O 1 0.023 0.000 a4/b1/Madd_n0023_Madd_Madd_cy<3> (a4/b1/Madd_n0023_Madd_Madd_cy<3>)
MUXCY:CI->O 1 0.023 0.000 a4/b1/Madd_n0023_Madd_Madd_cy<4> (a4/b1/Madd_n0023_Madd_Madd_cy<4>)
MUXCY:CI->O 1 0.023 0.000 a4/b1/Madd_n0023_Madd_Madd_cy<5> (a4/b1/Madd_n0023_Madd_Madd_cy<5>)
MUXCY:CI->O 0 0.023 0.000 a4/b1/Madd_n0023_Madd_Madd_cy<6> (a4/b1/Madd_n0023_Madd_Madd_cy<6>)
XORCY:CI->O 13 0.370 0.567 a4/b1/Madd_n0023_Madd_Madd_xor<7> (a4/b1/n0023<7>)
LUT3:I0->O 1 0.097 0.000 a4/b2/Madd_A_sum_lut<6> (a4/b2/Madd_A_sum_lut<6>)
MUXCY:S->O 0 0.353 0.000 a4/b2/Madd_A_sum_cy<6> (a4/b2/Madd_A_sum_cy<6>)
XORCY:CI->O 5 0.370 0.530 a4/b2/Madd_A_sum_xor<7> (a4/b2/A_sum<7>)
LUT5:I2->O 8 0.097 0.311 a4/b2/A_temp<7>1 (a4/temp_A3<6>)
MUXCY:DI->O 0 0.337 0.000 a4/b3/Madd_A_sum_cy<6> (a4/b3/Madd_A_sum_cy<6>)
XORCY:CI->O 5 0.370 0.398 a4/b3/Madd_A_sum_xor<7> (a4/b3/A_sum<7>)
LUT5:I3->O 8 0.097 0.311 a4/b3/A_temp<7>1 (a4/temp_A4<6>)
MUXCY:DI->O 0 0.337 0.000 a4/b4/Madd_A_sum_cy<6> (a4/b4/Madd_A_sum_cy<6>)
XORCY:CI->O 5 0.370 0.398 a4/b4/Madd_A_sum_xor<7> (a4/b4/A_sum<7>)
LUT5:I3->O 8 0.097 0.312 a4/b4/A_temp<7>1 (a4/temp_A5<6>)
MUXCY:DI->O 0 0.337 0.000 a4/b5/Madd_A_sum_cy<6> (a4/b5/Madd_A_sum_cy<6>)
XORCY:CI->O 5 0.370 0.398 a4/b5/Madd_A_sum_xor<7> (a4/b5/A_sum<7>)
LUT5:I3->O 8 0.097 0.312 a4/b5/A_temp<7>1 (a4/temp_A6<6>)
MUXCY:DI->O 0 0.337 0.000 a4/b6/Madd_A_sum_cy<6> (a4/b6/Madd_A_sum_cy<6>)
XORCY:CI->O 5 0.370 0.398 a4/b6/Madd_A_sum_xor<7> (a4/b6/A_sum<7>)
LUT5:I3->O 8 0.097 0.312 a4/b6/A_temp<7>1 (a4/temp_A7<6>)
MUXCY:DI->O 0 0.337 0.000 a4/b7/Madd_A_sum_cy<6> (a4/b7/Madd_A_sum_cy<6>)
XORCY:CI->O 5 0.370 0.398 a4/b7/Madd_A_sum_xor<7> (a4/b7/A_sum<7>)
LUT5:I3->O 2 0.097 0.283 a4/b7/A_temp<7>1 (a4/temp_A8<6>)
MUXCY:DI->O 0 0.337 0.000 a4/b8/Madd_A_sum_cy<6> (a4/b8/Madd_A_sum_cy<6>)
XORCY:CI->O 1 0.370 0.379 a4/b8/Madd_A_sum_xor<7> (a4/b8/A_sum<7>)
LUT5:I3->O 1 0.097 0.511 a4/b8/A_temp<7>1 (result_wire4<14>)
LUT3:I0->O 2 0.097 0.283 Mmux_product71 (product_14_OBUF)
OBUF:I->O 0.000 product_14_OBUF (product<14>)
----------------------------------------
Total 13.279ns (6.813ns logic, 6.466ns route)
(51.3% logic, 48.7% route)
=========================================================================
Cross Clock Domains Report:
--------------------------
=========================================================================
Total REAL time to Xst completion: 14.00 secs
Total CPU time to Xst completion: 13.57 secs
-->
Total memory usage is 482120 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 16 ( 0 filtered)
Number of infos : 0 ( 0 filtered)