From 6ca7db18aa32773ac2d268b8e92ea1860c3a491d Mon Sep 17 00:00:00 2001 From: Atsushi WATANABE Date: Tue, 25 Oct 2011 01:57:01 +0900 Subject: [PATCH] =?UTF-8?q?Git=E7=AE=A1=E7=90=86=E9=96=8B=E5=A7=8B?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .gitignore | 8 + .../at91sam7se512/AT91SAM7SE512.h | 2776 +++++++++++++++++ .../at91sam7se-ek/at91sam7se512/flash.lds | 77 + .../at91sam7se-ek/at91sam7se512/sdram.lds | 79 + .../at91sam7se-ek/at91sam7se512/sram.lds | 77 + at91lib/boards/at91sam7se-ek/board.h | 548 ++++ at91lib/boards/at91sam7se-ek/board.mak | 33 + at91lib/boards/at91sam7se-ek/board_cstartup.S | 181 ++ at91lib/boards/at91sam7se-ek/board_lowlevel.c | 175 ++ at91lib/boards/at91sam7se-ek/board_memories.c | 136 + at91lib/boards/at91sam7se-ek/board_memories.h | 57 + .../theva-rev1/at91sam7se512/AT91SAM7SE512.h | 2776 +++++++++++++++++ .../boards/theva-rev1/at91sam7se512/flash.icf | 48 + .../boards/theva-rev1/at91sam7se512/flash.lds | 77 + .../boards/theva-rev1/at91sam7se512/flash.sct | 53 + .../boards/theva-rev1/at91sam7se512/sdram.icf | 46 + .../boards/theva-rev1/at91sam7se512/sdram.lds | 79 + .../boards/theva-rev1/at91sam7se512/sdram.sct | 50 + .../theva-rev1/at91sam7se512/sdram_samba.lds | 79 + .../boards/theva-rev1/at91sam7se512/sram.icf | 36 + .../boards/theva-rev1/at91sam7se512/sram.lds | 77 + .../boards/theva-rev1/at91sam7se512/sram.sct | 53 + .../theva-rev1/at91sam7se512/sram_samba.lds | 78 + at91lib/boards/theva-rev1/board.h | 194 ++ at91lib/boards/theva-rev1/board.mak | 32 + at91lib/boards/theva-rev1/board_cstartup.S | 181 ++ .../boards/theva-rev1/board_cstartup_iar.s | 179 ++ .../boards/theva-rev1/board_cstartup_keil.s | 207 ++ at91lib/boards/theva-rev1/board_lowlevel.c | 179 ++ at91lib/boards/theva-rev1/board_lowlevel.h | 49 + at91lib/boards/theva-rev1/board_memories.c | 135 + at91lib/boards/theva-rev1/board_memories.h | 70 + at91lib/peripherals/aic/aic.c | 87 + at91lib/peripherals/aic/aic.h | 79 + at91lib/peripherals/cp15/cp15.c | 268 ++ at91lib/peripherals/cp15/cp15.h | 84 + at91lib/peripherals/cp15/cp15_asm.S | 138 + at91lib/peripherals/dbgu/dbgu.c | 174 ++ at91lib/peripherals/dbgu/dbgu.h | 79 + at91lib/peripherals/pio/pio.c | 346 ++ at91lib/peripherals/pio/pio.h | 163 + at91lib/peripherals/pio/pio_it.c | 395 +++ at91lib/peripherals/pio/pio_it.h | 83 + at91lib/peripherals/pmc/pmc.c | 186 ++ at91lib/peripherals/pmc/pmc.h | 62 + at91lib/peripherals/tc/tc.h | 74 + at91lib/peripherals/usart/usart.c | 272 ++ at91lib/peripherals/usart/usart.h | 118 + .../CDCAbstractControlManagementDescriptor.h | 104 + .../common/cdc/CDCCallManagementDescriptor.h | 97 + .../cdc/CDCCommunicationInterfaceDescriptor.h | 65 + .../common/cdc/CDCDataInterfaceDescriptor.h | 65 + at91lib/usb/common/cdc/CDCDeviceDescriptor.h | 64 + at91lib/usb/common/cdc/CDCGenericDescriptor.h | 91 + at91lib/usb/common/cdc/CDCGenericRequest.h | 63 + at91lib/usb/common/cdc/CDCHeaderDescriptor.h | 77 + at91lib/usb/common/cdc/CDCLineCoding.c | 78 + at91lib/usb/common/cdc/CDCLineCoding.h | 136 + .../cdc/CDCSetControlLineStateRequest.c | 84 + .../cdc/CDCSetControlLineStateRequest.h | 59 + at91lib/usb/common/cdc/CDCUnionDescriptor.h | 79 + .../common/core/USBConfigurationDescriptor.c | 162 + .../common/core/USBConfigurationDescriptor.h | 150 + at91lib/usb/common/core/USBDeviceDescriptor.h | 111 + .../core/USBDeviceQualifierDescriptor.h | 89 + .../usb/common/core/USBEndpointDescriptor.c | 98 + .../usb/common/core/USBEndpointDescriptor.h | 221 ++ at91lib/usb/common/core/USBFeatureRequest.c | 70 + at91lib/usb/common/core/USBFeatureRequest.h | 136 + .../usb/common/core/USBGenericDescriptor.c | 80 + .../usb/common/core/USBGenericDescriptor.h | 133 + at91lib/usb/common/core/USBGenericRequest.c | 138 + at91lib/usb/common/core/USBGenericRequest.h | 244 ++ .../usb/common/core/USBGetDescriptorRequest.c | 72 + .../usb/common/core/USBGetDescriptorRequest.h | 67 + .../usb/common/core/USBInterfaceDescriptor.h | 87 + at91lib/usb/common/core/USBInterfaceRequest.c | 69 + at91lib/usb/common/core/USBInterfaceRequest.h | 68 + .../usb/common/core/USBSetAddressRequest.c | 56 + .../usb/common/core/USBSetAddressRequest.h | 60 + .../common/core/USBSetConfigurationRequest.c | 58 + .../common/core/USBSetConfigurationRequest.h | 61 + at91lib/usb/common/core/USBStringDescriptor.h | 74 + .../usb/device/cdc-serial/CDCDSerialDriver.c | 300 ++ .../usb/device/cdc-serial/CDCDSerialDriver.h | 117 + .../cdc-serial/CDCDSerialDriverDescriptors.c | 625 ++++ .../cdc-serial/CDCDSerialDriverDescriptors.h | 77 + at91lib/usb/device/core/USBD.h | 187 ++ at91lib/usb/device/core/USBDCallbacks.h | 65 + .../device/core/USBDCallbacks_Initialized.c | 62 + at91lib/usb/device/core/USBDCallbacks_Reset.c | 47 + at91lib/usb/device/core/USBDDriver.c | 682 ++++ at91lib/usb/device/core/USBDDriver.h | 93 + at91lib/usb/device/core/USBDDriverCallbacks.h | 61 + .../usb/device/core/USBDDriverCb_CfgChanged.c | 49 + .../core/USBDDriverCb_IfSettingChanged.c | 52 + .../usb/device/core/USBDDriverDescriptors.h | 86 + at91lib/usb/device/core/USBD_OTGHS.c | 1677 ++++++++++ at91lib/usb/device/core/USBD_UDP.c | 1225 ++++++++ at91lib/usb/device/core/USBD_UDPHS.c | 1680 ++++++++++ at91lib/utility/assert.h | 114 + at91lib/utility/led.c | 162 + at91lib/utility/led.h | 70 + at91lib/utility/stdio.c | 512 +++ at91lib/utility/string.c | 239 ++ at91lib/utility/trace.h | 236 ++ cdc-test/Makefile | 168 + cdc-test/communication.c | 576 ++++ cdc-test/communication.h | 85 + cdc-test/controlPWM.c | 288 ++ cdc-test/controlPWM.h | 9 + cdc-test/controlVelocity.c | 217 ++ cdc-test/controlVelocity.h | 65 + cdc-test/fixpawd.c | 82 + cdc-test/fixpawd.h | 34 + cdc-test/fixpawd_math.c | 504 +++ cdc-test/fixpawd_math.h | 153 + cdc-test/main.c | 376 +++ cdc-test/mathSin.h | 8 + cdc-test/mathSin2000.c | 2002 ++++++++++++ cdc-test/mathSin2048.c | 2050 ++++++++++++ cdc-test/power.c | 81 + cdc-test/power.h | 7 + cdc-test/registerFPGA.h | 62 + icart1.param | 43 + resources/gdb/at91cap9-dk-bcram.gdb | 60 + resources/gdb/at91cap9-dk-ddram.gdb | 112 + resources/gdb/at91cap9-dk-sdram.gdb | 80 + resources/gdb/at91cap9-dk-sram.gdb | 25 + resources/gdb/at91sam7se-ek-sdram.gdb | 78 + resources/gdb/at91sam9260-ek-sdram.gdb | 70 + resources/gdb/at91sam9260-ek-sram.gdb | 26 + resources/gdb/at91sam9263-ek-sdram.gdb | 78 + resources/gdb/at91sam9263-ek-sram.gdb | 25 + resources/gdb/at91sam9g20-ek-sdram.gdb | 75 + resources/gdb/at91sam9g20-ek-sram.gdb | 26 + resources/gdb/at91sam9m10-ek-ddram.gdb | 217 ++ resources/gdb/at91sam9m10-ek-sram.gdb | 40 + resources/gdb/at91sam9rl-ek-sdram.gdb | 65 + resources/gdb/at91sam9rl-ek-sram.gdb | 25 + resources/gdb/at91sam9xe-ek-sdram.gdb | 70 + resources/gdb/at91sam9xe-ek-sram.gdb | 26 + resources/gdb/debug.pl | 93 + 143 files changed, 31218 insertions(+) create mode 100644 .gitignore create mode 100644 at91lib/boards/at91sam7se-ek/at91sam7se512/AT91SAM7SE512.h create mode 100644 at91lib/boards/at91sam7se-ek/at91sam7se512/flash.lds create mode 100644 at91lib/boards/at91sam7se-ek/at91sam7se512/sdram.lds create mode 100644 at91lib/boards/at91sam7se-ek/at91sam7se512/sram.lds create mode 100644 at91lib/boards/at91sam7se-ek/board.h create mode 100644 at91lib/boards/at91sam7se-ek/board.mak create mode 100644 at91lib/boards/at91sam7se-ek/board_cstartup.S create mode 100644 at91lib/boards/at91sam7se-ek/board_lowlevel.c create mode 100644 at91lib/boards/at91sam7se-ek/board_memories.c create mode 100644 at91lib/boards/at91sam7se-ek/board_memories.h create mode 100644 at91lib/boards/theva-rev1/at91sam7se512/AT91SAM7SE512.h create mode 100644 at91lib/boards/theva-rev1/at91sam7se512/flash.icf create mode 100644 at91lib/boards/theva-rev1/at91sam7se512/flash.lds create mode 100644 at91lib/boards/theva-rev1/at91sam7se512/flash.sct create mode 100644 at91lib/boards/theva-rev1/at91sam7se512/sdram.icf create mode 100644 at91lib/boards/theva-rev1/at91sam7se512/sdram.lds create mode 100644 at91lib/boards/theva-rev1/at91sam7se512/sdram.sct create mode 100644 at91lib/boards/theva-rev1/at91sam7se512/sdram_samba.lds create mode 100644 at91lib/boards/theva-rev1/at91sam7se512/sram.icf create mode 100644 at91lib/boards/theva-rev1/at91sam7se512/sram.lds create mode 100644 at91lib/boards/theva-rev1/at91sam7se512/sram.sct create mode 100644 at91lib/boards/theva-rev1/at91sam7se512/sram_samba.lds create mode 100644 at91lib/boards/theva-rev1/board.h create mode 100644 at91lib/boards/theva-rev1/board.mak create mode 100644 at91lib/boards/theva-rev1/board_cstartup.S create mode 100644 at91lib/boards/theva-rev1/board_cstartup_iar.s create mode 100644 at91lib/boards/theva-rev1/board_cstartup_keil.s create mode 100644 at91lib/boards/theva-rev1/board_lowlevel.c create mode 100644 at91lib/boards/theva-rev1/board_lowlevel.h create mode 100644 at91lib/boards/theva-rev1/board_memories.c create mode 100644 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at91lib/usb/common/cdc/CDCCallManagementDescriptor.h create mode 100644 at91lib/usb/common/cdc/CDCCommunicationInterfaceDescriptor.h create mode 100644 at91lib/usb/common/cdc/CDCDataInterfaceDescriptor.h create mode 100644 at91lib/usb/common/cdc/CDCDeviceDescriptor.h create mode 100644 at91lib/usb/common/cdc/CDCGenericDescriptor.h create mode 100644 at91lib/usb/common/cdc/CDCGenericRequest.h create mode 100644 at91lib/usb/common/cdc/CDCHeaderDescriptor.h create mode 100644 at91lib/usb/common/cdc/CDCLineCoding.c create mode 100644 at91lib/usb/common/cdc/CDCLineCoding.h create mode 100644 at91lib/usb/common/cdc/CDCSetControlLineStateRequest.c create mode 100644 at91lib/usb/common/cdc/CDCSetControlLineStateRequest.h create mode 100644 at91lib/usb/common/cdc/CDCUnionDescriptor.h create mode 100644 at91lib/usb/common/core/USBConfigurationDescriptor.c create mode 100644 at91lib/usb/common/core/USBConfigurationDescriptor.h create mode 100644 at91lib/usb/common/core/USBDeviceDescriptor.h create mode 100644 at91lib/usb/common/core/USBDeviceQualifierDescriptor.h create mode 100644 at91lib/usb/common/core/USBEndpointDescriptor.c create mode 100644 at91lib/usb/common/core/USBEndpointDescriptor.h create mode 100644 at91lib/usb/common/core/USBFeatureRequest.c create mode 100644 at91lib/usb/common/core/USBFeatureRequest.h create mode 100644 at91lib/usb/common/core/USBGenericDescriptor.c create mode 100644 at91lib/usb/common/core/USBGenericDescriptor.h create mode 100644 at91lib/usb/common/core/USBGenericRequest.c create mode 100644 at91lib/usb/common/core/USBGenericRequest.h create mode 100644 at91lib/usb/common/core/USBGetDescriptorRequest.c create mode 100644 at91lib/usb/common/core/USBGetDescriptorRequest.h create mode 100644 at91lib/usb/common/core/USBInterfaceDescriptor.h create mode 100644 at91lib/usb/common/core/USBInterfaceRequest.c create mode 100644 at91lib/usb/common/core/USBInterfaceRequest.h create mode 100644 at91lib/usb/common/core/USBSetAddressRequest.c create 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100644 at91lib/usb/device/core/USBDDriverCb_CfgChanged.c create mode 100644 at91lib/usb/device/core/USBDDriverCb_IfSettingChanged.c create mode 100644 at91lib/usb/device/core/USBDDriverDescriptors.h create mode 100644 at91lib/usb/device/core/USBD_OTGHS.c create mode 100644 at91lib/usb/device/core/USBD_UDP.c create mode 100644 at91lib/usb/device/core/USBD_UDPHS.c create mode 100644 at91lib/utility/assert.h create mode 100644 at91lib/utility/led.c create mode 100644 at91lib/utility/led.h create mode 100644 at91lib/utility/stdio.c create mode 100644 at91lib/utility/string.c create mode 100644 at91lib/utility/trace.h create mode 100644 cdc-test/Makefile create mode 100644 cdc-test/communication.c create mode 100644 cdc-test/communication.h create mode 100644 cdc-test/controlPWM.c create mode 100644 cdc-test/controlPWM.h create mode 100644 cdc-test/controlVelocity.c create mode 100644 cdc-test/controlVelocity.h create mode 100644 cdc-test/fixpawd.c create mode 100644 cdc-test/fixpawd.h create mode 100644 cdc-test/fixpawd_math.c create mode 100644 cdc-test/fixpawd_math.h create mode 100644 cdc-test/main.c create mode 100644 cdc-test/mathSin.h create mode 100644 cdc-test/mathSin2000.c create mode 100644 cdc-test/mathSin2048.c create mode 100644 cdc-test/power.c create mode 100644 cdc-test/power.h create mode 100644 cdc-test/registerFPGA.h create mode 100644 icart1.param create mode 100644 resources/gdb/at91cap9-dk-bcram.gdb create mode 100644 resources/gdb/at91cap9-dk-ddram.gdb create mode 100644 resources/gdb/at91cap9-dk-sdram.gdb create mode 100644 resources/gdb/at91cap9-dk-sram.gdb create mode 100644 resources/gdb/at91sam7se-ek-sdram.gdb create mode 100644 resources/gdb/at91sam9260-ek-sdram.gdb create mode 100644 resources/gdb/at91sam9260-ek-sram.gdb create mode 100644 resources/gdb/at91sam9263-ek-sdram.gdb create mode 100644 resources/gdb/at91sam9263-ek-sram.gdb create mode 100644 resources/gdb/at91sam9g20-ek-sdram.gdb create mode 100644 resources/gdb/at91sam9g20-ek-sram.gdb create mode 100644 resources/gdb/at91sam9m10-ek-ddram.gdb create mode 100644 resources/gdb/at91sam9m10-ek-sram.gdb create mode 100644 resources/gdb/at91sam9rl-ek-sdram.gdb create mode 100644 resources/gdb/at91sam9rl-ek-sram.gdb create mode 100644 resources/gdb/at91sam9xe-ek-sdram.gdb create mode 100644 resources/gdb/at91sam9xe-ek-sram.gdb create mode 100644 resources/gdb/debug.pl diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..2433285 --- /dev/null +++ b/.gitignore @@ -0,0 +1,8 @@ +*.log +*~ +*.o +*.a +*.bak +a.out +*.bin +*.elf \ No newline at end of file diff --git a/at91lib/boards/at91sam7se-ek/at91sam7se512/AT91SAM7SE512.h b/at91lib/boards/at91sam7se-ek/at91sam7se512/AT91SAM7SE512.h new file mode 100644 index 0000000..2f4376e --- /dev/null +++ b/at91lib/boards/at91sam7se-ek/at91sam7se512/AT91SAM7SE512.h @@ -0,0 +1,2776 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// Copyright (c) 2006, Atmel Corporation +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the disclaimer below. +// +// Atmel's name may not be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM7SE512.h +// Object : AT91SAM7SE512 definitions +// Generated : AT91 SW Application Group 07/07/2008 (16:12:05) +// +// CVS Reference : /AT91SAM7SE512.pl/1.21/Fri Feb 29 14:02:47 2008// +// CVS Reference : /SYS_SAM7X.pl/1.3/Wed Feb 2 15:48:15 2005// +// CVS Reference : /MC_SAM7SE.pl/1.10/Thu Feb 16 16:35:28 2006// +// CVS Reference : /PMC_SAM7S_USB.pl/1.4/Tue Feb 8 14:00:19 2005// +// CVS Reference : /RSTC_SAM7X.pl/1.2/Wed Jul 13 15:25:17 2005// +// CVS Reference : /UDP_8ept_puon.pl/1.1/Wed Aug 30 13:10:57 2006// +// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 12:38:54 2005// +// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005// +// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005// +// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004// +// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004// +// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004// +// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:40:38 2005// +// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005// +// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005// +// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005// +// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005// +// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004// +// CVS Reference : /TWI_6061B.pl/1.2/Fri Aug 4 08:47:25 2006// +// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005// +// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005// +// CVS Reference : /EBI_SAM7SE512.pl/1.22/Fri Nov 18 17:47:47 2005// +// CVS Reference : /SMC_1783A.pl/1.4/Thu Feb 3 10:30:06 2005// +// CVS Reference : /SDRC_SAM7SE512.pl/1.7/Fri Jul 8 07:50:18 2005// +// CVS Reference : /HECC_SAM7SE512.pl/1.8/Tue Jul 12 06:31:42 2005// +// ---------------------------------------------------------------------------- + +#ifndef AT91SAM7SE512_H +#define AT91SAM7SE512_H + +#ifndef __ASSEMBLY__ +typedef volatile unsigned int AT91_REG;// Hardware register definition +#define AT91_CAST(a) (a) +#else +#define AT91_CAST(a) +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SYS { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register + AT91_REG Reserved2[45]; // + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved3[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved4[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register + AT91_REG Reserved5[54]; // + AT91_REG PIOA_PER; // PIO Enable Register + AT91_REG PIOA_PDR; // PIO Disable Register + AT91_REG PIOA_PSR; // PIO Status Register + AT91_REG Reserved6[1]; // + AT91_REG PIOA_OER; // Output Enable Register + AT91_REG PIOA_ODR; // Output Disable Registerr + AT91_REG PIOA_OSR; // Output Status Register + AT91_REG Reserved7[1]; // + AT91_REG PIOA_IFER; // Input Filter Enable Register + AT91_REG PIOA_IFDR; // Input Filter Disable Register + AT91_REG PIOA_IFSR; // Input Filter Status Register + AT91_REG Reserved8[1]; // + AT91_REG PIOA_SODR; // Set Output Data Register + AT91_REG PIOA_CODR; // Clear Output Data Register + AT91_REG PIOA_ODSR; // Output Data Status Register + AT91_REG PIOA_PDSR; // Pin Data Status Register + AT91_REG PIOA_IER; // Interrupt Enable Register + AT91_REG PIOA_IDR; // Interrupt Disable Register + AT91_REG PIOA_IMR; // Interrupt Mask Register + AT91_REG PIOA_ISR; // Interrupt Status Register + AT91_REG PIOA_MDER; // Multi-driver Enable Register + AT91_REG PIOA_MDDR; // Multi-driver Disable Register + AT91_REG PIOA_MDSR; // Multi-driver Status Register + AT91_REG Reserved9[1]; // + AT91_REG PIOA_PPUDR; // Pull-up Disable Register + AT91_REG PIOA_PPUER; // Pull-up Enable Register + AT91_REG PIOA_PPUSR; // Pull-up Status Register + AT91_REG Reserved10[1]; // + AT91_REG PIOA_ASR; // Select A Register + AT91_REG PIOA_BSR; // Select B Register + AT91_REG PIOA_ABSR; // AB Select Status Register + AT91_REG Reserved11[9]; // + AT91_REG PIOA_OWER; // Output Write Enable Register + AT91_REG PIOA_OWDR; // Output Write Disable Register + AT91_REG PIOA_OWSR; // Output Write Status Register + AT91_REG Reserved12[85]; // + AT91_REG PIOB_PER; // PIO Enable Register + AT91_REG PIOB_PDR; // PIO Disable Register + AT91_REG PIOB_PSR; // PIO Status Register + AT91_REG Reserved13[1]; // + AT91_REG PIOB_OER; // Output Enable Register + AT91_REG PIOB_ODR; // Output Disable Registerr + AT91_REG PIOB_OSR; // Output Status Register + AT91_REG Reserved14[1]; // + AT91_REG PIOB_IFER; // Input Filter Enable Register + AT91_REG PIOB_IFDR; // Input Filter Disable Register + AT91_REG PIOB_IFSR; // Input Filter Status Register + AT91_REG Reserved15[1]; // + AT91_REG PIOB_SODR; // Set Output Data Register + AT91_REG PIOB_CODR; // Clear Output Data Register + AT91_REG PIOB_ODSR; // Output Data Status Register + AT91_REG PIOB_PDSR; // Pin Data Status Register + AT91_REG PIOB_IER; // Interrupt Enable Register + AT91_REG PIOB_IDR; // Interrupt Disable Register + AT91_REG PIOB_IMR; // Interrupt Mask Register + AT91_REG PIOB_ISR; // Interrupt Status Register + AT91_REG PIOB_MDER; // Multi-driver Enable Register + AT91_REG PIOB_MDDR; // Multi-driver Disable Register + AT91_REG PIOB_MDSR; // Multi-driver Status Register + AT91_REG Reserved16[1]; // + AT91_REG PIOB_PPUDR; // Pull-up Disable Register + AT91_REG PIOB_PPUER; // Pull-up Enable Register + AT91_REG PIOB_PPUSR; // Pull-up Status Register + AT91_REG Reserved17[1]; // + AT91_REG PIOB_ASR; // Select A Register + AT91_REG PIOB_BSR; // Select B Register + AT91_REG PIOB_ABSR; // AB Select Status Register + AT91_REG Reserved18[9]; // + AT91_REG PIOB_OWER; // Output Write Enable Register + AT91_REG PIOB_OWDR; // Output Write Disable Register + AT91_REG PIOB_OWSR; // Output Write Status Register + AT91_REG Reserved19[341]; // + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved20[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved21[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved22[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved23[3]; // + AT91_REG PMC_PCKR[3]; // Programmable Clock Register + AT91_REG Reserved24[5]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register + AT91_REG Reserved25[36]; // + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register + AT91_REG Reserved26[5]; // + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register + AT91_REG Reserved27[5]; // + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_SYS, *AT91PS_SYS; +#else + +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_AIC { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register +} AT91S_AIC, *AT91PS_AIC; +#else +#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register +#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register +#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register +#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register +#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register +#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register +#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register +#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register +#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register +#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register +#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register +#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register +#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register +#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register +#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect) +#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register +#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register +#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register + +#endif +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PDC { + AT91_REG PDC_RPR; // Receive Pointer Register + AT91_REG PDC_RCR; // Receive Counter Register + AT91_REG PDC_TPR; // Transmit Pointer Register + AT91_REG PDC_TCR; // Transmit Counter Register + AT91_REG PDC_RNPR; // Receive Next Pointer Register + AT91_REG PDC_RNCR; // Receive Next Counter Register + AT91_REG PDC_TNPR; // Transmit Next Pointer Register + AT91_REG PDC_TNCR; // Transmit Next Counter Register + AT91_REG PDC_PTCR; // PDC Transfer Control Register + AT91_REG PDC_PTSR; // PDC Transfer Status Register +} AT91S_PDC, *AT91PS_PDC; +#else +#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register +#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register +#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register +#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register +#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register +#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register +#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register +#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register +#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register +#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register + +#endif +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_DBGU { + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved0[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved1[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register +} AT91S_DBGU, *AT91PS_DBGU; +#else +#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register +#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register +#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register +#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register +#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register +#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register +#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register +#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register +#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register +#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register +#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register +#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register + +#endif +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable +#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PIO { + AT91_REG PIO_PER; // PIO Enable Register + AT91_REG PIO_PDR; // PIO Disable Register + AT91_REG PIO_PSR; // PIO Status Register + AT91_REG Reserved0[1]; // + AT91_REG PIO_OER; // Output Enable Register + AT91_REG PIO_ODR; // Output Disable Registerr + AT91_REG PIO_OSR; // Output Status Register + AT91_REG Reserved1[1]; // + AT91_REG PIO_IFER; // Input Filter Enable Register + AT91_REG PIO_IFDR; // Input Filter Disable Register + AT91_REG PIO_IFSR; // Input Filter Status Register + AT91_REG Reserved2[1]; // + AT91_REG PIO_SODR; // Set Output Data Register + AT91_REG PIO_CODR; // Clear Output Data Register + AT91_REG PIO_ODSR; // Output Data Status Register + AT91_REG PIO_PDSR; // Pin Data Status Register + AT91_REG PIO_IER; // Interrupt Enable Register + AT91_REG PIO_IDR; // Interrupt Disable Register + AT91_REG PIO_IMR; // Interrupt Mask Register + AT91_REG PIO_ISR; // Interrupt Status Register + AT91_REG PIO_MDER; // Multi-driver Enable Register + AT91_REG PIO_MDDR; // Multi-driver Disable Register + AT91_REG PIO_MDSR; // Multi-driver Status Register + AT91_REG Reserved3[1]; // + AT91_REG PIO_PPUDR; // Pull-up Disable Register + AT91_REG PIO_PPUER; // Pull-up Enable Register + AT91_REG PIO_PPUSR; // Pull-up Status Register + AT91_REG Reserved4[1]; // + AT91_REG PIO_ASR; // Select A Register + AT91_REG PIO_BSR; // Select B Register + AT91_REG PIO_ABSR; // AB Select Status Register + AT91_REG Reserved5[9]; // + AT91_REG PIO_OWER; // Output Write Enable Register + AT91_REG PIO_OWDR; // Output Write Disable Register + AT91_REG PIO_OWSR; // Output Write Status Register +} AT91S_PIO, *AT91PS_PIO; +#else +#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register +#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register +#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register +#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register +#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr +#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register +#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register +#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register +#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register +#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register +#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register +#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register +#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register +#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register +#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register +#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register +#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register +#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register +#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register +#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register +#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register +#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register +#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register +#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register +#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register +#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register +#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register +#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register +#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register + +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_CKGR { + AT91_REG CKGR_MOR; // Main Oscillator Register + AT91_REG CKGR_MCFR; // Main Clock Frequency Register + AT91_REG Reserved0[1]; // + AT91_REG CKGR_PLLR; // PLL Register +} AT91S_CKGR, *AT91PS_CKGR; +#else +#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register +#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register +#define CKGR_PLLR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLR) PLL Register + +#endif +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PMC { + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved0[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved1[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved2[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved3[3]; // + AT91_REG PMC_PCKR[3]; // Programmable Clock Register + AT91_REG Reserved4[5]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register +} AT91S_PMC, *AT91PS_PMC; +#else +#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register +#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register +#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register +#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register +#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register +#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register +#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register +#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register +#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register +#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register +#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register +#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register + +#endif +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_RSTC { + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register +} AT91S_RSTC, *AT91PS_RSTC; +#else +#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register +#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register +#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register + +#endif +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset +#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset +#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status +#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status +#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type +#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured. +#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level +#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Length +#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_RTTC { + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register +} AT91S_RTTC, *AT91PS_RTTC; +#else +#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register +#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register +#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register +#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register + +#endif +// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value +// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value +// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PITC { + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register +} AT91S_PITC, *AT91PS_PITC; +#else +#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register +#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register +#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register +#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register + +#endif +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_WDTC { + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register +} AT91S_WDTC, *AT91PS_WDTC; +#else +#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register +#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register +#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register + +#endif +// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart +#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password +// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_VREG { + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_VREG, *AT91PS_VREG; +#else +#define VREG_MR (AT91_CAST(AT91_REG *) 0x00000000) // (VREG_MR) Voltage Regulator Mode Register + +#endif +// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- +#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_MC { + AT91_REG MC_RCR; // MC Remap Control Register + AT91_REG MC_ASR; // MC Abort Status Register + AT91_REG MC_AASR; // MC Abort Address Status Register + AT91_REG Reserved0[1]; // + AT91_REG MC_PUIA[16]; // MC Protection Unit Area + AT91_REG MC_PUP; // MC Protection Unit Peripherals + AT91_REG MC_PUER; // MC Protection Unit Enable Register + AT91_REG Reserved1[2]; // + AT91_REG MC0_FMR; // MC Flash Mode Register + AT91_REG MC0_FCR; // MC Flash Command Register + AT91_REG MC0_FSR; // MC Flash Status Register + AT91_REG MC0_VR; // MC Flash Version Register + AT91_REG MC1_FMR; // MC Flash Mode Register + AT91_REG MC1_FCR; // MC Flash Command Register + AT91_REG MC1_FSR; // MC Flash Status Register + AT91_REG MC1_VR; // MC Flash Version Register +} AT91S_MC, *AT91PS_MC; +#else +#define MC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_RCR) MC Remap Control Register +#define MC_ASR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_ASR) MC Abort Status Register +#define MC_AASR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_AASR) MC Abort Address Status Register +#define MC_PUIA (AT91_CAST(AT91_REG *) 0x00000010) // (MC_PUIA) MC Protection Unit Area +#define MC_PUP (AT91_CAST(AT91_REG *) 0x00000050) // (MC_PUP) MC Protection Unit Peripherals +#define MC_PUER (AT91_CAST(AT91_REG *) 0x00000054) // (MC_PUER) MC Protection Unit Enable Register + +#endif +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_MPU (0x1 << 2) // (MC) Memory protection Unit Abort Status +#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area -------- +#define AT91C_MC_PROT (0x3 << 0) // (MC) Protection +#define AT91C_MC_PROT_PNAUNA (0x0) // (MC) Privilege: No Access, User: No Access +#define AT91C_MC_PROT_PRWUNA (0x1) // (MC) Privilege: Read/Write, User: No Access +#define AT91C_MC_PROT_PRWURO (0x2) // (MC) Privilege: Read/Write, User: Read Only +#define AT91C_MC_PROT_PRWURW (0x3) // (MC) Privilege: Read/Write, User: Read/Write +#define AT91C_MC_SIZE (0xF << 4) // (MC) Internal Area Size +#define AT91C_MC_SIZE_1KB (0x0 << 4) // (MC) Area size 1KByte +#define AT91C_MC_SIZE_2KB (0x1 << 4) // (MC) Area size 2KByte +#define AT91C_MC_SIZE_4KB (0x2 << 4) // (MC) Area size 4KByte +#define AT91C_MC_SIZE_8KB (0x3 << 4) // (MC) Area size 8KByte +#define AT91C_MC_SIZE_16KB (0x4 << 4) // (MC) Area size 16KByte +#define AT91C_MC_SIZE_32KB (0x5 << 4) // (MC) Area size 32KByte +#define AT91C_MC_SIZE_64KB (0x6 << 4) // (MC) Area size 64KByte +#define AT91C_MC_SIZE_128KB (0x7 << 4) // (MC) Area size 128KByte +#define AT91C_MC_SIZE_256KB (0x8 << 4) // (MC) Area size 256KByte +#define AT91C_MC_SIZE_512KB (0x9 << 4) // (MC) Area size 512KByte +#define AT91C_MC_SIZE_1MB (0xA << 4) // (MC) Area size 1MByte +#define AT91C_MC_SIZE_2MB (0xB << 4) // (MC) Area size 2MByte +#define AT91C_MC_SIZE_4MB (0xC << 4) // (MC) Area size 4MByte +#define AT91C_MC_SIZE_8MB (0xD << 4) // (MC) Area size 8MByte +#define AT91C_MC_SIZE_16MB (0xE << 4) // (MC) Area size 16MByte +#define AT91C_MC_SIZE_64MB (0xF << 4) // (MC) Area size 64MByte +#define AT91C_MC_BA (0x3FFFF << 10) // (MC) Internal Area Base Address +// -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral -------- +// -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area -------- +#define AT91C_MC_PUEB (0x1 << 0) // (MC) Protection Unit enable Bit + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Embedded Flash Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_EFC { + AT91_REG EFC_FMR; // MC Flash Mode Register + AT91_REG EFC_FCR; // MC Flash Command Register + AT91_REG EFC_FSR; // MC Flash Status Register + AT91_REG EFC_VR; // MC Flash Version Register +} AT91S_EFC, *AT91PS_EFC; +#else +#define MC_FMR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_FMR) MC Flash Mode Register +#define MC_FCR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_FCR) MC Flash Command Register +#define MC_FSR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_FSR) MC Flash Status Register +#define MC_VR (AT91_CAST(AT91_REG *) 0x0000000C) // (MC_VR) MC Flash Version Register + +#endif +// -------- MC_FMR : (EFC Offset: 0x0) MC Flash Mode Register -------- +#define AT91C_MC_FRDY (0x1 << 0) // (EFC) Flash Ready +#define AT91C_MC_LOCKE (0x1 << 2) // (EFC) Lock Error +#define AT91C_MC_PROGE (0x1 << 3) // (EFC) Programming Error +#define AT91C_MC_NEBP (0x1 << 7) // (EFC) No Erase Before Programming +#define AT91C_MC_FWS (0x3 << 8) // (EFC) Flash Wait State +#define AT91C_MC_FWS_0FWS (0x0 << 8) // (EFC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS (0x1 << 8) // (EFC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS (0x2 << 8) // (EFC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS (0x3 << 8) // (EFC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN (0xFF << 16) // (EFC) Flash Microsecond Cycle Number +// -------- MC_FCR : (EFC Offset: 0x4) MC Flash Command Register -------- +#define AT91C_MC_FCMD (0xF << 0) // (EFC) Flash Command +#define AT91C_MC_FCMD_START_PROG (0x1) // (EFC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK (0x2) // (EFC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (EFC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK (0x4) // (EFC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (EFC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (EFC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (EFC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (EFC) Set Security Bit. +#define AT91C_MC_PAGEN (0x3FF << 8) // (EFC) Page Number +#define AT91C_MC_KEY (0xFF << 24) // (EFC) Writing Protect Key +// -------- MC_FSR : (EFC Offset: 0x8) MC Flash Command Register -------- +#define AT91C_MC_SECURITY (0x1 << 4) // (EFC) Security Bit Status +#define AT91C_MC_GPNVM0 (0x1 << 8) // (EFC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 (0x1 << 9) // (EFC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 (0x1 << 10) // (EFC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 (0x1 << 11) // (EFC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 (0x1 << 12) // (EFC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 (0x1 << 13) // (EFC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 (0x1 << 14) // (EFC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 (0x1 << 15) // (EFC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 (0x1 << 16) // (EFC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 (0x1 << 17) // (EFC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 (0x1 << 18) // (EFC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 (0x1 << 19) // (EFC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 (0x1 << 20) // (EFC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 (0x1 << 21) // (EFC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 (0x1 << 22) // (EFC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 (0x1 << 23) // (EFC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 (0x1 << 24) // (EFC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 (0x1 << 25) // (EFC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 (0x1 << 26) // (EFC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 (0x1 << 27) // (EFC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 (0x1 << 28) // (EFC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 (0x1 << 29) // (EFC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 (0x1 << 30) // (EFC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 (0x1 << 31) // (EFC) Sector 15 Lock Status +// -------- EFC_VR : (EFC Offset: 0xc) EFC version register -------- +#define AT91C_EFC_VERSION (0xFFF << 0) // (EFC) EFC version number +#define AT91C_EFC_MFN (0x7 << 16) // (EFC) EFC MFN + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SPI { + AT91_REG SPI_CR; // Control Register + AT91_REG SPI_MR; // Mode Register + AT91_REG SPI_RDR; // Receive Data Register + AT91_REG SPI_TDR; // Transmit Data Register + AT91_REG SPI_SR; // Status Register + AT91_REG SPI_IER; // Interrupt Enable Register + AT91_REG SPI_IDR; // Interrupt Disable Register + AT91_REG SPI_IMR; // Interrupt Mask Register + AT91_REG Reserved0[4]; // + AT91_REG SPI_CSR[4]; // Chip Select Register + AT91_REG Reserved1[48]; // + AT91_REG SPI_RPR; // Receive Pointer Register + AT91_REG SPI_RCR; // Receive Counter Register + AT91_REG SPI_TPR; // Transmit Pointer Register + AT91_REG SPI_TCR; // Transmit Counter Register + AT91_REG SPI_RNPR; // Receive Next Pointer Register + AT91_REG SPI_RNCR; // Receive Next Counter Register + AT91_REG SPI_TNPR; // Transmit Next Pointer Register + AT91_REG SPI_TNCR; // Transmit Next Counter Register + AT91_REG SPI_PTCR; // PDC Transfer Control Register + AT91_REG SPI_PTSR; // PDC Transfer Status Register +} AT91S_SPI, *AT91PS_SPI; +#else +#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register +#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register +#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register +#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register +#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register +#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register +#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register +#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register +#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register + +#endif +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK +#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_USART { + AT91_REG US_CR; // Control Register + AT91_REG US_MR; // Mode Register + AT91_REG US_IER; // Interrupt Enable Register + AT91_REG US_IDR; // Interrupt Disable Register + AT91_REG US_IMR; // Interrupt Mask Register + AT91_REG US_CSR; // Channel Status Register + AT91_REG US_RHR; // Receiver Holding Register + AT91_REG US_THR; // Transmitter Holding Register + AT91_REG US_BRGR; // Baud Rate Generator Register + AT91_REG US_RTOR; // Receiver Time-out Register + AT91_REG US_TTGR; // Transmitter Time-guard Register + AT91_REG Reserved0[5]; // + AT91_REG US_FIDI; // FI_DI_Ratio Register + AT91_REG US_NER; // Nb Errors Register + AT91_REG Reserved1[1]; // + AT91_REG US_IF; // IRDA_FILTER Register + AT91_REG Reserved2[44]; // + AT91_REG US_RPR; // Receive Pointer Register + AT91_REG US_RCR; // Receive Counter Register + AT91_REG US_TPR; // Transmit Pointer Register + AT91_REG US_TCR; // Transmit Counter Register + AT91_REG US_RNPR; // Receive Next Pointer Register + AT91_REG US_RNCR; // Receive Next Counter Register + AT91_REG US_TNPR; // Transmit Next Pointer Register + AT91_REG US_TNCR; // Transmit Next Counter Register + AT91_REG US_PTCR; // PDC Transfer Control Register + AT91_REG US_PTSR; // PDC Transfer Status Register +} AT91S_USART, *AT91PS_USART; +#else +#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register +#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register +#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register +#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register +#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register +#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register +#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register +#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register +#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register +#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register +#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register +#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register +#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register +#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register + +#endif +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SSC { + AT91_REG SSC_CR; // Control Register + AT91_REG SSC_CMR; // Clock Mode Register + AT91_REG Reserved0[2]; // + AT91_REG SSC_RCMR; // Receive Clock ModeRegister + AT91_REG SSC_RFMR; // Receive Frame Mode Register + AT91_REG SSC_TCMR; // Transmit Clock Mode Register + AT91_REG SSC_TFMR; // Transmit Frame Mode Register + AT91_REG SSC_RHR; // Receive Holding Register + AT91_REG SSC_THR; // Transmit Holding Register + AT91_REG Reserved1[2]; // + AT91_REG SSC_RSHR; // Receive Sync Holding Register + AT91_REG SSC_TSHR; // Transmit Sync Holding Register + AT91_REG Reserved2[2]; // + AT91_REG SSC_SR; // Status Register + AT91_REG SSC_IER; // Interrupt Enable Register + AT91_REG SSC_IDR; // Interrupt Disable Register + AT91_REG SSC_IMR; // Interrupt Mask Register + AT91_REG Reserved3[44]; // + AT91_REG SSC_RPR; // Receive Pointer Register + AT91_REG SSC_RCR; // Receive Counter Register + AT91_REG SSC_TPR; // Transmit Pointer Register + AT91_REG SSC_TCR; // Transmit Counter Register + AT91_REG SSC_RNPR; // Receive Next Pointer Register + AT91_REG SSC_RNCR; // Receive Next Counter Register + AT91_REG SSC_TNPR; // Transmit Next Pointer Register + AT91_REG SSC_TNCR; // Transmit Next Counter Register + AT91_REG SSC_PTCR; // PDC Transfer Control Register + AT91_REG SSC_PTSR; // PDC Transfer Status Register +} AT91S_SSC, *AT91PS_SSC; +#else +#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register +#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register +#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister +#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register +#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register +#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register +#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register +#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register +#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register +#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register +#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register +#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register +#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register +#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register + +#endif +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin +#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TWI { + AT91_REG TWI_CR; // Control Register + AT91_REG TWI_MMR; // Master Mode Register + AT91_REG TWI_SMR; // Slave Mode Register + AT91_REG TWI_IADR; // Internal Address Register + AT91_REG TWI_CWGR; // Clock Waveform Generator Register + AT91_REG Reserved0[3]; // + AT91_REG TWI_SR; // Status Register + AT91_REG TWI_IER; // Interrupt Enable Register + AT91_REG TWI_IDR; // Interrupt Disable Register + AT91_REG TWI_IMR; // Interrupt Mask Register + AT91_REG TWI_RHR; // Receive Holding Register + AT91_REG TWI_THR; // Transmit Holding Register + AT91_REG Reserved1[50]; // + AT91_REG TWI_RPR; // Receive Pointer Register + AT91_REG TWI_RCR; // Receive Counter Register + AT91_REG TWI_TPR; // Transmit Pointer Register + AT91_REG TWI_TCR; // Transmit Counter Register + AT91_REG TWI_RNPR; // Receive Next Pointer Register + AT91_REG TWI_RNCR; // Receive Next Counter Register + AT91_REG TWI_TNPR; // Transmit Next Pointer Register + AT91_REG TWI_TNCR; // Transmit Next Counter Register + AT91_REG TWI_PTCR; // PDC Transfer Control Register + AT91_REG TWI_PTSR; // PDC Transfer Status Register +} AT91S_TWI, *AT91PS_TWI; +#else +#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register +#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register +#define TWI_SMR (AT91_CAST(AT91_REG *) 0x00000008) // (TWI_SMR) Slave Mode Register +#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register +#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register +#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register +#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register +#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register +#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register +#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register +#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register + +#endif +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SVEN (0x1 << 4) // (TWI) TWI Slave mode Enabled +#define AT91C_TWI_SVDIS (0x1 << 5) // (TWI) TWI Slave mode Disabled +#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address +// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- +#define AT91C_TWI_SADR (0x7F << 16) // (TWI) Slave Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP_SLAVE (0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_TXCOMP_MASTER (0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY_MASTER (0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_TXRDY_SLAVE (0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_SVREAD (0x1 << 3) // (TWI) Slave READ (used only in Slave mode) +#define AT91C_TWI_SVACC (0x1 << 4) // (TWI) Slave ACCess (used only in Slave mode) +#define AT91C_TWI_GACC (0x1 << 5) // (TWI) General Call ACcess (used only in Slave mode) +#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error (used only in Master and Multi-master mode) +#define AT91C_TWI_NACK_SLAVE (0x1 << 8) // (TWI) Not Acknowledged +#define AT91C_TWI_NACK_MASTER (0x1 << 8) // (TWI) Not Acknowledged +#define AT91C_TWI_ARBLST_MULTI_MASTER (0x1 << 9) // (TWI) Arbitration Lost (used only in Multimaster mode) +#define AT91C_TWI_SCLWS (0x1 << 10) // (TWI) Clock Wait State (used only in Slave mode) +#define AT91C_TWI_EOSACC (0x1 << 11) // (TWI) End Of Slave ACCess (used only in Slave mode) +#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI) End of Receiver Transfer +#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI) End of Receiver Transfer +#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI) RXBUFF Interrupt +#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI) TXBUFE Interrupt +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PWMC_CH { + AT91_REG PWMC_CMR; // Channel Mode Register + AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register + AT91_REG PWMC_CPRDR; // Channel Period Register + AT91_REG PWMC_CCNTR; // Channel Counter Register + AT91_REG PWMC_CUPDR; // Channel Update Register + AT91_REG PWMC_Reserved[3]; // Reserved +} AT91S_PWMC_CH, *AT91PS_PWMC_CH; +#else +#define PWMC_CMR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_CMR) Channel Mode Register +#define PWMC_CDTYR (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register +#define PWMC_CPRDR (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_CPRDR) Channel Period Register +#define PWMC_CCNTR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_CCNTR) Channel Counter Register +#define PWMC_CUPDR (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_CUPDR) Channel Update Register +#define Reserved (AT91_CAST(AT91_REG *) 0x00000014) // (Reserved) Reserved + +#endif +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PWMC { + AT91_REG PWMC_MR; // PWMC Mode Register + AT91_REG PWMC_ENA; // PWMC Enable Register + AT91_REG PWMC_DIS; // PWMC Disable Register + AT91_REG PWMC_SR; // PWMC Status Register + AT91_REG PWMC_IER; // PWMC Interrupt Enable Register + AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register + AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register + AT91_REG PWMC_ISR; // PWMC Interrupt Status Register + AT91_REG Reserved0[55]; // + AT91_REG PWMC_VR; // PWMC Version Register + AT91_REG Reserved1[64]; // + AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel +} AT91S_PWMC, *AT91PS_PWMC; +#else +#define PWMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_MR) PWMC Mode Register +#define PWMC_ENA (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_ENA) PWMC Enable Register +#define PWMC_DIS (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_DIS) PWMC Disable Register +#define PWMC_SR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_SR) PWMC Status Register +#define PWMC_IER (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register +#define PWMC_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register +#define PWMC_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register +#define PWMC_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register +#define PWMC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (PWMC_VR) PWMC Version Register + +#endif +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_UDP { + AT91_REG UDP_NUM; // Frame Number Register + AT91_REG UDP_GLBSTATE; // Global State Register + AT91_REG UDP_FADDR; // Function Address Register + AT91_REG Reserved0[1]; // + AT91_REG UDP_IER; // Interrupt Enable Register + AT91_REG UDP_IDR; // Interrupt Disable Register + AT91_REG UDP_IMR; // Interrupt Mask Register + AT91_REG UDP_ISR; // Interrupt Status Register + AT91_REG UDP_ICR; // Interrupt Clear Register + AT91_REG Reserved1[1]; // + AT91_REG UDP_RSTEP; // Reset Endpoint Register + AT91_REG Reserved2[1]; // + AT91_REG UDP_CSR[8]; // Endpoint Control and Status Register + AT91_REG UDP_FDR[8]; // Endpoint FIFO Data Register + AT91_REG Reserved3[1]; // + AT91_REG UDP_TXVC; // Transceiver Control Register +} AT91S_UDP, *AT91PS_UDP; +#else +#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register +#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register +#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register +#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register +#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register +#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register +#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register +#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register +#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register +#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register +#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register +#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register + +#endif +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured +#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume +#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_EPINT6 (0x1 << 6) // (UDP) Endpoint 6 Interrupt +#define AT91C_UDP_EPINT7 (0x1 << 7) // (UDP) Endpoint 7 Interrupt +#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5 +#define AT91C_UDP_EP6 (0x1 << 6) // (UDP) Reset Endpoint 6 +#define AT91C_UDP_EP7 (0x1 << 7) // (UDP) Reset Endpoint 7 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints) +#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) +#define AT91C_UDP_PUON (0x1 << 9) // (UDP) Pull-up ON + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TC { + AT91_REG TC_CCR; // Channel Control Register + AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) + AT91_REG Reserved0[2]; // + AT91_REG TC_CV; // Counter Value + AT91_REG TC_RA; // Register A + AT91_REG TC_RB; // Register B + AT91_REG TC_RC; // Register C + AT91_REG TC_SR; // Status Register + AT91_REG TC_IER; // Interrupt Enable Register + AT91_REG TC_IDR; // Interrupt Disable Register + AT91_REG TC_IMR; // Interrupt Mask Register +} AT91S_TC, *AT91PS_TC; +#else +#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register +#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode) +#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value +#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A +#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B +#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C +#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register +#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register +#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register +#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register + +#endif +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE (0x1 << 15) // (TC) +#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger +#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TCB { + AT91S_TC TCB_TC0; // TC Channel 0 + AT91_REG Reserved0[4]; // + AT91S_TC TCB_TC1; // TC Channel 1 + AT91_REG Reserved1[4]; // + AT91S_TC TCB_TC2; // TC Channel 2 + AT91_REG Reserved2[4]; // + AT91_REG TCB_BCR; // TC Block Control Register + AT91_REG TCB_BMR; // TC Block Mode Register +} AT91S_TCB, *AT91PS_TCB; +#else +#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register +#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register + +#endif +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_ADC { + AT91_REG ADC_CR; // ADC Control Register + AT91_REG ADC_MR; // ADC Mode Register + AT91_REG Reserved0[2]; // + AT91_REG ADC_CHER; // ADC Channel Enable Register + AT91_REG ADC_CHDR; // ADC Channel Disable Register + AT91_REG ADC_CHSR; // ADC Channel Status Register + AT91_REG ADC_SR; // ADC Status Register + AT91_REG ADC_LCDR; // ADC Last Converted Data Register + AT91_REG ADC_IER; // ADC Interrupt Enable Register + AT91_REG ADC_IDR; // ADC Interrupt Disable Register + AT91_REG ADC_IMR; // ADC Interrupt Mask Register + AT91_REG ADC_CDR0; // ADC Channel Data Register 0 + AT91_REG ADC_CDR1; // ADC Channel Data Register 1 + AT91_REG ADC_CDR2; // ADC Channel Data Register 2 + AT91_REG ADC_CDR3; // ADC Channel Data Register 3 + AT91_REG ADC_CDR4; // ADC Channel Data Register 4 + AT91_REG ADC_CDR5; // ADC Channel Data Register 5 + AT91_REG ADC_CDR6; // ADC Channel Data Register 6 + AT91_REG ADC_CDR7; // ADC Channel Data Register 7 + AT91_REG Reserved1[44]; // + AT91_REG ADC_RPR; // Receive Pointer Register + AT91_REG ADC_RCR; // Receive Counter Register + AT91_REG ADC_TPR; // Transmit Pointer Register + AT91_REG ADC_TCR; // Transmit Counter Register + AT91_REG ADC_RNPR; // Receive Next Pointer Register + AT91_REG ADC_RNCR; // Receive Next Counter Register + AT91_REG ADC_TNPR; // Transmit Next Pointer Register + AT91_REG ADC_TNCR; // Transmit Next Counter Register + AT91_REG ADC_PTCR; // PDC Transfer Control Register + AT91_REG ADC_PTSR; // PDC Transfer Status Register +} AT91S_ADC, *AT91PS_ADC; +#else +#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register +#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register +#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register +#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register +#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register +#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register +#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register +#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register +#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register +#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register +#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0 +#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1 +#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2 +#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3 +#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4 +#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5 +#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6 +#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7 + +#endif +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR External Bus Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_EBI { + AT91_REG EBI_CSA; // EBI Chip Select Assignment Register +} AT91S_EBI, *AT91PS_EBI; +#else +#define EBI_CSA (AT91_CAST(AT91_REG *) 0x00000000) // (EBI_CSA) EBI Chip Select Assignment Register + +#endif +// -------- EBI_CSA : (EBI Offset: 0x0) Chip Select Assignment Register -------- +#define AT91C_EBI_CS1A (0x1 << 1) // (EBI) Chip Select 1 Assignment +#define AT91C_EBI_CS1A_SMC (0x0 << 1) // (EBI) Chip Select 1 is assigned to the Static Memory Controller. +#define AT91C_EBI_CS1A_SDRAMC (0x1 << 1) // (EBI) Chip Select 1 is assigned to the SDRAM Controller. +#define AT91C_EBI_CS2A (0x1 << 2) // (EBI) Chip Select 2 Assignment +#define AT91C_EBI_CS2A_SMC (0x0 << 2) // (EBI) Chip Select 2 is assigned to the Static Memory Controller and NCS2, NCS5 and NCS6 behave as defined by the SMC. +#define AT91C_EBI_CS2A_SMC_CompactFlash (0x1 << 2) // (EBI) Chip Select 2 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is actived. Accesing the address space reserved to NCS5 and NCS6 may lead to an unpedictable outcome +#define AT91C_EBI_CS3A (0x1 << 3) // (EBI) Chip Select 3 Assignment +#define AT91C_EBI_CS3A_SMC (0x0 << 3) // (EBI) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC2. +#define AT91C_EBI_CS3A_SMC_NandFlash (0x1 << 3) // (EBI) Chip Select 3 is assigned to the Static Memory Controller and the NAND Flash Logic is activated. +#define AT91C_EBI_CS4A (0x1 << 4) // (EBI) Chip Select 4 Assignment +#define AT91C_EBI_CS4A_SMC (0x0 << 4) // (EBI) Chip Select 4 is assigned to the Static Memory Controller and NCS2, NCS5 and NCS6 behave as defined by the SMC. +#define AT91C_EBI_CS4A_SMC_CompactFlash (0x1 << 4) // (EBI) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is actived. Accesing the address space reserved to NCS5 and NCS6 may lead to an unpedictable outcome +#define AT91C_EBI_NWPC (0x1 << 16) // (EBI) NWait Pin Configuration +#define AT91C_EBI_NWPC_OFF (0x0 << 16) // (EBI) The NWAIT device pin is not connected to the External Wait Request input of the Static Memory Controller ,this multiplexe pin can be used as a PIO. +#define AT91C_EBI_NWPC_ON (0x1 << 16) // (EBI) The NWAIT device pin is connected to the External Wait Request input of the Static Memory Controller. + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SMC2 { + AT91_REG SMC2_CSR[8]; // SMC2 Chip Select Register +} AT91S_SMC2, *AT91PS_SMC2; +#else +#define SMC2_CSR (AT91_CAST(AT91_REG *) 0x00000000) // (SMC2_CSR) SMC2 Chip Select Register + +#endif +// -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register -------- +#define AT91C_SMC2_NWS (0x7F << 0) // (SMC2) Number of Wait States +#define AT91C_SMC2_WSEN (0x1 << 7) // (SMC2) Wait State Enable +#define AT91C_SMC2_TDF (0xF << 8) // (SMC2) Data Float Time +#define AT91C_SMC2_BAT (0x1 << 12) // (SMC2) Byte Access Type +#define AT91C_SMC2_DBW (0x1 << 13) // (SMC2) Data Bus Width +#define AT91C_SMC2_DBW_16 (0x1 << 13) // (SMC2) 16-bit. +#define AT91C_SMC2_DBW_8 (0x2 << 13) // (SMC2) 8-bit. +#define AT91C_SMC2_DRP (0x1 << 15) // (SMC2) Data Read Protocol +#define AT91C_SMC2_ACSS (0x3 << 16) // (SMC2) Address to Chip Select Setup +#define AT91C_SMC2_ACSS_STANDARD (0x0 << 16) // (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. +#define AT91C_SMC2_ACSS_1_CYCLE (0x1 << 16) // (SMC2) One cycle less at the beginning and the end of the access. +#define AT91C_SMC2_ACSS_2_CYCLES (0x2 << 16) // (SMC2) Two cycles less at the beginning and the end of the access. +#define AT91C_SMC2_ACSS_3_CYCLES (0x3 << 16) // (SMC2) Three cycles less at the beginning and the end of the access. +#define AT91C_SMC2_RWSETUP (0x7 << 24) // (SMC2) Read and Write Signal Setup Time +#define AT91C_SMC2_RWHOLD (0x7 << 28) // (SMC2) Read and Write Signal Hold Time + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR SDRAM Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SDRC { + AT91_REG SDRC_MR; // SDRAM Controller Mode Register + AT91_REG SDRC_TR; // SDRAM Controller Refresh Timer Register + AT91_REG SDRC_CR; // SDRAM Controller Configuration Register + AT91_REG SDRC_SRR; // SDRAM Controller Self Refresh Register + AT91_REG SDRC_LPR; // SDRAM Controller Low Power Register + AT91_REG SDRC_IER; // SDRAM Controller Interrupt Enable Register + AT91_REG SDRC_IDR; // SDRAM Controller Interrupt Disable Register + AT91_REG SDRC_IMR; // SDRAM Controller Interrupt Mask Register + AT91_REG SDRC_ISR; // SDRAM Controller Interrupt Mask Register + AT91_REG SDRC_VER; // SDRAM Controller Version Register +} AT91S_SDRC, *AT91PS_SDRC; +#else +#define SDRC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (SDRC_MR) SDRAM Controller Mode Register +#define SDRC_TR (AT91_CAST(AT91_REG *) 0x00000004) // (SDRC_TR) SDRAM Controller Refresh Timer Register +#define SDRC_CR (AT91_CAST(AT91_REG *) 0x00000008) // (SDRC_CR) SDRAM Controller Configuration Register +#define SDRC_SRR (AT91_CAST(AT91_REG *) 0x0000000C) // (SDRC_SRR) SDRAM Controller Self Refresh Register +#define SDRC_LPR (AT91_CAST(AT91_REG *) 0x00000010) // (SDRC_LPR) SDRAM Controller Low Power Register +#define SDRC_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SDRC_IER) SDRAM Controller Interrupt Enable Register +#define SDRC_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SDRC_IDR) SDRAM Controller Interrupt Disable Register +#define SDRC_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SDRC_IMR) SDRAM Controller Interrupt Mask Register +#define SDRC_ISR (AT91_CAST(AT91_REG *) 0x00000020) // (SDRC_ISR) SDRAM Controller Interrupt Mask Register +#define IPB_VER (AT91_CAST(AT91_REG *) 0x00000024) // (IPB_VER) SDRAM Controller Version Register + +#endif +// -------- SDRC_MR : (SDRC Offset: 0x0) SDRAM Controller Mode Register -------- +#define AT91C_SDRC_MODE (0xF << 0) // (SDRC) Mode +#define AT91C_SDRC_MODE_NORMAL_CMD (0x0) // (SDRC) Normal Mode +#define AT91C_SDRC_MODE_NOP_CMD (0x1) // (SDRC) NOP Command +#define AT91C_SDRC_MODE_PRCGALL_CMD (0x2) // (SDRC) All Banks Precharge Command +#define AT91C_SDRC_MODE_LMR_CMD (0x3) // (SDRC) Load Mode Register Command +#define AT91C_SDRC_MODE_RFSH_CMD (0x4) // (SDRC) Refresh Command +#define AT91C_SDRC_DBW (0x1 << 4) // (SDRC) Data Bus Width +#define AT91C_SDRC_DBW_32_BITS (0x0 << 4) // (SDRC) 32 Bits datas bus +#define AT91C_SDRC_DBW_16_BITS (0x1 << 4) // (SDRC) 16 Bits datas bus +// -------- SDRC_TR : (SDRC Offset: 0x4) SDRC Refresh Timer Register -------- +#define AT91C_SDRC_COUNT (0xFFF << 0) // (SDRC) Refresh Counter +// -------- SDRC_CR : (SDRC Offset: 0x8) SDRAM Configuration Register -------- +#define AT91C_SDRC_NC (0x3 << 0) // (SDRC) Number of Column Bits +#define AT91C_SDRC_NC_8 (0x0) // (SDRC) 8 Bits +#define AT91C_SDRC_NC_9 (0x1) // (SDRC) 9 Bits +#define AT91C_SDRC_NC_10 (0x2) // (SDRC) 10 Bits +#define AT91C_SDRC_NC_11 (0x3) // (SDRC) 11 Bits +#define AT91C_SDRC_NR (0x3 << 2) // (SDRC) Number of Row Bits +#define AT91C_SDRC_NR_11 (0x0 << 2) // (SDRC) 11 Bits +#define AT91C_SDRC_NR_12 (0x1 << 2) // (SDRC) 12 Bits +#define AT91C_SDRC_NR_13 (0x2 << 2) // (SDRC) 13 Bits +#define AT91C_SDRC_NB (0x1 << 4) // (SDRC) Number of Banks +#define AT91C_SDRC_NB_2_BANKS (0x0 << 4) // (SDRC) 2 banks +#define AT91C_SDRC_NB_4_BANKS (0x1 << 4) // (SDRC) 4 banks +#define AT91C_SDRC_CAS (0x3 << 5) // (SDRC) CAS Latency +#define AT91C_SDRC_CAS_2 (0x2 << 5) // (SDRC) 2 cycles +#define AT91C_SDRC_TWR (0xF << 7) // (SDRC) Number of Write Recovery Time Cycles +#define AT91C_SDRC_TRC (0xF << 11) // (SDRC) Number of RAS Cycle Time Cycles +#define AT91C_SDRC_TRP (0xF << 15) // (SDRC) Number of RAS Precharge Time Cycles +#define AT91C_SDRC_TRCD (0xF << 19) // (SDRC) Number of RAS to CAS Delay Cycles +#define AT91C_SDRC_TRAS (0xF << 23) // (SDRC) Number of RAS Active Time Cycles +#define AT91C_SDRC_TXSR (0xF << 27) // (SDRC) Number of Command Recovery Time Cycles +// -------- SDRC_SRR : (SDRC Offset: 0xc) SDRAM Controller Self-refresh Register -------- +#define AT91C_SDRC_SRCB (0x1 << 0) // (SDRC) Self-refresh Command Bit +// -------- SDRC_LPR : (SDRC Offset: 0x10) SDRAM Controller Low-power Register -------- +#define AT91C_SDRC_LPCB (0x1 << 0) // (SDRC) Low-power Command Bit +// -------- SDRC_IER : (SDRC Offset: 0x14) SDRAM Controller Interrupt Enable Register -------- +#define AT91C_SDRC_RES (0x1 << 0) // (SDRC) Refresh Error Status +// -------- SDRC_IDR : (SDRC Offset: 0x18) SDRAM Controller Interrupt Disable Register -------- +// -------- SDRC_IMR : (SDRC Offset: 0x1c) SDRAM Controller Interrupt Mask Register -------- +// -------- SDRC_ISR : (SDRC Offset: 0x20) SDRAM Controller Interrupt Status Register -------- +// -------- IPB_VER : (SDRC Offset: 0x24) SDRAM Controller IP version Register -------- +#define AT91C_SDRC_VERSION (0xFFF << 0) // (SDRC) IP version of the macrocell +#define AT91C_SDRC_MFN (0x7 << 1) // (SDRC) + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Error Correction Code controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_ECC { + AT91_REG ECC_CR; // ECC reset register + AT91_REG ECC_MR; // ECC Page size register + AT91_REG ECC_SR; // ECC Status register + AT91_REG ECC_PR; // ECC Parity register + AT91_REG ECC_NPR; // ECC Parity N register + AT91_REG ECC_VR; // ECC Version register +} AT91S_ECC, *AT91PS_ECC; +#else +#define ECC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ECC_CR) ECC reset register +#define ECC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ECC_MR) ECC Page size register +#define ECC_SR (AT91_CAST(AT91_REG *) 0x00000008) // (ECC_SR) ECC Status register +#define ECC_PR (AT91_CAST(AT91_REG *) 0x0000000C) // (ECC_PR) ECC Parity register +#define ECC_NPR (AT91_CAST(AT91_REG *) 0x00000010) // (ECC_NPR) ECC Parity N register +#define ECC_VR (AT91_CAST(AT91_REG *) 0x00000014) // (ECC_VR) ECC Version register + +#endif +// -------- ECC_CR : (ECC Offset: 0x0) ECC reset register -------- +#define AT91C_ECC_RST (0x1 << 0) // (ECC) ECC reset parity +// -------- ECC_MR : (ECC Offset: 0x4) ECC page size register -------- +#define AT91C_ECC_PAGE_SIZE (0x3 << 0) // (ECC) Nand Flash page size +// -------- ECC_SR : (ECC Offset: 0x8) ECC status register -------- +#define AT91C_ECC_RECERR (0x1 << 0) // (ECC) ECC error +#define AT91C_ECC_ECCERR (0x1 << 1) // (ECC) ECC single error +#define AT91C_ECC_MULERR (0x1 << 2) // (ECC) ECC_MULERR +// -------- ECC_PR : (ECC Offset: 0xc) ECC parity register -------- +#define AT91C_ECC_BITADDR (0xF << 0) // (ECC) Bit address error +#define AT91C_ECC_WORDADDR (0xFFF << 4) // (ECC) address of the failing bit +// -------- ECC_NPR : (ECC Offset: 0x10) ECC N parity register -------- +#define AT91C_ECC_NPARITY (0xFFFF << 0) // (ECC) ECC parity N +// -------- ECC_VR : (ECC Offset: 0x14) ECC version register -------- +#define AT91C_ECC_VERSION (0xFFF << 0) // (ECC) ECC version number +#define AT91C_ECC_MFN (0x7 << 16) // (ECC) ECC MFN + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7SE512 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register +#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register +#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register +#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register +// ========== Register definition for PIOB peripheral ========== +#define AT91C_PIOB_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register +#define AT91C_PIOB_MDER (AT91_CAST(AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register +#define AT91C_PIOB_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register +#define AT91C_PIOB_IMR (AT91_CAST(AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register +#define AT91C_PIOB_ASR (AT91_CAST(AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register +#define AT91C_PIOB_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register +#define AT91C_PIOB_PSR (AT91_CAST(AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register +#define AT91C_PIOB_IER (AT91_CAST(AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register +#define AT91C_PIOB_CODR (AT91_CAST(AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register +#define AT91C_PIOB_OWER (AT91_CAST(AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register +#define AT91C_PIOB_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register +#define AT91C_PIOB_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register +#define AT91C_PIOB_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register +#define AT91C_PIOB_IDR (AT91_CAST(AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register +#define AT91C_PIOB_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register +#define AT91C_PIOB_PDR (AT91_CAST(AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register +#define AT91C_PIOB_ODR (AT91_CAST(AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr +#define AT91C_PIOB_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register +#define AT91C_PIOB_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register +#define AT91C_PIOB_SODR (AT91_CAST(AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register +#define AT91C_PIOB_ISR (AT91_CAST(AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register +#define AT91C_PIOB_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register +#define AT91C_PIOB_OSR (AT91_CAST(AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register +#define AT91C_PIOB_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register +#define AT91C_PIOB_IFER (AT91_CAST(AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register +#define AT91C_PIOB_BSR (AT91_CAST(AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register +#define AT91C_PIOB_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register +#define AT91C_PIOB_OER (AT91_CAST(AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register +#define AT91C_PIOB_PER (AT91_CAST(AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register +// ========== Register definition for PIOC peripheral ========== +#define AT91C_PIOC_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF8A4) // (PIOC) Output Write Disable Register +#define AT91C_PIOC_SODR (AT91_CAST(AT91_REG *) 0xFFFFF830) // (PIOC) Set Output Data Register +#define AT91C_PIOC_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF864) // (PIOC) Pull-up Enable Register +#define AT91C_PIOC_CODR (AT91_CAST(AT91_REG *) 0xFFFFF834) // (PIOC) Clear Output Data Register +#define AT91C_PIOC_PSR (AT91_CAST(AT91_REG *) 0xFFFFF808) // (PIOC) PIO Status Register +#define AT91C_PIOC_PDR (AT91_CAST(AT91_REG *) 0xFFFFF804) // (PIOC) PIO Disable Register +#define AT91C_PIOC_ODR (AT91_CAST(AT91_REG *) 0xFFFFF814) // (PIOC) Output Disable Registerr +#define AT91C_PIOC_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF868) // (PIOC) Pull-up Status Register +#define AT91C_PIOC_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF878) // (PIOC) AB Select Status Register +#define AT91C_PIOC_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF828) // (PIOC) Input Filter Status Register +#define AT91C_PIOC_OER (AT91_CAST(AT91_REG *) 0xFFFFF810) // (PIOC) Output Enable Register +#define AT91C_PIOC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF848) // (PIOC) Interrupt Mask Register +#define AT91C_PIOC_ASR (AT91_CAST(AT91_REG *) 0xFFFFF870) // (PIOC) Select A Register +#define AT91C_PIOC_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF854) // (PIOC) Multi-driver Disable Register +#define AT91C_PIOC_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF8A8) // (PIOC) Output Write Status Register +#define AT91C_PIOC_PER (AT91_CAST(AT91_REG *) 0xFFFFF800) // (PIOC) PIO Enable Register +#define AT91C_PIOC_IDR (AT91_CAST(AT91_REG *) 0xFFFFF844) // (PIOC) Interrupt Disable Register +#define AT91C_PIOC_MDER (AT91_CAST(AT91_REG *) 0xFFFFF850) // (PIOC) Multi-driver Enable Register +#define AT91C_PIOC_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF83C) // (PIOC) Pin Data Status Register +#define AT91C_PIOC_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF858) // (PIOC) Multi-driver Status Register +#define AT91C_PIOC_OWER (AT91_CAST(AT91_REG *) 0xFFFFF8A0) // (PIOC) Output Write Enable Register +#define AT91C_PIOC_BSR (AT91_CAST(AT91_REG *) 0xFFFFF874) // (PIOC) Select B Register +#define AT91C_PIOC_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF860) // (PIOC) Pull-up Disable Register +#define AT91C_PIOC_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF824) // (PIOC) Input Filter Disable Register +#define AT91C_PIOC_IER (AT91_CAST(AT91_REG *) 0xFFFFF840) // (PIOC) Interrupt Enable Register +#define AT91C_PIOC_OSR (AT91_CAST(AT91_REG *) 0xFFFFF818) // (PIOC) Output Status Register +#define AT91C_PIOC_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF838) // (PIOC) Output Data Status Register +#define AT91C_PIOC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF84C) // (PIOC) Interrupt Status Register +#define AT91C_PIOC_IFER (AT91_CAST(AT91_REG *) 0xFFFFF820) // (PIOC) Input Filter Enable Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register +#define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register +#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register +#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register +#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register +#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register +// ========== Register definition for VREG peripheral ========== +#define AT91C_VREG_MR (AT91_CAST(AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_ASR (AT91_CAST(AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register +#define AT91C_MC_PUP (AT91_CAST(AT91_REG *) 0xFFFFFF50) // (MC) MC Protection Unit Peripherals +#define AT91C_MC_PUIA (AT91_CAST(AT91_REG *) 0xFFFFFF10) // (MC) MC Protection Unit Area +#define AT91C_MC_AASR (AT91_CAST(AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_PUER (AT91_CAST(AT91_REG *) 0xFFFFFF54) // (MC) MC Protection Unit Enable Register +// ========== Register definition for EFC0 peripheral ========== +#define AT91C_EFC0_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF64) // (EFC0) MC Flash Command Register +#define AT91C_EFC0_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF68) // (EFC0) MC Flash Status Register +#define AT91C_EFC0_VR (AT91_CAST(AT91_REG *) 0xFFFFFF6C) // (EFC0) MC Flash Version Register +#define AT91C_EFC0_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF60) // (EFC0) MC Flash Mode Register +// ========== Register definition for EFC1 peripheral ========== +#define AT91C_EFC1_VR (AT91_CAST(AT91_REG *) 0xFFFFFF7C) // (EFC1) MC Flash Version Register +#define AT91C_EFC1_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF74) // (EFC1) MC Flash Command Register +#define AT91C_EFC1_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF78) // (EFC1) MC Flash Status Register +#define AT91C_EFC1_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF70) // (EFC1) MC Flash Mode Register +// ========== Register definition for PDC_SPI peripheral ========== +#define AT91C_SPI_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register +#define AT91C_SPI_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register +#define AT91C_SPI_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register +#define AT91C_SPI_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register +#define AT91C_SPI_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register +#define AT91C_SPI_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register +#define AT91C_SPI_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register +#define AT91C_SPI_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register +#define AT91C_SPI_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register +#define AT91C_SPI_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register +// ========== Register definition for SPI peripheral ========== +#define AT91C_SPI_IER (AT91_CAST(AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register +#define AT91C_SPI_SR (AT91_CAST(AT91_REG *) 0xFFFE0010) // (SPI) Status Register +#define AT91C_SPI_IDR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register +#define AT91C_SPI_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (SPI) Control Register +#define AT91C_SPI_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (SPI) Mode Register +#define AT91C_SPI_IMR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register +#define AT91C_SPI_TDR (AT91_CAST(AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register +#define AT91C_SPI_RDR (AT91_CAST(AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register +#define AT91C_SPI_CSR (AT91_CAST(AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (US1) Control Register +#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register +#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register +#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register +#define AT91C_SSC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RHR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_RSHR (AT91_CAST(AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_TFMR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register +#define AT91C_SSC_IDR (AT91_CAST(AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_THR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_RCMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_IER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_TSHR (AT91_CAST(AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_SR (AT91_CAST(AT91_REG *) 0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_CMR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_TCMR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR (AT91_CAST(AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_RFMR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_IER (AT91_CAST(AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_SR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_IMR (AT91_CAST(AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_THR (AT91_CAST(AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IDR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_IADR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register +#define AT91C_TWI_CWGR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_RHR (AT91_CAST(AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register +#define AT91C_TWI_SMR (AT91_CAST(AT91_REG *) 0xFFFB8008) // (TWI) Slave Mode Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_CH3_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_CH3_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_CH3_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_CH3_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +#define AT91C_CH3_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_CH3_CMR (AT91_CAST(AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_CH2_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_CH2_CMR (AT91_CAST(AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_CH2_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_CH2_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_CH2_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_CH2_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_CH1_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_CH1_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_CH1_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_CH1_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_CH1_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +#define AT91C_CH1_CMR (AT91_CAST(AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_CH0_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_CH0_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_CH0_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +#define AT91C_CH0_CMR (AT91_CAST(AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_CH0_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_CH0_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_IDR (AT91_CAST(AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_DIS (AT91_CAST(AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER (AT91_CAST(AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +#define AT91C_PWMC_VR (AT91_CAST(AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_SR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_IMR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_ENA (AT91_CAST(AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register +#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register +#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register +#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register +#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register +#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register +#define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register +// ========== Register definition for EBI peripheral ========== +#define AT91C_EBI_CSA (AT91_CAST(AT91_REG *) 0xFFFFFF80) // (EBI) EBI Chip Select Assignment Register +// ========== Register definition for SMC peripheral ========== +#define AT91C_SMC_CSR (AT91_CAST(AT91_REG *) 0xFFFFFF90) // (SMC) SMC2 Chip Select Register +// ========== Register definition for SDRC peripheral ========== +#define AT91C_SDRC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFFC8) // (SDRC) SDRAM Controller Interrupt Disable Register +#define AT91C_SDRC_TR (AT91_CAST(AT91_REG *) 0xFFFFFFB4) // (SDRC) SDRAM Controller Refresh Timer Register +#define AT91C_SDRC_SRR (AT91_CAST(AT91_REG *) 0xFFFFFFBC) // (SDRC) SDRAM Controller Self Refresh Register +#define AT91C_SDRC_MR (AT91_CAST(AT91_REG *) 0xFFFFFFB0) // (SDRC) SDRAM Controller Mode Register +#define AT91C_SDRC_CR (AT91_CAST(AT91_REG *) 0xFFFFFFB8) // (SDRC) SDRAM Controller Configuration Register +#define AT91C_SDRC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFFCC) // (SDRC) SDRAM Controller Interrupt Mask Register +#define AT91C_SDRC_LPR (AT91_CAST(AT91_REG *) 0xFFFFFFC0) // (SDRC) SDRAM Controller Low Power Register +#define AT91C_SDRC_ISR (AT91_CAST(AT91_REG *) 0xFFFFFFD0) // (SDRC) SDRAM Controller Interrupt Mask Register +#define AT91C_SDRC_VER (AT91_CAST(AT91_REG *) 0xFFFFFFD4) // (SDRC) SDRAM Controller Version Register +#define AT91C_SDRC_IER (AT91_CAST(AT91_REG *) 0xFFFFFFC4) // (SDRC) SDRAM Controller Interrupt Enable Register +// ========== Register definition for HECC peripheral ========== +#define AT91C_HECC_MR (AT91_CAST(AT91_REG *) 0xFFFFFFE0) // (HECC) ECC Page size register +#define AT91C_HECC_CR (AT91_CAST(AT91_REG *) 0xFFFFFFDC) // (HECC) ECC reset register +#define AT91C_HECC_SR (AT91_CAST(AT91_REG *) 0xFFFFFFE4) // (HECC) ECC Status register +#define AT91C_HECC_VR (AT91_CAST(AT91_REG *) 0xFFFFFFF0) // (HECC) ECC Version register +#define AT91C_HECC_NPR (AT91_CAST(AT91_REG *) 0xFFFFFFEC) // (HECC) ECC Parity N register +#define AT91C_HECC_PR (AT91_CAST(AT91_REG *) 0xFFFFFFE8) // (HECC) ECC Parity register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7SE512 +// ***************************************************************************** +#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_PWM0 (AT91C_PIO_PA0) // +#define AT91C_PA0_A0_NBS0 (AT91C_PIO_PA0) // +#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_PWM1 (AT91C_PIO_PA1) // +#define AT91C_PA1_A1_NBS2 (AT91C_PIO_PA1) // +#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_DTXD (AT91C_PIO_PA10) // +#define AT91C_PA10_A10 (AT91C_PIO_PA10) // +#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_NPCS0 (AT91C_PIO_PA11) // +#define AT91C_PA11_A11 (AT91C_PIO_PA11) // +#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_MISO (AT91C_PIO_PA12) // +#define AT91C_PA12_A12 (AT91C_PIO_PA12) // +#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_MOSI (AT91C_PIO_PA13) // +#define AT91C_PA13_A13 (AT91C_PIO_PA13) // +#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_SPCK (AT91C_PIO_PA14) // +#define AT91C_PA14_A14 (AT91C_PIO_PA14) // +#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_TF (AT91C_PIO_PA15) // +#define AT91C_PA15_A15 (AT91C_PIO_PA15) // +#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_TK (AT91C_PIO_PA16) // +#define AT91C_PA16_A16_BA0 (AT91C_PIO_PA16) // +#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_TD (AT91C_PIO_PA17) // +#define AT91C_PA17_A17_BA1 (AT91C_PIO_PA17) // +#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_RD (AT91C_PIO_PA18) // +#define AT91C_PA18_NBS3_CFIOW (AT91C_PIO_PA18) // +#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_RK (AT91C_PIO_PA19) // +#define AT91C_PA19_NCS4_CFCS0 (AT91C_PIO_PA19) // +#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_PWM2 (AT91C_PIO_PA2) // +#define AT91C_PA2_A2 (AT91C_PIO_PA2) // +#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_RF (AT91C_PIO_PA20) // +#define AT91C_PA20_NCS2_CFCS1 (AT91C_PIO_PA20) // +#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_RXD1 (AT91C_PIO_PA21) // +#define AT91C_PA21_NCS6_CFCE2 (AT91C_PIO_PA21) // +#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TXD1 (AT91C_PIO_PA22) // +#define AT91C_PA22_NCS5_CFCE1 (AT91C_PIO_PA22) // +#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_SCK1 (AT91C_PIO_PA23) // +#define AT91C_PA23_NWR1_NBS1_CFIOR_NUB (AT91C_PIO_PA23) // +#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RTS1 (AT91C_PIO_PA24) // +#define AT91C_PA24_SDA10 (AT91C_PIO_PA24) // +#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_CTS1 (AT91C_PIO_PA25) // +#define AT91C_PA25_SDCKE (AT91C_PIO_PA25) // +#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_DCD1 (AT91C_PIO_PA26) // +#define AT91C_PA26_NCS1_SDCS (AT91C_PIO_PA26) // +#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DTR1 (AT91C_PIO_PA27) // +#define AT91C_PA27_SDWE (AT91C_PIO_PA27) // +#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DSR1 (AT91C_PIO_PA28) // +#define AT91C_PA28_CAS (AT91C_PIO_PA28) // +#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_RI1 (AT91C_PIO_PA29) // +#define AT91C_PA29_RAS (AT91C_PIO_PA29) // +#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_TWD (AT91C_PIO_PA3) // +#define AT91C_PA3_A3 (AT91C_PIO_PA3) // +#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ1 (AT91C_PIO_PA30) // +#define AT91C_PA30_D30 (AT91C_PIO_PA30) // +#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31 +#define AT91C_PA31_NPCS1 (AT91C_PIO_PA31) // +#define AT91C_PA31_D31 (AT91C_PIO_PA31) // +#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_TWCK (AT91C_PIO_PA4) // +#define AT91C_PA4_A4 (AT91C_PIO_PA4) // +#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD0 (AT91C_PIO_PA5) // +#define AT91C_PA5_A5 (AT91C_PIO_PA5) // +#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD0 (AT91C_PIO_PA6) // +#define AT91C_PA6_A6 (AT91C_PIO_PA6) // +#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_RTS0 (AT91C_PIO_PA7) // +#define AT91C_PA7_A7 (AT91C_PIO_PA7) // +#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_CTS0 (AT91C_PIO_PA8) // +#define AT91C_PA8_A8 (AT91C_PIO_PA8) // +#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_DRXD (AT91C_PIO_PA9) // +#define AT91C_PA9_A9 (AT91C_PIO_PA9) // +#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0 +#define AT91C_PB0_TIOA0 (AT91C_PIO_PB0) // +#define AT91C_PB0_A0_NBS0 (AT91C_PIO_PB0) // +#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1 +#define AT91C_PB1_TIOB0 (AT91C_PIO_PB1) // +#define AT91C_PB1_A1_NBS2 (AT91C_PIO_PB1) // +#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10 +#define AT91C_PB10_NPCS2 (AT91C_PIO_PB10) // +#define AT91C_PB10_A10 (AT91C_PIO_PB10) // +#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11 +#define AT91C_PB11_PWM0 (AT91C_PIO_PB11) // +#define AT91C_PB11_A11 (AT91C_PIO_PB11) // +#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12 +#define AT91C_PB12_PWM1 (AT91C_PIO_PB12) // +#define AT91C_PB12_A12 (AT91C_PIO_PB12) // +#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13 +#define AT91C_PB13_PWM2 (AT91C_PIO_PB13) // +#define AT91C_PB13_A13 (AT91C_PIO_PB13) // +#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14 +#define AT91C_PB14_PWM3 (AT91C_PIO_PB14) // +#define AT91C_PB14_A14 (AT91C_PIO_PB14) // +#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15 +#define AT91C_PB15_TIOA1 (AT91C_PIO_PB15) // +#define AT91C_PB15_A15 (AT91C_PIO_PB15) // +#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16 +#define AT91C_PB16_TIOB1 (AT91C_PIO_PB16) // +#define AT91C_PB16_A16_BA0 (AT91C_PIO_PB16) // +#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17 +#define AT91C_PB17_PCK1 (AT91C_PIO_PB17) // +#define AT91C_PB17_A17_BA1 (AT91C_PIO_PB17) // +#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18 +#define AT91C_PB18_PCK2 (AT91C_PIO_PB18) // +#define AT91C_PB18_D16 (AT91C_PIO_PB18) // +#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19 +#define AT91C_PB19_FIQ (AT91C_PIO_PB19) // +#define AT91C_PB19_D17 (AT91C_PIO_PB19) // +#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2 +#define AT91C_PB2_SCK0 (AT91C_PIO_PB2) // +#define AT91C_PB2_A2 (AT91C_PIO_PB2) // +#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20 +#define AT91C_PB20_IRQ0 (AT91C_PIO_PB20) // +#define AT91C_PB20_D18 (AT91C_PIO_PB20) // +#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21 +#define AT91C_PB21_PCK1 (AT91C_PIO_PB21) // +#define AT91C_PB21_D19 (AT91C_PIO_PB21) // +#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22 +#define AT91C_PB22_NPCS3 (AT91C_PIO_PB22) // +#define AT91C_PB22_D20 (AT91C_PIO_PB22) // +#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23 +#define AT91C_PB23_PWM0 (AT91C_PIO_PB23) // +#define AT91C_PB23_D21 (AT91C_PIO_PB23) // +#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24 +#define AT91C_PB24_PWM1 (AT91C_PIO_PB24) // +#define AT91C_PB24_D22 (AT91C_PIO_PB24) // +#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25 +#define AT91C_PB25_PWM2 (AT91C_PIO_PB25) // +#define AT91C_PB25_D23 (AT91C_PIO_PB25) // +#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26 +#define AT91C_PB26_TIOA2 (AT91C_PIO_PB26) // +#define AT91C_PB26_D24 (AT91C_PIO_PB26) // +#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27 +#define AT91C_PB27_TIOB2 (AT91C_PIO_PB27) // +#define AT91C_PB27_D25 (AT91C_PIO_PB27) // +#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28 +#define AT91C_PB28_TCLK1 (AT91C_PIO_PB28) // +#define AT91C_PB28_D26 (AT91C_PIO_PB28) // +#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29 +#define AT91C_PB29_TCLK2 (AT91C_PIO_PB29) // +#define AT91C_PB29_D27 (AT91C_PIO_PB29) // +#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3 +#define AT91C_PB3_NPCS3 (AT91C_PIO_PB3) // +#define AT91C_PB3_A3 (AT91C_PIO_PB3) // +#define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30 +#define AT91C_PB30_NPCS2 (AT91C_PIO_PB30) // +#define AT91C_PB30_D28 (AT91C_PIO_PB30) // +#define AT91C_PIO_PB31 (1 << 31) // Pin Controlled by PB31 +#define AT91C_PB31_PCK2 (AT91C_PIO_PB31) // +#define AT91C_PB31_D29 (AT91C_PIO_PB31) // +#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4 +#define AT91C_PB4_TCLK0 (AT91C_PIO_PB4) // +#define AT91C_PB4_A4 (AT91C_PIO_PB4) // +#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5 +#define AT91C_PB5_NPCS3 (AT91C_PIO_PB5) // +#define AT91C_PB5_A5 (AT91C_PIO_PB5) // +#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6 +#define AT91C_PB6_PCK0 (AT91C_PIO_PB6) // +#define AT91C_PB6_A6 (AT91C_PIO_PB6) // +#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7 +#define AT91C_PB7_PWM3 (AT91C_PIO_PB7) // +#define AT91C_PB7_A7 (AT91C_PIO_PB7) // +#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8 +#define AT91C_PB8_ADTRG (AT91C_PIO_PB8) // +#define AT91C_PB8_A8 (AT91C_PIO_PB8) // +#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9 +#define AT91C_PB9_NPCS1 (AT91C_PIO_PB9) // +#define AT91C_PB9_A9 (AT91C_PIO_PB9) // +#define AT91C_PIO_PC0 (1 << 0) // Pin Controlled by PC0 +#define AT91C_PC0_D0 (AT91C_PIO_PC0) // +#define AT91C_PIO_PC1 (1 << 1) // Pin Controlled by PC1 +#define AT91C_PC1_D1 (AT91C_PIO_PC1) // +#define AT91C_PIO_PC10 (1 << 10) // Pin Controlled by PC10 +#define AT91C_PC10_D10 (AT91C_PIO_PC10) // +#define AT91C_PC10_PCK0 (AT91C_PIO_PC10) // +#define AT91C_PIO_PC11 (1 << 11) // Pin Controlled by PC11 +#define AT91C_PC11_D11 (AT91C_PIO_PC11) // +#define AT91C_PC11_PCK1 (AT91C_PIO_PC11) // +#define AT91C_PIO_PC12 (1 << 12) // Pin Controlled by PC12 +#define AT91C_PC12_D12 (AT91C_PIO_PC12) // +#define AT91C_PC12_PCK2 (AT91C_PIO_PC12) // +#define AT91C_PIO_PC13 (1 << 13) // Pin Controlled by PC13 +#define AT91C_PC13_D13 (AT91C_PIO_PC13) // +#define AT91C_PIO_PC14 (1 << 14) // Pin Controlled by PC14 +#define AT91C_PC14_D14 (AT91C_PIO_PC14) // +#define AT91C_PC14_NPCS1 (AT91C_PIO_PC14) // +#define AT91C_PIO_PC15 (1 << 15) // Pin Controlled by PC15 +#define AT91C_PC15_D15 (AT91C_PIO_PC15) // +#define AT91C_PC15_NCS3_NANDCS (AT91C_PIO_PC15) // +#define AT91C_PIO_PC16 (1 << 16) // Pin Controlled by PC16 +#define AT91C_PC16_A18 (AT91C_PIO_PC16) // +#define AT91C_PC16_NWAIT (AT91C_PIO_PC16) // +#define AT91C_PIO_PC17 (1 << 17) // Pin Controlled by PC17 +#define AT91C_PC17_A19 (AT91C_PIO_PC17) // +#define AT91C_PC17_NANDOE (AT91C_PIO_PC17) // +#define AT91C_PIO_PC18 (1 << 18) // Pin Controlled by PC18 +#define AT91C_PC18_A20 (AT91C_PIO_PC18) // +#define AT91C_PC18_NANDWE (AT91C_PIO_PC18) // +#define AT91C_PIO_PC19 (1 << 19) // Pin Controlled by PC19 +#define AT91C_PC19_A21 (AT91C_PIO_PC19) // +#define AT91C_PIO_PC2 (1 << 2) // Pin Controlled by PC2 +#define AT91C_PC2_D2 (AT91C_PIO_PC2) // +#define AT91C_PIO_PC20 (1 << 20) // Pin Controlled by PC20 +#define AT91C_PC20_A22 (AT91C_PIO_PC20) // +#define AT91C_PC20_NCS7 (AT91C_PIO_PC20) // +#define AT91C_PIO_PC21 (1 << 21) // Pin Controlled by PC21 +#define AT91C_PC21_A23 (AT91C_PIO_PC21) // +#define AT91C_PC21_NWR0_NWE_CFWE (AT91C_PIO_PC21) // +#define AT91C_PIO_PC22 (1 << 22) // Pin Controlled by PC22 +#define AT91C_PC22_A24 (AT91C_PIO_PC22) // +#define AT91C_PC22_NRD_CFOE (AT91C_PIO_PC22) // +#define AT91C_PIO_PC23 (1 << 23) // Pin Controlled by PC23 +#define AT91C_PC23_A25_CFRNW (AT91C_PIO_PC23) // +#define AT91C_PC23_NCS0 (AT91C_PIO_PC23) // +#define AT91C_PIO_PC3 (1 << 3) // Pin Controlled by PC3 +#define AT91C_PC3_D3 (AT91C_PIO_PC3) // +#define AT91C_PIO_PC4 (1 << 4) // Pin Controlled by PC4 +#define AT91C_PC4_D4 (AT91C_PIO_PC4) // +#define AT91C_PIO_PC5 (1 << 5) // Pin Controlled by PC5 +#define AT91C_PC5_D5 (AT91C_PIO_PC5) // +#define AT91C_PIO_PC6 (1 << 6) // Pin Controlled by PC6 +#define AT91C_PC6_D6 (AT91C_PIO_PC6) // +#define AT91C_PIO_PC7 (1 << 7) // Pin Controlled by PC7 +#define AT91C_PC7_D7 (AT91C_PIO_PC7) // +#define AT91C_PIO_PC8 (1 << 8) // Pin Controlled by PC8 +#define AT91C_PC8_D8 (AT91C_PIO_PC8) // +#define AT91C_PC8_RTS1 (AT91C_PIO_PC8) // +#define AT91C_PIO_PC9 (1 << 9) // Pin Controlled by PC9 +#define AT91C_PC9_D9 (AT91C_PIO_PC9) // +#define AT91C_PC9_DTR1 (AT91C_PIO_PC9) // + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7SE512 +// ***************************************************************************** +#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ( 1) // System Peripheral +#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A +#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B +#define AT91C_ID_PIOC ( 4) // Parallel IO Controller C +#define AT91C_ID_SPI ( 5) // Serial Peripheral Interface 0 +#define AT91C_ID_US0 ( 6) // USART 0 +#define AT91C_ID_US1 ( 7) // USART 1 +#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ( 9) // Two-Wire Interface +#define AT91C_ID_PWMC (10) // PWM Controller +#define AT91C_ID_UDP (11) // USB Device Port +#define AT91C_ID_TC0 (12) // Timer Counter 0 +#define AT91C_ID_TC1 (13) // Timer Counter 1 +#define AT91C_ID_TC2 (14) // Timer Counter 2 +#define AT91C_ID_ADC (15) // Analog-to-Digital Converter +#define AT91C_ID_16_Reserved (16) // Reserved +#define AT91C_ID_17_Reserved (17) // Reserved +#define AT91C_ID_18_Reserved (18) // Reserved +#define AT91C_ID_19_Reserved (19) // Reserved +#define AT91C_ID_20_Reserved (20) // Reserved +#define AT91C_ID_21_Reserved (21) // Reserved +#define AT91C_ID_22_Reserved (22) // Reserved +#define AT91C_ID_23_Reserved (23) // Reserved +#define AT91C_ID_24_Reserved (24) // Reserved +#define AT91C_ID_25_Reserved (25) // Reserved +#define AT91C_ID_26_Reserved (26) // Reserved +#define AT91C_ID_27_Reserved (27) // Reserved +#define AT91C_ID_28_Reserved (28) // Reserved +#define AT91C_ID_IRQ0 (29) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 (30) // Advanced Interrupt Controller (IRQ1) +#define AT91C_ID_31_Reserved (31) // Reserved +#define AT91C_ALL_INT (0x6000FFFF) // ALL VALID INTERRUPTS + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7SE512 +// ***************************************************************************** +#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address +#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_PIOB (AT91_CAST(AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address +#define AT91C_BASE_PIOC (AT91_CAST(AT91PS_PIO) 0xFFFFF800) // (PIOC) Base Address +#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_VREG (AT91_CAST(AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address +#define AT91C_BASE_MC (AT91_CAST(AT91PS_MC) 0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_EFC0 (AT91_CAST(AT91PS_EFC) 0xFFFFFF60) // (EFC0) Base Address +#define AT91C_BASE_EFC1 (AT91_CAST(AT91PS_EFC) 0xFFFFFF70) // (EFC1) Base Address +#define AT91C_BASE_PDC_SPI (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address +#define AT91C_BASE_SPI (AT91_CAST(AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address +#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_PDC_SSC (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC (AT91_CAST(AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_TWI (AT91_CAST(AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_PWMC_CH3 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC (AT91_CAST(AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address +#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TCB (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address +#define AT91C_BASE_EBI (AT91_CAST(AT91PS_EBI) 0xFFFFFF80) // (EBI) Base Address +#define AT91C_BASE_SMC (AT91_CAST(AT91PS_SMC2) 0xFFFFFF90) // (SMC) Base Address +#define AT91C_BASE_SDRC (AT91_CAST(AT91PS_SDRC) 0xFFFFFFB0) // (SDRC) Base Address +#define AT91C_BASE_HECC (AT91_CAST(AT91PS_ECC) 0xFFFFFFDC) // (HECC) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7SE512 +// ***************************************************************************** +// ISRAM +#define AT91C_ISRAM (0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE (0x00008000) // Internal SRAM size in byte (32 Kbytes) +// IFLASH +#define AT91C_IFLASH (0x00100000) // Internal FLASH base address +#define AT91C_IFLASH_SIZE (0x00080000) // Internal FLASH size in byte (512 Kbytes) +#define AT91C_IFLASH_PAGE_SIZE (256) // Internal FLASH Page Size: 256 bytes +#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Internal FLASH Lock Region Size: 16 Kbytes +#define AT91C_IFLASH_NB_OF_PAGES (2048) // Internal FLASH Number of Pages: 2048 bytes +#define AT91C_IFLASH_NB_OF_LOCK_BITS (32) // Internal FLASH Number of Lock Bits: 32 bytes + +#endif diff --git a/at91lib/boards/at91sam7se-ek/at91sam7se512/flash.lds b/at91lib/boards/at91sam7se-ek/at91sam7se512/flash.lds new file mode 100644 index 0000000..ce1f8c6 --- /dev/null +++ b/at91lib/boards/at91sam7se-ek/at91sam7se512/flash.lds @@ -0,0 +1,77 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal Flash on the AT91SAM7SE512. + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(entry) + +MEMORY +{ + sram (W!RX) : ORIGIN = 0x200000, LENGTH = 0x8000 + flash (RX) : ORIGIN = 0x100000, LENGTH = 0x80000 +} + +SECTIONS +{ + .fixed : + { + . = ALIGN(4); + _sfixed = .; + *(.text*) + *(.rodata*) + . = ALIGN(4); + _efixed = .; + } >flash + + .relocate : AT (_efixed) + { + . = ALIGN(4); + _srelocate = .; + *(.vectors) + *(.ramfunc) + *(.data) + . = ALIGN(4); + _erelocate = .; + } >sram + + .bss (NOLOAD) : { + _szero = .; + *(.bss) + . = ALIGN(4); + _ezero = .; + } >sram + + _sstack = 0x208000; +} +end = .; + diff --git a/at91lib/boards/at91sam7se-ek/at91sam7se512/sdram.lds b/at91lib/boards/at91sam7se-ek/at91sam7se512/sdram.lds new file mode 100644 index 0000000..7eb988f --- /dev/null +++ b/at91lib/boards/at91sam7se-ek/at91sam7se512/sdram.lds @@ -0,0 +1,79 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in external SDRAM on the AT91SAM7SE512 + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(entry) + +MEMORY +{ + sram (W!RX) : ORIGIN = 0x200000, LENGTH = 0x8000 + sdram (W!RX) : ORIGIN = 0x20000000, LENGTH = 0x2000000 +} + +SECTIONS +{ + .fixed : + { + . = ALIGN(4); + _sfixed = .; + *(.text*) + *(.rodata*) + *(.glue_7) + *(.glue_7t) + . = ALIGN(4); + _efixed = .; + } >sdram + + .relocate : AT (_efixed) + { + . = ALIGN(4); + _srelocate = .; + *(.vectors); + *(.ramfunc) + *(.data) + . = ALIGN(4); + _erelocate = .; + } >sram + + .bss (NOLOAD) : { + _szero = .; + *(.bss) + . = ALIGN(4); + _ezero = .; + } >sram + + _sstack = 0x22000000; +} +end = .; + diff --git a/at91lib/boards/at91sam7se-ek/at91sam7se512/sram.lds b/at91lib/boards/at91sam7se-ek/at91sam7se512/sram.lds new file mode 100644 index 0000000..a5d9ce1 --- /dev/null +++ b/at91lib/boards/at91sam7se-ek/at91sam7se512/sram.lds @@ -0,0 +1,77 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal SRAM on the AT91SAM7SE512. + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(entry) + +MEMORY +{ + sram (W!RX) : ORIGIN = 0x200000, LENGTH = 0x8000 + flash (RX) : ORIGIN = 0x100000, LENGTH = 0x80000 +} + +SECTIONS +{ + . = ALIGN(4); + .fixed : + { + _sfixed = .; + *(.vectors) + *(.ramfunc) + *(.text*) + *(.rodata*) + *(.data) + . = ALIGN(4); + _efixed = .; + } >sram + + .relocate : AT (_efixed) + { + . = ALIGN(4); + _srelocate = .; + . = ALIGN(4); + _erelocate = .; + } + + .bss (NOLOAD) : { + _szero = .; + *(.bss) + . = ALIGN(4); + _ezero = .; + } >sram + + _sstack = 0x208000; +} +end = .; + diff --git a/at91lib/boards/at91sam7se-ek/board.h b/at91lib/boards/at91sam7se-ek/board.h new file mode 100644 index 0000000..e642add --- /dev/null +++ b/at91lib/boards/at91sam7se-ek/board.h @@ -0,0 +1,548 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \dir +/// !Purpose +/// +/// Definition and functions for using AT91SAM7SE-related features, such +/// has PIO pins, memories, etc. +/// +/// !Usage +/// -# The code for booting the board is provided by board_cstartup.S and +/// board_lowlevel.c. +/// -# For using board PIOs, board characteristics (clock, etc.) and external +/// components, see board.h. +/// -# For manipulating memories (remapping, SDRAM, etc.), see board_memories.h. +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \unit +/// !Purpose +/// +/// Definition of AT91SAM7SE-EK characteristics, AT91SAM7SE-dependant PIOs and +/// external components interfacing. +/// +/// !Usage +/// -# For operating frequency information, see "SAM7SE-EK - Operating frequencies". +/// -# For using portable PIO definitions, see "SAM7SE-EK - PIO definitions". +/// -# Several USB definitions are included here (see "SAM7SE-EK - USB device"). +/// -# For external components definitions, see "SAM7SE-EK - External components". +/// -# For memory-related definitions, see "SAM7SE-EK - Memories". +//------------------------------------------------------------------------------ + +#ifndef BOARD_H +#define BOARD_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#if defined(at91sam7se32) + #include "at91sam7se32/AT91SAM7SE32.h" +#elif defined(at91sam7se256) + #include "at91sam7se256/AT91SAM7SE256.h" +#elif defined(at91sam7se512) + #include "at91sam7se512/AT91SAM7SE512.h" +#else + #error Board does not support the specified chip. +#endif + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "SAM7SE-EK - Board Description" +/// This page lists several definition related to the board description +/// +/// !Definitions +/// - BOARD_NAME + +/// Name of the board. +#define BOARD_NAME "AT91SAM7SE-EK" +/// Board definition. +#define at91sam7seek +/// Family definition. +#define at91sam7se +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "SAM7SE-EK - Operating frequencies" +/// This page lists several definition related to the board operating frequency +/// (when using the initialization done by board_lowlevel.c). +/// +/// !Definitions +/// - BOARD_MAINOSC +/// - BOARD_MCK + +/// Frequency of the board main oscillator. +#define BOARD_MAINOSC 18432000 + +/// Master clock frequency (when using board_lowlevel.c). +#define BOARD_MCK 48000000 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// ADC +//------------------------------------------------------------------------------ +/// ADC clock frequency, at 10-bit resolution (in Hz) +#define ADC_MAX_CK_10BIT 5000000 +/// ADC clock frequency, at 8-bit resolution (in Hz) +#define ADC_MAX_CK_8BIT 8000000 +/// Startup time max, return from Idle mode (in s) +#define ADC_STARTUP_TIME_MAX 20 +/// Track and hold Acquisition Time min (in ns) +#define ADC_TRACK_HOLD_TIME_MIN 600 + + +//------------------------------------------------------------------------------ +/// \page "SAM7SE-EK - USB device" +/// This page lists constants describing several characteristics (controller +/// type, D+ pull-up type, etc.) of the USB device controller of the chip/board. +/// +/// !Constants +/// - BOARD_USB_UDP +/// - BOARD_USB_PULLUP_INTERNAL +/// - BOARD_USB_NUMENDPOINTS +/// - BOARD_USB_ENDPOINTS_MAXPACKETSIZE +/// - BOARD_USB_ENDPOINTS_BANKS +/// - BOARD_USB_BMATTRIBUTES + +/// Chip has a UDP controller. +#define BOARD_USB_UDP + +/// Indicates the D+ pull-up is internal to the USB controller. +#define BOARD_USB_PULLUP_INTERNAL + +/// Number of endpoints in the USB controller. +#define BOARD_USB_NUMENDPOINTS 8 + +/// Returns the maximum packet size of the given endpoint. +#define BOARD_USB_ENDPOINTS_MAXPACKETSIZE(i) (((i == 4) || (i == 5)) ? 512 : 64) + +/// Returns the number of FIFO banks for the given endpoint. +#define BOARD_USB_ENDPOINTS_BANKS(i) (((i == 0) || (i == 3)) ? 1 : 2) + +/// USB attributes configuration descriptor (bus or self powered, remote wakeup) +#define BOARD_USB_BMATTRIBUTES USBConfigurationDescriptor_SELFPOWERED_NORWAKEUP +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "SAM7SE-EK - PIO definitions" +/// This pages lists all the pio definitions contained in board.h. The constants +/// are named using the following convention: PIN_* for a constant which defines +/// a single Pin instance (but may include several PIOs sharing the same +/// controller), and PINS_* for a list of Pin instances. +/// +/// !Clocks +/// - PIN_PCK2 +/// +/// !DBGU +/// - PINS_DBGU +/// +/// !LEDs +/// - PIN_LED_0 +/// - PIN_LED_1 +/// - PIN_LED_2 +/// - PINS_LEDS +/// - LED_DS1 +/// - LED_DS2 +/// - LED_POWER +/// +/// !Push buttons +/// - PIN_PUSHBUTTON_1 +/// - PIN_PUSHBUTTON_2 +/// - PINS_PUSHBUTTONS +/// - PUSHBUTTON_BP1 +/// - PUSHBUTTON_BP2 +/// +/// !Joystick buttons +/// - PIN_JOYSTICK_UP +/// - PIN_JOYSTICK_DOWN +/// - PIN_JOYSTICK_LEFT +/// - PIN_JOYSTICK_RIGHT +/// - PIN_JOYSTICK_LCLIC, PIN_JOYSTICK_PUSH +/// - PIN_JOYSTICK_RCLIC +/// - PINS_JOYSTICK_MOVE, PINS_JOYSTICK_CLIC, PINS_JOYSTICK +/// - JOYSTICK_UP +/// - JOYSTICK_DOWN +/// - JOYSTICK_LEFT +/// - JOYSTICK_RIGHT +/// - JOYSTICK_LCLIC, JOYSTICK_PUSH +/// - JOYSTICK_RCLIC +/// +/// !USART0 +/// - PIN_USART0_RXD +/// - PIN_USART0_TXD +/// - PIN_USART0_SCK +/// +/// !SPI +/// - PIN_SPI_MISO +/// - PIN_SPI_MOSI +/// - PIN_SPI_SPCK +/// - PINS_SPI +/// - PIN_SPI_NPCS0 +/// - PIN_SPI_NPCS1 +/// +/// !SSC +/// - PIN_SSC_TRANSMITTER +/// +/// !PWMC +/// - PIN_PWMC_PWM0 +/// - PIN_PWMC_PWM1 +/// - PIN_PWMC_PWM2 +/// +/// !ADC +/// - PIN_ADC_ADC0 +/// - PIN_ADC_ADC1 +/// - PIN_ADC_ADC2 +/// - PIN_ADC_ADC3 +/// - PINS_ADC +/// +/// !TWI +/// - PINS_TWI +/// +/// !USB +/// - PIN_USB_VBUS + +/// Programmable clock output 2 pin definition. +#define PIN_PCK2 {1 << 31, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT} + +/// DBGU pins (DTXD and DRXD) definitions. +#define PINS_DBGU {0x00000600, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} + + +/// LED #0 pin definition. +#define PIN_LED_0 {1 << 8, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT} +/// LED #1 pin definition. +#define PIN_LED_1 {1 << 31, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_OUTPUT_1, PIO_DEFAULT} +/// LED #2 pin definition. +#define PIN_LED_2 {1 << 30, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_OUTPUT_1, PIO_DEFAULT} +/// List of all LEDs pin definitions. +#define PINS_LEDS PIN_LED_0, PIN_LED_1, PIN_LED_2 + +#define PINS_SRAM \ + {0x000000FE, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_B, PIO_DEFAULT}, \ + {0x0000FFFF, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT}, \ + {0x00E00000, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} + + + +/* +/// Push button #1 definition. +#define PIN_PUSHBUTTON_1 {1 << 25, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_INPUT, PIO_PULLUP} +/// Push button #2 definition. +#define PIN_PUSHBUTTON_2 {1 << 22, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_INPUT, PIO_PULLUP} +/// List of all push button definitions. +#define PINS_PUSHBUTTONS PIN_PUSHBUTTON_1, PIN_PUSHBUTTON_2 +/// Push button #1 index. +#define PUSHBUTTON_BP1 0 +/// Push button #2 index. +#define PUSHBUTTON_BP2 1 +*/ +/* +// Joystick definition. +/// Joystick UP. +#define PIN_JOYSTICK_UP {1 << 23, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_INPUT, PIO_PULLUP} +/// Joystick DOWN. +#define PIN_JOYSTICK_DOWN {1 << 24, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_INPUT, PIO_PULLUP} +/// Joystick LEFT. +#define PIN_JOYSTICK_LEFT {1 << 27, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_INPUT, PIO_PULLUP} +/// Joystick RIGHT. +#define PIN_JOYSTICK_RIGHT {1 << 26, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_INPUT, PIO_PULLUP} +/// Joystick LEFT clic. +#define PIN_JOYSTICK_LCLIC {1 << 25, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_INPUT, PIO_PULLUP} +/// Joystick PUSH button. +#define PIN_JOYSTICK_PUSH PIN_JOYSTICK_LCLIC +/// Joystick RIGHT clic push button. +#define PIN_JOYSTICK_RCLIC {1 << 22, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_INPUT, PIO_PULLUP} +/// List of all Joystick click definitions +#define PINS_JOYSTICK_CLIC PIN_JOYSTICK_RCLIC, PIN_JOYSTICK_LCLIC +/// List of all Joystick movement direction definitions +#define PINS_JOYSTICK_MOVE PIN_JOYSTICK_UP, PIN_JOYSTICK_DOWN, \ + PIN_JOYSTICK_LEFT, PIN_JOYSTICK_RIGHT +/// List of all Joystick definitions +#define PINS_JOYSTICK PINS_JOYSTICK_MOVE, \ + PINS_JOYSTICK_CLIC +/// Joystick UP index. +#define JOYSTICK_UP 0 +/// Joystick DOWN index. +#define JOYSTICK_DOWN 1 +/// Joystick LEFT index. +#define JOYSTICK_LEFT 2 +/// Joystick RIGHT index. +#define JOYSTICK_RIGHT 3 +/// Joystick LEFT CLICK index. +#define JOYSTICK_LCLIC 4 +/// Joystick PUSH button index. +#define JOYSTICK_PUSH 4 +/// Joystick RIGHT CLIC index. +#define JOYSTICK_RCLIC 5 +*/ +/// USART0 TXD pin definition. +#define PIN_USART0_RXD {1 << 5, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +/// USART0 RXD pin definition. +#define PIN_USART0_TXD {1 << 6, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +/// USART0 RTS pin definition +#define PIN_USART0_RTS {1 << 7, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +/// USART0 CTS pin definition +#define PIN_USART0_CTS {1 << 8, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +/// USART0 SCK pin definition +#define PIN_USART0_SCK {1 << 2, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT} + +/* +/// SPI MISO pin definition. +#define PIN_SPI_MISO {1 << 12, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_PULLUP} +/// SPI MOSI pin definition. +#define PIN_SPI_MOSI {1 << 13, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_PULLUP} +/// SPI SPCK pin definition. +#define PIN_SPI_SPCK {1 << 14, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_PULLUP} +/// List of SPI pin definitions (MISO, MOSI & SPCK). +#define PINS_SPI PIN_SPI_MISO, PIN_SPI_MOSI, PIN_SPI_SPCK +/// SPI chip select 0 pin definition. +#define PIN_SPI_NPCS0 {1 << 11, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_PULLUP} +/// SPI chip select 1 pin definition. +#define PIN_SPI_NPCS1 {1 << 31, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_PULLUP} +/// SPI chip select 2 pin definition. +#define PIN_SPI_NPCS2 {1 << 10, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_A, PIO_PULLUP} +/// SPI chip select 3 pin definition. +#define PIN_SPI_NPCS3 {1 << 3, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_A, PIO_PULLUP} + +/// SSC transmitter pins definition. +#define PINS_SSC_TX {0x00038000, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} + +/// PWMC PWM0 pin definition. +#define PIN_PWMC_PWM0 {1 << 0, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +/// PWMC PWM0 pin definition. +#define PIN_PWMC_PWM1 {1 << 1, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +/// PWMC PWM0 pin definition. +#define PIN_PWMC_PWM2 {1 << 2, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} + +/// PWM pin definition for LED0 +#define PIN_PWM_LED0 PIN_PWMC_PWM1 +/// PWM pin definition for LED1 +#define PIN_PWM_LED1 PIN_PWMC_PWM2 +/// PWM channel for LED0 +#define CHANNEL_PWM_LED0 1 +/// PWM channel for LED1 +#define CHANNEL_PWM_LED1 2 +*/ +/// ADC_AD0 pin definition. +#define PIN_ADC_ADC0 {1 << 17, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_INPUT, PIO_DEFAULT} +/// ADC_AD1 pin definition. +#define PIN_ADC_ADC1 {1 << 18, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_INPUT, PIO_DEFAULT} +/// ADC_AD2 pin definition. +#define PIN_ADC_ADC2 {1 << 19, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_INPUT, PIO_DEFAULT} +/// ADC_AD3 pin definition. +#define PIN_ADC_ADC3 {1 << 20, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_INPUT, PIO_DEFAULT} +/// Pins ADC +#define PINS_ADC PIN_ADC_ADC0, PIN_ADC_ADC1, PIN_ADC_ADC2, PIN_ADC_ADC3 +/* +/// TWI pins definition. +#define PINS_TWI {0x00000018, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_OPENDRAIN} +*/ +/// USB VBus monitoring pin definition. +#define PIN_USB_VBUS {1 << 19, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_INPUT, PIO_DEFAULT} +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "SAM7SE-EK - External components" +/// This page lists the definitions related to external on-board components +/// located in the board.h file for the AT91SAM7SE-EK. +/// +/// !AT45 Dataflash (serial onboard DataFlash) +/// - BOARD_AT45_A_SPI_BASE +/// - BOARD_AT45_A_SPI_ID +/// - BOARD_AT45_A_SPI_PINS +/// - BOARD_AT45_A_SPI +/// - BOARD_AT45_A_NPCS +/// - BOARD_AT45_A_NPCS_PIN +/// +/// !AT26 Serialflash +/// - BOARD_AT26_A_SPI_BASE +/// - BOARD_AT26_A_SPI_ID +/// - BOARD_AT26_A_SPI_PINS +/// - BOARD_AT26_A_SPI +/// - BOARD_AT26_A_NPCS +/// - BOARD_AT26_A_NPCS_PIN +/// +/// !AT73C213 +/// - BOARD_AT73C213_SPI +/// - BOARD_AT73C213_SPI_ID +/// - BOARD_AT73C213_NPCS +/// - BOARD_AT73C213_SSC +/// - BOARD_AT73C213_SSC_ID +/// - BOARD_AT73C213_MCK +/// +/// !SD Card SPI +/// - BOARD_SD_SPI_BASE +/// - BOARD_SD_SPI_ID +/// - BOARD_SD_SPI_PINS +/// - BOARD_SD_NPCS +/* +/// Base address of SPI peripheral connected to the dataflash. +#define BOARD_AT45_A_SPI_BASE AT91C_BASE_SPI +/// Identifier of SPI peripheral connected to the dataflash. +#define BOARD_AT45_A_SPI_ID AT91C_ID_SPI +/// Pins of the SPI peripheral connected to the dataflash. +#define BOARD_AT45_A_SPI_PINS PINS_SPI +/// Dataflash SPI peripheral index. +#define BOARD_AT45_A_SPI 0 +/// Chip select connected to the dataflash. +#define BOARD_AT45_A_NPCS 0 +/// Chip select pin connected to the dataflash. +#define BOARD_AT45_A_NPCS_PIN PIN_SPI_NPCS0 + +/// Base address of SPI peripheral connected to the serialflash. +#define BOARD_AT26_A_SPI_BASE AT91C_BASE_SPI +/// Identifier of SPI peripheral connected to the serialflash. +#define BOARD_AT26_A_SPI_ID AT91C_ID_SPI +/// Pins of the SPI peripheral connected to the serialflash. +#define BOARD_AT26_A_SPI_PINS PINS_SPI +/// Serialflash SPI number. +#define BOARD_AT26_A_SPI 0 +/// Chip select connected to the serialflash. +#define BOARD_AT26_A_NPCS 0 +/// Chip select pin connected to the serialflash. +#define BOARD_AT26_A_NPCS_PIN PIN_SPI_NPCS0 + +/// Base address of SPI peripheral to which the DAC is connected. +#define BOARD_AT73C213_SPI AT91C_BASE_SPI +/// Peripheral ID of the SPI connected to the DAC. +#define BOARD_AT73C213_SPI_ID AT91C_ID_SPI +/// Chip select value for accessing the DAC with the SPI. +#define BOARD_AT73C213_SPI_NPCS 1 +/// Pins required by the SPI interface. +#define BOARD_AT73C213_SPI_PINS PINS_SPI, PIN_SPI_NPCS1 +/// SSC peripheral to which the DAC is connected. +#define BOARD_AT73C213_SSC AT91C_BASE_SSC +/// Peripheral ID of the SSC connected to the DAC. +#define BOARD_AT73C213_SSC_ID AT91C_ID_SSC +/// Pins required by the SSC interface. +#define BOARD_AT73C213_SSC_PINS PINS_SSC_TX +/// PCK pin connected to the DAC MCK pin +#define BOARD_AT73C213_MCK PIN_PCK2 + +/// Not define in our board, but customer can add this feature +/// Base address of the SPI peripheral connected to the SD card. +#define BOARD_SD_SPI_BASE AT91C_BASE_SPI +/// Identifier of the SPI peripheral connected to the SD card. +#define BOARD_SD_SPI_ID AT91C_ID_SPI +/// List of pins to configure to access the SD card +#define BOARD_SD_SPI_PINS PINS_SPI, PIN_SPI_NPCS2 +/// NPCS number +#define BOARD_SD_NPCS 2 +*/ +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "SAM7SE-EK - Memories" +/// This page lists definitions related to external on-board memories. +/// +/// !Embedded flash +/// - BOARD_FLASH_EFC +/// +/// !SDRAM +/// - AT91C_EBI_SDRAM +/// - BOARD_SDRAM_SIZE +/// - PINS_SDRAM +/// - BOARD_SDRAM_BUSWIDTH +/// +/// !Nandflash +/// - BOARD_NF_COMMAND_ADDR +/// - BOARD_NF_ADDRESS_ADDR +/// - BOARD_NF_DATA_ADDR +/// - BOARD_NF_CE_PIN +/// - BOARD_NF_RB_PIN +/// - PINS_NANDFLASH +/// +/// !NorFlash +/// - BOARD_NORFLASH_ADDR +/* +/// Indicates board has an EFC. +#define BOARD_FLASH_EFC + +/// Base address of the SDRAM memory connected to the EBI. +#define AT91C_EBI_SDRAM ((volatile unsigned char *) 0x20000000) +/// Board SDRAM size +#define BOARD_SDRAM_SIZE (64*1024*1024) // 64 MB +/// List of the pins used by the EBI to connect to the external SDRAM chip. +#define PINS_SDRAM \ + {0x3F800000, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT}, \ + {0x0003FFFF, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_B, PIO_DEFAULT}, \ + {0x0000FFFF, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT} +/// SDRAM bus width. +#define BOARD_SDRAM_BUSWIDTH 16 + +/// Nandflash controller peripheral pins definition. +#define PINS_NANDFLASH {0x001800FF, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT}, \ + {0x00060000, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT}, \ + BOARD_NF_CE_PIN, \ + BOARD_NF_RB_PIN +/// Nandflash chip enable pin definition. +#define BOARD_NF_CE_PIN {1 << 18, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_OUTPUT_1, PIO_DEFAULT} +/// Nandflash ready/busy pin definition. +#define BOARD_NF_RB_PIN {1 << 19, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_INPUT, PIO_PULLUP} +/// Address for transferring command bytes to the nandflash. +#define BOARD_NF_COMMAND_ADDR 0x40400000 +/// Address for transferring address bytes to the nandflash. +#define BOARD_NF_ADDRESS_ADDR 0x40200000 +/// Address for transferring data bytes to the nandflash. +#define BOARD_NF_DATA_ADDR 0x40000000 + +/// NORFlash peripheral pins definition. +#define PINS_NORFLASH {0xC0000000, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT}, \ + {0xFFFFFFFE, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_B, PIO_DEFAULT},\ + {0x001FFFFF, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT},\ + {0x00E00000, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} +/// Address for transferring command bytes to the norflash. +#define BOARD_NORFLASH_ADDR 0x10000000 +//------------------------------------------------------------------------------ +*/ +//------------------------------------------------------------------------------ +/// \page "SAM7SE-EK - External components" +/// This page lists the definitions related to external on-board components +/// located in the board.h file for the SAM7SE-EK. +/// +/// !ISO7816 +/// - PIN_SMARTCARD_CONNECT +/// - PIN_ISO7816_RSTMC +/// - PINS_ISO7816 +/* +/// Smartcard detection pin +#define PIN_SMARTCARD_CONNECT {1 << 5, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_INPUT, PIO_DEFAULT} +/// PIN used for reset the smartcard +#define PIN_ISO7816_RSTMC {1 << 7, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT} +/// Pins used for connect the smartcard +#define PINS_ISO7816 PIN_USART0_TXD, PIN_USART0_SCK, PIN_ISO7816_RSTMC +//------------------------------------------------------------------------------ +*/ +#endif //#ifndef BOARD_H + diff --git a/at91lib/boards/at91sam7se-ek/board.mak b/at91lib/boards/at91sam7se-ek/board.mak new file mode 100644 index 0000000..3325af2 --- /dev/null +++ b/at91lib/boards/at91sam7se-ek/board.mak @@ -0,0 +1,33 @@ +# ---------------------------------------------------------------------------- +# ATMEL Microcontroller Software Support +# ---------------------------------------------------------------------------- +# Copyright (c) 2008, Atmel Corporation +# +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# - Redistributions of source code must retain the above copyright notice, +# this list of conditions and the disclaimer below. +# +# Atmel's name may not be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +# DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +# OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# ---------------------------------------------------------------------------- + +# Defines which are the available memory targets for the AT91SAM7SE-EK board. + +MEMORIES = flash +# sram + diff --git a/at91lib/boards/at91sam7se-ek/board_cstartup.S b/at91lib/boards/at91sam7se-ek/board_cstartup.S new file mode 100644 index 0000000..22a3269 --- /dev/null +++ b/at91lib/boards/at91sam7se-ek/board_cstartup.S @@ -0,0 +1,181 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "board.h" + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +#define IRQ_STACK_SIZE 8*3*4 + +#define ARM_MODE_ABT 0x17 +#define ARM_MODE_FIQ 0x11 +#define ARM_MODE_IRQ 0x12 +#define ARM_MODE_SVC 0x13 + +#define I_BIT 0x80 +#define F_BIT 0x40 + +//------------------------------------------------------------------------------ +// Startup routine +//------------------------------------------------------------------------------ + + .align 4 + .arm + +/* Exception vectors + *******************/ + .section .vectors, "a" + +resetVector: + ldr pc, =resetHandler /* Reset */ +undefVector: + b undefVector /* Undefined instruction */ +swiVector: + b swiVector /* Software interrupt */ +prefetchAbortVector: + b prefetchAbortVector /* Prefetch abort */ +dataAbortVector: + b dataAbortVector /* Data abort */ +reservedVector: + b reservedVector /* Reserved for future use */ +irqVector: + b irqHandler /* Interrupt */ +fiqVector: + /* Fast interrupt */ +//------------------------------------------------------------------------------ +/// Handles a fast interrupt request by branching to the address defined in the +/// AIC. +//------------------------------------------------------------------------------ +fiqHandler: + b fiqHandler + +//------------------------------------------------------------------------------ +/// Handles incoming interrupt requests by branching to the corresponding +/// handler, as defined in the AIC. Supports interrupt nesting. +//------------------------------------------------------------------------------ +irqHandler: + +/* Save interrupt context on the stack to allow nesting */ + sub lr, lr, #4 + stmfd sp!, {lr} + mrs lr, SPSR + stmfd sp!, {r0, lr} + +/* Write in the IVR to support Protect Mode */ + ldr lr, =AT91C_BASE_AIC + ldr r0, [r14, #AIC_IVR] + str lr, [r14, #AIC_IVR] + +/* Branch to interrupt handler in Supervisor mode */ + msr CPSR_c, #ARM_MODE_SVC + stmfd sp!, {r1-r3, r4, r12, lr} + mov lr, pc + bx r0 + ldmia sp!, {r1-r3, r4, r12, lr} + msr CPSR_c, #ARM_MODE_IRQ | I_BIT + +/* Acknowledge interrupt */ + ldr lr, =AT91C_BASE_AIC + str lr, [r14, #AIC_EOICR] + +/* Restore interrupt context and branch back to calling code */ + ldmia sp!, {r0, lr} + msr SPSR_cxsf, lr + ldmia sp!, {pc}^ + +//------------------------------------------------------------------------------ +/// Initializes the chip and branches to the main() function. +//------------------------------------------------------------------------------ + .section .text + .global entry + +entry: +resetHandler: + +/* Dummy access to the .vectors section so it does not get optimized */ + ldr r0, =resetVector + +/* Set pc to actual code location (i.e. not in remap zone) */ + ldr pc, =1f + +/* Perform low-level initialization of the chip using LowLevelInit() */ +1: + ldr r4, =_sstack + mov sp, r4 + ldr r0, =LowLevelInit + mov lr, pc + bx r0 + +/* Initialize the relocate segment */ + + ldr r0, =_efixed + ldr r1, =_srelocate + ldr r2, =_erelocate +1: + cmp r1, r2 + ldrcc r3, [r0], #4 + strcc r3, [r1], #4 + bcc 1b + +/* Clear the zero segment */ + ldr r0, =_szero + ldr r1, =_ezero + mov r2, #0 +1: + cmp r0, r1 + strcc r2, [r0], #4 + bcc 1b + +/* Setup stacks + **************/ +/* IRQ mode */ + msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT + mov sp, r4 + sub r4, r4, #IRQ_STACK_SIZE + +/* Supervisor mode (interrupts enabled) */ + msr CPSR_c, #ARM_MODE_SVC | F_BIT + mov sp, r4 + +/* Branch to main() + ******************/ + ldr r0, =main + mov lr, pc + bx r0 + +/* Loop indefinitely when program is finished */ +1: + b 1b + diff --git a/at91lib/boards/at91sam7se-ek/board_lowlevel.c b/at91lib/boards/at91sam7se-ek/board_lowlevel.c new file mode 100644 index 0000000..cb8f3ac --- /dev/null +++ b/at91lib/boards/at91sam7se-ek/board_lowlevel.c @@ -0,0 +1,175 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \unit +/// +/// !Purpose +/// +/// Provides the low-level initialization function that gets called on chip +/// startup. +/// +/// !Usage +/// +/// LowLevelInit() is called in #board_cstartup.S#. +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "board.h" +#include "board_memories.h" +#include + +//------------------------------------------------------------------------------ +// Internal definitions +//------------------------------------------------------------------------------ +// Startup time of main oscillator (in number of slow clock ticks). +#define BOARD_OSCOUNT (AT91C_CKGR_OSCOUNT & (0x40 << 8)) + +// USB PLL divisor value to obtain a 48MHz clock. +#define BOARD_USBDIV AT91C_CKGR_USBDIV_1 + +// PLL frequency range. +#define BOARD_CKGR_PLL AT91C_CKGR_OUT_0 + +// PLL startup time (in number of slow clock ticks). +#define BOARD_PLLCOUNT (16 << 8) + +// PLL MUL value. +#define BOARD_MUL (AT91C_CKGR_MUL & (72 << 16)) + +// PLL DIV value. +#define BOARD_DIV (AT91C_CKGR_DIV & 14) + +// Master clock prescaler value. +#define BOARD_PRESCALER AT91C_PMC_PRES_CLK_2 + +//------------------------------------------------------------------------------ +// Internal functions +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +/// Default spurious interrupt handler. Infinite loop. +//------------------------------------------------------------------------------ +void defaultSpuriousHandler( void ) +{ + while (1); +} + +//------------------------------------------------------------------------------ +/// Default handler for fast interrupt requests. Infinite loop. +//------------------------------------------------------------------------------ +void defaultFiqHandler( void ) +{ + while (1); +} + +//------------------------------------------------------------------------------ +/// Default handler for standard interrupt requests. Infinite loop. +//------------------------------------------------------------------------------ +void defaultIrqHandler( void ) +{ + while (1); +} + + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Performs the low-level initialization of the chip. This includes EFC, master +/// clock, AIC & watchdog configuration, as well as memory remapping. +//------------------------------------------------------------------------------ +void LowLevelInit( void ) +{ + unsigned char i; + + BOARD_ConfigureFlash48MHz(); + +//#if !defined(sdram) + /* Initialize main oscillator + ****************************/ + AT91C_BASE_PMC->PMC_MOR = BOARD_OSCOUNT | AT91C_CKGR_MOSCEN; + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS)); + + /* Initialize PLL at 96MHz (96.109) and USB clock to 48MHz */ + AT91C_BASE_PMC->PMC_PLLR = BOARD_USBDIV | BOARD_CKGR_PLL | BOARD_PLLCOUNT + | BOARD_MUL | BOARD_DIV; + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK)); + + /* Wait for the master clock if it was already initialized */ + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)); + + /* Switch to fast clock + **********************/ + /* Switch to slow clock + prescaler */ + AT91C_BASE_PMC->PMC_MCKR = BOARD_PRESCALER; + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)); + + /* Switch to fast clock + prescaler */ + AT91C_BASE_PMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK; + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)); +//#endif //#if !defined(sdram) + + /* Initialize AIC + ****************/ + AT91C_BASE_AIC->AIC_IDCR = 0xFFFFFFFF; + AT91C_BASE_AIC->AIC_SVR[0] = (unsigned int) defaultFiqHandler; + for (i = 1; i < 31; i++) { + + AT91C_BASE_AIC->AIC_SVR[i] = (unsigned int) defaultIrqHandler; + } + AT91C_BASE_AIC->AIC_SPU = (unsigned int) defaultSpuriousHandler; + + // Unstack nested interrupts + for (i = 0; i < 8 ; i++) { + + AT91C_BASE_AIC->AIC_EOICR = 0; + } + + // Enable Debug mode + AT91C_BASE_AIC->AIC_DCR = AT91C_AIC_DCR_PROT; + + /* Watchdog initialization + *************************/ + AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS; + + /* Remap + *******/ + BOARD_RemapRam(); + + // Disable RTT and PIT interrupts (potential problem when program A + // configures RTT, then program B wants to use PIT only, interrupts + // from the RTT will still occur since they both use AT91C_ID_SYS) + AT91C_BASE_RTTC->RTTC_RTMR &= ~(AT91C_RTTC_ALMIEN | AT91C_RTTC_RTTINCIEN); + AT91C_BASE_PITC->PITC_PIMR &= ~AT91C_PITC_PITIEN; +} + diff --git a/at91lib/boards/at91sam7se-ek/board_memories.c b/at91lib/boards/at91sam7se-ek/board_memories.c new file mode 100644 index 0000000..115b245 --- /dev/null +++ b/at91lib/boards/at91sam7se-ek/board_memories.c @@ -0,0 +1,136 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "board_memories.h" +#include "board.h" +#include + +/* + Macros: + READ - Reads a register value. Useful to add trace information to read + accesses. + WRITE - Writes data in a register. Useful to add trace information to + write accesses. +*/ +#define READ(peripheral, register) (peripheral->register) +#define WRITE(peripheral, register, value) (peripheral->register = value) + +//------------------------------------------------------------------------------ +// Internal definitions +//------------------------------------------------------------------------------ +/* + Constants: Remap types + BOARD_FLASH - Flash is mirrored in the remap zone. + BOARD_RAM - RAM is mirrored in the remap zone. +*/ +#define BOARD_FLASH 0 +#define BOARD_RAM 1 + +//------------------------------------------------------------------------------ +// Internal function +//------------------------------------------------------------------------------ +/* + Function: BOARD_GetRemap + Returns the current remap (see ). +*/ +static unsigned char BOARD_GetRemap( void ) +{ + volatile unsigned int *remap = (volatile unsigned int *) 0; + volatile unsigned int *ram = (volatile unsigned int *) AT91C_ISRAM; + + // Try to write in 0 and see if this affects the RAM + unsigned int temp = *ram; + *ram = temp + 1; + if (*remap == *ram) { + + *ram = temp; + return BOARD_RAM; + } + else { + + *ram = temp; + return BOARD_FLASH; + } +} + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ +/* + Function: BOARD_RemapFlash + Changes the mapping of the chip so that the remap area mirrors the + internal flash. +*/ +void BOARD_RemapFlash( void ) +{ + if (BOARD_GetRemap() != BOARD_FLASH) { + + AT91C_BASE_MC->MC_RCR = AT91C_MC_RCB; + } +} + +/* + Function: BOARD_RemapRam + Changes the mapping of the chip so that the remap area mirrors the + internal RAM. +*/ +void BOARD_RemapRam( void ) +{ + if (BOARD_GetRemap() != BOARD_RAM) { + + AT91C_BASE_MC->MC_RCR = AT91C_MC_RCB; + } +} + + +//------------------------------------------------------------------------------ +/// Configures a list of AT91S_EFC instances. +/// \param list Pointer to a list of AT91S_EFC instances. +/// \param size Size of the AT91S_EFC list. +/// \param numWaitStates Number of state cycles value for the EFC. +//------------------------------------------------------------------------------ +void BOARD_ConfigureFlash48MHz(void) +{ + /* Set flash wait states in the EFC + **********************************/ + /* 48MHz = 1 wait state */ +#if defined(at91sam7se512) + AT91C_BASE_EFC0->EFC_FMR = AT91C_MC_FWS_2FWS; + AT91C_BASE_EFC1->EFC_FMR = AT91C_MC_FWS_2FWS; +#elif defined(at91sam7se32) || defined(at91sam7se256) + AT91C_BASE_EFC->EFC_FMR = AT91C_MC_FWS_2FWS; +#else + #error No chip definition ? +#endif +} + diff --git a/at91lib/boards/at91sam7se-ek/board_memories.h b/at91lib/boards/at91sam7se-ek/board_memories.h new file mode 100644 index 0000000..3db17f5 --- /dev/null +++ b/at91lib/boards/at91sam7se-ek/board_memories.h @@ -0,0 +1,57 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/* + Title: Memories + + About: Purpose + Methods for initializing memories (SDRAM, etc.) and remapping. + + About: Usage + 1 - Remap the Flash at address 0 using . + 2 - Remap the internal RAM at address 0 using . + 3 - Initialize an external SDRAM using . +*/ + +#ifndef BOARD_MEMORIES_H +#define BOARD_MEMORIES_H + + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +extern void BOARD_RemapFlash(void); + +extern void BOARD_RemapRam(void); + +extern void BOARD_ConfigureFlash48MHz(void); + +#endif //#ifndef BOARD_MEMORIES_H + diff --git a/at91lib/boards/theva-rev1/at91sam7se512/AT91SAM7SE512.h b/at91lib/boards/theva-rev1/at91sam7se512/AT91SAM7SE512.h new file mode 100644 index 0000000..2f4376e --- /dev/null +++ b/at91lib/boards/theva-rev1/at91sam7se512/AT91SAM7SE512.h @@ -0,0 +1,2776 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// Copyright (c) 2006, Atmel Corporation +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// - Redistributions of source code must retain the above copyright notice, +// this list of conditions and the disclaimer below. +// +// Atmel's name may not be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// ---------------------------------------------------------------------------- +// File Name : AT91SAM7SE512.h +// Object : AT91SAM7SE512 definitions +// Generated : AT91 SW Application Group 07/07/2008 (16:12:05) +// +// CVS Reference : /AT91SAM7SE512.pl/1.21/Fri Feb 29 14:02:47 2008// +// CVS Reference : /SYS_SAM7X.pl/1.3/Wed Feb 2 15:48:15 2005// +// CVS Reference : /MC_SAM7SE.pl/1.10/Thu Feb 16 16:35:28 2006// +// CVS Reference : /PMC_SAM7S_USB.pl/1.4/Tue Feb 8 14:00:19 2005// +// CVS Reference : /RSTC_SAM7X.pl/1.2/Wed Jul 13 15:25:17 2005// +// CVS Reference : /UDP_8ept_puon.pl/1.1/Wed Aug 30 13:10:57 2006// +// CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 12:38:54 2005// +// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005// +// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005// +// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004// +// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004// +// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004// +// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:40:38 2005// +// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005// +// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005// +// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005// +// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005// +// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004// +// CVS Reference : /TWI_6061B.pl/1.2/Fri Aug 4 08:47:25 2006// +// CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005// +// CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005// +// CVS Reference : /EBI_SAM7SE512.pl/1.22/Fri Nov 18 17:47:47 2005// +// CVS Reference : /SMC_1783A.pl/1.4/Thu Feb 3 10:30:06 2005// +// CVS Reference : /SDRC_SAM7SE512.pl/1.7/Fri Jul 8 07:50:18 2005// +// CVS Reference : /HECC_SAM7SE512.pl/1.8/Tue Jul 12 06:31:42 2005// +// ---------------------------------------------------------------------------- + +#ifndef AT91SAM7SE512_H +#define AT91SAM7SE512_H + +#ifndef __ASSEMBLY__ +typedef volatile unsigned int AT91_REG;// Hardware register definition +#define AT91_CAST(a) (a) +#else +#define AT91_CAST(a) +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR System Peripherals +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SYS { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register + AT91_REG Reserved2[45]; // + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved3[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved4[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register + AT91_REG Reserved5[54]; // + AT91_REG PIOA_PER; // PIO Enable Register + AT91_REG PIOA_PDR; // PIO Disable Register + AT91_REG PIOA_PSR; // PIO Status Register + AT91_REG Reserved6[1]; // + AT91_REG PIOA_OER; // Output Enable Register + AT91_REG PIOA_ODR; // Output Disable Registerr + AT91_REG PIOA_OSR; // Output Status Register + AT91_REG Reserved7[1]; // + AT91_REG PIOA_IFER; // Input Filter Enable Register + AT91_REG PIOA_IFDR; // Input Filter Disable Register + AT91_REG PIOA_IFSR; // Input Filter Status Register + AT91_REG Reserved8[1]; // + AT91_REG PIOA_SODR; // Set Output Data Register + AT91_REG PIOA_CODR; // Clear Output Data Register + AT91_REG PIOA_ODSR; // Output Data Status Register + AT91_REG PIOA_PDSR; // Pin Data Status Register + AT91_REG PIOA_IER; // Interrupt Enable Register + AT91_REG PIOA_IDR; // Interrupt Disable Register + AT91_REG PIOA_IMR; // Interrupt Mask Register + AT91_REG PIOA_ISR; // Interrupt Status Register + AT91_REG PIOA_MDER; // Multi-driver Enable Register + AT91_REG PIOA_MDDR; // Multi-driver Disable Register + AT91_REG PIOA_MDSR; // Multi-driver Status Register + AT91_REG Reserved9[1]; // + AT91_REG PIOA_PPUDR; // Pull-up Disable Register + AT91_REG PIOA_PPUER; // Pull-up Enable Register + AT91_REG PIOA_PPUSR; // Pull-up Status Register + AT91_REG Reserved10[1]; // + AT91_REG PIOA_ASR; // Select A Register + AT91_REG PIOA_BSR; // Select B Register + AT91_REG PIOA_ABSR; // AB Select Status Register + AT91_REG Reserved11[9]; // + AT91_REG PIOA_OWER; // Output Write Enable Register + AT91_REG PIOA_OWDR; // Output Write Disable Register + AT91_REG PIOA_OWSR; // Output Write Status Register + AT91_REG Reserved12[85]; // + AT91_REG PIOB_PER; // PIO Enable Register + AT91_REG PIOB_PDR; // PIO Disable Register + AT91_REG PIOB_PSR; // PIO Status Register + AT91_REG Reserved13[1]; // + AT91_REG PIOB_OER; // Output Enable Register + AT91_REG PIOB_ODR; // Output Disable Registerr + AT91_REG PIOB_OSR; // Output Status Register + AT91_REG Reserved14[1]; // + AT91_REG PIOB_IFER; // Input Filter Enable Register + AT91_REG PIOB_IFDR; // Input Filter Disable Register + AT91_REG PIOB_IFSR; // Input Filter Status Register + AT91_REG Reserved15[1]; // + AT91_REG PIOB_SODR; // Set Output Data Register + AT91_REG PIOB_CODR; // Clear Output Data Register + AT91_REG PIOB_ODSR; // Output Data Status Register + AT91_REG PIOB_PDSR; // Pin Data Status Register + AT91_REG PIOB_IER; // Interrupt Enable Register + AT91_REG PIOB_IDR; // Interrupt Disable Register + AT91_REG PIOB_IMR; // Interrupt Mask Register + AT91_REG PIOB_ISR; // Interrupt Status Register + AT91_REG PIOB_MDER; // Multi-driver Enable Register + AT91_REG PIOB_MDDR; // Multi-driver Disable Register + AT91_REG PIOB_MDSR; // Multi-driver Status Register + AT91_REG Reserved16[1]; // + AT91_REG PIOB_PPUDR; // Pull-up Disable Register + AT91_REG PIOB_PPUER; // Pull-up Enable Register + AT91_REG PIOB_PPUSR; // Pull-up Status Register + AT91_REG Reserved17[1]; // + AT91_REG PIOB_ASR; // Select A Register + AT91_REG PIOB_BSR; // Select B Register + AT91_REG PIOB_ABSR; // AB Select Status Register + AT91_REG Reserved18[9]; // + AT91_REG PIOB_OWER; // Output Write Enable Register + AT91_REG PIOB_OWDR; // Output Write Disable Register + AT91_REG PIOB_OWSR; // Output Write Status Register + AT91_REG Reserved19[341]; // + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved20[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved21[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved22[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved23[3]; // + AT91_REG PMC_PCKR[3]; // Programmable Clock Register + AT91_REG Reserved24[5]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register + AT91_REG Reserved25[36]; // + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register + AT91_REG Reserved26[5]; // + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register + AT91_REG Reserved27[5]; // + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_SYS, *AT91PS_SYS; +#else + +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_AIC { + AT91_REG AIC_SMR[32]; // Source Mode Register + AT91_REG AIC_SVR[32]; // Source Vector Register + AT91_REG AIC_IVR; // IRQ Vector Register + AT91_REG AIC_FVR; // FIQ Vector Register + AT91_REG AIC_ISR; // Interrupt Status Register + AT91_REG AIC_IPR; // Interrupt Pending Register + AT91_REG AIC_IMR; // Interrupt Mask Register + AT91_REG AIC_CISR; // Core Interrupt Status Register + AT91_REG Reserved0[2]; // + AT91_REG AIC_IECR; // Interrupt Enable Command Register + AT91_REG AIC_IDCR; // Interrupt Disable Command Register + AT91_REG AIC_ICCR; // Interrupt Clear Command Register + AT91_REG AIC_ISCR; // Interrupt Set Command Register + AT91_REG AIC_EOICR; // End of Interrupt Command Register + AT91_REG AIC_SPU; // Spurious Vector Register + AT91_REG AIC_DCR; // Debug Control Register (Protect) + AT91_REG Reserved1[1]; // + AT91_REG AIC_FFER; // Fast Forcing Enable Register + AT91_REG AIC_FFDR; // Fast Forcing Disable Register + AT91_REG AIC_FFSR; // Fast Forcing Status Register +} AT91S_AIC, *AT91PS_AIC; +#else +#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register +#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register +#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register +#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register +#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register +#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register +#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register +#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register +#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register +#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register +#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register +#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register +#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register +#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register +#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect) +#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register +#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register +#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register + +#endif +// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- +#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level +#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level +#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level +#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type +#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive +#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered +#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered +#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive +#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered +// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- +#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status +#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status +// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- +#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode +#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Peripheral DMA Controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PDC { + AT91_REG PDC_RPR; // Receive Pointer Register + AT91_REG PDC_RCR; // Receive Counter Register + AT91_REG PDC_TPR; // Transmit Pointer Register + AT91_REG PDC_TCR; // Transmit Counter Register + AT91_REG PDC_RNPR; // Receive Next Pointer Register + AT91_REG PDC_RNCR; // Receive Next Counter Register + AT91_REG PDC_TNPR; // Transmit Next Pointer Register + AT91_REG PDC_TNCR; // Transmit Next Counter Register + AT91_REG PDC_PTCR; // PDC Transfer Control Register + AT91_REG PDC_PTSR; // PDC Transfer Status Register +} AT91S_PDC, *AT91PS_PDC; +#else +#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register +#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register +#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register +#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register +#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register +#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register +#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register +#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register +#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register +#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register + +#endif +// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- +#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable +#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable +#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable +#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable +// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Debug Unit +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_DBGU { + AT91_REG DBGU_CR; // Control Register + AT91_REG DBGU_MR; // Mode Register + AT91_REG DBGU_IER; // Interrupt Enable Register + AT91_REG DBGU_IDR; // Interrupt Disable Register + AT91_REG DBGU_IMR; // Interrupt Mask Register + AT91_REG DBGU_CSR; // Channel Status Register + AT91_REG DBGU_RHR; // Receiver Holding Register + AT91_REG DBGU_THR; // Transmitter Holding Register + AT91_REG DBGU_BRGR; // Baud Rate Generator Register + AT91_REG Reserved0[7]; // + AT91_REG DBGU_CIDR; // Chip ID Register + AT91_REG DBGU_EXID; // Chip ID Extension Register + AT91_REG DBGU_FNTR; // Force NTRST Register + AT91_REG Reserved1[45]; // + AT91_REG DBGU_RPR; // Receive Pointer Register + AT91_REG DBGU_RCR; // Receive Counter Register + AT91_REG DBGU_TPR; // Transmit Pointer Register + AT91_REG DBGU_TCR; // Transmit Counter Register + AT91_REG DBGU_RNPR; // Receive Next Pointer Register + AT91_REG DBGU_RNCR; // Receive Next Counter Register + AT91_REG DBGU_TNPR; // Transmit Next Pointer Register + AT91_REG DBGU_TNCR; // Transmit Next Counter Register + AT91_REG DBGU_PTCR; // PDC Transfer Control Register + AT91_REG DBGU_PTSR; // PDC Transfer Status Register +} AT91S_DBGU, *AT91PS_DBGU; +#else +#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register +#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register +#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register +#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register +#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register +#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register +#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register +#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register +#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register +#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register +#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register +#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register + +#endif +// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver +#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter +#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable +#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable +#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable +#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable +#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits +// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type +#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity +#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity +#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) +#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) +#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity +#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode +#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode +#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. +#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. +#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. +#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. +// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt +#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt +#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt +#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt +#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt +#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt +#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt +#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt +#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt +#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt +#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt +#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt +// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- +// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- +#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Parallel Input Output Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PIO { + AT91_REG PIO_PER; // PIO Enable Register + AT91_REG PIO_PDR; // PIO Disable Register + AT91_REG PIO_PSR; // PIO Status Register + AT91_REG Reserved0[1]; // + AT91_REG PIO_OER; // Output Enable Register + AT91_REG PIO_ODR; // Output Disable Registerr + AT91_REG PIO_OSR; // Output Status Register + AT91_REG Reserved1[1]; // + AT91_REG PIO_IFER; // Input Filter Enable Register + AT91_REG PIO_IFDR; // Input Filter Disable Register + AT91_REG PIO_IFSR; // Input Filter Status Register + AT91_REG Reserved2[1]; // + AT91_REG PIO_SODR; // Set Output Data Register + AT91_REG PIO_CODR; // Clear Output Data Register + AT91_REG PIO_ODSR; // Output Data Status Register + AT91_REG PIO_PDSR; // Pin Data Status Register + AT91_REG PIO_IER; // Interrupt Enable Register + AT91_REG PIO_IDR; // Interrupt Disable Register + AT91_REG PIO_IMR; // Interrupt Mask Register + AT91_REG PIO_ISR; // Interrupt Status Register + AT91_REG PIO_MDER; // Multi-driver Enable Register + AT91_REG PIO_MDDR; // Multi-driver Disable Register + AT91_REG PIO_MDSR; // Multi-driver Status Register + AT91_REG Reserved3[1]; // + AT91_REG PIO_PPUDR; // Pull-up Disable Register + AT91_REG PIO_PPUER; // Pull-up Enable Register + AT91_REG PIO_PPUSR; // Pull-up Status Register + AT91_REG Reserved4[1]; // + AT91_REG PIO_ASR; // Select A Register + AT91_REG PIO_BSR; // Select B Register + AT91_REG PIO_ABSR; // AB Select Status Register + AT91_REG Reserved5[9]; // + AT91_REG PIO_OWER; // Output Write Enable Register + AT91_REG PIO_OWDR; // Output Write Disable Register + AT91_REG PIO_OWSR; // Output Write Status Register +} AT91S_PIO, *AT91PS_PIO; +#else +#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register +#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register +#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register +#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register +#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr +#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register +#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register +#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register +#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register +#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register +#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register +#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register +#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register +#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register +#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register +#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register +#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register +#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register +#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register +#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register +#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register +#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register +#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register +#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register +#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register +#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register +#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register +#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register +#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register + +#endif + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Clock Generator Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_CKGR { + AT91_REG CKGR_MOR; // Main Oscillator Register + AT91_REG CKGR_MCFR; // Main Clock Frequency Register + AT91_REG Reserved0[1]; // + AT91_REG CKGR_PLLR; // PLL Register +} AT91S_CKGR, *AT91PS_CKGR; +#else +#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register +#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register +#define CKGR_PLLR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLR) PLL Register + +#endif +// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- +#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable +#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass +#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time +// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- +#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency +#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready +// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- +#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected +#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 +#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed +#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter +#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range +#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet +#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier +#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks +#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output +#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 +#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Power Management Controler +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PMC { + AT91_REG PMC_SCER; // System Clock Enable Register + AT91_REG PMC_SCDR; // System Clock Disable Register + AT91_REG PMC_SCSR; // System Clock Status Register + AT91_REG Reserved0[1]; // + AT91_REG PMC_PCER; // Peripheral Clock Enable Register + AT91_REG PMC_PCDR; // Peripheral Clock Disable Register + AT91_REG PMC_PCSR; // Peripheral Clock Status Register + AT91_REG Reserved1[1]; // + AT91_REG PMC_MOR; // Main Oscillator Register + AT91_REG PMC_MCFR; // Main Clock Frequency Register + AT91_REG Reserved2[1]; // + AT91_REG PMC_PLLR; // PLL Register + AT91_REG PMC_MCKR; // Master Clock Register + AT91_REG Reserved3[3]; // + AT91_REG PMC_PCKR[3]; // Programmable Clock Register + AT91_REG Reserved4[5]; // + AT91_REG PMC_IER; // Interrupt Enable Register + AT91_REG PMC_IDR; // Interrupt Disable Register + AT91_REG PMC_SR; // Status Register + AT91_REG PMC_IMR; // Interrupt Mask Register +} AT91S_PMC, *AT91PS_PMC; +#else +#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register +#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register +#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register +#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register +#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register +#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register +#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register +#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register +#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register +#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register +#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register +#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register + +#endif +// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- +#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock +#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock +#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output +#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output +// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- +// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- +// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- +// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- +// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- +// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- +#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection +#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected +#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected +#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected +#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler +#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock +#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 +#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 +#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 +#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 +#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 +#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 +// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- +// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- +#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask +#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask +#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask +#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask +// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- +// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- +// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Reset Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_RSTC { + AT91_REG RSTC_RCR; // Reset Control Register + AT91_REG RSTC_RSR; // Reset Status Register + AT91_REG RSTC_RMR; // Reset Mode Register +} AT91S_RSTC, *AT91PS_RSTC; +#else +#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register +#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register +#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register + +#endif +// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- +#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset +#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset +#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset +#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password +// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- +#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status +#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status +#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type +#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. +#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. +#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. +#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. +#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured. +#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level +#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. +// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- +#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable +#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable +#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Length +#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_RTTC { + AT91_REG RTTC_RTMR; // Real-time Mode Register + AT91_REG RTTC_RTAR; // Real-time Alarm Register + AT91_REG RTTC_RTVR; // Real-time Value Register + AT91_REG RTTC_RTSR; // Real-time Status Register +} AT91S_RTTC, *AT91PS_RTTC; +#else +#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register +#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register +#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register +#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register + +#endif +// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- +#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value +#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable +#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable +#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart +// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- +#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value +// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- +#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value +// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- +#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status +#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PITC { + AT91_REG PITC_PIMR; // Period Interval Mode Register + AT91_REG PITC_PISR; // Period Interval Status Register + AT91_REG PITC_PIVR; // Period Interval Value Register + AT91_REG PITC_PIIR; // Period Interval Image Register +} AT91S_PITC, *AT91PS_PITC; +#else +#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register +#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register +#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register +#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register + +#endif +// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- +#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value +#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled +#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable +// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- +#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status +// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- +#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value +#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter +// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_WDTC { + AT91_REG WDTC_WDCR; // Watchdog Control Register + AT91_REG WDTC_WDMR; // Watchdog Mode Register + AT91_REG WDTC_WDSR; // Watchdog Status Register +} AT91S_WDTC, *AT91PS_WDTC; +#else +#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register +#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register +#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register + +#endif +// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- +#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart +#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password +// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- +#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable +#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable +#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart +#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable +#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value +#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt +#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt +// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- +#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow +#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_VREG { + AT91_REG VREG_MR; // Voltage Regulator Mode Register +} AT91S_VREG, *AT91PS_VREG; +#else +#define VREG_MR (AT91_CAST(AT91_REG *) 0x00000000) // (VREG_MR) Voltage Regulator Mode Register + +#endif +// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- +#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Memory Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_MC { + AT91_REG MC_RCR; // MC Remap Control Register + AT91_REG MC_ASR; // MC Abort Status Register + AT91_REG MC_AASR; // MC Abort Address Status Register + AT91_REG Reserved0[1]; // + AT91_REG MC_PUIA[16]; // MC Protection Unit Area + AT91_REG MC_PUP; // MC Protection Unit Peripherals + AT91_REG MC_PUER; // MC Protection Unit Enable Register + AT91_REG Reserved1[2]; // + AT91_REG MC0_FMR; // MC Flash Mode Register + AT91_REG MC0_FCR; // MC Flash Command Register + AT91_REG MC0_FSR; // MC Flash Status Register + AT91_REG MC0_VR; // MC Flash Version Register + AT91_REG MC1_FMR; // MC Flash Mode Register + AT91_REG MC1_FCR; // MC Flash Command Register + AT91_REG MC1_FSR; // MC Flash Status Register + AT91_REG MC1_VR; // MC Flash Version Register +} AT91S_MC, *AT91PS_MC; +#else +#define MC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_RCR) MC Remap Control Register +#define MC_ASR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_ASR) MC Abort Status Register +#define MC_AASR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_AASR) MC Abort Address Status Register +#define MC_PUIA (AT91_CAST(AT91_REG *) 0x00000010) // (MC_PUIA) MC Protection Unit Area +#define MC_PUP (AT91_CAST(AT91_REG *) 0x00000050) // (MC_PUP) MC Protection Unit Peripherals +#define MC_PUER (AT91_CAST(AT91_REG *) 0x00000054) // (MC_PUER) MC Protection Unit Enable Register + +#endif +// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- +#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit +// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- +#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status +#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status +#define AT91C_MC_MPU (0x1 << 2) // (MC) Memory protection Unit Abort Status +#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status +#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte +#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word +#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word +#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status +#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read +#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write +#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch +#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source +#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source +#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source +#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source +// -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area -------- +#define AT91C_MC_PROT (0x3 << 0) // (MC) Protection +#define AT91C_MC_PROT_PNAUNA (0x0) // (MC) Privilege: No Access, User: No Access +#define AT91C_MC_PROT_PRWUNA (0x1) // (MC) Privilege: Read/Write, User: No Access +#define AT91C_MC_PROT_PRWURO (0x2) // (MC) Privilege: Read/Write, User: Read Only +#define AT91C_MC_PROT_PRWURW (0x3) // (MC) Privilege: Read/Write, User: Read/Write +#define AT91C_MC_SIZE (0xF << 4) // (MC) Internal Area Size +#define AT91C_MC_SIZE_1KB (0x0 << 4) // (MC) Area size 1KByte +#define AT91C_MC_SIZE_2KB (0x1 << 4) // (MC) Area size 2KByte +#define AT91C_MC_SIZE_4KB (0x2 << 4) // (MC) Area size 4KByte +#define AT91C_MC_SIZE_8KB (0x3 << 4) // (MC) Area size 8KByte +#define AT91C_MC_SIZE_16KB (0x4 << 4) // (MC) Area size 16KByte +#define AT91C_MC_SIZE_32KB (0x5 << 4) // (MC) Area size 32KByte +#define AT91C_MC_SIZE_64KB (0x6 << 4) // (MC) Area size 64KByte +#define AT91C_MC_SIZE_128KB (0x7 << 4) // (MC) Area size 128KByte +#define AT91C_MC_SIZE_256KB (0x8 << 4) // (MC) Area size 256KByte +#define AT91C_MC_SIZE_512KB (0x9 << 4) // (MC) Area size 512KByte +#define AT91C_MC_SIZE_1MB (0xA << 4) // (MC) Area size 1MByte +#define AT91C_MC_SIZE_2MB (0xB << 4) // (MC) Area size 2MByte +#define AT91C_MC_SIZE_4MB (0xC << 4) // (MC) Area size 4MByte +#define AT91C_MC_SIZE_8MB (0xD << 4) // (MC) Area size 8MByte +#define AT91C_MC_SIZE_16MB (0xE << 4) // (MC) Area size 16MByte +#define AT91C_MC_SIZE_64MB (0xF << 4) // (MC) Area size 64MByte +#define AT91C_MC_BA (0x3FFFF << 10) // (MC) Internal Area Base Address +// -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral -------- +// -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area -------- +#define AT91C_MC_PUEB (0x1 << 0) // (MC) Protection Unit enable Bit + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Embedded Flash Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_EFC { + AT91_REG EFC_FMR; // MC Flash Mode Register + AT91_REG EFC_FCR; // MC Flash Command Register + AT91_REG EFC_FSR; // MC Flash Status Register + AT91_REG EFC_VR; // MC Flash Version Register +} AT91S_EFC, *AT91PS_EFC; +#else +#define MC_FMR (AT91_CAST(AT91_REG *) 0x00000000) // (MC_FMR) MC Flash Mode Register +#define MC_FCR (AT91_CAST(AT91_REG *) 0x00000004) // (MC_FCR) MC Flash Command Register +#define MC_FSR (AT91_CAST(AT91_REG *) 0x00000008) // (MC_FSR) MC Flash Status Register +#define MC_VR (AT91_CAST(AT91_REG *) 0x0000000C) // (MC_VR) MC Flash Version Register + +#endif +// -------- MC_FMR : (EFC Offset: 0x0) MC Flash Mode Register -------- +#define AT91C_MC_FRDY (0x1 << 0) // (EFC) Flash Ready +#define AT91C_MC_LOCKE (0x1 << 2) // (EFC) Lock Error +#define AT91C_MC_PROGE (0x1 << 3) // (EFC) Programming Error +#define AT91C_MC_NEBP (0x1 << 7) // (EFC) No Erase Before Programming +#define AT91C_MC_FWS (0x3 << 8) // (EFC) Flash Wait State +#define AT91C_MC_FWS_0FWS (0x0 << 8) // (EFC) 1 cycle for Read, 2 for Write operations +#define AT91C_MC_FWS_1FWS (0x1 << 8) // (EFC) 2 cycles for Read, 3 for Write operations +#define AT91C_MC_FWS_2FWS (0x2 << 8) // (EFC) 3 cycles for Read, 4 for Write operations +#define AT91C_MC_FWS_3FWS (0x3 << 8) // (EFC) 4 cycles for Read, 4 for Write operations +#define AT91C_MC_FMCN (0xFF << 16) // (EFC) Flash Microsecond Cycle Number +// -------- MC_FCR : (EFC Offset: 0x4) MC Flash Command Register -------- +#define AT91C_MC_FCMD (0xF << 0) // (EFC) Flash Command +#define AT91C_MC_FCMD_START_PROG (0x1) // (EFC) Starts the programming of th epage specified by PAGEN. +#define AT91C_MC_FCMD_LOCK (0x2) // (EFC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (EFC) The lock sequence automatically happens after the programming sequence is completed. +#define AT91C_MC_FCMD_UNLOCK (0x4) // (EFC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. +#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (EFC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. +#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (EFC) Set General Purpose NVM bits. +#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (EFC) Clear General Purpose NVM bits. +#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (EFC) Set Security Bit. +#define AT91C_MC_PAGEN (0x3FF << 8) // (EFC) Page Number +#define AT91C_MC_KEY (0xFF << 24) // (EFC) Writing Protect Key +// -------- MC_FSR : (EFC Offset: 0x8) MC Flash Command Register -------- +#define AT91C_MC_SECURITY (0x1 << 4) // (EFC) Security Bit Status +#define AT91C_MC_GPNVM0 (0x1 << 8) // (EFC) Sector 0 Lock Status +#define AT91C_MC_GPNVM1 (0x1 << 9) // (EFC) Sector 1 Lock Status +#define AT91C_MC_GPNVM2 (0x1 << 10) // (EFC) Sector 2 Lock Status +#define AT91C_MC_GPNVM3 (0x1 << 11) // (EFC) Sector 3 Lock Status +#define AT91C_MC_GPNVM4 (0x1 << 12) // (EFC) Sector 4 Lock Status +#define AT91C_MC_GPNVM5 (0x1 << 13) // (EFC) Sector 5 Lock Status +#define AT91C_MC_GPNVM6 (0x1 << 14) // (EFC) Sector 6 Lock Status +#define AT91C_MC_GPNVM7 (0x1 << 15) // (EFC) Sector 7 Lock Status +#define AT91C_MC_LOCKS0 (0x1 << 16) // (EFC) Sector 0 Lock Status +#define AT91C_MC_LOCKS1 (0x1 << 17) // (EFC) Sector 1 Lock Status +#define AT91C_MC_LOCKS2 (0x1 << 18) // (EFC) Sector 2 Lock Status +#define AT91C_MC_LOCKS3 (0x1 << 19) // (EFC) Sector 3 Lock Status +#define AT91C_MC_LOCKS4 (0x1 << 20) // (EFC) Sector 4 Lock Status +#define AT91C_MC_LOCKS5 (0x1 << 21) // (EFC) Sector 5 Lock Status +#define AT91C_MC_LOCKS6 (0x1 << 22) // (EFC) Sector 6 Lock Status +#define AT91C_MC_LOCKS7 (0x1 << 23) // (EFC) Sector 7 Lock Status +#define AT91C_MC_LOCKS8 (0x1 << 24) // (EFC) Sector 8 Lock Status +#define AT91C_MC_LOCKS9 (0x1 << 25) // (EFC) Sector 9 Lock Status +#define AT91C_MC_LOCKS10 (0x1 << 26) // (EFC) Sector 10 Lock Status +#define AT91C_MC_LOCKS11 (0x1 << 27) // (EFC) Sector 11 Lock Status +#define AT91C_MC_LOCKS12 (0x1 << 28) // (EFC) Sector 12 Lock Status +#define AT91C_MC_LOCKS13 (0x1 << 29) // (EFC) Sector 13 Lock Status +#define AT91C_MC_LOCKS14 (0x1 << 30) // (EFC) Sector 14 Lock Status +#define AT91C_MC_LOCKS15 (0x1 << 31) // (EFC) Sector 15 Lock Status +// -------- EFC_VR : (EFC Offset: 0xc) EFC version register -------- +#define AT91C_EFC_VERSION (0xFFF << 0) // (EFC) EFC version number +#define AT91C_EFC_MFN (0x7 << 16) // (EFC) EFC MFN + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Serial Parallel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SPI { + AT91_REG SPI_CR; // Control Register + AT91_REG SPI_MR; // Mode Register + AT91_REG SPI_RDR; // Receive Data Register + AT91_REG SPI_TDR; // Transmit Data Register + AT91_REG SPI_SR; // Status Register + AT91_REG SPI_IER; // Interrupt Enable Register + AT91_REG SPI_IDR; // Interrupt Disable Register + AT91_REG SPI_IMR; // Interrupt Mask Register + AT91_REG Reserved0[4]; // + AT91_REG SPI_CSR[4]; // Chip Select Register + AT91_REG Reserved1[48]; // + AT91_REG SPI_RPR; // Receive Pointer Register + AT91_REG SPI_RCR; // Receive Counter Register + AT91_REG SPI_TPR; // Transmit Pointer Register + AT91_REG SPI_TCR; // Transmit Counter Register + AT91_REG SPI_RNPR; // Receive Next Pointer Register + AT91_REG SPI_RNCR; // Receive Next Counter Register + AT91_REG SPI_TNPR; // Transmit Next Pointer Register + AT91_REG SPI_TNCR; // Transmit Next Counter Register + AT91_REG SPI_PTCR; // PDC Transfer Control Register + AT91_REG SPI_PTSR; // PDC Transfer Status Register +} AT91S_SPI, *AT91PS_SPI; +#else +#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register +#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register +#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register +#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register +#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register +#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register +#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register +#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register +#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register + +#endif +// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- +#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable +#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable +#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset +#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer +// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- +#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode +#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select +#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select +#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select +#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode +#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection +#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection +#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection +#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select +#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects +// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- +#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data +#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- +#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data +#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status +// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- +#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full +#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty +#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error +#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status +#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer +#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer +#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt +#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt +#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt +#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt +#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status +// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- +// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- +// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- +// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- +#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity +#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase +#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer +#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer +#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer +#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer +#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer +#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer +#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer +#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer +#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer +#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer +#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer +#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate +#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK +#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Usart +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_USART { + AT91_REG US_CR; // Control Register + AT91_REG US_MR; // Mode Register + AT91_REG US_IER; // Interrupt Enable Register + AT91_REG US_IDR; // Interrupt Disable Register + AT91_REG US_IMR; // Interrupt Mask Register + AT91_REG US_CSR; // Channel Status Register + AT91_REG US_RHR; // Receiver Holding Register + AT91_REG US_THR; // Transmitter Holding Register + AT91_REG US_BRGR; // Baud Rate Generator Register + AT91_REG US_RTOR; // Receiver Time-out Register + AT91_REG US_TTGR; // Transmitter Time-guard Register + AT91_REG Reserved0[5]; // + AT91_REG US_FIDI; // FI_DI_Ratio Register + AT91_REG US_NER; // Nb Errors Register + AT91_REG Reserved1[1]; // + AT91_REG US_IF; // IRDA_FILTER Register + AT91_REG Reserved2[44]; // + AT91_REG US_RPR; // Receive Pointer Register + AT91_REG US_RCR; // Receive Counter Register + AT91_REG US_TPR; // Transmit Pointer Register + AT91_REG US_TCR; // Transmit Counter Register + AT91_REG US_RNPR; // Receive Next Pointer Register + AT91_REG US_RNCR; // Receive Next Counter Register + AT91_REG US_TNPR; // Transmit Next Pointer Register + AT91_REG US_TNCR; // Transmit Next Counter Register + AT91_REG US_PTCR; // PDC Transfer Control Register + AT91_REG US_PTSR; // PDC Transfer Status Register +} AT91S_USART, *AT91PS_USART; +#else +#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register +#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register +#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register +#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register +#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register +#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register +#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register +#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register +#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register +#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register +#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register +#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register +#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register +#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register + +#endif +// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- +#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break +#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break +#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out +#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address +#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations +#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge +#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out +#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable +#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable +#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable +#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable +// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- +#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode +#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal +#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 +#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking +#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem +#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 +#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 +#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA +#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking +#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock +#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 +#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) +#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) +#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock +#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits +#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits +#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits +#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits +#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select +#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits +#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit +#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits +#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits +#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order +#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length +#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select +#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode +#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge +#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK +#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions +#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter +// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- +#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break +#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out +#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached +#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge +#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag +#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag +#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag +#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag +// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- +// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- +// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- +#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input +#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input +#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input +#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SSC { + AT91_REG SSC_CR; // Control Register + AT91_REG SSC_CMR; // Clock Mode Register + AT91_REG Reserved0[2]; // + AT91_REG SSC_RCMR; // Receive Clock ModeRegister + AT91_REG SSC_RFMR; // Receive Frame Mode Register + AT91_REG SSC_TCMR; // Transmit Clock Mode Register + AT91_REG SSC_TFMR; // Transmit Frame Mode Register + AT91_REG SSC_RHR; // Receive Holding Register + AT91_REG SSC_THR; // Transmit Holding Register + AT91_REG Reserved1[2]; // + AT91_REG SSC_RSHR; // Receive Sync Holding Register + AT91_REG SSC_TSHR; // Transmit Sync Holding Register + AT91_REG Reserved2[2]; // + AT91_REG SSC_SR; // Status Register + AT91_REG SSC_IER; // Interrupt Enable Register + AT91_REG SSC_IDR; // Interrupt Disable Register + AT91_REG SSC_IMR; // Interrupt Mask Register + AT91_REG Reserved3[44]; // + AT91_REG SSC_RPR; // Receive Pointer Register + AT91_REG SSC_RCR; // Receive Counter Register + AT91_REG SSC_TPR; // Transmit Pointer Register + AT91_REG SSC_TCR; // Transmit Counter Register + AT91_REG SSC_RNPR; // Receive Next Pointer Register + AT91_REG SSC_RNCR; // Receive Next Counter Register + AT91_REG SSC_TNPR; // Transmit Next Pointer Register + AT91_REG SSC_TNCR; // Transmit Next Counter Register + AT91_REG SSC_PTCR; // PDC Transfer Control Register + AT91_REG SSC_PTSR; // PDC Transfer Status Register +} AT91S_SSC, *AT91PS_SSC; +#else +#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register +#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register +#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister +#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register +#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register +#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register +#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register +#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register +#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register +#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register +#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register +#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register +#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register +#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register + +#endif +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin +#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Two-wire Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TWI { + AT91_REG TWI_CR; // Control Register + AT91_REG TWI_MMR; // Master Mode Register + AT91_REG TWI_SMR; // Slave Mode Register + AT91_REG TWI_IADR; // Internal Address Register + AT91_REG TWI_CWGR; // Clock Waveform Generator Register + AT91_REG Reserved0[3]; // + AT91_REG TWI_SR; // Status Register + AT91_REG TWI_IER; // Interrupt Enable Register + AT91_REG TWI_IDR; // Interrupt Disable Register + AT91_REG TWI_IMR; // Interrupt Mask Register + AT91_REG TWI_RHR; // Receive Holding Register + AT91_REG TWI_THR; // Transmit Holding Register + AT91_REG Reserved1[50]; // + AT91_REG TWI_RPR; // Receive Pointer Register + AT91_REG TWI_RCR; // Receive Counter Register + AT91_REG TWI_TPR; // Transmit Pointer Register + AT91_REG TWI_TCR; // Transmit Counter Register + AT91_REG TWI_RNPR; // Receive Next Pointer Register + AT91_REG TWI_RNCR; // Receive Next Counter Register + AT91_REG TWI_TNPR; // Transmit Next Pointer Register + AT91_REG TWI_TNCR; // Transmit Next Counter Register + AT91_REG TWI_PTCR; // PDC Transfer Control Register + AT91_REG TWI_PTSR; // PDC Transfer Status Register +} AT91S_TWI, *AT91PS_TWI; +#else +#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register +#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register +#define TWI_SMR (AT91_CAST(AT91_REG *) 0x00000008) // (TWI_SMR) Slave Mode Register +#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register +#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register +#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register +#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register +#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register +#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register +#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register +#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register + +#endif +// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- +#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition +#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition +#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled +#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled +#define AT91C_TWI_SVEN (0x1 << 4) // (TWI) TWI Slave mode Enabled +#define AT91C_TWI_SVDIS (0x1 << 5) // (TWI) TWI Slave mode Disabled +#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset +// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- +#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size +#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address +#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address +#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address +#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address +#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction +#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address +// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- +#define AT91C_TWI_SADR (0x7F << 16) // (TWI) Slave Address +// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- +#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider +#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider +#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider +// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- +#define AT91C_TWI_TXCOMP_SLAVE (0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_TXCOMP_MASTER (0x1 << 0) // (TWI) Transmission Completed +#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY +#define AT91C_TWI_TXRDY_MASTER (0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_TXRDY_SLAVE (0x1 << 2) // (TWI) Transmit holding register ReaDY +#define AT91C_TWI_SVREAD (0x1 << 3) // (TWI) Slave READ (used only in Slave mode) +#define AT91C_TWI_SVACC (0x1 << 4) // (TWI) Slave ACCess (used only in Slave mode) +#define AT91C_TWI_GACC (0x1 << 5) // (TWI) General Call ACcess (used only in Slave mode) +#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error (used only in Master and Multi-master mode) +#define AT91C_TWI_NACK_SLAVE (0x1 << 8) // (TWI) Not Acknowledged +#define AT91C_TWI_NACK_MASTER (0x1 << 8) // (TWI) Not Acknowledged +#define AT91C_TWI_ARBLST_MULTI_MASTER (0x1 << 9) // (TWI) Arbitration Lost (used only in Multimaster mode) +#define AT91C_TWI_SCLWS (0x1 << 10) // (TWI) Clock Wait State (used only in Slave mode) +#define AT91C_TWI_EOSACC (0x1 << 11) // (TWI) End Of Slave ACCess (used only in Slave mode) +#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI) End of Receiver Transfer +#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI) End of Receiver Transfer +#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI) RXBUFF Interrupt +#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI) TXBUFE Interrupt +// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- +// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- +// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR PWMC Channel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PWMC_CH { + AT91_REG PWMC_CMR; // Channel Mode Register + AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register + AT91_REG PWMC_CPRDR; // Channel Period Register + AT91_REG PWMC_CCNTR; // Channel Counter Register + AT91_REG PWMC_CUPDR; // Channel Update Register + AT91_REG PWMC_Reserved[3]; // Reserved +} AT91S_PWMC_CH, *AT91PS_PWMC_CH; +#else +#define PWMC_CMR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_CMR) Channel Mode Register +#define PWMC_CDTYR (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register +#define PWMC_CPRDR (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_CPRDR) Channel Period Register +#define PWMC_CCNTR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_CCNTR) Channel Counter Register +#define PWMC_CUPDR (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_CUPDR) Channel Update Register +#define Reserved (AT91_CAST(AT91_REG *) 0x00000014) // (Reserved) Reserved + +#endif +// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- +#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx +#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) +#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) +#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment +#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity +#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period +// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- +#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle +// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- +#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period +// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- +#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter +// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- +#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_PWMC { + AT91_REG PWMC_MR; // PWMC Mode Register + AT91_REG PWMC_ENA; // PWMC Enable Register + AT91_REG PWMC_DIS; // PWMC Disable Register + AT91_REG PWMC_SR; // PWMC Status Register + AT91_REG PWMC_IER; // PWMC Interrupt Enable Register + AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register + AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register + AT91_REG PWMC_ISR; // PWMC Interrupt Status Register + AT91_REG Reserved0[55]; // + AT91_REG PWMC_VR; // PWMC Version Register + AT91_REG Reserved1[64]; // + AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel +} AT91S_PWMC, *AT91PS_PWMC; +#else +#define PWMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_MR) PWMC Mode Register +#define PWMC_ENA (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_ENA) PWMC Enable Register +#define PWMC_DIS (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_DIS) PWMC Disable Register +#define PWMC_SR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_SR) PWMC Status Register +#define PWMC_IER (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_IER) PWMC Interrupt Enable Register +#define PWMC_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (PWMC_IDR) PWMC Interrupt Disable Register +#define PWMC_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (PWMC_IMR) PWMC Interrupt Mask Register +#define PWMC_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (PWMC_ISR) PWMC Interrupt Status Register +#define PWMC_VR (AT91_CAST(AT91_REG *) 0x000000FC) // (PWMC_VR) PWMC Version Register + +#endif +// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- +#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. +#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A +#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) +#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. +#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B +#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) +// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- +#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 +#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 +#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 +#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 +// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- +// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- +// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- +// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- +// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- +// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR USB Device Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_UDP { + AT91_REG UDP_NUM; // Frame Number Register + AT91_REG UDP_GLBSTATE; // Global State Register + AT91_REG UDP_FADDR; // Function Address Register + AT91_REG Reserved0[1]; // + AT91_REG UDP_IER; // Interrupt Enable Register + AT91_REG UDP_IDR; // Interrupt Disable Register + AT91_REG UDP_IMR; // Interrupt Mask Register + AT91_REG UDP_ISR; // Interrupt Status Register + AT91_REG UDP_ICR; // Interrupt Clear Register + AT91_REG Reserved1[1]; // + AT91_REG UDP_RSTEP; // Reset Endpoint Register + AT91_REG Reserved2[1]; // + AT91_REG UDP_CSR[8]; // Endpoint Control and Status Register + AT91_REG UDP_FDR[8]; // Endpoint FIFO Data Register + AT91_REG Reserved3[1]; // + AT91_REG UDP_TXVC; // Transceiver Control Register +} AT91S_UDP, *AT91PS_UDP; +#else +#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register +#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register +#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register +#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register +#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register +#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register +#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register +#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register +#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register +#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register +#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register +#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register + +#endif +// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- +#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats +#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error +#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK +// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- +#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable +#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured +#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume +#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host +#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable +// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- +#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value +#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable +// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- +#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt +#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt +#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt +#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt +#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt +#define AT91C_UDP_EPINT6 (0x1 << 6) // (UDP) Endpoint 6 Interrupt +#define AT91C_UDP_EPINT7 (0x1 << 7) // (UDP) Endpoint 7 Interrupt +#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt +#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt +#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt +#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt +#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt +// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- +// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- +// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- +#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt +// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- +// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- +#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 +#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 +#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 +#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 +#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4 +#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5 +#define AT91C_UDP_EP6 (0x1 << 6) // (UDP) Reset Endpoint 6 +#define AT91C_UDP_EP7 (0x1 << 7) // (UDP) Reset Endpoint 7 +// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- +#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR +#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 +#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) +#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) +#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints) +#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready +#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). +#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). +#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction +#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type +#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control +#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT +#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT +#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT +#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN +#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN +#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN +#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle +#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable +#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO +// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- +#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) +#define AT91C_UDP_PUON (0x1 << 9) // (UDP) Pull-up ON + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TC { + AT91_REG TC_CCR; // Channel Control Register + AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) + AT91_REG Reserved0[2]; // + AT91_REG TC_CV; // Counter Value + AT91_REG TC_RA; // Register A + AT91_REG TC_RB; // Register B + AT91_REG TC_RC; // Register C + AT91_REG TC_SR; // Status Register + AT91_REG TC_IER; // Interrupt Enable Register + AT91_REG TC_IDR; // Interrupt Disable Register + AT91_REG TC_IMR; // Interrupt Mask Register +} AT91S_TC, *AT91PS_TC; +#else +#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register +#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode) +#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value +#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A +#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B +#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C +#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register +#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register +#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register +#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register + +#endif +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK +#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK +#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 +#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 +#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 +#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal +#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock +#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock +#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock +#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading +#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading +#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection +#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection +#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE (0x1 << 15) // (TC) +#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection +#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None +#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA +#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection +#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None +#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA +#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA +#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA +#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger +#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_TCB { + AT91S_TC TCB_TC0; // TC Channel 0 + AT91_REG Reserved0[4]; // + AT91S_TC TCB_TC1; // TC Channel 1 + AT91_REG Reserved1[4]; // + AT91S_TC TCB_TC2; // TC Channel 2 + AT91_REG Reserved2[4]; // + AT91_REG TCB_BCR; // TC Block Control Register + AT91_REG TCB_BMR; // TC Block Mode Register +} AT91S_TCB, *AT91PS_TCB; +#else +#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register +#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register + +#endif +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Analog to Digital Convertor +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_ADC { + AT91_REG ADC_CR; // ADC Control Register + AT91_REG ADC_MR; // ADC Mode Register + AT91_REG Reserved0[2]; // + AT91_REG ADC_CHER; // ADC Channel Enable Register + AT91_REG ADC_CHDR; // ADC Channel Disable Register + AT91_REG ADC_CHSR; // ADC Channel Status Register + AT91_REG ADC_SR; // ADC Status Register + AT91_REG ADC_LCDR; // ADC Last Converted Data Register + AT91_REG ADC_IER; // ADC Interrupt Enable Register + AT91_REG ADC_IDR; // ADC Interrupt Disable Register + AT91_REG ADC_IMR; // ADC Interrupt Mask Register + AT91_REG ADC_CDR0; // ADC Channel Data Register 0 + AT91_REG ADC_CDR1; // ADC Channel Data Register 1 + AT91_REG ADC_CDR2; // ADC Channel Data Register 2 + AT91_REG ADC_CDR3; // ADC Channel Data Register 3 + AT91_REG ADC_CDR4; // ADC Channel Data Register 4 + AT91_REG ADC_CDR5; // ADC Channel Data Register 5 + AT91_REG ADC_CDR6; // ADC Channel Data Register 6 + AT91_REG ADC_CDR7; // ADC Channel Data Register 7 + AT91_REG Reserved1[44]; // + AT91_REG ADC_RPR; // Receive Pointer Register + AT91_REG ADC_RCR; // Receive Counter Register + AT91_REG ADC_TPR; // Transmit Pointer Register + AT91_REG ADC_TCR; // Transmit Counter Register + AT91_REG ADC_RNPR; // Receive Next Pointer Register + AT91_REG ADC_RNCR; // Receive Next Counter Register + AT91_REG ADC_TNPR; // Transmit Next Pointer Register + AT91_REG ADC_TNCR; // Transmit Next Counter Register + AT91_REG ADC_PTCR; // PDC Transfer Control Register + AT91_REG ADC_PTSR; // PDC Transfer Status Register +} AT91S_ADC, *AT91PS_ADC; +#else +#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register +#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register +#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register +#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register +#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register +#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register +#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register +#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register +#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register +#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register +#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0 +#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1 +#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2 +#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3 +#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4 +#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5 +#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6 +#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7 + +#endif +// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- +#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset +#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion +// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- +#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable +#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software +#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. +#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection +#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 +#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 +#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 +#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 +#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 +#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 +#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger +#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. +#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution +#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution +#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode +#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode +#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection +#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time +#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time +// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- +#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 +#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 +#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 +#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 +#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 +#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 +#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 +#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 +// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- +// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- +// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- +#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion +#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion +#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion +#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion +#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion +#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion +#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion +#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion +#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error +#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error +#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error +#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error +#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error +#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error +#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error +#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error +#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready +#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun +#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer +#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt +// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- +#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted +// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- +// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- +// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- +// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- +#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data +// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- +// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- +// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- +// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- +// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- +// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- +// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR External Bus Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_EBI { + AT91_REG EBI_CSA; // EBI Chip Select Assignment Register +} AT91S_EBI, *AT91PS_EBI; +#else +#define EBI_CSA (AT91_CAST(AT91_REG *) 0x00000000) // (EBI_CSA) EBI Chip Select Assignment Register + +#endif +// -------- EBI_CSA : (EBI Offset: 0x0) Chip Select Assignment Register -------- +#define AT91C_EBI_CS1A (0x1 << 1) // (EBI) Chip Select 1 Assignment +#define AT91C_EBI_CS1A_SMC (0x0 << 1) // (EBI) Chip Select 1 is assigned to the Static Memory Controller. +#define AT91C_EBI_CS1A_SDRAMC (0x1 << 1) // (EBI) Chip Select 1 is assigned to the SDRAM Controller. +#define AT91C_EBI_CS2A (0x1 << 2) // (EBI) Chip Select 2 Assignment +#define AT91C_EBI_CS2A_SMC (0x0 << 2) // (EBI) Chip Select 2 is assigned to the Static Memory Controller and NCS2, NCS5 and NCS6 behave as defined by the SMC. +#define AT91C_EBI_CS2A_SMC_CompactFlash (0x1 << 2) // (EBI) Chip Select 2 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is actived. Accesing the address space reserved to NCS5 and NCS6 may lead to an unpedictable outcome +#define AT91C_EBI_CS3A (0x1 << 3) // (EBI) Chip Select 3 Assignment +#define AT91C_EBI_CS3A_SMC (0x0 << 3) // (EBI) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC2. +#define AT91C_EBI_CS3A_SMC_NandFlash (0x1 << 3) // (EBI) Chip Select 3 is assigned to the Static Memory Controller and the NAND Flash Logic is activated. +#define AT91C_EBI_CS4A (0x1 << 4) // (EBI) Chip Select 4 Assignment +#define AT91C_EBI_CS4A_SMC (0x0 << 4) // (EBI) Chip Select 4 is assigned to the Static Memory Controller and NCS2, NCS5 and NCS6 behave as defined by the SMC. +#define AT91C_EBI_CS4A_SMC_CompactFlash (0x1 << 4) // (EBI) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is actived. Accesing the address space reserved to NCS5 and NCS6 may lead to an unpedictable outcome +#define AT91C_EBI_NWPC (0x1 << 16) // (EBI) NWait Pin Configuration +#define AT91C_EBI_NWPC_OFF (0x0 << 16) // (EBI) The NWAIT device pin is not connected to the External Wait Request input of the Static Memory Controller ,this multiplexe pin can be used as a PIO. +#define AT91C_EBI_NWPC_ON (0x1 << 16) // (EBI) The NWAIT device pin is connected to the External Wait Request input of the Static Memory Controller. + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SMC2 { + AT91_REG SMC2_CSR[8]; // SMC2 Chip Select Register +} AT91S_SMC2, *AT91PS_SMC2; +#else +#define SMC2_CSR (AT91_CAST(AT91_REG *) 0x00000000) // (SMC2_CSR) SMC2 Chip Select Register + +#endif +// -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register -------- +#define AT91C_SMC2_NWS (0x7F << 0) // (SMC2) Number of Wait States +#define AT91C_SMC2_WSEN (0x1 << 7) // (SMC2) Wait State Enable +#define AT91C_SMC2_TDF (0xF << 8) // (SMC2) Data Float Time +#define AT91C_SMC2_BAT (0x1 << 12) // (SMC2) Byte Access Type +#define AT91C_SMC2_DBW (0x1 << 13) // (SMC2) Data Bus Width +#define AT91C_SMC2_DBW_16 (0x1 << 13) // (SMC2) 16-bit. +#define AT91C_SMC2_DBW_8 (0x2 << 13) // (SMC2) 8-bit. +#define AT91C_SMC2_DRP (0x1 << 15) // (SMC2) Data Read Protocol +#define AT91C_SMC2_ACSS (0x3 << 16) // (SMC2) Address to Chip Select Setup +#define AT91C_SMC2_ACSS_STANDARD (0x0 << 16) // (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. +#define AT91C_SMC2_ACSS_1_CYCLE (0x1 << 16) // (SMC2) One cycle less at the beginning and the end of the access. +#define AT91C_SMC2_ACSS_2_CYCLES (0x2 << 16) // (SMC2) Two cycles less at the beginning and the end of the access. +#define AT91C_SMC2_ACSS_3_CYCLES (0x3 << 16) // (SMC2) Three cycles less at the beginning and the end of the access. +#define AT91C_SMC2_RWSETUP (0x7 << 24) // (SMC2) Read and Write Signal Setup Time +#define AT91C_SMC2_RWHOLD (0x7 << 28) // (SMC2) Read and Write Signal Hold Time + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR SDRAM Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_SDRC { + AT91_REG SDRC_MR; // SDRAM Controller Mode Register + AT91_REG SDRC_TR; // SDRAM Controller Refresh Timer Register + AT91_REG SDRC_CR; // SDRAM Controller Configuration Register + AT91_REG SDRC_SRR; // SDRAM Controller Self Refresh Register + AT91_REG SDRC_LPR; // SDRAM Controller Low Power Register + AT91_REG SDRC_IER; // SDRAM Controller Interrupt Enable Register + AT91_REG SDRC_IDR; // SDRAM Controller Interrupt Disable Register + AT91_REG SDRC_IMR; // SDRAM Controller Interrupt Mask Register + AT91_REG SDRC_ISR; // SDRAM Controller Interrupt Mask Register + AT91_REG SDRC_VER; // SDRAM Controller Version Register +} AT91S_SDRC, *AT91PS_SDRC; +#else +#define SDRC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (SDRC_MR) SDRAM Controller Mode Register +#define SDRC_TR (AT91_CAST(AT91_REG *) 0x00000004) // (SDRC_TR) SDRAM Controller Refresh Timer Register +#define SDRC_CR (AT91_CAST(AT91_REG *) 0x00000008) // (SDRC_CR) SDRAM Controller Configuration Register +#define SDRC_SRR (AT91_CAST(AT91_REG *) 0x0000000C) // (SDRC_SRR) SDRAM Controller Self Refresh Register +#define SDRC_LPR (AT91_CAST(AT91_REG *) 0x00000010) // (SDRC_LPR) SDRAM Controller Low Power Register +#define SDRC_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SDRC_IER) SDRAM Controller Interrupt Enable Register +#define SDRC_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SDRC_IDR) SDRAM Controller Interrupt Disable Register +#define SDRC_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SDRC_IMR) SDRAM Controller Interrupt Mask Register +#define SDRC_ISR (AT91_CAST(AT91_REG *) 0x00000020) // (SDRC_ISR) SDRAM Controller Interrupt Mask Register +#define IPB_VER (AT91_CAST(AT91_REG *) 0x00000024) // (IPB_VER) SDRAM Controller Version Register + +#endif +// -------- SDRC_MR : (SDRC Offset: 0x0) SDRAM Controller Mode Register -------- +#define AT91C_SDRC_MODE (0xF << 0) // (SDRC) Mode +#define AT91C_SDRC_MODE_NORMAL_CMD (0x0) // (SDRC) Normal Mode +#define AT91C_SDRC_MODE_NOP_CMD (0x1) // (SDRC) NOP Command +#define AT91C_SDRC_MODE_PRCGALL_CMD (0x2) // (SDRC) All Banks Precharge Command +#define AT91C_SDRC_MODE_LMR_CMD (0x3) // (SDRC) Load Mode Register Command +#define AT91C_SDRC_MODE_RFSH_CMD (0x4) // (SDRC) Refresh Command +#define AT91C_SDRC_DBW (0x1 << 4) // (SDRC) Data Bus Width +#define AT91C_SDRC_DBW_32_BITS (0x0 << 4) // (SDRC) 32 Bits datas bus +#define AT91C_SDRC_DBW_16_BITS (0x1 << 4) // (SDRC) 16 Bits datas bus +// -------- SDRC_TR : (SDRC Offset: 0x4) SDRC Refresh Timer Register -------- +#define AT91C_SDRC_COUNT (0xFFF << 0) // (SDRC) Refresh Counter +// -------- SDRC_CR : (SDRC Offset: 0x8) SDRAM Configuration Register -------- +#define AT91C_SDRC_NC (0x3 << 0) // (SDRC) Number of Column Bits +#define AT91C_SDRC_NC_8 (0x0) // (SDRC) 8 Bits +#define AT91C_SDRC_NC_9 (0x1) // (SDRC) 9 Bits +#define AT91C_SDRC_NC_10 (0x2) // (SDRC) 10 Bits +#define AT91C_SDRC_NC_11 (0x3) // (SDRC) 11 Bits +#define AT91C_SDRC_NR (0x3 << 2) // (SDRC) Number of Row Bits +#define AT91C_SDRC_NR_11 (0x0 << 2) // (SDRC) 11 Bits +#define AT91C_SDRC_NR_12 (0x1 << 2) // (SDRC) 12 Bits +#define AT91C_SDRC_NR_13 (0x2 << 2) // (SDRC) 13 Bits +#define AT91C_SDRC_NB (0x1 << 4) // (SDRC) Number of Banks +#define AT91C_SDRC_NB_2_BANKS (0x0 << 4) // (SDRC) 2 banks +#define AT91C_SDRC_NB_4_BANKS (0x1 << 4) // (SDRC) 4 banks +#define AT91C_SDRC_CAS (0x3 << 5) // (SDRC) CAS Latency +#define AT91C_SDRC_CAS_2 (0x2 << 5) // (SDRC) 2 cycles +#define AT91C_SDRC_TWR (0xF << 7) // (SDRC) Number of Write Recovery Time Cycles +#define AT91C_SDRC_TRC (0xF << 11) // (SDRC) Number of RAS Cycle Time Cycles +#define AT91C_SDRC_TRP (0xF << 15) // (SDRC) Number of RAS Precharge Time Cycles +#define AT91C_SDRC_TRCD (0xF << 19) // (SDRC) Number of RAS to CAS Delay Cycles +#define AT91C_SDRC_TRAS (0xF << 23) // (SDRC) Number of RAS Active Time Cycles +#define AT91C_SDRC_TXSR (0xF << 27) // (SDRC) Number of Command Recovery Time Cycles +// -------- SDRC_SRR : (SDRC Offset: 0xc) SDRAM Controller Self-refresh Register -------- +#define AT91C_SDRC_SRCB (0x1 << 0) // (SDRC) Self-refresh Command Bit +// -------- SDRC_LPR : (SDRC Offset: 0x10) SDRAM Controller Low-power Register -------- +#define AT91C_SDRC_LPCB (0x1 << 0) // (SDRC) Low-power Command Bit +// -------- SDRC_IER : (SDRC Offset: 0x14) SDRAM Controller Interrupt Enable Register -------- +#define AT91C_SDRC_RES (0x1 << 0) // (SDRC) Refresh Error Status +// -------- SDRC_IDR : (SDRC Offset: 0x18) SDRAM Controller Interrupt Disable Register -------- +// -------- SDRC_IMR : (SDRC Offset: 0x1c) SDRAM Controller Interrupt Mask Register -------- +// -------- SDRC_ISR : (SDRC Offset: 0x20) SDRAM Controller Interrupt Status Register -------- +// -------- IPB_VER : (SDRC Offset: 0x24) SDRAM Controller IP version Register -------- +#define AT91C_SDRC_VERSION (0xFFF << 0) // (SDRC) IP version of the macrocell +#define AT91C_SDRC_MFN (0x7 << 1) // (SDRC) + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Error Correction Code controller +// ***************************************************************************** +#ifndef __ASSEMBLY__ +typedef struct _AT91S_ECC { + AT91_REG ECC_CR; // ECC reset register + AT91_REG ECC_MR; // ECC Page size register + AT91_REG ECC_SR; // ECC Status register + AT91_REG ECC_PR; // ECC Parity register + AT91_REG ECC_NPR; // ECC Parity N register + AT91_REG ECC_VR; // ECC Version register +} AT91S_ECC, *AT91PS_ECC; +#else +#define ECC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ECC_CR) ECC reset register +#define ECC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ECC_MR) ECC Page size register +#define ECC_SR (AT91_CAST(AT91_REG *) 0x00000008) // (ECC_SR) ECC Status register +#define ECC_PR (AT91_CAST(AT91_REG *) 0x0000000C) // (ECC_PR) ECC Parity register +#define ECC_NPR (AT91_CAST(AT91_REG *) 0x00000010) // (ECC_NPR) ECC Parity N register +#define ECC_VR (AT91_CAST(AT91_REG *) 0x00000014) // (ECC_VR) ECC Version register + +#endif +// -------- ECC_CR : (ECC Offset: 0x0) ECC reset register -------- +#define AT91C_ECC_RST (0x1 << 0) // (ECC) ECC reset parity +// -------- ECC_MR : (ECC Offset: 0x4) ECC page size register -------- +#define AT91C_ECC_PAGE_SIZE (0x3 << 0) // (ECC) Nand Flash page size +// -------- ECC_SR : (ECC Offset: 0x8) ECC status register -------- +#define AT91C_ECC_RECERR (0x1 << 0) // (ECC) ECC error +#define AT91C_ECC_ECCERR (0x1 << 1) // (ECC) ECC single error +#define AT91C_ECC_MULERR (0x1 << 2) // (ECC) ECC_MULERR +// -------- ECC_PR : (ECC Offset: 0xc) ECC parity register -------- +#define AT91C_ECC_BITADDR (0xF << 0) // (ECC) Bit address error +#define AT91C_ECC_WORDADDR (0xFFF << 4) // (ECC) address of the failing bit +// -------- ECC_NPR : (ECC Offset: 0x10) ECC N parity register -------- +#define AT91C_ECC_NPARITY (0xFFFF << 0) // (ECC) ECC parity N +// -------- ECC_VR : (ECC Offset: 0x14) ECC version register -------- +#define AT91C_ECC_VERSION (0xFFF << 0) // (ECC) ECC version number +#define AT91C_ECC_MFN (0x7 << 16) // (ECC) ECC MFN + +// ***************************************************************************** +// REGISTER ADDRESS DEFINITION FOR AT91SAM7SE512 +// ***************************************************************************** +// ========== Register definition for SYS peripheral ========== +// ========== Register definition for AIC peripheral ========== +#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register +#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register +#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register +#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) +#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register +#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register +#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register +#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register +#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register +#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register +#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register +#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register +#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register +#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register +#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register +#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register +#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register +#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register +// ========== Register definition for PDC_DBGU peripheral ========== +#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register +#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register +#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register +#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register +#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register +#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register +#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register +#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register +#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register +#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register +// ========== Register definition for DBGU peripheral ========== +#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register +#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register +#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register +#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register +#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register +#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register +#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register +#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register +#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register +#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register +#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register +#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register +// ========== Register definition for PIOA peripheral ========== +#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register +#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register +#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register +#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register +#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register +#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register +#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register +#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register +#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register +#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register +#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register +// ========== Register definition for PIOB peripheral ========== +#define AT91C_PIOB_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register +#define AT91C_PIOB_MDER (AT91_CAST(AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register +#define AT91C_PIOB_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register +#define AT91C_PIOB_IMR (AT91_CAST(AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register +#define AT91C_PIOB_ASR (AT91_CAST(AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register +#define AT91C_PIOB_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register +#define AT91C_PIOB_PSR (AT91_CAST(AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register +#define AT91C_PIOB_IER (AT91_CAST(AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register +#define AT91C_PIOB_CODR (AT91_CAST(AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register +#define AT91C_PIOB_OWER (AT91_CAST(AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register +#define AT91C_PIOB_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register +#define AT91C_PIOB_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register +#define AT91C_PIOB_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register +#define AT91C_PIOB_IDR (AT91_CAST(AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register +#define AT91C_PIOB_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register +#define AT91C_PIOB_PDR (AT91_CAST(AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register +#define AT91C_PIOB_ODR (AT91_CAST(AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr +#define AT91C_PIOB_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register +#define AT91C_PIOB_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register +#define AT91C_PIOB_SODR (AT91_CAST(AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register +#define AT91C_PIOB_ISR (AT91_CAST(AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register +#define AT91C_PIOB_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register +#define AT91C_PIOB_OSR (AT91_CAST(AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register +#define AT91C_PIOB_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register +#define AT91C_PIOB_IFER (AT91_CAST(AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register +#define AT91C_PIOB_BSR (AT91_CAST(AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register +#define AT91C_PIOB_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register +#define AT91C_PIOB_OER (AT91_CAST(AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register +#define AT91C_PIOB_PER (AT91_CAST(AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register +// ========== Register definition for PIOC peripheral ========== +#define AT91C_PIOC_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF8A4) // (PIOC) Output Write Disable Register +#define AT91C_PIOC_SODR (AT91_CAST(AT91_REG *) 0xFFFFF830) // (PIOC) Set Output Data Register +#define AT91C_PIOC_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF864) // (PIOC) Pull-up Enable Register +#define AT91C_PIOC_CODR (AT91_CAST(AT91_REG *) 0xFFFFF834) // (PIOC) Clear Output Data Register +#define AT91C_PIOC_PSR (AT91_CAST(AT91_REG *) 0xFFFFF808) // (PIOC) PIO Status Register +#define AT91C_PIOC_PDR (AT91_CAST(AT91_REG *) 0xFFFFF804) // (PIOC) PIO Disable Register +#define AT91C_PIOC_ODR (AT91_CAST(AT91_REG *) 0xFFFFF814) // (PIOC) Output Disable Registerr +#define AT91C_PIOC_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF868) // (PIOC) Pull-up Status Register +#define AT91C_PIOC_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF878) // (PIOC) AB Select Status Register +#define AT91C_PIOC_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF828) // (PIOC) Input Filter Status Register +#define AT91C_PIOC_OER (AT91_CAST(AT91_REG *) 0xFFFFF810) // (PIOC) Output Enable Register +#define AT91C_PIOC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF848) // (PIOC) Interrupt Mask Register +#define AT91C_PIOC_ASR (AT91_CAST(AT91_REG *) 0xFFFFF870) // (PIOC) Select A Register +#define AT91C_PIOC_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF854) // (PIOC) Multi-driver Disable Register +#define AT91C_PIOC_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF8A8) // (PIOC) Output Write Status Register +#define AT91C_PIOC_PER (AT91_CAST(AT91_REG *) 0xFFFFF800) // (PIOC) PIO Enable Register +#define AT91C_PIOC_IDR (AT91_CAST(AT91_REG *) 0xFFFFF844) // (PIOC) Interrupt Disable Register +#define AT91C_PIOC_MDER (AT91_CAST(AT91_REG *) 0xFFFFF850) // (PIOC) Multi-driver Enable Register +#define AT91C_PIOC_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF83C) // (PIOC) Pin Data Status Register +#define AT91C_PIOC_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF858) // (PIOC) Multi-driver Status Register +#define AT91C_PIOC_OWER (AT91_CAST(AT91_REG *) 0xFFFFF8A0) // (PIOC) Output Write Enable Register +#define AT91C_PIOC_BSR (AT91_CAST(AT91_REG *) 0xFFFFF874) // (PIOC) Select B Register +#define AT91C_PIOC_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF860) // (PIOC) Pull-up Disable Register +#define AT91C_PIOC_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF824) // (PIOC) Input Filter Disable Register +#define AT91C_PIOC_IER (AT91_CAST(AT91_REG *) 0xFFFFF840) // (PIOC) Interrupt Enable Register +#define AT91C_PIOC_OSR (AT91_CAST(AT91_REG *) 0xFFFFF818) // (PIOC) Output Status Register +#define AT91C_PIOC_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF838) // (PIOC) Output Data Status Register +#define AT91C_PIOC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF84C) // (PIOC) Interrupt Status Register +#define AT91C_PIOC_IFER (AT91_CAST(AT91_REG *) 0xFFFFF820) // (PIOC) Input Filter Enable Register +// ========== Register definition for CKGR peripheral ========== +#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register +#define AT91C_CKGR_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register +#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register +// ========== Register definition for PMC peripheral ========== +#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register +#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register +#define AT91C_PMC_PLLR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register +#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register +#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register +#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register +#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register +#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register +#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register +#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register +#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register +#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register +#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register +#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register +#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register +// ========== Register definition for RSTC peripheral ========== +#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register +#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register +#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register +// ========== Register definition for RTTC peripheral ========== +#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register +#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register +#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register +#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register +// ========== Register definition for PITC peripheral ========== +#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register +#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register +#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register +#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register +// ========== Register definition for WDTC peripheral ========== +#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register +#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register +#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register +// ========== Register definition for VREG peripheral ========== +#define AT91C_VREG_MR (AT91_CAST(AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register +// ========== Register definition for MC peripheral ========== +#define AT91C_MC_ASR (AT91_CAST(AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register +#define AT91C_MC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register +#define AT91C_MC_PUP (AT91_CAST(AT91_REG *) 0xFFFFFF50) // (MC) MC Protection Unit Peripherals +#define AT91C_MC_PUIA (AT91_CAST(AT91_REG *) 0xFFFFFF10) // (MC) MC Protection Unit Area +#define AT91C_MC_AASR (AT91_CAST(AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register +#define AT91C_MC_PUER (AT91_CAST(AT91_REG *) 0xFFFFFF54) // (MC) MC Protection Unit Enable Register +// ========== Register definition for EFC0 peripheral ========== +#define AT91C_EFC0_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF64) // (EFC0) MC Flash Command Register +#define AT91C_EFC0_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF68) // (EFC0) MC Flash Status Register +#define AT91C_EFC0_VR (AT91_CAST(AT91_REG *) 0xFFFFFF6C) // (EFC0) MC Flash Version Register +#define AT91C_EFC0_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF60) // (EFC0) MC Flash Mode Register +// ========== Register definition for EFC1 peripheral ========== +#define AT91C_EFC1_VR (AT91_CAST(AT91_REG *) 0xFFFFFF7C) // (EFC1) MC Flash Version Register +#define AT91C_EFC1_FCR (AT91_CAST(AT91_REG *) 0xFFFFFF74) // (EFC1) MC Flash Command Register +#define AT91C_EFC1_FSR (AT91_CAST(AT91_REG *) 0xFFFFFF78) // (EFC1) MC Flash Status Register +#define AT91C_EFC1_FMR (AT91_CAST(AT91_REG *) 0xFFFFFF70) // (EFC1) MC Flash Mode Register +// ========== Register definition for PDC_SPI peripheral ========== +#define AT91C_SPI_PTCR (AT91_CAST(AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register +#define AT91C_SPI_TPR (AT91_CAST(AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register +#define AT91C_SPI_TCR (AT91_CAST(AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register +#define AT91C_SPI_RCR (AT91_CAST(AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register +#define AT91C_SPI_PTSR (AT91_CAST(AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register +#define AT91C_SPI_RNPR (AT91_CAST(AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register +#define AT91C_SPI_RPR (AT91_CAST(AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register +#define AT91C_SPI_TNCR (AT91_CAST(AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register +#define AT91C_SPI_RNCR (AT91_CAST(AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register +#define AT91C_SPI_TNPR (AT91_CAST(AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register +// ========== Register definition for SPI peripheral ========== +#define AT91C_SPI_IER (AT91_CAST(AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register +#define AT91C_SPI_SR (AT91_CAST(AT91_REG *) 0xFFFE0010) // (SPI) Status Register +#define AT91C_SPI_IDR (AT91_CAST(AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register +#define AT91C_SPI_CR (AT91_CAST(AT91_REG *) 0xFFFE0000) // (SPI) Control Register +#define AT91C_SPI_MR (AT91_CAST(AT91_REG *) 0xFFFE0004) // (SPI) Mode Register +#define AT91C_SPI_IMR (AT91_CAST(AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register +#define AT91C_SPI_TDR (AT91_CAST(AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register +#define AT91C_SPI_RDR (AT91_CAST(AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register +#define AT91C_SPI_CSR (AT91_CAST(AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register +// ========== Register definition for PDC_US1 peripheral ========== +#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register +#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register +#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register +#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register +#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register +#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register +#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register +#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register +#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register +#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register +// ========== Register definition for US1 peripheral ========== +#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register +#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register +#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register +#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register +#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register +#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register +#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register +#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register +#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register +#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register +#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register +#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register +#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (US1) Control Register +#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (US1) Mode Register +// ========== Register definition for PDC_US0 peripheral ========== +#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register +#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register +#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register +#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register +#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register +#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register +#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register +#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register +#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register +#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register +// ========== Register definition for US0 peripheral ========== +#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register +#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register +#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFC0000) // (US0) Control Register +#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register +#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register +#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register +#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFC0004) // (US0) Mode Register +#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register +#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register +#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register +#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register +#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register +#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register +#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register +// ========== Register definition for PDC_SSC peripheral ========== +#define AT91C_SSC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register +#define AT91C_SSC_RPR (AT91_CAST(AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register +#define AT91C_SSC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register +#define AT91C_SSC_TPR (AT91_CAST(AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register +#define AT91C_SSC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register +#define AT91C_SSC_TCR (AT91_CAST(AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register +#define AT91C_SSC_RCR (AT91_CAST(AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register +#define AT91C_SSC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register +#define AT91C_SSC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register +#define AT91C_SSC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register +// ========== Register definition for SSC peripheral ========== +#define AT91C_SSC_RHR (AT91_CAST(AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register +#define AT91C_SSC_RSHR (AT91_CAST(AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register +#define AT91C_SSC_TFMR (AT91_CAST(AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register +#define AT91C_SSC_IDR (AT91_CAST(AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register +#define AT91C_SSC_THR (AT91_CAST(AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register +#define AT91C_SSC_RCMR (AT91_CAST(AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister +#define AT91C_SSC_IER (AT91_CAST(AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register +#define AT91C_SSC_TSHR (AT91_CAST(AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register +#define AT91C_SSC_SR (AT91_CAST(AT91_REG *) 0xFFFD4040) // (SSC) Status Register +#define AT91C_SSC_CMR (AT91_CAST(AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register +#define AT91C_SSC_TCMR (AT91_CAST(AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register +#define AT91C_SSC_CR (AT91_CAST(AT91_REG *) 0xFFFD4000) // (SSC) Control Register +#define AT91C_SSC_IMR (AT91_CAST(AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register +#define AT91C_SSC_RFMR (AT91_CAST(AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register +// ========== Register definition for TWI peripheral ========== +#define AT91C_TWI_IER (AT91_CAST(AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register +#define AT91C_TWI_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (TWI) Control Register +#define AT91C_TWI_SR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (TWI) Status Register +#define AT91C_TWI_IMR (AT91_CAST(AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register +#define AT91C_TWI_THR (AT91_CAST(AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register +#define AT91C_TWI_IDR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register +#define AT91C_TWI_IADR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register +#define AT91C_TWI_MMR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register +#define AT91C_TWI_CWGR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register +#define AT91C_TWI_RHR (AT91_CAST(AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register +#define AT91C_TWI_SMR (AT91_CAST(AT91_REG *) 0xFFFB8008) // (TWI) Slave Mode Register +// ========== Register definition for PWMC_CH3 peripheral ========== +#define AT91C_CH3_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register +#define AT91C_CH3_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved +#define AT91C_CH3_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register +#define AT91C_CH3_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register +#define AT91C_CH3_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register +#define AT91C_CH3_CMR (AT91_CAST(AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register +// ========== Register definition for PWMC_CH2 peripheral ========== +#define AT91C_CH2_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved +#define AT91C_CH2_CMR (AT91_CAST(AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register +#define AT91C_CH2_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register +#define AT91C_CH2_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register +#define AT91C_CH2_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register +#define AT91C_CH2_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register +// ========== Register definition for PWMC_CH1 peripheral ========== +#define AT91C_CH1_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved +#define AT91C_CH1_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register +#define AT91C_CH1_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register +#define AT91C_CH1_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register +#define AT91C_CH1_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register +#define AT91C_CH1_CMR (AT91_CAST(AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register +// ========== Register definition for PWMC_CH0 peripheral ========== +#define AT91C_CH0_Reserved (AT91_CAST(AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved +#define AT91C_CH0_CPRDR (AT91_CAST(AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register +#define AT91C_CH0_CDTYR (AT91_CAST(AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register +#define AT91C_CH0_CMR (AT91_CAST(AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register +#define AT91C_CH0_CUPDR (AT91_CAST(AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register +#define AT91C_CH0_CCNTR (AT91_CAST(AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register +// ========== Register definition for PWMC peripheral ========== +#define AT91C_PWMC_IDR (AT91_CAST(AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register +#define AT91C_PWMC_DIS (AT91_CAST(AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register +#define AT91C_PWMC_IER (AT91_CAST(AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register +#define AT91C_PWMC_VR (AT91_CAST(AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register +#define AT91C_PWMC_ISR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register +#define AT91C_PWMC_SR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register +#define AT91C_PWMC_IMR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register +#define AT91C_PWMC_MR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register +#define AT91C_PWMC_ENA (AT91_CAST(AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register +// ========== Register definition for UDP peripheral ========== +#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register +#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register +#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register +#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register +#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register +#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register +#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register +#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register +#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register +#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register +#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFB0004) // (UDP) Global State Register +#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register +// ========== Register definition for TC0 peripheral ========== +#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register +#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C +#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B +#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register +#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register +#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A +#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register +#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value +#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register +// ========== Register definition for TC1 peripheral ========== +#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B +#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register +#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register +#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register +#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register +#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A +#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C +#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register +#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value +// ========== Register definition for TC2 peripheral ========== +#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) +#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register +#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value +#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A +#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B +#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register +#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register +#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C +#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register +#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register +// ========== Register definition for TCB peripheral ========== +#define AT91C_TCB_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register +#define AT91C_TCB_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register +// ========== Register definition for PDC_ADC peripheral ========== +#define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register +#define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register +#define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register +#define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register +#define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register +#define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register +#define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register +#define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register +#define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register +#define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register +// ========== Register definition for ADC peripheral ========== +#define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 +#define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 +#define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 +#define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 +#define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register +#define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register +#define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 +#define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 +#define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register +#define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register +#define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register +#define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 +#define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 +#define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register +#define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register +#define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register +#define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register +#define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register +// ========== Register definition for EBI peripheral ========== +#define AT91C_EBI_CSA (AT91_CAST(AT91_REG *) 0xFFFFFF80) // (EBI) EBI Chip Select Assignment Register +// ========== Register definition for SMC peripheral ========== +#define AT91C_SMC_CSR (AT91_CAST(AT91_REG *) 0xFFFFFF90) // (SMC) SMC2 Chip Select Register +// ========== Register definition for SDRC peripheral ========== +#define AT91C_SDRC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFFC8) // (SDRC) SDRAM Controller Interrupt Disable Register +#define AT91C_SDRC_TR (AT91_CAST(AT91_REG *) 0xFFFFFFB4) // (SDRC) SDRAM Controller Refresh Timer Register +#define AT91C_SDRC_SRR (AT91_CAST(AT91_REG *) 0xFFFFFFBC) // (SDRC) SDRAM Controller Self Refresh Register +#define AT91C_SDRC_MR (AT91_CAST(AT91_REG *) 0xFFFFFFB0) // (SDRC) SDRAM Controller Mode Register +#define AT91C_SDRC_CR (AT91_CAST(AT91_REG *) 0xFFFFFFB8) // (SDRC) SDRAM Controller Configuration Register +#define AT91C_SDRC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFFCC) // (SDRC) SDRAM Controller Interrupt Mask Register +#define AT91C_SDRC_LPR (AT91_CAST(AT91_REG *) 0xFFFFFFC0) // (SDRC) SDRAM Controller Low Power Register +#define AT91C_SDRC_ISR (AT91_CAST(AT91_REG *) 0xFFFFFFD0) // (SDRC) SDRAM Controller Interrupt Mask Register +#define AT91C_SDRC_VER (AT91_CAST(AT91_REG *) 0xFFFFFFD4) // (SDRC) SDRAM Controller Version Register +#define AT91C_SDRC_IER (AT91_CAST(AT91_REG *) 0xFFFFFFC4) // (SDRC) SDRAM Controller Interrupt Enable Register +// ========== Register definition for HECC peripheral ========== +#define AT91C_HECC_MR (AT91_CAST(AT91_REG *) 0xFFFFFFE0) // (HECC) ECC Page size register +#define AT91C_HECC_CR (AT91_CAST(AT91_REG *) 0xFFFFFFDC) // (HECC) ECC reset register +#define AT91C_HECC_SR (AT91_CAST(AT91_REG *) 0xFFFFFFE4) // (HECC) ECC Status register +#define AT91C_HECC_VR (AT91_CAST(AT91_REG *) 0xFFFFFFF0) // (HECC) ECC Version register +#define AT91C_HECC_NPR (AT91_CAST(AT91_REG *) 0xFFFFFFEC) // (HECC) ECC Parity N register +#define AT91C_HECC_PR (AT91_CAST(AT91_REG *) 0xFFFFFFE8) // (HECC) ECC Parity register + +// ***************************************************************************** +// PIO DEFINITIONS FOR AT91SAM7SE512 +// ***************************************************************************** +#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 +#define AT91C_PA0_PWM0 (AT91C_PIO_PA0) // +#define AT91C_PA0_A0_NBS0 (AT91C_PIO_PA0) // +#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 +#define AT91C_PA1_PWM1 (AT91C_PIO_PA1) // +#define AT91C_PA1_A1_NBS2 (AT91C_PIO_PA1) // +#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 +#define AT91C_PA10_DTXD (AT91C_PIO_PA10) // +#define AT91C_PA10_A10 (AT91C_PIO_PA10) // +#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 +#define AT91C_PA11_NPCS0 (AT91C_PIO_PA11) // +#define AT91C_PA11_A11 (AT91C_PIO_PA11) // +#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 +#define AT91C_PA12_MISO (AT91C_PIO_PA12) // +#define AT91C_PA12_A12 (AT91C_PIO_PA12) // +#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 +#define AT91C_PA13_MOSI (AT91C_PIO_PA13) // +#define AT91C_PA13_A13 (AT91C_PIO_PA13) // +#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 +#define AT91C_PA14_SPCK (AT91C_PIO_PA14) // +#define AT91C_PA14_A14 (AT91C_PIO_PA14) // +#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 +#define AT91C_PA15_TF (AT91C_PIO_PA15) // +#define AT91C_PA15_A15 (AT91C_PIO_PA15) // +#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 +#define AT91C_PA16_TK (AT91C_PIO_PA16) // +#define AT91C_PA16_A16_BA0 (AT91C_PIO_PA16) // +#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 +#define AT91C_PA17_TD (AT91C_PIO_PA17) // +#define AT91C_PA17_A17_BA1 (AT91C_PIO_PA17) // +#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 +#define AT91C_PA18_RD (AT91C_PIO_PA18) // +#define AT91C_PA18_NBS3_CFIOW (AT91C_PIO_PA18) // +#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 +#define AT91C_PA19_RK (AT91C_PIO_PA19) // +#define AT91C_PA19_NCS4_CFCS0 (AT91C_PIO_PA19) // +#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 +#define AT91C_PA2_PWM2 (AT91C_PIO_PA2) // +#define AT91C_PA2_A2 (AT91C_PIO_PA2) // +#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 +#define AT91C_PA20_RF (AT91C_PIO_PA20) // +#define AT91C_PA20_NCS2_CFCS1 (AT91C_PIO_PA20) // +#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 +#define AT91C_PA21_RXD1 (AT91C_PIO_PA21) // +#define AT91C_PA21_NCS6_CFCE2 (AT91C_PIO_PA21) // +#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 +#define AT91C_PA22_TXD1 (AT91C_PIO_PA22) // +#define AT91C_PA22_NCS5_CFCE1 (AT91C_PIO_PA22) // +#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 +#define AT91C_PA23_SCK1 (AT91C_PIO_PA23) // +#define AT91C_PA23_NWR1_NBS1_CFIOR_NUB (AT91C_PIO_PA23) // +#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 +#define AT91C_PA24_RTS1 (AT91C_PIO_PA24) // +#define AT91C_PA24_SDA10 (AT91C_PIO_PA24) // +#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 +#define AT91C_PA25_CTS1 (AT91C_PIO_PA25) // +#define AT91C_PA25_SDCKE (AT91C_PIO_PA25) // +#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 +#define AT91C_PA26_DCD1 (AT91C_PIO_PA26) // +#define AT91C_PA26_NCS1_SDCS (AT91C_PIO_PA26) // +#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 +#define AT91C_PA27_DTR1 (AT91C_PIO_PA27) // +#define AT91C_PA27_SDWE (AT91C_PIO_PA27) // +#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 +#define AT91C_PA28_DSR1 (AT91C_PIO_PA28) // +#define AT91C_PA28_CAS (AT91C_PIO_PA28) // +#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 +#define AT91C_PA29_RI1 (AT91C_PIO_PA29) // +#define AT91C_PA29_RAS (AT91C_PIO_PA29) // +#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 +#define AT91C_PA3_TWD (AT91C_PIO_PA3) // +#define AT91C_PA3_A3 (AT91C_PIO_PA3) // +#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 +#define AT91C_PA30_IRQ1 (AT91C_PIO_PA30) // +#define AT91C_PA30_D30 (AT91C_PIO_PA30) // +#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31 +#define AT91C_PA31_NPCS1 (AT91C_PIO_PA31) // +#define AT91C_PA31_D31 (AT91C_PIO_PA31) // +#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 +#define AT91C_PA4_TWCK (AT91C_PIO_PA4) // +#define AT91C_PA4_A4 (AT91C_PIO_PA4) // +#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 +#define AT91C_PA5_RXD0 (AT91C_PIO_PA5) // +#define AT91C_PA5_A5 (AT91C_PIO_PA5) // +#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 +#define AT91C_PA6_TXD0 (AT91C_PIO_PA6) // +#define AT91C_PA6_A6 (AT91C_PIO_PA6) // +#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 +#define AT91C_PA7_RTS0 (AT91C_PIO_PA7) // +#define AT91C_PA7_A7 (AT91C_PIO_PA7) // +#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 +#define AT91C_PA8_CTS0 (AT91C_PIO_PA8) // +#define AT91C_PA8_A8 (AT91C_PIO_PA8) // +#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 +#define AT91C_PA9_DRXD (AT91C_PIO_PA9) // +#define AT91C_PA9_A9 (AT91C_PIO_PA9) // +#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0 +#define AT91C_PB0_TIOA0 (AT91C_PIO_PB0) // +#define AT91C_PB0_A0_NBS0 (AT91C_PIO_PB0) // +#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1 +#define AT91C_PB1_TIOB0 (AT91C_PIO_PB1) // +#define AT91C_PB1_A1_NBS2 (AT91C_PIO_PB1) // +#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10 +#define AT91C_PB10_NPCS2 (AT91C_PIO_PB10) // +#define AT91C_PB10_A10 (AT91C_PIO_PB10) // +#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11 +#define AT91C_PB11_PWM0 (AT91C_PIO_PB11) // +#define AT91C_PB11_A11 (AT91C_PIO_PB11) // +#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12 +#define AT91C_PB12_PWM1 (AT91C_PIO_PB12) // +#define AT91C_PB12_A12 (AT91C_PIO_PB12) // +#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13 +#define AT91C_PB13_PWM2 (AT91C_PIO_PB13) // +#define AT91C_PB13_A13 (AT91C_PIO_PB13) // +#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14 +#define AT91C_PB14_PWM3 (AT91C_PIO_PB14) // +#define AT91C_PB14_A14 (AT91C_PIO_PB14) // +#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15 +#define AT91C_PB15_TIOA1 (AT91C_PIO_PB15) // +#define AT91C_PB15_A15 (AT91C_PIO_PB15) // +#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16 +#define AT91C_PB16_TIOB1 (AT91C_PIO_PB16) // +#define AT91C_PB16_A16_BA0 (AT91C_PIO_PB16) // +#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17 +#define AT91C_PB17_PCK1 (AT91C_PIO_PB17) // +#define AT91C_PB17_A17_BA1 (AT91C_PIO_PB17) // +#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18 +#define AT91C_PB18_PCK2 (AT91C_PIO_PB18) // +#define AT91C_PB18_D16 (AT91C_PIO_PB18) // +#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19 +#define AT91C_PB19_FIQ (AT91C_PIO_PB19) // +#define AT91C_PB19_D17 (AT91C_PIO_PB19) // +#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2 +#define AT91C_PB2_SCK0 (AT91C_PIO_PB2) // +#define AT91C_PB2_A2 (AT91C_PIO_PB2) // +#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20 +#define AT91C_PB20_IRQ0 (AT91C_PIO_PB20) // +#define AT91C_PB20_D18 (AT91C_PIO_PB20) // +#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21 +#define AT91C_PB21_PCK1 (AT91C_PIO_PB21) // +#define AT91C_PB21_D19 (AT91C_PIO_PB21) // +#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22 +#define AT91C_PB22_NPCS3 (AT91C_PIO_PB22) // +#define AT91C_PB22_D20 (AT91C_PIO_PB22) // +#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23 +#define AT91C_PB23_PWM0 (AT91C_PIO_PB23) // +#define AT91C_PB23_D21 (AT91C_PIO_PB23) // +#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24 +#define AT91C_PB24_PWM1 (AT91C_PIO_PB24) // +#define AT91C_PB24_D22 (AT91C_PIO_PB24) // +#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25 +#define AT91C_PB25_PWM2 (AT91C_PIO_PB25) // +#define AT91C_PB25_D23 (AT91C_PIO_PB25) // +#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26 +#define AT91C_PB26_TIOA2 (AT91C_PIO_PB26) // +#define AT91C_PB26_D24 (AT91C_PIO_PB26) // +#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27 +#define AT91C_PB27_TIOB2 (AT91C_PIO_PB27) // +#define AT91C_PB27_D25 (AT91C_PIO_PB27) // +#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28 +#define AT91C_PB28_TCLK1 (AT91C_PIO_PB28) // +#define AT91C_PB28_D26 (AT91C_PIO_PB28) // +#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29 +#define AT91C_PB29_TCLK2 (AT91C_PIO_PB29) // +#define AT91C_PB29_D27 (AT91C_PIO_PB29) // +#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3 +#define AT91C_PB3_NPCS3 (AT91C_PIO_PB3) // +#define AT91C_PB3_A3 (AT91C_PIO_PB3) // +#define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30 +#define AT91C_PB30_NPCS2 (AT91C_PIO_PB30) // +#define AT91C_PB30_D28 (AT91C_PIO_PB30) // +#define AT91C_PIO_PB31 (1 << 31) // Pin Controlled by PB31 +#define AT91C_PB31_PCK2 (AT91C_PIO_PB31) // +#define AT91C_PB31_D29 (AT91C_PIO_PB31) // +#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4 +#define AT91C_PB4_TCLK0 (AT91C_PIO_PB4) // +#define AT91C_PB4_A4 (AT91C_PIO_PB4) // +#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5 +#define AT91C_PB5_NPCS3 (AT91C_PIO_PB5) // +#define AT91C_PB5_A5 (AT91C_PIO_PB5) // +#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6 +#define AT91C_PB6_PCK0 (AT91C_PIO_PB6) // +#define AT91C_PB6_A6 (AT91C_PIO_PB6) // +#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7 +#define AT91C_PB7_PWM3 (AT91C_PIO_PB7) // +#define AT91C_PB7_A7 (AT91C_PIO_PB7) // +#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8 +#define AT91C_PB8_ADTRG (AT91C_PIO_PB8) // +#define AT91C_PB8_A8 (AT91C_PIO_PB8) // +#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9 +#define AT91C_PB9_NPCS1 (AT91C_PIO_PB9) // +#define AT91C_PB9_A9 (AT91C_PIO_PB9) // +#define AT91C_PIO_PC0 (1 << 0) // Pin Controlled by PC0 +#define AT91C_PC0_D0 (AT91C_PIO_PC0) // +#define AT91C_PIO_PC1 (1 << 1) // Pin Controlled by PC1 +#define AT91C_PC1_D1 (AT91C_PIO_PC1) // +#define AT91C_PIO_PC10 (1 << 10) // Pin Controlled by PC10 +#define AT91C_PC10_D10 (AT91C_PIO_PC10) // +#define AT91C_PC10_PCK0 (AT91C_PIO_PC10) // +#define AT91C_PIO_PC11 (1 << 11) // Pin Controlled by PC11 +#define AT91C_PC11_D11 (AT91C_PIO_PC11) // +#define AT91C_PC11_PCK1 (AT91C_PIO_PC11) // +#define AT91C_PIO_PC12 (1 << 12) // Pin Controlled by PC12 +#define AT91C_PC12_D12 (AT91C_PIO_PC12) // +#define AT91C_PC12_PCK2 (AT91C_PIO_PC12) // +#define AT91C_PIO_PC13 (1 << 13) // Pin Controlled by PC13 +#define AT91C_PC13_D13 (AT91C_PIO_PC13) // +#define AT91C_PIO_PC14 (1 << 14) // Pin Controlled by PC14 +#define AT91C_PC14_D14 (AT91C_PIO_PC14) // +#define AT91C_PC14_NPCS1 (AT91C_PIO_PC14) // +#define AT91C_PIO_PC15 (1 << 15) // Pin Controlled by PC15 +#define AT91C_PC15_D15 (AT91C_PIO_PC15) // +#define AT91C_PC15_NCS3_NANDCS (AT91C_PIO_PC15) // +#define AT91C_PIO_PC16 (1 << 16) // Pin Controlled by PC16 +#define AT91C_PC16_A18 (AT91C_PIO_PC16) // +#define AT91C_PC16_NWAIT (AT91C_PIO_PC16) // +#define AT91C_PIO_PC17 (1 << 17) // Pin Controlled by PC17 +#define AT91C_PC17_A19 (AT91C_PIO_PC17) // +#define AT91C_PC17_NANDOE (AT91C_PIO_PC17) // +#define AT91C_PIO_PC18 (1 << 18) // Pin Controlled by PC18 +#define AT91C_PC18_A20 (AT91C_PIO_PC18) // +#define AT91C_PC18_NANDWE (AT91C_PIO_PC18) // +#define AT91C_PIO_PC19 (1 << 19) // Pin Controlled by PC19 +#define AT91C_PC19_A21 (AT91C_PIO_PC19) // +#define AT91C_PIO_PC2 (1 << 2) // Pin Controlled by PC2 +#define AT91C_PC2_D2 (AT91C_PIO_PC2) // +#define AT91C_PIO_PC20 (1 << 20) // Pin Controlled by PC20 +#define AT91C_PC20_A22 (AT91C_PIO_PC20) // +#define AT91C_PC20_NCS7 (AT91C_PIO_PC20) // +#define AT91C_PIO_PC21 (1 << 21) // Pin Controlled by PC21 +#define AT91C_PC21_A23 (AT91C_PIO_PC21) // +#define AT91C_PC21_NWR0_NWE_CFWE (AT91C_PIO_PC21) // +#define AT91C_PIO_PC22 (1 << 22) // Pin Controlled by PC22 +#define AT91C_PC22_A24 (AT91C_PIO_PC22) // +#define AT91C_PC22_NRD_CFOE (AT91C_PIO_PC22) // +#define AT91C_PIO_PC23 (1 << 23) // Pin Controlled by PC23 +#define AT91C_PC23_A25_CFRNW (AT91C_PIO_PC23) // +#define AT91C_PC23_NCS0 (AT91C_PIO_PC23) // +#define AT91C_PIO_PC3 (1 << 3) // Pin Controlled by PC3 +#define AT91C_PC3_D3 (AT91C_PIO_PC3) // +#define AT91C_PIO_PC4 (1 << 4) // Pin Controlled by PC4 +#define AT91C_PC4_D4 (AT91C_PIO_PC4) // +#define AT91C_PIO_PC5 (1 << 5) // Pin Controlled by PC5 +#define AT91C_PC5_D5 (AT91C_PIO_PC5) // +#define AT91C_PIO_PC6 (1 << 6) // Pin Controlled by PC6 +#define AT91C_PC6_D6 (AT91C_PIO_PC6) // +#define AT91C_PIO_PC7 (1 << 7) // Pin Controlled by PC7 +#define AT91C_PC7_D7 (AT91C_PIO_PC7) // +#define AT91C_PIO_PC8 (1 << 8) // Pin Controlled by PC8 +#define AT91C_PC8_D8 (AT91C_PIO_PC8) // +#define AT91C_PC8_RTS1 (AT91C_PIO_PC8) // +#define AT91C_PIO_PC9 (1 << 9) // Pin Controlled by PC9 +#define AT91C_PC9_D9 (AT91C_PIO_PC9) // +#define AT91C_PC9_DTR1 (AT91C_PIO_PC9) // + +// ***************************************************************************** +// PERIPHERAL ID DEFINITIONS FOR AT91SAM7SE512 +// ***************************************************************************** +#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) +#define AT91C_ID_SYS ( 1) // System Peripheral +#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A +#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B +#define AT91C_ID_PIOC ( 4) // Parallel IO Controller C +#define AT91C_ID_SPI ( 5) // Serial Peripheral Interface 0 +#define AT91C_ID_US0 ( 6) // USART 0 +#define AT91C_ID_US1 ( 7) // USART 1 +#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller +#define AT91C_ID_TWI ( 9) // Two-Wire Interface +#define AT91C_ID_PWMC (10) // PWM Controller +#define AT91C_ID_UDP (11) // USB Device Port +#define AT91C_ID_TC0 (12) // Timer Counter 0 +#define AT91C_ID_TC1 (13) // Timer Counter 1 +#define AT91C_ID_TC2 (14) // Timer Counter 2 +#define AT91C_ID_ADC (15) // Analog-to-Digital Converter +#define AT91C_ID_16_Reserved (16) // Reserved +#define AT91C_ID_17_Reserved (17) // Reserved +#define AT91C_ID_18_Reserved (18) // Reserved +#define AT91C_ID_19_Reserved (19) // Reserved +#define AT91C_ID_20_Reserved (20) // Reserved +#define AT91C_ID_21_Reserved (21) // Reserved +#define AT91C_ID_22_Reserved (22) // Reserved +#define AT91C_ID_23_Reserved (23) // Reserved +#define AT91C_ID_24_Reserved (24) // Reserved +#define AT91C_ID_25_Reserved (25) // Reserved +#define AT91C_ID_26_Reserved (26) // Reserved +#define AT91C_ID_27_Reserved (27) // Reserved +#define AT91C_ID_28_Reserved (28) // Reserved +#define AT91C_ID_IRQ0 (29) // Advanced Interrupt Controller (IRQ0) +#define AT91C_ID_IRQ1 (30) // Advanced Interrupt Controller (IRQ1) +#define AT91C_ID_31_Reserved (31) // Reserved +#define AT91C_ALL_INT (0x6000FFFF) // ALL VALID INTERRUPTS + +// ***************************************************************************** +// BASE ADDRESS DEFINITIONS FOR AT91SAM7SE512 +// ***************************************************************************** +#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address +#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address +#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address +#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address +#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address +#define AT91C_BASE_PIOB (AT91_CAST(AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address +#define AT91C_BASE_PIOC (AT91_CAST(AT91PS_PIO) 0xFFFFF800) // (PIOC) Base Address +#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address +#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address +#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address +#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address +#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address +#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address +#define AT91C_BASE_VREG (AT91_CAST(AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address +#define AT91C_BASE_MC (AT91_CAST(AT91PS_MC) 0xFFFFFF00) // (MC) Base Address +#define AT91C_BASE_EFC0 (AT91_CAST(AT91PS_EFC) 0xFFFFFF60) // (EFC0) Base Address +#define AT91C_BASE_EFC1 (AT91_CAST(AT91PS_EFC) 0xFFFFFF70) // (EFC1) Base Address +#define AT91C_BASE_PDC_SPI (AT91_CAST(AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address +#define AT91C_BASE_SPI (AT91_CAST(AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address +#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address +#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFC4000) // (US1) Base Address +#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address +#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFC0000) // (US0) Base Address +#define AT91C_BASE_PDC_SSC (AT91_CAST(AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address +#define AT91C_BASE_SSC (AT91_CAST(AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address +#define AT91C_BASE_TWI (AT91_CAST(AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address +#define AT91C_BASE_PWMC_CH3 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address +#define AT91C_BASE_PWMC_CH2 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address +#define AT91C_BASE_PWMC_CH1 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address +#define AT91C_BASE_PWMC_CH0 (AT91_CAST(AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address +#define AT91C_BASE_PWMC (AT91_CAST(AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address +#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address +#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address +#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address +#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address +#define AT91C_BASE_TCB (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address +#define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address +#define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address +#define AT91C_BASE_EBI (AT91_CAST(AT91PS_EBI) 0xFFFFFF80) // (EBI) Base Address +#define AT91C_BASE_SMC (AT91_CAST(AT91PS_SMC2) 0xFFFFFF90) // (SMC) Base Address +#define AT91C_BASE_SDRC (AT91_CAST(AT91PS_SDRC) 0xFFFFFFB0) // (SDRC) Base Address +#define AT91C_BASE_HECC (AT91_CAST(AT91PS_ECC) 0xFFFFFFDC) // (HECC) Base Address + +// ***************************************************************************** +// MEMORY MAPPING DEFINITIONS FOR AT91SAM7SE512 +// ***************************************************************************** +// ISRAM +#define AT91C_ISRAM (0x00200000) // Internal SRAM base address +#define AT91C_ISRAM_SIZE (0x00008000) // Internal SRAM size in byte (32 Kbytes) +// IFLASH +#define AT91C_IFLASH (0x00100000) // Internal FLASH base address +#define AT91C_IFLASH_SIZE (0x00080000) // Internal FLASH size in byte (512 Kbytes) +#define AT91C_IFLASH_PAGE_SIZE (256) // Internal FLASH Page Size: 256 bytes +#define AT91C_IFLASH_LOCK_REGION_SIZE (16384) // Internal FLASH Lock Region Size: 16 Kbytes +#define AT91C_IFLASH_NB_OF_PAGES (2048) // Internal FLASH Number of Pages: 2048 bytes +#define AT91C_IFLASH_NB_OF_LOCK_BITS (32) // Internal FLASH Number of Lock Bits: 32 bytes + +#endif diff --git a/at91lib/boards/theva-rev1/at91sam7se512/flash.icf b/at91lib/boards/theva-rev1/at91sam7se512/flash.icf new file mode 100644 index 0000000..4971f69 --- /dev/null +++ b/at91lib/boards/theva-rev1/at91sam7se512/flash.icf @@ -0,0 +1,48 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x100000; +define symbol __ICFEDIT_region_ROM_end__ = 0x17FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x200000; +define symbol __ICFEDIT_region_RAM_end__ = 0x207FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_startup__ = 0x100; +define symbol __ICFEDIT_size_vectors__ = 0x100; +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_sysstack__ = 0x60; +define symbol __ICFEDIT_size_irqstack__ = 0x60; +define symbol __ICFEDIT_size_heap__ = 0x0; +/*-Exports-*/ +export symbol __ICFEDIT_region_ROM_start__; +export symbol __ICFEDIT_region_ROM_end__; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +export symbol __ICFEDIT_size_startup__; +export symbol __ICFEDIT_size_vectors__; +export symbol __ICFEDIT_size_cstack__; +export symbol __ICFEDIT_size_sysstack__; +export symbol __ICFEDIT_size_irqstack__; +export symbol __ICFEDIT_size_heap__; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region STA_region = mem:[from __ICFEDIT_region_ROM_start__ size __ICFEDIT_size_startup__]; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__+__ICFEDIT_size_startup__ to __ICFEDIT_region_ROM_end__]; +define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SYS_STACK with alignment = 8, size = __ICFEDIT_size_sysstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +initialize by copy { section .vectors }; +do not initialize { section .noinit }; + +place in STA_region { section .cstartup }; +place in ROM_region { readonly }; +place in VEC_region { section .vectors }; +place in RAM_region { readwrite, block IRQ_STACK, block SYS_STACK, block CSTACK, block HEAP }; + diff --git a/at91lib/boards/theva-rev1/at91sam7se512/flash.lds b/at91lib/boards/theva-rev1/at91sam7se512/flash.lds new file mode 100644 index 0000000..ce1f8c6 --- /dev/null +++ b/at91lib/boards/theva-rev1/at91sam7se512/flash.lds @@ -0,0 +1,77 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal Flash on the AT91SAM7SE512. + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(entry) + +MEMORY +{ + sram (W!RX) : ORIGIN = 0x200000, LENGTH = 0x8000 + flash (RX) : ORIGIN = 0x100000, LENGTH = 0x80000 +} + +SECTIONS +{ + .fixed : + { + . = ALIGN(4); + _sfixed = .; + *(.text*) + *(.rodata*) + . = ALIGN(4); + _efixed = .; + } >flash + + .relocate : AT (_efixed) + { + . = ALIGN(4); + _srelocate = .; + *(.vectors) + *(.ramfunc) + *(.data) + . = ALIGN(4); + _erelocate = .; + } >sram + + .bss (NOLOAD) : { + _szero = .; + *(.bss) + . = ALIGN(4); + _ezero = .; + } >sram + + _sstack = 0x208000; +} +end = .; + diff --git a/at91lib/boards/theva-rev1/at91sam7se512/flash.sct b/at91lib/boards/theva-rev1/at91sam7se512/flash.sct new file mode 100644 index 0000000..a80397c --- /dev/null +++ b/at91lib/boards/theva-rev1/at91sam7se512/flash.sct @@ -0,0 +1,53 @@ +; * ---------------------------------------------------------------------------- +; * ATMEL Microcontroller Software Support +; * ---------------------------------------------------------------------------- +; * Copyright (c) 2008, Atmel Corporation +; * +; * All rights reserved. +; * +; * Redistribution and use in source and binary forms, with or without +; * modification, are permitted provided that the following conditions are met: +; * +; * - Redistributions of source code must retain the above copyright notice, +; * this list of conditions and the disclaimer below. +; * +; * Atmel's name may not be used to endorse or promote products derived from +; * this software without specific prior written permission. +; * +; * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +; * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +; * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +; * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +; * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +; * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +; * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +; * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +; * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +; * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; * ---------------------------------------------------------------------------- + +; *------------------------------------------------------------------------------ +; * Linker scatter for running in internal FLASH on the AT91SAM7SE512 +; *----------------------------------------------------------------------------*/ + +Load_region 0x100000 0x80000 { + + Fixed_region 0x100000 0x80000 { + *(cstartup +First) + .ANY (+RO) + } + + Relocate_region 0x200000 { + *.o (VECTOR, +First) + .ANY (+RW +ZI) + } + + ScatterAssert(ImageLength(Relocate_region) < 0x6000) + + ARM_LIB_HEAP 0x206000 EMPTY 0x1000 { + } + + ARM_LIB_STACK 0x208000 EMPTY -0x1000 { + } +} + diff --git a/at91lib/boards/theva-rev1/at91sam7se512/sdram.icf b/at91lib/boards/theva-rev1/at91sam7se512/sdram.icf new file mode 100644 index 0000000..bb42b18 --- /dev/null +++ b/at91lib/boards/theva-rev1/at91sam7se512/sdram.icf @@ -0,0 +1,46 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_SDRAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_SDRAM_end__ = 0x21FFFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x200000; +define symbol __ICFEDIT_region_RAM_end__ = 0x207FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_startup__ = 0x100; +define symbol __ICFEDIT_size_vectors__ = 0x100; +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_sysstack__ = 0x60; +define symbol __ICFEDIT_size_irqstack__ = 0x60; +define symbol __ICFEDIT_size_heap__ = 0x0; +/*-Exports-*/ +export symbol __ICFEDIT_region_SDRAM_start__; +export symbol __ICFEDIT_region_SDRAM_end__; +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +export symbol __ICFEDIT_size_startup__; +export symbol __ICFEDIT_size_vectors__; +export symbol __ICFEDIT_size_cstack__; +export symbol __ICFEDIT_size_sysstack__; +export symbol __ICFEDIT_size_irqstack__; +export symbol __ICFEDIT_size_heap__; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region STA_region = mem:[from __ICFEDIT_region_SDRAM_start__ size __ICFEDIT_size_startup__]; +define region SDRAM_region = mem:[from __ICFEDIT_region_SDRAM_start__+__ICFEDIT_size_startup__ to __ICFEDIT_region_SDRAM_end__]; +define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SYS_STACK with alignment = 8, size = __ICFEDIT_size_sysstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { section .vectors }; +do not initialize { section .noinit }; + +place in STA_region { section .cstartup }; +place in VEC_region { section .vectors }; +place in SDRAM_region { readonly, readwrite, block IRQ_STACK, block SYS_STACK, block CSTACK, block HEAP }; + diff --git a/at91lib/boards/theva-rev1/at91sam7se512/sdram.lds b/at91lib/boards/theva-rev1/at91sam7se512/sdram.lds new file mode 100644 index 0000000..7eb988f --- /dev/null +++ b/at91lib/boards/theva-rev1/at91sam7se512/sdram.lds @@ -0,0 +1,79 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in external SDRAM on the AT91SAM7SE512 + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(entry) + +MEMORY +{ + sram (W!RX) : ORIGIN = 0x200000, LENGTH = 0x8000 + sdram (W!RX) : ORIGIN = 0x20000000, LENGTH = 0x2000000 +} + +SECTIONS +{ + .fixed : + { + . = ALIGN(4); + _sfixed = .; + *(.text*) + *(.rodata*) + *(.glue_7) + *(.glue_7t) + . = ALIGN(4); + _efixed = .; + } >sdram + + .relocate : AT (_efixed) + { + . = ALIGN(4); + _srelocate = .; + *(.vectors); + *(.ramfunc) + *(.data) + . = ALIGN(4); + _erelocate = .; + } >sram + + .bss (NOLOAD) : { + _szero = .; + *(.bss) + . = ALIGN(4); + _ezero = .; + } >sram + + _sstack = 0x22000000; +} +end = .; + diff --git a/at91lib/boards/theva-rev1/at91sam7se512/sdram.sct b/at91lib/boards/theva-rev1/at91sam7se512/sdram.sct new file mode 100644 index 0000000..4eacf15 --- /dev/null +++ b/at91lib/boards/theva-rev1/at91sam7se512/sdram.sct @@ -0,0 +1,50 @@ +; * ---------------------------------------------------------------------------- +; * ATMEL Microcontroller Software Support +; * ---------------------------------------------------------------------------- +; * Copyright (c) 2008, Atmel Corporation +; * +; * All rights reserved. +; * +; * Redistribution and use in source and binary forms, with or without +; * modification, are permitted provided that the following conditions are met: +; * +; * - Redistributions of source code must retain the above copyright notice, +; * this list of conditions and the disclaimer below. +; * +; * Atmel's name may not be used to endorse or promote products derived from +; * this software without specific prior written permission. +; * +; * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +; * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +; * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +; * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +; * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +; * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +; * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +; * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +; * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +; * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; * ---------------------------------------------------------------------------- + +; *------------------------------------------------------------------------------ +; * Linker scatter for running in external SDRAM on the AT91SAM7SE512 +; *----------------------------------------------------------------------------*/ + +Load_region 0x20000000 0x2000000 { + + Fixed_region 0x20000000 { + *(cstartup +First) + .ANY (+RO) + } + + Relocate_region 0x200000 0x8000 { + *.o (VECTOR, +First) + .ANY (+RW +ZI) + } + + ARM_LIB_HEAP 0x21FFE000 EMPTY 0x1000 { + } + + ARM_LIB_STACK 0x22000000 EMPTY -0x1000 { + } +} \ No newline at end of file diff --git a/at91lib/boards/theva-rev1/at91sam7se512/sdram_samba.lds b/at91lib/boards/theva-rev1/at91sam7se512/sdram_samba.lds new file mode 100644 index 0000000..43d182a --- /dev/null +++ b/at91lib/boards/theva-rev1/at91sam7se512/sdram_samba.lds @@ -0,0 +1,79 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in external SDRAM on the AT91SAM7SE512 + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(entry) + +MEMORY +{ + romcodesram (W!RX) : ORIGIN = 0x200000, LENGTH = 0x2000 + sram (W!RX) : ORIGIN = 0x202000, LENGTH = 0x6000 + sdram (W!RX) : ORIGIN = 0x20000000, LENGTH = 0x2000000 +} + +SECTIONS +{ + .fixed : + { + . = ALIGN(4); + _sfixed = .; + *(.text*) + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.data) + . = ALIGN(4); + _efixed = .; + } >sdram + + .relocate : AT (_efixed) + { + . = ALIGN(4); + _srelocate = .; + *(.vectors); + . = ALIGN(4); + _erelocate = .; + } >romcodesram + + .bss (NOLOAD) : { + _szero = .; + *(.bss) + . = ALIGN(4); + _ezero = .; + } >sram + + _sstack = 0x208000; +} +end = .; + diff --git a/at91lib/boards/theva-rev1/at91sam7se512/sram.icf b/at91lib/boards/theva-rev1/at91sam7se512/sram.icf new file mode 100644 index 0000000..49ad5e9 --- /dev/null +++ b/at91lib/boards/theva-rev1/at91sam7se512/sram.icf @@ -0,0 +1,36 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_RAM_start__ = 0x200000; +define symbol __ICFEDIT_region_RAM_end__ = 0x207FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_vectors__ = 0x100; +define symbol __ICFEDIT_size_cstack__ = 0x800; +define symbol __ICFEDIT_size_sysstack__ = 0x60; +define symbol __ICFEDIT_size_irqstack__ = 0x60; +define symbol __ICFEDIT_size_heap__ = 0x0; +/*-Exports-*/ +export symbol __ICFEDIT_region_RAM_start__; +export symbol __ICFEDIT_region_RAM_end__; +export symbol __ICFEDIT_size_vectors__; +export symbol __ICFEDIT_size_cstack__; +export symbol __ICFEDIT_size_sysstack__; +export symbol __ICFEDIT_size_irqstack__; +export symbol __ICFEDIT_size_heap__; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SYS_STACK with alignment = 8, size = __ICFEDIT_size_sysstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +do not initialize { section .noinit }; + +place in VEC_region { section .vectors }; +place in RAM_region { section .cstartup, readonly, readwrite, block IRQ_STACK, block SYS_STACK, block CSTACK, block HEAP }; + diff --git a/at91lib/boards/theva-rev1/at91sam7se512/sram.lds b/at91lib/boards/theva-rev1/at91sam7se512/sram.lds new file mode 100644 index 0000000..a5d9ce1 --- /dev/null +++ b/at91lib/boards/theva-rev1/at91sam7se512/sram.lds @@ -0,0 +1,77 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal SRAM on the AT91SAM7SE512. + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(entry) + +MEMORY +{ + sram (W!RX) : ORIGIN = 0x200000, LENGTH = 0x8000 + flash (RX) : ORIGIN = 0x100000, LENGTH = 0x80000 +} + +SECTIONS +{ + . = ALIGN(4); + .fixed : + { + _sfixed = .; + *(.vectors) + *(.ramfunc) + *(.text*) + *(.rodata*) + *(.data) + . = ALIGN(4); + _efixed = .; + } >sram + + .relocate : AT (_efixed) + { + . = ALIGN(4); + _srelocate = .; + . = ALIGN(4); + _erelocate = .; + } + + .bss (NOLOAD) : { + _szero = .; + *(.bss) + . = ALIGN(4); + _ezero = .; + } >sram + + _sstack = 0x208000; +} +end = .; + diff --git a/at91lib/boards/theva-rev1/at91sam7se512/sram.sct b/at91lib/boards/theva-rev1/at91sam7se512/sram.sct new file mode 100644 index 0000000..158f670 --- /dev/null +++ b/at91lib/boards/theva-rev1/at91sam7se512/sram.sct @@ -0,0 +1,53 @@ +; * ---------------------------------------------------------------------------- +; * ATMEL Microcontroller Software Support +; * ---------------------------------------------------------------------------- +; * Copyright (c) 2008, Atmel Corporation +; * +; * All rights reserved. +; * +; * Redistribution and use in source and binary forms, with or without +; * modification, are permitted provided that the following conditions are met: +; * +; * - Redistributions of source code must retain the above copyright notice, +; * this list of conditions and the disclaimer below. +; * +; * Atmel's name may not be used to endorse or promote products derived from +; * this software without specific prior written permission. +; * +; * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +; * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +; * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +; * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +; * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +; * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +; * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +; * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +; * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +; * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; * ---------------------------------------------------------------------------- + +; *------------------------------------------------------------------------------ +; * Linker scatter for running in internal SRAM on the AT91SAM7SE512 +; *----------------------------------------------------------------------------*/ + +Load_region 0x200000 0x8000 { + + Fixed_region 0x200000 { + *.o (VECTOR, +First) + .ANY (+RO) + } + + Relocate_region +0 { + *(cstartup +First) + .ANY (+RW +ZI) + } + + ScatterAssert((ImageLength(Fixed_region) + ImageLength(Relocate_region)) < 0x7800) + + ARM_LIB_HEAP 0x207800 EMPTY 0x400 { + } + + ARM_LIB_STACK 0x208000 EMPTY -0x400 { + } +} + diff --git a/at91lib/boards/theva-rev1/at91sam7se512/sram_samba.lds b/at91lib/boards/theva-rev1/at91sam7se512/sram_samba.lds new file mode 100644 index 0000000..efe4827 --- /dev/null +++ b/at91lib/boards/theva-rev1/at91sam7se512/sram_samba.lds @@ -0,0 +1,78 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal SRAM on the AT91SAM7SE512. + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(entry) + +MEMORY +{ + romcodesram (W!RX) : ORIGIN = 0x200000, LENGTH = 0x2000 + sram (W!RX) : ORIGIN = 0x202000, LENGTH = 0x6000 + flash (RX) : ORIGIN = 0x100000, LENGTH = 0x80000 +} + +SECTIONS +{ + . = ALIGN(4); + .fixed : + { + _sfixed = .; + *(.text*) + *(.rodata*) + *(.data) + . = ALIGN(4); + _efixed = .; + } >sram + + .relocate : AT (_efixed) + { + . = ALIGN(4); + _srelocate = .; + *(.vectors) + *(.ramfunc) + . = ALIGN(4); + _erelocate = .; + } >romcodesram + + .bss (NOLOAD) : { + _szero = .; + *(.bss) + . = ALIGN(4); + _ezero = .; + } >sram + + _sstack = 0x208000; +} +end = .; + diff --git a/at91lib/boards/theva-rev1/board.h b/at91lib/boards/theva-rev1/board.h new file mode 100644 index 0000000..8dca0cb --- /dev/null +++ b/at91lib/boards/theva-rev1/board.h @@ -0,0 +1,194 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// ¥dir +/// !Purpose +/// +/// Definition and functions for using AT91SAM7SE-related features, such +/// has PIO pins, memories, etc. +/// +/// !Usage +/// -# The code for booting the board is provided by board_cstartup.S and +/// board_lowlevel.c. +/// -# For using board PIOs, board characteristics (clock, etc.) and external +/// components, see board.h. +/// -# For manipulating memories (remapping, SDRAM, etc.), see board_memories.h. +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// ¥unit +/// !Purpose +/// +/// Definition of AT91SAM7SE-EK characteristics, AT91SAM7SE-dependant PIOs and +/// external components interfacing. +/// +/// !Usage +/// -# For operating frequency information, see "SAM7SE-EK - Operating frequencies". +/// -# For using portable PIO definitions, see "SAM7SE-EK - PIO definitions". +/// -# Several USB definitions are included here (see "SAM7SE-EK - USB device"). +/// -# For external components definitions, see "SAM7SE-EK - External components". +/// -# For memory-related definitions, see "SAM7SE-EK - Memories". +//------------------------------------------------------------------------------ + +#ifndef BOARD_H +#define BOARD_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#if defined(at91sam7se512) + #include "at91sam7se512/AT91SAM7SE512.h" +#else + #error Board does not support the specified chip. +#endif + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// ¥page "SAM7SE-EK - Board Description" +/// This page lists several definition related to the board description +/// +/// !Definitions +/// - BOARD_NAME + +/// Name of the board. +#define BOARD_NAME "THEVA rev.1" +/// Board definition. +#define theva_rev1 +/// Family definition. +#define at91sam7se +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// ¥page "SAM7SE-EK - Operating frequencies" +/// This page lists several definition related to the board operating frequency +/// (when using the initialization done by board_lowlevel.c). +/// +/// !Definitions +/// - BOARD_MAINOSC +/// - BOARD_MCK + +/// Frequency of the board main oscillator. +#define BOARD_MAINOSC 18432000 + +/// Master clock frequency (when using board_lowlevel.c). +#define BOARD_MCK 48000000 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// ADC +//------------------------------------------------------------------------------ +/// ADC clock frequency, at 10-bit resolution (in Hz) +#define ADC_MAX_CK_10BIT 5000000 +/// ADC clock frequency, at 8-bit resolution (in Hz) +#define ADC_MAX_CK_8BIT 8000000 +/// Startup time max, return from Idle mode (in ｵs) +#define ADC_STARTUP_TIME_MAX 20 +/// Track and hold Acquisition Time min (in ns) +#define ADC_TRACK_HOLD_TIME_MIN 600 + + +//------------------------------------------------------------------------------ +/// ¥page "SAM7SE-EK - USB device" +/// This page lists constants describing several characteristics (controller +/// type, D+ pull-up type, etc.) of the USB device controller of the chip/board. +/// + +/// Chip has a UDP controller. +#define BOARD_USB_UDP + +/// Indicates the D+ pull-up is internal to the USB controller. +#define BOARD_USB_PULLUP_INTERNAL + +/// Number of endpoints in the USB controller. +#define BOARD_USB_NUMENDPOINTS 8 + +/// Returns the maximum packet size of the given endpoint. +#define BOARD_USB_ENDPOINTS_MAXPACKETSIZE(i) (((i == 4) || (i == 5)) ? 512 : 64) + +/// Returns the number of FIFO banks for the given endpoint. +#define BOARD_USB_ENDPOINTS_BANKS(i) (((i == 0) || (i == 3)) ? 1 : 2) + +/// USB attributes configuration descriptor (bus or self powered, remote wakeup) +#define BOARD_USB_BMATTRIBUTES USBConfigurationDescriptor_SELFPOWERED_NORWAKEUP +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// ¥page "SAM7SE - PIO definitions" +/// This pages lists all the pio definitions contained in board.h. The constants +/// are named using the following convention: PIN_* for a constant which defines +/// a single Pin instance (but may include several PIOs sharing the same +/// controller), and PINS_* for a list of Pin instances. +/// + +/// DBGU pins (DTXD and DRXD) definitions. +#define PINS_DBGU {0x00000600, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} + +/// LED #0 pin definition. +#define PIN_LED_0 {1 << 8, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT} +/// LED #1 pin definition. +#define PIN_LED_1 {1 << 31, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_OUTPUT_1, PIO_DEFAULT} +/// LED #2 pin definition. +#define PIN_LED_2 {1 << 30, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_OUTPUT_1, PIO_DEFAULT} +/// List of all LEDs pin definitions. +#define PINS_LEDS PIN_LED_0, PIN_LED_1, PIN_LED_2 + +/// ADC_AD0 pin definition. +#define PIN_ADC_ADC0 {1 << 17, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_INPUT, PIO_DEFAULT} +/// ADC_AD1 pin definition. +#define PIN_ADC_ADC1 {1 << 18, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_INPUT, PIO_DEFAULT} +/// ADC_AD2 pin definition. +#define PIN_ADC_ADC2 {1 << 19, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_INPUT, PIO_DEFAULT} +/// ADC_AD3 pin definition. +#define PIN_ADC_ADC3 {1 << 20, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_INPUT, PIO_DEFAULT} +/// Pins ADC +#define PINS_ADC PIN_ADC_ADC0, PIN_ADC_ADC1, PIN_ADC_ADC2, PIN_ADC_ADC3 + +/// USB VBus monitoring pin definition. +#define PIN_USB_VBUS {1 << 19, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_INPUT, PIO_DEFAULT} + +#define PINS_SRAM \ + {0x000000FE, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_B, PIO_DEFAULT}, \ + {0x0000FFFF, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT}, \ + {0x00E00000, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} +//------------------------------------------------------------------------------ + +#define PIN_PWM_ENABLE {1 << 16, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} + +#define PIN_PWM_CYCLE {1 << 19, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_INPUT, PIO_DEFAULT} +#define PIN_PWM_CYCLE2 {1 << 20, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT} +//#define PIN_PWM_CYCLE {1 << 19, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT} + + +#endif //#ifndef BOARD_H + diff --git a/at91lib/boards/theva-rev1/board.mak b/at91lib/boards/theva-rev1/board.mak new file mode 100644 index 0000000..3b1b738 --- /dev/null +++ b/at91lib/boards/theva-rev1/board.mak @@ -0,0 +1,32 @@ +# ---------------------------------------------------------------------------- +# ATMEL Microcontroller Software Support +# ---------------------------------------------------------------------------- +# Copyright (c) 2008, Atmel Corporation +# +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# - Redistributions of source code must retain the above copyright notice, +# this list of conditions and the disclaimer below. +# +# Atmel's name may not be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +# DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +# OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# ---------------------------------------------------------------------------- + +# Defines which are the available memory targets for the AT91SAM7SE-EK board. + +MEMORIES = flash + diff --git a/at91lib/boards/theva-rev1/board_cstartup.S b/at91lib/boards/theva-rev1/board_cstartup.S new file mode 100644 index 0000000..70e66ba --- /dev/null +++ b/at91lib/boards/theva-rev1/board_cstartup.S @@ -0,0 +1,181 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "board.h" + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +#define IRQ_STACK_SIZE 8*3*16 + +#define ARM_MODE_ABT 0x17 +#define ARM_MODE_FIQ 0x11 +#define ARM_MODE_IRQ 0x12 +#define ARM_MODE_SVC 0x13 + +#define I_BIT 0x80 +#define F_BIT 0x40 + +//------------------------------------------------------------------------------ +// Startup routine +//------------------------------------------------------------------------------ + + .align 4 + .arm + +/* Exception vectors + *******************/ + .section .vectors, "a" + +resetVector: + ldr pc, =resetHandler /* Reset */ +undefVector: + b undefVector /* Undefined instruction */ +swiVector: + b swiVector /* Software interrupt */ +prefetchAbortVector: + b prefetchAbortVector /* Prefetch abort */ +dataAbortVector: + b dataAbortVector /* Data abort */ +reservedVector: + b reservedVector /* Reserved for future use */ +irqVector: + b irqHandler /* Interrupt */ +fiqVector: + /* Fast interrupt */ +//------------------------------------------------------------------------------ +/// Handles a fast interrupt request by branching to the address defined in the +/// AIC. +//------------------------------------------------------------------------------ +fiqHandler: + b fiqHandler + +//------------------------------------------------------------------------------ +/// Handles incoming interrupt requests by branching to the corresponding +/// handler, as defined in the AIC. Supports interrupt nesting. +//------------------------------------------------------------------------------ +irqHandler: + +/* Save interrupt context on the stack to allow nesting */ + sub lr, lr, #4 + stmfd sp!, {lr} + mrs lr, SPSR + stmfd sp!, {r0, lr} + +/* Write in the IVR to support Protect Mode */ + ldr lr, =AT91C_BASE_AIC + ldr r0, [r14, #AIC_IVR] + str lr, [r14, #AIC_IVR] + +/* Branch to interrupt handler in Supervisor mode */ + msr CPSR_c, #ARM_MODE_SVC | F_BIT + stmfd sp!, {r1-r3, r4, r12, lr} + mov lr, pc + bx r0 + ldmia sp!, {r1-r3, r4, r12, lr} + msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT + +/* Acknowledge interrupt */ + ldr lr, =AT91C_BASE_AIC + str lr, [r14, #AIC_EOICR] + +/* Restore interrupt context and branch back to calling code */ + ldmia sp!, {r0, lr} + msr SPSR_cxsf, lr + ldmia sp!, {pc}^ + +//------------------------------------------------------------------------------ +/// Initializes the chip and branches to the main() function. +//------------------------------------------------------------------------------ + .section .text + .global entry + +entry: +resetHandler: + +/* Dummy access to the .vectors section so it does not get optimized */ + ldr r0, =resetVector + +/* Set pc to actual code location (i.e. not in remap zone) */ + ldr pc, =1f + +/* Perform low-level initialization of the chip using LowLevelInit() */ +1: + ldr r4, =_sstack + mov sp, r4 + ldr r0, =LowLevelInit + mov lr, pc + bx r0 + +/* Initialize the relocate segment */ + + ldr r0, =_efixed + ldr r1, =_srelocate + ldr r2, =_erelocate +1: + cmp r1, r2 + ldrcc r3, [r0], #4 + strcc r3, [r1], #4 + bcc 1b + +/* Clear the zero segment */ + ldr r0, =_szero + ldr r1, =_ezero + mov r2, #0 +1: + cmp r0, r1 + strcc r2, [r0], #4 + bcc 1b + +/* Setup stacks + **************/ +/* IRQ mode */ + msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT + mov sp, r4 + sub r4, r4, #IRQ_STACK_SIZE + +/* Supervisor mode (interrupts enabled) */ + msr CPSR_c, #ARM_MODE_SVC | F_BIT + mov sp, r4 + +/* Branch to main() + ******************/ + ldr r0, =main + mov lr, pc + bx r0 + +/* Loop indefinitely when program is finished */ +1: + b 1b + diff --git a/at91lib/boards/theva-rev1/board_cstartup_iar.s b/at91lib/boards/theva-rev1/board_cstartup_iar.s new file mode 100644 index 0000000..ab845ba --- /dev/null +++ b/at91lib/boards/theva-rev1/board_cstartup_iar.s @@ -0,0 +1,179 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/* + IAR startup file for AT91SAM7SE microcontrollers. + */ + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION IRQ_STACK:DATA:NOROOT(2) + SECTION CSTACK:DATA:NOROOT(3) + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#define __ASSEMBLY__ +#include "board.h" + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +#define ARM_MODE_ABT 0x17 +#define ARM_MODE_FIQ 0x11 +#define ARM_MODE_IRQ 0x12 +#define ARM_MODE_SVC 0x13 +#define ARM_MODE_SYS 0x1F + +#define I_BIT 0x80 +#define F_BIT 0x40 + +//------------------------------------------------------------------------------ +// Startup routine +//------------------------------------------------------------------------------ + +/* + Exception vectors + */ + SECTION .vectors:CODE:NOROOT(2) + + PUBLIC resetVector + PUBLIC irqHandler + + EXTERN Undefined_Handler + EXTERN SWI_Handler + EXTERN Prefetch_Handler + EXTERN Abort_Handler + EXTERN FIQ_Handler + + ARM + +__iar_init$$done: ; The interrupt vector is not needed + ; until after copy initialization is done + +resetVector: + ; All default exception handlers (except reset) are + ; defined as weak symbol definitions. + ; If a handler is defined by the application it will take precedence. + LDR pc, =resetHandler ; Reset + LDR pc, Undefined_Addr ; Undefined instructions + LDR pc, SWI_Addr ; Software interrupt (SWI/SYS) + LDR pc, Prefetch_Addr ; Prefetch abort + LDR pc, Abort_Addr ; Data abort + B . ; RESERVED + LDR pc, =irqHandler ; IRQ + LDR pc, FIQ_Addr ; FIQ + +Undefined_Addr: DCD Undefined_Handler +SWI_Addr: DCD SWI_Handler +Prefetch_Addr: DCD Prefetch_Handler +Abort_Addr: DCD Abort_Handler +FIQ_Addr: DCD FIQ_Handler + +/* + Handles incoming interrupt requests by branching to the corresponding + handler, as defined in the AIC. Supports interrupt nesting. + */ +irqHandler: + /* Save interrupt context on the stack to allow nesting */ + SUB lr, lr, #4 + STMFD sp!, {lr} + MRS lr, SPSR + STMFD sp!, {r0, lr} + + /* Write in the IVR to support Protect Mode */ + LDR lr, =AT91C_BASE_AIC + LDR r0, [r14, #AIC_IVR] + STR lr, [r14, #AIC_IVR] + + /* Branch to interrupt handler in Supervisor mode */ + MSR CPSR_c, #ARM_MODE_SYS + STMFD sp!, {r1-r3, r4, r12, lr} + MOV lr, pc + BX r0 + LDMIA sp!, {r1-r3, r4, r12, lr} + MSR CPSR_c, #ARM_MODE_IRQ | I_BIT + + /* Acknowledge interrupt */ + LDR lr, =AT91C_BASE_AIC + STR lr, [r14, #AIC_EOICR] + + /* Restore interrupt context and branch back to calling code */ + LDMIA sp!, {r0, lr} + MSR SPSR_cxsf, lr + LDMIA sp!, {pc}^ + + +/* + After a reset, execution starts here, the mode is ARM, supervisor + with interrupts disabled. + Initializes the chip and branches to the main() function. + */ + SECTION .cstartup:CODE:NOROOT(2) + + PUBLIC resetHandler + EXTERN LowLevelInit + EXTERN ?main + REQUIRE resetVector + ARM + +resetHandler: + + /* Set pc to actual code location (i.e. not in remap zone) */ + LDR pc, =label + + /* Perform low-level initialization of the chip using LowLevelInit() */ +label: + LDR r0, =LowLevelInit + LDR r4, =SFE(CSTACK) + MOV sp, r4 + MOV lr, pc + BX r0 + + /* Set up the interrupt stack pointer. */ + MSR cpsr_c, #ARM_MODE_IRQ | I_BIT | F_BIT ; Change the mode + LDR sp, =SFE(IRQ_STACK) + + /* Set up the SYS stack pointer. */ + MSR cpsr_c, #ARM_MODE_SYS | F_BIT ; Change the mode + LDR sp, =SFE(CSTACK) + + /* Branch to main() */ + LDR r0, =?main + MOV lr, pc + BX r0 + + /* Loop indefinitely when program is finished */ +loop4: + B loop4 + + END diff --git a/at91lib/boards/theva-rev1/board_cstartup_keil.s b/at91lib/boards/theva-rev1/board_cstartup_keil.s new file mode 100644 index 0000000..78a0b00 --- /dev/null +++ b/at91lib/boards/theva-rev1/board_cstartup_keil.s @@ -0,0 +1,207 @@ +; * ---------------------------------------------------------------------------- +; * ATMEL Microcontroller Software Support +; * ---------------------------------------------------------------------------- +; * Copyright (c) 2008, Atmel Corporation +; * +; * All rights reserved. +; * +; * Redistribution and use in source and binary forms, with or without +; * modification, are permitted provided that the following conditions are met: +; * +; * - Redistributions of source code must retain the above copyright notice, +; * this list of conditions and the disclaimer below. +; * +; * Atmel's name may not be used to endorse or promote products derived from +; * this software without specific prior written permission. +; * +; * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +; * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +; * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +; * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +; * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +; * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +; * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +; * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +; * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +; * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; * ---------------------------------------------------------------------------- + + +; KEIL startup file for AT91SAM7SE microcontrollers. + +; ------------------------------------------------------------------------------ +; Definitions +; ------------------------------------------------------------------------------ + +; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs + +ARM_MODE_USR EQU 0x10 +ARM_MODE_FIQ EQU 0x11 +ARM_MODE_IRQ EQU 0x12 +ARM_MODE_SVC EQU 0x13 +ARM_MODE_ABT EQU 0x17 +ARM_MODE_UND EQU 0x1B +ARM_MODE_SYS EQU 0x1F + +I_BIT EQU 0x80 ; when I bit is set, IRQ is disabled +F_BIT EQU 0x40 ; when F bit is set, FIQ is disabled + +AT91C_BASE_AIC EQU 0xFFFFF000 +AIC_IVR EQU 0x100 +AIC_EOICR EQU 0x130 + +UND_Stack_Size EQU 0x00000000 +SVC_Stack_Size EQU 0x00000100 +ABT_Stack_Size EQU 0x00000000 +FIQ_Stack_Size EQU 0x00000000 +IRQ_Stack_Size EQU 0x00000080 +USR_Stack_Size EQU 0x00000400 + + PRESERVE8 + +; Area Definition and Entry Point +; Startup Code must be linked first at Address at which it expects to run. + + AREA VECTOR, CODE + ARM + +; Exception Vectors + +Vectors + LDR pc,=resetHandler +undefVector + b undefVector ; Undefined instruction +swiVector + b swiVector ; Software interrupt +prefetchAbortVector + b prefetchAbortVector ; Prefetch abort +dataAbortVector + b dataAbortVector ; Data abort +reservedVector + b reservedVector ; Reserved for future use +irqVector + b irqHandler ; Interrupt +fiqVector + ; Fast interrupt + +;------------------------------------------------------------------------------ +; Handles a fast interrupt request by branching to the address defined in the +; AIC. +;------------------------------------------------------------------------------ +fiqHandler + b fiqHandler + +;------------------------------------------------------------------------------ +; Handles incoming interrupt requests by branching to the corresponding +; handler, as defined in the AIC. Supports interrupt nesting. +;------------------------------------------------------------------------------ +irqHandler + ; Save interrupt context on the stack to allow nesting */ + SUB lr, lr, #4 + STMFD sp!, {lr} + MRS lr, SPSR + STMFD sp!, {r0,r1,lr} + + ; Write in the IVR to support Protect Mode */ + LDR lr, =AT91C_BASE_AIC + LDR r0, [r14, #AIC_IVR] + STR lr, [r14, #AIC_IVR] + + ; Branch to interrupt handler in Supervisor mode */ + MSR CPSR_c, #ARM_MODE_SVC + STMFD sp!, {r1-r4, r12, lr} + MOV lr, pc + BX r0 + LDMIA sp!, {r1-r4, r12, lr} + MSR CPSR_c, #ARM_MODE_IRQ | I_BIT + + ; Acknowledge interrupt */ + LDR lr, =AT91C_BASE_AIC + STR lr, [r14, #AIC_EOICR] + + ; Restore interrupt context and branch back to calling code + LDMIA sp!, {r0,r1,lr} + MSR SPSR_cxsf, lr + LDMIA sp!, {pc}^ + +;------------------------------------------------------------------------------ +; After a reset, execution starts here, the mode is ARM, supervisor +; with interrupts disabled. +; Initializes the chip and branches to the main() function. +;------------------------------------------------------------------------------ + + AREA cstartup, CODE + ENTRY ; Entry point for the application + + +; Reset Handler + + EXPORT resetHandler + IMPORT |Image$$Fixed_region$$Limit| + IMPORT |Image$$Relocate_region$$Base| + IMPORT |Image$$Relocate_region$$ZI$$Base| + IMPORT |Image$$Relocate_region$$ZI$$Limit| + IMPORT |Image$$ARM_LIB_STACK$$Base| + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| + + ; Perform low-level initialization of the chip using LowLevelInit() + IMPORT LowLevelInit + +resetHandler + + ; Set pc to actual code location (i.e. not in remap zone) + LDR pc, =label +label + ; Set up temporary stack (Top of the SRAM) + LDR r0, = |Image$$ARM_LIB_STACK$$ZI$$Limit| + MOV sp, r0 + ; Call Low level init + LDR r0, =LowLevelInit + MOV lr, pc + BX r0 + + +;Initialize the Relocate_region segment + LDR r0, = |Image$$Fixed_region$$Limit| + LDR r1, = |Image$$Relocate_region$$Base| + LDR r3, = |Image$$Relocate_region$$ZI$$Base| + + CMP r0, r1 + BEQ %1 + + + ; Copy init data +0 CMP r1, r3 + LDRCC r2, [r0], #4 + STRCC r2, [r1], #4 + BCC %0 + +1 LDR r1, =|Image$$Relocate_region$$ZI$$Limit| + MOV r2, #0 +2 CMP r3, r1 + STRCC r2, [r3], #4 + BCC %2 + + +; Setup Stack for each mode + + LDR R0, = |Image$$ARM_LIB_STACK$$ZI$$Limit| + +; Enter IRQ Mode and set its Stack Pointer + MSR CPSR_c, #ARM_MODE_IRQ:OR:I_BIT:OR:F_BIT + MOV SP, R0 + SUB R4, SP, #IRQ_Stack_Size + +; Supervisor mode (interrupts enabled) + MSR CPSR_c, #ARM_MODE_SVC | F_BIT + MOV SP, R4 + +; Enter the C code + + IMPORT __main + LDR R0, =__main + BX R0 +loop4 + B loop4 + + END diff --git a/at91lib/boards/theva-rev1/board_lowlevel.c b/at91lib/boards/theva-rev1/board_lowlevel.c new file mode 100644 index 0000000..7d9f2f0 --- /dev/null +++ b/at91lib/boards/theva-rev1/board_lowlevel.c @@ -0,0 +1,179 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \unit +/// +/// !Purpose +/// +/// Provides the low-level initialization function that gets called on chip +/// startup. +/// +/// !Usage +/// +/// LowLevelInit() is called in #board_cstartup.S#. +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "board.h" +#include "board_memories.h" +#include +#include + +//------------------------------------------------------------------------------ +// Internal definitions +//------------------------------------------------------------------------------ +// Startup time of main oscillator (in number of slow clock ticks). +#define BOARD_OSCOUNT (AT91C_CKGR_OSCOUNT & (0x40 << 8)) + +// USB PLL divisor value to obtain a 48MHz clock. +#define BOARD_USBDIV AT91C_CKGR_USBDIV_1 + +// PLL frequency range. +#define BOARD_CKGR_PLL AT91C_CKGR_OUT_0 + +// PLL startup time (in number of slow clock ticks). +#define BOARD_PLLCOUNT (16 << 8) + +// PLL MUL value. +#define BOARD_MUL (AT91C_CKGR_MUL & (72 << 16)) + +// PLL DIV value. +#define BOARD_DIV (AT91C_CKGR_DIV & 14) + +// Master clock prescaler value. +#define BOARD_PRESCALER AT91C_PMC_PRES_CLK_2 + +//------------------------------------------------------------------------------ +// Internal functions +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +/// Default spurious interrupt handler. Infinite loop. +//------------------------------------------------------------------------------ +void defaultSpuriousHandler( void ) +{ + TRACE_ERROR( "Invalid Interrupt\n\r"); + while (1); +} + +//------------------------------------------------------------------------------ +/// Default handler for fast interrupt requests. Infinite loop. +//------------------------------------------------------------------------------ +void defaultFiqHandler( void ) +{ + TRACE_ERROR( "Invalid Interrupt\n\r"); + while (1); +} + +//------------------------------------------------------------------------------ +/// Default handler for standard interrupt requests. Infinite loop. +//------------------------------------------------------------------------------ +void defaultIrqHandler( void ) +{ + TRACE_ERROR( "Invalid Interrupt\n\r"); + while (1); +} + + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Performs the low-level initialization of the chip. This includes EFC, master +/// clock, AIC & watchdog configuration, as well as memory remapping. +//------------------------------------------------------------------------------ +void LowLevelInit( void ) +{ + unsigned char i; + + BOARD_ConfigureFlash48MHz(); + +//#if !defined(sdram) + /* Initialize main oscillator + ****************************/ + AT91C_BASE_PMC->PMC_MOR = BOARD_OSCOUNT | AT91C_CKGR_MOSCEN; + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS)); + + /* Initialize PLL at 96MHz (96.109) and USB clock to 48MHz */ + AT91C_BASE_PMC->PMC_PLLR = BOARD_USBDIV | BOARD_CKGR_PLL | BOARD_PLLCOUNT + | BOARD_MUL | BOARD_DIV; + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK)); + + /* Wait for the master clock if it was already initialized */ + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)); + + /* Switch to fast clock + **********************/ + /* Switch to slow clock + prescaler */ + AT91C_BASE_PMC->PMC_MCKR = BOARD_PRESCALER; + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)); + + /* Switch to fast clock + prescaler */ + AT91C_BASE_PMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK; + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)); +//#endif //#if !defined(sdram) + + /* Initialize AIC + ****************/ + AT91C_BASE_AIC->AIC_IDCR = 0xFFFFFFFF; + AT91C_BASE_AIC->AIC_SVR[0] = (unsigned int) defaultFiqHandler; + for (i = 1; i < 31; i++) { + + AT91C_BASE_AIC->AIC_SVR[i] = (unsigned int) defaultIrqHandler; + } + AT91C_BASE_AIC->AIC_SPU = (unsigned int) defaultSpuriousHandler; + + // Unstack nested interrupts + for (i = 0; i < 8 ; i++) { + + AT91C_BASE_AIC->AIC_EOICR = 0; + } + + // Enable Debug mode + AT91C_BASE_AIC->AIC_DCR = AT91C_AIC_DCR_PROT; + + /* Watchdog initialization + *************************/ + AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS; + + /* Remap + *******/ + BOARD_RemapRam(); + + // Disable RTT and PIT interrupts (potential problem when program A + // configures RTT, then program B wants to use PIT only, interrupts + // from the RTT will still occur since they both use AT91C_ID_SYS) + AT91C_BASE_RTTC->RTTC_RTMR &= ~(AT91C_RTTC_ALMIEN | AT91C_RTTC_RTTINCIEN); + AT91C_BASE_PITC->PITC_PIMR &= ~AT91C_PITC_PITIEN; +} + diff --git a/at91lib/boards/theva-rev1/board_lowlevel.h b/at91lib/boards/theva-rev1/board_lowlevel.h new file mode 100644 index 0000000..b05e12d --- /dev/null +++ b/at91lib/boards/theva-rev1/board_lowlevel.h @@ -0,0 +1,49 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \unit +/// +/// !!!Purpose +/// +/// Collection of methods for lowlevel. +/// +//------------------------------------------------------------------------------ + +#ifndef BOARD_LOWLEVEL_H +#define BOARD_LOWLEVEL_H + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ +extern void LowLevelInit(void); + +#endif // BOARD_LOWLEVEL_H + + diff --git a/at91lib/boards/theva-rev1/board_memories.c b/at91lib/boards/theva-rev1/board_memories.c new file mode 100644 index 0000000..46e53b8 --- /dev/null +++ b/at91lib/boards/theva-rev1/board_memories.c @@ -0,0 +1,135 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "board_memories.h" +#include "board.h" +#include + +/* + Macros: + READ - Reads a register value. Useful to add trace information to read + accesses. + WRITE - Writes data in a register. Useful to add trace information to + write accesses. +*/ +#define READ(peripheral, register) (peripheral->register) +#define WRITE(peripheral, register, value) (peripheral->register = value) + +//------------------------------------------------------------------------------ +// Internal definitions +//------------------------------------------------------------------------------ +/* + Constants: Remap types + BOARD_FLASH - Flash is mirrored in the remap zone. + BOARD_RAM - RAM is mirrored in the remap zone. +*/ +#define BOARD_FLASH 0 +#define BOARD_RAM 1 + +//------------------------------------------------------------------------------ +// Internal function +//------------------------------------------------------------------------------ +/* + Function: BOARD_GetRemap + Returns the current remap (see ). +*/ +static unsigned char BOARD_GetRemap( void ) +{ + volatile unsigned int *remap = (volatile unsigned int *) 0; + volatile unsigned int *ram = (volatile unsigned int *) AT91C_ISRAM; + + // Try to write in 0 and see if this affects the RAM + unsigned int temp = *ram; + *ram = temp + 1; + if (*remap == *ram) { + + *ram = temp; + return BOARD_RAM; + } + else { + + *ram = temp; + return BOARD_FLASH; + } +} + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ +/* + Function: BOARD_RemapFlash + Changes the mapping of the chip so that the remap area mirrors the + internal flash. +*/ +void BOARD_RemapFlash( void ) +{ + if (BOARD_GetRemap() != BOARD_FLASH) { + + AT91C_BASE_MC->MC_RCR = AT91C_MC_RCB; + } +} + +/* + Function: BOARD_RemapRam + Changes the mapping of the chip so that the remap area mirrors the + internal RAM. +*/ +void BOARD_RemapRam( void ) +{ + if (BOARD_GetRemap() != BOARD_RAM) { + + AT91C_BASE_MC->MC_RCR = AT91C_MC_RCB; + } +} + +//------------------------------------------------------------------------------ +/// Configures a list of AT91S_EFC instances. +/// \param list Pointer to a list of AT91S_EFC instances. +/// \param size Size of the AT91S_EFC list. +/// \param numWaitStates Number of state cycles value for the EFC. +//------------------------------------------------------------------------------ +void BOARD_ConfigureFlash48MHz(void) +{ + /* Set flash wait states in the EFC + **********************************/ + /* 48MHz = 1 wait state */ +#if defined(at91sam7se512) + AT91C_BASE_EFC0->EFC_FMR = AT91C_MC_FWS_2FWS; + AT91C_BASE_EFC1->EFC_FMR = AT91C_MC_FWS_2FWS; +#elif defined(at91sam7se32) || defined(at91sam7se256) + AT91C_BASE_EFC->EFC_FMR = AT91C_MC_FWS_2FWS; +#else + #error No chip definition ? +#endif +} + diff --git a/at91lib/boards/theva-rev1/board_memories.h b/at91lib/boards/theva-rev1/board_memories.h new file mode 100644 index 0000000..e70d347 --- /dev/null +++ b/at91lib/boards/theva-rev1/board_memories.h @@ -0,0 +1,70 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/* + Title: Memories + + About: Purpose + Methods for initializing memories (SDRAM, etc.) and remapping. + + About: Usage + 1 - Remap the Flash at address 0 using . + 2 - Remap the internal RAM at address 0 using . + 3 - Initialize an external SDRAM using . +*/ + +#ifndef BOARD_MEMORIES_H +#define BOARD_MEMORIES_H + + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +/// Alias for BOARD_ConfigureSdram48MHz() function +#define BOARD_ConfigureSdram48MHz BOARD_ConfigureSdram + +/// Alias for BOARD_ConfigureNandFlash48MHz() function +#define BOARD_ConfigureNandFlash48MHz BOARD_ConfigureNandFlash + +/// Alias for BOARD_ConfigureNorFlash48MHz() function +#define BOARD_ConfigureNorFlash48MHz BOARD_ConfigureNorFlash + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +extern void BOARD_RemapFlash(void); + +extern void BOARD_RemapRam(void); + +extern void BOARD_ConfigureFlash48MHz(void); + +#endif //#ifndef BOARD_MEMORIES_H + diff --git a/at91lib/peripherals/aic/aic.c b/at91lib/peripherals/aic/aic.c new file mode 100644 index 0000000..4ff52c2 --- /dev/null +++ b/at91lib/peripherals/aic/aic.c @@ -0,0 +1,87 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "aic.h" +#include + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Configures an interrupt in the AIC. The interrupt is identified by its +/// source (AT91C_ID_xxx) and is configured to use the specified mode and +/// interrupt handler function. Mode is the value that will be put in AIC_SMRx +/// and the function address will be set in AIC_SVRx. +/// The interrupt is disabled before configuration, so it is useless +/// to do it before calling this function. When AIC_ConfigureIT returns, the +/// interrupt will always be disabled and cleared; it must be enabled by a +/// call to AIC_EnableIT(). +/// \param source Interrupt source to configure. +/// \param mode Triggering mode and priority of the interrupt. +/// \param handler Interrupt handler function. +//------------------------------------------------------------------------------ +void AIC_ConfigureIT( + unsigned int source, + unsigned int mode, + void (*handler)(void)) +{ + // Disable the interrupt first + AT91C_BASE_AIC->AIC_IDCR = 1 << source; + + // Configure mode and handler + AT91C_BASE_AIC->AIC_SMR[source] = mode; + AT91C_BASE_AIC->AIC_SVR[source] = (unsigned int) handler; + + // Clear interrupt + AT91C_BASE_AIC->AIC_ICCR = 1 << source; +} + +//------------------------------------------------------------------------------ +/// Enables interrupts coming from the given (unique) source (AT91C_ID_xxx). +/// \param source Interrupt source to enable. +//------------------------------------------------------------------------------ +void AIC_EnableIT(unsigned int source) +{ + AT91C_BASE_AIC->AIC_IECR = 1 << source; +} + +//------------------------------------------------------------------------------ +/// Disables interrupts coming from the given (unique) source (AT91C_ID_xxx). +/// \param source Interrupt source to enable. +//------------------------------------------------------------------------------ +void AIC_DisableIT(unsigned int source) +{ + AT91C_BASE_AIC->AIC_IDCR = 1 << source; +} + diff --git a/at91lib/peripherals/aic/aic.h b/at91lib/peripherals/aic/aic.h new file mode 100644 index 0000000..bddf787 --- /dev/null +++ b/at91lib/peripherals/aic/aic.h @@ -0,0 +1,79 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \unit +/// +/// !Purpose +/// +/// Methods and definitions for configuring interrupts using the Advanced +/// Interrupt Controller (AIC). +/// +/// !Usage +/// +/// -# Configure an interrupt source using AIC_ConfigureIT +/// -# Enable or disable interrupt generation of a particular source with +/// AIC_EnableIT and AIC_DisableIT. +/// +/// \note Most of the time, peripheral interrupts must be also configured +/// inside the peripheral itself. +//------------------------------------------------------------------------------ + +#ifndef AIC_H +#define AIC_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +#ifndef AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL + /// Interrupt is internal and uses a logical 1 level. + #define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE +#endif + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ + +extern void AIC_ConfigureIT(unsigned int source, + unsigned int mode, + void (*handler)( void )); + +extern void AIC_EnableIT(unsigned int source); + +extern void AIC_DisableIT(unsigned int source); + +#endif //#ifndef AIC_H + diff --git a/at91lib/peripherals/cp15/cp15.c b/at91lib/peripherals/cp15/cp15.c new file mode 100644 index 0000000..17a1f70 --- /dev/null +++ b/at91lib/peripherals/cp15/cp15.c @@ -0,0 +1,268 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//----------------------------------------------------------------------------- +// Headers +//----------------------------------------------------------------------------- + +#include + +#ifdef CP15_PRESENT + +#include +#include "cp15.h" + +#if defined(__ICCARM__) +#include +#endif + + +//----------------------------------------------------------------------------- +// Macros +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +// Defines +//----------------------------------------------------------------------------- +/* +#define CP15_RR_BIT 14 // RR bit Replacement strategy for ICache and DCache: + // 0 = Random replacement + // 1 = Round-robin replacement. + +#define CP15_V_BIT 13 // V bit Location of exception vectors: + // 0 = Normal exception vectors selected address range = 0x0000 0000 to 0x0000 001C + // 1 = High exception vect selected, address range = 0xFFFF 0000 to 0xFFFF 001C +*/ +#define CP15_I_BIT 12 // I bit ICache enable/disable: + // 0 = ICache disabled + // 1 = ICache enabled +/* +#define CP15_R_BIT 9 // R bit ROM protection + +#define CP15_S_BIT 8 // S bit System protection + +#define CP15_B_BIT 7 // B bit Endianness: + // 0 = Little-endian operation + // 1 = Big-endian operation. +*/ +#define CP15_C_BIT 2 // C bit DCache enable/disable: + // 0 = Cache disabled + // 1 = Cache enabled +/* +#define CP15_A_BIT 1 // A bit Alignment fault enable/disable: + // 0 = Data address alignment fault checking disabled + // 1 = Data address alignment fault checking enabled +*/ +#define CP15_M_BIT 0 // M bit MMU enable/disable: 0 = disabled 1 = enabled. + // 0 = disabled + // 1 = enabled + + +//----------------------------------------------------------------------------- +// Global functions +//----------------------------------------------------------------------------- + +//------------------------------------------------------------------------------ +/// Check Instruction Cache +/// \return 0 if I_Cache disable, 1 if I_Cache enable +//------------------------------------------------------------------------------ +unsigned int CP15_Is_I_CacheEnabled(void) +{ + unsigned int control; + + control = _readControlRegister(); + return ((control & (1 << CP15_I_BIT)) != 0); +} + +//------------------------------------------------------------------------------ +/// Enable Instruction Cache +//------------------------------------------------------------------------------ +void CP15_Enable_I_Cache(void) +{ + unsigned int control; + + control = _readControlRegister(); + + // Check if cache is disabled + if ((control & (1 << CP15_I_BIT)) == 0) { + + control |= (1 << CP15_I_BIT); + _writeControlRegister(control); + TRACE_INFO("I cache enabled.\n\r"); + } +#if !defined(OP_BOOTSTRAP_on) + else { + + TRACE_INFO("I cache is already enabled.\n\r"); + } +#endif +} + +//------------------------------------------------------------------------------ +/// Disable Instruction Cache +//------------------------------------------------------------------------------ +void CP15_Disable_I_Cache(void) +{ + unsigned int control; + + control = _readControlRegister(); + + // Check if cache is enabled + if ((control & (1 << CP15_I_BIT)) != 0) { + + control &= ~(1 << CP15_I_BIT); + _writeControlRegister(control); + TRACE_INFO("I cache disabled.\n\r"); + } + else { + + TRACE_INFO("I cache is already disabled.\n\r"); + } +} + +//------------------------------------------------------------------------------ +/// Check MMU +/// \return 0 if MMU disable, 1 if MMU enable +//------------------------------------------------------------------------------ +unsigned int CP15_Is_MMUEnabled(void) +{ + unsigned int control; + + control = _readControlRegister(); + return ((control & (1 << CP15_M_BIT)) != 0); +} + +//------------------------------------------------------------------------------ +/// Enable MMU +//------------------------------------------------------------------------------ +void CP15_EnableMMU(void) +{ + unsigned int control; + + control = _readControlRegister(); + + // Check if MMU is disabled + if ((control & (1 << CP15_M_BIT)) == 0) { + + control |= (1 << CP15_M_BIT); + _writeControlRegister(control); + TRACE_INFO("MMU enabled.\n\r"); + } + else { + + TRACE_INFO("MMU is already enabled.\n\r"); + } +} + +//------------------------------------------------------------------------------ +/// Disable MMU +//------------------------------------------------------------------------------ +void CP15_DisableMMU(void) +{ + unsigned int control; + + control = _readControlRegister(); + + // Check if MMU is enabled + if ((control & (1 << CP15_M_BIT)) != 0) { + + control &= ~(1 << CP15_M_BIT); + control &= ~(1 << CP15_C_BIT); + _writeControlRegister(control); + TRACE_INFO("MMU disabled.\n\r"); + } + else { + + TRACE_INFO("MMU is already disabled.\n\r"); + } +} + +//------------------------------------------------------------------------------ +/// Check D_Cache +/// \return 0 if D_Cache disable, 1 if D_Cache enable (with MMU of course) +//------------------------------------------------------------------------------ +unsigned int CP15_Is_DCacheEnabled(void) +{ + unsigned int control; + + control = _readControlRegister(); + return ((control & ((1 << CP15_C_BIT)||(1 << CP15_M_BIT))) != 0); +} + +//------------------------------------------------------------------------------ +/// Enable Data Cache +//------------------------------------------------------------------------------ +void CP15_Enable_D_Cache(void) +{ + unsigned int control; + + control = _readControlRegister(); + + if( !CP15_Is_MMUEnabled() ) { + TRACE_ERROR("Do nothing: MMU not enabled\n\r"); + } + else { + // Check if cache is disabled + if ((control & (1 << CP15_C_BIT)) == 0) { + + control |= (1 << CP15_C_BIT); + _writeControlRegister(control); + TRACE_INFO("D cache enabled.\n\r"); + } + else { + + TRACE_INFO("D cache is already enabled.\n\r"); + } + } +} + +//------------------------------------------------------------------------------ +/// Disable Data Cache +//------------------------------------------------------------------------------ +void CP15_Disable_D_Cache(void) +{ + unsigned int control; + + control = _readControlRegister(); + + // Check if cache is enabled + if ((control & (1 << CP15_C_BIT)) != 0) { + + control &= ~(1 << CP15_C_BIT); + _writeControlRegister(control); + TRACE_INFO("D cache disabled.\n\r"); + } + else { + + TRACE_INFO("D cache is already disabled.\n\r"); + } +} + +#endif // CP15_PRESENT + diff --git a/at91lib/peripherals/cp15/cp15.h b/at91lib/peripherals/cp15/cp15.h new file mode 100644 index 0000000..ddaaeb6 --- /dev/null +++ b/at91lib/peripherals/cp15/cp15.h @@ -0,0 +1,84 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \unit +/// +/// !Purpose +/// +/// Methods to manage the Coprocessor 15. Coprocessor 15, or System Control +/// Coprocessor CP15, is used to configure and control all the items in the +/// list below: +/// ARM core +/// Caches (ICache, DCache and write buffer) +/// TCM +/// MMU +/// Other system options +/// +/// !Usage +/// +/// -# Enable or disable D cache with Enable_D_Cache and Disable_D_Cache +/// -# Enable or disable I cache with Enable_I_Cache and Disable_I_Cache +/// +//------------------------------------------------------------------------------ + +#ifndef _CP15_H +#define _CP15_H + +#ifdef CP15_PRESENT + +//----------------------------------------------------------------------------- +// Exported functions +//----------------------------------------------------------------------------- +extern void CP15_Enable_I_Cache(void); +extern unsigned int CP15_Is_I_CacheEnabled(void); +extern void CP15_Enable_I_Cache(void); +extern void CP15_Disable_I_Cache(void); +extern unsigned int CP15_Is_MMUEnabled(void); +extern void CP15_EnableMMU(void); +extern void CP15_DisableMMU(void); +extern unsigned int CP15_Is_DCacheEnabled(void); +extern void CP15_Enable_D_Cache(void); +extern void CP15_Disable_D_Cache(void); + +//----------------------------------------------------------------------------- +// External functions defined in cp15.S +//----------------------------------------------------------------------------- +extern unsigned int _readControlRegister(void); +extern void _writeControlRegister(unsigned int value); +extern void _waitForInterrupt(void); +extern void _writeTTB(unsigned int value); +extern void _writeDomain(unsigned int value); +extern void _writeITLBLockdown(unsigned int value); +extern void _prefetchICacheLine(unsigned int value); + +#endif // CP15_PRESENT + +#endif // #ifndef _CP15_H + diff --git a/at91lib/peripherals/cp15/cp15_asm.S b/at91lib/peripherals/cp15/cp15_asm.S new file mode 100644 index 0000000..00ef47d --- /dev/null +++ b/at91lib/peripherals/cp15/cp15_asm.S @@ -0,0 +1,138 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#define __ASSEMBLY__ +#include "board.h" + +#ifdef CP15_PRESENT + +//------------------------------------------------------------------------------ +/// Functions to access CP15 coprocessor register +//------------------------------------------------------------------------------ + + .global _readControlRegister + .global _writeControlRegister + .global _waitForInterrupt + .global _writeTTB + .global _writeDomain + .global _writeITLBLockdown + .global _prefetchICacheLine + +//------------------------------------------------------------------------------ +/// Control Register c1 +/// Register c1 is the Control Register for the ARM926EJ-S processor. +/// This register specifies the configuration used to enable and disable the +/// caches and MMU. It is recommended that you access this register using a +/// read-modify-write sequence. +//------------------------------------------------------------------------------ +// CP15 Read Control Register +_readControlRegister: + mov r0, #0 + mrc p15, 0, r0, c1, c0, 0 + bx lr + +// CP15 Write Control Register +_writeControlRegister: + mcr p15, 0, r0, c1, c0, 0 + bx lr + +//------------------------------------------------------------------------------ +/// CP15 Wait For Interrupt operation +/// The purpose of the Wait For Interrupt operation is to put the processor in +/// to a low power state. +/// This puts the processor into a low-power state and stops it executing more +/// instructions until an interrupt, or debug request occurs, regardless of +/// whether the interrupts are disabled by the masks in the CPSR. +/// When an interrupt does occur, the MCR instruction completes and the IRQ or +/// FIQ handler is entered as normal. The return link in r14_irq or r14_fiq +/// contains the address of the MCR instruction plus 8, so that the normal +/// instruction used for interrupt return (SUBS PC,R14,#4) returns to the +/// instruction following the MCR. +/// Wait For Interrupt : MCR p15, 0, , c7, c0, 4 +//------------------------------------------------------------------------------ +_waitForInterrupt: + mov r0, #0 + mcr p15, 0, r0, c7, c0, 4 + bx lr + +//------------------------------------------------------------------------------ +/// CP15 Translation Table Base Register c2 +/// Register c2 is the Translation Table Base Register (TTBR), for the base +/// address of the first-level translation table. +/// Reading from c2 returns the pointer to the currently active first-level +/// translation table in bits [31:14] and an Unpredictable value in bits [13:0]. +/// Writing to register c2 updates the pointer to the first-level translation +/// table from the value in bits [31:14] of the written value. Bits [13:0] +/// Should Be Zero. +/// You can use the following instructions to access the TTBR: +/// Read TTBR : MRC p15, 0, , c2, c0, 0 +/// Write TTBR : MCR p15, 0, , c2, c0, 0 +//------------------------------------------------------------------------------ +_writeTTB: + MCR p15, 0, r0, c2, c0, 0 + bx lr + +//------------------------------------------------------------------------------ +/// Domain Access Control Register c3 +/// Read domain access permissions : MRC p15, 0, , c3, c0, 0 +/// Write domain access permissions : MCR p15, 0, , c3, c0, 0 +//------------------------------------------------------------------------------ +_writeDomain: + MCR p15, 0, r0, c3, c0, 0 + bx lr + +//------------------------------------------------------------------------------ +/// TLB Lockdown Register c10 +/// The TLB Lockdown Register controls where hardware page table walks place the +/// TLB entry, in the set associative region or the lockdown region of the TLB, +/// and if in the lockdown region, which entry is written. The lockdown region +/// of the TLB contains eight entries. See TLB structure for a description of +/// the structure of the TLB. +/// Read data TLB lockdown victim : MRC p15,0,,c10,c0,0 +/// Write data TLB lockdown victim : MCR p15,0,,c10,c0,0 +//------------------------------------------------------------------------------ +_writeITLBLockdown: + MCR p15, 0, r0, c10, c0, 0 + bx lr + +//------------------------------------------------------------------------------ +/// Prefetch ICache line +/// Performs an ICache lookup of the specified modified virtual address. +/// If the cache misses, and the region is cacheable, a linefill is performed. +/// Prefetch ICache line (MVA): MCR p15, 0, , c7, c13, 1 +//------------------------------------------------------------------------------ +_prefetchICacheLine: + MCR p15, 0, r0, c7, c13, 1 + bx lr +#endif + diff --git a/at91lib/peripherals/dbgu/dbgu.c b/at91lib/peripherals/dbgu/dbgu.c new file mode 100644 index 0000000..2034730 --- /dev/null +++ b/at91lib/peripherals/dbgu/dbgu.c @@ -0,0 +1,174 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "dbgu.h" +#include +#include + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +/// Initializes the DBGU with the given parameters, and enables both the +/// transmitter and the receiver. The mode parameter contains the value of the +/// DBGU_MR register. +/// Value DBGU_STANDARD can be used for mode to get the most common configuration +/// (i.e. aysnchronous, 8bits, no parity, 1 stop bit, no flow control). +/// \param mode Operating mode to configure. +/// \param baudrate Desired baudrate (e.g. 115200). +/// \param mck Frequency of the system master clock in Hz. +//------------------------------------------------------------------------------ +void DBGU_Configure( + unsigned int mode, + unsigned int baudrate, + unsigned int mck) +{ + // Reset & disable receiver and transmitter, disable interrupts + AT91C_BASE_DBGU->DBGU_CR = AT91C_US_RSTRX | AT91C_US_RSTTX; + AT91C_BASE_DBGU->DBGU_IDR = 0xFFFFFFFF; + + // Configure baud rate + AT91C_BASE_DBGU->DBGU_BRGR = mck / (baudrate * 16); + + // Configure mode register + AT91C_BASE_DBGU->DBGU_MR = mode; + + // Disable DMA channel + AT91C_BASE_DBGU->DBGU_PTCR = AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS; + + // Enable receiver and transmitter + AT91C_BASE_DBGU->DBGU_CR = AT91C_US_RXEN | AT91C_US_TXEN; +} + +//------------------------------------------------------------------------------ +/// Outputs a character on the DBGU line. +/// \note This function is synchronous (i.e. uses polling). +/// \param c Character to send. +//------------------------------------------------------------------------------ +void DBGU_PutChar(unsigned char c) +{ + // Wait for the transmitter to be ready + while ((AT91C_BASE_DBGU->DBGU_CSR & AT91C_US_TXEMPTY) == 0); + + // Send character + AT91C_BASE_DBGU->DBGU_THR = c; + + // Wait for the transfer to complete + while ((AT91C_BASE_DBGU->DBGU_CSR & AT91C_US_TXEMPTY) == 0); +} + +//------------------------------------------------------------------------------ +/// Return 1 if a character can be read in DBGU +//------------------------------------------------------------------------------ +unsigned int DBGU_IsRxReady() +{ + return (AT91C_BASE_DBGU->DBGU_CSR & AT91C_US_RXRDY); +} + +//------------------------------------------------------------------------------ +/// Reads and returns a character from the DBGU. +/// \note This function is synchronous (i.e. uses polling). +/// \return Character received. +//------------------------------------------------------------------------------ +unsigned char DBGU_GetChar(void) +{ + while ((AT91C_BASE_DBGU->DBGU_CSR & AT91C_US_RXRDY) == 0); + return AT91C_BASE_DBGU->DBGU_RHR; +} + +#ifndef NOFPUT +#include + +//------------------------------------------------------------------------------ +/// \exclude +/// Implementation of fputc using the DBGU as the standard output. Required +/// for printf(). +/// \param c Character to write. +/// \param pStream Output stream. +/// \param The character written if successful, or -1 if the output stream is +/// not stdout or stderr. +//------------------------------------------------------------------------------ +signed int fputc(signed int c, FILE *pStream) +{ + if ((pStream == stdout) || (pStream == stderr)) { + + DBGU_PutChar(c); + return c; + } + else { + + return EOF; + } +} + +//------------------------------------------------------------------------------ +/// \exclude +/// Implementation of fputs using the DBGU as the standard output. Required +/// for printf(). Does NOT currently use the PDC. +/// \param pStr String to write. +/// \param pStream Output stream. +/// \return Number of characters written if successful, or -1 if the output +/// stream is not stdout or stderr. +//------------------------------------------------------------------------------ +signed int fputs(const char *pStr, FILE *pStream) +{ + signed int num = 0; + + while (*pStr != 0) { + + if (fputc(*pStr, pStream) == -1) { + + return -1; + } + num++; + pStr++; + } + + return num; +} + +#undef putchar + +//------------------------------------------------------------------------------ +/// \exclude +/// Outputs a character on the DBGU. +/// \param c Character to output. +/// \return The character that was output. +//------------------------------------------------------------------------------ +signed int putchar(signed int c) +{ + return fputc(c, stdout); +} + +#endif //#ifndef NOFPUT + diff --git a/at91lib/peripherals/dbgu/dbgu.h b/at91lib/peripherals/dbgu/dbgu.h new file mode 100644 index 0000000..816f11d --- /dev/null +++ b/at91lib/peripherals/dbgu/dbgu.h @@ -0,0 +1,79 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \unit +/// +/// !Purpose +/// +/// This module provides definitions and functions for using the Debug Unit +/// (DBGU). +/// +/// It also overloads the fputc(), fputs() & putchar() functions so the printf() +/// method outputs its data on the DBGU. This behavior can be suppressed by +/// defining NOFPUT during compilation. +/// +/// !Usage +/// +/// -# Enable the DBGU pins (see pio & board.h). +/// -# Configure the DBGU using DBGU_Configure with the desired operating mode. +/// -# Send characters using DBGU_PutChar() or the printf() method. +/// -# Receive characters using DBGU_GetChar(). +/// +/// \note Unless specified, all the functions defined here operate synchronously; +/// i.e. they all wait the data is sent/received before returning. +//------------------------------------------------------------------------------ + +#ifndef DBGU_H +#define DBGU_H + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +/// Standard operating mode (asynchronous, 8bit, no parity, 1 stop bit) +#define DBGU_STANDARD AT91C_US_PAR_NONE + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ + +extern void DBGU_Configure( + unsigned int mode, + unsigned int baudrate, + unsigned int mck); + +extern unsigned char DBGU_GetChar(void); + +extern void DBGU_PutChar(unsigned char c); + +extern unsigned int DBGU_IsRxReady(void); + +#endif //#ifndef DBGU_H + diff --git a/at91lib/peripherals/pio/pio.c b/at91lib/peripherals/pio/pio.c new file mode 100644 index 0000000..5b21751 --- /dev/null +++ b/at91lib/peripherals/pio/pio.c @@ -0,0 +1,346 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "pio.h" +#include + +//------------------------------------------------------------------------------ +// Local Functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Configures one or more pin(s) of a PIO controller as being controlled by +/// peripheral A. Optionally, the corresponding internal pull-up(s) can be +/// enabled. +/// \param pio Pointer to a PIO controller. +/// \param mask Bitmask of one or more pin(s) to configure. +/// \param enablePullUp Indicates if the pin(s) internal pull-up shall be +/// configured. +//------------------------------------------------------------------------------ +static void PIO_SetPeripheralA( + AT91S_PIO *pio, + unsigned int mask, + unsigned char enablePullUp) +{ + // Disable interrupts on the pin(s) + pio->PIO_IDR = mask; + + // Enable the pull-up(s) if necessary + if (enablePullUp) { + + pio->PIO_PPUER = mask; + } + else { + + pio->PIO_PPUDR = mask; + } + + // Configure pin + pio->PIO_ASR = mask; + pio->PIO_PDR = mask; +} + +//------------------------------------------------------------------------------ +/// Configures one or more pin(s) of a PIO controller as being controlled by +/// peripheral B. Optionally, the corresponding internal pull-up(s) can be +/// enabled. +/// \param pio Pointer to a PIO controller. +/// \param mask Bitmask of one or more pin(s) to configure. +/// \param enablePullUp Indicates if the pin(s) internal pull-up shall be +/// configured. +//------------------------------------------------------------------------------ +static void PIO_SetPeripheralB( + AT91S_PIO *pio, + unsigned int mask, + unsigned char enablePullUp) +{ + // Disable interrupts on the pin(s) + pio->PIO_IDR = mask; + + // Enable the pull-up(s) if necessary + if (enablePullUp) { + + pio->PIO_PPUER = mask; + } + else { + + pio->PIO_PPUDR = mask; + } + + // Configure pin + pio->PIO_BSR = mask; + pio->PIO_PDR = mask; +} + +//------------------------------------------------------------------------------ +/// Configures one or more pin(s) or a PIO controller as inputs. Optionally, +/// the corresponding internal pull-up(s) and glitch filter(s) can be +/// enabled. +/// \param pio Pointer to a PIO controller. +/// \param mask Bitmask indicating which pin(s) to configure as input(s). +/// \param enablePullUp Indicates if the internal pull-up(s) must be enabled. +/// \param enableFilter Indicates if the glitch filter(s) must be enabled. +//------------------------------------------------------------------------------ +static void PIO_SetInput( + AT91S_PIO *pio, + unsigned int mask, + unsigned char enablePullUp, + unsigned char enableFilter) +{ + // Disable interrupts + pio->PIO_IDR = mask; + + // Enable pull-up(s) if necessary + if (enablePullUp) { + + pio->PIO_PPUER = mask; + } + else { + + pio->PIO_PPUDR = mask; + } + + // Enable filter(s) if necessary + if (enableFilter) { + + pio->PIO_IFER = mask; + } + else { + + pio->PIO_IFDR = mask; + } + + // Configure pin as input + pio->PIO_ODR = mask; + pio->PIO_PER = mask; +} + +//------------------------------------------------------------------------------ +/// Configures one or more pin(s) of a PIO controller as outputs, with the +/// given default value. Optionally, the multi-drive feature can be enabled +/// on the pin(s). +/// \param pio Pointer to a PIO controller. +/// \param mask Bitmask indicating which pin(s) to configure. +/// \param defaultValue Default level on the pin(s). +/// \param enableMultiDrive Indicates if the pin(s) shall be configured as +/// open-drain. +/// \param enablePullUp Indicates if the pin shall have its pull-up activated. +//------------------------------------------------------------------------------ +static void PIO_SetOutput( + AT91S_PIO *pio, + unsigned int mask, + unsigned char defaultValue, + unsigned char enableMultiDrive, + unsigned char enablePullUp) +{ + // Disable interrupts + pio->PIO_IDR = mask; + + // Enable pull-up(s) if necessary + if (enablePullUp) { + + pio->PIO_PPUER = mask; + } + else { + + pio->PIO_PPUDR = mask; + } + + // Enable multi-drive if necessary + if (enableMultiDrive) { + + pio->PIO_MDER = mask; + } + else { + + pio->PIO_MDDR = mask; + } + + // Set default value + if (defaultValue) { + + pio->PIO_SODR = mask; + } + else { + + pio->PIO_CODR = mask; + } + + // Configure pin(s) as output(s) + pio->PIO_OER = mask; + pio->PIO_PER = mask; +} + +//------------------------------------------------------------------------------ +// Global Functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Configures a list of Pin instances, each of which can either hold a single +/// pin or a group of pins, depending on the mask value; all pins are configured +/// by this function. The size of the array must also be provided and is easily +/// computed using PIO_LISTSIZE whenever its length is not known in advance. +/// \param list Pointer to a list of Pin instances. +/// \param size Size of the Pin list (calculated using PIO_LISTSIZE). +/// \return 1 if the pins have been configured properly; otherwise 0. +//------------------------------------------------------------------------------ +unsigned char PIO_Configure(const Pin *list, unsigned int size) +{ + // Configure pins + while (size > 0) { + + switch (list->type) { + + case PIO_PERIPH_A: + PIO_SetPeripheralA(list->pio, + list->mask, + (list->attribute & PIO_PULLUP) ? 1 : 0); + break; + + case PIO_PERIPH_B: + PIO_SetPeripheralB(list->pio, + list->mask, + (list->attribute & PIO_PULLUP) ? 1 : 0); + break; + + case PIO_INPUT: + AT91C_BASE_PMC->PMC_PCER = 1 << list->id; + PIO_SetInput(list->pio, + list->mask, + (list->attribute & PIO_PULLUP) ? 1 : 0, + (list->attribute & PIO_DEGLITCH)? 1 : 0); + break; + + case PIO_OUTPUT_0: + case PIO_OUTPUT_1: + PIO_SetOutput(list->pio, + list->mask, + (list->type == PIO_OUTPUT_1), + (list->attribute & PIO_OPENDRAIN) ? 1 : 0, + (list->attribute & PIO_PULLUP) ? 1 : 0); + break; + + default: return 0; + } + + list++; + size--; + } + + return 1; +} + +//------------------------------------------------------------------------------ +/// Sets a high output level on all the PIOs defined in the given Pin instance. +/// This has no immediate effects on PIOs that are not output, but the PIO +/// controller will memorize the value they are changed to outputs. +/// \param pin Pointer to a Pin instance describing one or more pins. +//------------------------------------------------------------------------------ +void PIO_Set(const Pin *pin) +{ + pin->pio->PIO_SODR = pin->mask; +} + +//------------------------------------------------------------------------------ +/// Sets a low output level on all the PIOs defined in the given Pin instance. +/// This has no immediate effects on PIOs that are not output, but the PIO +/// controller will memorize the value they are changed to outputs. +/// \param pin Pointer to a Pin instance describing one or more pins. +//------------------------------------------------------------------------------ +void PIO_Clear(const Pin *pin) +{ + pin->pio->PIO_CODR = pin->mask; +} + +//------------------------------------------------------------------------------ +/// Returns 1 if one or more PIO of the given Pin instance currently have a high +/// level; otherwise returns 0. This method returns the actual value that is +/// being read on the pin. To return the supposed output value of a pin, use +/// PIO_GetOutputDataStatus() instead. +/// \param pin Pointer to a Pin instance describing one or more pins. +/// \return 1 if the Pin instance contains at least one PIO that currently has +/// a high level; otherwise 0. +//------------------------------------------------------------------------------ +unsigned char PIO_Get(const Pin *pin) +{ + unsigned int reg; + if ((pin->type == PIO_OUTPUT_0) || (pin->type == PIO_OUTPUT_1)) { + + reg = pin->pio->PIO_ODSR; + } + else { + + reg = pin->pio->PIO_PDSR; + } + + if ((reg & pin->mask) == 0) { + + return 0; + } + else { + + return 1; + } +} + + +//------------------------------------------------------------------------------ +/// Returns 1 if one or more PIO of the given Pin are configured to output a +/// high level (even if they are not output). +/// To get the actual value of the pin, use PIO_Get() instead. +/// \param pin Pointer to a Pin instance describing one or more pins. +/// \return 1 if the Pin instance contains at least one PIO that is configured +/// to output a high level; otherwise 0. +//------------------------------------------------------------------------------ +unsigned char PIO_GetOutputDataStatus(const Pin *pin) +{ + if ((pin->pio->PIO_ODSR & pin->mask) == 0) { + + return 0; + } + else { + + return 1; + } +} + +//------------------------------------------------------------------------------ +/// Returns the value of ISR for the PIO controller of the pin. +/// Reading this register acknoledges all the ITs. +/// \param pin Pointer to a Pin instance describing one or more pins. +//------------------------------------------------------------------------------ +unsigned int PIO_GetISR(const Pin *pin) +{ + return (pin->pio->PIO_ISR); +} + diff --git a/at91lib/peripherals/pio/pio.h b/at91lib/peripherals/pio/pio.h new file mode 100644 index 0000000..69fe29d --- /dev/null +++ b/at91lib/peripherals/pio/pio.h @@ -0,0 +1,163 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \unit +/// +/// !!!Purpose +/// +/// This file provides a basic API for PIO configuration and usage of +/// user-controlled pins. Please refer to the board.h file for a list of +/// available pin definitions. +/// +/// !!!Usage +/// +/// -# Define a constant pin description array such as the following one, using +/// the existing definitions provided by the board.h file if possible: +/// \code +/// const Pin pPins[] = {PIN_USART0_TXD, PIN_USART0_RXD}; +/// \endcode +/// Alternatively, it is possible to add new pins by provided the full Pin +/// structure: +/// \code +/// // Pin instance to configure PA10 & PA11 as inputs with the internal +/// // pull-up enabled. +/// const Pin pPins = { +/// (1 << 10) | (1 << 11), +/// AT91C_BASE_PIOA, +/// AT91C_ID_PIOA, +/// PIO_INPUT, +/// PIO_PULLUP +/// }; +/// \endcode +/// -# Configure a pin array by calling PIO_Configure() with a pointer to the +/// array and its size (which is computed using the PIO_LISTSIZE macro). +/// -# Change and get the value of a user-controlled pin using the PIO_Set, +/// PIO_Clear and PIO_Get methods. +/// -# Get the level being currently output by a user-controlled pin configured +/// as an output using PIO_GetOutputDataStatus(). +//------------------------------------------------------------------------------ + +#ifndef PIO_H +#define PIO_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include + +//------------------------------------------------------------------------------ +// Global Definitions +//------------------------------------------------------------------------------ + +/// The pin is controlled by the associated signal of peripheral A. +#define PIO_PERIPH_A 0 +/// The pin is controlled by the associated signal of peripheral B. +#define PIO_PERIPH_B 1 +/// The pin is an input. +#define PIO_INPUT 2 +/// The pin is an output and has a default level of 0. +#define PIO_OUTPUT_0 3 +/// The pin is an output and has a default level of 1. +#define PIO_OUTPUT_1 4 + +/// Default pin configuration (no attribute). +#define PIO_DEFAULT (0 << 0) +/// The internal pin pull-up is active. +#define PIO_PULLUP (1 << 0) +/// The internal glitch filter is active. +#define PIO_DEGLITCH (1 << 1) +/// The pin is open-drain. +#define PIO_OPENDRAIN (1 << 2) + +//------------------------------------------------------------------------------ +// Global Macros +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Calculates the size of an array of Pin instances. The array must be defined +/// locally (i.e. not a pointer), otherwise the computation will not be correct. +/// \param pPins Local array of Pin instances. +/// \return Number of elements in array. +//------------------------------------------------------------------------------ +#define PIO_LISTSIZE(pPins) (sizeof(pPins) / sizeof(Pin)) + +//------------------------------------------------------------------------------ +// Global Types +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Describes the type and attribute of one PIO pin or a group of similar pins. +/// The #type# field can have the following values: +/// - PIO_PERIPH_A +/// - PIO_PERIPH_B +/// - PIO_OUTPUT_0 +/// - PIO_OUTPUT_1 +/// - PIO_INPUT +/// +/// The #attribute# field is a bitmask that can either be set to PIO_DEFAULt, +/// or combine (using bitwise OR '|') any number of the following constants: +/// - PIO_PULLUP +/// - PIO_DEGLITCH +/// - PIO_OPENDRAIN +//------------------------------------------------------------------------------ +typedef struct { + + /// Bitmask indicating which pin(s) to configure. + unsigned int mask; + /// Pointer to the PIO controller which has the pin(s). + AT91S_PIO *pio; + /// Peripheral ID of the PIO controller which has the pin(s). + unsigned char id; + /// Pin type. + unsigned char type; + /// Pin attribute. + unsigned char attribute; + +} Pin; + +//------------------------------------------------------------------------------ +// Global Functions +//------------------------------------------------------------------------------ + +extern unsigned char PIO_Configure(const Pin *list, unsigned int size); + +extern void PIO_Set(const Pin *pin); + +extern void PIO_Clear(const Pin *pin); + +extern unsigned char PIO_Get(const Pin *pin); + +extern unsigned int PIO_GetISR(const Pin *pin); + +extern unsigned char PIO_GetOutputDataStatus(const Pin *pin); + +#endif //#ifndef PIO_H + diff --git a/at91lib/peripherals/pio/pio_it.c b/at91lib/peripherals/pio/pio_it.c new file mode 100644 index 0000000..266feb0 --- /dev/null +++ b/at91lib/peripherals/pio/pio_it.c @@ -0,0 +1,395 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/// Disable traces for this file +#undef TRACE_LEVEL +#define TRACE_LEVEL 0 + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "pio_it.h" +#include "pio.h" +#include +#include +#include +#include + +//------------------------------------------------------------------------------ +// Local definitions +//------------------------------------------------------------------------------ + +/// \exclude +/// Maximum number of interrupt sources that can be defined. This +/// constant can be increased, but the current value is the smallest possible +/// that will be compatible with all existing projects. +#define MAX_INTERRUPT_SOURCES 7 + +//------------------------------------------------------------------------------ +// Local types +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \exclude +/// Describes a PIO interrupt source, including the PIO instance triggering the +/// interrupt and the associated interrupt handler. +//------------------------------------------------------------------------------ +typedef struct { + + /// Pointer to the source pin instance. + const Pin *pPin; + + /// Interrupt handler. + void (*handler)(const Pin *); + +} InterruptSource; + +//------------------------------------------------------------------------------ +// Local variables +//------------------------------------------------------------------------------ + +/// List of interrupt sources. +static InterruptSource pSources[MAX_INTERRUPT_SOURCES]; + +/// Number of currently defined interrupt sources. +static unsigned int numSources; + +//------------------------------------------------------------------------------ +// Local functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Handles all interrupts on the given PIO controller. +/// \param id PIO controller ID. +/// \param pPio PIO controller base address. +//------------------------------------------------------------------------------ +static void PioInterruptHandler(unsigned int id, AT91S_PIO *pPio) +{ + unsigned int status; + unsigned int i; + + // Read PIO controller status + status = pPio->PIO_ISR; + status &= pPio->PIO_IMR; + + // Check pending events + if (status != 0) { + + TRACE_DEBUG("PIO interrupt on PIO controller #%d\n\r", id); + + // Find triggering source + i = 0; + while (status != 0) { + + // There cannot be an unconfigured source enabled. + SANITY_CHECK(i < numSources); + + // Source is configured on the same controller + if (pSources[i].pPin->id == id) { + + // Source has PIOs whose statuses have changed + if ((status & pSources[i].pPin->mask) != 0) { + + TRACE_DEBUG("Interrupt source #%d triggered\n\r", i); + + pSources[i].handler(pSources[i].pPin); + status &= ~(pSources[i].pPin->mask); + } + } + i++; + } + } +} + +//------------------------------------------------------------------------------ +/// Generic PIO interrupt handler. Single entry point for interrupts coming +/// from any PIO controller (PIO A, B, C ...). Dispatches the interrupt to +/// the user-configured handlers. +//------------------------------------------------------------------------------ +static void InterruptHandler(void) +{ +#if defined(AT91C_ID_PIOA) + // Treat PIOA interrupts + PioInterruptHandler(AT91C_ID_PIOA, AT91C_BASE_PIOA); +#endif + +#if defined(AT91C_ID_PIOB) + // Treat PIOB interrupts + PioInterruptHandler(AT91C_ID_PIOB, AT91C_BASE_PIOB); +#endif + +#if defined(AT91C_ID_PIOC) + // Treat PIOC interrupts + PioInterruptHandler(AT91C_ID_PIOC, AT91C_BASE_PIOC); +#endif + +#if defined(AT91C_ID_PIOD) + // Treat PIOD interrupts + PioInterruptHandler(AT91C_ID_PIOD, AT91C_BASE_PIOD); +#endif + +#if defined(AT91C_ID_PIOE) + // Treat PIOE interrupts + PioInterruptHandler(AT91C_ID_PIOE, AT91C_BASE_PIOE); +#endif + +#if defined(AT91C_ID_PIOABCD) + // Treat PIOABCD interrupts + #if !defined(AT91C_ID_PIOA) + PioInterruptHandler(AT91C_ID_PIOABCD, AT91C_BASE_PIOA); + #endif + #if !defined(AT91C_ID_PIOB) + PioInterruptHandler(AT91C_ID_PIOABCD, AT91C_BASE_PIOB); + #endif + #if !defined(AT91C_ID_PIOC) + PioInterruptHandler(AT91C_ID_PIOABCD, AT91C_BASE_PIOC); + #endif + #if !defined(AT91C_ID_PIOD) + PioInterruptHandler(AT91C_ID_PIOABCD, AT91C_BASE_PIOD); + #endif +#endif + +#if defined(AT91C_ID_PIOABCDE) + // Treat PIOABCDE interrupts + #if !defined(AT91C_ID_PIOA) + PioInterruptHandler(AT91C_ID_PIOABCDE, AT91C_BASE_PIOA); + #endif + #if !defined(AT91C_ID_PIOB) + PioInterruptHandler(AT91C_ID_PIOABCDE, AT91C_BASE_PIOB); + #endif + #if !defined(AT91C_ID_PIOC) + PioInterruptHandler(AT91C_ID_PIOABCDE, AT91C_BASE_PIOC); + #endif + #if !defined(AT91C_ID_PIOD) + PioInterruptHandler(AT91C_ID_PIOABCDE, AT91C_BASE_PIOD); + #endif + #if !defined(AT91C_ID_PIOE) + PioInterruptHandler(AT91C_ID_PIOABCDE, AT91C_BASE_PIOE); + #endif +#endif + +#if defined(AT91C_ID_PIOCDE) + // Treat PIOCDE interrupts + #if !defined(AT91C_ID_PIOC) + PioInterruptHandler(AT91C_ID_PIOCDE, AT91C_BASE_PIOC); + #endif + #if !defined(AT91C_ID_PIOD) + PioInterruptHandler(AT91C_ID_PIOCDE, AT91C_BASE_PIOD); + #endif + #if !defined(AT91C_ID_PIOE) + PioInterruptHandler(AT91C_ID_PIOCDE, AT91C_BASE_PIOE); + #endif +#endif +} + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Initializes the PIO interrupt management logic. The desired priority of PIO +/// interrupts must be provided. Calling this function multiple times result in +/// the reset of currently configured interrupts. +/// \param priority PIO controller interrupts priority. +//------------------------------------------------------------------------------ +void PIO_InitializeInterrupts(unsigned int priority) +{ + TRACE_DEBUG("PIO_Initialize()\n\r"); + + SANITY_CHECK((priority & ~AT91C_AIC_PRIOR) == 0); + + // Reset sources + numSources = 0; + +#ifdef AT91C_ID_PIOA + // Configure PIO interrupt sources + TRACE_DEBUG("PIO_Initialize: Configuring PIOA\n\r"); + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOA; + AT91C_BASE_PIOA->PIO_ISR; + AT91C_BASE_PIOA->PIO_IDR = 0xFFFFFFFF; + AIC_ConfigureIT(AT91C_ID_PIOA, priority, InterruptHandler); + AIC_EnableIT(AT91C_ID_PIOA); +#endif + +#ifdef AT91C_ID_PIOB + TRACE_DEBUG("PIO_Initialize: Configuring PIOB\n\r"); + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOB; + AT91C_BASE_PIOB->PIO_ISR; + AT91C_BASE_PIOB->PIO_IDR = 0xFFFFFFFF; + AIC_ConfigureIT(AT91C_ID_PIOB, priority, InterruptHandler); + AIC_EnableIT(AT91C_ID_PIOB); +#endif + +#ifdef AT91C_ID_PIOC + TRACE_DEBUG("PIO_Initialize: Configuring PIOC\n\r"); + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOC; + AT91C_BASE_PIOC->PIO_ISR; + AT91C_BASE_PIOC->PIO_IDR = 0xFFFFFFFF; + AIC_ConfigureIT(AT91C_ID_PIOC, priority, InterruptHandler); + AIC_EnableIT(AT91C_ID_PIOC); +#endif + +#ifdef AT91C_ID_PIOD + TRACE_DEBUG("PIO_Initialize: Configuring PIOD\n\r"); + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOD; + AT91C_BASE_PIOC->PIO_ISR; + AT91C_BASE_PIOC->PIO_IDR = 0xFFFFFFFF; + AIC_ConfigureIT(AT91C_ID_PIOD, priority, InterruptHandler); + AIC_EnableIT(AT91C_ID_PIOD); +#endif + +#ifdef AT91C_ID_PIOE + TRACE_DEBUG("PIO_Initialize: Configuring PIOE\n\r"); + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOE; + AT91C_BASE_PIOC->PIO_ISR; + AT91C_BASE_PIOC->PIO_IDR = 0xFFFFFFFF; + AIC_ConfigureIT(AT91C_ID_PIOE, priority, InterruptHandler); + AIC_EnableIT(AT91C_ID_PIOE); +#endif + +#if defined(AT91C_ID_PIOABCD) + // Treat PIOABCD interrupts + #if !defined(AT91C_ID_PIOA) \ + && !defined(AT91C_ID_PIOB) \ + && !defined(AT91C_ID_PIOC) \ + && !defined(AT91C_ID_PIOD) + + TRACE_DEBUG("PIO_Initialize: Configuring PIOABCD\n\r"); + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOABCD; + AT91C_BASE_PIOA->PIO_ISR; + AT91C_BASE_PIOA->PIO_IDR = 0xFFFFFFFF; + AIC_ConfigureIT(AT91C_ID_PIOABCD, priority, InterruptHandler); + AIC_EnableIT(AT91C_ID_PIOABCD); + #endif +#endif + +#if defined(AT91C_ID_PIOABCDE) + // Treat PIOABCDE interrupts + #if !defined(AT91C_ID_PIOA) \ + && !defined(AT91C_ID_PIOB) \ + && !defined(AT91C_ID_PIOC) \ + && !defined(AT91C_ID_PIOD) \ + && !defined(AT91C_ID_PIOE) + + TRACE_DEBUG("PIO_Initialize: Configuring PIOABCDE\n\r"); + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOABCDE; + AT91C_BASE_PIOA->PIO_ISR; + AT91C_BASE_PIOA->PIO_IDR = 0xFFFFFFFF; + AIC_ConfigureIT(AT91C_ID_PIOABCDE, priority, InterruptHandler); + AIC_EnableIT(AT91C_ID_PIOABCDE); + #endif +#endif + +#if defined(AT91C_ID_PIOCDE) + // Treat PIOCDE interrupts + #if !defined(AT91C_ID_PIOC) \ + && !defined(AT91C_ID_PIOD) \ + && !defined(AT91C_ID_PIOE) + + TRACE_DEBUG("PIO_Initialize: Configuring PIOC\n\r"); + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOCDE; + AT91C_BASE_PIOC->PIO_ISR; + AT91C_BASE_PIOC->PIO_IDR = 0xFFFFFFFF; + AIC_ConfigureIT(AT91C_ID_PIOCDE, priority, InterruptHandler); + AIC_EnableIT(AT91C_ID_PIOCDE); + #endif +#endif +} + +//------------------------------------------------------------------------------ +/// Configures a PIO or a group of PIO to generate an interrupt on status +/// change. The provided interrupt handler will be called with the triggering +/// pin as its parameter (enabling different pin instances to share the same +/// handler). +/// \param pPin Pointer to a Pin instance. +/// \param handler Interrupt handler function pointer. +//------------------------------------------------------------------------------ +void PIO_ConfigureIt(const Pin *pPin, void (*handler)(const Pin *)) +{ + InterruptSource *pSource; + + TRACE_DEBUG("PIO_ConfigureIt()\n\r"); + + SANITY_CHECK(pPin); + ASSERT(numSources < MAX_INTERRUPT_SOURCES, + "-F- PIO_ConfigureIt: Increase MAX_INTERRUPT_SOURCES\n\r"); + + // Define new source + TRACE_DEBUG("PIO_ConfigureIt: Defining new source #%d.\n\r", numSources); + + pSource = &(pSources[numSources]); + pSource->pPin = pPin; + pSource->handler = handler; + numSources++; +} + +//------------------------------------------------------------------------------ +/// Enables the given interrupt source if it has been configured. The status +/// register of the corresponding PIO controller is cleared prior to enabling +/// the interrupt. +/// \param pPin Interrupt source to enable. +//------------------------------------------------------------------------------ +void PIO_EnableIt(const Pin *pPin) +{ + TRACE_DEBUG("PIO_EnableIt()\n\r"); + + SANITY_CHECK(pPin); + +#ifndef NOASSERT + unsigned int i = 0; + unsigned char found = 0; + while ((i < numSources) && !found) { + + if (pSources[i].pPin == pPin) { + + found = 1; + } + i++; + } + ASSERT(found, "-F- PIO_EnableIt: Interrupt source has not been configured\n\r"); +#endif + + pPin->pio->PIO_ISR; + pPin->pio->PIO_IER = pPin->mask; +} + +//------------------------------------------------------------------------------ +/// Disables a given interrupt source, with no added side effects. +/// \param pPin Interrupt source to disable. +//------------------------------------------------------------------------------ +void PIO_DisableIt(const Pin *pPin) +{ + SANITY_CHECK(pPin); + + TRACE_DEBUG("PIO_DisableIt()\n\r"); + + pPin->pio->PIO_IDR = pPin->mask; +} + diff --git a/at91lib/peripherals/pio/pio_it.h b/at91lib/peripherals/pio/pio_it.h new file mode 100644 index 0000000..0fcf7be --- /dev/null +++ b/at91lib/peripherals/pio/pio_it.h @@ -0,0 +1,83 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \unit +/// +/// !!!Purpose +/// +/// Configuration and handling of interrupts on PIO status changes. The API +/// provided here have several advantages over the traditional PIO interrupt +/// configuration approach: +/// - It is highly portable +/// - It automatically demultiplexes interrupts when multiples pins have been +/// configured on a single PIO controller +/// - It allows a group of pins to share the same interrupt +/// +/// However, it also has several minor drawbacks that may prevent from using it +/// in particular applications: +/// - It enables the clocks of all PIO controllers +/// - PIO controllers all share the same interrupt handler, which does the +/// demultiplexing and can be slower than direct configuration +/// - It reserves space for a fixed number of interrupts, which can be +/// increased by modifying the appropriate constant in pio_it.c. +/// +/// !!!Usage +/// +/// -# Initialize the PIO interrupt mechanism using PIO_InitializeInterrupts() +/// with the desired priority (0 ... 7). +/// -# Configure a status change interrupt on one or more pin(s) with +/// PIO_ConfigureIt(). +/// -# Enable & disable interrupts on pins using PIO_EnableIt() and +/// PIO_DisableIt(). +//------------------------------------------------------------------------------ + +#ifndef PIO_IT_H +#define PIO_IT_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "pio.h" + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ + +extern void PIO_InitializeInterrupts(unsigned int priority); + +extern void PIO_ConfigureIt(const Pin *pPin, void (*handler)(const Pin *)); + +extern void PIO_EnableIt(const Pin *pPin); + +extern void PIO_DisableIt(const Pin *pPin); + +#endif //#ifndef PIO_IT_H + diff --git a/at91lib/peripherals/pmc/pmc.c b/at91lib/peripherals/pmc/pmc.c new file mode 100644 index 0000000..136e401 --- /dev/null +++ b/at91lib/peripherals/pmc/pmc.c @@ -0,0 +1,186 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "pmc.h" +#include +#include +#include + +#ifdef CP15_PRESENT +#include +#endif + +#define MASK_STATUS 0x3FFFFFFC + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ + +#if defined(at91sam7l64) || defined(at91sam7l128) +//------------------------------------------------------------------------------ +/// Sets the fast wake-up inputs that can get the device out of Wait mode. +/// \param inputs Fast wake-up inputs to enable. +//------------------------------------------------------------------------------ +void PMC_SetFastWakeUpInputs(unsigned int inputs) +{ + SANITY_CHECK((inputs & ~0xFF) == 0); + AT91C_BASE_PMC->PMC_FSMR = inputs; +} + +#if !defined(__ICCARM__) +__attribute__ ((section (".ramfunc"))) // GCC +#endif +//------------------------------------------------------------------------------ +/// Disables the main oscillator, making the device enter Wait mode. +//------------------------------------------------------------------------------ +void PMC_DisableMainOscillatorForWaitMode(void) +{ + AT91C_BASE_PMC->PMC_MOR = 0x37 << 16; + while ((AT91C_BASE_PMC->PMC_MOR & AT91C_PMC_MAINSELS) != AT91C_PMC_MAINSELS); +} + +#endif + +#if defined(at91sam7l) +//------------------------------------------------------------------------------ +/// Disables the main oscillator when NOT running on it. +//------------------------------------------------------------------------------ +void PMC_DisableMainOscillator(void) +{ + AT91C_BASE_PMC->PMC_MOR = 0x37 << 16; + while ((AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MAINSELS) == AT91C_PMC_MAINSELS); +} +#endif + +//------------------------------------------------------------------------------ +/// Disables the processor clock +//------------------------------------------------------------------------------ +void PMC_DisableProcessorClock(void) +{ + AT91C_BASE_PMC->PMC_SCDR = AT91C_PMC_PCK; + while ((AT91C_BASE_PMC->PMC_SCSR & AT91C_PMC_PCK) != AT91C_PMC_PCK); +} + +//------------------------------------------------------------------------------ +/// Enables the clock of a peripheral. The peripheral ID (AT91C_ID_xxx) is used +/// to identify which peripheral is targetted. +/// Note that the ID must NOT be shifted (i.e. 1 << AT91C_ID_xxx). +/// \param id Peripheral ID (AT91C_ID_xxx). +//------------------------------------------------------------------------------ +void PMC_EnablePeripheral(unsigned int id) +{ + SANITY_CHECK(id < 32); + + if ((AT91C_BASE_PMC->PMC_PCSR & (1 << id)) == (1 << id)) { + + TRACE_INFO("PMC_EnablePeripheral: clock of peripheral" + " %u is already enabled\n\r", + id); + } + else { + + AT91C_BASE_PMC->PMC_PCER = 1 << id; + } +} + +//------------------------------------------------------------------------------ +/// Disables the clock of a peripheral. The peripheral ID (AT91C_ID_xxx) is used +/// to identify which peripheral is targetted. +/// Note that the ID must NOT be shifted (i.e. 1 << AT91C_ID_xxx). +/// \param id Peripheral ID (AT91C_ID_xxx). +//------------------------------------------------------------------------------ +void PMC_DisablePeripheral(unsigned int id) +{ + SANITY_CHECK(id < 32); + + if ((AT91C_BASE_PMC->PMC_PCSR & (1 << id)) != (1 << id)) { + + TRACE_INFO("PMC_DisablePeripheral: clock of peripheral" + " %u is not enabled\n\r", + id); + } + else { + + AT91C_BASE_PMC->PMC_PCDR = 1 << id; + } +} + +//------------------------------------------------------------------------------ +/// Enable all the periph clock via PMC +/// (Becareful of the last 2 bits, it is not periph clock) +//------------------------------------------------------------------------------ +void PMC_EnableAllPeripherals(void) +{ + AT91C_BASE_PMC->PMC_PCER = MASK_STATUS; + while( (AT91C_BASE_PMC->PMC_PCSR & MASK_STATUS) != MASK_STATUS); + TRACE_INFO("Enable all periph clocks\n\r"); +} + +//------------------------------------------------------------------------------ +/// Disable all the periph clock via PMC +/// (Becareful of the last 2 bits, it is not periph clock) +//------------------------------------------------------------------------------ +void PMC_DisableAllPeripherals(void) +{ + AT91C_BASE_PMC->PMC_PCDR = MASK_STATUS; + while((AT91C_BASE_PMC->PMC_PCSR & MASK_STATUS) != 0); + TRACE_INFO("Disable all periph clocks\n\r"); +} + +//----------------------------------------------------------------------------- +/// Get Periph Status +//----------------------------------------------------------------------------- +unsigned int PMC_IsAllPeriphEnabled(void) +{ + return (AT91C_BASE_PMC->PMC_PCSR == MASK_STATUS); +} + +//----------------------------------------------------------------------------- +/// Get Periph Status +//----------------------------------------------------------------------------- +unsigned int PMC_IsPeriphEnabled(unsigned int id) +{ + return (AT91C_BASE_PMC->PMC_PCSR & (1 << id)); +} +//------------------------------------------------------------------------------ +/// Put the CPU in Idle Mode for lower consumption +//------------------------------------------------------------------------------ +void PMC_CPUInIdleMode(void) +{ + PMC_DisableProcessorClock(); +#ifdef CP15_PRESENT + _waitForInterrupt(); +#endif +} + + diff --git a/at91lib/peripherals/pmc/pmc.h b/at91lib/peripherals/pmc/pmc.h new file mode 100644 index 0000000..a53b365 --- /dev/null +++ b/at91lib/peripherals/pmc/pmc.h @@ -0,0 +1,62 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef PMC_H +#define PMC_H + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ + +#if defined(at91sam7l64) || defined(at91sam7l128) +extern void PMC_SetFastWakeUpInputs(unsigned int inputs); +extern void PMC_DisableMainOscillator(void); +extern +#ifdef __ICCARM__ +__ramfunc +#endif //__ICCARM__ +void PMC_DisableMainOscillatorForWaitMode(void); +#endif // at91sam7l64 at91sam7l128 + +extern void PMC_DisableProcessorClock(void); +extern void PMC_EnablePeripheral(unsigned int id); +extern void PMC_DisablePeripheral(unsigned int id); +extern void PMC_CPUInIdleMode(void); + + +extern void PMC_EnableAllPeripherals(void); + +extern void PMC_DisableAllPeripherals(void); + +extern unsigned int PMC_IsAllPeriphEnabled(void); + +extern unsigned int PMC_IsPeriphEnabled(unsigned int id); + +#endif //#ifndef PMC_H + diff --git a/at91lib/peripherals/tc/tc.h b/at91lib/peripherals/tc/tc.h new file mode 100644 index 0000000..8bf96e5 --- /dev/null +++ b/at91lib/peripherals/tc/tc.h @@ -0,0 +1,74 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \unit +/// +/// !Purpose +/// +/// API for configuring and using Timer Counter (TC) peripherals. +/// +/// !Usage +/// -# Optionally, use TC_FindMckDivisor() to let the program find the best +/// TCCLKS field value automatically. +/// -# Configure a Timer Counter in the desired mode using TC_Configure(). +/// -# Start or stop the timer clock using TC_Start() and TC_Stop(). +//------------------------------------------------------------------------------ + +#ifndef TC_H +#define TC_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include + +#if !defined(AT91C_ID_TC0) && defined(AT91C_ID_TC012) + #define AT91C_ID_TC0 AT91C_ID_TC012 +#endif + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ + +extern void TC_Configure(AT91S_TC *pTc, unsigned int mode); + +extern void TC_Start(AT91S_TC *pTc); + +extern void TC_Stop(AT91S_TC *pTc); + +extern unsigned char TC_FindMckDivisor( + unsigned int freq, + unsigned int mck, + unsigned int *div, + unsigned int *tcclks); + +#endif //#ifndef TC_H + diff --git a/at91lib/peripherals/usart/usart.c b/at91lib/peripherals/usart/usart.c new file mode 100644 index 0000000..3f6d0e3 --- /dev/null +++ b/at91lib/peripherals/usart/usart.c @@ -0,0 +1,272 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "usart.h" +#include +#include + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +/// Configures an USART peripheral with the specified parameters. +/// \param usart Pointer to the USART peripheral to configure. +/// \param mode Desired value for the USART mode register (see the datasheet). +/// \param baudrate Baudrate at which the USART should operate (in Hz). +/// \param masterClock Frequency of the system master clock (in Hz). +//------------------------------------------------------------------------------ +void USART_Configure(AT91S_USART *usart, + unsigned int mode, + unsigned int baudrate, + unsigned int masterClock) +{ + // Reset and disable receiver & transmitter + usart->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX + | AT91C_US_RXDIS | AT91C_US_TXDIS; + + // Configure mode + usart->US_MR = mode; + + // Configure baudrate + // Asynchronous, no oversampling + if (((mode & AT91C_US_SYNC) == 0) + && ((mode & AT91C_US_OVER) == 0)) { + + usart->US_BRGR = (masterClock / baudrate) / 16; + } + // TODO other modes +} + +//------------------------------------------------------------------------------ +/// Enables or disables the transmitter of an USART peripheral. +/// \param usart Pointer to an USART peripheral +/// \param enabled If true, the transmitter is enabled; otherwise it is +/// disabled. +//------------------------------------------------------------------------------ +void USART_SetTransmitterEnabled(AT91S_USART *usart, + unsigned char enabled) +{ + if (enabled) { + + usart->US_CR = AT91C_US_TXEN; + } + else { + + usart->US_CR = AT91C_US_TXDIS; + } +} + +//------------------------------------------------------------------------------ +/// Enables or disables the receiver of an USART peripheral +/// \param usart Pointer to an USART peripheral +/// \param enabled If true, the receiver is enabled; otherwise it is disabled. +//------------------------------------------------------------------------------ +void USART_SetReceiverEnabled(AT91S_USART *usart, + unsigned char enabled) +{ + if (enabled) { + + usart->US_CR = AT91C_US_RXEN; + } + else { + + usart->US_CR = AT91C_US_RXDIS; + } +} + +//------------------------------------------------------------------------------ +/// Sends one packet of data through the specified USART peripheral. This +/// function operates synchronously, so it only returns when the data has been +/// actually sent. +/// \param usart Pointer to an USART peripheral. +/// \param data Data to send including 9nth bit and sync field if necessary (in +/// the same format as the US_THR register in the datasheet). +/// \param timeOut Time out value (0 = no timeout). +//------------------------------------------------------------------------------ +void USART_Write( + AT91S_USART *usart, + unsigned short data, + volatile unsigned int timeOut) +{ + if (timeOut == 0) { + + while ((usart->US_CSR & AT91C_US_TXEMPTY) == 0); + } + else { + + while ((usart->US_CSR & AT91C_US_TXEMPTY) == 0) { + + if (timeOut == 0) { + + TRACE_ERROR("USART_Write: Timed out.\n\r"); + return; + } + timeOut--; + } + } + + usart->US_THR = data; +} + +//------------------------------------------------------------------------------ +/// Sends the contents of a data buffer through the specified USART peripheral. +/// This function returns immediately (1 if the buffer has been queued, 0 +/// otherwise); poll the ENDTX and TXBUFE bits of the USART status register +/// to check for the transfer completion. +/// \param usart Pointer to an USART peripheral. +/// \param buffer Pointer to the data buffer to send. +/// \param size Size of the data buffer (in bytes). +//------------------------------------------------------------------------------ +unsigned char USART_WriteBuffer( + AT91S_USART *usart, + void *buffer, + unsigned int size) +{ + // Check if the first PDC bank is free + if ((usart->US_TCR == 0) && (usart->US_TNCR == 0)) { + + usart->US_TPR = (unsigned int) buffer; + usart->US_TCR = size; + usart->US_PTCR = AT91C_PDC_TXTEN; + + return 1; + } + // Check if the second PDC bank is free + else if (usart->US_TNCR == 0) { + + usart->US_TNPR = (unsigned int) buffer; + usart->US_TNCR = size; + + return 1; + } + else { + + return 0; + } +} + +//------------------------------------------------------------------------------ +/// Reads and return a packet of data on the specified USART peripheral. This +/// function operates asynchronously, so it waits until some data has been +/// received. +/// \param usart Pointer to an USART peripheral. +/// \param timeOut Time out value (0 -> no timeout). +//------------------------------------------------------------------------------ +unsigned short USART_Read( + AT91S_USART *usart, + volatile unsigned int timeOut) +{ + if (timeOut == 0) { + + while ((usart->US_CSR & AT91C_US_RXRDY) == 0); + } + else { + + while ((usart->US_CSR & AT91C_US_RXRDY) == 0) { + + if (timeOut == 0) { + + TRACE_ERROR("USART_Read: Timed out.\n\r"); + return 0; + } + timeOut--; + } + } + + return usart->US_RHR; +} + +//------------------------------------------------------------------------------ +/// Reads data from an USART peripheral, filling the provided buffer until it +/// becomes full. This function returns immediately with 1 if the buffer has +/// been queued for transmission; otherwise 0. +/// \param usart Pointer to an USART peripheral. +/// \param buffer Pointer to the buffer where the received data will be stored. +/// \param size Size of the data buffer (in bytes). +//------------------------------------------------------------------------------ +unsigned char USART_ReadBuffer(AT91S_USART *usart, + void *buffer, + unsigned int size) +{ + // Check if the first PDC bank is free + if ((usart->US_RCR == 0) && (usart->US_RNCR == 0)) { + + usart->US_RPR = (unsigned int) buffer; + usart->US_RCR = size; + usart->US_PTCR = AT91C_PDC_RXTEN; + + return 1; + } + // Check if the second PDC bank is free + else if (usart->US_RNCR == 0) { + + usart->US_RNPR = (unsigned int) buffer; + usart->US_RNCR = size; + + return 1; + } + else { + + return 0; + } +} + +//------------------------------------------------------------------------------ +/// Returns 1 if some data has been received and can be read from an USART; +/// otherwise returns 0. +/// \param usart Pointer to an AT91S_USART instance. +//------------------------------------------------------------------------------ +unsigned char USART_IsDataAvailable(AT91S_USART *usart) +{ + if ((usart->US_CSR & AT91C_US_RXRDY) != 0) { + + return 1; + } + else { + + return 0; + } +} + +//------------------------------------------------------------------------------ +/// Sets the filter value for the IRDA demodulator. +/// \param pUsart Pointer to an AT91S_USART instance. +/// \param filter Filter value. +//------------------------------------------------------------------------------ +void USART_SetIrdaFilter(AT91S_USART *pUsart, unsigned char filter) +{ + SANITY_CHECK(pUsart); + + pUsart->US_IF = filter; +} + diff --git a/at91lib/peripherals/usart/usart.h b/at91lib/peripherals/usart/usart.h new file mode 100644 index 0000000..84a633c --- /dev/null +++ b/at91lib/peripherals/usart/usart.h @@ -0,0 +1,118 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \dir +/// !Purpose +/// +/// This module provides several definitions and methods for using an USART +/// peripheral. +/// +/// !Usage +/// -# Enable the USART peripheral clock in the PMC. +/// -# Enable the required USART PIOs (see pio.h). +/// -# Configure the UART by calling USART_Configure. +/// -# Enable the transmitter and/or the receiver of the USART using +/// USART_SetTransmitterEnabled and USART_SetReceiverEnabled. +/// -# Send data through the USART using the USART_Write and +/// USART_WriteBuffer methods. +/// -# Receive data from the USART using the USART_Read and +/// USART_ReadBuffer functions; the availability of data can be polled +/// with USART_IsDataAvailable. +/// -# Disable the transmitter and/or the receiver of the USART with +/// USART_SetTransmitterEnabled and USART_SetReceiverEnabled. +//------------------------------------------------------------------------------ + +#ifndef USART_H +#define USART_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USART modes" +/// This page lists several common operating modes for an USART peripheral. +/// +/// !Modes +/// - USART_MODE_ASYNCHRONOUS +/// - USART_MODE_IRDA + +/// Basic asynchronous mode, i.e. 8 bits no parity. +#define USART_MODE_ASYNCHRONOUS (AT91C_US_CHRL_8_BITS | AT91C_US_PAR_NONE) + +/// IRDA mode +#define USART_MODE_IRDA (AT91C_US_USMODE_IRDA | AT91C_US_CHRL_8_BITS | AT91C_US_PAR_NONE | AT91C_US_FILTER) +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +extern void USART_Configure( + AT91S_USART *usart, + unsigned int mode, + unsigned int baudrate, + unsigned int masterClock); + +extern void USART_SetTransmitterEnabled(AT91S_USART *usart, unsigned char enabled); + +extern void USART_SetReceiverEnabled(AT91S_USART *usart, unsigned char enabled); + +extern void USART_Write( + AT91S_USART *usart, + unsigned short data, + volatile unsigned int timeOut); + +extern unsigned char USART_WriteBuffer( + AT91S_USART *usart, + void *buffer, + unsigned int size); + +extern unsigned short USART_Read( + AT91S_USART *usart, + volatile unsigned int timeOut); + +extern unsigned char USART_ReadBuffer( + AT91S_USART *usart, + void *buffer, + unsigned int size); + +extern unsigned char USART_IsDataAvailable(AT91S_USART *usart); + +extern void USART_SetIrdaFilter(AT91S_USART *pUsart, unsigned char filter); + +#endif //#ifndef USART_H + diff --git a/at91lib/usb/common/cdc/CDCAbstractControlManagementDescriptor.h b/at91lib/usb/common/cdc/CDCAbstractControlManagementDescriptor.h new file mode 100644 index 0000000..943204c --- /dev/null +++ b/at91lib/usb/common/cdc/CDCAbstractControlManagementDescriptor.h @@ -0,0 +1,104 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Definition of a class for manipulating CDC abstract control management + descriptors. + + !!!Usage + + Should be included in a list of USB configuration descriptors. +*/ + +#ifndef CDCABSTRACTCONTROLMANAGEMENTDESCRIPTOR_H +#define CDCABSTRACTCONTROLMANAGEMENTDESCRIPTOR_H + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "CDC ACM Capabilities" +/// This page lists the capabilities of the CDC ACM. +/// +/// !Capabilities +/// - CDCAbstractControlManagementDescriptor_COMMFEATURE +/// - CDCAbstractControlManagementDescriptor_LINE +/// - CDCAbstractControlManagementDescriptor_SENDBREAK +/// - CDCAbstractControlManagementDescriptor_NETWORKCONNECTION + +/// Device supports the request combination of SetCommFeature, ClearCommFeature +/// and GetCommFeature. +#define CDCAbstractControlManagementDescriptor_COMMFEATURE (1 << 0) +/// Device supports the request combination of SetLineCoding, GetLineCoding and +/// SetControlLineState. +#define CDCAbstractControlManagementDescriptor_LINE (1 << 1) +/// Device supports the SendBreak request. +#define CDCAbstractControlManagementDescriptor_SENDBREAK (1 << 2) +/// Device supports the NetworkConnection notification. +#define CDCAbstractControlManagementDescriptor_NETWORKCONNECTION (1 << 3) +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Types +//------------------------------------------------------------------------------ + +#ifdef __ICCARM__ // IAR +#pragma pack(1) // IAR +#define __attribute__(...) // IAR +#endif // IAR + +//------------------------------------------------------------------------------ +/// Describes the command supported by the communication interface class +/// with the Abstract Control Model subclass code. +//------------------------------------------------------------------------------ +typedef struct { + + /// Size of this descriptor in bytes. + unsigned char bFunctionLength; + /// Descriptor type (CDCDescriptors_INTERFACE). + unsigned char bDescriptorType; + /// Descriptor subtype (CDCDescriptors_ABSTRACTCONTROLMANAGEMENT). + unsigned char bDescriptorSubtype; + /// Configuration capabilities. + /// \sa "CDC ACM Capabilities". + unsigned char bmCapabilities; + +} __attribute__ ((packed)) CDCAbstractControlManagementDescriptor; // GCC + +#ifdef __ICCARM__ // IAR +#pragma pack() // IAR +#endif // IAR + +#endif //#ifndef CDCABSTRACTCONTROLMANAGEMENTDESCRIPTOR_H + diff --git a/at91lib/usb/common/cdc/CDCCallManagementDescriptor.h b/at91lib/usb/common/cdc/CDCCallManagementDescriptor.h new file mode 100644 index 0000000..191ff61 --- /dev/null +++ b/at91lib/usb/common/cdc/CDCCallManagementDescriptor.h @@ -0,0 +1,97 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Definition of a class for managing CDC call management descriptors. + + !!!Usage + + Should be included in a list of configuration descriptors for a USB + device. +*/ + +#ifndef CDCCALLMANAGEMENTDESCRIPTOR_H +#define CDCCALLMANAGEMENTDESCRIPTOR_H + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "CDC CallManagement Capabilities" +/// This page lists CDC CallManagement Capabilities. +/// +/// !Capabilities +/// - CDCCallManagementDescriptor_SELFCALLMANAGEMENT +/// - CDCCallManagementDescriptor_DATACALLMANAGEMENT + +/// Device handles call management itself. +#define CDCCallManagementDescriptor_SELFCALLMANAGEMENT (1 << 0) +/// Device can exchange call management information over a Data class interface. +#define CDCCallManagementDescriptor_DATACALLMANAGEMENT (1 << 1) +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Types +//------------------------------------------------------------------------------ + +#ifdef __ICCARM__ // IAR +#pragma pack(1) // IAR +#define __attribute__(...) // IAR +#endif // IAR + +//------------------------------------------------------------------------------ +/// Describes the processing of calls for the communication class interface. +//------------------------------------------------------------------------------ +typedef struct { + + /// Size of this descriptor in bytes. + unsigned char bFunctionLength; + /// Descriptor type (CDCDescriptors_INTERFACE). + unsigned char bDescriptorType; + /// Descriptor sub-type (CDCDescriptors_CALLMANAGEMENT). + unsigned char bDescriptorSubtype; + /// Configuration capabilities ("CDC CallManagement Capabilities"). + unsigned char bmCapabilities; + /// Interface number of the data class interface used for call management + /// (optional). + unsigned char bDataInterface; + +} __attribute__ ((packed)) CDCCallManagementDescriptor; // GCC + +#ifdef __ICCARM__ // IAR +#pragma pack() // IAR +#endif // IAR + +#endif //#ifndef CDCCALLMANAGEMENTDESCRIPTOR_H + diff --git a/at91lib/usb/common/cdc/CDCCommunicationInterfaceDescriptor.h b/at91lib/usb/common/cdc/CDCCommunicationInterfaceDescriptor.h new file mode 100644 index 0000000..aa13915 --- /dev/null +++ b/at91lib/usb/common/cdc/CDCCommunicationInterfaceDescriptor.h @@ -0,0 +1,65 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Definition of several constants used when declaring a CDC communication + class interface descriptor. +*/ + +#ifndef CDCCOMMUNICATIONINTERFACEDESCRIPTOR_H +#define CDCCOMMUNICATIONINTERFACEDESCRIPTOR_H + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "CDC Communication Interface Values" +/// This page lists the values for CDC Communication Interface Descriptor. +/// +/// !Values +/// - CDCCommunicationInterfaceDescriptor_CLASS +/// - CDCCommunicationInterfaceDescriptor_ABSTRACTCONTROLMODEL +/// - CDCCommunicationInterfaceDescriptor_NOPROTOCOL + +/// Interface class code for a CDC communication class interface. +#define CDCCommunicationInterfaceDescriptor_CLASS 0x02 +/// Interface subclass code for an Abstract Control Model interface descriptor. +#define CDCCommunicationInterfaceDescriptor_ABSTRACTCONTROLMODEL 0x02 +/// Interface protocol code when a CDC communication interface does not +/// implemenent any particular protocol. +#define CDCCommunicationInterfaceDescriptor_NOPROTOCOL 0x00 +//------------------------------------------------------------------------------ + +#endif //#ifndef CDCCOMMUNICATIONINTERFACEDESCRIPTOR_H + diff --git a/at91lib/usb/common/cdc/CDCDataInterfaceDescriptor.h b/at91lib/usb/common/cdc/CDCDataInterfaceDescriptor.h new file mode 100644 index 0000000..640f8dc --- /dev/null +++ b/at91lib/usb/common/cdc/CDCDataInterfaceDescriptor.h @@ -0,0 +1,65 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Definitions of constants used when declaring a CDC data class interface + descriptor. +*/ + +#ifndef CDCDATAINTERFACEDESCRIPTOR_H +#define CDCDATAINTERFACEDESCRIPTOR_H + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "CDC Data Interface Values" +/// This page lists the values for CDC Data Interface Descriptor. +/// +/// !Values +/// - CDCDataInterfaceDescriptor_CLASS +/// - CDCDataInterfaceDescriptor_SUBCLASS +/// - CDCDataInterfaceDescriptor_NOPROTOCOL + +/// Interface class code for a data class interface. +#define CDCDataInterfaceDescriptor_CLASS 0x0A +/// Interface subclass code for a data class interface. +#define CDCDataInterfaceDescriptor_SUBCLASS 0x00 +/// Protocol code for a data class interface which does not implement any +/// particular protocol. +#define CDCDataInterfaceDescriptor_NOPROTOCOL 0x00 +//------------------------------------------------------------------------------ + +#endif //#ifndef CDCDATAINTERFACEDESCRIPTOR_H + diff --git a/at91lib/usb/common/cdc/CDCDeviceDescriptor.h b/at91lib/usb/common/cdc/CDCDeviceDescriptor.h new file mode 100644 index 0000000..b1bc177 --- /dev/null +++ b/at91lib/usb/common/cdc/CDCDeviceDescriptor.h @@ -0,0 +1,64 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Definition of several constants used when declaring USB CDC device + descriptors. +*/ + +#ifndef CDCDEVICEDESCRIPTOR_H +#define CDCDEVICEDESCRIPTOR_H + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "CDC Device Descriptor Values" +/// This page lists the values for CDC Device Descriptor. +/// +/// !Values +/// - CDCDeviceDescriptor_CLASS +/// - CDCDeviceDescriptor_SUBCLASS +/// - CDCDeviceDescriptor_PROTOCOL + +/// Device class code when using the CDC class. +#define CDCDeviceDescriptor_CLASS 0x02 +/// Device subclass code when using the CDC class. +#define CDCDeviceDescriptor_SUBCLASS 0x00 +/// Device protocol code when using the CDC class. +#define CDCDeviceDescriptor_PROTOCOL 0x00 +//------------------------------------------------------------------------------ + +#endif //#ifndef CDCDEVICEDESCRIPTOR_H + diff --git a/at91lib/usb/common/cdc/CDCGenericDescriptor.h b/at91lib/usb/common/cdc/CDCGenericDescriptor.h new file mode 100644 index 0000000..3d93656 --- /dev/null +++ b/at91lib/usb/common/cdc/CDCGenericDescriptor.h @@ -0,0 +1,91 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Definition of several constants for declaring CDC descriptors. +*/ + +#ifndef CDCGENERICDESCRIPTOR_H +#define CDCGENERICDESCRIPTOR_H + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "CDC Specification Release Numbers" +/// This page list the CDC Spec. Release Numbers. +/// +/// !Numbers +/// - CDCGenericDescriptor_CDC1_10 + +/// Identify CDC specification version 1.10. +#define CDCGenericDescriptor_CDC1_10 0x0110 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "CDC Descriptro Types" +/// This page lists CDC descriptor types. +/// +/// !Types +/// - CDCGenericDescriptor_INTERFACE +/// - CDCGenericDescriptor_ENDPOINT + +///Indicates that a CDC descriptor applies to an interface. +#define CDCGenericDescriptor_INTERFACE 0x24 +/// Indicates that a CDC descriptor applies to an endpoint. +#define CDCGenericDescriptor_ENDPOINT 0x25 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "CDC Descriptor Subtypes" +/// This page lists CDC descriptor sub types +/// +/// !Types +/// - CDCGenericDescriptor_HEADER +/// - CDCGenericDescriptor_CALLMANAGEMENT +/// - CDCGenericDescriptor_ABSTRACTCONTROLMANAGEMENT +/// - CDCGenericDescriptor_UNION + +/// Header functional descriptor subtype. +#define CDCGenericDescriptor_HEADER 0x00 +/// Call management functional descriptor subtype. +#define CDCGenericDescriptor_CALLMANAGEMENT 0x01 +/// Abstract control management descriptor subtype. +#define CDCGenericDescriptor_ABSTRACTCONTROLMANAGEMENT 0x02 +/// Union descriptor subtype. +#define CDCGenericDescriptor_UNION 0x06 +//------------------------------------------------------------------------------ + +#endif //#ifndef CDCGENERICDESCRIPTOR_H + diff --git a/at91lib/usb/common/cdc/CDCGenericRequest.h b/at91lib/usb/common/cdc/CDCGenericRequest.h new file mode 100644 index 0000000..d6abd0b --- /dev/null +++ b/at91lib/usb/common/cdc/CDCGenericRequest.h @@ -0,0 +1,63 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Various definitions used for characterizing USB CDC requests. +*/ + +#ifndef CDCGENERICREQUEST_H +#define CDCGENERICREQUEST_H + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "CDC Request Codes" +/// This page lists USB CDC Request Codes. +/// +/// !Codes +/// - CDCGenericRequest_SETLINECODING +/// - CDCGenericRequest_GETLINECODING +/// - CDCGenericRequest_SETCONTROLLINESTATE + +/// SetLineCoding request code. +#define CDCGenericRequest_SETLINECODING 0x20 +/// GetLineCoding request code. +#define CDCGenericRequest_GETLINECODING 0x21 +/// SetControlLineState request code. +#define CDCGenericRequest_SETCONTROLLINESTATE 0x22 +//------------------------------------------------------------------------------ + +#endif //#ifndef CDCGENERICREQUEST_H + diff --git a/at91lib/usb/common/cdc/CDCHeaderDescriptor.h b/at91lib/usb/common/cdc/CDCHeaderDescriptor.h new file mode 100644 index 0000000..b04926f --- /dev/null +++ b/at91lib/usb/common/cdc/CDCHeaderDescriptor.h @@ -0,0 +1,77 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Definition of the CDCHeaderDescriptor class. + + !!!Usage + + Should be included in a USB configuration descriptor. +*/ + +#ifndef CDCHEADERDESCRIPTOR_H +#define CDCHEADERDESCRIPTOR_H + +//------------------------------------------------------------------------------ +// Types +//------------------------------------------------------------------------------ + +#ifdef __ICCARM__ // IAR +#pragma pack(1) // IAR +#define __attribute__(...) // IAR +#endif // IAR + +//------------------------------------------------------------------------------ +/// Marks the beginning of the concatenated set of functional descriptors +/// for the interface. +//------------------------------------------------------------------------------ +typedef struct { + + /// Size of this descriptor in bytes. + unsigned char bFunctionLength; + /// Descriptor type (CDCDescriptors_INTERFACE). + unsigned char bDescriptorType; + /// Descriptor sub-type (CDCDescriptors_HEADER). + unsigned char bDescriptorSubtype; + /// USB CDC specification release number. + unsigned short bcdCDC; + +} __attribute__ ((packed)) CDCHeaderDescriptor; // GCC + +#ifdef __ICCARM__ // IAR +#pragma pack() // IAR +#endif // IAR + +#endif //#ifndef CDCHEADERDESCRIPTOR_H + + diff --git a/at91lib/usb/common/cdc/CDCLineCoding.c b/at91lib/usb/common/cdc/CDCLineCoding.c new file mode 100644 index 0000000..4223fec --- /dev/null +++ b/at91lib/usb/common/cdc/CDCLineCoding.c @@ -0,0 +1,78 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/* + Title: CDCLineCoding + + About: Purpose + Implementation of the CDCLineCoding class. +*/ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "CDCLineCoding.h" +#include + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Initializes the bitrate, number of stop bits, parity checking and +/// number of data bits of a CDCLineCoding object. +/// \param lineCoding Pointer to a CDCLineCoding instance. +/// \param bitrate Bitrate of the virtual COM connection. +/// \param stopbits Number of stop bits ("CDC LineCoding StopBits"). +/// \param parity Parity check type ("CDC LineCoding ParityChecking"). +/// \param databits Number of data bits. +//------------------------------------------------------------------------------ +void CDCLineCoding_Initialize(CDCLineCoding *lineCoding, + unsigned int bitrate, + unsigned char stopbits, + unsigned char parity, + unsigned char databits) +{ + ASSERT(stopbits <= CDCLineCoding_TWOSTOPBITS, + "CDCLineCoding_Initialize: Invalid stopbits value (%d)\n\r", + stopbits); + ASSERT(parity <= CDCLineCoding_SPACEPARITY, + "CDCLineCoding_Initialize: Invalid parity value (%d)\n\r", + parity); + ASSERT(((databits >= 5) && (databits <= 8)) || (databits == 16), + "CDCLineCoding_Initialize: Invalid databits value (%d)\n\r", + databits); + + lineCoding->dwDTERate = bitrate; + lineCoding->bCharFormat = stopbits; + lineCoding->bParityType = parity; + lineCoding->bDataBits = databits; +} + diff --git a/at91lib/usb/common/cdc/CDCLineCoding.h b/at91lib/usb/common/cdc/CDCLineCoding.h new file mode 100644 index 0000000..dfe3c10 --- /dev/null +++ b/at91lib/usb/common/cdc/CDCLineCoding.h @@ -0,0 +1,136 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Line coding structure used for by the CDC GetLineCoding and SetLineCoding + requests. + + !!!Usage + + -# Initialize a CDCLineCoding instance using CDCLineCoding_Initialize. + -# Send a CDCLineCoding object to the host in response to a GetLineCoding + request. + -# Receive a CDCLineCoding object from the host after a SetLineCoding + request. +*/ + +#ifndef CDCLINECODING_H +#define CDCLINECODING_H + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "CDC LineCoding StopBits" +/// This page lists Stop Bits for CDC Line Coding. +/// +/// !Stop bits +/// - CDCLineCoding_ONESTOPBIT +/// - CDCLineCoding_ONE5STOPBIT +/// - CDCLineCoding_TWOSTOPBITS + +/// The transmission protocol uses one stop bit. +#define CDCLineCoding_ONESTOPBIT 0 +/// The transmission protocol uses 1.5 stop bit. +#define CDCLineCoding_ONE5STOPBIT 1 +/// The transmissin protocol uses two stop bits. +#define CDCLineCoding_TWOSTOPBITS 2 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "CDC LineCoding ParityCheckings" +/// This page lists Parity checkings for CDC Line Coding. +/// +/// !Parity checking +/// - CDCLineCoding_NOPARITY +/// - CDCLineCoding_ODDPARITY +/// - CDCLineCoding_EVENPARITY +/// - CDCLineCoding_MARKPARITY +/// - CDCLineCoding_SPACEPARITY + +/// No parity checking. +#define CDCLineCoding_NOPARITY 0 +/// Odd parity checking. +#define CDCLineCoding_ODDPARITY 1 +/// Even parity checking. +#define CDCLineCoding_EVENPARITY 2 +/// Mark parity checking. +#define CDCLineCoding_MARKPARITY 3 +/// Space parity checking. +#define CDCLineCoding_SPACEPARITY 4 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Types +//------------------------------------------------------------------------------ + +#ifdef __ICCARM__ // IAR +#pragma pack(1) // IAR +#define __attribute__(...) // IAR +#endif // IAR + +//------------------------------------------------------------------------------ +/// Format of the data returned when a GetLineCoding request is received. +//------------------------------------------------------------------------------ +typedef struct { + + /// Data terminal rate in bits per second. + unsigned int dwDTERate; + /// Number of stop bits. + /// \sa "CDC LineCoding StopBits". + char bCharFormat; + /// Type of parity checking used. + /// \sa "CDC LineCoding ParityCheckings". + char bParityType; + /// Number of data bits (5, 6, 7, 8 or 16). + char bDataBits; + +} __attribute__ ((packed)) CDCLineCoding; // GCC + +#ifdef __ICCARM__ // IAR +#pragma pack() // IAR +#endif // IAR + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +extern void CDCLineCoding_Initialize(CDCLineCoding *lineCoding, + unsigned int bitrate, + unsigned char stopbits, + unsigned char parity, + unsigned char databits); + +#endif //#ifndef CDCLINECODING_H + diff --git a/at91lib/usb/common/cdc/CDCSetControlLineStateRequest.c b/at91lib/usb/common/cdc/CDCSetControlLineStateRequest.c new file mode 100644 index 0000000..43079ca --- /dev/null +++ b/at91lib/usb/common/cdc/CDCSetControlLineStateRequest.c @@ -0,0 +1,84 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + CDCSetControlLineStateRequest.c + + !!!Purpose + + Implementation of the CDCSetControlLineStateRequest class. +*/ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "CDCSetControlLineStateRequest.h" + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Notifies if the given request indicates that the DTE signal is present. +/// \param request Pointer to a USBGenericRequest instance. +/// \return 1 if the DTE signal is present, otherwise 0. +//------------------------------------------------------------------------------ +unsigned char CDCSetControlLineStateRequest_IsDtePresent( + const USBGenericRequest *request) +{ + if ((USBGenericRequest_GetValue(request) & 0x0001) != 0) { + + return 1; + } + else { + + return 0; + } +} + +//------------------------------------------------------------------------------ +/// Notifies if the given request indicates that the device carrier should +/// be activated. +/// \param request Pointer to a USBGenericRequest instance. +/// \return 1 is the device should activate its carrier, 0 otherwise. +//------------------------------------------------------------------------------ +unsigned char CDCSetControlLineStateRequest_ActivateCarrier( + const USBGenericRequest *request) +{ + if ((USBGenericRequest_GetValue(request) & 0x0002) != 0) { + + return 1; + } + else { + + return 0; + } +} + diff --git a/at91lib/usb/common/cdc/CDCSetControlLineStateRequest.h b/at91lib/usb/common/cdc/CDCSetControlLineStateRequest.h new file mode 100644 index 0000000..5d6c661 --- /dev/null +++ b/at91lib/usb/common/cdc/CDCSetControlLineStateRequest.h @@ -0,0 +1,59 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Definition of a class for manipulating SetControlLineState requests. +*/ + +#ifndef CDCSETCONTROLLINESTATE_H +#define CDCSETCONTROLLINESTATE_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +extern unsigned char CDCSetControlLineStateRequest_IsDtePresent( + const USBGenericRequest *request); + + +extern unsigned char CDCSetControlLineStateRequest_ActivateCarrier( + const USBGenericRequest *request); + +#endif //#ifndef CDCSETCONTROLLINESTATE_H + diff --git a/at91lib/usb/common/cdc/CDCUnionDescriptor.h b/at91lib/usb/common/cdc/CDCUnionDescriptor.h new file mode 100644 index 0000000..0ba9eaa --- /dev/null +++ b/at91lib/usb/common/cdc/CDCUnionDescriptor.h @@ -0,0 +1,79 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Definition of a class for manipulating CDC union descriptors. + + !!!Usage + + Should be included in the list of USB descriptor used for a device + configuration. +*/ + +#ifndef CDCUNIONDESCRIPTOR_H +#define CDCUNIONDESCRIPTOR_H + +//------------------------------------------------------------------------------ +// Types +//------------------------------------------------------------------------------ + +#ifdef __ICCARM__ // IAR +#pragma pack(1) // IAR +#define __attribute__(...) // IAR +#endif // IAR + +//------------------------------------------------------------------------------ +/// Describes the relationship between a group of interfaces that can +/// be considered to form a functional unit. +//------------------------------------------------------------------------------ +typedef struct { + + /// Size of the descriptor in bytes. + unsigned char bFunctionLength; + /// Descriptor type (CDCDescriptors_INTERFACE). + unsigned char bDescriptorType; + /// Descriptor subtype (CDCDescriptors_UNION). + unsigned char bDescriptorSubtype; + /// Number of the master interface for this union. + unsigned char bMasterInterface; + /// Number of the first slave interface for this union. + unsigned char bSlaveInterface0; + +} __attribute__ ((packed)) CDCUnionDescriptor; // GCC + +#ifdef __ICCARM__ // IAR +#pragma pack() // IAR +#endif // IAR + +#endif //#ifndef CDCUNIONDESCRIPTOR_H + diff --git a/at91lib/usb/common/core/USBConfigurationDescriptor.c b/at91lib/usb/common/core/USBConfigurationDescriptor.c new file mode 100644 index 0000000..503dceb --- /dev/null +++ b/at91lib/usb/common/core/USBConfigurationDescriptor.c @@ -0,0 +1,162 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/* + Title: USBConfigurationDescriptor implementation + + About: Purpose + Implementation of the USBConfigurationDescriptor class. +*/ + +//----------------------------------------------------------------------------- +// Headers +//----------------------------------------------------------------------------- + +#include "USBConfigurationDescriptor.h" + +//----------------------------------------------------------------------------- +// Exported functions +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +/// Returns the total length of a configuration, i.e. including the +/// descriptors following it. +/// \param configuration Pointer to a USBConfigurationDescriptor instance. +/// \return Total length (in bytes) of the configuration. +//----------------------------------------------------------------------------- +unsigned int USBConfigurationDescriptor_GetTotalLength( + const USBConfigurationDescriptor *configuration) +{ + return configuration->wTotalLength; +} + +//----------------------------------------------------------------------------- +/// Returns the number of interfaces in a configuration. +/// \param configuration Pointer to a USBConfigurationDescriptor instance. +/// \return Number of interfaces in configuration. +//----------------------------------------------------------------------------- +unsigned char USBConfigurationDescriptor_GetNumInterfaces( + const USBConfigurationDescriptor *configuration) +{ + return configuration->bNumInterfaces; +} + +//----------------------------------------------------------------------------- +/// Indicates if the device is self-powered when in a given configuration. +/// \param configuration Pointer to a USBConfigurationDescriptor instance. +/// \return 1 if the device is self-powered when in the given configuration; +/// otherwise 0. +//----------------------------------------------------------------------------- +unsigned char USBConfigurationDescriptor_IsSelfPowered( + const USBConfigurationDescriptor *configuration) +{ + if ((configuration->bmAttributes & (1 << 6)) != 0) { + + return 1; + } + else { + + return 0; + } +} + +//----------------------------------------------------------------------------- +/// Parses the given Configuration descriptor (followed by relevant +/// interface, endpoint and class-specific descriptors) into three arrays. +/// *Each array must have its size equal or greater to the number of +/// descriptors it stores plus one*. A null-value is inserted after the last +/// descriptor of each type to indicate the array end. +/// +/// Note that if the pointer to an array is null (0), nothing is stored in +/// it. +/// \param configuration Pointer to the start of the whole Configuration +/// descriptor. +/// \param interfaces Pointer to the Interface descriptor array. +/// \param endpoints Pointer to the Endpoint descriptor array. +/// \param others Pointer to the class-specific descriptor array. +//----------------------------------------------------------------------------- +void USBConfigurationDescriptor_Parse( + const USBConfigurationDescriptor *configuration, + USBInterfaceDescriptor **interfaces, + USBEndpointDescriptor **endpoints, + USBGenericDescriptor **others) +{ + // Get size of configuration to parse + int size = USBConfigurationDescriptor_GetTotalLength(configuration); + size -= sizeof(USBConfigurationDescriptor); + + // Start parsing descriptors + USBGenericDescriptor *descriptor = (USBGenericDescriptor *) configuration; + while (size > 0) { + + // Get next descriptor + descriptor = USBGenericDescriptor_GetNextDescriptor(descriptor); + size -= USBGenericDescriptor_GetLength(descriptor); + + // Store descriptor in correponding array + if (USBGenericDescriptor_GetType(descriptor) + == USBGenericDescriptor_INTERFACE) { + + if (interfaces) { + + *interfaces = (USBInterfaceDescriptor *) descriptor; + interfaces++; + } + } + else if (USBGenericDescriptor_GetType(descriptor) + == USBGenericDescriptor_ENDPOINT) { + + if (endpoints) { + + *endpoints = (USBEndpointDescriptor *) descriptor; + endpoints++; + } + } + else if (others) { + + *others = descriptor; + others++; + } + } + + // Null-terminate arrays + if (interfaces) { + + *interfaces = 0; + } + if (endpoints) { + + *endpoints = 0; + } + if (others) { + + *others = 0; + } +} + diff --git a/at91lib/usb/common/core/USBConfigurationDescriptor.h b/at91lib/usb/common/core/USBConfigurationDescriptor.h new file mode 100644 index 0000000..150e656 --- /dev/null +++ b/at91lib/usb/common/core/USBConfigurationDescriptor.h @@ -0,0 +1,150 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + !!!Purpose + + Definitions and methods for USB configuration descriptor structures + described by the USB specification. + + !!!Usage + + -# Declare USBConfigurationDescriptor instance as a part + of the configuration descriptors of a USB device. + -# To get useful information (field values) from the defined USB device + configuration descriptor, use + - USBConfigurationDescriptor_GetTotalLength + - USBConfigurationDescriptor_GetNumInterfaces + - USBConfigurationDescriptor_IsSelfPowered + -# To pase the defined USB device configuration descriptor, use + - USBConfigurationDescriptor_Parse +*/ + +#ifndef USBCONFIGURATIONDESCRIPTOR_H +#define USBCONFIGURATIONDESCRIPTOR_H + +//----------------------------------------------------------------------------- +// Headers +//----------------------------------------------------------------------------- + +#include "USBGenericDescriptor.h" +#include "USBInterfaceDescriptor.h" +#include "USBEndpointDescriptor.h" + +//----------------------------------------------------------------------------- +// Definitions +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +/// \page "USB device Attributes" +/// +/// This page lists the codes of the usb attributes. +/// +/// !Attributes +/// - USBConfigurationDescriptor_BUSPOWERED_NORWAKEUP +/// - USBConfigurationDescriptor_SELFPOWERED_NORWAKEUP +/// - USBConfigurationDescriptor_BUSPOWERED_RWAKEUP +/// - USBConfigurationDescriptor_SELFPOWERED_RWAKEUP +/// - USBConfigurationDescriptor_POWER + +/// Device is bus-powered and not support remote wake-up. +#define USBConfigurationDescriptor_BUSPOWERED_NORWAKEUP 0x80 +/// Device is self-powered and not support remote wake-up. +#define USBConfigurationDescriptor_SELFPOWERED_NORWAKEUP 0xC0 +/// Device is bus-powered and supports remote wake-up. +#define USBConfigurationDescriptor_BUSPOWERED_RWAKEUP 0xA0 +/// Device is self-powered and supports remote wake-up. +#define USBConfigurationDescriptor_SELFPOWERED_RWAKEUP 0xE0 + +/// Calculates the value of the power consumption field given the value in mA. +/// \param power The power consumption value in mA +/// \return The value that should be set to the field in descriptor +#define USBConfigurationDescriptor_POWER(power) (power / 2) +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +// Types +//----------------------------------------------------------------------------- + +#ifdef __ICCARM__ // IAR +#pragma pack(1) // IAR +#define __attribute__(...) // IAR +#endif // IAR + +//----------------------------------------------------------------------------- +/// USB standard configuration descriptor structure. +//----------------------------------------------------------------------------- +typedef struct { + + /// Size of the descriptor in bytes. + unsigned char bLength; + /// Descriptor type (USBDESC_CONFIGURATION of "USB Descriptor types"). + unsigned char bDescriptorType; + /// Length of all descriptors returned along with this configuration + /// descriptor. + unsigned short wTotalLength; + /// Number of interfaces in this configuration. + unsigned char bNumInterfaces; + /// Value for selecting this configuration. + unsigned char bConfigurationValue; + /// Index of the configuration string descriptor. + unsigned char iConfiguration; + /// Configuration characteristics. + unsigned char bmAttributes; + /// Maximum power consumption of the device when in this configuration. + unsigned char bMaxPower; + +} __attribute__ ((packed)) USBConfigurationDescriptor; // GCC + +#ifdef __ICCARM__ // IAR +#pragma pack() // IAR +#endif // IAR + +//----------------------------------------------------------------------------- +// Exported functions +//----------------------------------------------------------------------------- + +extern unsigned int USBConfigurationDescriptor_GetTotalLength( + const USBConfigurationDescriptor *configuration); + +extern unsigned char USBConfigurationDescriptor_GetNumInterfaces( + const USBConfigurationDescriptor *configuration); + +extern unsigned char USBConfigurationDescriptor_IsSelfPowered( + const USBConfigurationDescriptor *configuration); + +extern void USBConfigurationDescriptor_Parse( + const USBConfigurationDescriptor *configuration, + USBInterfaceDescriptor **interfaces, + USBEndpointDescriptor **endpoints, + USBGenericDescriptor **others); + +#endif //#ifndef USBCONFIGURATIONDESCRIPTOR_H + diff --git a/at91lib/usb/common/core/USBDeviceDescriptor.h b/at91lib/usb/common/core/USBDeviceDescriptor.h new file mode 100644 index 0000000..4cebe66 --- /dev/null +++ b/at91lib/usb/common/core/USBDeviceDescriptor.h @@ -0,0 +1,111 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + !!!Purpose + + Class for manipulating USB device descriptors. + + !!!Usage + + - Declare a USBDeviceDescriptor instance as the device descriptor of a + USB device. +*/ + +#ifndef USBDEVICEDESCRIPTOR_H +#define USBDEVICEDESCRIPTOR_H + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB release numbers" +/// +/// This page lists the codes of USB release numbers. +/// +/// !Code +/// - USBDeviceDescriptor_USB2_00 + +/// The device supports USB 2.00. +#define USBDeviceDescriptor_USB2_00 0x0200 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Types +//------------------------------------------------------------------------------ + +#ifdef __ICCARM__ // IAR +#pragma pack(1) // IAR +#define __attribute__(...) // IAR +#endif // IAR + +//------------------------------------------------------------------------------ +/// USB standard device descriptor structure. +//------------------------------------------------------------------------------ +typedef struct { + + /// Size of this descriptor in bytes. + unsigned char bLength; + /// Descriptor type (USBGenericDescriptor_DEVICE). + unsigned char bDescriptorType; + /// USB specification release number in BCD format. + unsigned short bcdUSB; + /// Device class code. + unsigned char bDeviceClass; + /// Device subclass code. + unsigned char bDeviceSubClass; + /// Device protocol code. + unsigned char bDeviceProtocol; + /// Maximum packet size of endpoint 0 (in bytes). + unsigned char bMaxPacketSize0; + /// Vendor ID. + unsigned short idVendor; + /// Product ID. + unsigned short idProduct; + /// Device release number in BCD format. + unsigned short bcdDevice; + /// Index of the manufacturer string descriptor. + unsigned char iManufacturer; + /// Index of the product string descriptor. + unsigned char iProduct; + /// Index of the serial number string descriptor. + unsigned char iSerialNumber; + /// Number of possible configurations for the device. + unsigned char bNumConfigurations; + +} __attribute__ ((packed)) USBDeviceDescriptor; // GCC + +#ifdef __ICCARM__ // IAR +#pragma pack() // IAR +#endif // IAR + +#endif //#ifndef USBDEVICEDESCRIPTOR_H + diff --git a/at91lib/usb/common/core/USBDeviceQualifierDescriptor.h b/at91lib/usb/common/core/USBDeviceQualifierDescriptor.h new file mode 100644 index 0000000..3728865 --- /dev/null +++ b/at91lib/usb/common/core/USBDeviceQualifierDescriptor.h @@ -0,0 +1,89 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Class for manipulating USB device qualifier descriptors. + + !!!Usage + + - Declare a USBDeviceQualifierDescriptor instance as the device qualifier + descriptor of a USB device. +*/ + +#ifndef USBDEVICEQUALIFIERDESCRIPTOR_H +#define USBDEVICEQUALIFIERDESCRIPTOR_H + +//------------------------------------------------------------------------------ +// Types +//------------------------------------------------------------------------------ + +#ifdef __ICCARM__ // IAR +#pragma pack(1) // IAR +#define __attribute__(...) // IAR +#endif // IAR + +//------------------------------------------------------------------------------ +/// Alternate device descriptor indicating the capabilities of the device +/// in full-speed, if currently in high-speed; or in high-speed, if it is +/// currently in full-speed. Only relevant for devices supporting the +/// high-speed mode. +//------------------------------------------------------------------------------ +typedef struct { + + /// Size of the descriptor in bytes. + unsigned char bLength; + /// Descriptor type (USBDESC_DEVICE_QUALIFIER or "USB device types"). + unsigned char bDescriptorType; + /// USB specification release number (in BCD format). + unsigned short bcdUSB; + /// Device class code. + unsigned char bDeviceClass; + /// Device subclass code. + unsigned char bDeviceSubClass; + /// Device protocol code. + unsigned char bDeviceProtocol; + /// Maximum packet size of endpoint 0. + unsigned char bMaxPacketSize0; + /// Number of possible configurations for the device. + unsigned char bNumConfigurations; + /// Reserved. + unsigned char bReserved; + +} __attribute__ ((packed)) USBDeviceQualifierDescriptor; // GCC + +#ifdef __ICCARM__ // IAR +#pragma pack() // IAR +#endif // IAR + +#endif //#ifndef USBDEVICEQUALIFIERDESCRIPTOR_H + diff --git a/at91lib/usb/common/core/USBEndpointDescriptor.c b/at91lib/usb/common/core/USBEndpointDescriptor.c new file mode 100644 index 0000000..9b3d696 --- /dev/null +++ b/at91lib/usb/common/core/USBEndpointDescriptor.c @@ -0,0 +1,98 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/* + Title: USBEndpointDescriptor implementation + + About: Purpose + Implementation of the USBEndpointDescriptor class. +*/ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "USBEndpointDescriptor.h" + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Returns the number of an endpoint given its descriptor. +/// \param endpoint Pointer to a USBEndpointDescriptor instance. +/// \return Endpoint number. +//------------------------------------------------------------------------------ +unsigned char USBEndpointDescriptor_GetNumber( + const USBEndpointDescriptor *endpoint) +{ + return endpoint->bEndpointAddress & 0xF; +} + +//------------------------------------------------------------------------------ +/// Returns the direction of an endpoint given its descriptor. +/// \param endpoint Pointer to a USBEndpointDescriptor instance. +/// \return Endpoint direction (see ). +//------------------------------------------------------------------------------ +unsigned char USBEndpointDescriptor_GetDirection( + const USBEndpointDescriptor *endpoint) +{ + if ((endpoint->bEndpointAddress & 0x80) != 0) { + + return USBEndpointDescriptor_IN; + } + else { + + return USBEndpointDescriptor_OUT; + } +} + +//------------------------------------------------------------------------------ +/// Returns the type of an endpoint given its descriptor. +/// \param endpoint Pointer to a USBEndpointDescriptor instance. +/// \return Endpoint type (see ). +//------------------------------------------------------------------------------ +unsigned char USBEndpointDescriptor_GetType( + const USBEndpointDescriptor *endpoint) +{ + return endpoint->bmAttributes & 0x3; +} + +//------------------------------------------------------------------------------ +/// Returns the maximum size of a packet (in bytes) on an endpoint given +/// its descriptor. +/// \param endpoint - Pointer to a USBEndpointDescriptor instance. +/// \return Maximum packet size of endpoint. +//------------------------------------------------------------------------------ +unsigned short USBEndpointDescriptor_GetMaxPacketSize( + const USBEndpointDescriptor *endpoint) +{ + return endpoint->wMaxPacketSize; +} + diff --git a/at91lib/usb/common/core/USBEndpointDescriptor.h b/at91lib/usb/common/core/USBEndpointDescriptor.h new file mode 100644 index 0000000..4a8a658 --- /dev/null +++ b/at91lib/usb/common/core/USBEndpointDescriptor.h @@ -0,0 +1,221 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Definition of a class for handling USB endpoint descriptors. + + !!!Usage + + -# Declare USBEndpointDescriptor instance as a part of the + configuration descriptors of a USB device. + -# To get useful information (field values) from the defined USB device + endpoint descriptor (to configure hardware for endpoints, etc), use + - USBEndpointDescriptor_GetNumber + - USBEndpointDescriptor_GetDirection + - USBEndpointDescriptor_GetType + - USBEndpointDescriptor_GetMaxPacketSize +*/ + +#ifndef USBENDPOINTDESCRIPTOR_H +#define USBENDPOINTDESCRIPTOR_H + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB Endpoint definitions" +/// +/// This page lists definitions and macro for endpoint descriptors. +/// +/// - USB Endpoint directions +/// - USBEndpointDescriptor_OUT +/// - USBEndpointDescriptor_IN +/// +/// - USB Endpoint types +/// - USBEndpointDescriptor_CONTROL +/// - USBEndpointDescriptor_ISOCHRONOUS +/// - USBEndpointDescriptor_BULK +/// - USBEndpointDescriptor_INTERRUPT +/// +/// - USB Endpoint maximun sizes +/// - USBEndpointDescriptor_MAXCTRLSIZE_FS +/// - USBEndpointDescriptor_MAXCTRLSIZE_HS +/// - USBEndpointDescriptor_MAXBULKSIZE_FS +/// - USBEndpointDescriptor_MAXBULKSIZE_HS +/// - USBEndpointDescriptor_MAXINTERRUPTSIZE_FS +/// - USBEndpointDescriptor_MAXINTERRUPTSIZE_HS +/// - USBEndpointDescriptor_MAXISOCHRONOUSSIZE_FS +/// - USBEndpointDescriptor_MAXISOCHRONOUSSIZE_HS +/// +/// - USB Endpoint address define +/// - USBEndpointDescriptor_ADDRESS +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB Endpoint directions" +/// +/// This page lists definitions of USB endpoint directions. +/// +/// !Directions +/// - USBEndpointDescriptor_OUT +/// - USBEndpointDescriptor_IN + +/// Endpoint receives data from the host. +#define USBEndpointDescriptor_OUT 0 +/// Endpoint sends data to the host. +#define USBEndpointDescriptor_IN 1 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB Endpoint types" +/// +/// This page lists definitions of USB endpoint types. +/// +/// !Types +/// - USBEndpointDescriptor_CONTROL +/// - USBEndpointDescriptor_ISOCHRONOUS +/// - USBEndpointDescriptor_BULK +/// - USBEndpointDescriptor_INTERRUPT + +/// Control endpoint type. +#define USBEndpointDescriptor_CONTROL 0 +/// Isochronous endpoint type. +#define USBEndpointDescriptor_ISOCHRONOUS 1 +/// Bulk endpoint type. +#define USBEndpointDescriptor_BULK 2 +/// Interrupt endpoint type. +#define USBEndpointDescriptor_INTERRUPT 3 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB Endpoint maximun sizes" +/// +/// This page lists definitions of USB endpoint maximun sizes. +/// +/// !Sizes +/// - USBEndpointDescriptor_MAXCTRLSIZE_FS +/// - USBEndpointDescriptor_MAXCTRLSIZE_HS +/// - USBEndpointDescriptor_MAXBULKSIZE_FS +/// - USBEndpointDescriptor_MAXBULKSIZE_HS +/// - USBEndpointDescriptor_MAXINTERRUPTSIZE_FS +/// - USBEndpointDescriptor_MAXINTERRUPTSIZE_HS +/// - USBEndpointDescriptor_MAXISOCHRONOUSSIZE_FS +/// - USBEndpointDescriptor_MAXISOCHRONOUSSIZE_HS + +/// Maximum size for a full-speed control endpoint. +#define USBEndpointDescriptor_MAXCTRLSIZE_FS 64 +/// Maximum size for a high-speed control endpoint. +#define USBEndpointDescriptor_MAXCTRLSIZE_HS 64 +/// Maximum size for a full-speed bulk endpoint. +#define USBEndpointDescriptor_MAXBULKSIZE_FS 64 +/// Maximum size for a high-speed bulk endpoint. +#define USBEndpointDescriptor_MAXBULKSIZE_HS 512 +/// Maximum size for a full-speed interrupt endpoint. +#define USBEndpointDescriptor_MAXINTERRUPTSIZE_FS 64 +/// Maximum size for a high-speed interrupt endpoint. +#define USBEndpointDescriptor_MAXINTERRUPTSIZE_HS 1024 +/// Maximum size for a full-speed isochronous endpoint. +#define USBEndpointDescriptor_MAXISOCHRONOUSSIZE_FS 1023 +/// Maximum size for a high-speed isochronous endpoint. +#define USBEndpointDescriptor_MAXISOCHRONOUSSIZE_HS 1024 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB Endpoint address define" +/// +/// This page lists macro for USB endpoint address definition. +/// +/// !Macro +/// - USBEndpointDescriptor_ADDRESS + +/// Calculates the address of an endpoint given its number and direction +/// \param direction USB endpoint direction definition +/// \param number USB endpoint number +/// \return The value used to set the endpoint descriptor based on input number +/// and direction +#define USBEndpointDescriptor_ADDRESS(direction, number) \ + (((direction & 0x01) << 7) | (number & 0xF)) +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Types +//------------------------------------------------------------------------------ + +#ifdef __ICCARM__ // IAR +#pragma pack(1) // IAR +#define __attribute__(...) // IAR +#endif // IAR + +//------------------------------------------------------------------------------ +/// USB standard endpoint descriptor structure. +//------------------------------------------------------------------------------ +typedef struct { + + /// Size of the descriptor in bytes. + unsigned char bLength; + /// Descriptor type (). + unsigned char bDescriptorType; + /// Address and direction of the endpoint. + unsigned char bEndpointAddress; + /// Endpoint type and additional characteristics (for isochronous endpoints). + unsigned char bmAttributes; + /// Maximum packet size (in bytes) of the endpoint. + unsigned short wMaxPacketSize; + /// Polling rate of the endpoint. + unsigned char bInterval; + +} __attribute__ ((packed)) USBEndpointDescriptor; // GCC + +#ifdef __ICCARM__ // IAR +#pragma pack() // IAR +#endif // IAR + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +extern unsigned char USBEndpointDescriptor_GetNumber( + const USBEndpointDescriptor *endpoint); + +extern unsigned char USBEndpointDescriptor_GetDirection( + const USBEndpointDescriptor *endpoint); + +extern unsigned char USBEndpointDescriptor_GetType( + const USBEndpointDescriptor *endpoint); + +extern unsigned short USBEndpointDescriptor_GetMaxPacketSize( + const USBEndpointDescriptor *endpoint); + +#endif //#ifndef USBENDPOINTDESCRIPTOR_H + diff --git a/at91lib/usb/common/core/USBFeatureRequest.c b/at91lib/usb/common/core/USBFeatureRequest.c new file mode 100644 index 0000000..1e0422a --- /dev/null +++ b/at91lib/usb/common/core/USBFeatureRequest.c @@ -0,0 +1,70 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/* + Title: USBFeatureRequest implementation + + About: Purpose + Implementation of the USBFeatureRequest class. +*/ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "USBFeatureRequest.h" + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Returns the feature selector of a given CLEAR_FEATURE or SET_FEATURE +/// request. +/// \param request Pointer to a USBGenericRequest instance. +/// \return Feature selector. +//------------------------------------------------------------------------------ +unsigned char USBFeatureRequest_GetFeatureSelector( + const USBGenericRequest *request) +{ + return USBGenericRequest_GetValue(request); +} + +//------------------------------------------------------------------------------ +/// Indicates the test that the device must undertake following a +/// SET_FEATURE request. +/// \param request Pointer to a USBGenericRequest instance. +/// \return Test selector. +//------------------------------------------------------------------------------ +unsigned char USBFeatureRequest_GetTestSelector( + const USBGenericRequest *request) +{ + return (USBGenericRequest_GetIndex(request) >> 8) & 0xFF; +} + diff --git a/at91lib/usb/common/core/USBFeatureRequest.h b/at91lib/usb/common/core/USBFeatureRequest.h new file mode 100644 index 0000000..93b5445 --- /dev/null +++ b/at91lib/usb/common/core/USBFeatureRequest.h @@ -0,0 +1,136 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Definition of a class for manipulating CLEAR_FEATURE and SET_FEATURE + requests. + + !!!Usage + + - To get USB feature request information (field values) from the + USBGenericRequest instance, use + - USBFeatureRequest_GetFeatureSelector + - USBFeatureRequest_GetTestSelector +*/ + +#ifndef USBFEATUREREQUEST_H +#define USBFEATUREREQUEST_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "USBGenericRequest.h" + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB Feature Request definitions" +/// +/// This page lists codes of USB Feature Request +/// +/// - USB Feature selectors +/// - USBFeatureRequest_ENDPOINTHALT +/// - USBFeatureRequest_DEVICEREMOTEWAKEUP +/// - USBFeatureRequest_TESTMODE +/// +/// - USB Test mode selectors +/// - USBFeatureRequest_TESTJ +/// - USBFeatureRequest_TESTK +/// - USBFeatureRequest_TESTSE0NAK +/// - USBFeatureRequest_TESTPACKET +/// - USBFeatureRequest_TESTFORCEENABLE +/// - USBFeatureRequest_TESTSENDZLP +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB Feature selectors" +/// +/// This page lists codes of USB feature selectors. +/// +/// !Selectors +/// - USBFeatureRequest_ENDPOINTHALT +/// - USBFeatureRequest_DEVICEREMOTEWAKEUP +/// - USBFeatureRequest_TESTMODE + +/// Halt feature of an endpoint. +#define USBFeatureRequest_ENDPOINTHALT 0 +/// Remote wake-up feature of the device. +#define USBFeatureRequest_DEVICEREMOTEWAKEUP 1 +/// Test mode of the device. +#define USBFeatureRequest_TESTMODE 2 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB Test mode selectors" +/// +/// This page lists codes of USB high speed test mode selectors. +/// +/// !Selectors +/// - USBFeatureRequest_TESTJ +/// - USBFeatureRequest_TESTK +/// - USBFeatureRequest_TESTSE0NAK +/// - USBFeatureRequest_TESTPACKET +/// - USBFeatureRequest_TESTFORCEENABLE +/// - USBFeatureRequest_TESTSENDZLP + +/// Tests the high-output drive level on the D+ line. +#define USBFeatureRequest_TESTJ 1 +/// Tests the high-output drive level on the D- line. +#define USBFeatureRequest_TESTK 2 +/// Tests the output impedance, low-level output voltage and loading +/// characteristics. +#define USBFeatureRequest_TESTSE0NAK 3 +/// Tests rise and fall times, eye patterns and jitter. +#define USBFeatureRequest_TESTPACKET 4 +/// Tests the hub disconnect detection. +#define USBFeatureRequest_TESTFORCEENABLE 5 +/// Send a ZLP in Test Mode. +#define USBFeatureRequest_TESTSENDZLP 6 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +extern unsigned char USBFeatureRequest_GetFeatureSelector( + const USBGenericRequest *request); + + +extern unsigned char USBFeatureRequest_GetTestSelector( + const USBGenericRequest *request); + +#endif //#ifndef USBFEATUREREQUEST_H + diff --git a/at91lib/usb/common/core/USBGenericDescriptor.c b/at91lib/usb/common/core/USBGenericDescriptor.c new file mode 100644 index 0000000..99ed6f9 --- /dev/null +++ b/at91lib/usb/common/core/USBGenericDescriptor.c @@ -0,0 +1,80 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/* + Title: USBGenericDescriptor implementation + + About: Purpose + Implementation of the USBGenericDescriptor class. +*/ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "USBGenericDescriptor.h" + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Returns the length of a descriptor. +/// \param descriptor Pointer to a USBGenericDescriptor instance. +/// \return Length of descriptor in bytes. +//------------------------------------------------------------------------------ +unsigned int USBGenericDescriptor_GetLength( + const USBGenericDescriptor *descriptor) +{ + return descriptor->bLength; +} + +//------------------------------------------------------------------------------ +/// Returns the type of a descriptor. +/// \param descriptor Pointer to a USBGenericDescriptor instance. +/// \return Type of descriptor. +//------------------------------------------------------------------------------ +unsigned char USBGenericDescriptor_GetType( + const USBGenericDescriptor *descriptor) +{ + return descriptor->bDescriptorType; +} + +//------------------------------------------------------------------------------ +/// Returns a pointer to the descriptor right after the given one, when +/// parsing a Configuration descriptor. +/// \param descriptor - Pointer to a USBGenericDescriptor instance. +/// \return Pointer to the next descriptor. +//------------------------------------------------------------------------------ +USBGenericDescriptor *USBGenericDescriptor_GetNextDescriptor( + const USBGenericDescriptor *descriptor) +{ + return (USBGenericDescriptor *) + (((char *) descriptor) + USBGenericDescriptor_GetLength(descriptor)); +} diff --git a/at91lib/usb/common/core/USBGenericDescriptor.h b/at91lib/usb/common/core/USBGenericDescriptor.h new file mode 100644 index 0000000..b1237ae --- /dev/null +++ b/at91lib/usb/common/core/USBGenericDescriptor.h @@ -0,0 +1,133 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \unit +/// +/// !!!Purpose +/// +/// Definition of a generic USB descriptor class. +/// +/// !!!Usage +/// +/// -# Declare or access USB descriptors by USBGenericDescriptor instance. +/// -# To get usful information (field values) from the USB descriptors, use +/// - USBGenericDescriptor_GetLength +/// - USBGenericDescriptor_GetType +/// -# To scan the descriptors, use +/// - USBGenericDescriptor_GetNextDescriptor +//------------------------------------------------------------------------------ + +#ifndef USBGENERICDESCRIPTOR_H +#define USBGENERICDESCRIPTOR_H + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB Descriptor types" +/// +/// This page lists the codes of the usb descriptor types +/// +/// !Types +/// - USBGenericDescriptor_DEVICE +/// - USBGenericDescriptor_CONFIGURATION +/// - USBGenericDescriptor_STRING +/// - USBGenericDescriptor_INTERFACE +/// - USBGenericDescriptor_ENDPOINT +/// - USBGenericDescriptor_DEVICEQUALIFIER +/// - USBGenericDescriptor_OTHERSPEEDCONFIGURATION +/// - USBGenericDescriptor_INTERFACEPOWER +/// - USBGenericDescriptor_OTG +/// - USBGenericDescriptor_DEBUG +/// - USBGenericDescriptor_INTERFACEASSOCIATION + +/// Device descriptor type. +#define USBGenericDescriptor_DEVICE 1 +/// Configuration descriptor type. +#define USBGenericDescriptor_CONFIGURATION 2 +/// String descriptor type. +#define USBGenericDescriptor_STRING 3 +/// Interface descriptor type. +#define USBGenericDescriptor_INTERFACE 4 +/// Endpoint descriptor type. +#define USBGenericDescriptor_ENDPOINT 5 +/// Device qualifier descriptor type. +#define USBGenericDescriptor_DEVICEQUALIFIER 6 +/// Other speed configuration descriptor type. +#define USBGenericDescriptor_OTHERSPEEDCONFIGURATION 7 +/// Interface power descriptor type. +#define USBGenericDescriptor_INTERFACEPOWER 8 +/// On-The-Go descriptor type. +#define USBGenericDescriptor_OTG 9 +/// Debug descriptor type. +#define USBGenericDescriptor_DEBUG 10 +/// Interface association descriptor type. +#define USBGenericDescriptor_INTERFACEASSOCIATION 11 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Types +//------------------------------------------------------------------------------ + +#ifdef __ICCARM__ // IAR +#pragma pack(1) // IAR +#define __attribute__(...) // IAR +#endif // IAR + +/// Holds the few fields shared by all USB descriptors. +typedef struct { + + /// Length of the descriptor in bytes. + unsigned char bLength; + /// Descriptor type. + unsigned char bDescriptorType; + +} __attribute__ ((packed)) USBGenericDescriptor; // GCC + +#ifdef __ICCARM__ // IAR +#pragma pack() // IAR +#endif // IAR + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +extern unsigned int USBGenericDescriptor_GetLength( + const USBGenericDescriptor *descriptor); + +extern unsigned char USBGenericDescriptor_GetType( + const USBGenericDescriptor *descriptor); + +extern USBGenericDescriptor *USBGenericDescriptor_GetNextDescriptor( + const USBGenericDescriptor *descriptor); + +#endif //#ifndef USBGENERICDESCRIPTOR_H + diff --git a/at91lib/usb/common/core/USBGenericRequest.c b/at91lib/usb/common/core/USBGenericRequest.c new file mode 100644 index 0000000..a3bbbfd --- /dev/null +++ b/at91lib/usb/common/core/USBGenericRequest.c @@ -0,0 +1,138 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/* + Title: USBGenericRequest implementation + + About: Purpose + Implementation of the USBGenericRequest class. +*/ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "USBGenericRequest.h" + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +/// Returns the type of the given request. +/// \param request Pointer to a USBGenericRequest instance. +/// \return "USB Request Types" +//------------------------------------------------------------------------------ +extern unsigned char USBGenericRequest_GetType(const USBGenericRequest *request) +{ + return ((request->bmRequestType >> 5) & 0x3); +} + +//------------------------------------------------------------------------------ +/// Returns the request code of the given request. +/// \param request Pointer to a USBGenericRequest instance. +/// \return Request code. +/// \sa "USB Request Codes" +//------------------------------------------------------------------------------ +unsigned char USBGenericRequest_GetRequest(const USBGenericRequest *request) +{ + return request->bRequest; +} + +//------------------------------------------------------------------------------ +/// Returns the wValue field of the given request. +/// \param request - Pointer to a USBGenericRequest instance. +/// \return Request value. +//------------------------------------------------------------------------------ +unsigned short USBGenericRequest_GetValue(const USBGenericRequest *request) +{ + return request->wValue; +} + +//------------------------------------------------------------------------------ +/// Returns the wIndex field of the given request. +/// \param request Pointer to a USBGenericRequest instance. +/// \return Request index; +//------------------------------------------------------------------------------ +unsigned short USBGenericRequest_GetIndex(const USBGenericRequest *request) +{ + return request->wIndex; +} + +//------------------------------------------------------------------------------ +/// Returns the expected length of the data phase following a request. +/// \param request Pointer to a USBGenericRequest instance. +/// \return Length of data phase. +//------------------------------------------------------------------------------ +unsigned short USBGenericRequest_GetLength(const USBGenericRequest *request) +{ + return request->wLength; +} + +//------------------------------------------------------------------------------ +/// Returns the endpoint number targetted by a given request. +/// \param request Pointer to a USBGenericRequest instance. +/// \return Endpoint number. +//------------------------------------------------------------------------------ +unsigned char USBGenericRequest_GetEndpointNumber( + const USBGenericRequest *request) +{ + return USBGenericRequest_GetIndex(request) & 0xF; +} + +//------------------------------------------------------------------------------ +/// Returns the intended recipient of a given request. +/// \param request Pointer to a USBGenericRequest instance. +/// \return Request recipient. +/// \sa "USB Request Recipients" +//------------------------------------------------------------------------------ +unsigned char USBGenericRequest_GetRecipient(const USBGenericRequest *request) +{ + // Recipient is in bits [0..4] of the bmRequestType field + return request->bmRequestType & 0xF; +} + +//------------------------------------------------------------------------------ +/// Returns the direction of the data transfer following the given request. +/// \param request Pointer to a USBGenericRequest instance. +/// \return Transfer direction. +/// \sa "USB Request Directions" +//------------------------------------------------------------------------------ +unsigned char USBGenericRequest_GetDirection(const USBGenericRequest *request) +{ + // Transfer direction is located in bit D7 of the bmRequestType field + if ((request->bmRequestType & 0x80) != 0) { + + return USBGenericRequest_IN; + } + else { + + return USBGenericRequest_OUT; + } +} + diff --git a/at91lib/usb/common/core/USBGenericRequest.h b/at91lib/usb/common/core/USBGenericRequest.h new file mode 100644 index 0000000..77f8ca5 --- /dev/null +++ b/at91lib/usb/common/core/USBGenericRequest.h @@ -0,0 +1,244 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Definition of the USBGenericRequest class and its methods. + + !!!Usage + + -# Declare or access USB requests by USBGenericRequest instance. + -# To get usful information (field values) from the USB requests, use + - USBGenericRequest_GetType + - USBGenericRequest_GetRequest + - USBGenericRequest_GetValue + - USBGenericRequest_GetIndex + - USBGenericRequest_GetLength + - USBGenericRequest_GetEndpointNumber + - USBGenericRequest_GetRecipient + - USBGenericRequest_GetDirection +*/ + +#ifndef USBGENERICREQUEST_H +#define USBGENERICREQUEST_H + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB Generic Request definitions" +/// +/// This page lists the codes of USB generic request. +/// +/// - USB Request codes +/// - USBGenericRequest_GETSTATUS +/// - USBGenericRequest_CLEARFEATURE +/// - USBGenericRequest_SETFEATURE +/// - USBGenericRequest_SETADDRESS +/// - USBGenericRequest_GETDESCRIPTOR +/// - USBGenericRequest_SETDESCRIPTOR +/// - USBGenericRequest_GETCONFIGURATION +/// - USBGenericRequest_SETCONFIGURATION +/// - USBGenericRequest_GETINTERFACE +/// - USBGenericRequest_SETINTERFACE +/// - USBGenericRequest_SYNCHFRAME +/// +/// - USB Request Recipients +/// - USBGenericRequest_DEVICE +/// - USBGenericRequest_INTERFACE +/// - USBGenericRequest_ENDPOINT +/// - USBGenericRequest_OTHER +/// +/// - USB Request Types +/// - USBGenericRequest_STANDARD +/// - USBGenericRequest_CLASS +/// - USBGenericRequest_VENDOR +/// +/// - USB Request Directions +/// - USBGenericRequest_IN +/// - USBGenericRequest_OUT +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB Request codes" +/// +/// This page lists the USB generic request codes. +/// +/// !Codes +/// - USBGenericRequest_GETSTATUS +/// - USBGenericRequest_CLEARFEATURE +/// - USBGenericRequest_SETFEATURE +/// - USBGenericRequest_SETADDRESS +/// - USBGenericRequest_GETDESCRIPTOR +/// - USBGenericRequest_SETDESCRIPTOR +/// - USBGenericRequest_GETCONFIGURATION +/// - USBGenericRequest_SETCONFIGURATION +/// - USBGenericRequest_GETINTERFACE +/// - USBGenericRequest_SETINTERFACE +/// - USBGenericRequest_SYNCHFRAME + +/// GET_STATUS request code. +#define USBGenericRequest_GETSTATUS 0 +/// CLEAR_FEATURE request code. +#define USBGenericRequest_CLEARFEATURE 1 +/// SET_FEATURE request code. +#define USBGenericRequest_SETFEATURE 3 +/// SET_ADDRESS request code. +#define USBGenericRequest_SETADDRESS 5 +/// GET_DESCRIPTOR request code. +#define USBGenericRequest_GETDESCRIPTOR 6 +/// SET_DESCRIPTOR request code. +#define USBGenericRequest_SETDESCRIPTOR 7 +/// GET_CONFIGURATION request code. +#define USBGenericRequest_GETCONFIGURATION 8 +/// SET_CONFIGURATION request code. +#define USBGenericRequest_SETCONFIGURATION 9 +/// GET_INTERFACE request code. +#define USBGenericRequest_GETINTERFACE 10 +/// SET_INTERFACE request code. +#define USBGenericRequest_SETINTERFACE 11 +/// SYNCH_FRAME request code. +#define USBGenericRequest_SYNCHFRAME 12 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB Request Recipients" +/// +/// This page lists codes of USB request recipients. +/// +/// !Recipients +/// - USBGenericRequest_DEVICE +/// - USBGenericRequest_INTERFACE +/// - USBGenericRequest_ENDPOINT +/// - USBGenericRequest_OTHER + +/// Recipient is the whole device. +#define USBGenericRequest_DEVICE 0 +/// Recipient is an interface. +#define USBGenericRequest_INTERFACE 1 +/// Recipient is an endpoint. +#define USBGenericRequest_ENDPOINT 2 +/// Recipient is another entity. +#define USBGenericRequest_OTHER 3 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB Request Types" +/// +/// This page lists codes of USB request types. +/// +/// !Types +/// - USBGenericRequest_STANDARD +/// - USBGenericRequest_CLASS +/// - USBGenericRequest_VENDOR + +/// Request is standard. +#define USBGenericRequest_STANDARD 0 +/// Request is class-specific. +#define USBGenericRequest_CLASS 1 +/// Request is vendor-specific. +#define USBGenericRequest_VENDOR 2 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB Request Directions" +/// +/// This page lists codes of USB request directions. +/// +/// !Directions +/// - USBGenericRequest_IN +/// - USBGenericRequest_OUT + +/// Transfer occurs from device to the host. +#define USBGenericRequest_OUT 0 +/// Transfer occurs from the host to the device. +#define USBGenericRequest_IN 1 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Types +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Generic USB SETUP request sent over Control endpoints. +//------------------------------------------------------------------------------ +typedef struct { + + /// Type of request + /// \sa "USB Request Recipients" + /// \sa "USB Request Types" + /// \sa "USB Request Directions" + unsigned char bmRequestType:8; + /// Request code + /// \sa "USB Request Codes" + unsigned char bRequest:8; + /// Request-specific value parameter. + unsigned short wValue:16; + /// Request-specific index parameter. + unsigned short wIndex:16; + /// Expected length (in bytes) of the data phase. + unsigned short wLength:16; + +} USBGenericRequest; + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +extern unsigned char USBGenericRequest_GetType( + const USBGenericRequest *request); + + +extern unsigned char USBGenericRequest_GetRequest( + const USBGenericRequest *request); + +extern unsigned short USBGenericRequest_GetValue( + const USBGenericRequest *request); + +extern unsigned short USBGenericRequest_GetIndex( + const USBGenericRequest *request); + +extern unsigned short USBGenericRequest_GetLength( + const USBGenericRequest *request); + +extern unsigned char USBGenericRequest_GetEndpointNumber( + const USBGenericRequest *request); + +extern unsigned char USBGenericRequest_GetRecipient( + const USBGenericRequest *request); + +extern unsigned char USBGenericRequest_GetDirection( + const USBGenericRequest *request); + +#endif //#ifndef USBGENERICREQUEST_H + diff --git a/at91lib/usb/common/core/USBGetDescriptorRequest.c b/at91lib/usb/common/core/USBGetDescriptorRequest.c new file mode 100644 index 0000000..2937929 --- /dev/null +++ b/at91lib/usb/common/core/USBGetDescriptorRequest.c @@ -0,0 +1,72 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/* + Title: USBGetDescriptorRequest implementation + + About: Purpose + Implementation of the USBGetDescriptorRequest class. +*/ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "USBGetDescriptorRequest.h" + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Returns the type of the descriptor requested by the host given the +/// corresponding GET_DESCRIPTOR request. +/// \param request Pointer to a USBGenericDescriptor instance. +/// \return Type of the requested descriptor. +//------------------------------------------------------------------------------ +unsigned char USBGetDescriptorRequest_GetDescriptorType( + const USBGenericRequest *request) +{ + // Requested descriptor type is in the high-byte of the wValue field + return (USBGenericRequest_GetValue(request) >> 8) & 0xFF; +} + +//------------------------------------------------------------------------------ +/// Returns the index of the requested descriptor, given the corresponding +/// GET_DESCRIPTOR request. +/// \param request Pointer to a USBGenericDescriptor instance. +/// \return Index of the requested descriptor. +//------------------------------------------------------------------------------ +unsigned char USBGetDescriptorRequest_GetDescriptorIndex( + const USBGenericRequest *request) +{ + // Requested descriptor index if in the low byte of the wValue field + return USBGenericRequest_GetValue(request) & 0xFF; +} + diff --git a/at91lib/usb/common/core/USBGetDescriptorRequest.h b/at91lib/usb/common/core/USBGetDescriptorRequest.h new file mode 100644 index 0000000..43f6afd --- /dev/null +++ b/at91lib/usb/common/core/USBGetDescriptorRequest.h @@ -0,0 +1,67 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Definition of the USBGetDescriptorRequest class. + + !!!Usage + + - After a GET_DESCRIPTOR request has been received, retrive the useful + values with following functions: + - USBGetDescriptorRequest_GetDescriptorType: the descriptor type + - USBGetDescriptorRequest_GetDescriptorIndex: the index of the requested + descriptor + +*/ + +#ifndef USBGETDESCRIPTORREQUEST_H +#define USBGETDESCRIPTORREQUEST_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "USBGenericRequest.h" + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +extern unsigned char USBGetDescriptorRequest_GetDescriptorType( + const USBGenericRequest *request); + +extern unsigned char USBGetDescriptorRequest_GetDescriptorIndex( + const USBGenericRequest *request); + +#endif //#ifndef USBGETDESCRIPTORREQUEST_H + diff --git a/at91lib/usb/common/core/USBInterfaceDescriptor.h b/at91lib/usb/common/core/USBInterfaceDescriptor.h new file mode 100644 index 0000000..63910bf --- /dev/null +++ b/at91lib/usb/common/core/USBInterfaceDescriptor.h @@ -0,0 +1,87 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Definition of a class for manipulating USB interface descriptors. + + !!!Usage + + - Declare USBInterfaceDescriptor instance as a part of the configuration + descriptors of a USB device. + +*/ + +#ifndef USBINTERFACEDESCRIPTOR_H +#define USBINTERFACEDESCRIPTOR_H + +//------------------------------------------------------------------------------ +// Types +//------------------------------------------------------------------------------ + +#ifdef __ICCARM__ // IAR +#pragma pack(1) // IAR +#define __attribute__(...) // IAR +#endif // IAR + +//------------------------------------------------------------------------------ +/// USB standard interface descriptor structure. +//------------------------------------------------------------------------------ +typedef struct { + + /// Size of the descriptor in bytes. + unsigned char bLength; + /// Descriptor type (USBGenericDescriptor_INTERFACE). + unsigned char bDescriptorType; + /// Number of the interface in its configuration. + unsigned char bInterfaceNumber; + /// Value to select this alternate interface setting. + unsigned char bAlternateSetting; + /// Number of endpoints used by the inteface (excluding endpoint 0). + unsigned char bNumEndpoints; + /// Interface class code. + unsigned char bInterfaceClass; + /// Interface subclass code. + unsigned char bInterfaceSubClass; + /// Interface protocol code. + unsigned char bInterfaceProtocol; + /// Index of the interface string descriptor. + unsigned char iInterface; + +} __attribute__ ((packed)) USBInterfaceDescriptor; // GCC + +#ifdef __ICCARM__ // IAR +#pragma pack() // IAR +#endif // IAR + +#endif //#ifndef USBINTERFACEDESCRIPTOR_H + diff --git a/at91lib/usb/common/core/USBInterfaceRequest.c b/at91lib/usb/common/core/USBInterfaceRequest.c new file mode 100644 index 0000000..61bf6ed --- /dev/null +++ b/at91lib/usb/common/core/USBInterfaceRequest.c @@ -0,0 +1,69 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/* + Title: USBInterfaceRequest + + About: Purpose + Implementation of USBInterfaceRequest class methods. +*/ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "USBInterfaceRequest.h" + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Indicates which interface is targetted by a GET_INTERFACE or +/// SET_INTERFACE request. +/// \param request Pointer to a USBGenericRequest instance. +/// \return Interface number. +//------------------------------------------------------------------------------ +unsigned char USBInterfaceRequest_GetInterface(const USBGenericRequest *request) +{ + return (USBGenericRequest_GetIndex(request) & 0xFF); +} + +//------------------------------------------------------------------------------ +/// Indicates the new alternate setting that the interface targetted by a +/// SET_INTERFACE request should use. +/// \param request Pointer to a USBGenericRequest instance. +/// \return New active setting for the interface. +//------------------------------------------------------------------------------ +unsigned char USBInterfaceRequest_GetAlternateSetting( + const USBGenericRequest *request) +{ + return (USBGenericRequest_GetValue(request) & 0xFF); +} + diff --git a/at91lib/usb/common/core/USBInterfaceRequest.h b/at91lib/usb/common/core/USBInterfaceRequest.h new file mode 100644 index 0000000..bd4cddd --- /dev/null +++ b/at91lib/usb/common/core/USBInterfaceRequest.h @@ -0,0 +1,68 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Definitions for manipulating SET_INTERFACE and GET_INTERFACE request. + + !!!Usage + + -# After a SET_INTERFACE request has been received, retrieve the + target interface using USBInterfaceRequest_GetInterface and its + new alternate setting with USBInterfaceRequest_GetAlternateSetting. + -# After a GET_INTERFACE request has been received, retrieve the target + interface using USBInterfaceRequest_GetInterface. + +*/ + +#ifndef USBINTERFACEREQUEST_H +#define USBINTERFACEREQUEST_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "USBGenericRequest.h" + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +extern unsigned char USBInterfaceRequest_GetInterface( + const USBGenericRequest *request); + + +extern unsigned char USBInterfaceRequest_GetAlternateSetting( + const USBGenericRequest *request); + +#endif //#ifndef USBINTERFACEREQUEST_H + diff --git a/at91lib/usb/common/core/USBSetAddressRequest.c b/at91lib/usb/common/core/USBSetAddressRequest.c new file mode 100644 index 0000000..0e82a7f --- /dev/null +++ b/at91lib/usb/common/core/USBSetAddressRequest.c @@ -0,0 +1,56 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/* + Title: USBSetAddressRequest implementation + + About: Purpose + Implementation of the USBSetAddressRequest class. +*/ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "USBSetAddressRequest.h" + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +/// Returns the address that the device must take in response to a +/// SET_ADDRESS request. +/// \param request Pointer to a USBGenericRequest instance. +/// \return New device address. +//------------------------------------------------------------------------------ +unsigned char USBSetAddressRequest_GetAddress(const USBGenericRequest *request) +{ + return USBGenericRequest_GetValue(request) & 0x7F; +} + diff --git a/at91lib/usb/common/core/USBSetAddressRequest.h b/at91lib/usb/common/core/USBSetAddressRequest.h new file mode 100644 index 0000000..78034c3 --- /dev/null +++ b/at91lib/usb/common/core/USBSetAddressRequest.h @@ -0,0 +1,60 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Definition of a class for manipulating SET_ADDRESS USB requests. + + !!!Usage + + - After a SET_ADDRESS request has been received, retrive the new address + value with USBSetAddressRequest_GetAddress. +*/ + +#ifndef USBSETADDRESSREQUEST_H +#define USBSETADDRESSREQUEST_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "USBGenericRequest.h" + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +extern unsigned char USBSetAddressRequest_GetAddress( + const USBGenericRequest *request); + +#endif //#ifndef USBSETADDRESSREQUEST_H + diff --git a/at91lib/usb/common/core/USBSetConfigurationRequest.c b/at91lib/usb/common/core/USBSetConfigurationRequest.c new file mode 100644 index 0000000..3aa747d --- /dev/null +++ b/at91lib/usb/common/core/USBSetConfigurationRequest.c @@ -0,0 +1,58 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/* + Title: USBSetConfigurationRequest implementation + + About: Purpose + Implementation of the USBSetConfigurationRequest class. +*/ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "USBSetConfigurationRequest.h" + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Returns the number of the configuration that should be set in response +/// to the given SET_CONFIGURATION request. +/// \param request Pointer to a USBGenericRequest instance. +/// \return Number of the requested configuration. +//------------------------------------------------------------------------------ +unsigned char USBSetConfigurationRequest_GetConfiguration( + const USBGenericRequest *request) +{ + return USBGenericRequest_GetValue(request); +} + diff --git a/at91lib/usb/common/core/USBSetConfigurationRequest.h b/at91lib/usb/common/core/USBSetConfigurationRequest.h new file mode 100644 index 0000000..aa1fa17 --- /dev/null +++ b/at91lib/usb/common/core/USBSetConfigurationRequest.h @@ -0,0 +1,61 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Definition of a class for the Set Configuration request. + + !!!Usage + + - After a SET_CONFIGURATION request has been received, retrive the new + configuration value with USBSetConfigurationRequest_GetConfiguration. + +*/ + +#ifndef USBSETCONFIGURATIONREQUEST_H +#define USBSETCONFIGURATIONREQUEST_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "USBGenericRequest.h" + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +extern unsigned char USBSetConfigurationRequest_GetConfiguration( + const USBGenericRequest *request); + +#endif //#ifndef USBSETCONFIGURATIONREQUEST_H + diff --git a/at91lib/usb/common/core/USBStringDescriptor.h b/at91lib/usb/common/core/USBStringDescriptor.h new file mode 100644 index 0000000..bcf4b83 --- /dev/null +++ b/at91lib/usb/common/core/USBStringDescriptor.h @@ -0,0 +1,74 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \unit +/// +/// !!!Purpose +/// +/// Definition of a class for manipulating String descriptors. +//------------------------------------------------------------------------------ + +#ifndef USBSTRINGDESCRIPTOR_H +#define USBSTRINGDESCRIPTOR_H + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB String Descriptor definitions" +/// +/// This page lists the codes and macros for USB string descriptor definition. +/// +/// !Language IDs +/// - USBStringDescriptor_ENGLISH_US +/// +/// !String Descriptor Length +/// - USBStringDescriptor_LENGTH +/// +/// !ASCII to UNICODE convertion +/// - USBStringDescriptor_UNICODE + +/// Language ID for US english. +#define USBStringDescriptor_ENGLISH_US 0x09, 0x04 + +/// Calculates the length of a string descriptor given the number of ascii +/// characters/language IDs in it. +/// \param length The ascii format string length. +/// \return The actual data length in bytes. +#define USBStringDescriptor_LENGTH(length) ((length) * 2 + 2) +/// Converts an ascii character to its unicode representation. +/// \param ascii The ASCII character to convert +/// \return A 2-byte-array for the UNICODE based on given ASCII +#define USBStringDescriptor_UNICODE(ascii) (ascii), 0 +//------------------------------------------------------------------------------ + +#endif //#ifndef USBSTRINGDESCRIPTOR_H + diff --git a/at91lib/usb/device/cdc-serial/CDCDSerialDriver.c b/at91lib/usb/device/cdc-serial/CDCDSerialDriver.c new file mode 100644 index 0000000..3e58592 --- /dev/null +++ b/at91lib/usb/device/cdc-serial/CDCDSerialDriver.c @@ -0,0 +1,300 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/* + Title: CDCDSerialDriver implementation + + About: Purpose + Implementation of the CDCDSerialDriver class methods. +*/ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "CDCDSerialDriver.h" +#include "CDCDSerialDriverDescriptors.h" +#include +#include +#include +#include +#include +#include + +//------------------------------------------------------------------------------ +// Types +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// USB driver for a CDC class implementing a virtual COM serial connection. +//------------------------------------------------------------------------------ +typedef struct { + + /// Standard USBDDriver instance. + USBDDriver usbdDriver; + /// Current line coding (baudrate, parity, stop bits). + CDCLineCoding lineCoding; + /// Indicates if the RS232 carrier is active. + unsigned char isCarrierActivated; + /// Current serial port states + unsigned short serialState; + +} CDCDSerialDriver; + +//------------------------------------------------------------------------------ +// Internal variables +//------------------------------------------------------------------------------ + +/// Static instance of the CDC serial driver. +static CDCDSerialDriver cdcdSerialDriver; + +//------------------------------------------------------------------------------ +// Internal functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Callback function which should be invoked after the data of a +/// SetLineCoding request has been retrieved. Sends a zero-length packet +/// to the host for acknowledging the request. +//------------------------------------------------------------------------------ +static void CDCDSerialDriver_SetLineCodingCallback() +{ + USBD_Write(0, 0, 0, 0, 0); +} + +//------------------------------------------------------------------------------ +/// Receives new line coding information from the USB host. +//------------------------------------------------------------------------------ +static void CDCDSerialDriver_SetLineCoding() +{ + TRACE_INFO_WP("sLineCoding "); + + USBD_Read(0, + (void *) &(cdcdSerialDriver.lineCoding), + sizeof(CDCLineCoding), + (TransferCallback) CDCDSerialDriver_SetLineCodingCallback, + 0); +} + +//------------------------------------------------------------------------------ +/// Sends the current line coding information to the host through Control +/// endpoint 0. +//------------------------------------------------------------------------------ +static void CDCDSerialDriver_GetLineCoding() +{ + TRACE_INFO_WP("gLineCoding "); + + USBD_Write(0, + (void *) &(cdcdSerialDriver.lineCoding), + sizeof(CDCLineCoding), + 0, + 0); +} + +//------------------------------------------------------------------------------ +/// Changes the state of the serial driver according to the information +/// sent by the host via a SetControlLineState request, and acknowledges +/// the request with a zero-length packet. +//------------------------------------------------------------------------------ +static void CDCDSerialDriver_SetControlLineState(unsigned char activateCarrier, + unsigned char isDTEPresent) +{ + TRACE_INFO_WP( + "sControlLineState(%d, %d) ", + activateCarrier, + isDTEPresent); + + cdcdSerialDriver.isCarrierActivated = activateCarrier; + USBD_Write(0, 0, 0, 0, 0); +} + +//------------------------------------------------------------------------------ +// Optional RequestReceived() callback re-implementation +//------------------------------------------------------------------------------ +#if !defined(NOAUTOCALLBACK) + +//------------------------------------------------------------------------------ +/// Re-implemented callback, invoked when a new USB Request is received. +//------------------------------------------------------------------------------ +void USBDCallbacks_RequestReceived(const USBGenericRequest *request) +{ + CDCDSerialDriver_RequestHandler(request); +} + +#endif + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Initializes the USB Device CDC serial driver & USBD Driver. +//------------------------------------------------------------------------------ +void CDCDSerialDriver_Initialize() +{ + TRACE_INFO("CDCDSerialDriver_Initialize\n\r"); + + // Initialize Abstract Control Model attributes + CDCLineCoding_Initialize(&(cdcdSerialDriver.lineCoding), + 115200, + CDCLineCoding_ONESTOPBIT, + CDCLineCoding_NOPARITY, + 8); + cdcdSerialDriver.isCarrierActivated = 0; + cdcdSerialDriver.serialState = 0; + + // Initialize the standard driver + USBDDriver_Initialize(&(cdcdSerialDriver.usbdDriver), + &cdcdSerialDriverDescriptors, + 0); // Multiple settings for interfaces not supported + + // Initialize the USB driver + USBD_Init(); +} + +//------------------------------------------------------------------------------ +/// Handles CDC-specific SETUP requests. Should be called from a +/// re-implementation of USBDCallbacks_RequestReceived() method. +/// \param Pointer to a USBGenericRequest instance. +//------------------------------------------------------------------------------ +void CDCDSerialDriver_RequestHandler(const USBGenericRequest *request) +{ + TRACE_INFO_WP("NewReq "); + + // Handle the request + switch (USBGenericRequest_GetRequest(request)) { + + case CDCGenericRequest_SETLINECODING: + + CDCDSerialDriver_SetLineCoding(); + break; + + case CDCGenericRequest_GETLINECODING: + + CDCDSerialDriver_GetLineCoding(); + break; + + case CDCGenericRequest_SETCONTROLLINESTATE: + + CDCDSerialDriver_SetControlLineState( + CDCSetControlLineStateRequest_ActivateCarrier(request), + CDCSetControlLineStateRequest_IsDtePresent(request)); + + break; + + default: + + USBDDriver_RequestHandler(&(cdcdSerialDriver.usbdDriver), request); + break; + } +} + +//------------------------------------------------------------------------------ +/// Receives data from the host through the virtual COM port created by +/// the CDC device serial driver. This function behaves like USBD_Read. +/// \param data Pointer to the data buffer to put received data. +/// \param size Size of the data buffer in bytes. +/// \param callback Optional callback function to invoke when the transfer +/// finishes. +/// \param argument Optional argument to the callback function. +/// \return USBD_STATUS_SUCCESS if the read operation has been started normally; +/// otherwise, the corresponding error code. +//------------------------------------------------------------------------------ +unsigned char CDCDSerialDriver_Read(void *data, + unsigned int size, + TransferCallback callback, + void *argument) +{ + return USBD_Read(CDCDSerialDriverDescriptors_DATAOUT, + data, + size, + callback, + argument); +} + +//------------------------------------------------------------------------------ +/// Sends a data buffer through the virtual COM port created by the CDC +/// device serial driver. This function behaves exactly like USBD_Write. +/// \param data Pointer to the data buffer to send. +/// \param size Size of the data buffer in bytes. +/// \param callback Optional callback function to invoke when the transfer +/// finishes. +/// \param argument Optional argument to the callback function. +/// \return USBD_STATUS_SUCCESS if the read operation has been started normally; +/// otherwise, the corresponding error code. +//------------------------------------------------------------------------------ +unsigned char CDCDSerialDriver_Write(void *data, + unsigned int size, + TransferCallback callback, + void *argument) +{ + return USBD_Write(CDCDSerialDriverDescriptors_DATAIN, + data, + size, + callback, + argument); +} + +//------------------------------------------------------------------------------ +/// Returns the current status of the RS-232 line. +//------------------------------------------------------------------------------ +unsigned short CDCDSerialDriver_GetSerialState() +{ + return cdcdSerialDriver.serialState; +} + +//------------------------------------------------------------------------------ +/// Sets the current serial state of the device to the given value. +/// \param serialState New device state. +//------------------------------------------------------------------------------ +void CDCDSerialDriver_SetSerialState(unsigned short serialState) +{ + ASSERT((serialState & 0xFF80) == 0, + "CDCDSerialDriver_SetSerialState: Bits D7-D15 are reserved\n\r"); + + // If new state is different from previous one, send a notification to the + // host + if (cdcdSerialDriver.serialState != serialState) { + + cdcdSerialDriver.serialState = serialState; + USBD_Write(CDCDSerialDriverDescriptors_NOTIFICATION, + &(cdcdSerialDriver.serialState), + 2, + 0, + 0); + + // Reset one-time flags + cdcdSerialDriver.serialState &= ~(CDCDSerialDriver_STATE_OVERRUN + | CDCDSerialDriver_STATE_PARITY + | CDCDSerialDriver_STATE_FRAMING + | CDCDSerialDriver_STATE_RINGSIGNAL + | CDCDSerialDriver_STATE_BREAK); + } +} + diff --git a/at91lib/usb/device/cdc-serial/CDCDSerialDriver.h b/at91lib/usb/device/cdc-serial/CDCDSerialDriver.h new file mode 100644 index 0000000..5ccc901 --- /dev/null +++ b/at91lib/usb/device/cdc-serial/CDCDSerialDriver.h @@ -0,0 +1,117 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Definition of a class for implementing a USB device CDC serial driver. + + !!!Usage + + -# Re-implement the USBDCallbacks_RequestReceived method to pass + received requests to CDCDSerialDriver_RequestHandler. *This is + automatically done unless the NOAUTOCALLBACK symbol is defined*. + -# Initialize the CDC serial and USB drivers using + CDCDSerialDriver_Initialize. + -# Logically connect the device to the host using USBD_Connect. + -# Send serial data to the USB host using CDCDSerialDriver_Write. + -# Receive serial data from the USB host using CDCDSerialDriver_Read. +*/ + +#ifndef CDCDSERIALDRIVER_H +#define CDCDSERIALDRIVER_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include +#include + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "CDC Serial Port States" +/// This page lists the bit map for CDC Serial Port States. +/// +/// !BitMaps +/// - CDCDSerialDriver_STATE_RXDRIVER +/// - CDCDSerialDriver_STATE_TXCARRIER +/// - CDCDSerialDriver_STATE_BREAK +/// - CDCDSerialDriver_STATE_RINGSIGNAL +/// - CDCDSerialDriver_STATE_FRAMING +/// - CDCDSerialDriver_STATE_PARITY +/// - CDCDSerialDriver_STATE_OVERRUN + +/// Indicates the receiver carrier signal is present. +#define CDCDSerialDriver_STATE_RXDRIVER (1 << 0) +/// Indicates the transmission carrier signal is present. +#define CDCDSerialDriver_STATE_TXCARRIER (1 << 1) +/// Indicates a break has been detected. +#define CDCDSerialDriver_STATE_BREAK (1 << 2) +/// Indicates a ring signal has been detected. +#define CDCDSerialDriver_STATE_RINGSIGNAL (1 << 3) +/// Indicates a framing error has occured. +#define CDCDSerialDriver_STATE_FRAMING (1 << 4) +/// Indicates a parity error has occured. +#define CDCDSerialDriver_STATE_PARITY (1 << 5) +/// Indicates a data overrun error has occured. +#define CDCDSerialDriver_STATE_OVERRUN (1 << 6) +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +extern void CDCDSerialDriver_Initialize(); + +extern void CDCDSerialDriver_RequestHandler(const USBGenericRequest *request); + +extern unsigned char CDCDSerialDriver_Write( + void *data, + unsigned int size, + TransferCallback callback, + void *argument); + +extern unsigned char CDCDSerialDriver_Read( + void *data, + unsigned int size, + TransferCallback callback, + void *argument); + +extern unsigned short CDCDSerialDriver_GetSerialState(); + +extern void CDCDSerialDriver_SetSerialState(unsigned short serialState); + +#endif //#ifndef CDCSERIALDRIVER_H + diff --git a/at91lib/usb/device/cdc-serial/CDCDSerialDriverDescriptors.c b/at91lib/usb/device/cdc-serial/CDCDSerialDriverDescriptors.c new file mode 100644 index 0000000..0c900e1 --- /dev/null +++ b/at91lib/usb/device/cdc-serial/CDCDSerialDriverDescriptors.c @@ -0,0 +1,625 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "CDCDSerialDriverDescriptors.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "CDC Serial Device IDs" +/// This page lists the IDs used in the CDC Serial Device Descriptor. +/// +/// !IDs +/// - CDCDSerialDriverDescriptors_PRODUCTID +/// - CDCDSerialDriverDescriptors_VENDORID +/// - CDCDSerialDriverDescriptors_RELEASE + +/// Device product ID. +#define CDCDSerialDriverDescriptors_PRODUCTID 0x6119 +/// Device vendor ID (Atmel). +#define CDCDSerialDriverDescriptors_VENDORID 0x03EB +/// Device release number. +#define CDCDSerialDriverDescriptors_RELEASE 0x0100 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Macros +//------------------------------------------------------------------------------ + +/// Returns the minimum between two values. +#define MIN(a, b) ((a < b) ? a : b) + +//------------------------------------------------------------------------------ +// Internal structures +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Configuration descriptor list for a device implementing a CDC serial driver. +//------------------------------------------------------------------------------ +typedef struct { + + /// Standard configuration descriptor. + USBConfigurationDescriptor configuration; + /// Communication interface descriptor. + USBInterfaceDescriptor communication; + /// CDC header functional descriptor. + CDCHeaderDescriptor header; + /// CDC call management functional descriptor. + CDCCallManagementDescriptor callManagement; + /// CDC abstract control management functional descriptor. + CDCAbstractControlManagementDescriptor abstractControlManagement; + /// CDC union functional descriptor (with one slave interface). + CDCUnionDescriptor union1; + /// Notification endpoint descriptor. + USBEndpointDescriptor notification; + /// Data interface descriptor. + USBInterfaceDescriptor data; + /// Data OUT endpoint descriptor. + USBEndpointDescriptor dataOut; + /// Data IN endpoint descriptor. + USBEndpointDescriptor dataIn; + +} __attribute__ ((packed)) CDCDSerialDriverConfigurationDescriptors; + +//------------------------------------------------------------------------------ +// Exported variables +//------------------------------------------------------------------------------ + +/// Standard USB device descriptor for the CDC serial driver +const USBDeviceDescriptor deviceDescriptor = { + + sizeof(USBDeviceDescriptor), + USBGenericDescriptor_DEVICE, + USBDeviceDescriptor_USB2_00, + CDCDeviceDescriptor_CLASS, + CDCDeviceDescriptor_SUBCLASS, + CDCDeviceDescriptor_PROTOCOL, + BOARD_USB_ENDPOINTS_MAXPACKETSIZE(0), + CDCDSerialDriverDescriptors_VENDORID, + CDCDSerialDriverDescriptors_PRODUCTID, + CDCDSerialDriverDescriptors_RELEASE, + 0, // No string descriptor for manufacturer + 1, // Index of product string descriptor is #1 + 0, // No string descriptor for serial number + 1 // Device has 1 possible configuration +}; + +#if defined(BOARD_USB_UDPHS) + +/// USB device qualifier descriptor. +const USBDeviceQualifierDescriptor qualifierDescriptor = { + + sizeof(USBDeviceQualifierDescriptor), + USBGenericDescriptor_DEVICEQUALIFIER, + USBDeviceDescriptor_USB2_00, + CDCDeviceDescriptor_CLASS, + CDCDeviceDescriptor_SUBCLASS, + CDCDeviceDescriptor_PROTOCOL, + BOARD_USB_ENDPOINTS_MAXPACKETSIZE(0), + 1, // Device has one possible configuration + 0 // Reserved +}; + +#endif + +/// Standard USB configuration descriptor for the CDC serial driver +const CDCDSerialDriverConfigurationDescriptors configurationDescriptors = { + + // Standard configuration descriptor + { + sizeof(USBConfigurationDescriptor), + USBGenericDescriptor_CONFIGURATION, + sizeof(CDCDSerialDriverConfigurationDescriptors), + 2, // There are two interfaces in this configuration + 1, // This is configuration #1 + 0, // No string descriptor for this configuration + BOARD_USB_BMATTRIBUTES, + USBConfigurationDescriptor_POWER(100) + }, + // Communication class interface standard descriptor + { + sizeof(USBInterfaceDescriptor), + USBGenericDescriptor_INTERFACE, + 0, // This is interface #0 + 0, // This is alternate setting #0 for this interface + 1, // This interface uses 1 endpoint + CDCCommunicationInterfaceDescriptor_CLASS, + CDCCommunicationInterfaceDescriptor_ABSTRACTCONTROLMODEL, + CDCCommunicationInterfaceDescriptor_NOPROTOCOL, + 0 // No string descriptor for this interface + }, + // Class-specific header functional descriptor + { + sizeof(CDCHeaderDescriptor), + CDCGenericDescriptor_INTERFACE, + CDCGenericDescriptor_HEADER, + CDCGenericDescriptor_CDC1_10 + }, + // Class-specific call management functional descriptor + { + sizeof(CDCCallManagementDescriptor), + CDCGenericDescriptor_INTERFACE, + CDCGenericDescriptor_CALLMANAGEMENT, + CDCCallManagementDescriptor_SELFCALLMANAGEMENT, + 0 // No associated data interface + }, + // Class-specific abstract control management functional descriptor + { + sizeof(CDCAbstractControlManagementDescriptor), + CDCGenericDescriptor_INTERFACE, + CDCGenericDescriptor_ABSTRACTCONTROLMANAGEMENT, + CDCAbstractControlManagementDescriptor_LINE + }, + // Class-specific union functional descriptor with one slave interface + { + sizeof(CDCUnionDescriptor), + CDCGenericDescriptor_INTERFACE, + CDCGenericDescriptor_UNION, + 0, // Number of master interface is #0 + 1 // First slave interface is #1 + }, + // Notification endpoint standard descriptor + { + sizeof(USBEndpointDescriptor), + USBGenericDescriptor_ENDPOINT, + USBEndpointDescriptor_ADDRESS(USBEndpointDescriptor_IN, + CDCDSerialDriverDescriptors_NOTIFICATION), + USBEndpointDescriptor_INTERRUPT, + MIN(BOARD_USB_ENDPOINTS_MAXPACKETSIZE(CDCDSerialDriverDescriptors_NOTIFICATION), + USBEndpointDescriptor_MAXINTERRUPTSIZE_FS), + 10 // Endpoint is polled every 10ms + }, + // Data class interface standard descriptor + { + sizeof(USBInterfaceDescriptor), + USBGenericDescriptor_INTERFACE, + 1, // This is interface #1 + 0, // This is alternate setting #0 for this interface + 2, // This interface uses 2 endpoints + CDCDataInterfaceDescriptor_CLASS, + CDCDataInterfaceDescriptor_SUBCLASS, + CDCDataInterfaceDescriptor_NOPROTOCOL, + 0 // No string descriptor for this interface + }, + // Bulk-OUT endpoint standard descriptor + { + sizeof(USBEndpointDescriptor), + USBGenericDescriptor_ENDPOINT, + USBEndpointDescriptor_ADDRESS(USBEndpointDescriptor_OUT, + CDCDSerialDriverDescriptors_DATAOUT), + USBEndpointDescriptor_BULK, + MIN(BOARD_USB_ENDPOINTS_MAXPACKETSIZE(CDCDSerialDriverDescriptors_DATAOUT), + USBEndpointDescriptor_MAXBULKSIZE_FS), + 0 // Must be 0 for full-speed bulk endpoints + }, + // Bulk-IN endpoint descriptor + { + sizeof(USBEndpointDescriptor), + USBGenericDescriptor_ENDPOINT, + USBEndpointDescriptor_ADDRESS(USBEndpointDescriptor_IN, + CDCDSerialDriverDescriptors_DATAIN), + USBEndpointDescriptor_BULK, + MIN(BOARD_USB_ENDPOINTS_MAXPACKETSIZE(CDCDSerialDriverDescriptors_DATAIN), + USBEndpointDescriptor_MAXBULKSIZE_FS), + 0 // Must be 0 for full-speed bulk endpoints + }, +}; + +/// Language ID string descriptor +const unsigned char languageIdStringDescriptor[] = { + + USBStringDescriptor_LENGTH(1), + USBGenericDescriptor_STRING, + USBStringDescriptor_ENGLISH_US +}; + +#if defined(BOARD_USB_UDPHS) +/// Other-speed configuration descriptor (when in full-speed). +const CDCDSerialDriverConfigurationDescriptors otherSpeedDescriptorsFS = { + + // Standard configuration descriptor + { + sizeof(USBConfigurationDescriptor), + USBGenericDescriptor_OTHERSPEEDCONFIGURATION, + sizeof(CDCDSerialDriverConfigurationDescriptors), + 2, // There are two interfaces in this configuration + 1, // This is configuration #1 + 0, // No string descriptor for this configuration + BOARD_USB_BMATTRIBUTES, + USBConfigurationDescriptor_POWER(100) + }, + // Communication class interface standard descriptor + { + sizeof(USBInterfaceDescriptor), + USBGenericDescriptor_INTERFACE, + 0, // This is interface #0 + 0, // This is alternate setting #0 for this interface + 1, // This interface uses 1 endpoint + CDCCommunicationInterfaceDescriptor_CLASS, + CDCCommunicationInterfaceDescriptor_ABSTRACTCONTROLMODEL, + CDCCommunicationInterfaceDescriptor_NOPROTOCOL, + 0 // No string descriptor for this interface + }, + // Class-specific header functional descriptor + { + sizeof(CDCHeaderDescriptor), + CDCGenericDescriptor_INTERFACE, + CDCGenericDescriptor_HEADER, + CDCGenericDescriptor_CDC1_10 + }, + // Class-specific call management functional descriptor + { + sizeof(CDCCallManagementDescriptor), + CDCGenericDescriptor_INTERFACE, + CDCGenericDescriptor_CALLMANAGEMENT, + CDCCallManagementDescriptor_SELFCALLMANAGEMENT, + 0 // No associated data interface + }, + // Class-specific abstract control management functional descriptor + { + sizeof(CDCAbstractControlManagementDescriptor), + CDCGenericDescriptor_INTERFACE, + CDCGenericDescriptor_ABSTRACTCONTROLMANAGEMENT, + CDCAbstractControlManagementDescriptor_LINE + }, + // Class-specific union functional descriptor with one slave interface + { + sizeof(CDCUnionDescriptor), + CDCGenericDescriptor_INTERFACE, + CDCGenericDescriptor_UNION, + 0, // Number of master interface is #0 + 1 // First slave interface is #1 + }, + // Notification endpoint standard descriptor + { + sizeof(USBEndpointDescriptor), + USBGenericDescriptor_ENDPOINT, + USBEndpointDescriptor_ADDRESS(USBEndpointDescriptor_IN, + CDCDSerialDriverDescriptors_NOTIFICATION), + USBEndpointDescriptor_INTERRUPT, + MIN(BOARD_USB_ENDPOINTS_MAXPACKETSIZE(CDCDSerialDriverDescriptors_NOTIFICATION), + USBEndpointDescriptor_MAXINTERRUPTSIZE_HS), + 10 // Endpoint is polled every 10ms + }, + // Data class interface standard descriptor + { + sizeof(USBInterfaceDescriptor), + USBGenericDescriptor_INTERFACE, + 1, // This is interface #1 + 0, // This is alternate setting #0 for this interface + 2, // This interface uses 2 endpoints + CDCDataInterfaceDescriptor_CLASS, + CDCDataInterfaceDescriptor_SUBCLASS, + CDCDataInterfaceDescriptor_NOPROTOCOL, + 0 // No string descriptor for this interface + }, + // Bulk-OUT endpoint standard descriptor + { + sizeof(USBEndpointDescriptor), + USBGenericDescriptor_ENDPOINT, + USBEndpointDescriptor_ADDRESS(USBEndpointDescriptor_OUT, + CDCDSerialDriverDescriptors_DATAOUT), + USBEndpointDescriptor_BULK, + MIN(BOARD_USB_ENDPOINTS_MAXPACKETSIZE(CDCDSerialDriverDescriptors_DATAOUT), + USBEndpointDescriptor_MAXBULKSIZE_HS), + 0 // Must be 0 for full-speed bulk endpoints + }, + // Bulk-IN endpoint descriptor + { + sizeof(USBEndpointDescriptor), + USBGenericDescriptor_ENDPOINT, + USBEndpointDescriptor_ADDRESS(USBEndpointDescriptor_IN, + CDCDSerialDriverDescriptors_DATAIN), + USBEndpointDescriptor_BULK, + MIN(BOARD_USB_ENDPOINTS_MAXPACKETSIZE(CDCDSerialDriverDescriptors_DATAIN), + USBEndpointDescriptor_MAXBULKSIZE_HS), + 0 // Must be 0 for full-speed bulk endpoints + }, +}; + + +/// Configuration descriptor (when in high-speed). +const CDCDSerialDriverConfigurationDescriptors configurationDescriptorsHS = { + + // Standard configuration descriptor + { + sizeof(USBConfigurationDescriptor), + USBGenericDescriptor_CONFIGURATION, + sizeof(CDCDSerialDriverConfigurationDescriptors), + 2, // There are two interfaces in this configuration + 1, // This is configuration #1 + 0, // No string descriptor for this configuration + BOARD_USB_BMATTRIBUTES, + USBConfigurationDescriptor_POWER(100) + }, + // Communication class interface standard descriptor + { + sizeof(USBInterfaceDescriptor), + USBGenericDescriptor_INTERFACE, + 0, // This is interface #0 + 0, // This is alternate setting #0 for this interface + 1, // This interface uses 1 endpoint + CDCCommunicationInterfaceDescriptor_CLASS, + CDCCommunicationInterfaceDescriptor_ABSTRACTCONTROLMODEL, + CDCCommunicationInterfaceDescriptor_NOPROTOCOL, + 0 // No string descriptor for this interface + }, + // Class-specific header functional descriptor + { + sizeof(CDCHeaderDescriptor), + CDCGenericDescriptor_INTERFACE, + CDCGenericDescriptor_HEADER, + CDCGenericDescriptor_CDC1_10 + }, + // Class-specific call management functional descriptor + { + sizeof(CDCCallManagementDescriptor), + CDCGenericDescriptor_INTERFACE, + CDCGenericDescriptor_CALLMANAGEMENT, + CDCCallManagementDescriptor_SELFCALLMANAGEMENT, + 0 // No associated data interface + }, + // Class-specific abstract control management functional descriptor + { + sizeof(CDCAbstractControlManagementDescriptor), + CDCGenericDescriptor_INTERFACE, + CDCGenericDescriptor_ABSTRACTCONTROLMANAGEMENT, + CDCAbstractControlManagementDescriptor_LINE + }, + // Class-specific union functional descriptor with one slave interface + { + sizeof(CDCUnionDescriptor), + CDCGenericDescriptor_INTERFACE, + CDCGenericDescriptor_UNION, + 0, // Number of master interface is #0 + 1 // First slave interface is #1 + }, + // Notification endpoint standard descriptor + { + sizeof(USBEndpointDescriptor), + USBGenericDescriptor_ENDPOINT, + USBEndpointDescriptor_ADDRESS(USBEndpointDescriptor_IN, + CDCDSerialDriverDescriptors_NOTIFICATION), + USBEndpointDescriptor_INTERRUPT, + MIN(BOARD_USB_ENDPOINTS_MAXPACKETSIZE(CDCDSerialDriverDescriptors_NOTIFICATION), + USBEndpointDescriptor_MAXINTERRUPTSIZE_HS), + 10 // Endpoint is polled every 10ms + }, + // Data class interface standard descriptor + { + sizeof(USBInterfaceDescriptor), + USBGenericDescriptor_INTERFACE, + 1, // This is interface #1 + 0, // This is alternate setting #0 for this interface + 2, // This interface uses 2 endpoints + CDCDataInterfaceDescriptor_CLASS, + CDCDataInterfaceDescriptor_SUBCLASS, + CDCDataInterfaceDescriptor_NOPROTOCOL, + 0 // No string descriptor for this interface + }, + // Bulk-OUT endpoint standard descriptor + { + sizeof(USBEndpointDescriptor), + USBGenericDescriptor_ENDPOINT, + USBEndpointDescriptor_ADDRESS(USBEndpointDescriptor_OUT, + CDCDSerialDriverDescriptors_DATAOUT), + USBEndpointDescriptor_BULK, + MIN(BOARD_USB_ENDPOINTS_MAXPACKETSIZE(CDCDSerialDriverDescriptors_DATAOUT), + USBEndpointDescriptor_MAXBULKSIZE_HS), + 0 // Must be 0 for full-speed bulk endpoints + }, + // Bulk-IN endpoint descriptor + { + sizeof(USBEndpointDescriptor), + USBGenericDescriptor_ENDPOINT, + USBEndpointDescriptor_ADDRESS(USBEndpointDescriptor_IN, + CDCDSerialDriverDescriptors_DATAIN), + USBEndpointDescriptor_BULK, + MIN(BOARD_USB_ENDPOINTS_MAXPACKETSIZE(CDCDSerialDriverDescriptors_DATAIN), + USBEndpointDescriptor_MAXBULKSIZE_HS), + 0 // Must be 0 for full-speed bulk endpoints + }, +}; + +/// Other-speed configuration descriptor (when in high-speed). +const CDCDSerialDriverConfigurationDescriptors otherSpeedDescriptorsHS = { + + // Standard configuration descriptor + { + sizeof(USBConfigurationDescriptor), + USBGenericDescriptor_OTHERSPEEDCONFIGURATION, + sizeof(CDCDSerialDriverConfigurationDescriptors), + 2, // There are two interfaces in this configuration + 1, // This is configuration #1 + 0, // No string descriptor for this configuration + BOARD_USB_BMATTRIBUTES, + USBConfigurationDescriptor_POWER(100) + }, + // Communication class interface standard descriptor + { + sizeof(USBInterfaceDescriptor), + USBGenericDescriptor_INTERFACE, + 0, // This is interface #0 + 0, // This is alternate setting #0 for this interface + 1, // This interface uses 1 endpoint + CDCCommunicationInterfaceDescriptor_CLASS, + CDCCommunicationInterfaceDescriptor_ABSTRACTCONTROLMODEL, + CDCCommunicationInterfaceDescriptor_NOPROTOCOL, + 0 // No string descriptor for this interface + }, + // Class-specific header functional descriptor + { + sizeof(CDCHeaderDescriptor), + CDCGenericDescriptor_INTERFACE, + CDCGenericDescriptor_HEADER, + CDCGenericDescriptor_CDC1_10 + }, + // Class-specific call management functional descriptor + { + sizeof(CDCCallManagementDescriptor), + CDCGenericDescriptor_INTERFACE, + CDCGenericDescriptor_CALLMANAGEMENT, + CDCCallManagementDescriptor_SELFCALLMANAGEMENT, + 0 // No associated data interface + }, + // Class-specific abstract control management functional descriptor + { + sizeof(CDCAbstractControlManagementDescriptor), + CDCGenericDescriptor_INTERFACE, + CDCGenericDescriptor_ABSTRACTCONTROLMANAGEMENT, + CDCAbstractControlManagementDescriptor_LINE + }, + // Class-specific union functional descriptor with one slave interface + { + sizeof(CDCUnionDescriptor), + CDCGenericDescriptor_INTERFACE, + CDCGenericDescriptor_UNION, + 0, // Number of master interface is #0 + 1 // First slave interface is #1 + }, + // Notification endpoint standard descriptor + { + sizeof(USBEndpointDescriptor), + USBGenericDescriptor_ENDPOINT, + USBEndpointDescriptor_ADDRESS(USBEndpointDescriptor_IN, + CDCDSerialDriverDescriptors_NOTIFICATION), + USBEndpointDescriptor_INTERRUPT, + MIN(BOARD_USB_ENDPOINTS_MAXPACKETSIZE(CDCDSerialDriverDescriptors_NOTIFICATION), + USBEndpointDescriptor_MAXINTERRUPTSIZE_FS), + 10 // Endpoint is polled every 10ms + }, + // Data class interface standard descriptor + { + sizeof(USBInterfaceDescriptor), + USBGenericDescriptor_INTERFACE, + 1, // This is interface #1 + 0, // This is alternate setting #0 for this interface + 2, // This interface uses 2 endpoints + CDCDataInterfaceDescriptor_CLASS, + CDCDataInterfaceDescriptor_SUBCLASS, + CDCDataInterfaceDescriptor_NOPROTOCOL, + 0 // No string descriptor for this interface + }, + // Bulk-OUT endpoint standard descriptor + { + sizeof(USBEndpointDescriptor), + USBGenericDescriptor_ENDPOINT, + USBEndpointDescriptor_ADDRESS(USBEndpointDescriptor_OUT, + CDCDSerialDriverDescriptors_DATAOUT), + USBEndpointDescriptor_BULK, + MIN(BOARD_USB_ENDPOINTS_MAXPACKETSIZE(CDCDSerialDriverDescriptors_DATAOUT), + USBEndpointDescriptor_MAXBULKSIZE_FS), + 0 // Must be 0 for full-speed bulk endpoints + }, + // Bulk-IN endpoint descriptor + { + sizeof(USBEndpointDescriptor), + USBGenericDescriptor_ENDPOINT, + USBEndpointDescriptor_ADDRESS(USBEndpointDescriptor_IN, + CDCDSerialDriverDescriptors_DATAIN), + USBEndpointDescriptor_BULK, + MIN(BOARD_USB_ENDPOINTS_MAXPACKETSIZE(CDCDSerialDriverDescriptors_DATAIN), + USBEndpointDescriptor_MAXBULKSIZE_FS), + 0 // Must be 0 for full-speed bulk endpoints + }, +}; +#endif + +/// Product string descriptor +const unsigned char productStringDescriptor[] = { + + USBStringDescriptor_LENGTH(13), + USBGenericDescriptor_STRING, + USBStringDescriptor_UNICODE('A'), + USBStringDescriptor_UNICODE('T'), + USBStringDescriptor_UNICODE('9'), + USBStringDescriptor_UNICODE('1'), + USBStringDescriptor_UNICODE('U'), + USBStringDescriptor_UNICODE('S'), + USBStringDescriptor_UNICODE('B'), + USBStringDescriptor_UNICODE('S'), + USBStringDescriptor_UNICODE('e'), + USBStringDescriptor_UNICODE('r'), + USBStringDescriptor_UNICODE('i'), + USBStringDescriptor_UNICODE('a'), + USBStringDescriptor_UNICODE('l') +}; + +/// List of string descriptors used by the device +const unsigned char *stringDescriptors[] = { + + languageIdStringDescriptor, + productStringDescriptor, +}; + +/// List of standard descriptors for the serial driver. +USBDDriverDescriptors cdcdSerialDriverDescriptors = { + + &deviceDescriptor, + (USBConfigurationDescriptor *) &(configurationDescriptors), +#ifdef BOARD_USB_UDPHS + &qualifierDescriptor, + (USBConfigurationDescriptor *) &(otherSpeedDescriptorsFS), + &deviceDescriptor, + (USBConfigurationDescriptor *) &(configurationDescriptorsHS), + &qualifierDescriptor, + (USBConfigurationDescriptor *) &(otherSpeedDescriptorsHS), +#else + 0, // No full-speed device qualifier descriptor + 0, // No full-speed other speed configuration + 0, // No high-speed device descriptor + 0, // No high-speed configuration descriptor + 0, // No high-speed device qualifier descriptor + 0, // No high-speed other speed configuration descriptor + +#endif + stringDescriptors, + 2 // 2 string descriptors in list +}; + diff --git a/at91lib/usb/device/cdc-serial/CDCDSerialDriverDescriptors.h b/at91lib/usb/device/cdc-serial/CDCDSerialDriverDescriptors.h new file mode 100644 index 0000000..8ab4edf --- /dev/null +++ b/at91lib/usb/device/cdc-serial/CDCDSerialDriverDescriptors.h @@ -0,0 +1,77 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Definition of the USB descriptors required by a CDC device serial + driver. +*/ + +#ifndef CDCDSERIALDRIVERDESCRIPTORS_H +#define CDCDSERIALDRIVERDESCRIPTORS_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "CDC Serial Endpoints" +/// This page lists the endpoints used in CDC Serial Device. +/// +/// !Endpoints +/// - CDCDSerialDriverDescriptors_DATAOUT +/// - CDCDSerialDriverDescriptors_DATAIN +/// - CDCDSerialDriverDescriptors_NOTIFICATION + +/// Data OUT endpoint number. +#define CDCDSerialDriverDescriptors_DATAOUT 1 +/// Data IN endpoint number. +#define CDCDSerialDriverDescriptors_DATAIN 2 +/// Notification endpoint number. +#define CDCDSerialDriverDescriptors_NOTIFICATION 3 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Exported variables +//------------------------------------------------------------------------------ + +/// List of descriptors for a CDC device serial driver. +extern USBDDriverDescriptors cdcdSerialDriverDescriptors; + +#endif //#ifndef CDCDDRIVERDESCRIPTORS_H + diff --git a/at91lib/usb/device/core/USBD.h b/at91lib/usb/device/core/USBD.h new file mode 100644 index 0000000..6680e27 --- /dev/null +++ b/at91lib/usb/device/core/USBD.h @@ -0,0 +1,187 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \unit +/// +/// !!!Purpose +/// +/// Collection of methods for using the USB device controller on AT91 +/// microcontrollers. +/// +/// !!!Usage +/// +/// Please refer to the corresponding application note. +/// - "AT91 USB device framework" +/// - "USBD API" . "USBD API Methods" +//------------------------------------------------------------------------------ + +#ifndef USBD_H +#define USBD_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include +#include + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB device API return values" +/// +/// This page lists the return values of the USB %device driver API +/// +/// !Return codes +/// - USBD_STATUS_SUCCESS +/// - USBD_STATUS_LOCKED +/// - USBD_STATUS_ABORTED +/// - USBD_STATUS_RESET + +/// Indicates the operation was successful. +#define USBD_STATUS_SUCCESS 0 +/// Endpoint/device is already busy. +#define USBD_STATUS_LOCKED 1 +/// Operation has been aborted. +#define USBD_STATUS_ABORTED 2 +/// Operation has been aborted because the device has been reset. +#define USBD_STATUS_RESET 3 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB device states" +/// +/// This page lists the %device states of the USB %device driver. +/// +/// !States +/// - USBD_STATE_SUSPENDED +/// - USBD_STATE_ATTACHED +/// - USBD_STATE_POWERED +/// - USBD_STATE_DEFAULT +/// - USBD_STATE_ADDRESS +/// - USBD_STATE_CONFIGURED + +/// The device is currently suspended. +#define USBD_STATE_SUSPENDED 0 +/// USB cable is plugged into the device. +#define USBD_STATE_ATTACHED 1 +/// Host is providing +5V through the USB cable. +#define USBD_STATE_POWERED 2 +/// Device has been reset. +#define USBD_STATE_DEFAULT 3 +/// The device has been given an address on the bus. +#define USBD_STATE_ADDRESS 4 +/// A valid configuration has been selected. +#define USBD_STATE_CONFIGURED 5 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "USB device LEDs" +/// +/// This page lists the LEDs used in the USB %device driver. +/// +/// !LEDs +/// - USBD_LEDPOWER +/// - USBD_LEDUSB +/// - USBD_LEDOTHER + +/// LED for indicating that the device is powered. +#define USBD_LEDPOWER 0 +/// LED for indicating USB activity. +#define USBD_LEDUSB 1 +/// LED for custom usage. +#define USBD_LEDOTHER 2 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Types +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Callback used by transfer functions (USBD_Read & USBD_Write) to notify +/// that a transaction is complete. +//------------------------------------------------------------------------------ +typedef void (*TransferCallback)(void *pArg, + unsigned char status, + unsigned int transferred, + unsigned int remaining); + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +extern void USBD_InterruptHandler(void); + +extern void USBD_Init(void); + +extern void USBD_Connect(void); + +extern void USBD_Disconnect(void); + +extern char USBD_Write( + unsigned char bEndpoint, + const void *pData, + unsigned int size, + TransferCallback callback, + void *pArg); + +extern char USBD_Read( + unsigned char bEndpoint, + void *pData, + unsigned int dLength, + TransferCallback fCallback, + void *pArg); + +extern unsigned char USBD_Stall(unsigned char bEndpoint); + +extern void USBD_Halt(unsigned char bEndpoint); + +extern void USBD_Unhalt(unsigned char bEndpoint); + +extern void USBD_ConfigureEndpoint(const USBEndpointDescriptor *pDescriptor); + +extern unsigned char USBD_IsHalted(unsigned char bEndpoint); + +extern void USBD_RemoteWakeUp(void); + +extern void USBD_SetAddress(unsigned char address); + +extern void USBD_SetConfiguration(unsigned char cfgnum); + +extern unsigned char USBD_GetState(void); + +extern unsigned char USBD_IsHighSpeed(void); + +extern void USBD_Test(unsigned char bIndex); + +#endif //#ifndef USBD_H + diff --git a/at91lib/usb/device/core/USBDCallbacks.h b/at91lib/usb/device/core/USBDCallbacks.h new file mode 100644 index 0000000..d4d5c7e --- /dev/null +++ b/at91lib/usb/device/core/USBDCallbacks.h @@ -0,0 +1,65 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Definitions of callbacks used by the USBD API to notify the user + application of incoming events. These functions are declared as 'weak', + so they can be re-implemented elsewhere in the application in a + transparent way. +*/ + +#ifndef USBDCALLBACKS_H +#define USBDCALLBACKS_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +extern void USBDCallbacks_Initialized(void); + +extern void USBDCallbacks_Reset(void); + +extern void USBDCallbacks_Suspended(void); + +extern void USBDCallbacks_Resumed(void); + +extern void USBDCallbacks_RequestReceived(const USBGenericRequest *request); + +#endif //#ifndef USBDCALLBACKS_H + diff --git a/at91lib/usb/device/core/USBDCallbacks_Initialized.c b/at91lib/usb/device/core/USBDCallbacks_Initialized.c new file mode 100644 index 0000000..5b2f8bc --- /dev/null +++ b/at91lib/usb/device/core/USBDCallbacks_Initialized.c @@ -0,0 +1,62 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "USBDCallbacks.h" +#include "USBD.h" +#include +#include + +//------------------------------------------------------------------------------ +// Exported function +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Invoked after the USB driver has been initialized. By default, configures +/// the UDP/UDPHS interrupt. +//------------------------------------------------------------------------------ +void USBDCallbacks_Initialized(void) +{ +#if defined(BOARD_USB_UDP) + // Configure and enable the UDP interrupt + AIC_ConfigureIT(AT91C_ID_UDP, 1, USBD_InterruptHandler); + AIC_EnableIT(AT91C_ID_UDP); + +#elif defined(BOARD_USB_UDPHS) + // Configure and enable the UDPHS interrupt + AIC_ConfigureIT(AT91C_ID_UDPHS, 1, USBD_InterruptHandler); + AIC_EnableIT(AT91C_ID_UDPHS); +#else + #error Unsupported controller. +#endif +} + diff --git a/at91lib/usb/device/core/USBDCallbacks_Reset.c b/at91lib/usb/device/core/USBDCallbacks_Reset.c new file mode 100644 index 0000000..64d9aaa --- /dev/null +++ b/at91lib/usb/device/core/USBDCallbacks_Reset.c @@ -0,0 +1,47 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "USBDCallbacks.h" + +//------------------------------------------------------------------------------ +// Exported function +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Invoked when the USB driver is reset. Does nothing by default. +//------------------------------------------------------------------------------ +void USBDCallbacks_Reset(void) +{ + // Does nothing +} + diff --git a/at91lib/usb/device/core/USBDDriver.c b/at91lib/usb/device/core/USBDDriver.c new file mode 100644 index 0000000..c2a8abd --- /dev/null +++ b/at91lib/usb/device/core/USBDDriver.c @@ -0,0 +1,682 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "USBDDriver.h" +#include "USBDDriverCallbacks.h" +#include "USBD.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +//------------------------------------------------------------------------------ +// Local functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Configures the device by setting it into the Configured state and +/// initializing all endpoints. +/// \param pDriver Pointer to a USBDDriver instance. +/// \param cfgnum Configuration number to set. +//------------------------------------------------------------------------------ +static void SetConfiguration(USBDDriver *pDriver, unsigned char cfgnum) +{ + USBEndpointDescriptor *pEndpoints[BOARD_USB_NUMENDPOINTS+1]; + const USBConfigurationDescriptor *pConfiguration; + + // Use different descriptor depending on device speed + if (USBD_IsHighSpeed()) { + + pConfiguration = pDriver->pDescriptors->pHsConfiguration; + } + else { + + pConfiguration = pDriver->pDescriptors->pFsConfiguration; + } + + // Set & save the desired configuration + USBD_SetConfiguration(cfgnum); + pDriver->cfgnum = cfgnum; + + // If the configuration is not 0, configure endpoints + if (cfgnum != 0) { + + // Parse configuration to get endpoint descriptors + USBConfigurationDescriptor_Parse(pConfiguration, 0, pEndpoints, 0); + + // Configure endpoints + int i = 0; + while (pEndpoints[i] != 0) { + + USBD_ConfigureEndpoint(pEndpoints[i]); + i++; + } + } + // Should be done before send the ZLP + USBDDriverCallbacks_ConfigurationChanged(cfgnum); + + // Acknowledge the request + USBD_Write(0, // Endpoint #0 + 0, // No data buffer + 0, // No data buffer + (TransferCallback) 0, + (void *) 0); +} + +//------------------------------------------------------------------------------ +/// Sends the current configuration number to the host. +/// \param pDriver Pointer to a USBDDriver instance. +//------------------------------------------------------------------------------ +static void GetConfiguration(const USBDDriver *pDriver) +{ + USBD_Write(0, &(pDriver->cfgnum), 1, 0, 0); +} + +//------------------------------------------------------------------------------ +/// Sends the current status of the device to the host. +/// \param pDriver Pointer to a USBDDriver instance. +//------------------------------------------------------------------------------ +static void GetDeviceStatus(const USBDDriver *pDriver) +{ + unsigned short data = 0; + const USBConfigurationDescriptor *pConfiguration; + + // Use different configuration depending on device speed + if (USBD_IsHighSpeed()) { + + pConfiguration = pDriver->pDescriptors->pHsConfiguration; + } + else { + + pConfiguration = pDriver->pDescriptors->pFsConfiguration; + } + + // Check current configuration for power mode (if device is configured) + if (pDriver->cfgnum != 0) { + + if (USBConfigurationDescriptor_IsSelfPowered(pConfiguration)) { + + data |= 1; + } + } + + // Check if remote wake-up is enabled + if (pDriver->isRemoteWakeUpEnabled) { + + data |= 2; + } + + // Send the device status + USBD_Write(0, &data, 2, 0, 0); +} + +//------------------------------------------------------------------------------ +/// Sends the current status of an endpoints to the USB host. +/// \param bEndpoint Endpoint number. +//------------------------------------------------------------------------------ +static void GetEndpointStatus(unsigned char bEndpoint) +{ + unsigned short data = 0; + + // Check if the endpoint exists + if (bEndpoint > BOARD_USB_NUMENDPOINTS) { + + USBD_Stall(0); + } + else { + + // Check if the endpoint if currently halted + if (USBD_IsHalted(bEndpoint)) { + + data = 1; + } + + // Send the endpoint status + USBD_Write(0, &data, 2, 0, 0); + } +} + +//------------------------------------------------------------------------------ +/// Sends the requested USB descriptor to the host if available, or STALLs the +/// request. +/// \param pDriver Pointer to a USBDDriver instance. +/// \param type Type of the requested descriptor +/// \param index Index of the requested descriptor. +/// \param length Maximum number of bytes to return. +//------------------------------------------------------------------------------ +static void GetDescriptor( + const USBDDriver *pDriver, + unsigned char type, + unsigned char index, + unsigned int length) +{ + const USBDeviceDescriptor *pDevice; + const USBConfigurationDescriptor *pConfiguration; + const USBDeviceQualifierDescriptor *pQualifier; + const USBConfigurationDescriptor *pOtherSpeed; + const USBGenericDescriptor **pStrings = + (const USBGenericDescriptor **) pDriver->pDescriptors->pStrings; + unsigned char numStrings = pDriver->pDescriptors->numStrings; + const USBGenericDescriptor *pString; + + // Use different set of descriptors depending on device speed + if (USBD_IsHighSpeed()) { + + TRACE_DEBUG("HS "); + pDevice = pDriver->pDescriptors->pHsDevice; + pConfiguration = pDriver->pDescriptors->pHsConfiguration; + pQualifier = pDriver->pDescriptors->pHsQualifier; + pOtherSpeed = pDriver->pDescriptors->pHsOtherSpeed; + } + else { + + TRACE_DEBUG("FS "); + pDevice = pDriver->pDescriptors->pFsDevice; + pConfiguration = pDriver->pDescriptors->pFsConfiguration; + pQualifier = pDriver->pDescriptors->pFsQualifier; + pOtherSpeed = pDriver->pDescriptors->pFsOtherSpeed; + } + + // Check the descriptor type + switch (type) { + + case USBGenericDescriptor_DEVICE: + TRACE_INFO_WP("Dev "); + + // Adjust length and send descriptor + if (length > USBGenericDescriptor_GetLength((USBGenericDescriptor *) pDevice)) { + + length = USBGenericDescriptor_GetLength((USBGenericDescriptor *) pDevice); + } + USBD_Write(0, pDevice, length, 0, 0); + break; + + case USBGenericDescriptor_CONFIGURATION: + TRACE_INFO_WP("Cfg "); + + // Adjust length and send descriptor + if (length > USBConfigurationDescriptor_GetTotalLength(pConfiguration)) { + + length = USBConfigurationDescriptor_GetTotalLength(pConfiguration); + } + USBD_Write(0, pConfiguration, length, 0, 0); + break; + + case USBGenericDescriptor_DEVICEQUALIFIER: + TRACE_INFO_WP("Qua "); + + // Check if descriptor exists + if (!pQualifier) { + + USBD_Stall(0); + } + else { + + // Adjust length and send descriptor + if (length > USBGenericDescriptor_GetLength((USBGenericDescriptor *) pQualifier)) { + + length = USBGenericDescriptor_GetLength((USBGenericDescriptor *) pQualifier); + } + USBD_Write(0, pQualifier, length, 0, 0); + } + break; + + case USBGenericDescriptor_OTHERSPEEDCONFIGURATION: + TRACE_INFO_WP("OSC "); + + // Check if descriptor exists + if (!pOtherSpeed) { + + USBD_Stall(0); + } + else { + + // Adjust length and send descriptor + if (length > USBConfigurationDescriptor_GetTotalLength(pOtherSpeed)) { + + length = USBConfigurationDescriptor_GetTotalLength(pOtherSpeed); + } + USBD_Write(0, pOtherSpeed, length, 0, 0); + } + break; + + case USBGenericDescriptor_STRING: + TRACE_INFO_WP("Str%d ", index); + + // Check if descriptor exists + if (index > numStrings) { + + USBD_Stall(0); + } + else { + + pString = pStrings[index]; + + // Adjust length and send descriptor + if (length > USBGenericDescriptor_GetLength(pString)) { + + length = USBGenericDescriptor_GetLength(pString); + } + USBD_Write(0, pString, length, 0, 0); + } + break; + + default: + TRACE_WARNING( + "USBDDriver_GetDescriptor: Unknown descriptor type (%d)\n\r", + type); + USBD_Stall(0); + } +} + +//------------------------------------------------------------------------------ +/// Sets the active setting of the given interface if the configuration supports +/// it; otherwise, the control pipe is STALLed. If the setting of an interface +/// changes. +/// \parma pDriver Pointer to a USBDDriver instance. +/// \parma infnum Interface number. +/// \parma setting New active setting for the interface. +//------------------------------------------------------------------------------ +static void SetInterface( + USBDDriver *pDriver, + unsigned char infnum, + unsigned char setting) +{ + // Make sure alternate settings are supported + if (!pDriver->pInterfaces) { + + USBD_Stall(0); + } + else { + + // Change the current setting of the interface and trigger the callback + // if necessary + if (pDriver->pInterfaces[infnum] != setting) { + + pDriver->pInterfaces[infnum] = setting; + USBDDriverCallbacks_InterfaceSettingChanged(infnum, setting); + } + + // Acknowledge the request + USBD_Write(0, 0, 0, 0, 0); + } +} + +//------------------------------------------------------------------------------ +/// Sends the currently active setting of the given interface to the USB +/// host. If alternate settings are not supported, this function STALLs the +/// control pipe. +/// \param pDriver Pointer to a USBDDriver instance. +/// \param infnum Interface number. +//------------------------------------------------------------------------------ +static void GetInterface( + const USBDDriver *pDriver, + unsigned char infnum) +{ + // Make sure alternate settings are supported, or STALL the control pipe + if (!pDriver->pInterfaces) { + + USBD_Stall(0); + } + else { + + // Sends the current interface setting to the host + USBD_Write(0, &(pDriver->pInterfaces[infnum]), 1, 0, 0); + } +} + +#ifdef BOARD_USB_UDPHS +//------------------------------------------------------------------------------ +// Performs the selected test on the USB device (high-speed only). +// \param test Test selector value. +//------------------------------------------------------------------------------ +static void USBDDriver_Test(unsigned char test) +{ + TRACE_DEBUG("UDPHS_Test\n\r"); + + // the lower byte of wIndex must be zero + // the most significant byte of wIndex is used to specify the specific test mode + switch (test) { + case USBFeatureRequest_TESTPACKET: + //Test mode Test_Packet: + //Upon command, a port must repetitively transmit the following test packet until + //the exit action is taken. This enables the testing of rise and fall times, eye + //patterns, jitter, and any other dynamic waveform specifications. + //The test packet is made up by concatenating the following strings. + //(Note: For J/K NRZI data, and for NRZ data, the bit on the left is the first one + //transmitted. S indicates that a bit stuff occurs, which inserts an extra NRZI data bit. + //* N is used to indicate N occurrences of a string of bits or symbols.) + //A port in Test_Packet mode must send this packet repetitively. The inter-packet timing + //must be no less than the minimum allowable inter-packet gap as defined in Section 7.1.18 and + //no greater than 125 us. + // Send ZLP + USBD_Test(USBFeatureRequest_TESTSENDZLP); + // Tst PACKET + USBD_Test(USBFeatureRequest_TESTPACKET); + while (1); + break; + + case USBFeatureRequest_TESTJ: + //Test mode Test_J: + //Upon command, a ports transceiver must enter the high-speed J state and remain in that + //state until the exit action is taken. This enables the testing of the high output drive + //level on the D+ line. + // Send ZLP + USBD_Test(USBFeatureRequest_TESTSENDZLP); + // Tst J + USBD_Test(USBFeatureRequest_TESTJ); + while (1); + break; + + case USBFeatureRequest_TESTK: + //Test mode Test_K: + //Upon command, a ports transceiver must enter the high-speed K state and remain in + //that state until the exit action is taken. This enables the testing of the high output drive + //level on the D- line. + // Send a ZLP + USBD_Test(USBFeatureRequest_TESTSENDZLP); + USBD_Test(USBFeatureRequest_TESTK); + while (1); + break; + + case USBFeatureRequest_TESTSE0NAK: + //Test mode Test_SE0_NAK: + //Upon command, a ports transceiver must enter the high-speed receive mode + //and remain in that mode until the exit action is taken. This enables the testing + //of output impedance, low level output voltage, and loading characteristics. + //In addition, while in this mode, upstream facing ports (and only upstream facing ports) + //must respond to any IN token packet with a NAK handshake (only if the packet CRC is + //determined to be correct) within the normal allowed device response time. This enables testing of + //the device squelch level circuitry and, additionally, provides a general purpose stimulus/response + //test for basic functional testing. + USBD_Test(USBFeatureRequest_TESTSE0NAK); + // Send a ZLP + USBD_Test(USBFeatureRequest_TESTSENDZLP); + while (1); + break; + + default: + USBD_Stall( 0 ); + break; + + } + // The exit action is to power cycle the device. + // The device must be disconnected from the host +} +#endif + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Initializes a USBDDriver instance with a list of descriptors. If +/// interfaces can have multiple alternate settings, an array to store the +/// current setting for each interface must be provided. +/// \param pDriver Pointer to a USBDDriver instance. +/// \param pDescriptors Pointer to a USBDDriverDescriptors instance. +/// \param pInterfaces Pointer to an array for storing the current alternate +/// setting of each interface (optional). +//------------------------------------------------------------------------------ +void USBDDriver_Initialize( + USBDDriver *pDriver, + const USBDDriverDescriptors *pDescriptors, + unsigned char *pInterfaces) +{ + + pDriver->cfgnum = 0; +#if (BOARD_USB_BMATTRIBUTES == USBConfigurationDescriptor_SELFPOWERED_RWAKEUP) \ + || (BOARD_USB_BMATTRIBUTES == USBConfigurationDescriptor_BUSPOWERED_RWAKEUP) + pDriver->isRemoteWakeUpEnabled = 1; +#else + pDriver->isRemoteWakeUpEnabled = 0; +#endif + + pDriver->pDescriptors = pDescriptors; + pDriver->pInterfaces = pInterfaces; + + // Initialize interfaces array if not null + if (pInterfaces != 0) { + + memset(pInterfaces, sizeof(pInterfaces), 0); + } +} + +//------------------------------------------------------------------------------ +/// Handles the given request if it is standard, otherwise STALLs it. +/// \param pDriver Pointer to a USBDDriver instance. +/// \param pRequest Pointer to a USBGenericRequest instance. +//------------------------------------------------------------------------------ +void USBDDriver_RequestHandler( + USBDDriver *pDriver, + const USBGenericRequest *pRequest) +{ + unsigned char cfgnum; + unsigned char infnum; + unsigned char eptnum; + unsigned char setting; + unsigned char type; + unsigned char index; + unsigned int length; + unsigned int address; + + TRACE_INFO_WP("Std "); + + // Check request code + switch (USBGenericRequest_GetRequest(pRequest)) { + + case USBGenericRequest_GETDESCRIPTOR: + TRACE_INFO_WP("gDesc "); + + // Send the requested descriptor + type = USBGetDescriptorRequest_GetDescriptorType(pRequest); + index = USBGetDescriptorRequest_GetDescriptorIndex(pRequest); + length = USBGenericRequest_GetLength(pRequest); + GetDescriptor(pDriver, type, index, length); + break; + + case USBGenericRequest_SETADDRESS: + TRACE_INFO_WP("sAddr "); + + // Sends a zero-length packet and then set the device address + address = USBSetAddressRequest_GetAddress(pRequest); + USBD_Write(0, 0, 0, (TransferCallback) USBD_SetAddress, (void *) address); + break; + + case USBGenericRequest_SETCONFIGURATION: + TRACE_INFO_WP("sCfg "); + + // Set the requested configuration + cfgnum = USBSetConfigurationRequest_GetConfiguration(pRequest); + SetConfiguration(pDriver, cfgnum); + break; + + case USBGenericRequest_GETCONFIGURATION: + TRACE_INFO_WP("gCfg "); + + // Send the current configuration number + GetConfiguration(pDriver); + break; + + case USBGenericRequest_GETSTATUS: + TRACE_INFO_WP("gSta "); + + // Check who is the recipient + switch (USBGenericRequest_GetRecipient(pRequest)) { + + case USBGenericRequest_DEVICE: + TRACE_INFO_WP("Dev "); + + // Send the device status + GetDeviceStatus(pDriver); + break; + + case USBGenericRequest_ENDPOINT: + TRACE_INFO_WP("Ept "); + + // Send the endpoint status + eptnum = USBGenericRequest_GetEndpointNumber(pRequest); + GetEndpointStatus(eptnum); + break; + + default: + TRACE_WARNING( + "USBDDriver_RequestHandler: Unknown recipient (%d)\n\r", + USBGenericRequest_GetRecipient(pRequest)); + USBD_Stall(0); + } + break; + + case USBGenericRequest_CLEARFEATURE: + TRACE_INFO_WP("cFeat "); + + // Check which is the requested feature + switch (USBFeatureRequest_GetFeatureSelector(pRequest)) { + + case USBFeatureRequest_ENDPOINTHALT: + TRACE_INFO_WP("Hlt "); + + // Unhalt endpoint and send a zero-length packet + USBD_Unhalt(USBGenericRequest_GetEndpointNumber(pRequest)); + USBD_Write(0, 0, 0, 0, 0); + break; + + case USBFeatureRequest_DEVICEREMOTEWAKEUP: + TRACE_INFO_WP("RmWU "); + + // Disable remote wake-up and send a zero-length packet + pDriver->isRemoteWakeUpEnabled = 0; + USBD_Write(0, 0, 0, 0, 0); + break; + + default: + TRACE_WARNING( + "USBDDriver_RequestHandler: Unknown feature selector (%d)\n\r", + USBFeatureRequest_GetFeatureSelector(pRequest)); + USBD_Stall(0); + } + break; + + case USBGenericRequest_SETFEATURE: + TRACE_INFO_WP("sFeat "); + + // Check which is the selected feature + switch (USBFeatureRequest_GetFeatureSelector(pRequest)) { + + case USBFeatureRequest_DEVICEREMOTEWAKEUP: + TRACE_INFO_WP("RmWU "); + + // Enable remote wake-up and send a ZLP + pDriver->isRemoteWakeUpEnabled = 1; + USBD_Write(0, 0, 0, 0, 0); + break; + + case USBFeatureRequest_ENDPOINTHALT: + TRACE_INFO_WP("Ept "); + + // Halt endpoint + USBD_Halt(USBGenericRequest_GetEndpointNumber(pRequest)); + USBD_Write(0, 0, 0, 0, 0); + break; + +#if defined(BOARD_USB_UDPHS) + + case USBFeatureRequest_TESTMODE: + // 7.1.20 Test Mode Support + if ((USBGenericRequest_GetType(pRequest) == USBGenericRequest_DEVICE) + && ((USBGenericRequest_GetIndex(pRequest) & 0x000F) == 0)) { + + // Handle test request + USBDDriver_Test(USBFeatureRequest_GetTestSelector(pRequest)); + } + else { + + USBD_Stall(0); + } + break; +#endif + + default: + TRACE_WARNING( + "USBDDriver_RequestHandler: Unknown feature selector (%d)\n\r", + USBFeatureRequest_GetFeatureSelector(pRequest)); + USBD_Stall(0); + } + break; + + case USBGenericRequest_SETINTERFACE: + TRACE_INFO_WP("sInterface "); + + infnum = USBInterfaceRequest_GetInterface(pRequest); + setting = USBInterfaceRequest_GetAlternateSetting(pRequest); + SetInterface(pDriver, infnum, setting); + break; + + case USBGenericRequest_GETINTERFACE: + TRACE_INFO_WP("gInterface "); + + infnum = USBInterfaceRequest_GetInterface(pRequest); + GetInterface(pDriver, infnum); + break; + + default: + TRACE_WARNING( + "USBDDriver_RequestHandler: Unknown request code (%d)\n\r", + USBGenericRequest_GetRequest(pRequest)); + USBD_Stall(0); + } +} + + +//------------------------------------------------------------------------------ +/// Test if RemoteWakeUP feature is enabled +/// \param pDriver Pointer to an USBDDriver instance. +/// \return 1 if remote wake up has been enabled by the host; otherwise, returns +/// 0 +//------------------------------------------------------------------------------ +unsigned char USBDDriver_IsRemoteWakeUpEnabled(const USBDDriver *pDriver) +{ + return pDriver->isRemoteWakeUpEnabled; +} + + diff --git a/at91lib/usb/device/core/USBDDriver.h b/at91lib/usb/device/core/USBDDriver.h new file mode 100644 index 0000000..7b14b8e --- /dev/null +++ b/at91lib/usb/device/core/USBDDriver.h @@ -0,0 +1,93 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + USB Device Driver class definition. + + !!!Usage + + -# Instanciate a USBDDriver object and initialize it using + USBDDriver_Initialize. + -# When a USB SETUP request is received, forward it to the standard + driver using USBDDriver_RequestHandler. + -# Check the Remote Wakeup setting via USBDDriver_IsRemoteWakeUpEnabled. +*/ + +#ifndef USBDDRIVER_H +#define USBDDRIVER_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "USBDDriverDescriptors.h" +#include + +//------------------------------------------------------------------------------ +// Types +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// USB device driver structure, holding a list of descriptors identifying +/// the device as well as the driver current state. +//------------------------------------------------------------------------------ +typedef struct { + + /// List of descriptors used by the device. + const USBDDriverDescriptors *pDescriptors; + /// Current setting for each interface. + unsigned char *pInterfaces; + /// Current configuration number (0 -> device is not configured). + unsigned char cfgnum; + /// Indicates if remote wake up has been enabled by the host. + unsigned char isRemoteWakeUpEnabled; + +} USBDDriver; + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +extern void USBDDriver_Initialize( + USBDDriver *pDriver, + const USBDDriverDescriptors *pDescriptors, + unsigned char *pInterfaces); + +extern void USBDDriver_RequestHandler( + USBDDriver *pDriver, + const USBGenericRequest *pRequest); + +extern unsigned char USBDDriver_IsRemoteWakeUpEnabled(const USBDDriver *pDriver); + +#endif //#ifndef USBDDRIVER_H + diff --git a/at91lib/usb/device/core/USBDDriverCallbacks.h b/at91lib/usb/device/core/USBDDriverCallbacks.h new file mode 100644 index 0000000..053e8ac --- /dev/null +++ b/at91lib/usb/device/core/USBDDriverCallbacks.h @@ -0,0 +1,61 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Definition of several callbacks which are triggered by the USB software + driver after receiving specific requests. + + !!!Usage + + -# Re-implement the USBDDriverCallbacks_ConfigurationChanged + callback to know when the hosts changes the active configuration of + the device. + -# Re-implement the USBDDriverCallbacks_InterfaceSettingChanged + callback to get notified whenever the active setting of an interface + is changed by the host. +*/ + +#ifndef USBDDRIVERCALLBACKS_H +#define USBDDRIVERCALLBACKS_H + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +extern void USBDDriverCallbacks_ConfigurationChanged(unsigned char cfgnum); + +extern void USBDDriverCallbacks_InterfaceSettingChanged(unsigned char interface, + unsigned char setting); + +#endif //#ifndef USBDDRIVERCALLBACKS_H + diff --git a/at91lib/usb/device/core/USBDDriverCb_CfgChanged.c b/at91lib/usb/device/core/USBDDriverCb_CfgChanged.c new file mode 100644 index 0000000..08e2b2f --- /dev/null +++ b/at91lib/usb/device/core/USBDDriverCb_CfgChanged.c @@ -0,0 +1,49 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "USBDDriverCallbacks.h" +#include + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Indicates that the current configuration of the device has changed. +/// \param cfgnum New device configuration index. +//------------------------------------------------------------------------------ +void USBDDriverCallbacks_ConfigurationChanged(unsigned char cfgnum) +{ + TRACE_INFO_WP("ConfigurationChanged "); +} + diff --git a/at91lib/usb/device/core/USBDDriverCb_IfSettingChanged.c b/at91lib/usb/device/core/USBDDriverCb_IfSettingChanged.c new file mode 100644 index 0000000..c9049e6 --- /dev/null +++ b/at91lib/usb/device/core/USBDDriverCb_IfSettingChanged.c @@ -0,0 +1,52 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "USBDDriverCallbacks.h" +#include + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Notifies of a change in the currently active setting of an interface. +/// \param interface Number of the interface whose setting has changed. +/// \param setting New interface setting. +//------------------------------------------------------------------------------ +void USBDDriverCallbacks_InterfaceSettingChanged( + unsigned char interface, + unsigned char setting) +{ + TRACE_INFO_WP("InterfaceSettingChanged "); +} + diff --git a/at91lib/usb/device/core/USBDDriverDescriptors.h b/at91lib/usb/device/core/USBDDriverDescriptors.h new file mode 100644 index 0000000..f1064e4 --- /dev/null +++ b/at91lib/usb/device/core/USBDDriverDescriptors.h @@ -0,0 +1,86 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Definition of a class for declaring USB descriptors required by the + device driver. +*/ + +#ifndef USBDDRIVERDESCRIPTORS_H +#define USBDDRIVERDESCRIPTORS_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include +#include +#include + +//------------------------------------------------------------------------------ +// Types +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// List of all descriptors used by a USB device driver. Each descriptor can +/// be provided in two versions: full-speed and high-speed. Devices which are +/// not high-speed capable do not need to provided high-speed descriptors and +/// the full-speed qualifier & other speed descriptors. +//------------------------------------------------------------------------------ +typedef struct { + + /// Pointer to the full-speed device descriptor. + const USBDeviceDescriptor *pFsDevice; + /// Pointer to the full-speed configuration descriptor. + const USBConfigurationDescriptor *pFsConfiguration; + /// Pointer to the full-speed qualifier descriptor. + const USBDeviceQualifierDescriptor *pFsQualifier; + /// Pointer to the full-speed other speed configuration descriptor. + const USBConfigurationDescriptor *pFsOtherSpeed; + /// Pointer to the high-speed device descriptor. + const USBDeviceDescriptor *pHsDevice; + /// Pointer to the high-speed configuration descriptor. + const USBConfigurationDescriptor *pHsConfiguration; + /// Pointer to the high-speed qualifier descriptor. + const USBDeviceQualifierDescriptor *pHsQualifier; + /// Pointer to the high-speed other speed configuration descriptor. + const USBConfigurationDescriptor *pHsOtherSpeed; + /// Pointer to the list of string descriptors. + const unsigned char **pStrings; + /// Number of string descriptors in list. + unsigned char numStrings; + +} USBDDriverDescriptors; + +#endif //#ifndef USBDDRIVERDESCRIPTORS_H + diff --git a/at91lib/usb/device/core/USBD_OTGHS.c b/at91lib/usb/device/core/USBD_OTGHS.c new file mode 100644 index 0000000..0f87143 --- /dev/null +++ b/at91lib/usb/device/core/USBD_OTGHS.c @@ -0,0 +1,1677 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/*! + Functions for OTGHS peripheral usage. +*/ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include + +#ifdef CHIP_OTGHS + +#include "common.h" +#include "trace.h" +#include "usb.h" + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +#define NUM_IT_MAX (AT91C_BASE_OTGHS->OTGHS_IPFEATURES & AT91C_OTGHS_EPT_NBR_MAX) +#define NUM_IT_MAX_DMA ((AT91C_BASE_OTGHS->OTGHS_IPFEATURES & AT91C_OTGHS_DMA_CHANNEL_NBR)>>4) + +#define SHIFT_DMA 24 +#define SHIFT_INTERUPT 12 + +#define DMA + +//------------------------------------------------------------------------------ +// Structures +//------------------------------------------------------------------------------ + +// \brief Endpoint states +typedef enum { + + endpointStateDisabled, + endpointStateIdle, + endpointStateWrite, + endpointStateRead, + endpointStateHalted + +} EndpointState_t; + +//------------------------------------------------------------------------------ +// Macros +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Internal Functions +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +// \brief Returns a pointer to the OTGHS controller interface used by an USB +// driver +// +// The pointer is cast to the correct type (AT91PS_OTGHS). +// \param pUsb Pointer to a S_usb instance +// \return Pointer to the USB controller interface +// \see S_usb +//------------------------------------------------------------------------------ +static AT91PS_OTGHS OTGHS_GetDriverInterface(const S_usb *pUsb) +{ + return (AT91PS_OTGHS) pUsb->pDriver->pInterface; +} + +//------------------------------------------------------------------------------ +// \fn OTGHS_GetInterfaceEPT +// \brief Returns OTGHS endpoint FIFO interface from S_usb structure +//------------------------------------------------------------------------------ +static AT91PS_OTGHS_EPTFIFO OTGHS_GetInterfaceEPT(const S_usb *pUsb) +{ + return (AT91PS_OTGHS_EPTFIFO) pUsb->pDriver->pEndpointFIFO; +} + + +//------------------------------------------------------------------------------ +// \brief Enables the peripheral clock of the USB controller associated with +// the specified USB driver +// \param pUsb Pointer to a S_usb instance +// \see S_usb +//------------------------------------------------------------------------------ +static void OTGHS_EnableMCK(const S_usb *pUsb) +{ + +} + +//------------------------------------------------------------------------------ +// \brief Disables the peripheral clock of the USB controller associated with +// the specified USB driver +// \param pUsb Pointer to a S_usb instance +// \see S_usb +//------------------------------------------------------------------------------ +static void OTGHS_DisableMCK(const S_usb *pUsb) +{ + +} + +//------------------------------------------------------------------------------ +// \brief Enables the 48MHz clock of the USB controller associated with +// the specified USB driver +// \param pUsb Pointer to a S_usb instance +// \see S_usb +//------------------------------------------------------------------------------ +static void OTGHS_EnableOTGHSCK(const S_usb *pUsb) +{ + +} + +//------------------------------------------------------------------------------ +// \brief Disables the 48MHz clock of the USB controller associated with +// the specified USB driver +// \param pUsb Pointer to a S_usb instance +// \see S_usb +//------------------------------------------------------------------------------ +static void OTGHS_DisableOTGHSCK(const S_usb *pUsb) +{ + +} + +//------------------------------------------------------------------------------ +// \brief Enables the transceiver of the USB controller associated with +// the specified USB driver +// \param pUsb Pointer to a S_usb instance +// \see S_usb +//------------------------------------------------------------------------------ +static void OTGHS_EnableTransceiver(const S_usb *pUsb) +{ + SET(OTGHS_GetDriverInterface(pUsb)->OTGHS_CTRL, AT91C_OTGHS_OTGPADE); +} + +//------------------------------------------------------------------------------ +// \brief Disables the transceiver of the USB controller associated with +// the specified USB driver +// \param pUsb Pointer to a S_usb instance +// \see S_usb +//------------------------------------------------------------------------------ +static void OTGHS_DisableTransceiver(const S_usb *pUsb) +{ + CLEAR(OTGHS_GetDriverInterface(pUsb)->OTGHS_CTRL, AT91C_OTGHS_OTGPADE); +} + +//------------------------------------------------------------------------------ +// \brief Invokes the callback associated with a finished transfer on an +// endpoint +// \param pEndpoint Pointer to a S_usb_endpoint instance +// \param bStatus Status code returned by the transfer operation +// \see Status codes +// \see S_usb_endpoint +//------------------------------------------------------------------------------ +static void OTGHS_EndOfTransfer(S_usb_endpoint *pEndpoint, + char bStatus) +{ + if ((pEndpoint->dState == endpointStateWrite) + || (pEndpoint->dState == endpointStateRead)) { + + TRACE_DEBUG_WP("E"); + + // Endpoint returns in Idle state + pEndpoint->dState = endpointStateIdle; + + // Invoke callback is present + if (pEndpoint->fCallback != 0) { + + pEndpoint->fCallback((unsigned int) pEndpoint->pArgument, + (unsigned int) bStatus, + pEndpoint->dBytesTransferred, + pEndpoint->dBytesRemaining + + pEndpoint->dBytesBuffered); + } + } +} + +//------------------------------------------------------------------------------ +// \brief Transfers a data payload from the current tranfer buffer to the +// endpoint FIFO. +// \param pUsb Pointer to a S_usb instance +// \param bEndpoint Index of endpoint +// \return Number of bytes transferred +// \see S_usb +//------------------------------------------------------------------------------ +static unsigned int OTGHS_WritePayload(const S_usb *pUsb, + unsigned char bEndpoint) +{ + AT91PS_OTGHS_EPTFIFO pInterfaceEPT = OTGHS_GetInterfaceEPT(pUsb); + S_usb_endpoint *pEndpoint = USB_GetEndpoint(pUsb, bEndpoint); + char *pfifo; + unsigned int dBytes; + unsigned int dCtr; + + pfifo = (char*)&(pInterfaceEPT->OTGHS_READEPT0[bEndpoint*16384]); + + // Get the number of bytes to send + dBytes = min(pEndpoint->wMaxPacketSize, pEndpoint->dBytesRemaining); + + // Transfer one packet in the FIFO buffer + for (dCtr = 0; dCtr < dBytes; dCtr++) { + + pfifo[dCtr] = *(pEndpoint->pData); + pEndpoint->pData++; + } + + pEndpoint->dBytesBuffered += dBytes; + pEndpoint->dBytesRemaining -= dBytes; + + return dBytes; +} + +//---------------------------------------------------------------------------- +// \brief Transfers a data payload from an endpoint FIFO to the current +// transfer buffer. +// \param pUsb Pointer to a S_usb instance +// \param bEndpoint Index of endpoint +// \param wPacketSize Size of received data packet +// \return Number of bytes transferred +// \see S_usb +//------------------------------------------------------------------------------ +static unsigned int OTGHS_GetPayload(const S_usb *pUsb, + unsigned char bEndpoint, + unsigned short wPacketSize) +{ + AT91PS_OTGHS_EPTFIFO pInterfaceEPT = OTGHS_GetInterfaceEPT(pUsb); + S_usb_endpoint *pEndpoint = USB_GetEndpoint(pUsb, bEndpoint); + char *pfifo; + unsigned int dBytes; + unsigned int dCtr; + + pfifo = (char*)&(pInterfaceEPT->OTGHS_READEPT0[bEndpoint*16384]); + + // Get number of bytes to retrieve + dBytes = min(pEndpoint->dBytesRemaining, wPacketSize); + + // Retrieve packet + for (dCtr = 0; dCtr < dBytes; dCtr++) { + + *(pEndpoint->pData) = pfifo[dCtr]; + pEndpoint->pData++; + } + + pEndpoint->dBytesRemaining -= dBytes; + pEndpoint->dBytesTransferred += dBytes; + pEndpoint->dBytesBuffered += wPacketSize - dBytes; + + return dBytes; +} + +//------------------------------------------------------------------------------ +// \brief Transfers a received SETUP packet from endpoint 0 FIFO to the +// S_usb_request structure of an USB driver +// \param pUsb Pointer to a S_usb instance +// \see S_usb +//------------------------------------------------------------------------------ +static void OTGHS_GetSetup(const S_usb *pUsb) +{ + unsigned int *pData = (unsigned int *) USB_GetSetup(pUsb); + AT91PS_OTGHS_EPTFIFO pInterfaceEPT = OTGHS_GetInterfaceEPT(pUsb); + + pData[0] = pInterfaceEPT->OTGHS_READEPT0[0]; + pData[1] = pInterfaceEPT->OTGHS_READEPT0[0]; +} + +//------------------------------------------------------------------------------ +// \brief This function reset all endpoint transfer descriptors +// \param pUsb Pointer to a S_usb instance +// \see S_usb +//------------------------------------------------------------------------------ +static void OTGHS_ResetEndpoints(const S_usb *pUsb) +{ + S_usb_endpoint *pEndpoint; + unsigned char bEndpoint; + + // Reset the transfer descriptor of every endpoint + for (bEndpoint = 0; bEndpoint < pUsb->dNumEndpoints; bEndpoint++) { + + pEndpoint = USB_GetEndpoint(pUsb, bEndpoint); + + // Reset endpoint transfer descriptor + pEndpoint->pData = 0; + pEndpoint->dBytesRemaining = 0; + pEndpoint->dBytesTransferred = 0; + pEndpoint->dBytesBuffered = 0; + pEndpoint->fCallback = 0; + pEndpoint->pArgument = 0; + + // Configure endpoint characteristics + pEndpoint->dState = endpointStateDisabled; + } +} + +//------------------------------------------------------------------------------ +// \brief Disable all endpoints (except control endpoint 0), aborting current +// transfers if necessary. +// \param pUsb Pointer to a S_usb instance +//------------------------------------------------------------------------------ +static void OTGHS_DisableEndpoints(const S_usb *pUsb) +{ + S_usb_endpoint *pEndpoint; + unsigned char bEndpoint; + + // Foreach endpoint, if it is enabled, disable it and invoke the callback + // Control endpoint 0 is not disabled + for (bEndpoint = 1; bEndpoint < pUsb->dNumEndpoints; bEndpoint++) { + + pEndpoint = USB_GetEndpoint(pUsb, bEndpoint); + OTGHS_EndOfTransfer(pEndpoint, USB_STATUS_RESET); + + pEndpoint->dState = endpointStateDisabled; + } +} + +//------------------------------------------------------------------------------ +// \brief Endpoint interrupt handler. +// +// Handle IN/OUT transfers, received SETUP packets and STALLing +// \param pUsb Pointer to a S_usb instance +// \param bEndpoint Index of endpoint +// \see S_usb +//------------------------------------------------------------------------------ +static void OTGHS_EndpointHandler(const S_usb *pUsb, unsigned char bEndpoint) +{ + S_usb_endpoint *pEndpoint = USB_GetEndpoint(pUsb, bEndpoint); + AT91PS_OTGHS pInterface = OTGHS_GetDriverInterface(pUsb); + unsigned int dStatus = pInterface->OTGHS_DEVEPTCSR[bEndpoint]; + unsigned short wPacketSize; + + TRACE_DEBUG_WP("Ept%d, 0x%X ", bEndpoint, dStatus); + + // Handle interrupts + // IN packet sent + if((ISSET(pInterface->OTGHS_DEVEPTCMR[bEndpoint], AT91C_OTGHS_TXINI)) + && (ISSET(dStatus, AT91C_OTGHS_TXINI ))) { + + TRACE_DEBUG_WP("Wr "); + + if (pEndpoint->dBytesBuffered > 0) { + + TRACE_DEBUG_WP("%d ", pEndpoint->dBytesBuffered); + + pEndpoint->dBytesTransferred += pEndpoint->dBytesBuffered; + pEndpoint->dBytesBuffered = 0; + } + + if ((!pEndpoint->isDataSent) || (pEndpoint->dBytesRemaining > 0)) { + + OTGHS_WritePayload(pUsb, bEndpoint); + pEndpoint->isDataSent = true; + + pInterface->OTGHS_DEVEPTCCR[bEndpoint] = AT91C_OTGHS_TXINI; + // For a non-control endpoint, the FIFOCON bit must be cleared + // to start the transfer + if ((AT91C_OTGHS_EPT_TYPE & pInterface->OTGHS_DEVEPTCFG[bEndpoint]) + != AT91C_OTGHS_EPT_TYPE_CTL_EPT) { + + pInterface->OTGHS_DEVEPTCDR[bEndpoint] = AT91C_OTGHS_FIFOCON; + } + } + else { + + pInterface->OTGHS_DEVEPTCDR[bEndpoint] = AT91C_OTGHS_TXINI; + + // Disable interrupt if this is not a control endpoint + if ((AT91C_OTGHS_EPT_TYPE & pInterface->OTGHS_DEVEPTCFG[bEndpoint]) + != AT91C_OTGHS_EPT_TYPE_CTL_EPT) { + + pInterface->OTGHS_DEVIDR = 1<dState != endpointStateRead) { + + // Endpoint is NOT in Read state + if (ISCLEARED(pInterface->OTGHS_DEVEPTCFG[bEndpoint], AT91C_OTGHS_EPT_TYPE) + && ISCLEARED(dStatus, (0x7FF<<20))) { // byte count + + // Control endpoint, 0 bytes received + // Acknowledge the data and finish the current transfer + TRACE_DEBUG_WP("Ack "); + pInterface->OTGHS_DEVEPTCCR[bEndpoint] = AT91C_OTGHS_RXOUT; + + OTGHS_EndOfTransfer(pEndpoint, USB_STATUS_SUCCESS); + } + else if (ISSET(dStatus, AT91C_OTGHS_STALL)) { + + // Non-control endpoint + // Discard stalled data + TRACE_DEBUG_WP("Disc "); + pInterface->OTGHS_DEVEPTCCR[bEndpoint] = AT91C_OTGHS_RXOUT; + } + else { + + // Non-control endpoint + // Nak data + TRACE_DEBUG_WP("Nak "); + pInterface->OTGHS_DEVIDR = 1<> 20) & 0x7FF); + + TRACE_DEBUG_WP("%d ", wPacketSize); + + OTGHS_GetPayload(pUsb, bEndpoint, wPacketSize); + + pInterface->OTGHS_DEVEPTCCR[bEndpoint] = AT91C_OTGHS_RXOUT; + pInterface->OTGHS_DEVEPTCDR[bEndpoint] = AT91C_OTGHS_FIFOCON; + + if ((pEndpoint->dBytesRemaining == 0) + || (wPacketSize < pEndpoint->wMaxPacketSize)) { + + pInterface->OTGHS_DEVEPTCDR[bEndpoint] = AT91C_OTGHS_RXOUT; + + // Disable interrupt if this is not a control endpoint + if ((AT91C_OTGHS_EPT_TYPE & pInterface->OTGHS_DEVEPTCFG[bEndpoint]) + != AT91C_OTGHS_EPT_TYPE_CTL_EPT) { + + pInterface->OTGHS_DEVIDR = 1<dState == endpointStateWrite) + || (pEndpoint->dState == endpointStateRead)) { + + OTGHS_EndOfTransfer(pEndpoint, USB_STATUS_SUCCESS); + } + + // Copy the setup packet in S_usb + OTGHS_GetSetup(pUsb); + + // Acknowledge setup packet + pInterface->OTGHS_DEVEPTCCR[bEndpoint] = AT91C_OTGHS_RXSTP; + + // Forward the request to the upper layer + USB_NewRequestCallback(pUsb); + } + + // STALL sent + if (ISSET(dStatus, AT91C_OTGHS_STALL)) { + + TRACE_WARNING("Sta 0x%X [%d] ", dStatus, bEndpoint); + + // Acknowledge STALL interrupt and disable it + pInterface->OTGHS_DEVEPTCCR[bEndpoint] = AT91C_OTGHS_STALL; + //pInterface->OTGHS_DEVEPTCDR[bEndpoint] = AT91C_OTGHS_STALL; + + // If the endpoint is not halted, clear the stall condition + if (pEndpoint->dState != endpointStateHalted) { + + TRACE_WARNING("_ " ); + // Acknowledge the stall RQ flag + pInterface->OTGHS_DEVEPTCDR[bEndpoint] = AT91C_OTGHS_STALLRQ; + } + + } + +} + + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +// \brief Configure an endpoint with the provided endpoint descriptor +// \param pUsb Pointer to a S_usb instance +// \param pEpDesc Pointer to the endpoint descriptor +// \return true if the endpoint is now configured, false otherwise +// \see S_usb_endpoint_descriptor +// \see S_usb +//------------------------------------------------------------------------------ +static bool OTGHS_ConfigureEndpoint(const S_usb *pUsb, + const S_usb_endpoint_descriptor *pEpDesc) +{ + AT91PS_OTGHS pInterface = OTGHS_GetDriverInterface(pUsb); + S_usb_endpoint *pEndpoint; + unsigned char bEndpoint; + unsigned char bType; + unsigned char endpointDir; + unsigned short sizeEpt = 0; + + // Maximum packet size configuration value + if( pEpDesc->wMaxPacketSize == 8 ) { + sizeEpt = AT91C_OTGHS_EPT_SIZE_8; + } else if ( pEpDesc->wMaxPacketSize == 16 ) { + sizeEpt = AT91C_OTGHS_EPT_SIZE_16; + } else if ( pEpDesc->wMaxPacketSize == 32 ) { + sizeEpt = AT91C_OTGHS_EPT_SIZE_32; + } else if ( pEpDesc->wMaxPacketSize == 64 ) { + sizeEpt = AT91C_OTGHS_EPT_SIZE_64; + } else if ( pEpDesc->wMaxPacketSize == 128 ) { + sizeEpt = AT91C_OTGHS_EPT_SIZE_128; + } else if ( pEpDesc->wMaxPacketSize == 256 ) { + sizeEpt = AT91C_OTGHS_EPT_SIZE_256; + } else if ( pEpDesc->wMaxPacketSize == 512 ) { + sizeEpt = AT91C_OTGHS_EPT_SIZE_512; + } else if ( pEpDesc->wMaxPacketSize == 1024 ) { + sizeEpt = AT91C_OTGHS_EPT_SIZE_1024; + } //else { + // sizeEpt = 0; // control endpoint + //} + + // if pEpDesc == 0 then initialize the control endpoint + if (pEpDesc == (S_usb_endpoint_descriptor const *) 0) { + + bEndpoint = 0; + bType = 0; // Control endpoint + } + else { + // The endpoint number + bEndpoint = (unsigned char) (pEpDesc->bEndpointAddress & 0x7); + // Transfer type: Control, Isochronous, Bulk, Interrupt + bType = (unsigned char) (pEpDesc->bmAttributes & 0x3); + // Direction, ignored for control endpoints + endpointDir = (unsigned char) (pEpDesc->bEndpointAddress & (1<<7)); + } + + // Get pointer on endpoint + pEndpoint = USB_GetEndpoint(pUsb, bEndpoint); + if (pEndpoint == 0) { + + return false; + } + + // Configure wMaxPacketSize + if (pEpDesc != 0) { + + pEndpoint->wMaxPacketSize = pEpDesc->wMaxPacketSize; + } + else { + + pEndpoint->wMaxPacketSize = USB_ENDPOINT0_MAXPACKETSIZE; + } + + // Abort the current transfer is the endpoint was configured and in + // Write or Read state + if ((pEndpoint->dState == endpointStateRead) + || (pEndpoint->dState == endpointStateWrite)) { + + OTGHS_EndOfTransfer(pEndpoint, USB_STATUS_RESET); + } + + // Enter in IDLE state + pEndpoint->dState = endpointStateIdle; + + // Reset Endpoint Fifos + pInterface->OTGHS_DEVEPT |= (1<OTGHS_DEVEPT &= ~(1<OTGHS_DEVEPT |= (1<OTGHS_DEVEPTCFG[bEndpoint] = AT91C_OTGHS_ALLOC | + AT91C_OTGHS_EPT_SIZE_64 | AT91C_OTGHS_EPT_DIR_OUT | AT91C_OTGHS_EPT_TYPE_CTL_EPT | AT91C_OTGHS_BK_NUMBER_1; + + // Enable RXSTP interrupt + pInterface->OTGHS_DEVEPTCER[bEndpoint] = AT91C_OTGHS_RXSTP; + + // Enable endpoint IT + pInterface->OTGHS_DEVIER = 1<OTGHS_DEVEPTCFG[bEndpoint] = AT91C_OTGHS_ALLOC | + sizeEpt | AT91C_OTGHS_EPT_DIR_IN | AT91C_OTGHS_EPT_TYPE_ISO_EPT | AT91C_OTGHS_BK_NUMBER_2; +#else + pInterface->OTGHS_DEVEPTCFG[bEndpoint] = AT91C_OTGHS_ALLOC | AT91C_OTGHS_AUTOSW | + sizeEpt | AT91C_OTGHS_EPT_DIR_IN | AT91C_OTGHS_EPT_TYPE_ISO_EPT | AT91C_OTGHS_BK_NUMBER_2; +#endif + + } + else { + TRACE_INFO("Iso Out[%d]\n\r",bEndpoint); + + //! Configure endpoint +#ifndef DMA + pInterface->OTGHS_DEVEPTCFG[bEndpoint] = AT91C_OTGHS_ALLOC | + sizeEpt | AT91C_OTGHS_EPT_DIR_OUT | AT91C_OTGHS_EPT_TYPE_ISO_EPT | AT91C_OTGHS_BK_NUMBER_2; +#else + pInterface->OTGHS_DEVEPTCFG[bEndpoint] = AT91C_OTGHS_ALLOC | AT91C_OTGHS_AUTOSW | + sizeEpt | AT91C_OTGHS_EPT_DIR_OUT | AT91C_OTGHS_EPT_TYPE_ISO_EPT | AT91C_OTGHS_BK_NUMBER_2; +#endif + + } + break; + + //---------------------- + case ENDPOINT_TYPE_BULK: + //---------------------- + if (endpointDir) { + TRACE_INFO("Bulk In(%d)[%d] ",bEndpoint, pEpDesc->wMaxPacketSize); + //! Configure endpoint +#ifndef DMA + pInterface->OTGHS_DEVEPTCFG[bEndpoint] = AT91C_OTGHS_ALLOC | + sizeEpt | AT91C_OTGHS_EPT_DIR_IN | AT91C_OTGHS_EPT_TYPE_BUL_EPT | AT91C_OTGHS_BK_NUMBER_2; +#else + pInterface->OTGHS_DEVEPTCFG[bEndpoint] = AT91C_OTGHS_ALLOC | AT91C_OTGHS_AUTOSW | + sizeEpt | AT91C_OTGHS_EPT_DIR_IN | AT91C_OTGHS_EPT_TYPE_BUL_EPT | AT91C_OTGHS_BK_NUMBER_2; +#endif + + } + else { + TRACE_INFO("Bulk Out(%d)[%d]\n\r",bEndpoint, pEpDesc->wMaxPacketSize); + //! Configure endpoint +#ifndef DMA + pInterface->OTGHS_DEVEPTCFG[bEndpoint] = AT91C_OTGHS_ALLOC | + sizeEpt | AT91C_OTGHS_EPT_DIR_OUT | AT91C_OTGHS_EPT_TYPE_BUL_EPT | AT91C_OTGHS_BK_NUMBER_2; +#else + pInterface->OTGHS_DEVEPTCFG[bEndpoint] = AT91C_OTGHS_ALLOC | AT91C_OTGHS_AUTOSW | + sizeEpt | AT91C_OTGHS_EPT_DIR_OUT | AT91C_OTGHS_EPT_TYPE_BUL_EPT | AT91C_OTGHS_BK_NUMBER_2; +#endif + } + break; + + //--------------------------- + case ENDPOINT_TYPE_INTERRUPT: + //--------------------------- + if (endpointDir) { + TRACE_INFO("Interrupt In[%d]\n\r",bEndpoint); + //! Configure endpoint +#ifndef DMA + pInterface->OTGHS_DEVEPTCFG[bEndpoint] = AT91C_OTGHS_ALLOC | + sizeEpt | AT91C_OTGHS_EPT_DIR_IN | AT91C_OTGHS_EPT_TYPE_INT_EPT | AT91C_OTGHS_BK_NUMBER_2; +#else + pInterface->OTGHS_DEVEPTCFG[bEndpoint] = AT91C_OTGHS_ALLOC | AT91C_OTGHS_AUTOSW | + sizeEpt | AT91C_OTGHS_EPT_DIR_IN | AT91C_OTGHS_EPT_TYPE_INT_EPT | AT91C_OTGHS_BK_NUMBER_2; +#endif + + } + else { + TRACE_INFO("Interrupt Out[%d]\n\r",bEndpoint); + //! Configure endpoint +#ifndef DMA + pInterface->OTGHS_DEVEPTCFG[bEndpoint] = AT91C_OTGHS_ALLOC | + sizeEpt | AT91C_OTGHS_EPT_DIR_OUT | AT91C_OTGHS_EPT_TYPE_INT_EPT | AT91C_OTGHS_BK_NUMBER_2; +#else + pInterface->OTGHS_DEVEPTCFG[bEndpoint] = AT91C_OTGHS_ALLOC | AT91C_OTGHS_AUTOSW | + sizeEpt | AT91C_OTGHS_EPT_DIR_OUT | AT91C_OTGHS_EPT_TYPE_INT_EPT | AT91C_OTGHS_BK_NUMBER_2; +#endif + + } + break; + + //------ + default: + //------ + TRACE_ERROR(" unknown endpoint type\n\r"); + return false; + } + + // Check if the configuration is ok + if (ISCLEARED(pInterface->OTGHS_DEVEPTCSR[bEndpoint], AT91C_OTGHS_CFGOK)) { + + TRACE_FATAL("OTGHS_ConfigureEndpoint: Cannot configure endpoint\n\r"); + return false; + } + + return true; +} + + +//------------------------------------------------------------------------------ +// Interrupt service routine +//------------------------------------------------------------------------------ +#ifdef DMA +//---------------------------------------------------------------------------- +//! \fn OTGHS_DmaHandler +//! \brief This function (ISR) handles DMA interrupts +//---------------------------------------------------------------------------- +static void OTGHS_DmaHandler(const S_usb *pUsb, unsigned char endpoint) +{ + AT91PS_OTGHS pInterface = OTGHS_GetDriverInterface(pUsb); + S_usb_endpoint *pEndpoint = USB_GetEndpoint(pUsb, endpoint); + unsigned int csr; + + csr = pInterface->OTGHS_DEVDMA[endpoint].OTGHS_DEVDMASTATUS; + pInterface->OTGHS_DEVIDR = (1<dBytesTransferred = pEndpoint->dBytesBuffered; + pEndpoint->dBytesBuffered = 0; + + TRACE_DEBUG_M("dBytesBuffered: 0x%x\n\r",pEndpoint->dBytesBuffered); + TRACE_DEBUG_M("dBytesRemaining: 0x%x\n\r",pEndpoint->dBytesRemaining); + TRACE_DEBUG_M("dBytesTransferred: 0x%x\n\r",pEndpoint->dBytesTransferred); + + OTGHS_EndOfTransfer(pEndpoint, USB_STATUS_SUCCESS); + pEndpoint->dState = endpointStateIdle; + } + else { + TRACE_FATAL("Probleme IT DMA\n\r"); + } +} +#endif + + +//------------------------------------------------------------------------------ +// \brief OTGHS interrupt handler +// +// Manages device resume, suspend, end of bus reset. Forwards endpoint +// interrupts to the appropriate handler. +// \param pUsb Pointer to a S_usb instance +//------------------------------------------------------------------------------ +static void OTGHS_Handler(const S_usb *pUsb) +{ + AT91PS_OTGHS pInterface = OTGHS_GetDriverInterface(pUsb); + unsigned int dStatus; + unsigned char numIT; + + if ( (!ISSET(USB_GetState(pUsb), USB_STATE_SUSPENDED)) + && (ISSET(USB_GetState(pUsb), USB_STATE_POWERED))){ + + LED_TOGGLE(LED_USB); + } + + TRACE_DEBUG_H("Hlr "); + + // Get General interrupts status + dStatus = pInterface->OTGHS_SR & pInterface->OTGHS_CTRL & 0xFF; + while (dStatus != 0) { + + if(ISSET(dStatus, AT91C_OTGHS_VBUSTI)) + { + TRACE_DEBUG_M("__VBus\n\r"); + + USB_Attach(pUsb); + + // Acknowledge the interrupt + pInterface->OTGHS_SCR = AT91C_OTGHS_VBUSTI; + } + + // Don't treat others interrupt for this time + pInterface->OTGHS_SCR = AT91C_OTGHS_IDT | AT91C_OTGHS_SRP + | AT91C_OTGHS_VBERR | AT91C_OTGHS_BCERR + | AT91C_OTGHS_ROLEEX | AT91C_OTGHS_HNPERR + | AT91C_OTGHS_STO; + + dStatus = pInterface->OTGHS_SR & pInterface->OTGHS_CTRL & 0xFF; + } + + + // Get OTG Device interrupts status + dStatus = pInterface->OTGHS_DEVISR & pInterface->OTGHS_DEVIMR; + TRACE_DEBUG_H("OTGHS_DEVISR:0x%X\n\r", pInterface->OTGHS_DEVISR); + while (dStatus != 0) { + + // Start Of Frame (SOF) + if (ISSET(dStatus, AT91C_OTGHS_SOF)) { + TRACE_DEBUG_WP("SOF "); + + // Invoke the SOF callback + USB_StartOfFrameCallback(pUsb); + + // Acknowledge interrupt + SET(pInterface->OTGHS_DEVICR, AT91C_OTGHS_SOF); + CLEAR(dStatus, AT91C_OTGHS_SOF); + } + + // Suspend + else if (dStatus & AT91C_OTGHS_SUSP) { + + TRACE_DEBUG_M("S "); + + if (!ISSET(USB_GetState(pUsb), USB_STATE_SUSPENDED)) { + + // The device enters the Suspended state + // MCK + UDPCK must be off + // Pull-Up must be connected + // Transceiver must be disabled + + // Enable wakeup + SET(pInterface->OTGHS_DEVIER, AT91C_OTGHS_EORST | AT91C_OTGHS_WAKEUP | AT91C_OTGHS_EORSM); + + // Acknowledge interrupt + pInterface->OTGHS_DEVICR = AT91C_OTGHS_SUSP; + SET(*(pUsb->pState), USB_STATE_SUSPENDED); + OTGHS_DisableTransceiver(pUsb); + OTGHS_DisableMCK(pUsb); + OTGHS_DisableOTGHSCK(pUsb); + + // Invoke the Suspend callback + + USB_SuspendCallback(pUsb); + } + } + + // Resume + else if (ISSET(dStatus, AT91C_OTGHS_WAKEUP) + || ISSET(dStatus, AT91C_OTGHS_EORSM)) { + + // Invoke the Resume callback + USB_ResumeCallback(pUsb); + + TRACE_DEBUG_M("R "); + + // The device enters Configured state + // MCK + UDPCK must be on + // Pull-Up must be connected + // Transceiver must be enabled + + if (ISSET(USB_GetState(pUsb), USB_STATE_SUSPENDED)) { + + // Powered state + OTGHS_EnableMCK(pUsb); + OTGHS_EnableOTGHSCK(pUsb); + + // Default state + if (ISSET(USB_GetState(pUsb), USB_STATE_DEFAULT)) { + + OTGHS_EnableTransceiver(pUsb); + } + + CLEAR(*(pUsb->pState), USB_STATE_SUSPENDED); + } + pInterface->OTGHS_DEVICR = + (AT91C_OTGHS_WAKEUP | AT91C_OTGHS_EORSM | AT91C_OTGHS_SUSP); + + pInterface->OTGHS_DEVIER = (AT91C_OTGHS_EORST | AT91C_OTGHS_SUSP); + pInterface->OTGHS_DEVICR = (AT91C_OTGHS_WAKEUP | AT91C_OTGHS_EORSM); + pInterface->OTGHS_DEVIDR = AT91C_OTGHS_WAKEUP; + + } + + // End of bus reset + else if (dStatus & AT91C_OTGHS_EORST) { + + TRACE_DEBUG_M("EoB "); + // The device enters the Default state + // MCK + UDPCK are already enabled + // Pull-Up is already connected + // Transceiver must be enabled + // Endpoint 0 must be enabled + SET(*(pUsb->pState), USB_STATE_DEFAULT); + + OTGHS_EnableTransceiver(pUsb); + + // The device leaves the Address & Configured states + CLEAR(*(pUsb->pState), USB_STATE_ADDRESS | USB_STATE_CONFIGURED); + OTGHS_ResetEndpoints(pUsb); + OTGHS_DisableEndpoints(pUsb); + OTGHS_ConfigureEndpoint(pUsb, 0); + + // Flush and enable the Suspend interrupt + SET(pInterface->OTGHS_DEVICR, AT91C_OTGHS_WAKEUP | AT91C_OTGHS_SUSP); + + // Enable the Start Of Frame (SOF) interrupt if needed + if (pUsb->pCallbacks->startOfFrame != 0) { + + SET(pInterface->OTGHS_DEVIER, AT91C_OTGHS_SOF); + } + + // Invoke the Reset callback + USB_ResetCallback(pUsb); + + // Acknowledge end of bus reset interrupt + pInterface->OTGHS_DEVICR = AT91C_OTGHS_EORST; + } + + // Handle upstream resume interrupt + else if (dStatus & AT91C_OTGHS_UPRSM) { + + TRACE_DEBUG_WP(" External resume interrupt\n\r"); + + // - Acknowledge the IT + pInterface->OTGHS_DEVICR = AT91C_OTGHS_UPRSM; + } + + // Endpoint interrupts + else { +#ifndef DMA + // Handle endpoint interrupts + for (numIT = 0; numIT < NUM_IT_MAX; numIT++) { + if( dStatus & (1<OTGHS_DEVISR) & (pInterface->OTGHS_DEVIMR); + + // Mask unneeded interrupts + if (!ISSET(USB_GetState(pUsb), USB_STATE_DEFAULT)) { + + dStatus &= AT91C_OTGHS_EORST | AT91C_OTGHS_SOF; + } + + TRACE_DEBUG_H("\n\r"); + + if (dStatus != 0) { + + TRACE_DEBUG_WP(" - "); + } + } + + if ( (!ISSET(USB_GetState(pUsb), USB_STATE_SUSPENDED)) + && (ISSET(USB_GetState(pUsb), USB_STATE_POWERED))){ + + LED_TOGGLE(LED_USB); + } +} + +//------------------------------------------------------------------------------ +// \brief Sends data through an USB endpoint +// +// Sets up the transfer descriptor, write one or two data payloads +// (depending on the number of FIFO banks for the endpoint) and then +// starts the actual transfer. The operation is complete when all +// the data has been sent. +// \param pUsb Pointer to a S_usb instance +// \param bEndpoint Index of endpoint +// \param pData Pointer to a buffer containing the data to send +// \param dLength Length of the data buffer +// \param fCallback Optional function to invoke when the transfer finishes +// \param pArgument Optional argument for the callback function +// \return Operation result code +// \see Operation result codes +// \see Callback_f +// \see S_usb +//------------------------------------------------------------------------------ +static char OTGHS_Write(const S_usb *pUsb, + unsigned char bEndpoint, + const void *pData, + unsigned int dLength, + Callback_f fCallback, + void *pArgument) +{ + S_usb_endpoint *pEndpoint = USB_GetEndpoint(pUsb, bEndpoint); + AT91PS_OTGHS pInterface = OTGHS_GetDriverInterface(pUsb); + + // Check that the endpoint is in Idle state + if (pEndpoint->dState != endpointStateIdle) { + + return USB_STATUS_LOCKED; + } + + TRACE_DEBUG_WP("Write%d(%d) ", bEndpoint, dLength); + + // Setup the transfer descriptor + pEndpoint->pData = (char *) pData; + pEndpoint->dBytesRemaining = dLength; + pEndpoint->dBytesBuffered = 0; + pEndpoint->dBytesTransferred = 0; + pEndpoint->fCallback = fCallback; + pEndpoint->pArgument = pArgument; + pEndpoint->isDataSent = false; + + // Send one packet + pEndpoint->dState = endpointStateWrite; + +#ifdef DMA + // Test if endpoint type control + if (AT91C_OTGHS_EPT_TYPE_CTL_EPT == (AT91C_OTGHS_EPT_TYPE & pInterface->OTGHS_DEVEPTCFG[bEndpoint])) { +#endif + // Enable endpoint IT + pInterface->OTGHS_DEVIER = (1<OTGHS_DEVEPTCER[bEndpoint] = AT91C_OTGHS_TXINI; + +#ifdef DMA + } + else { + + // others endoint (not control) + pEndpoint->dBytesBuffered = pEndpoint->dBytesRemaining; + pEndpoint->dBytesRemaining = 0; + + pInterface->OTGHS_DEVDMA[bEndpoint].OTGHS_DEVDMAADDRESS = (unsigned int) pEndpoint->pData; + + // Enable IT DMA + pInterface->OTGHS_DEVIER = (1<OTGHS_DEVDMA[bEndpoint].OTGHS_DEVDMACONTROL = + (((pEndpoint->dBytesBuffered<<16)&AT91C_OTGHS_BUFF_LENGTH) + | AT91C_OTGHS_END_B_EN + | AT91C_OTGHS_END_BUFFIT + | AT91C_OTGHS_CHANN_ENB); + + } +#endif + + return USB_STATUS_SUCCESS; +} + +//------------------------------------------------------------------------------ +// \brief Reads incoming data on an USB endpoint +// +// This methods sets the transfer descriptor and activate the endpoint +// interrupt. The actual transfer is then carried out by the endpoint +// interrupt handler. The Read operation finishes either when the +// buffer is full, or a short packet (inferior to endpoint maximum +// packet size) is received. +// \param pUsb Pointer to a S_usb instance +// \param bEndpoint Index of endpoint +// \param pData Pointer to a buffer to store the received data +// \param dLength Length of the receive buffer +// \param fCallback Optional callback function +// \param pArgument Optional callback argument +// \return Operation result code +// \see Callback_f +// \see S_usb +//------------------------------------------------------------------------------ +static char OTGHS_Read(const S_usb *pUsb, + unsigned char bEndpoint, + void *pData, + unsigned int dLength, + Callback_f fCallback, + void *pArgument) +{ + AT91PS_OTGHS pInterface = OTGHS_GetDriverInterface(pUsb); + S_usb_endpoint *pEndpoint = USB_GetEndpoint(pUsb, bEndpoint); + + //! Return if the endpoint is not in IDLE state + if (pEndpoint->dState != endpointStateIdle) { + + return USB_STATUS_LOCKED; + } + + TRACE_DEBUG_M("Read%d(%d) ", bEndpoint, dLength); + + // Endpoint enters Read state + pEndpoint->dState = endpointStateRead; + + //! Set the transfer descriptor + pEndpoint->pData = (char *) pData; + pEndpoint->dBytesRemaining = dLength; + pEndpoint->dBytesBuffered = 0; + pEndpoint->dBytesTransferred = 0; + pEndpoint->fCallback = fCallback; + pEndpoint->pArgument = pArgument; + +#ifdef DMA + // Test if endpoint type control + if (AT91C_OTGHS_EPT_TYPE_CTL_EPT == (AT91C_OTGHS_EPT_TYPE & pInterface->OTGHS_DEVEPTCFG[bEndpoint])) { +#endif + // Control endpoint + // Enable endpoint IT + pInterface->OTGHS_DEVIER = (1<OTGHS_DEVEPTCER[bEndpoint] = AT91C_OTGHS_RXOUT; +#ifdef DMA + } + else { + + // others endoint (not control) + pEndpoint->dBytesBuffered = pEndpoint->dBytesRemaining; + pEndpoint->dBytesRemaining = 0; + + // Enable IT DMA + pInterface->OTGHS_DEVIER = (1<OTGHS_DEVDMA[bEndpoint].OTGHS_DEVDMAADDRESS = (unsigned int) pEndpoint->pData; + + pInterface->OTGHS_DEVDMA[bEndpoint].OTGHS_DEVDMACONTROL = \ + ( (pEndpoint->dBytesBuffered<<16) + | AT91C_OTGHS_END_TR_EN + | AT91C_OTGHS_END_TR_IT + | AT91C_OTGHS_END_B_EN + | AT91C_OTGHS_END_BUFFIT + | AT91C_OTGHS_CHANN_ENB); + } +#endif + + return USB_STATUS_SUCCESS; +} + +//------------------------------------------------------------------------------ +// \brief Clears, sets or returns the Halt state on specified endpoint +// +// When in Halt state, an endpoint acknowledges every received packet +// with a STALL handshake. This continues until the endpoint is +// manually put out of the Halt state by calling this function. +// \param pUsb Pointer to a S_usb instance +// \param bEndpoint Index of endpoint +// \param bRequest Request to perform +// -> USB_SET_FEATURE, USB_CLEAR_FEATURE, USB_GET_STATUS +// \return true if the endpoint is currently Halted, false otherwise +// \see S_usb +//------------------------------------------------------------------------------ +static bool OTGHS_Halt(const S_usb *pUsb, + unsigned char bEndpoint, + unsigned char bRequest) +{ + AT91PS_OTGHS pInterface = OTGHS_GetDriverInterface(pUsb); + S_usb_endpoint *pEndpoint = USB_GetEndpoint(pUsb, bEndpoint); + + // Clear the Halt feature of the endpoint if it is enabled + if (bRequest == USB_CLEAR_FEATURE) { + + TRACE_DEBUG_WP("Unhalt%d ", bEndpoint); + + // Return endpoint to Idle state + pEndpoint->dState = endpointStateIdle; + + // Clear FORCESTALL flag + + // Disable stall on endpoint + pInterface->OTGHS_DEVEPTCDR[bEndpoint] = AT91C_OTGHS_STALLRQ; + pEndpoint->dState = endpointStateIdle; + + // Reset data-toggle + pInterface->OTGHS_DEVEPTCER[bEndpoint] = AT91C_OTGHS_RSTDT; + } + // Set the Halt feature on the endpoint if it is not already enabled + // and the endpoint is not disabled + else if ((bRequest == USB_SET_FEATURE) + && (pEndpoint->dState != endpointStateHalted) + && (pEndpoint->dState != endpointStateDisabled)) { + + TRACE_DEBUG_WP("Halt%d ", bEndpoint); + + // Abort the current transfer if necessary + OTGHS_EndOfTransfer(pEndpoint, USB_STATUS_ABORTED); + + // Put endpoint into Halt state + pInterface->OTGHS_DEVEPTCER[bEndpoint] = AT91C_OTGHS_STALLRQ; + pEndpoint->dState = endpointStateHalted; + + // Enable the endpoint interrupt + pInterface->OTGHS_DEVIER = (1<dState == endpointStateHalted) { + + return true; + } + else { + + return false; + } +} + +//------------------------------------------------------------------------------ +// \brief Causes the endpoint to acknowledge the next received packet with +// a STALL handshake. +// +// Further packets are then handled normally. +// \param pUsb Pointer to a S_usb instance +// \param bEndpoint Index of endpoint +// \return Operation result code +// \see S_usb +//------------------------------------------------------------------------------ +static char OTGHS_Stall(const S_usb *pUsb, + unsigned char bEndpoint) +{ + AT91PS_OTGHS pInterface = OTGHS_GetDriverInterface(pUsb); + S_usb_endpoint *pEndpoint = USB_GetEndpoint(pUsb, bEndpoint); + + // Check that endpoint is in Idle state + if (pEndpoint->dState != endpointStateIdle) { + + TRACE_WARNING("UDP_Stall: Endpoint%d locked\n\r", bEndpoint); + return USB_STATUS_LOCKED; + } + + TRACE_DEBUG_WP("Stall%d ", bEndpoint); + + pInterface->OTGHS_DEVEPTCER[bEndpoint] = AT91C_OTGHS_STALL; + pInterface->OTGHS_DEVEPTCER[bEndpoint] = AT91C_OTGHS_STALLRQ; + + return USB_STATUS_SUCCESS; +} + +//------------------------------------------------------------------------------ +// \brief Activates a remote wakeup procedure +// \param pUsb Pointer to a S_usb instance +// \see S_usb +//------------------------------------------------------------------------------ +static void OTGHS_RemoteWakeUp(const S_usb *pUsb) +{ + AT91PS_OTGHS pInterface = OTGHS_GetDriverInterface(pUsb); + + OTGHS_EnableMCK(pUsb); + OTGHS_EnableOTGHSCK(pUsb); + OTGHS_EnableTransceiver(pUsb); + + TRACE_DEBUG_WP("Remote WakeUp "); + + //! Enable wakeup interrupt + //pInterface->OTGHS_DEVIER = AT91C_OTGHS_UPRSM; + + // Activates a remote wakeup + pInterface->OTGHS_DEVCTRL |= AT91C_OTGHS_RMWKUP; +} + +//------------------------------------------------------------------------------ +// \brief Handles attachment or detachment from the USB when the VBus power +// line status changes. +// \param pUsb Pointer to a S_usb instance +// \return true if VBus is present, false otherwise +// \see S_usb +//------------------------------------------------------------------------------ +static bool OTGHS_Attach(const S_usb *pUsb) +{ + AT91PS_OTGHS pInterface = OTGHS_GetDriverInterface(pUsb); + + TRACE_DEBUG_WP("Attach("); + + // Check if VBus is present + if (!ISSET(USB_GetState(pUsb), USB_STATE_POWERED) + && BRD_IsVBusConnected(pInterface)) { + + // Powered state: + // MCK + UDPCK must be on + // Pull-Up must be connected + // Transceiver must be disabled + + // Invoke the Resume callback + USB_ResumeCallback(pUsb); + + OTGHS_EnableMCK(pUsb); + OTGHS_EnableOTGHSCK(pUsb); + + // Enable the transceiver + OTGHS_EnableTransceiver(pUsb); + + // Reconnect the pull-up if needed + if (ISSET(*(pUsb->pState), USB_STATE_SHOULD_RECONNECT)) { + + USB_Connect(pUsb); + CLEAR(*(pUsb->pState), USB_STATE_SHOULD_RECONNECT); + } + + // Clear the Suspend and Resume interrupts + pInterface->OTGHS_DEVICR = \ + AT91C_OTGHS_WAKEUP | AT91C_OTGHS_EORSM | AT91C_OTGHS_SUSP; + + // Enable interrupt + pInterface->OTGHS_DEVIER = AT91C_OTGHS_EORST | AT91C_OTGHS_WAKEUP | AT91C_OTGHS_EORSM; + + // The device is in Powered state + SET(*(pUsb->pState), USB_STATE_POWERED); + + } + else if (ISSET(USB_GetState(pUsb), USB_STATE_POWERED) + && !BRD_IsVBusConnected(pInterface)) { + + // Attached state: + // MCK + UDPCK off + // Pull-Up must be disconnected + // Transceiver must be disabled + + // Warning: MCK must be enabled to be able to write in UDP registers + // It may have been disabled by the Suspend interrupt, so re-enable it + OTGHS_EnableMCK(pUsb); + + // Disable interrupts + pInterface->OTGHS_DEVIDR &= ~(AT91C_OTGHS_WAKEUP | AT91C_OTGHS_EORSM + | AT91C_OTGHS_SUSP | AT91C_OTGHS_SOF); + + OTGHS_DisableEndpoints(pUsb); + + // Disconnect the pull-up if needed + if (ISSET(USB_GetState(pUsb), USB_STATE_DEFAULT)) { + + USB_Disconnect(pUsb); + SET(*(pUsb->pState), USB_STATE_SHOULD_RECONNECT); + } + + OTGHS_DisableTransceiver(pUsb); + OTGHS_DisableMCK(pUsb); + OTGHS_DisableOTGHSCK(pUsb); + + // The device leaves the all states except Attached + CLEAR(*(pUsb->pState), USB_STATE_POWERED | USB_STATE_DEFAULT + | USB_STATE_ADDRESS | USB_STATE_CONFIGURED | USB_STATE_SUSPENDED); + + // Invoke the Suspend callback + USB_SuspendCallback(pUsb); + + } + + TRACE_DEBUG_WP("%d) ", ISSET(USB_GetState(pUsb), USB_STATE_POWERED)); + + return ISSET(USB_GetState(pUsb), USB_STATE_POWERED); +} + +//------------------------------------------------------------------------------ +// \brief Sets the device address +// +// This function directly accesses the S_usb_request instance located +// in the S_usb structure to extract its new address. +// \param pUsb Pointer to a S_usb instance +// \see S_usb +//------------------------------------------------------------------------------ +static void OTGHS_SetAddress(S_usb const *pUsb) +{ + unsigned short wAddress = USB_GetSetup(pUsb)->wValue; + AT91PS_OTGHS pInterface = OTGHS_GetDriverInterface(pUsb); + + TRACE_DEBUG_WP("SetAddr(%d) ", wAddress); + + // Set address + pInterface->OTGHS_DEVCTRL = wAddress & AT91C_OTGHS_UADD; + pInterface->OTGHS_DEVCTRL |= AT91C_OTGHS_ADDEN; + +} + +//------------------------------------------------------------------------------ +// \brief Changes the device state from Address to Configured, or from +// Configured to Address. +// +// This method directly access the last received SETUP packet to +// decide on what to do. +// \see S_usb +//------------------------------------------------------------------------------ +static void OTGHS_SetConfiguration(S_usb const *pUsb) +{ + unsigned short wValue = USB_GetSetup(pUsb)->wValue; + + TRACE_DEBUG_WP("SetCfg() "); + + // Check the request + if (wValue != 0) { + // Enter Configured state + SET(*(pUsb->pState), USB_STATE_CONFIGURED); + + } + else { + + // Go back to Address state + CLEAR(*(pUsb->pState), USB_STATE_CONFIGURED); + + // Abort all transfers + OTGHS_DisableEndpoints(pUsb); + } +} + +//------------------------------------------------------------------------------ +// \brief Enables the pull-up on the D+ line to connect the device to the USB. +// \param pUsb Pointer to a S_usb instance +// \see S_usb +//------------------------------------------------------------------------------ +static void OTGHS_Connect(const S_usb *pUsb) +{ +#if defined(INTERNAL_PULLUP) + CLEAR(OTGHS_GetDriverInterface(pUsb)->OTGHS_DEVCTRL, AT91C_OTGHS_DETACH); + +#elif defined(INTERNAL_PULLUP_MATRIX) + TRACE_DEBUG_WP("PUON 1\n\r"); + AT91C_BASE_MATRIX->MATRIX_USBPCR |= AT91C_MATRIX_USBPCR_PUON; + +#else + BRD_ConnectPullUp(UDP_GetDriverInterface(pUsb)); + +#endif +} + +//------------------------------------------------------------------------------ +// \brief Disables the pull-up on the D+ line to disconnect the device from +// the bus. +// \param pUsb Pointer to a S_usb instance +// \see S_usb +//------------------------------------------------------------------------------ +static void OTGHS_Disconnect(const S_usb *pUsb) +{ +#if defined(INTERNAL_PULLUP) + SET(OTGHS_GetDriverInterface(pUsb)->OTGHS_DEVCTRL, AT91C_OTGHS_DETACH); + +#elif defined(INTERNAL_PULLUP_MATRIX) + TRACE_DEBUG_WP("PUON 0\n\r"); + AT91C_BASE_MATRIX->MATRIX_USBPCR &= ~AT91C_MATRIX_USBPCR_PUON; + +#else + BRD_DisconnectPullUp(UDP_GetDriverInterface(pUsb)); + +#endif + // Device leaves the Default state + CLEAR(*(pUsb->pState), USB_STATE_DEFAULT); +} + +//------------------------------------------------------------------------------ +// \brief Certification test for High Speed device. +// \param pUsb Pointer to a S_usb instance +// \param bIndex char for the test choice +// \see S_usb +//------------------------------------------------------------------------------ +static void OTGHS_Test(const S_usb *pUsb, unsigned char bIndex) +{ + AT91PS_OTGHS pInterface = OTGHS_GetDriverInterface(pUsb); + + pInterface->OTGHS_DEVIDR &= ~AT91C_OTGHS_SUSP; + pInterface->OTGHS_DEVCTRL |= AT91C_OTGHS_SPDCONF_HS; // remove suspend ? + + switch( bIndex ) { + case TEST_PACKET: + TRACE_DEBUG_M("TEST_PACKET "); + pInterface->OTGHS_DEVCTRL |= AT91C_OTGHS_TSTPCKT; + break; + + case TEST_J: + TRACE_DEBUG_M("TEST_J "); + pInterface->OTGHS_DEVCTRL |= AT91C_OTGHS_TSTJ; + break; + + case TEST_K: + TRACE_DEBUG_M("TEST_K "); + pInterface->OTGHS_DEVCTRL |= AT91C_OTGHS_TSTK; + break; + + case TEST_SEO_NAK: + TRACE_DEBUG_M("TEST_SEO_NAK "); + pInterface->OTGHS_DEVIDR = 0xFFFFFFFF; + break; + + case TEST_SEND_ZLP: + pInterface->OTGHS_DEVEPTCCR[0] = AT91C_OTGHS_TXINI; + TRACE_DEBUG_M("SEND_ZLP "); + break; + + TRACE_DEBUG_M("\n\r"); + } +} + +//------------------------------------------------------------------------------ +// \brief Certification test for High Speed device. +// \param pUsb Pointer to a S_usb instance +// \see S_usb +//------------------------------------------------------------------------------ +static bool OTGHS_IsHighSpeed(const S_usb *pUsb) +{ + AT91PS_OTGHS pInterface = OTGHS_GetDriverInterface(pUsb); + bool status = false; + + if(AT91C_OTGHS_SPEED_SR_HS == (pInterface->OTGHS_SR & (0x03<<12))) { + // High Speed + status = true; + } + + return status; +} + +//------------------------------------------------------------------------------ +// \brief Initializes the specified USB driver +// +// This function initializes the current FIFO bank of endpoints, +// configures the pull-up and VBus lines, disconnects the pull-up and +// then trigger the Init callback. +// \param pUsb Pointer to a S_usb instance +// \see S_usb +//------------------------------------------------------------------------------ +static void OTGHS_Init(const S_usb *pUsb) +{ + AT91PS_OTGHS pInterface = OTGHS_GetDriverInterface(pUsb); + unsigned char i; + + TRACE_DEBUG_WP("Init()\n\r"); + + // Enable USB macro + SET(OTGHS_GetDriverInterface(pUsb)->OTGHS_CTRL, AT91C_OTGHS_USBECTRL); + + pInterface->OTGHS_DEVCTRL &=~ AT91C_OTGHS_DETACH; // detach + + //// Force FS (for debug or test) +// pDriver->OTGHS_DEVCTRL |= AT91C_OTGHS_SPDCONF_FS; + pInterface->OTGHS_DEVCTRL &= ~AT91C_OTGHS_SPDCONF_FS; // Normal mode + pInterface->OTGHS_DEVCTRL &= ~( AT91C_OTGHS_LS | AT91C_OTGHS_TSTJ + | AT91C_OTGHS_TSTK | AT91C_OTGHS_TSTPCKT + | AT91C_OTGHS_OPMODE2 ); // Normal mode + + + // With OR without DMA !!! + // Initialization of DMA + for( i=1; i<=((AT91C_BASE_OTGHS->OTGHS_IPFEATURES & AT91C_OTGHS_DMA_CHANNEL_NBR)>>4); i++ ) { + + // RESET endpoint canal DMA: + // DMA stop channel command + AT91C_BASE_OTGHS->OTGHS_DEVDMA[i].OTGHS_DEVDMACONTROL = 0; // STOP command + + // Disable endpoint + AT91C_BASE_OTGHS->OTGHS_DEVEPTCDR[i] = 0XFFFFFFFF; + + // Reset endpoint config + AT91C_BASE_OTGHS->OTGHS_DEVEPTCFG[i] = 0; + + // Reset DMA channel (Buff count and Control field) + AT91C_BASE_OTGHS->OTGHS_DEVDMA[i].OTGHS_DEVDMACONTROL = 0x02; // NON STOP command + + // Reset DMA channel 0 (STOP) + AT91C_BASE_OTGHS->OTGHS_DEVDMA[i].OTGHS_DEVDMACONTROL = 0; // STOP command + + // Clear DMA channel status (read the register for clear it) + AT91C_BASE_OTGHS->OTGHS_DEVDMA[i].OTGHS_DEVDMASTATUS = AT91C_BASE_OTGHS->OTGHS_DEVDMA[i].OTGHS_DEVDMASTATUS; + + } + + // Enable clock OTG pad + pInterface->OTGHS_CTRL &= ~AT91C_OTGHS_FRZCLKCTRL; + + // Clear General IT + pInterface->OTGHS_SCR = 0x01FF; + + // Clear OTG Device IT + pInterface->OTGHS_DEVICR = 0xFF; + + // Clear OTG Host IT + pInterface->OTGHS_HSTICR = 0x7F; + + // Reset all Endpoints Fifos + pInterface->OTGHS_DEVEPT |= (0x7F<<16); + pInterface->OTGHS_DEVEPT &= ~(0x7F<<16); + + // Disable all endpoints + pInterface->OTGHS_DEVEPT &= ~0x7F; + + // Bypass UTMI problems // jcb to be removed with new version of UTMI + // pInterface->OTGHS_TSTA2 = (1<<6)|(1<<7)|(1<<8); + // pInterface->OTGHS_TSTA2 = (1<<8); + pInterface->OTGHS_TSTA2 = 0; + + // External pull-up on D+ + // Configure + BRD_ConfigurePullUp(pInterface); + + // Detach + OTGHS_Disconnect(pUsb); + + // Device is in the Attached state + *(pUsb->pState) = USB_STATE_ATTACHED; + + // Disable the UDP transceiver and interrupts + OTGHS_EnableMCK(pUsb); + SET(pInterface->OTGHS_DEVIER, AT91C_OTGHS_EORSM); + + OTGHS_DisableMCK(pUsb); + OTGHS_Disconnect(pUsb); + + // Test ID + if( 0 != (pInterface->OTGHS_SR & AT91C_OTGHS_ID) ) { + TRACE_INFO("ID=1: PERIPHERAL\n\r"); + } + else { + TRACE_INFO("ID=0: HOST\n\r"); + } + + // Test VBUS + if( 0 != (pInterface->OTGHS_SR & AT91C_OTGHS_VBUSSR) ) { + TRACE_INFO("VBUS = 1\n\r"); + } + else { + TRACE_INFO("VBUS = 0\n\r"); + } + + // Test SPEED + if(AT91C_OTGHS_SPEED_SR_HS == (pInterface->OTGHS_SR & (0x03<<12))) { + TRACE_INFO("HIGH SPEED\n\r"); + } + else if(AT91C_OTGHS_SPEED_SR_LS == (pInterface->OTGHS_SR & (0x03<<12))) { + TRACE_INFO("LOW SPEED\n\r"); + } + else { + TRACE_INFO("FULL SPEED\n\r"); + } + + // Configure interrupts + USB_InitCallback(pUsb); + + pInterface->OTGHS_CTRL |= AT91C_OTGHS_VBUSTI; +} + +//------------------------------------------------------------------------------ +// Global variables +//------------------------------------------------------------------------------ + +// \brief Low-level driver methods to use with the OTGHS USB controller +// \see S_driver_methods +const S_driver_methods sOTGHSMethods = { + + OTGHS_Init, + OTGHS_Write, + OTGHS_Read, + OTGHS_Stall, + OTGHS_Halt, + OTGHS_RemoteWakeUp, + OTGHS_ConfigureEndpoint, + OTGHS_Attach, + OTGHS_SetAddress, + OTGHS_SetConfiguration, + OTGHS_Handler, + OTGHS_Connect, + OTGHS_Disconnect, + OTGHS_Test, + OTGHS_IsHighSpeed +}; + +// \brief Default driver when an UDP controller is present on a chip +const S_usb_driver sDefaultDriver = { + + AT91C_BASE_OTGHS, + AT91C_BASE_OTGHS_EPTFIFO, + 0, + AT91C_ID_OTGHS, + AT91C_PMC_OTG, + &sOTGHSMethods +}; + +#endif //#ifdef CHIP_OTGHS + diff --git a/at91lib/usb/device/core/USBD_UDP.c b/at91lib/usb/device/core/USBD_UDP.c new file mode 100644 index 0000000..239ce6e --- /dev/null +++ b/at91lib/usb/device/core/USBD_UDP.c @@ -0,0 +1,1225 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + \unit + + !!!Purpose + + Implementation of USB device functions on a UDP controller. + + See "USBD API Methods". +*/ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "USBD.h" +#include "USBDCallbacks.h" +#include +#include +#include +#include +#include +#include + +#if defined(BOARD_USB_UDP) + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "UDP register field values" +/// +/// This page lists the initialize values of UDP registers. +/// +/// !Values +/// - UDP_RXDATA + +/// Bit mask for both banks of the UDP_CSR register. +#define UDP_RXDATA (AT91C_UDP_RX_DATA_BK0 | AT91C_UDP_RX_DATA_BK1) +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "Endpoint states" +/// +/// This page lists the endpoint states. +/// +/// !States +// - UDP_ENDPOINT_DISABLED +// - UDP_ENDPOINT_HALTED +// - UDP_ENDPOINT_IDLE +// - UDP_ENDPOINT_SENDING +// - UDP_ENDPOINT_RECEIVING + +/// Endpoint states: Endpoint is disabled +#define UDP_ENDPOINT_DISABLED 0 +/// Endpoint states: Endpoint is halted (i.e. STALLs every request) +#define UDP_ENDPOINT_HALTED 1 +/// Endpoint states: Endpoint is idle (i.e. ready for transmission) +#define UDP_ENDPOINT_IDLE 2 +/// Endpoint states: Endpoint is sending data +#define UDP_ENDPOINT_SENDING 3 +/// Endpoint states: Endpoint is receiving data +#define UDP_ENDPOINT_RECEIVING 4 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// \page "UDP_CSR register access" +/// +/// This page lists the macroes to access UDP CSR register. +/// +/// !Macros +/// - CLEAR_CSR +/// - SET_CSR + +/// Bitmap for all status bits in CSR. +#define REG_NO_EFFECT_1_ALL AT91C_UDP_RX_DATA_BK0 | AT91C_UDP_RX_DATA_BK1 \ + |AT91C_UDP_STALLSENT | AT91C_UDP_RXSETUP \ + |AT91C_UDP_TXCOMP + +/// Clears the specified bit(s) in the UDP_CSR register. +/// \param endpoint The endpoint number of the CSR to process. +/// \param flags The bitmap to set to 1. +#define SET_CSR(endpoint, flags) \ + { \ + volatile unsigned int reg; \ + reg = AT91C_BASE_UDP->UDP_CSR[endpoint] ; \ + reg |= REG_NO_EFFECT_1_ALL; \ + reg |= (flags); \ + AT91C_BASE_UDP->UDP_CSR[endpoint] = reg; \ + } + //while ( (AT91C_BASE_UDP->UDP_CSR[endpoint] & (flags)) != (flags)); \ + +/// Sets the specified bit(s) in the UDP_CSR register. +/// \param endpoint The endpoint number of the CSR to process. +/// \param flags The bitmap to clear to 0. +#define CLEAR_CSR(endpoint, flags) \ + { \ + volatile unsigned int reg; \ + reg = AT91C_BASE_UDP->UDP_CSR[endpoint]; \ + reg |= REG_NO_EFFECT_1_ALL; \ + reg &= ~(flags); \ + AT91C_BASE_UDP->UDP_CSR[endpoint] = reg; \ + } + //while ( (AT91C_BASE_UDP->UDP_CSR[endpoint] & (flags)) == (flags)); \ +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Types +//------------------------------------------------------------------------------ + +/// Describes an ongoing transfer on a UDP endpoint. +typedef struct { + + /// Pointer to a data buffer used for emission/reception. + char *pData; + /// Number of bytes which have been written into the UDP internal FIFO + /// buffers. + volatile int buffered; + /// Number of bytes which have been sent/received. + volatile int transferred; + /// Number of bytes which have not been buffered/transferred yet. + volatile int remaining; + /// Optional callback to invoke when the transfer completes. + volatile TransferCallback fCallback; + /// Optional argument to the callback function. + void *pArgument; +} Transfer; + +//------------------------------------------------------------------------------ +/// Describes the state of an endpoint of the UDP controller. +//------------------------------------------------------------------------------ +typedef struct { + + /// Current endpoint state. + volatile unsigned char state; + /// Current reception bank (0 or 1). + volatile unsigned char bank; + /// Maximum packet size for the endpoint. + volatile unsigned short size; + /// Describes an ongoing transfer (if current state is either + /// or ) + Transfer transfer; +} Endpoint; + +//------------------------------------------------------------------------------ +// Internal variables +//------------------------------------------------------------------------------ + +/// Holds the internal state for each endpoint of the UDP. +static Endpoint endpoints[BOARD_USB_NUMENDPOINTS]; + +/// Device current state. +static unsigned char deviceState; +/// Indicates the previous device state +static unsigned char previousDeviceState; + +//------------------------------------------------------------------------------ +// Internal Functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Enables the clock of the UDP peripheral. +//------------------------------------------------------------------------------ +static inline void UDP_EnablePeripheralClock(void) +{ + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_UDP; +} + +//------------------------------------------------------------------------------ +/// Disables the UDP peripheral clock. +//------------------------------------------------------------------------------ +static inline void UDP_DisablePeripheralClock(void) +{ + AT91C_BASE_PMC->PMC_PCDR = 1 << AT91C_ID_UDP; +} + +//------------------------------------------------------------------------------ +/// Enables the 48MHz USB clock. +//------------------------------------------------------------------------------ +static inline void UDP_EnableUsbClock(void) +{ + AT91C_BASE_PMC->PMC_SCER = AT91C_PMC_UDP; +} + +//------------------------------------------------------------------------------ +/// Disables the 48MHz USB clock. +//------------------------------------------------------------------------------ +static inline void UDP_DisableUsbClock(void) +{ + AT91C_BASE_PMC->PMC_SCDR = AT91C_PMC_UDP; +} + +//------------------------------------------------------------------------------ +/// Enables the UDP transceiver. +//------------------------------------------------------------------------------ +static inline void UDP_EnableTransceiver(void) +{ + AT91C_BASE_UDP->UDP_TXVC &= ~AT91C_UDP_TXVDIS; +} + +//------------------------------------------------------------------------------ +/// Disables the UDP transceiver. +//------------------------------------------------------------------------------ +static inline void UDP_DisableTransceiver(void) +{ + AT91C_BASE_UDP->UDP_TXVC |= AT91C_UDP_TXVDIS; +} + +//------------------------------------------------------------------------------ +/// Handles a completed transfer on the given endpoint, invoking the +/// configured callback if any. +/// \param bEndpoint Number of the endpoint for which the transfer has completed. +/// \param bStatus Status code returned by the transfer operation +//------------------------------------------------------------------------------ +static void UDP_EndOfTransfer(unsigned char bEndpoint, char bStatus) +{ + Endpoint *pEndpoint = &(endpoints[bEndpoint]); + Transfer *pTransfer = &(pEndpoint->transfer); + + // Check that endpoint was sending or receiving data + if( (pEndpoint->state == UDP_ENDPOINT_RECEIVING) + || (pEndpoint->state == UDP_ENDPOINT_SENDING)) { + + TRACE_DEBUG_WP("Eo "); + + // Endpoint returns in Idle state + pEndpoint->state = UDP_ENDPOINT_IDLE; + + // Invoke callback is present + if (pTransfer->fCallback != 0) { + + ((TransferCallback) pTransfer->fCallback) + (pTransfer->pArgument, + bStatus, + pTransfer->transferred, + pTransfer->remaining + pTransfer->buffered); + } + else { + TRACE_DEBUG_WP("No callBack\n\r"); + } + } +} + +//------------------------------------------------------------------------------ +/// Clears the correct reception flag (bank 0 or bank 1) of an endpoint +/// \param bEndpoint Index of endpoint +//------------------------------------------------------------------------------ +static void UDP_ClearRxFlag(unsigned char bEndpoint) +{ + Endpoint *pEndpoint = &(endpoints[bEndpoint]); + + // Clear flag and change banks + if (pEndpoint->bank == 0) { + + CLEAR_CSR(bEndpoint, AT91C_UDP_RX_DATA_BK0); + // Swap bank if in dual-fifo mode + if (BOARD_USB_ENDPOINTS_BANKS(bEndpoint) > 1) { + + pEndpoint->bank = 1; + } + } + else { + + CLEAR_CSR(bEndpoint, AT91C_UDP_RX_DATA_BK1); + pEndpoint->bank = 0; + } +} + +//------------------------------------------------------------------------------ +/// Transfers a data payload from the current tranfer buffer to the endpoint +/// FIFO +/// \param bEndpoint Number of the endpoint which is sending data. +//------------------------------------------------------------------------------ +static void UDP_WritePayload(unsigned char bEndpoint) +{ + Endpoint *pEndpoint = &(endpoints[bEndpoint]); + Transfer *pTransfer = &(pEndpoint->transfer); + signed int size; + + // Get the number of bytes to send + size = pEndpoint->size; + if (size > pTransfer->remaining) { + + size = pTransfer->remaining; + } + + // Update transfer descriptor information + pTransfer->buffered += size; + pTransfer->remaining -= size; + + // Write packet in the FIFO buffer + while (size > 0) { + + AT91C_BASE_UDP->UDP_FDR[bEndpoint] = *(pTransfer->pData); + pTransfer->pData++; + size--; + } +} + + +//------------------------------------------------------------------------------ +/// Transfers a data payload from an endpoint FIFO to the current transfer buffer +/// \param bEndpoint Endpoint number. +/// \param wPacketSize Size of received data packet +//------------------------------------------------------------------------------ +static void UDP_ReadPayload(unsigned char bEndpoint, int wPacketSize) +{ + Endpoint *pEndpoint = &(endpoints[bEndpoint]); + Transfer *pTransfer = &(pEndpoint->transfer); + + // Check that the requested size is not bigger than the remaining transfer + if (wPacketSize > pTransfer->remaining) { + + pTransfer->buffered += wPacketSize - pTransfer->remaining; + wPacketSize = pTransfer->remaining; + } + + // Update transfer descriptor information + pTransfer->remaining -= wPacketSize; + pTransfer->transferred += wPacketSize; + + // Retrieve packet + while (wPacketSize > 0) { + + *(pTransfer->pData) = (char) AT91C_BASE_UDP->UDP_FDR[bEndpoint]; + pTransfer->pData++; + wPacketSize--; + } +} + +//------------------------------------------------------------------------------ +/// Received SETUP packet from endpoint 0 FIFO +/// \param pRequest Generic USB SETUP request sent over Control endpoints +//------------------------------------------------------------------------------ +static void UDP_ReadRequest(USBGenericRequest *pRequest) +{ + unsigned char *pData = (unsigned char *)pRequest; + unsigned int i; + + // Copy packet + for (i = 0; i < 8; i++) { + + *pData = (unsigned char) AT91C_BASE_UDP->UDP_FDR[0]; + pData++; + } +} + +//------------------------------------------------------------------------------ +/// Reset all endpoint transfer descriptors +//------------------------------------------------------------------------------ +static void UDP_ResetEndpoints( void ) +{ + Endpoint *pEndpoint; + Transfer *pTransfer; + unsigned char bEndpoint; + + // Reset the transfer descriptor of every endpoint + for (bEndpoint = 0; bEndpoint < BOARD_USB_NUMENDPOINTS; bEndpoint++) { + + pEndpoint = &(endpoints[bEndpoint]); + pTransfer = &(pEndpoint->transfer); + + // Reset endpoint transfer descriptor + pTransfer->pData = 0; + pTransfer->transferred = -1; + pTransfer->buffered = -1; + pTransfer->remaining = -1; + pTransfer->fCallback = 0; + pTransfer->pArgument = 0; + + // Reset endpoint state + pEndpoint->bank = 0; + pEndpoint->state = UDP_ENDPOINT_DISABLED; + } +} + +//------------------------------------------------------------------------------ +/// Disable all endpoints (except control endpoint 0), aborting current +/// transfers if necessary +//------------------------------------------------------------------------------ +static void UDP_DisableEndpoints( void ) + +{ + unsigned char bEndpoint; + + // Disable each endpoint, terminating any pending transfer + // Control endpoint 0 is not disabled + for (bEndpoint = 1; bEndpoint < BOARD_USB_NUMENDPOINTS; bEndpoint++) { + + UDP_EndOfTransfer(bEndpoint, USBD_STATUS_ABORTED); + endpoints[bEndpoint].state = UDP_ENDPOINT_DISABLED; + } +} + +//------------------------------------------------------------------------------ +/// Checks if an ongoing transfer on an endpoint has been completed. +/// \param bEndpoint Endpoint number. +/// \return 1 if the current transfer on the given endpoint is complete; +/// otherwise 0. +//------------------------------------------------------------------------------ +static unsigned char UDP_IsTransferFinished(unsigned char bEndpoint) +{ + Endpoint *pEndpoint = &(endpoints[bEndpoint]); + Transfer *pTransfer = &(pEndpoint->transfer); + + // Check if it is a Control endpoint + // -> Control endpoint must always finish their transfer with a zero-length + // packet + if ((AT91C_BASE_UDP->UDP_CSR[bEndpoint] & AT91C_UDP_EPTYPE) + == AT91C_UDP_EPTYPE_CTRL) { + + return (pTransfer->buffered < pEndpoint->size); + } + // Other endpoints only need to transfer all the data + else { + + return (pTransfer->buffered <= pEndpoint->size) + && (pTransfer->remaining == 0); + } +} + +//------------------------------------------------------------------------------ +/// Endpoint interrupt handler. +/// Handle IN/OUT transfers, received SETUP packets and STALLing +/// \param bEndpoint Index of endpoint +//------------------------------------------------------------------------------ +static void UDP_EndpointHandler(unsigned char bEndpoint) +{ + Endpoint *pEndpoint = &(endpoints[bEndpoint]); + Transfer *pTransfer = &(pEndpoint->transfer); + unsigned int status = AT91C_BASE_UDP->UDP_CSR[bEndpoint]; + unsigned short wPacketSize; + USBGenericRequest request; + + TRACE_DEBUG_WP("E%d ", bEndpoint); + TRACE_DEBUG_WP("st:0x%X ", status); + + // Handle interrupts + // IN packet sent + if ((status & AT91C_UDP_TXCOMP) != 0) { + + TRACE_DEBUG_WP("Wr "); + + // Check that endpoint was in Sending state + if (pEndpoint->state == UDP_ENDPOINT_SENDING) { + + // End of transfer ? + if (UDP_IsTransferFinished(bEndpoint)) { + + pTransfer->transferred += pTransfer->buffered; + pTransfer->buffered = 0; + + // Disable interrupt if this is not a control endpoint + if ((status & AT91C_UDP_EPTYPE) != AT91C_UDP_EPTYPE_CTRL) { + + AT91C_BASE_UDP->UDP_IDR = 1 << bEndpoint; + } + + UDP_EndOfTransfer(bEndpoint, USBD_STATUS_SUCCESS); + CLEAR_CSR(bEndpoint, AT91C_UDP_TXCOMP); + } + else { + + // Transfer remaining data + TRACE_DEBUG_WP(" %d ", pEndpoint->size); + + pTransfer->transferred += pEndpoint->size; + pTransfer->buffered -= pEndpoint->size; + + // Send next packet + if (BOARD_USB_ENDPOINTS_BANKS(bEndpoint) == 1) { + + // No double buffering + UDP_WritePayload(bEndpoint); + SET_CSR(bEndpoint, AT91C_UDP_TXPKTRDY); + CLEAR_CSR(bEndpoint, AT91C_UDP_TXCOMP); + } + else { + // Double buffering + SET_CSR(bEndpoint, AT91C_UDP_TXPKTRDY); + CLEAR_CSR(bEndpoint, AT91C_UDP_TXCOMP); + UDP_WritePayload(bEndpoint); + } + } + } + else { + // Acknowledge interrupt + TRACE_ERROR("Error Wr"); + CLEAR_CSR(bEndpoint, AT91C_UDP_TXCOMP); + } + } + + // OUT packet received + if ((status & UDP_RXDATA) != 0) { + + TRACE_DEBUG_WP("Rd "); + + // Check that the endpoint is in Receiving state + if (pEndpoint->state != UDP_ENDPOINT_RECEIVING) { + + // Check if an ACK has been received on a Control endpoint + if (((status & AT91C_UDP_EPTYPE) == AT91C_UDP_EPTYPE_CTRL) + && ((status & AT91C_UDP_RXBYTECNT) == 0)) { + + // Acknowledge the data and finish the current transfer + UDP_ClearRxFlag(bEndpoint); + UDP_EndOfTransfer(bEndpoint, USBD_STATUS_SUCCESS); + } + // Check if the data has been STALLed + else if ((status & AT91C_UDP_FORCESTALL) != 0) { + + // Discard STALLed data + TRACE_DEBUG_WP("Discard "); + UDP_ClearRxFlag(bEndpoint); + } + // NAK the data + else { + + TRACE_DEBUG_WP("Nak "); + AT91C_BASE_UDP->UDP_IDR = 1 << bEndpoint; + } + } + // Endpoint is in Read state + else { + + // Retrieve data and store it into the current transfer buffer + wPacketSize = (unsigned short) (status >> 16); + TRACE_DEBUG_WP("%d ", wPacketSize); + UDP_ReadPayload(bEndpoint, wPacketSize); + UDP_ClearRxFlag(bEndpoint); + + // Check if the transfer is finished + if ((pTransfer->remaining == 0) || (wPacketSize < pEndpoint->size)) { + + // Disable interrupt if this is not a control endpoint + if ((status & AT91C_UDP_EPTYPE) != AT91C_UDP_EPTYPE_CTRL) { + + AT91C_BASE_UDP->UDP_IDR = 1 << bEndpoint; + } + UDP_EndOfTransfer(bEndpoint, USBD_STATUS_SUCCESS); + } + } + } + + // STALL sent + if ((status & AT91C_UDP_STALLSENT) != 0) { + + TRACE_WARNING( "Sta 0x%X [%d] ", status, bEndpoint); + + // If the endpoint is not halted, clear the STALL condition + CLEAR_CSR(bEndpoint, AT91C_UDP_STALLSENT); + if (pEndpoint->state != UDP_ENDPOINT_HALTED) { + + TRACE_WARNING( "_ " ); + CLEAR_CSR(bEndpoint, AT91C_UDP_FORCESTALL); + } + } + + // SETUP packet received + if ((status & AT91C_UDP_RXSETUP) != 0) { + + TRACE_DEBUG_WP("Stp "); + + // If a transfer was pending, complete it + // Handles the case where during the status phase of a control write + // transfer, the host receives the device ZLP and ack it, but the ack + // is not received by the device + if ((pEndpoint->state == UDP_ENDPOINT_RECEIVING) + || (pEndpoint->state == UDP_ENDPOINT_SENDING)) { + + UDP_EndOfTransfer(bEndpoint, USBD_STATUS_SUCCESS); + } + // Copy the setup packet + UDP_ReadRequest(&request); + + // Set the DIR bit before clearing RXSETUP in Control IN sequence + if (USBGenericRequest_GetDirection(&request) == USBGenericRequest_IN) { + + SET_CSR(bEndpoint, AT91C_UDP_DIR); + } + // Acknowledge setup packet + CLEAR_CSR(bEndpoint, AT91C_UDP_RXSETUP); + + // Forward the request to the upper layer + USBDCallbacks_RequestReceived(&request); + } + +} + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +/// USB interrupt handler +/// Manages device resume, suspend, end of bus reset. +/// Forwards endpoint interrupts to the appropriate handler. +//------------------------------------------------------------------------------ +void USBD_InterruptHandler(void) +{ + unsigned int status; + int eptnum = 0; + + // Get interrupt status + // Some interrupts may get masked depending on the device state + status = AT91C_BASE_UDP->UDP_ISR; + status &= AT91C_BASE_UDP->UDP_IMR; + + if (deviceState < USBD_STATE_POWERED) { + + status &= AT91C_UDP_WAKEUP | AT91C_UDP_RXRSM; + AT91C_BASE_UDP->UDP_ICR = ~status; + } + + // Return immediately if there is no interrupt to service + if (status == 0) { + + return; + } + + // Toggle USB LED if the device is active + if (deviceState >= USBD_STATE_POWERED) { + + //LED_Set(USBD_LEDUSB); + } + + // Service interrupts + + //// Start Of Frame (SOF) + //if (ISSET(dStatus, AT91C_UDP_SOFINT)) { + // + // TRACE_DEBUG("SOF"); + // + // // Invoke the SOF callback + // USB_StartOfFrameCallback(pUsb); + // + // // Acknowledge interrupt + // AT91C_BASE_UDP->UDP_ICR = AT91C_UDP_SOFINT; + // dStatus &= ~AT91C_UDP_SOFINT; + //} + + // Suspend + // This interrupt is always treated last (hence the '==') + if (status == AT91C_UDP_RXSUSP) { + + TRACE_INFO_WP("Susp "); + + // Don't do anything if the device is already suspended + if (deviceState != USBD_STATE_SUSPENDED) { + + // The device enters the Suspended state + // Enable wakeup + AT91C_BASE_UDP->UDP_IER = AT91C_UDP_WAKEUP | AT91C_UDP_RXRSM; + + // Acknowledge interrupt + AT91C_BASE_UDP->UDP_ICR = AT91C_UDP_RXSUSP; + + // Switch to the Suspended state + previousDeviceState = deviceState; + deviceState = USBD_STATE_SUSPENDED; + // Invoke the Suspended callback + USBDCallbacks_Suspended(); + UDP_DisableTransceiver(); + UDP_DisablePeripheralClock(); + UDP_DisableUsbClock(); + } + } + // Resume + else if ((status & (AT91C_UDP_WAKEUP | AT91C_UDP_RXRSM)) != 0) { + + TRACE_INFO_WP("Res \n\r"); + + // Don't do anything if the device was not suspended + if (deviceState == USBD_STATE_SUSPENDED) { + + // The device enters its previous state + UDP_EnablePeripheralClock(); + UDP_EnableUsbClock(); + + // Enable the transceiver if the device was past the Default + // state + deviceState = previousDeviceState; + if (deviceState >= USBD_STATE_DEFAULT) { + + UDP_EnableTransceiver(); + + // Invoke the Resume callback + USBDCallbacks_Resumed(); + } + } + + // Clear and disable resume interrupts + AT91C_BASE_UDP->UDP_ICR = AT91C_UDP_WAKEUP + | AT91C_UDP_RXRSM + | AT91C_UDP_RXSUSP; + AT91C_BASE_UDP->UDP_IDR = AT91C_UDP_WAKEUP | AT91C_UDP_RXRSM; + } + // End of bus reset + else if ((status & AT91C_UDP_ENDBUSRES) != 0) { + + TRACE_INFO_WP("EoBRes \n\r"); + + // The device enters the Default state + deviceState = USBD_STATE_DEFAULT; + UDP_EnableTransceiver(); + UDP_ResetEndpoints(); + UDP_DisableEndpoints(); + USBD_ConfigureEndpoint(0); + + // Flush and enable the Suspend interrupt + AT91C_BASE_UDP->UDP_ICR = AT91C_UDP_WAKEUP + | AT91C_UDP_RXRSM + | AT91C_UDP_RXSUSP; + AT91C_BASE_UDP->UDP_IER = AT91C_UDP_RXSUSP; + + //// Enable the Start Of Frame (SOF) interrupt if needed + //if (pUsb->pCallbacks->startOfFrame != 0) { + // + // AT91C_BASE_UDP->UDP_IER = AT91C_UDP_SOFINT; + //} + + // Invoke the Reset callback + USBDCallbacks_Reset(); + + // Acknowledge end of bus reset interrupt + AT91C_BASE_UDP->UDP_ICR = AT91C_UDP_ENDBUSRES; + } + // Endpoint interrupts + else { + + while (status != 0) { + + // Check if endpoint has a pending interrupt + if ((status & (1 << eptnum)) != 0) { + + UDP_EndpointHandler(eptnum); + status &= ~(1 << eptnum); + + if (status != 0) { + + TRACE_INFO_WP("\n\r - "); + } + } + eptnum++; + } + } + + // Toggle LED back to its previous state + TRACE_INFO_WP("\n\r"); + if (deviceState >= USBD_STATE_POWERED) { + + //LED_Clear(USBD_LEDUSB); + } +} + +//------------------------------------------------------------------------------ +/// Configures an endpoint according to its Endpoint Descriptor. +/// \param pDescriptor Pointer to an Endpoint descriptor. +//------------------------------------------------------------------------------ +void USBD_ConfigureEndpoint(const USBEndpointDescriptor *pDescriptor) +{ + Endpoint *pEndpoint; + unsigned char bEndpoint; + unsigned char bType; + unsigned char bEndpointDir; + + // NULL descriptor -> Control endpoint 0 + if (pDescriptor == 0) { + + bEndpoint = 0; + pEndpoint = &(endpoints[bEndpoint]); + bType= USBEndpointDescriptor_CONTROL; + bEndpointDir = 0; + pEndpoint->size = BOARD_USB_ENDPOINTS_MAXPACKETSIZE(0); + } + else { + + bEndpoint = USBEndpointDescriptor_GetNumber(pDescriptor); + pEndpoint = &(endpoints[bEndpoint]); + bType = USBEndpointDescriptor_GetType(pDescriptor); + bEndpointDir = USBEndpointDescriptor_GetDirection(pDescriptor); + pEndpoint->size = USBEndpointDescriptor_GetMaxPacketSize(pDescriptor); + } + + // Abort the current transfer is the endpoint was configured and in + // Write or Read state + if ((pEndpoint->state == UDP_ENDPOINT_RECEIVING) + || (pEndpoint->state == UDP_ENDPOINT_SENDING)) { + + UDP_EndOfTransfer(bEndpoint, USBD_STATUS_RESET); + } + pEndpoint->state = UDP_ENDPOINT_IDLE; + + // Reset Endpoint Fifos + AT91C_BASE_UDP->UDP_RSTEP |= (1 << bEndpoint); + AT91C_BASE_UDP->UDP_RSTEP &= ~(1 << bEndpoint); + + // Configure endpoint + SET_CSR(bEndpoint, (unsigned int)AT91C_UDP_EPEDS | (bType << 8) | (bEndpointDir << 10)); + if (bType == USBEndpointDescriptor_CONTROL) { + + AT91C_BASE_UDP->UDP_IER = (1 << bEndpoint); + } + + TRACE_INFO_WP("CfgEpt%d \n\r", bEndpoint); +} + +//------------------------------------------------------------------------------ +/// Sends data through a USB endpoint. Sets up the transfer descriptor, +/// writes one or two data payloads (depending on the number of FIFO bank +/// for the endpoint) and then starts the actual transfer. The operation is +/// complete when all the data has been sent. +/// +/// *If the size of the buffer is greater than the size of the endpoint +/// (or twice the size if the endpoint has two FIFO banks), then the buffer +/// must be kept allocated until the transfer is finished*. This means that +/// it is not possible to declare it on the stack (i.e. as a local variable +/// of a function which returns after starting a transfer). +/// +/// \param bEndpoint Endpoint number. +/// \param pData Pointer to a buffer with the data to send. +/// \param dLength Size of the data buffer. +/// \param fCallback Optional callback function to invoke when the transfer is +/// complete. +/// \param pArgument Optional argument to the callback function. +/// \return USBD_STATUS_SUCCESS if the transfer has been started; +/// otherwise, the corresponding error status code. +//------------------------------------------------------------------------------ +char USBD_Write( unsigned char bEndpoint, + const void *pData, + unsigned int dLength, + TransferCallback fCallback, + void *pArgument ) +{ + Endpoint *pEndpoint = &(endpoints[bEndpoint]); + Transfer *pTransfer = &(pEndpoint->transfer); + + // Check that the endpoint is in Idle state + if (pEndpoint->state != UDP_ENDPOINT_IDLE) { + + return USBD_STATUS_LOCKED; + } + TRACE_DEBUG_WP("Write%d(%d) \n\r", bEndpoint, dLength); + + // Setup the transfer descriptor + pTransfer->pData = (void *) pData; + pTransfer->remaining = dLength; + pTransfer->buffered = 0; + pTransfer->transferred = 0; + pTransfer->fCallback = fCallback; + pTransfer->pArgument = pArgument; + + // Send the first packet + pEndpoint->state = UDP_ENDPOINT_SENDING; + while((AT91C_BASE_UDP->UDP_CSR[bEndpoint]&AT91C_UDP_TXPKTRDY)==AT91C_UDP_TXPKTRDY); + + UDP_WritePayload(bEndpoint); + SET_CSR(bEndpoint, AT91C_UDP_TXPKTRDY); + + // If double buffering is enabled and there is data remaining, + // prepare another packet + if ((BOARD_USB_ENDPOINTS_BANKS(bEndpoint) > 1) && (pTransfer->remaining > 0)) { + + UDP_WritePayload(bEndpoint); + } + + // Enable interrupt on endpoint + AT91C_BASE_UDP->UDP_IER = 1 << bEndpoint; + + return USBD_STATUS_SUCCESS; +} + + +//------------------------------------------------------------------------------ +/// Reads incoming data on an USB endpoint This methods sets the transfer +/// descriptor and activate the endpoint interrupt. The actual transfer is +/// then carried out by the endpoint interrupt handler. The Read operation +/// finishes either when the buffer is full, or a short packet (inferior to +/// endpoint maximum size) is received. +/// +/// *The buffer must be kept allocated until the transfer is finished*. +/// \param bEndpoint Endpoint number. +/// \param pData Pointer to a data buffer. +/// \param dLength Size of the data buffer in bytes. +/// \param fCallback Optional end-of-transfer callback function. +/// \param pArgument Optional argument to the callback function. +/// \return USBD_STATUS_SUCCESS if the read operation has been started; +/// otherwise, the corresponding error code. +//------------------------------------------------------------------------------ +char USBD_Read(unsigned char bEndpoint, + void *pData, + unsigned int dLength, + TransferCallback fCallback, + void *pArgument) +{ + Endpoint *pEndpoint = &(endpoints[bEndpoint]); + Transfer *pTransfer = &(pEndpoint->transfer); + + // Return if the endpoint is not in IDLE state + if (pEndpoint->state != UDP_ENDPOINT_IDLE) { + + return USBD_STATUS_LOCKED; + } + + // Endpoint enters Receiving state + pEndpoint->state = UDP_ENDPOINT_RECEIVING; + TRACE_DEBUG_WP("Read%d(%d) \n\r", bEndpoint, dLength); + + // Set the transfer descriptor + pTransfer->pData = pData; + pTransfer->remaining = dLength; + pTransfer->buffered = 0; + pTransfer->transferred = 0; + pTransfer->fCallback = fCallback; + pTransfer->pArgument = pArgument; + + // Enable interrupt on endpoint + AT91C_BASE_UDP->UDP_IER = 1 << bEndpoint; + + return USBD_STATUS_SUCCESS; +} + +//------------------------------------------------------------------------------ +/// Sets the HALT feature on the given endpoint (if not already in this state). +/// \param bEndpoint Endpoint number. +//------------------------------------------------------------------------------ +void USBD_Halt(unsigned char bEndpoint) +{ + Endpoint *pEndpoint = &(endpoints[bEndpoint]); + + // Check that endpoint is enabled and not already in Halt state + if ((pEndpoint->state != UDP_ENDPOINT_DISABLED) + && (pEndpoint->state != UDP_ENDPOINT_HALTED)) { + + TRACE_DEBUG_WP("Halt%d \n\r", bEndpoint); + + // Abort the current transfer if necessary + UDP_EndOfTransfer(bEndpoint, USBD_STATUS_ABORTED); + + // Put endpoint into Halt state + SET_CSR(bEndpoint, AT91C_UDP_FORCESTALL); + pEndpoint->state = UDP_ENDPOINT_HALTED; + + // Enable the endpoint interrupt + AT91C_BASE_UDP->UDP_IER = 1 << bEndpoint; + } +} + +//------------------------------------------------------------------------------ +/// Clears the Halt feature on the given endpoint. +/// \param bEndpoint Index of endpoint +//------------------------------------------------------------------------------ +void USBD_Unhalt(unsigned char bEndpoint) +{ + Endpoint *pEndpoint = &(endpoints[bEndpoint]); + + // Check if the endpoint is enabled + if (pEndpoint->state != UDP_ENDPOINT_DISABLED) { + + TRACE_DEBUG_WP("Unhalt%d \n\r", bEndpoint); + + // Return endpoint to Idle state + pEndpoint->state = UDP_ENDPOINT_IDLE; + + // Clear FORCESTALL flag + CLEAR_CSR(bEndpoint, AT91C_UDP_FORCESTALL); + + // Reset Endpoint Fifos, beware this is a 2 steps operation + AT91C_BASE_UDP->UDP_RSTEP |= 1 << bEndpoint; + AT91C_BASE_UDP->UDP_RSTEP &= ~(1 << bEndpoint); + } +} + +//------------------------------------------------------------------------------ +/// Returns the current Halt status of an endpoint. +/// \param bEndpoint Index of endpoint +/// \return 1 if the endpoint is currently halted; otherwise 0 +//------------------------------------------------------------------------------ +unsigned char USBD_IsHalted(unsigned char bEndpoint) +{ + Endpoint *pEndpoint = &(endpoints[bEndpoint]); + unsigned char status = 0; + + if (pEndpoint->state == UDP_ENDPOINT_HALTED) { + + status = 1; + } + return( status ); +} + +//------------------------------------------------------------------------------ +/// Indicates if the device is running in high or full-speed. Always returns 0 +/// since UDP does not support high-speed mode. +//------------------------------------------------------------------------------ +unsigned char USBD_IsHighSpeed(void) +{ + return 0; +} + +//------------------------------------------------------------------------------ +/// Causes the given endpoint to acknowledge the next packet it receives +/// with a STALL handshake. +/// \param bEndpoint Endpoint number. +/// \return USBD_STATUS_SUCCESS or USBD_STATUS_LOCKED. +//------------------------------------------------------------------------------ +unsigned char USBD_Stall(unsigned char bEndpoint) + +{ + Endpoint *pEndpoint = &(endpoints[bEndpoint]); + + // Check that endpoint is in Idle state + if (pEndpoint->state != UDP_ENDPOINT_IDLE) { + + TRACE_WARNING("UDP_Stall: Endpoint%d locked\n\r", bEndpoint); + return USBD_STATUS_LOCKED; + } + + TRACE_DEBUG_WP("Stall%d \n\r", bEndpoint); + SET_CSR(bEndpoint, AT91C_UDP_FORCESTALL); + + return USBD_STATUS_SUCCESS; +} + +//------------------------------------------------------------------------------ +/// Starts a remote wake-up procedure. +//------------------------------------------------------------------------------ +void USBD_RemoteWakeUp(void) +{ + UDP_EnablePeripheralClock(); + UDP_EnableUsbClock(); + UDP_EnableTransceiver(); + + TRACE_INFO_WP("RWUp \n\r"); + + // Activates a remote wakeup (edge on ESR), then clear ESR + AT91C_BASE_UDP->UDP_GLBSTATE |= AT91C_UDP_ESR; + AT91C_BASE_UDP->UDP_GLBSTATE &= ~AT91C_UDP_ESR; +} + +//------------------------------------------------------------------------------ +/// Sets the device address to the given value. +/// \param address New device address. +//------------------------------------------------------------------------------ +void USBD_SetAddress(unsigned char address) +{ + TRACE_INFO_WP("SetAddr(%d) \n\r", address); + + // Set address + AT91C_BASE_UDP->UDP_FADDR = AT91C_UDP_FEN | address; + + // If the address is 0, the device returns to the Default state + if (address == 0) { + + AT91C_BASE_UDP->UDP_GLBSTATE = 0; + deviceState = USBD_STATE_DEFAULT; + } + // If the address is non-zero, the device enters the Address state + else { + + AT91C_BASE_UDP->UDP_GLBSTATE = AT91C_UDP_FADDEN; + deviceState = USBD_STATE_ADDRESS; + } +} + +//------------------------------------------------------------------------------ +/// Sets the current device configuration. +/// \param cfgnum - Configuration number to set. +//------------------------------------------------------------------------------ +void USBD_SetConfiguration(unsigned char cfgnum) +{ + TRACE_INFO_WP("SetCfg(%d) \n\r", cfgnum); + + // If the configuration number if non-zero, the device enters the + // Configured state + if (cfgnum != 0) { + + // Enter Configured state + deviceState = USBD_STATE_CONFIGURED; + AT91C_BASE_UDP->UDP_GLBSTATE |= AT91C_UDP_CONFG; + } + // If the configuration number is zero, the device goes back to the Address + // state + else { + + deviceState = USBD_STATE_ADDRESS; + AT91C_BASE_UDP->UDP_GLBSTATE = AT91C_UDP_FADDEN; + + // Abort all transfers + UDP_DisableEndpoints(); + } +} + +//------------------------------------------------------------------------------ +/// Connects the pull-up on the D+ line of the USB. +//------------------------------------------------------------------------------ +void USBD_Connect(void) +{ + TRACE_DEBUG("Conn \n\r"); + +#if defined(BOARD_USB_PULLUP_EXTERNAL) + const Pin pinPullUp = PIN_USB_PULLUP; + if (pinPullUp.attribute == PIO_OUTPUT_0) { + + PIO_Set(&pinPullUp); + } + else { + + PIO_Clear(&pinPullUp); + } +#elif defined(BOARD_USB_PULLUP_INTERNAL) + AT91C_BASE_UDP->UDP_TXVC |= AT91C_UDP_PUON; +#elif defined(BOARD_USB_PULLUP_MATRIX) + AT91C_BASE_MATRIX->MATRIX_USBPCR |= AT91C_MATRIX_USBPCR_PUON; +#elif !defined(BOARD_USB_PULLUP_ALWAYSON) + #error Unsupported pull-up type. +#endif +} + +//------------------------------------------------------------------------------ +/// Disconnects the pull-up from the D+ line of the USB. +//------------------------------------------------------------------------------ +void USBD_Disconnect(void) +{ + TRACE_DEBUG("Disc \n\r"); + +#if defined(BOARD_USB_PULLUP_EXTERNAL) + const Pin pinPullUp = PIN_USB_PULLUP; + if (pinPullUp.attribute == PIO_OUTPUT_0) { + + PIO_Clear(&pinPullUp); + } + else { + + PIO_Set(&pinPullUp); + } +#elif defined(BOARD_USB_PULLUP_INTERNAL) + AT91C_BASE_UDP->UDP_TXVC &= ~AT91C_UDP_PUON; +#elif defined(BOARD_USB_PULLUP_MATRIX) + AT91C_BASE_MATRIX->MATRIX_USBPCR &= ~AT91C_MATRIX_USBPCR_PUON; +#elif !defined(BOARD_USB_PULLUP_ALWAYSON) + #error Unsupported pull-up type. +#endif + + // Device returns to the Powered state + if (deviceState > USBD_STATE_POWERED) { + + deviceState = USBD_STATE_POWERED; + } +} + +//------------------------------------------------------------------------------ +/// Initializes the USB driver. +//------------------------------------------------------------------------------ +void USBD_Init(void) +{ + TRACE_INFO_WP("USBD_Init\n\r"); + + // Reset endpoint structures + UDP_ResetEndpoints(); + + // Configure the pull-up on D+ and disconnect it +#if defined(BOARD_USB_PULLUP_EXTERNAL) + const Pin pinPullUp = PIN_USB_PULLUP; + PIO_Configure(&pinPullUp, 1); +#elif defined(BOARD_USB_PULLUP_INTERNAL) + AT91C_BASE_UDP->UDP_TXVC &= ~AT91C_UDP_PUON; +#elif defined(BOARD_USB_PULLUP_MATRIX) + AT91C_BASE_MATRIX->MATRIX_USBPCR &= ~AT91C_MATRIX_USBPCR_PUON; +#elif !defined(BOARD_USB_PULLUP_ALWAYSON) + #error Missing pull-up definition. +#endif + + // Device is in the Attached state + deviceState = USBD_STATE_SUSPENDED; + previousDeviceState = USBD_STATE_POWERED; + UDP_EnablePeripheralClock(); + UDP_EnableUsbClock(); + + AT91C_BASE_UDP->UDP_IDR = 0xFE; + + AT91C_BASE_UDP->UDP_IER = AT91C_UDP_WAKEUP; + + // Configure interrupts + USBDCallbacks_Initialized(); +} + +//------------------------------------------------------------------------------ +/// Returns the current state of the USB device. +/// \return Device current state. +//------------------------------------------------------------------------------ +unsigned char USBD_GetState(void) +{ + return deviceState; +} + +#endif // BOARD_USB_UDP + diff --git a/at91lib/usb/device/core/USBD_UDPHS.c b/at91lib/usb/device/core/USBD_UDPHS.c new file mode 100644 index 0000000..f7c0684 --- /dev/null +++ b/at91lib/usb/device/core/USBD_UDPHS.c @@ -0,0 +1,1680 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "USBD.h" +#include "USBDCallbacks.h" +#include "USBDDriver.h" +#include +#include +#include +#include +#include +#include +#include + +#include + +#ifdef BOARD_USB_UDPHS + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +/// Maximum number of endpoints interrupts. +#define NUM_IT_MAX \ + (AT91C_BASE_UDPHS->UDPHS_IPFEATURES & AT91C_UDPHS_EPT_NBR_MAX) +/// Maximum number of endpoint DMA interrupts +#define NUM_IT_MAX_DMA \ + ((AT91C_BASE_UDPHS->UDPHS_IPFEATURES & AT91C_UDPHS_DMA_CHANNEL_NBR)>>4) +/// Bits that should be shifted to access DMA control bits. +#define SHIFT_DMA 24 +/// Bits that should be shifted to access interrupt bits. +#define SHIFT_INTERUPT 8 + +/// Compile option, use DMA. Remove this define for not use DMA. +#define DMA + +/// Max size of the FMA FIFO +#define DMA_MAX_FIFO_SIZE 65536 + +//------------------------------------------------------------------------------ +/// \page "Endpoint states" +/// This page lists the endpoint states. +/// !States +// - UDP_ENDPOINT_DISABLED +// - UDP_ENDPOINT_HALTED +// - UDP_ENDPOINT_IDLE +// - UDP_ENDPOINT_SENDING +// - UDP_ENDPOINT_RECEIVING + +/// Endpoint states: Endpoint is disabled +#define UDP_ENDPOINT_DISABLED 0 +/// Endpoint states: Endpoint is halted (i.e. STALLs every request) +#define UDP_ENDPOINT_HALTED 1 +/// Endpoint states: Endpoint is idle (i.e. ready for transmission) +#define UDP_ENDPOINT_IDLE 2 +/// Endpoint states: Endpoint is sending data +#define UDP_ENDPOINT_SENDING 3 +/// Endpoint states: Endpoint is receiving data +#define UDP_ENDPOINT_RECEIVING 4 +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Structures +//------------------------------------------------------------------------------ + +/// Describes an ongoing transfer on a UDP endpoint. +typedef struct +{ + /// Pointer to a data buffer used for emission/reception. + char *pData; + /// Number of bytes which have been written into the UDP internal FIFO + /// buffers. + volatile int buffered; + /// Number of bytes which have been sent/received. + volatile int transferred; + /// Number of bytes which have not been buffered/transferred yet. + volatile int remaining; + /// Optional callback to invoke when the transfer completes. + volatile TransferCallback fCallback; + /// Optional argument to the callback function. + void *pArgument; +} Transfer; + +//------------------------------------------------------------------------------ +/// Describes the state of an endpoint of the UDP controller. +//------------------------------------------------------------------------------ +typedef struct +{ + /// Current endpoint state. + volatile unsigned char state; + /// Current reception bank (0 or 1). + unsigned char bank; + /// Maximum packet size for the endpoint. + unsigned short size; + /// Describes an ongoing transfer (if current state is either + /// or ) + Transfer transfer; +} Endpoint; + +//------------------------------------------------------------------------------ +// Internal variables +//------------------------------------------------------------------------------ + +/// Holds the internal state for each endpoint of the UDP. +static Endpoint endpoints[BOARD_USB_NUMENDPOINTS]; +/// Device current state. +static unsigned char deviceState; +/// Indicates the previous device state +static unsigned char previousDeviceState; +/// Special case for send a ZLP +static unsigned char sendZLP = 0; + +/// 7.1.20 Test Mode Support +/// Test codes for the USB HS test mode. +static const char test_packet_buffer[] = { + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, // JKJKJKJK * 9 + 0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA, // JJKKJJKK * 8 + 0xEE,0xEE,0xEE,0xEE,0xEE,0xEE,0xEE,0xEE, // JJJJKKKK * 8 + 0xFE,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, // JJJJJJJKKKKKKK * 8 + 0x7F,0xBF,0xDF,0xEF,0xF7,0xFB,0xFD, // JJJJJJJK * 8 + 0xFC,0x7E,0xBF,0xDF,0xEF,0xF7,0xFB,0xFD,0x7E // {JKKKKKKK * 10}, JK +}; + +//------------------------------------------------------------------------------ +// Internal Functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Disables the BIAS of the USB controller +//------------------------------------------------------------------------------ +static inline void UDPHS_DisableBIAS( void ) +{ + // For CAP9, SAM9RL, HS +#if !defined (BOARD_USB_NO_BIAS_COMMAND) + AT91C_BASE_PMC->PMC_UCKR &= ~AT91C_CKGR_BIASEN_ENABLED; +#endif +} + +//------------------------------------------------------------------------------ +/// Enables the BIAS of the USB controller +//------------------------------------------------------------------------------ +static inline void UDPHS_EnableBIAS( void ) +{ + // For CAP9, SAM9RL, HS +#if !defined (BOARD_USB_NO_BIAS_COMMAND) + UDPHS_DisableBIAS(); + AT91C_BASE_PMC->PMC_UCKR |= AT91C_CKGR_BIASEN_ENABLED; +#endif +} + +//------------------------------------------------------------------------------ +/// Enable UDPHS clock +//------------------------------------------------------------------------------ +static inline void UDPHS_EnableUsbClock( void ) +{ +#if !defined (PMC_BY_HARD) + AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_UDPHS); + // Enable 480MHZ + AT91C_BASE_CKGR->CKGR_UCKR |= (AT91C_CKGR_PLLCOUNT & (3 << 20)) | AT91C_CKGR_UPLLEN; + // Wait until UTMI PLL is locked + while ((AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKU) == 0); +#endif +} + +//------------------------------------------------------------------------------ +/// Disable UDPHS clock +//------------------------------------------------------------------------------ +static inline void UDPHS_DisableUsbClock( void ) +{ +#if !defined (PMC_BY_HARD) + AT91C_BASE_PMC->PMC_PCDR = (1 << AT91C_ID_UDPHS); + // 480MHZ + AT91C_BASE_CKGR->CKGR_UCKR &= ~AT91C_CKGR_UPLLEN; +#endif +} + +//------------------------------------------------------------------------------ +/// Handles a completed transfer on the given endpoint, invoking the +/// configured callback if any. +/// \param bEndpoint Number of the endpoint for which the transfer has completed. +/// \param bStatus Status code returned by the transfer operation +//------------------------------------------------------------------------------ +static void UDPHS_EndOfTransfer( unsigned char bEndpoint, char bStatus ) +{ + Endpoint *pEndpoint = &(endpoints[bEndpoint]); + Transfer *pTransfer = &(pEndpoint->transfer); + + // Check that endpoint was sending or receiving data + if( (pEndpoint->state == UDP_ENDPOINT_RECEIVING) + || (pEndpoint->state == UDP_ENDPOINT_SENDING) ) { + + TRACE_DEBUG_WP("Eo"); + + // Endpoint returns in Idle state + pEndpoint->state = UDP_ENDPOINT_IDLE; + + // Invoke callback is present + if (pTransfer->fCallback != 0) { + + ((TransferCallback) pTransfer->fCallback) + (pTransfer->pArgument, + bStatus, + pTransfer->transferred, + pTransfer->remaining + pTransfer->buffered); + } + else { + TRACE_DEBUG_WP("No callBack\n\r"); + } + } +} + +//------------------------------------------------------------------------------ +/// Clears the correct RX flag in endpoint status register +/// \param bEndpoint Index of endpoint +//------------------------------------------------------------------------------ +static void UDPHS_ClearRxFlag( unsigned char bEndpoint ) +{ + AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCLRSTA = AT91C_UDPHS_RX_BK_RDY; +} + +//------------------------------------------------------------------------------ +/// Transfers a data payload from the current tranfer buffer to the endpoint +/// FIFO +/// \param bEndpoint Number of the endpoint which is sending data. +//------------------------------------------------------------------------------ +static void UDPHS_WritePayload( unsigned char bEndpoint ) +{ + Endpoint *pEndpoint = &(endpoints[bEndpoint]); + Transfer *pTransfer = &(pEndpoint->transfer); + char *pFifo; + signed int size; + unsigned int dCtr; + + pFifo = (char*)((unsigned int *)AT91C_BASE_UDPHS_EPTFIFO + (16384 * bEndpoint)); + + // Get the number of bytes to send + size = pEndpoint->size; + if (size > pTransfer->remaining) { + + size = pTransfer->remaining; + } + + // Update transfer descriptor information + pTransfer->buffered += size; + pTransfer->remaining -= size; + + // Write packet in the FIFO buffer + dCtr = 0; + while (size > 0) { + + pFifo[dCtr] = *(pTransfer->pData); + pTransfer->pData++; + size--; + dCtr++; + } +} + +//------------------------------------------------------------------------------ +/// Transfers a data payload from an endpoint FIFO to the current transfer buffer +/// \param bEndpoint Endpoint number. +/// \param wPacketSize Size of received data packet +//------------------------------------------------------------------------------ +static void UDPHS_ReadPayload( unsigned char bEndpoint, int wPacketSize ) +{ + Endpoint *pEndpoint = &(endpoints[bEndpoint]); + Transfer *pTransfer = &(pEndpoint->transfer); + char *pFifo; + unsigned char dBytes=0; + + pFifo = (char*)((unsigned int *)AT91C_BASE_UDPHS_EPTFIFO + (16384 * bEndpoint)); + + // Check that the requested size is not bigger than the remaining transfer + if (wPacketSize > pTransfer->remaining) { + + pTransfer->buffered += wPacketSize - pTransfer->remaining; + wPacketSize = pTransfer->remaining; + } + + // Update transfer descriptor information + pTransfer->remaining -= wPacketSize; + pTransfer->transferred += wPacketSize; + + // Retrieve packet + while (wPacketSize > 0) { + + *(pTransfer->pData) = pFifo[dBytes]; + pTransfer->pData++; + wPacketSize--; + dBytes++; + } +} + + +//------------------------------------------------------------------------------ +/// Received SETUP packet from endpoint 0 FIFO +/// \param pRequest Generic USB SETUP request sent over Control endpoints +//------------------------------------------------------------------------------ +static void UDPHS_ReadRequest( USBGenericRequest *pRequest ) +{ + unsigned int *pData = (unsigned int *)pRequest; + unsigned int fifo; + + fifo = (AT91C_BASE_UDPHS_EPTFIFO->UDPHS_READEPT0[0]); + *pData = fifo; + fifo = (AT91C_BASE_UDPHS_EPTFIFO->UDPHS_READEPT0[0]); + pData++; + *pData = fifo; + //TRACE_ERROR("SETUP: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n\r", pData[0],pData[1],pData[2],pData[3],pData[4],pData[5],pData[6],pData[7]); +} + +//------------------------------------------------------------------------------ +/// Reset all endpoint transfer descriptors +//------------------------------------------------------------------------------ +static void UDPHS_ResetEndpoints( void ) +{ + Endpoint *pEndpoint; + Transfer *pTransfer; + unsigned char bEndpoint; + + // Reset the transfer descriptor of every endpoint + for( bEndpoint = 0; bEndpoint < BOARD_USB_NUMENDPOINTS; bEndpoint++ ) { + + pEndpoint = &(endpoints[bEndpoint]); + pTransfer = &(pEndpoint->transfer); + + // Reset endpoint transfer descriptor + pTransfer->pData = 0; + pTransfer->transferred = -1; + pTransfer->buffered = -1; + pTransfer->remaining = -1; + pTransfer->fCallback = 0; + pTransfer->pArgument = 0; + + // Reset endpoint state + pEndpoint->bank = 0; + pEndpoint->state = UDP_ENDPOINT_DISABLED; + } +} + + +//------------------------------------------------------------------------------ +/// Disable all endpoints (except control endpoint 0), aborting current +/// transfers if necessary +//------------------------------------------------------------------------------ +static void UDPHS_DisableEndpoints( void ) +{ + unsigned char bEndpoint; + + // Disable each endpoint, terminating any pending transfer + // Control endpoint 0 is not disabled + for( bEndpoint = 1; bEndpoint < BOARD_USB_NUMENDPOINTS; bEndpoint++ ) { + + UDPHS_EndOfTransfer( bEndpoint, USBD_STATUS_ABORTED ); + endpoints[bEndpoint].state = UDP_ENDPOINT_DISABLED; + } +} + +//------------------------------------------------------------------------------ +/// Endpoint interrupt handler. +/// Handle IN/OUT transfers, received SETUP packets and STALLing +/// \param bEndpoint Index of endpoint +//------------------------------------------------------------------------------ +static void UDPHS_EndpointHandler( unsigned char bEndpoint ) +{ + Endpoint *pEndpoint = &(endpoints[bEndpoint]); + Transfer *pTransfer = &(pEndpoint->transfer); + unsigned int status = AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTSTA; + unsigned short wPacketSize; + USBGenericRequest request; + + TRACE_DEBUG_WP("E%d ", bEndpoint); + TRACE_DEBUG_WP("st:0x%X ", status); + + // Handle interrupts + // IN packet sent + if( (AT91C_UDPHS_TX_PK_RDY == (AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCTL & AT91C_UDPHS_TX_PK_RDY)) + && (0 == (status & AT91C_UDPHS_TX_PK_RDY )) ) { + + TRACE_DEBUG_WP("Wr "); + + // Check that endpoint was in Sending state + if( pEndpoint->state == UDP_ENDPOINT_SENDING ) { + + if (pTransfer->buffered > 0) { + pTransfer->transferred += pTransfer->buffered; + pTransfer->buffered = 0; + } + + if( ((pTransfer->buffered)==0) + &&((pTransfer->transferred)==0) + &&((pTransfer->remaining)==0) + &&(sendZLP == 0)) { + sendZLP = 1; + } + + // End of transfer ? + if( (pTransfer->remaining > 0) + ||(sendZLP == 1)) { + TRACE_DEBUG_WP("\n\r1pTransfer->buffered %d \n\r", pTransfer->buffered); + TRACE_DEBUG_WP("1pTransfer->transferred %d \n\r", pTransfer->transferred); + TRACE_DEBUG_WP("1pTransfer->remaining %d \n\r", pTransfer->remaining); + + // Transfer remaining data + TRACE_DEBUG_WP(" %d ", pEndpoint->size); + + // Send next packet + UDPHS_WritePayload(bEndpoint); + AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTSETSTA = AT91C_UDPHS_TX_PK_RDY; + sendZLP = 2; + } + else { + TRACE_DEBUG_WP("\n\r0pTransfer->buffered %d \n\r", pTransfer->buffered); + TRACE_DEBUG_WP("0pTransfer->transferred %d \n\r", pTransfer->transferred); + TRACE_DEBUG_WP("0pTransfer->remaining %d \n\r", pTransfer->remaining); + + TRACE_DEBUG_WP(" %d ", pTransfer->transferred); + + // Disable interrupt if this is not a control endpoint + if( AT91C_UDPHS_EPT_TYPE_CTL_EPT != (AT91C_UDPHS_EPT_TYPE&(AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCFG)) ) { + + AT91C_BASE_UDPHS->UDPHS_IEN &= ~(1<UDPHS_EPT[bEndpoint].UDPHS_EPTCTLDIS = AT91C_UDPHS_TX_PK_RDY; + + UDPHS_EndOfTransfer(bEndpoint, USBD_STATUS_SUCCESS); + sendZLP = 0; + } + } + else { + + TRACE_ERROR("Error Wr"); + } + } + + // OUT packet received + if( AT91C_UDPHS_RX_BK_RDY == (status & AT91C_UDPHS_RX_BK_RDY) ) { + + TRACE_DEBUG_WP("Rd "); + + // Check that the endpoint is in Receiving state + if (pEndpoint->state != UDP_ENDPOINT_RECEIVING) { + + // Check if an ACK has been received on a Control endpoint + if( (0 == (AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCFG & AT91C_UDPHS_EPT_TYPE)) + && (0 == (status & AT91C_UDPHS_BYTE_COUNT)) ) { + + // Control endpoint, 0 bytes received + // Acknowledge the data and finish the current transfer + TRACE_DEBUG_WP("Ack "); + UDPHS_ClearRxFlag(bEndpoint); + UDPHS_EndOfTransfer(bEndpoint, USBD_STATUS_SUCCESS); + } + // Check if the data has been STALLed + else if( AT91C_UDPHS_FRCESTALL == (status & AT91C_UDPHS_FRCESTALL)) { + + // Discard STALLed data + TRACE_DEBUG_WP("Discard "); + UDPHS_ClearRxFlag(bEndpoint); + } + // NAK the data + else { + + TRACE_DEBUG_WP("Nak "); + AT91C_BASE_UDPHS->UDPHS_IEN &= ~(1<>20); + + TRACE_DEBUG_WP("%d ", wPacketSize); + UDPHS_ReadPayload(bEndpoint, wPacketSize); + UDPHS_ClearRxFlag(bEndpoint); + + // Check if the transfer is finished + if ((pTransfer->remaining == 0) || (wPacketSize < pEndpoint->size)) { + + AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCTLDIS = AT91C_UDPHS_RX_BK_RDY; + + // Disable interrupt if this is not a control endpoint + if( AT91C_UDPHS_EPT_TYPE_CTL_EPT != (AT91C_UDPHS_EPT_TYPE & (AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCFG)) ) { + + AT91C_BASE_UDPHS->UDPHS_IEN &= ~(1<UDPHS_EPT[bEndpoint].UDPHS_EPTCLRSTA = AT91C_UDPHS_STALL_SNT; + + // If the endpoint is not halted, clear the STALL condition + if (pEndpoint->state != UDP_ENDPOINT_HALTED) { + + TRACE_WARNING( "_ " ); + AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCLRSTA = AT91C_UDPHS_FRCESTALL; + } + } + + // SETUP packet received + if( AT91C_UDPHS_RX_SETUP == (status & AT91C_UDPHS_RX_SETUP) ) { + + TRACE_DEBUG_WP("Stp "); + + // If a transfer was pending, complete it + // Handles the case where during the status phase of a control write + // transfer, the host receives the device ZLP and ack it, but the ack + // is not received by the device + if ((pEndpoint->state == UDP_ENDPOINT_RECEIVING) + || (pEndpoint->state == UDP_ENDPOINT_SENDING)) { + + UDPHS_EndOfTransfer(bEndpoint, USBD_STATUS_SUCCESS); + } + // Copy the setup packet + UDPHS_ReadRequest(&request); + + // Acknowledge setup packet + AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCLRSTA = AT91C_UDPHS_RX_SETUP; + + // Forward the request to the upper layer + USBDCallbacks_RequestReceived(&request); + } + +} + +//------------------------------------------------------------------------------ +// Interrupt service routine +//------------------------------------------------------------------------------ +#ifdef DMA +//---------------------------------------------------------------------------- +/// Endpoint DMA interrupt handler. +/// This function (ISR) handles dma interrupts +/// \param bEndpoint Index of endpoint +//---------------------------------------------------------------------------- +static void UDPHS_DmaHandler( unsigned char bEndpoint ) +{ + Endpoint *pEndpoint = &(endpoints[bEndpoint]); + Transfer *pTransfer = &(pEndpoint->transfer); + int justTransferred; + unsigned int status; + unsigned char result = USBD_STATUS_SUCCESS; + + status = AT91C_BASE_UDPHS->UDPHS_DMA[bEndpoint].UDPHS_DMASTATUS; + TRACE_DEBUG_WP("Dma Ept%d ", bEndpoint); + + // Disable DMA interrupt to avoid receiving 2 interrupts (B_EN and TR_EN) + AT91C_BASE_UDPHS->UDPHS_DMA[bEndpoint].UDPHS_DMACONTROL &= + ~(AT91C_UDPHS_END_TR_EN | AT91C_UDPHS_END_B_EN); + + AT91C_BASE_UDPHS->UDPHS_IEN &= ~(1 << SHIFT_DMA << bEndpoint); + + if( AT91C_UDPHS_END_BF_ST == (status & AT91C_UDPHS_END_BF_ST) ) { + + TRACE_DEBUG_WP("EndBuffer "); + + // BUFF_COUNT holds the number of untransmitted bytes. + // BUFF_COUNT is equal to zero in case of good transfer + justTransferred = pTransfer->buffered + - ((status & AT91C_UDPHS_BUFF_COUNT) >> 16); + pTransfer->transferred += justTransferred; + + pTransfer->buffered = ((status & AT91C_UDPHS_BUFF_COUNT) >> 16); + + pTransfer->remaining -= justTransferred; + + TRACE_DEBUG_WP("\n\r1pTransfer->buffered %d \n\r", pTransfer->buffered); + TRACE_DEBUG_WP("1pTransfer->transferred %d \n\r", pTransfer->transferred); + TRACE_DEBUG_WP("1pTransfer->remaining %d \n\r", pTransfer->remaining); + + if( (pTransfer->remaining + pTransfer->buffered) > 0 ) { + + // Prepare an other transfer + if( pTransfer->remaining > DMA_MAX_FIFO_SIZE ) { + + pTransfer->buffered = DMA_MAX_FIFO_SIZE; + } + else { + pTransfer->buffered = pTransfer->remaining; + } + + AT91C_BASE_UDPHS->UDPHS_DMA[bEndpoint].UDPHS_DMAADDRESS = + (unsigned int)((pTransfer->pData) + (pTransfer->transferred)); + + // Clear unwanted interrupts + AT91C_BASE_UDPHS->UDPHS_DMA[bEndpoint].UDPHS_DMASTATUS; + + // Enable DMA endpoint interrupt + AT91C_BASE_UDPHS->UDPHS_IEN |= (1 << SHIFT_DMA << bEndpoint); + // DMA config for receive the good size of buffer, or an error buffer + + AT91C_BASE_UDPHS->UDPHS_DMA[bEndpoint].UDPHS_DMACONTROL = 0; // raz + AT91C_BASE_UDPHS->UDPHS_DMA[bEndpoint].UDPHS_DMACONTROL = + ( ((pTransfer->buffered << 16) & AT91C_UDPHS_BUFF_COUNT) + | AT91C_UDPHS_END_TR_EN + | AT91C_UDPHS_END_TR_IT + | AT91C_UDPHS_END_B_EN + | AT91C_UDPHS_END_BUFFIT + | AT91C_UDPHS_CHANN_ENB ); + } + } + else if( AT91C_UDPHS_END_TR_ST == (status & AT91C_UDPHS_END_TR_ST) ) { + + TRACE_DEBUG_WP("EndTransf "); + + pTransfer->transferred = pTransfer->buffered + - ((status & AT91C_UDPHS_BUFF_COUNT) >> 16); + pTransfer->remaining = 0; + TRACE_DEBUG_WP("\n\r0pTransfer->buffered %d \n\r", pTransfer->buffered); + TRACE_DEBUG_WP("0pTransfer->transferred %d \n\r", pTransfer->transferred); + TRACE_DEBUG_WP("0pTransfer->remaining %d \n\r", pTransfer->remaining); + } + else { + + TRACE_ERROR("UDPHS_DmaHandler: Error (0x%08X)\n\r", status); + result = USBD_STATUS_ABORTED; + } + + // Invoke callback + if( pTransfer->remaining == 0 ) { + + TRACE_DEBUG_WP("EOT "); + UDPHS_EndOfTransfer(bEndpoint, result); + } +} +#endif + + +//------------------------------------------------------------------------------ +// Exported functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// USB interrupt handler +/// Manages device resume, suspend, end of bus reset. +/// Forwards endpoint interrupts to the appropriate handler. +//------------------------------------------------------------------------------ +void USBD_InterruptHandler(void) +{ + unsigned int status; + unsigned char numIT; + + if (deviceState >= USBD_STATE_POWERED) { + + LED_Set(USBD_LEDUSB); + } + + // Get interrupts status + status = AT91C_BASE_UDPHS->UDPHS_INTSTA & AT91C_BASE_UDPHS->UDPHS_IEN; + + // Handle all UDPHS interrupts + TRACE_DEBUG_WP("H"); + while (status != 0) { + + // Start Of Frame (SOF) + if ((status & AT91C_UDPHS_IEN_SOF) != 0) { + + TRACE_DEBUG_WP("SOF "); + + // Invoke the SOF callback + //USB_StartOfFrameCallback(pUsb); + + // Acknowledge interrupt + AT91C_BASE_UDPHS->UDPHS_CLRINT = AT91C_UDPHS_IEN_SOF; + status &= ~AT91C_UDPHS_IEN_SOF; + } + // Suspend + // This interrupt is always treated last (hence the '==') + else if (status == AT91C_UDPHS_DET_SUSPD) { + + TRACE_DEBUG_WP("S"); + + // The device enters the Suspended state + // MCK + UDPCK must be off + // Pull-Up must be connected + // Transceiver must be disabled + + LED_Clear(USBD_LEDUSB); + + UDPHS_DisableBIAS(); + + // Enable wakeup + AT91C_BASE_UDPHS->UDPHS_IEN |= AT91C_UDPHS_WAKE_UP | AT91C_UDPHS_ENDOFRSM; + AT91C_BASE_UDPHS->UDPHS_IEN &= ~AT91C_UDPHS_DET_SUSPD; + + // Acknowledge interrupt + AT91C_BASE_UDPHS->UDPHS_CLRINT = AT91C_UDPHS_DET_SUSPD | AT91C_UDPHS_WAKE_UP; + previousDeviceState = deviceState; + deviceState = USBD_STATE_SUSPENDED; + UDPHS_DisableUsbClock(); + + // Invoke the Suspend callback + USBDCallbacks_Suspended(); + } + // Resume + else if( ((status & AT91C_UDPHS_WAKE_UP) != 0) // line activity + || ((status & AT91C_UDPHS_ENDOFRSM) != 0)) { // pc wakeup + +//JCB +#ifdef NOT_DEFINED +#if !defined(PIN_USB_VBUS) + // Configure PIO + PIO_Configure(&pinVbus, 1); + + // Check current level on VBus + if (PIO_Get(&pinVbus) == 1) // Protection +#endif +#endif + { + // Invoke the Resume callback + USBDCallbacks_Resumed(); + + TRACE_DEBUG_WP("R"); + + UDPHS_EnableUsbClock(); + UDPHS_EnableBIAS(); + + // The device enters Configured state + // MCK + UDPCK must be on + // Pull-Up must be connected + // Transceiver must be enabled + + deviceState = previousDeviceState; + + AT91C_BASE_UDPHS->UDPHS_CLRINT = AT91C_UDPHS_WAKE_UP | AT91C_UDPHS_ENDOFRSM | AT91C_UDPHS_DET_SUSPD; + + AT91C_BASE_UDPHS->UDPHS_IEN |= AT91C_UDPHS_ENDOFRSM | AT91C_UDPHS_DET_SUSPD; + AT91C_BASE_UDPHS->UDPHS_CLRINT = AT91C_UDPHS_WAKE_UP | AT91C_UDPHS_ENDOFRSM; + AT91C_BASE_UDPHS->UDPHS_IEN &= ~AT91C_UDPHS_WAKE_UP; + } +// jcb !!! +#ifdef NOT_DEFINED +#if !defined(PIN_USB_VBUS) + else { + + // No VBUS + // Disconnect the pull-up + USBD_Disconnect(); + AT91C_BASE_UDPHS->UDPHS_CLRINT = AT91C_UDPHS_WAKE_UP; + } +#endif +#endif + } + // End of bus reset + else if ((status & AT91C_UDPHS_ENDRESET) == AT91C_UDPHS_ENDRESET) { + +// TRACE_DEBUG_WP("EoB "); + + // The device enters the Default state + deviceState = USBD_STATE_DEFAULT; + // MCK + UDPCK are already enabled + // Pull-Up is already connected + // Transceiver must be enabled + // Endpoint 0 must be enabled + + UDPHS_ResetEndpoints(); + UDPHS_DisableEndpoints(); + USBD_ConfigureEndpoint(0); + + // Flush and enable the Suspend interrupt + AT91C_BASE_UDPHS->UDPHS_CLRINT = AT91C_UDPHS_WAKE_UP | AT91C_UDPHS_DET_SUSPD; + + //// Enable the Start Of Frame (SOF) interrupt if needed + //if (pCallbacks->startOfFrame != 0) + //{ + // AT91C_BASE_UDPHS->UDPHS_IEN |= AT91C_UDPHS_IEN_SOF; + //} + + // Invoke the Reset callback + USBDCallbacks_Reset(); + + // Acknowledge end of bus reset interrupt + AT91C_BASE_UDPHS->UDPHS_CLRINT = AT91C_UDPHS_ENDRESET; + + AT91C_BASE_UDPHS->UDPHS_IEN |= AT91C_UDPHS_DET_SUSPD; + } + // Handle upstream resume interrupt + else if (status & AT91C_UDPHS_UPSTR_RES) { + + TRACE_DEBUG_WP("ExtRes "); + + // - Acknowledge the IT + AT91C_BASE_UDPHS->UDPHS_CLRINT = AT91C_UDPHS_UPSTR_RES; + } + // Endpoint interrupts + else { +#ifndef DMA + // Handle endpoint interrupts + for (numIT = 0; numIT < NUM_IT_MAX; numIT++) { + + if ((status & (1 << SHIFT_INTERUPT << numIT)) != 0) { + + UDPHS_EndpointHandler(numIT); + } + } +#else + // Handle endpoint control interrupt + if ((status & (1 << SHIFT_INTERUPT << 0)) != 0) { + + UDPHS_EndpointHandler( 0 ); + } + else { + + numIT = 1; + while((status&(0x7E<UDPHS_INTSTA & AT91C_BASE_UDPHS->UDPHS_IEN; + + TRACE_DEBUG_WP("\n\r"); + if (status != 0) { + + TRACE_DEBUG_WP(" - "); + } + } + + if (deviceState >= USBD_STATE_POWERED) { + + LED_Clear(USBD_LEDUSB); + } +} + +//------------------------------------------------------------------------------ +/// Configure an endpoint with the provided endpoint descriptor +/// \param pDdescriptor Pointer to the endpoint descriptor +//------------------------------------------------------------------------------ +void USBD_ConfigureEndpoint(const USBEndpointDescriptor *pDescriptor) +{ + Endpoint *pEndpoint; + unsigned char bEndpoint; + unsigned char bType; + unsigned char bEndpointDir; + unsigned char bSizeEpt = 0; + + // NULL descriptor -> Control endpoint 0 + if (pDescriptor == 0) { + + bEndpoint = 0; + pEndpoint = &(endpoints[bEndpoint]); + bType = USBEndpointDescriptor_CONTROL; + bEndpointDir = 0; + pEndpoint->size = BOARD_USB_ENDPOINTS_MAXPACKETSIZE(0); + pEndpoint->bank = BOARD_USB_ENDPOINTS_BANKS(0); + } + else { + + // The endpoint number + bEndpoint = USBEndpointDescriptor_GetNumber(pDescriptor); + pEndpoint = &(endpoints[bEndpoint]); + // Transfer type: Control, Isochronous, Bulk, Interrupt + bType = USBEndpointDescriptor_GetType(pDescriptor); + // Direction, ignored for control endpoints + bEndpointDir = USBEndpointDescriptor_GetDirection(pDescriptor); + pEndpoint->size = USBEndpointDescriptor_GetMaxPacketSize(pDescriptor); + pEndpoint->bank = BOARD_USB_ENDPOINTS_BANKS(bEndpoint); + } + + // Abort the current transfer is the endpoint was configured and in + // Write or Read state + if( (pEndpoint->state == UDP_ENDPOINT_RECEIVING) + || (pEndpoint->state == UDP_ENDPOINT_SENDING) ) { + + UDPHS_EndOfTransfer(bEndpoint, USBD_STATUS_RESET); + } + pEndpoint->state = UDP_ENDPOINT_IDLE; + + // Disable endpoint + AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCTLDIS = AT91C_UDPHS_SHRT_PCKT + | AT91C_UDPHS_BUSY_BANK + | AT91C_UDPHS_NAK_OUT + | AT91C_UDPHS_NAK_IN + | AT91C_UDPHS_STALL_SNT + | AT91C_UDPHS_RX_SETUP + | AT91C_UDPHS_TX_PK_RDY + | AT91C_UDPHS_TX_COMPLT + | AT91C_UDPHS_RX_BK_RDY + | AT91C_UDPHS_ERR_OVFLW + | AT91C_UDPHS_MDATA_RX + | AT91C_UDPHS_DATAX_RX + | AT91C_UDPHS_NYET_DIS + | AT91C_UDPHS_INTDIS_DMA + | AT91C_UDPHS_AUTO_VALID + | AT91C_UDPHS_EPT_DISABL; + + // Reset Endpoint Fifos + AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCLRSTA = AT91C_UDPHS_TOGGLESQ | AT91C_UDPHS_FRCESTALL; + AT91C_BASE_UDPHS->UDPHS_EPTRST = 1<size <= 8 ) { + bSizeEpt = 0; + } + else if ( pEndpoint->size <= 16 ) { + bSizeEpt = 1; + } + else if ( pEndpoint->size <= 32 ) { + bSizeEpt = 2; + } + else if ( pEndpoint->size <= 64 ) { + bSizeEpt = 3; + } + else if ( pEndpoint->size <= 128 ) { + bSizeEpt = 4; + } + else if ( pEndpoint->size <= 256 ) { + bSizeEpt = 5; + } + else if ( pEndpoint->size <= 512 ) { + bSizeEpt = 6; + } + else if ( pEndpoint->size <= 1024 ) { + bSizeEpt = 7; + } //else { + // sizeEpt = 0; // control endpoint + //} + + // Configure endpoint + if (bType == USBEndpointDescriptor_CONTROL) { + + // Enable endpoint IT for control endpoint + AT91C_BASE_UDPHS->UDPHS_IEN |= (1<UDPHS_EPT[bEndpoint].UDPHS_EPTCFG = bSizeEpt + | (bEndpointDir << 3) + | (bType << 4) + | ((pEndpoint->bank) << 6); + + while( (signed int)AT91C_UDPHS_EPT_MAPD != (signed int)((AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCFG) & AT91C_UDPHS_EPT_MAPD) ) { + + // resolved by clearing the reset IT in good place + TRACE_ERROR("PB bEndpoint: 0x%X\n\r", bEndpoint); + TRACE_ERROR("PB bSizeEpt: 0x%X\n\r", bSizeEpt); + TRACE_ERROR("PB bEndpointDir: 0x%X\n\r", bEndpointDir); + TRACE_ERROR("PB bType: 0x%X\n\r", bType); + TRACE_ERROR("PB pEndpoint->bank: 0x%X\n\r", pEndpoint->bank); + TRACE_ERROR("PB UDPHS_EPTCFG: 0x%X\n\r", AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCFG); + for(;;); + } + + if (bType == USBEndpointDescriptor_CONTROL) { + + AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCTLENB = AT91C_UDPHS_RX_BK_RDY + | AT91C_UDPHS_RX_SETUP + | AT91C_UDPHS_EPT_ENABL; + } + else { +#ifndef DMA + AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCTLENB = AT91C_UDPHS_EPT_ENABL; +#else + AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCTLENB = AT91C_UDPHS_AUTO_VALID + | AT91C_UDPHS_EPT_ENABL; +#endif + } + +} + +//------------------------------------------------------------------------------ +/// Sends data through an USB endpoint (IN) +/// Sets up the transfer descriptor, write one or two data payloads +/// (depending on the number of FIFO banks for the endpoint) and then +/// starts the actual transfer. The operation is complete when all +/// the data has been sent. +/// \param bEndpoint Index of endpoint +/// \param *pData Data to be written +/// \param dLength Data length to be send +/// \param fCallback Callback to be call after the success command +/// \param *pArgument Callback argument +/// \return USBD_STATUS_LOCKED or USBD_STATUS_SUCCESS +//------------------------------------------------------------------------------ +char USBD_Write( unsigned char bEndpoint, + const void *pData, + unsigned int dLength, + TransferCallback fCallback, + void *pArgument ) +{ + Endpoint *pEndpoint = &(endpoints[bEndpoint]); + Transfer *pTransfer = &(pEndpoint->transfer); + + // Return if the endpoint is not in IDLE state + if (pEndpoint->state != UDP_ENDPOINT_IDLE) { + + return USBD_STATUS_LOCKED; + } + + TRACE_DEBUG_WP("Write%d(%d) ", bEndpoint, dLength); + + // Setup the transfer descriptor + pTransfer->pData = (void *) pData; + pTransfer->remaining = dLength; + pTransfer->buffered = 0; + pTransfer->transferred = 0; + pTransfer->fCallback = fCallback; + pTransfer->pArgument = pArgument; + + // Send one packet + pEndpoint->state = UDP_ENDPOINT_SENDING; + +#ifdef DMA + // Test if endpoint type control + if(AT91C_UDPHS_EPT_TYPE_CTL_EPT == (AT91C_UDPHS_EPT_TYPE&(AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCFG))) { +#endif + // Enable endpoint IT + AT91C_BASE_UDPHS->UDPHS_IEN |= (1 << SHIFT_INTERUPT << bEndpoint); + AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCTLENB = AT91C_UDPHS_TX_PK_RDY; + +#ifdef DMA + } + else { + + if( pTransfer->remaining == 0 ) { + // DMA not handle ZLP + AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTSETSTA = AT91C_UDPHS_TX_PK_RDY; + // Enable endpoint IT + AT91C_BASE_UDPHS->UDPHS_IEN |= (1 << SHIFT_INTERUPT << bEndpoint); + AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCTLENB = AT91C_UDPHS_TX_PK_RDY; + } + else { + // Others endpoints (not control) + if( pTransfer->remaining > DMA_MAX_FIFO_SIZE ) { + + // Transfer the max + pTransfer->buffered = DMA_MAX_FIFO_SIZE; + } + else { + // Transfer the good size + pTransfer->buffered = pTransfer->remaining; + } + + TRACE_DEBUG_WP("\n\r_WR:%d ", pTransfer->remaining ); + TRACE_DEBUG_WP("B:%d ", pTransfer->buffered ); + TRACE_DEBUG_WP("T:%d ", pTransfer->transferred ); + + AT91C_BASE_UDPHS->UDPHS_DMA[bEndpoint].UDPHS_DMAADDRESS = (unsigned int)(pTransfer->pData); + + // Clear unwanted interrupts + AT91C_BASE_UDPHS->UDPHS_DMA[bEndpoint].UDPHS_DMASTATUS; + // Enable DMA endpoint interrupt + AT91C_BASE_UDPHS->UDPHS_IEN |= (1 << SHIFT_DMA << bEndpoint); + // DMA config + AT91C_BASE_UDPHS->UDPHS_DMA[bEndpoint].UDPHS_DMACONTROL = 0; // raz + AT91C_BASE_UDPHS->UDPHS_DMA[bEndpoint].UDPHS_DMACONTROL = + ( ((pTransfer->buffered << 16) & AT91C_UDPHS_BUFF_COUNT) + | AT91C_UDPHS_END_B_EN + | AT91C_UDPHS_END_BUFFIT + | AT91C_UDPHS_CHANN_ENB ); + } + } +#endif + + return USBD_STATUS_SUCCESS; +} + +//------------------------------------------------------------------------------ +/// Reads incoming data on an USB endpoint (OUT) +/// \param bEndpoint Index of endpoint +/// \param *pData Data to be readen +/// \param dLength Data length to be receive +/// \param fCallback Callback to be call after the success command +/// \param *pArgument Callback argument +/// \return USBD_STATUS_LOCKED or USBD_STATUS_SUCCESS +//------------------------------------------------------------------------------ +char USBD_Read( unsigned char bEndpoint, + void *pData, + unsigned int dLength, + TransferCallback fCallback, + void *pArgument ) +{ + Endpoint *pEndpoint = &(endpoints[bEndpoint]); + Transfer *pTransfer = &(pEndpoint->transfer); + + // Return if the endpoint is not in IDLE state + if (pEndpoint->state != UDP_ENDPOINT_IDLE) { + + return USBD_STATUS_LOCKED; + } + + TRACE_DEBUG_WP("Read%d(%d) ", bEndpoint, dLength); + + // Endpoint enters Receiving state + pEndpoint->state = UDP_ENDPOINT_RECEIVING; + + // Set the transfer descriptor + pTransfer->pData = pData; + pTransfer->remaining = dLength; + pTransfer->buffered = 0; + pTransfer->transferred = 0; + pTransfer->fCallback = fCallback; + pTransfer->pArgument = pArgument; + +#ifdef DMA + // Test if endpoint type control + if(AT91C_UDPHS_EPT_TYPE_CTL_EPT == (AT91C_UDPHS_EPT_TYPE&(AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCFG))) { +#endif + // Control endpoint + // Enable endpoint IT + AT91C_BASE_UDPHS->UDPHS_IEN |= (1 << SHIFT_INTERUPT << bEndpoint); + AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCTLENB = AT91C_UDPHS_RX_BK_RDY; +#ifdef DMA + } + else { + + TRACE_DEBUG_WP("Read%d(%d) ", bEndpoint, dLength); + + // Others endpoints (not control) + if( pTransfer->remaining > DMA_MAX_FIFO_SIZE ) { + + // Transfer the max + pTransfer->buffered = DMA_MAX_FIFO_SIZE; + } + else { + // Transfer the good size + pTransfer->buffered = pTransfer->remaining; + } + + AT91C_BASE_UDPHS->UDPHS_DMA[bEndpoint].UDPHS_DMAADDRESS = (unsigned int)(pTransfer->pData); + + // Clear unwanted interrupts + AT91C_BASE_UDPHS->UDPHS_DMA[bEndpoint].UDPHS_DMASTATUS; + + // Enable DMA endpoint interrupt + AT91C_BASE_UDPHS->UDPHS_IEN |= (1 << SHIFT_DMA << bEndpoint); + + TRACE_DEBUG_WP("\n\r_RR:%d ", pTransfer->remaining ); + TRACE_DEBUG_WP("B:%d ", pTransfer->buffered ); + TRACE_DEBUG_WP("T:%d ", pTransfer->transferred ); + + // DMA config + AT91C_BASE_UDPHS->UDPHS_DMA[bEndpoint].UDPHS_DMACONTROL = 0; // raz + AT91C_BASE_UDPHS->UDPHS_DMA[bEndpoint].UDPHS_DMACONTROL = + ( ((pTransfer->buffered << 16) & AT91C_UDPHS_BUFF_COUNT) + | AT91C_UDPHS_END_TR_EN + | AT91C_UDPHS_END_TR_IT + | AT91C_UDPHS_END_B_EN + | AT91C_UDPHS_END_BUFFIT + | AT91C_UDPHS_CHANN_ENB ); + } +#endif + + return USBD_STATUS_SUCCESS; +} + +//------------------------------------------------------------------------------ +/// Put endpoint into Halt state +/// \param bEndpoint Index of endpoint +//------------------------------------------------------------------------------ +void USBD_Halt( unsigned char bEndpoint ) +{ + Endpoint *pEndpoint = &(endpoints[bEndpoint]); + + // Check that endpoint is enabled and not already in Halt state + if( (pEndpoint->state != UDP_ENDPOINT_DISABLED) + && (pEndpoint->state != UDP_ENDPOINT_HALTED) ) { + + TRACE_DEBUG_WP("Halt%d ", bEndpoint); + + // Abort the current transfer if necessary + UDPHS_EndOfTransfer(bEndpoint, USBD_STATUS_ABORTED); + + // Put endpoint into Halt state + AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTSETSTA = AT91C_UDPHS_FRCESTALL; + pEndpoint->state = UDP_ENDPOINT_HALTED; + +#ifdef DMA + // Test if endpoint type control + if(AT91C_UDPHS_EPT_TYPE_CTL_EPT == (AT91C_UDPHS_EPT_TYPE&(AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCFG))) { +#endif + // Enable the endpoint interrupt + AT91C_BASE_UDPHS->UDPHS_IEN |= (1<UDPHS_IEN |= (1<state != UDP_ENDPOINT_DISABLED) { + + TRACE_DEBUG_WP("Unhalt%d ", bEndpoint); + + // Return endpoint to Idle state + pEndpoint->state = UDP_ENDPOINT_IDLE; + + // Clear FORCESTALL flag + AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTCLRSTA = AT91C_UDPHS_TOGGLESQ | AT91C_UDPHS_FRCESTALL; + + // Reset Endpoint Fifos + AT91C_BASE_UDPHS->UDPHS_EPTRST = (1<state == UDP_ENDPOINT_HALTED) { + status = 1; + } + return( status ); +} + +//------------------------------------------------------------------------------ +/// IS High Speed device working in High Speed ? +/// \return 1 if the device is in High Speed; otherwise 0 (Full Speed) +//------------------------------------------------------------------------------ +unsigned char USBD_IsHighSpeed( void ) +{ + unsigned char status = 0; + + if( AT91C_UDPHS_SPEED == (AT91C_BASE_UDPHS->UDPHS_INTSTA & AT91C_UDPHS_SPEED) ) + { + // High Speed + TRACE_DEBUG_WP("High Speed\n\r"); + status = 1; + } + else { + TRACE_DEBUG_WP("Full Speed\n\r"); + } + return( status ); +} + + +//------------------------------------------------------------------------------ +/// Causes the endpoint to acknowledge the next received packet with a STALL +/// handshake. +/// Further packets are then handled normally. +/// \param bEndpoint Index of endpoint +/// \return Operation result code: USBD_STATUS_LOCKED or USBD_STATUS_SUCCESS +//------------------------------------------------------------------------------ +unsigned char USBD_Stall( unsigned char bEndpoint ) +{ + Endpoint *pEndpoint = &(endpoints[bEndpoint]); + + // Check that endpoint is in Idle state + if (pEndpoint->state != UDP_ENDPOINT_IDLE) { + + TRACE_WARNING("UDP_Stall: Endpoint%d locked\n\r", bEndpoint); + return USBD_STATUS_LOCKED; + } + + TRACE_DEBUG_WP("Stall%d ", bEndpoint); + + AT91C_BASE_UDPHS->UDPHS_EPT[bEndpoint].UDPHS_EPTSETSTA = AT91C_UDPHS_FRCESTALL; + + return USBD_STATUS_SUCCESS; +} + +//------------------------------------------------------------------------------ +/// Activates a remote wakeup procedure +//------------------------------------------------------------------------------ +void USBD_RemoteWakeUp(void) +{ + TRACE_DEBUG_WP("Remote WakeUp\n\r"); + + // Device is currently suspended + if (deviceState == USBD_STATE_SUSPENDED) { + + TRACE_DEBUG_WP("RW\n\r"); + UDPHS_EnableUsbClock(); + + // Activates a remote wakeup + AT91C_BASE_UDPHS->UDPHS_CTRL |= AT91C_UDPHS_REWAKEUP; + + while ((AT91C_BASE_UDPHS->UDPHS_CTRL&AT91C_UDPHS_REWAKEUP) == AT91C_UDPHS_REWAKEUP) { + + TRACE_DEBUG_WP("W"); + } + UDPHS_EnableBIAS(); + } + // Device is NOT suspended + else { + + TRACE_WARNING("USBD_RemoteWakeUp: Device is not suspended\n\r"); + } +} + +//------------------------------------------------------------------------------ +/// Sets the device address +/// \param address Adress to be set +//------------------------------------------------------------------------------ +void USBD_SetAddress( unsigned char address ) +{ + TRACE_DEBUG_WP("SetAddr(%d) ", address); + + // Set address + AT91C_BASE_UDPHS->UDPHS_CTRL &= ~AT91C_UDPHS_DEV_ADDR; // RAZ Address + AT91C_BASE_UDPHS->UDPHS_CTRL |= address | AT91C_UDPHS_FADDR_EN; + + // If the address is 0, the device returns to the Default state + if (address == 0) { + deviceState = USBD_STATE_DEFAULT; + } + // If the address is non-zero, the device enters the Address state + else { + deviceState = USBD_STATE_ADDRESS; + } +} + +//------------------------------------------------------------------------------ +/// Changes the device state from Address to Configured, or from Configured +/// to Address. +/// This method directly access the last received SETUP packet to decide on +/// what to do. +/// \param cfgnum configuration number +//------------------------------------------------------------------------------ +void USBD_SetConfiguration( unsigned char cfgnum ) +{ + TRACE_DEBUG_WP("SetCfg(%d) ", cfgnum); + + // Check the request + if( cfgnum != 0 ) { + + // Enter Configured state + deviceState = USBD_STATE_CONFIGURED; + } + // If the configuration number is zero, the device goes back to the Address + // state + else { + + // Go back to Address state + deviceState = USBD_STATE_ADDRESS; + + // Abort all transfers + UDPHS_DisableEndpoints(); + } +} + +//------------------------------------------------------------------------------ +/// Enables the pull-up on the D+ line to connect the device to the USB. +//------------------------------------------------------------------------------ +void USBD_Connect( void ) +{ + TRACE_DEBUG_WP("Conn "); +#if defined(BOARD_USB_PULLUP_INTERNAL) + AT91C_BASE_UDPHS->UDPHS_CTRL &= ~AT91C_UDPHS_DETACH; // Pull Up on DP + AT91C_BASE_UDPHS->UDPHS_CTRL |= AT91C_UDPHS_PULLD_DIS; // Disable Pull Down + +#elif defined(BOARD_USB_PULLUP_INTERNAL_BY_MATRIX) + TRACE_DEBUG_WP("PUON 1\n\r"); + AT91C_BASE_MATRIX->MATRIX_USBPCR |= AT91C_MATRIX_USBPCR_PUON; + +#elif defined(BOARD_USB_PULLUP_EXTERNAL) + +#ifdef PIN_USB_PULLUP + const Pin pinPullUp = PIN_USB_PULLUP; + if( pinPullUp.attribute == PIO_OUTPUT_0 ) { + + PIO_Set(&pinPullUp); + } + else { + + PIO_Clear(&pinPullUp); + } +#else + #error unsupported now +#endif + +#elif !defined(BOARD_USB_PULLUP_ALWAYSON) + #error Unsupported pull-up type. + +#endif +} + +//------------------------------------------------------------------------------ +/// Disables the pull-up on the D+ line to disconnect the device from the bus. +//------------------------------------------------------------------------------ +void USBD_Disconnect( void ) +{ + TRACE_DEBUG_WP("Disc "); + +#if defined(BOARD_USB_PULLUP_INTERNAL) + AT91C_BASE_UDPHS->UDPHS_CTRL |= AT91C_UDPHS_DETACH; // detach + AT91C_BASE_UDPHS->UDPHS_CTRL &= ~AT91C_UDPHS_PULLD_DIS; // Enable Pull Down + +#elif defined(BOARD_USB_PULLUP_INTERNAL_BY_MATRIX) + AT91C_BASE_MATRIX->MATRIX_USBPCR &= ~AT91C_MATRIX_USBPCR_PUON; + +#elif defined(BOARD_USB_PULLUP_EXTERNAL) + +#ifdef PIN_USB_PULLUP + const Pin pinPullUp = PIN_USB_PULLUP; + if (pinPullUp.attribute == PIO_OUTPUT_0) { + + PIO_Clear(&pinPullUp); + } + else { + + PIO_Set(&pinPullUp); + } +#else + #error unsupported now +#endif + +#elif !defined(BOARD_USB_PULLUP_ALWAYSON) + #error Unsupported pull-up type. + +#endif + + // Device returns to the Powered state + if (deviceState > USBD_STATE_POWERED) { + + deviceState = USBD_STATE_POWERED; + } +} + +//------------------------------------------------------------------------------ +/// Certification test for High Speed device. +/// \param bIndex Test to be done +//------------------------------------------------------------------------------ +void USBD_Test( unsigned char bIndex ) +{ + char *pFifo; + unsigned char i; + + AT91C_BASE_UDPHS->UDPHS_IEN &= ~AT91C_UDPHS_DET_SUSPD; // remove suspend for TEST + AT91C_BASE_UDPHS->UDPHS_TST |= AT91C_UDPHS_SPEED_CFG_HS; // force High Speed (remove suspend) + + switch( bIndex ) { + + case USBFeatureRequest_TESTPACKET: + TRACE_DEBUG_WP("TEST_PACKET "); + + AT91C_BASE_UDPHS->UDPHS_DMA[1].UDPHS_DMACONTROL = 0; + AT91C_BASE_UDPHS->UDPHS_DMA[2].UDPHS_DMACONTROL = 0; + + // Configure endpoint 2, 64 bytes, direction IN, type BULK, 1 bank + AT91C_BASE_UDPHS->UDPHS_EPT[2].UDPHS_EPTCFG = AT91C_UDPHS_EPT_SIZE_64 | AT91C_UDPHS_EPT_DIR_IN | AT91C_UDPHS_EPT_TYPE_BUL_EPT | AT91C_UDPHS_BK_NUMBER_1; + while( (signed int)(AT91C_BASE_UDPHS->UDPHS_EPT[2].UDPHS_EPTCFG & AT91C_UDPHS_EPT_MAPD) != (signed int)AT91C_UDPHS_EPT_MAPD ) {} + + AT91C_BASE_UDPHS->UDPHS_EPT[2].UDPHS_EPTCTLENB = AT91C_UDPHS_EPT_ENABL; + + // Write FIFO + pFifo = (char*)((unsigned int *)(AT91C_BASE_UDPHS_EPTFIFO->UDPHS_READEPT0) + (16384 * 2)); + for( i=0; iUDPHS_TST |= AT91C_UDPHS_TST_PKT; + // Send packet + AT91C_BASE_UDPHS->UDPHS_EPT[2].UDPHS_EPTSETSTA = AT91C_UDPHS_TX_PK_RDY; + break; + + case USBFeatureRequest_TESTJ: + TRACE_DEBUG_WP("TEST_J "); + AT91C_BASE_UDPHS->UDPHS_TST = AT91C_UDPHS_TST_J; + break; + + case USBFeatureRequest_TESTK: + TRACE_DEBUG_WP("TEST_K "); + AT91C_BASE_UDPHS->UDPHS_TST = AT91C_UDPHS_TST_K; + break; + + case USBFeatureRequest_TESTSE0NAK: + TRACE_DEBUG_WP("TEST_SEO_NAK "); + AT91C_BASE_UDPHS->UDPHS_IEN = 0; // for test + break; + + case USBFeatureRequest_TESTSENDZLP: + //while( 0 != (AT91C_BASE_UDPHS->UDPHS_EPT[0].UDPHS_EPTSTA & AT91C_UDPHS_TX_PK_RDY ) ) {} + AT91C_BASE_UDPHS->UDPHS_EPT[0].UDPHS_EPTSETSTA = AT91C_UDPHS_TX_PK_RDY; + //while( 0 != (AT91C_BASE_UDPHS->UDPHS_EPT[0].UDPHS_EPTSTA & AT91C_UDPHS_TX_PK_RDY ) ) {} + TRACE_DEBUG_WP("SEND_ZLP "); + break; + } + TRACE_DEBUG_WP("\n\r"); +} + + +//------------------------------------------------------------------------------ +/// Initializes the specified USB driver +/// This function initializes the current FIFO bank of endpoints, +/// configures the pull-up and VBus lines, disconnects the pull-up and +/// then trigger the Init callback. +//------------------------------------------------------------------------------ +void USBD_Init( void ) +{ + unsigned char i; + + TRACE_DEBUG_WP("USBD Init()\n\r"); + + // Reset endpoint structures + UDPHS_ResetEndpoints(); + + // Enables the USB Clock + UDPHS_EnableUsbClock(); + + // Configure the pull-up on D+ and disconnect it +#if defined(BOARD_USB_PULLUP_INTERNAL) + AT91C_BASE_UDPHS->UDPHS_CTRL |= AT91C_UDPHS_DETACH; // detach + AT91C_BASE_UDPHS->UDPHS_CTRL |= AT91C_UDPHS_PULLD_DIS; // Disable Pull Down + +#elif defined(BOARD_USB_PULLUP_INTERNAL_BY_MATRIX) + TRACE_DEBUG_WP("PUON 0\n\r"); + AT91C_BASE_MATRIX->MATRIX_USBPCR &= ~AT91C_MATRIX_USBPCR_PUON; + +#elif defined(BOARD_USB_PULLUP_EXTERNAL) +#ifdef PIN_USB_PULLUP + const Pin pinPullUp = PIN_USB_PULLUP; + PIO_Configure(&pinPullUp, 1); + if (pinPullUp.attribute == PIO_OUTPUT_0) { + + PIO_Clear(&pinPullUp); + } + else { + + PIO_Set(&pinPullUp); + } +#else + #error unsupported now +#endif +#elif !defined(BOARD_USB_PULLUP_ALWAYSON) + #error Unsupported pull-up type. + +#endif + + // Reset and enable IP UDPHS + AT91C_BASE_UDPHS->UDPHS_CTRL &= ~AT91C_UDPHS_EN_UDPHS; + AT91C_BASE_UDPHS->UDPHS_CTRL |= AT91C_UDPHS_EN_UDPHS; + // Enable and disable of the transceiver is automaticaly done by the IP. + + // With OR without DMA !!! + // Initialization of DMA + for( i=1; i<=((AT91C_BASE_UDPHS->UDPHS_IPFEATURES & AT91C_UDPHS_DMA_CHANNEL_NBR)>>4); i++ ) { + + // RESET endpoint canal DMA: + // DMA stop channel command + AT91C_BASE_UDPHS->UDPHS_DMA[i].UDPHS_DMACONTROL = 0; // STOP command + + // Disable endpoint + AT91C_BASE_UDPHS->UDPHS_EPT[i].UDPHS_EPTCTLDIS = AT91C_UDPHS_SHRT_PCKT + | AT91C_UDPHS_BUSY_BANK + | AT91C_UDPHS_NAK_OUT + | AT91C_UDPHS_NAK_IN + | AT91C_UDPHS_STALL_SNT + | AT91C_UDPHS_RX_SETUP + | AT91C_UDPHS_TX_PK_RDY + | AT91C_UDPHS_TX_COMPLT + | AT91C_UDPHS_RX_BK_RDY + | AT91C_UDPHS_ERR_OVFLW + | AT91C_UDPHS_MDATA_RX + | AT91C_UDPHS_DATAX_RX + | AT91C_UDPHS_NYET_DIS + | AT91C_UDPHS_INTDIS_DMA + | AT91C_UDPHS_AUTO_VALID + | AT91C_UDPHS_EPT_DISABL; + + // Clear status endpoint + AT91C_BASE_UDPHS->UDPHS_EPT[i].UDPHS_EPTCLRSTA = AT91C_UDPHS_TOGGLESQ + | AT91C_UDPHS_FRCESTALL + | AT91C_UDPHS_RX_BK_RDY + | AT91C_UDPHS_TX_COMPLT + | AT91C_UDPHS_RX_SETUP + | AT91C_UDPHS_STALL_SNT + | AT91C_UDPHS_NAK_IN + | AT91C_UDPHS_NAK_OUT; + + // Reset endpoint config + AT91C_BASE_UDPHS->UDPHS_EPT[i].UDPHS_EPTCTLENB = 0; + + // Reset DMA channel (Buff count and Control field) + AT91C_BASE_UDPHS->UDPHS_DMA[i].UDPHS_DMACONTROL = AT91C_UDPHS_LDNXT_DSC; // NON STOP command + + // Reset DMA channel 0 (STOP) + AT91C_BASE_UDPHS->UDPHS_DMA[i].UDPHS_DMACONTROL = 0; // STOP command + + // Clear DMA channel status (read the register for clear it) + AT91C_BASE_UDPHS->UDPHS_DMA[i].UDPHS_DMASTATUS = AT91C_BASE_UDPHS->UDPHS_DMA[i].UDPHS_DMASTATUS; + + } + + AT91C_BASE_UDPHS->UDPHS_TST = 0; + AT91C_BASE_UDPHS->UDPHS_IEN = 0; + AT91C_BASE_UDPHS->UDPHS_CLRINT = AT91C_UDPHS_UPSTR_RES + | AT91C_UDPHS_ENDOFRSM + | AT91C_UDPHS_WAKE_UP + | AT91C_UDPHS_ENDRESET + | AT91C_UDPHS_IEN_SOF + | AT91C_UDPHS_MICRO_SOF + | AT91C_UDPHS_DET_SUSPD; + + // Device is in the Attached state + deviceState = USBD_STATE_SUSPENDED; + previousDeviceState = USBD_STATE_POWERED; + + // Disable interrupts + AT91C_BASE_UDPHS->UDPHS_IEN = AT91C_UDPHS_ENDOFRSM + | AT91C_UDPHS_WAKE_UP + | AT91C_UDPHS_DET_SUSPD; + + // Disable USB clocks + UDPHS_DisableUsbClock(); + + // Configure interrupts + USBDCallbacks_Initialized(); +} + +//------------------------------------------------------------------------------ +/// Returns the current state of the USB device. +/// \return Device current state. +//------------------------------------------------------------------------------ +unsigned char USBD_GetState( void ) +{ + return deviceState; +} + +#endif // BOARD_USB_UDPHS + diff --git a/at91lib/utility/assert.h b/at91lib/utility/assert.h new file mode 100644 index 0000000..5cccb61 --- /dev/null +++ b/at91lib/utility/assert.h @@ -0,0 +1,114 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \unit +/// +/// !Purpose +/// +/// Definition of the ASSERT() and SANITY_CHECK() macros, which are used for +/// runtime condition & parameter verifying. +/// +/// !Usage +/// +/// -# Use ASSERT() in your code to check the value of function parameters, +/// return values, etc. *Warning:* the ASSERT() condition must not have +/// any side-effect; otherwise, the program may not work properly +/// anymore when assertions are disabled. +/// -# Use SANITY_CHECK() to perform checks with a default error message +/// (outputs the file and line number where the error occured). This +/// reduces memory overhead caused by assertion error strings. +/// -# Initialize the dbgu to see failed assertions at run-time. +/// -# Assertions can be entirely disabled by defining the NOASSERT symbol +/// at compilation time. +//------------------------------------------------------------------------------ + +#ifndef ASSERT_H +#define ASSERT_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include +#include "trace.h" + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ +#if defined(NOASSERT) + #define ASSERT(...) + #define SANITY_CHECK(...) +#else + + #if (TRACE_LEVEL == 0) + /// Checks that the given condition is true, + /// otherwise stops the program execution. + /// \param condition Condition to verify. + #define ASSERT(condition, ...) { \ + if (!(condition)) { \ + while (1); \ + } \ + } + + /// Performs the same duty as the ASSERT() macro + /// \param condition Condition to verify. + #define SANITY_CHECK(condition) ASSERT(condition, ...) + + #else + /// Checks that the given condition is true, otherwise displays an error + /// message and stops the program execution. + /// \param condition Condition to verify. + #define ASSERT(condition, ...) { \ + if (!(condition)) { \ + printf("-F- ASSERT: "); \ + printf(__VA_ARGS__); \ + while (1); \ + } \ + } + #define SANITY_ERROR "Sanity check failed at %s:%d\n\r" + + /// Performs the same duty as the ASSERT() macro, except a default error + /// message is output if the condition is false. + /// \param condition Condition to verify. + #define SANITY_CHECK(condition) ASSERT(condition, SANITY_ERROR, __FILE__, __LINE__) + #endif +#endif + + + + + + + + + + +#endif //#ifndef ASSERT_H + diff --git a/at91lib/utility/led.c b/at91lib/utility/led.c new file mode 100644 index 0000000..7048b2a --- /dev/null +++ b/at91lib/utility/led.c @@ -0,0 +1,162 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include "led.h" +#include +#include + +//------------------------------------------------------------------------------ +// Local Variables +//------------------------------------------------------------------------------ + +#ifdef PINS_LEDS +static const Pin pinsLeds[] = {PINS_LEDS}; +static const unsigned int numLeds = PIO_LISTSIZE(pinsLeds); +#endif + +//------------------------------------------------------------------------------ +// Global Functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Configures the pin associated with the given LED number. If the LED does +/// not exist on the board, the function does nothing. +/// \param led Number of the LED to configure. +/// \return 1 if the LED exists and has been configured; otherwise 0. +//------------------------------------------------------------------------------ +unsigned char LED_Configure(unsigned int led) +{ +#ifdef PINS_LEDS + // Check that LED exists + if (led >= numLeds) { + + return 0; + } + + // Configure LED + return (PIO_Configure(&pinsLeds[led], 1)); +#else + return 0; +#endif +} + +//------------------------------------------------------------------------------ +/// Turns the given LED on if it exists; otherwise does nothing. +/// \param led Number of the LED to turn on. +/// \return 1 if the LED has been turned on; 0 otherwise. +//------------------------------------------------------------------------------ +unsigned char LED_Set(unsigned int led) +{ +#ifdef PINS_LEDS + // Check if LED exists + if (led >= numLeds) { + + return 0; + } + + // Turn LED on + if (pinsLeds[led].type == PIO_OUTPUT_0) { + + PIO_Set(&pinsLeds[led]); + } + else { + + PIO_Clear(&pinsLeds[led]); + } + + return 1; +#else + return 0; +#endif +} + +//------------------------------------------------------------------------------ +/// Turns a LED off. +/// \param led Number of the LED to turn off. +/// \param 1 if the LED has been turned off; 0 otherwise. +//------------------------------------------------------------------------------ +unsigned char LED_Clear(unsigned int led) +{ +#ifdef PINS_LEDS + // Check if LED exists + if (led >= numLeds) { + + return 0; + } + + // Turn LED off + if (pinsLeds[led].type == PIO_OUTPUT_0) { + + PIO_Clear(&pinsLeds[led]); + } + else { + + PIO_Set(&pinsLeds[led]); + } + + return 1; +#else + return 0; +#endif +} + +//------------------------------------------------------------------------------ +/// Toggles the current state of a LED. +/// \param led Number of the LED to toggle. +/// \return 1 if the LED has been toggled; otherwise 0. +//------------------------------------------------------------------------------ +unsigned char LED_Toggle(unsigned int led) +{ +#ifdef PINS_LEDS + // Check if LED exists + if (led >= numLeds) { + + return 0; + } + + // Toggle LED + if (PIO_GetOutputDataStatus(&pinsLeds[led])) { + + PIO_Clear(&pinsLeds[led]); + } + else { + + PIO_Set(&pinsLeds[led]); + } + + return 1; +#else + return 0; +#endif +} + diff --git a/at91lib/utility/led.h b/at91lib/utility/led.h new file mode 100644 index 0000000..3f4878f --- /dev/null +++ b/at91lib/utility/led.h @@ -0,0 +1,70 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \unit +/// +/// !Purpose +/// +/// Small set of functions for simple and portable LED usage. +/// +/// !Usage +/// +/// -# Configure one or more LEDs using LED_Configure and +/// LED_ConfigureAll. +/// -# Set, clear and toggle LEDs using LED_Set, LED_Clear and +/// LED_Toggle. +/// +/// LEDs are numbered starting from 0; the number of LEDs depend on the +/// board being used. All the functions defined here will compile properly +/// regardless of whether the LED is defined or not; they will simply +/// return 0 when a LED which does not exist is given as an argument. +/// Also, these functions take into account how each LED is connected on to +/// board; thus, might change the level on the corresponding pin +/// to 0 or 1, but it will always light the LED on; same thing for the other +/// methods. +//------------------------------------------------------------------------------ + +#ifndef LED_H +#define LED_H + +//------------------------------------------------------------------------------ +// Global Functions +//------------------------------------------------------------------------------ + +extern unsigned char LED_Configure(unsigned int led); + +extern unsigned char LED_Set(unsigned int led); + +extern unsigned char LED_Clear(unsigned int led); + +extern unsigned char LED_Toggle(unsigned int led); + +#endif //#ifndef LED_H + diff --git a/at91lib/utility/stdio.c b/at91lib/utility/stdio.c new file mode 100644 index 0000000..3e76ddc --- /dev/null +++ b/at91lib/utility/stdio.c @@ -0,0 +1,512 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \unit +/// +/// !Purpose +/// +/// Implementation of several stdio.h methods, such as printf(), sprintf() and +/// so on. This reduces the memory footprint of the binary when using those +/// methods, compared to the libc implementation. +/// +/// !Usage +/// +/// Adds stdio.c to the list of file to compile for the project. This will +/// automatically replace libc methods by the custom ones. +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include +#include + +//------------------------------------------------------------------------------ +// Local Definitions +//------------------------------------------------------------------------------ + +// Maximum string size allowed (in bytes). +#define MAX_STRING_SIZE 100 + +//------------------------------------------------------------------------------ +// Global Variables +//------------------------------------------------------------------------------ + +// Required for proper compilation. +struct _reent r = {0, (FILE *) 0, (FILE *) 1, (FILE *) 0}; +struct _reent *_impure_ptr = &r; + +//------------------------------------------------------------------------------ +// Local Functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Writes a character inside the given string. Returns 1. +// \param pStr Storage string. +// \param c Character to write. +//------------------------------------------------------------------------------ +signed int PutChar(char *pStr, char c) +{ + *pStr = c; + return 1; +} + +//------------------------------------------------------------------------------ +// Writes a string inside the given string. +// Returns the size of the written +// string. +// \param pStr Storage string. +// \param pSource Source string. +//------------------------------------------------------------------------------ +signed int PutString(char *pStr, const char *pSource) +{ + signed int num = 0; + + while (*pSource != 0) { + + *pStr++ = *pSource++; + num++; + } + + return num; +} + +//------------------------------------------------------------------------------ +// Writes an unsigned int inside the given string, using the provided fill & +// width parameters. +// Returns the size in characters of the written integer. +// \param pStr Storage string. +// \param fill Fill character. +// \param width Minimum integer width. +// \param value Integer value. +//------------------------------------------------------------------------------ +signed int PutUnsignedInt( + char *pStr, + char fill, + signed int width, + unsigned int value) +{ + signed int num = 0; + + // Take current digit into account when calculating width + width--; + + // Recursively write upper digits + if ((value / 10) > 0) { + + num = PutUnsignedInt(pStr, fill, width, value / 10); + pStr += num; + } + // Write filler characters + else { + + while (width > 0) { + + PutChar(pStr, fill); + pStr++; + num++; + width--; + } + } + + // Write lower digit + num += PutChar(pStr, (value % 10) + '0'); + + return num; +} + +//------------------------------------------------------------------------------ +// Writes a signed int inside the given string, using the provided fill & width +// parameters. +// Returns the size of the written integer. +// \param pStr Storage string. +// \param fill Fill character. +// \param width Minimum integer width. +// \param value Signed integer value. +//------------------------------------------------------------------------------ +signed int PutSignedInt( + char *pStr, + char fill, + signed int width, + signed int value) +{ + signed int num = 0; + unsigned int absolute; + + // Compute absolute value + if (value < 0) { + + absolute = -value; + } + else { + + absolute = value; + } + + // Take current digit into account when calculating width + width--; + + // Recursively write upper digits + if ((absolute / 10) > 0) { + + if (value < 0) { + + num = PutSignedInt(pStr, fill, width, -(absolute / 10)); + } + else { + + num = PutSignedInt(pStr, fill, width, absolute / 10); + } + pStr += num; + } + else { + + // Reserve space for sign + if (value < 0) { + + width--; + } + + // Write filler characters + while (width > 0) { + + PutChar(pStr, fill); + pStr++; + num++; + width--; + } + + // Write sign + if (value < 0) { + + num += PutChar(pStr, '-'); + pStr++; + } + } + + // Write lower digit + num += PutChar(pStr, (absolute % 10) + '0'); + + return num; +} + +//------------------------------------------------------------------------------ +// Writes an hexadecimal value into a string, using the given fill, width & +// capital parameters. +// Returns the number of char written. +// \param pStr Storage string. +// \param fill Fill character. +// \param width Minimum integer width. +// \param maj Indicates if the letters must be printed in lower- or upper-case. +// \param value Hexadecimal value. +//------------------------------------------------------------------------------ +signed int PutHexa( + char *pStr, + char fill, + signed int width, + unsigned char maj, + unsigned int value) +{ + signed int num = 0; + + // Decrement width + width--; + + // Recursively output upper digits + if ((value >> 4) > 0) { + + num += PutHexa(pStr, fill, width, maj, value >> 4); + pStr += num; + } + // Write filler chars + else { + + while (width > 0) { + + PutChar(pStr, fill); + pStr++; + num++; + width--; + } + } + + // Write current digit + if ((value & 0xF) < 10) { + + PutChar(pStr, (value & 0xF) + '0'); + } + else if (maj) { + + PutChar(pStr, (value & 0xF) - 10 + 'A'); + } + else { + + PutChar(pStr, (value & 0xF) - 10 + 'a'); + } + num++; + + return num; +} + +//------------------------------------------------------------------------------ +// Global Functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Stores the result of a formatted string into another string. Format +/// arguments are given in a va_list instance. +/// Return the number of characters written. +/// \param pStr Destination string. +/// \param length Length of Destination string. +/// \param pFormat Format string. +/// \param ap Argument list. +//------------------------------------------------------------------------------ +signed int vsnprintf(char *pStr, size_t length, const char *pFormat, va_list ap) +{ + char fill; + unsigned char width; + signed int num = 0; + signed int size = 0; + + // Clear the string + if (pStr) { + + *pStr = 0; + } + + // Phase string + while (*pFormat != 0 && size < length) { + + // Normal character + if (*pFormat != '%') { + + *pStr++ = *pFormat++; + size++; + } + // Escaped '%' + else if (*(pFormat+1) == '%') { + + *pStr++ = '%'; + pFormat += 2; + size++; + } + // Token delimiter + else { + + fill = ' '; + width = 0; + pFormat++; + + // Parse filler + if (*pFormat == '0') { + + fill = '0'; + pFormat++; + } + + // Parse width + while ((*pFormat >= '0') && (*pFormat <= '9')) { + + width = (width*10) + *pFormat-'0'; + pFormat++; + } + + // Check if there is enough space + if (size + width > length) { + + width = length - size; + } + + // Parse type + switch (*pFormat) { + case 'd': + case 'i': num = PutSignedInt(pStr, fill, width, va_arg(ap, signed int)); break; + case 'u': num = PutUnsignedInt(pStr, fill, width, va_arg(ap, unsigned int)); break; + case 'x': num = PutHexa(pStr, fill, width, 0, va_arg(ap, unsigned int)); break; + case 'X': num = PutHexa(pStr, fill, width, 1, va_arg(ap, unsigned int)); break; + case 's': num = PutString(pStr, va_arg(ap, char *)); break; + case 'c': num = PutChar(pStr, va_arg(ap, unsigned int)); break; + default: + return EOF; + } + + pFormat++; + pStr += num; + size += num; + } + } + + // NULL-terminated (final \0 is not counted) + if (size < length) { + + *pStr = 0; + } + else { + + *(--pStr) = 0; + size--; + } + + return size; +} + +//------------------------------------------------------------------------------ +/// Stores the result of a formatted string into another string. Format +/// arguments are given in a va_list instance. +/// Return the number of characters written. +/// \param pString Destination string. +/// \param length Length of Destination string. +/// \param pFormat Format string. +/// \param ... Other arguments +//------------------------------------------------------------------------------ +signed int snprintf(char *pString, size_t length, const char *pFormat, ...) +{ + va_list ap; + signed int rc; + + va_start(ap, pFormat); + rc = vsnprintf(pString, length, pFormat, ap); + va_end(ap); + + return rc; +} + +//------------------------------------------------------------------------------ +/// Stores the result of a formatted string into another string. Format +/// arguments are given in a va_list instance. +/// Return the number of characters written. +/// \param pString Destination string. +/// \param pFormat Format string. +/// \param ap Argument list. +//------------------------------------------------------------------------------ +signed int vsprintf(char *pString, const char *pFormat, va_list ap) +{ + return vsnprintf(pString, MAX_STRING_SIZE, pFormat, ap); +} + +//------------------------------------------------------------------------------ +/// Outputs a formatted string on the given stream. Format arguments are given +/// in a va_list instance. +/// \param pStream Output stream. +/// \param pFormat Format string +/// \param ap Argument list. +//------------------------------------------------------------------------------ +signed int vfprintf(FILE *pStream, const char *pFormat, va_list ap) +{ + char pStr[MAX_STRING_SIZE]; + char pError[] = "stdio.c: increase MAX_STRING_SIZE\n\r"; + + // Write formatted string in buffer + if (vsprintf(pStr, pFormat, ap) >= MAX_STRING_SIZE) { + + fputs(pError, stderr); + while (1); // Increase MAX_STRING_SIZE + } + + // Display string + return fputs(pStr, pStream); +} + +//------------------------------------------------------------------------------ +/// Outputs a formatted string on the DBGU stream. Format arguments are given +/// in a va_list instance. +/// \param pFormat Format string +/// \param ap Argument list. +//------------------------------------------------------------------------------ +signed int vprintf(const char *pFormat, va_list ap) +{ + return vfprintf(stdout, pFormat, ap); +} + +//------------------------------------------------------------------------------ +/// Outputs a formatted string on the given stream, using a variable number of +/// arguments. +/// \param pStream Output stream. +/// \param pFormat Format string. +//------------------------------------------------------------------------------ +signed int fprintf(FILE *pStream, const char *pFormat, ...) +{ + va_list ap; + signed int result; + + // Forward call to vfprintf + va_start(ap, pFormat); + result = vfprintf(pStream, pFormat, ap); + va_end(ap); + + return result; +} + +//------------------------------------------------------------------------------ +/// Outputs a formatted string on the DBGU stream, using a variable number of +/// arguments. +/// \param pFormat Format string. +//------------------------------------------------------------------------------ +signed int printf(const char *pFormat, ...) +{ + va_list ap; + signed int result; + + // Forward call to vprintf + va_start(ap, pFormat); + result = vprintf(pFormat, ap); + va_end(ap); + + return result; +} + +//------------------------------------------------------------------------------ +/// Writes a formatted string inside another string. +/// \param pStr Storage string. +/// \param pFormat Format string. +//------------------------------------------------------------------------------ +signed int sprintf(char *pStr, const char *pFormat, ...) +{ + va_list ap; + signed int result; + + // Forward call to vsprintf + va_start(ap, pFormat); + result = vsprintf(pStr, pFormat, ap); + va_end(ap); + + return result; +} + +//------------------------------------------------------------------------------ +/// Outputs a string on stdout. +/// \param pStr String to output. +//------------------------------------------------------------------------------ +signed int puts(const char *pStr) +{ + return fputs(pStr, stdout); +} + diff --git a/at91lib/utility/string.c b/at91lib/utility/string.c new file mode 100644 index 0000000..6c2af0d --- /dev/null +++ b/at91lib/utility/string.c @@ -0,0 +1,239 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \unit +/// +/// !Purpose +/// +/// Implementation of several methods defined in string.h, for reducing the +/// memory footprint when using them (since the whole libc.o file gets included +/// even when using a single method). +/// +/// !Usage +/// +/// Add string.c to the list of files to compile for the project. This will +/// automatically replace standard libc methods by the custom ones. +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include + +//------------------------------------------------------------------------------ +// Global Functions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Copies data from a source buffer into a destination buffer. The two buffers +/// must NOT overlap. Returns the destination buffer. +/// \param pDestination Destination buffer. +/// \param pSource Source buffer. +/// \param num Number of bytes to copy. +//------------------------------------------------------------------------------ +void * memcpy(void *pDestination, const void *pSource, size_t num) +{ + unsigned char *pByteDestination; + unsigned char *pByteSource; + unsigned int *pAlignedSource = (unsigned int *) pSource; + unsigned int *pAlignedDestination = (unsigned int *) pDestination; + + // If num is more than 4 bytes, and both dest. and source are aligned, + // then copy dwords + if ((((unsigned int) pAlignedDestination & 0x3) == 0) + && (((unsigned int) pAlignedSource & 0x3) == 0) + && (num >= 4)) { + + while (num >= 4) { + + *pAlignedDestination++ = *pAlignedSource++; + num -= 4; + } + } + + // Copy remaining bytes + pByteDestination = (unsigned char *) pAlignedDestination; + pByteSource = (unsigned char *) pAlignedSource; + while (num--) { + + *pByteDestination++ = *pByteSource++; + } + + return pDestination; +} + +//------------------------------------------------------------------------------ +/// Fills a memory region with the given value. Returns a pointer to the +/// memory region. +/// \param pBuffer Pointer to the start of the memory region to fill +/// \param value Value to fill the region with +/// \param num Size to fill in bytes +//------------------------------------------------------------------------------ +void * memset(void *pBuffer, int value, size_t num) +{ + unsigned char *pByteDestination; + unsigned int *pAlignedDestination = (unsigned int *) pBuffer; + unsigned int alignedValue = (value << 24) | (value << 16) | (value << 8) | value; + + // Set words if possible + if ((((unsigned int) pAlignedDestination & 0x3) == 0) && (num >= 4)) { + while (num >= 4) { + *pAlignedDestination++ = alignedValue; + num -= 4; + } + } + // Set remaining bytes + pByteDestination = (unsigned char *) pAlignedDestination; + while (num--) { + *pByteDestination++ = value; + } + return pBuffer; +} + +//----------------------------------------------------------------------------- +/// Search a character in the given string. +/// Returns a pointer to the character location. +/// \param pString Pointer to the start of the string to search. +/// \param character The character to find. +//----------------------------------------------------------------------------- +char * strchr(const char *pString, int character) +{ + char * p = (char *)pString; + char c = character & 0xFF; + + while(*p != c) { + if (*p == 0) { + return 0; + } + p++; + } + return p; +} + +//----------------------------------------------------------------------------- +/// Return the length of a given string +/// \param pString Pointer to the start of the string. +//----------------------------------------------------------------------------- +size_t strlen(const char *pString) +{ + unsigned int length = 0; + + while(*pString++ != 0) { + length++; + } + return length; +} + + +//----------------------------------------------------------------------------- +/// Search a character backword from the end of given string. +/// Returns a pointer to the character location. +/// \param pString Pointer to the start of the string to search. +/// \param character The character to find. +//----------------------------------------------------------------------------- +char * strrchr(const char *pString, int character) +{ + char *p = 0; + + while(*pString != 0) { + if (*pString++ == character) { + p = (char*)pString; + } + } + return p; +} + +//----------------------------------------------------------------------------- +/// Copy from source string to destination string +/// Return a pointer to the destination string +/// \param pDestination Pointer to the destination string. +/// \param pSource Pointer to the source string. +//----------------------------------------------------------------------------- +char * strcpy(char *pDestination, const char *pSource) +{ + char *pSaveDest = pDestination; + + for(; (*pDestination = *pSource) != 0; ++pSource, ++pDestination); + return pSaveDest; +} + +//----------------------------------------------------------------------------- +/// Compare the first specified bytes of 2 given strings +/// Return 0 if equals +/// Return >0 if 1st string > 2nd string +/// Return <0 if 1st string < 2nd string +/// \param pString1 Pointer to the start of the 1st string. +/// \param pString2 Pointer to the start of the 2nd string. +/// \param count Number of bytes that should be compared. +//----------------------------------------------------------------------------- +int strncmp(const char *pString1, const char *pString2, size_t count) +{ + int r; + + while(count) { + r = *pString1 - *pString2; + if (r == 0) { + if (*pString1 == 0) { + break; + } + pString1++; + pString2++; + count--; + continue; + } + return r; + } + return 0; +} + +//----------------------------------------------------------------------------- +/// Copy the first number of bytes from source string to destination string +/// Return the pointer to the destination string. +/// \param pDestination Pointer to the start of destination string. +/// \param pSource Pointer to the start of the source string. +/// \param count Number of bytes that should be copied. +//----------------------------------------------------------------------------- +char * strncpy(char *pDestination, const char *pSource, size_t count) +{ + char *pSaveDest = pDestination; + + while (count) { + *pDestination = *pSource; + if (*pSource == 0) { + break; + } + pDestination++; + pSource++; + count--; + } + return pSaveDest; +} + diff --git a/at91lib/utility/trace.h b/at91lib/utility/trace.h new file mode 100644 index 0000000..d996dcd --- /dev/null +++ b/at91lib/utility/trace.h @@ -0,0 +1,236 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/// \unit +/// +/// !Purpose +/// +/// Standard output methods for reporting debug information, warnings and +/// errors, which can be easily be turned on/off. +/// +/// !Usage +/// -# Initialize the DBGU using TRACE_CONFIGURE() if you intend to eventually +/// disable ALL traces; otherwise use DBGU_Configure(). +/// -# Uses the TRACE_DEBUG(), TRACE_INFO(), TRACE_WARNING(), TRACE_ERROR() +/// TRACE_FATAL() macros to output traces throughout the program. +/// -# Each type of trace has a level : Debug 5, Info 4, Warning 3, Error 2 +/// and Fatal 1. Disable a group of traces by changing the value of +/// TRACE_LEVEL during compilation; traces with a level bigger than TRACE_LEVEL +/// are not generated. To generate no trace, use the reserved value 0. +/// -# Trace disabling can be static or dynamic. If dynamic disabling is selected +/// the trace level can be modified in runtime. If static disabling is selected +/// the disabled traces are not compiled. +/// +/// !Trace level description +/// -# TRACE_DEBUG (5): Traces whose only purpose is for debugging the program, +/// and which do not produce meaningful information otherwise. +/// -# TRACE_INFO (4): Informational trace about the program execution. Should +/// enable the user to see the execution flow. +/// -# TRACE_WARNING (3): Indicates that a minor error has happened. In most case +/// it can be discarded safely; it may even be expected. +/// -# TRACE_ERROR (2): Indicates an error which may not stop the program execution, +/// but which indicates there is a problem with the code. +/// -# TRACE_FATAL (1): Indicates a major error which prevents the program from going +/// any further. + +//------------------------------------------------------------------------------ + +#ifndef TRACE_H +#define TRACE_H + +//------------------------------------------------------------------------------ +// Headers +//------------------------------------------------------------------------------ + +#include +#include +#include +#include + +//------------------------------------------------------------------------------ +// Global Definitions +//------------------------------------------------------------------------------ + +/// Softpack Version +#define SOFTPACK_VERSION "1.5" + +#define TRACE_LEVEL_DEBUG 5 +#define TRACE_LEVEL_INFO 4 +#define TRACE_LEVEL_WARNING 3 +#define TRACE_LEVEL_ERROR 2 +#define TRACE_LEVEL_FATAL 1 +#define TRACE_LEVEL_NO_TRACE 0 + +// By default, all traces are output except the debug one. +#if !defined(TRACE_LEVEL) +#define TRACE_LEVEL TRACE_LEVEL_INFO +#endif + +// By default, trace level is static (not dynamic) +#if !defined(DYN_TRACES) +#define DYN_TRACES 0 +#endif + +#if defined(NOTRACE) +#error "Error: NOTRACE has to be not defined !" +#endif + +#undef NOTRACE +#if (TRACE_LEVEL == TRACE_LEVEL_NO_TRACE) +#define NOTRACE +#endif + + + +//------------------------------------------------------------------------------ +// Global Macros +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Initializes the DBGU +/// \param mode DBGU mode. +/// \param baudrate DBGU baudrate. +/// \param mck Master clock frequency. +//------------------------------------------------------------------------------ +#define TRACE_CONFIGURE(mode, baudrate, mck) { \ + const Pin pinsDbgu[] = {PINS_DBGU}; \ + PIO_Configure(pinsDbgu, PIO_LISTSIZE(pinsDbgu)); \ + DBGU_Configure(mode, baudrate, mck); \ + } + +//------------------------------------------------------------------------------ +/// Initializes the DBGU for ISP project +/// \param mode DBGU mode. +/// \param baudrate DBGU baudrate. +/// \param mck Master clock frequency. +//------------------------------------------------------------------------------ +#if (TRACE_LEVEL==0) && (DYNTRACE==0) +#define TRACE_CONFIGURE_ISP(mode, baudrate, mck) {} +#else +#define TRACE_CONFIGURE_ISP(mode, baudrate, mck) { \ + const Pin pinsDbgu[] = {PINS_DBGU}; \ + PIO_Configure(pinsDbgu, PIO_LISTSIZE(pinsDbgu)); \ + DBGU_Configure(mode, baudrate, mck); \ + } +#endif + +//------------------------------------------------------------------------------ +/// Outputs a formatted string using if the log level is high +/// enough. Can be disabled by defining TRACE_LEVEL=0 during compilation. +/// \param format Formatted string to output. +/// \param ... Additional parameters depending on formatted string. +//------------------------------------------------------------------------------ +#if defined(NOTRACE) + +// Empty macro +#define TRACE_DEBUG(...) { } +#define TRACE_INFO(...) { } +#define TRACE_WARNING(...) { } +#define TRACE_ERROR(...) { } +#define TRACE_FATAL(...) { while(1); } + +#define TRACE_DEBUG_WP(...) { } +#define TRACE_INFO_WP(...) { } +#define TRACE_WARNING_WP(...) { } +#define TRACE_ERROR_WP(...) { } +#define TRACE_FATAL_WP(...) { while(1); } + +#elif (DYN_TRACES == 1) + +// Trace output depends on traceLevel value +#define TRACE_DEBUG(...) { if (traceLevel >= TRACE_LEVEL_DEBUG) { printf("-D- " __VA_ARGS__); } } +#define TRACE_INFO(...) { if (traceLevel >= TRACE_LEVEL_INFO) { printf("-I- " __VA_ARGS__); } } +#define TRACE_WARNING(...) { if (traceLevel >= TRACE_LEVEL_WARNING) { printf("-W- " __VA_ARGS__); } } +#define TRACE_ERROR(...) { if (traceLevel >= TRACE_LEVEL_ERROR) { printf("-E- " __VA_ARGS__); } } +#define TRACE_FATAL(...) { if (traceLevel >= TRACE_LEVEL_FATAL) { printf("-F- " __VA_ARGS__); while(1); } } + +#define TRACE_DEBUG_WP(...) { if (traceLevel >= TRACE_LEVEL_DEBUG) { printf(__VA_ARGS__); } } +#define TRACE_INFO_WP(...) { if (traceLevel >= TRACE_LEVEL_INFO) { printf(__VA_ARGS__); } } +#define TRACE_WARNING_WP(...) { if (traceLevel >= TRACE_LEVEL_WARNING) { printf(__VA_ARGS__); } } +#define TRACE_ERROR_WP(...) { if (traceLevel >= TRACE_LEVEL_ERROR) { printf(__VA_ARGS__); } } +#define TRACE_FATAL_WP(...) { if (traceLevel >= TRACE_LEVEL_FATAL) { printf(__VA_ARGS__); while(1); } } + +#else + +// Trace compilation depends on TRACE_LEVEL value +#if (TRACE_LEVEL >= TRACE_LEVEL_DEBUG) +#define TRACE_DEBUG(...) { printf("-D- " __VA_ARGS__); } +#define TRACE_DEBUG_WP(...) { printf(__VA_ARGS__); } +#else +#define TRACE_DEBUG(...) { } +#define TRACE_DEBUG_WP(...) { } +#endif + +#if (TRACE_LEVEL >= TRACE_LEVEL_INFO) +#define TRACE_INFO(...) { printf("-I- " __VA_ARGS__); } +#define TRACE_INFO_WP(...) { printf(__VA_ARGS__); } +#else +#define TRACE_INFO(...) { } +#define TRACE_INFO_WP(...) { } +#endif + +#if (TRACE_LEVEL >= TRACE_LEVEL_WARNING) +#define TRACE_WARNING(...) { printf("-W- " __VA_ARGS__); } +#define TRACE_WARNING_WP(...) { printf(__VA_ARGS__); } +#else +#define TRACE_WARNING(...) { } +#define TRACE_WARNING_WP(...) { } +#endif + +#if (TRACE_LEVEL >= TRACE_LEVEL_ERROR) +#define TRACE_ERROR(...) { printf("-E- " __VA_ARGS__); } +#define TRACE_ERROR_WP(...) { printf(__VA_ARGS__); } +#else +#define TRACE_ERROR(...) { } +#define TRACE_ERROR_WP(...) { } +#endif + +#if (TRACE_LEVEL >= TRACE_LEVEL_FATAL) +#define TRACE_FATAL(...) { printf("-F- " __VA_ARGS__); while(1); } +#define TRACE_FATAL_WP(...) { printf(__VA_ARGS__); while(1); } +#else +#define TRACE_FATAL(...) { while(1); } +#define TRACE_FATAL_WP(...) { while(1); } +#endif + +#endif + + +//------------------------------------------------------------------------------ +// Exported variables +//------------------------------------------------------------------------------ +// Depending on DYN_TRACES, traceLevel is a modifable runtime variable +// or a define +#if !defined(NOTRACE) && (DYN_TRACES == 1) + extern unsigned int traceLevel; +#endif + +#endif //#ifndef TRACE_H + diff --git a/cdc-test/Makefile b/cdc-test/Makefile new file mode 100644 index 0000000..2450cba --- /dev/null +++ b/cdc-test/Makefile @@ -0,0 +1,168 @@ +# ---------------------------------------------------------------------------- +# ATMEL Microcontroller Software Support +# ---------------------------------------------------------------------------- +# Copyright (c) 2008, Atmel Corporation +# +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# - Redistributions of source code must retain the above copyright notice, +# this list of conditions and the disclaimer below. +# +# Atmel's name may not be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +# DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +# OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# ---------------------------------------------------------------------------- + +# Makefile for compiling the USB CDC serial project + +#------------------------------------------------------------------------------- +# User-modifiable options +#------------------------------------------------------------------------------- + +# Chip & board used for compilation +# (can be overriden by adding CHIP=chip and BOARD=board to the command-line) +CHIP = at91sam7se512 +BOARD = theva-rev1 + +# Trace level used for compilation +# (can be overriden by adding TRACE_LEVEL=#number to the command-line) +# TRACE_LEVEL_DEBUG 5 +# TRACE_LEVEL_INFO 4 +# TRACE_LEVEL_WARNING 3 +# TRACE_LEVEL_ERROR 2 +# TRACE_LEVEL_FATAL 1 +# TRACE_LEVEL_NO_TRACE 0 +TRACE_LEVEL = 3 + +# Optimization level, put in comment for debugging +OPTIMIZATION = -O4 -mcpu=arm7tdmi + +# AT91 library directory +AT91LIB = ../at91lib + +# Output file basename +OUTPUT = cdc-test-$(BOARD)-$(CHIP) + +# Compile for all memories available on the board (this sets $(MEMORIES)) +include $(AT91LIB)/boards/$(BOARD)/board.mak + +# Output directories +BIN = bin +OBJ = obj + +#------------------------------------------------------------------------------- +# Tools +#------------------------------------------------------------------------------- + +# Tool suffix when cross-compiling +CROSS_COMPILE = arm-elf- +#arm-none-eabi- + +# Compilation tools +CC = $(CROSS_COMPILE)gcc +SIZE = $(CROSS_COMPILE)size +OBJCOPY = $(CROSS_COMPILE)objcopy + +# Flags +INCLUDES = -I$(AT91LIB)/boards/$(BOARD) -I$(AT91LIB)/peripherals +INCLUDES += -I$(AT91LIB)/components -I$(AT91LIB)/usb/device -I$(AT91LIB) + +CFLAGS = -Wall -mlong-calls -ffunction-sections +CFLAGS += $(OPTIMIZATION) $(INCLUDES) -D$(CHIP) -DTRACE_LEVEL=$(TRACE_LEVEL) +ASFLAGS = $(OPTIMIZATION) $(INCLUDES) -D$(CHIP) -D__ASSEMBLY__ +LDFLAGS = $(OPTIMIZATION) -nostartfiles -Wl,--gc-sections -L/usr/local/arm/arm-elf/lib + +#------------------------------------------------------------------------------- +# Files +#------------------------------------------------------------------------------- + +# Directories where source files can be found +USB = $(AT91LIB)/usb +UTILITY = $(AT91LIB)/utility +PERIPH = $(AT91LIB)/peripherals +BOARDS = $(AT91LIB)/boards + +VPATH += $(USB)/device/cdc-serial $(USB)/device/core $(USB)/common/core +VPATH += $(USB)/common/cdc +VPATH += $(UTILITY) +VPATH += $(PERIPH)/dbgu $(PERIPH)/aic $(PERIPH)/usart $(PERIPH)/pio $(PERIPH)/pmc +#VPATH += $(PERIPH)/cp15 +VPATH += $(BOARDS)/$(BOARD) $(BOARDS)/$(BOARD)/$(CHIP) + +# Objects built from C source files +C_OBJECTS = main.o +C_OBJECTS += CDCDSerialDriver.o CDCDSerialDriverDescriptors.o +C_OBJECTS += CDCSetControlLineStateRequest.o CDCLineCoding.o +C_OBJECTS += USBD_OTGHS.o USBD_UDP.o USBD_UDPHS.o USBDDriver.o +C_OBJECTS += USBDCallbacks_Initialized.o +C_OBJECTS += USBDCallbacks_Reset.o +#C_OBJECTS += USBDCallbacks_Resumed.o +#C_OBJECTS += USBDCallbacks_Suspended.o +C_OBJECTS += USBDDriverCb_CfgChanged.o +C_OBJECTS += USBDDriverCb_IfSettingChanged.o +C_OBJECTS += USBSetAddressRequest.o USBGenericDescriptor.o USBInterfaceRequest.o +C_OBJECTS += USBGenericRequest.o USBGetDescriptorRequest.o +C_OBJECTS += USBSetConfigurationRequest.o USBFeatureRequest.o +C_OBJECTS += USBEndpointDescriptor.o USBConfigurationDescriptor.o +C_OBJECTS += led.o string.o stdio.o +C_OBJECTS += aic.o dbgu.o usart.o pio.o pio_it.o pmc.o +C_OBJECTS += board_memories.o +C_OBJECTS += board_lowlevel.o +C_OBJECTS += power.o +C_OBJECTS += controlVelocity.o controlPWM.o communication.o # mathSin2000.o mathSin2048.o +C_OBJECTS += fixpawd.o fixpawd_math.o + +# Objects built from Assembly source files +ASM_OBJECTS = board_cstartup.o +#ASM_OBJECTS += cp15_asm.o + +# Append OBJ and BIN directories to output filename +OUTPUT := $(BIN)/$(OUTPUT) + +#------------------------------------------------------------------------------- +# Rules +#------------------------------------------------------------------------------- + +all: $(BIN) $(OBJ) $(MEMORIES) + +$(BIN) $(OBJ): + mkdir $@ + +define RULES +C_OBJECTS_$(1) = $(addprefix $(OBJ)/$(1)_, $(C_OBJECTS)) +ASM_OBJECTS_$(1) = $(addprefix $(OBJ)/$(1)_, $(ASM_OBJECTS)) + +$(1): $$(ASM_OBJECTS_$(1)) $$(C_OBJECTS_$(1)) + $(CC) $(LDFLAGS) -T"$(AT91LIB)/boards/$(BOARD)/$(CHIP)/$$@.lds" -o $(OUTPUT)-$$@.elf $$^ + $(OBJCOPY) -O binary $(OUTPUT)-$$@.elf $(OUTPUT)-$$@.bin + $(SIZE) $$^ $(OUTPUT)-$$@.elf + +$$(C_OBJECTS_$(1)): $(OBJ)/$(1)_%.o: %.c Makefile $(OBJ) $(BIN) + $(CC) $(CFLAGS) -D$(1) -c -o $$@ $$< + +$$(ASM_OBJECTS_$(1)): $(OBJ)/$(1)_%.o: %.S Makefile $(OBJ) $(BIN) + $(CC) $(ASFLAGS) -D$(1) -c -o $$@ $$< + +debug_$(1): $(1) + perl ../resources/gdb/debug.pl $(OUTPUT)-$(1).elf + +endef + +$(foreach MEMORY, $(MEMORIES), $(eval $(call RULES,$(MEMORY)))) + +clean: + -rm -f $(OBJ)/*.o $(BIN)/*.bin $(BIN)/*.elf + diff --git a/cdc-test/communication.c b/cdc-test/communication.c new file mode 100644 index 0000000..adb53fd --- /dev/null +++ b/cdc-test/communication.c @@ -0,0 +1,576 @@ +//----------------------------------------------------------------------------- +// Headers +//------------------------------------------------------------------------------ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "communication.h" +#include "registerFPGA.h" +#include "controlVelocity.h" +#include "controlPWM.h" + + +unsigned char send_buf[1024]; +unsigned char receive_buf[2048]; +int w_receive_buf = 0; +int r_receive_buf = 0; +unsigned long send_buf_pos = 0; +extern const Pin pinPWMEnable; + +void send( char *buf ) +{ + for( ; *buf; buf ++ ) + { + send_buf[send_buf_pos] = (unsigned char)(*buf); + send_buf_pos ++; + } +} + +void flush( void ) +{ + static int itry = 0; + if( send_buf_pos == 0 ) return; + while (1) + { + if( CDCDSerialDriver_Write(send_buf, + send_buf_pos, 0, 0) != USBD_STATUS_SUCCESS ) + { + itry ++; + if( itry > 0 ) + { + send_buf[send_buf_pos] = 0; + TRACE_ERROR( "Send Failed\n\r%s\n\r", send_buf); + break; + } + } + else + { + break; + } + } +// CDCDSerialDriver_Write(send_buf, send_buf_pos, 0, 0); +// printf("%u\n\r",send_buf_pos); + send_buf_pos = 0; +} + + +/** + * @brief GR[h + */ +int encode( unsigned char *src, int len, unsigned char *dst, int buf_max ) +{ + static int pos, s_pos, w_pos; + static unsigned short b; + pos = 0; // read position + w_pos = 0; // write_position + s_pos = 0; + b = 0; + + while( pos < len || s_pos >= 6 ) + { + if( s_pos >= 6 ) + { + dst[w_pos] = ( ( b >> 10 ) & 0x3f ) + 0x40; + w_pos++; + if( w_pos >= buf_max ) + return ( -1 ); + b = b << 6; + s_pos -= 6; + } + else + { + b |= src[pos] << ( 8 - s_pos ); + s_pos += 8; + pos++; + if( pos >= len ) + s_pos += 4; // Ō + } + } + + if( w_pos >= buf_max ) + return ( -1 ); + + return w_pos; +} + +/** + * @brief fR[h + * @param src[in] fR[h镶 + * @param len[in] fR[h镶̒ + * @param dst[out] fR[h̃f[^ + * @param buf_max[in] fR[h̃f[^obt@̃TCY + * @return fR[h̃oCg + */ +int decord( unsigned char *src, int len, unsigned char *dst, int buf_max ) +{ + static unsigned short dat, b; +// static int pos; + static int s_pos, w_pos; + static int rerr; +// pos = 0; // read position + w_pos = 0; // write_position + s_pos = 0; // shift position + rerr = 0; + dat = 0; + b = 0; + while( /*pos <*/ len ) + { + // if( src[pos] >= 0x40 ) + // b = src[pos] - 0x40; + if( *src >= 0x40 ) + b = *src - 0x40; + else + rerr++; + + dat |= ( b << ( 10 - s_pos ) ); + s_pos += 6; + if( s_pos >= 8 ) + { + dst[w_pos] = ( dat >> 8 ); + w_pos++; + if( w_pos >= buf_max ) + return 0; + s_pos -= 8; + dat = dat << 8; + } + // pos++; + src ++; + len --; + } + + if( rerr ) + return -rerr; + return w_pos; +} + +/* Ihgf[^̑M */ +int data_send( short cnt1, short cnt2, short pwm1, short pwm2, short *analog, unsigned short analog_mask ) +{ + static unsigned char data[34]; + + static int len, i, encode_len; + + data[0] = ( ( Integer2 ) cnt1 ).byte[1]; + data[1] = ( ( Integer2 ) cnt1 ).byte[0]; + data[2] = ( ( Integer2 ) cnt2 ).byte[1]; + data[3] = ( ( Integer2 ) cnt2 ).byte[0]; + data[4] = ( ( Integer2 ) pwm1 ).byte[1]; + data[5] = ( ( Integer2 ) pwm1 ).byte[0]; + data[6] = ( ( Integer2 ) pwm2 ).byte[1]; + data[7] = ( ( Integer2 ) pwm2 ).byte[0]; + + len = 8; + for ( i = 0; analog_mask != 0; analog_mask = analog_mask >> 1, i++ ) + { + if( analog_mask & 1 ) + { + data[len] = ( ( Integer2 ) analog[i] ).byte[1]; + data[len + 1] = ( ( Integer2 ) analog[i] ).byte[0]; + len += 2; + } + } + + // ϊ + send_buf_pos = 0; + send_buf[ 0 ] = COMMUNICATION_START_BYTE; + encode_len = encode( ( unsigned char * )data, len, send_buf + 1, 1024 - 2 ); + if( encode_len < 0 ) return encode_len; + send_buf[ encode_len + 1 ] = COMMUNICATION_END_BYTE; + send_buf_pos = encode_len + 2; + + flush(); + + return encode_len; +} + +int data_fetch( unsigned char *data, int len ) +{ + unsigned char *data_begin; + + data_begin = data; + for( ; len; len -- ) + { + receive_buf[ w_receive_buf ] = *data; + w_receive_buf ++; + data ++; + if( w_receive_buf >= 2048 ) w_receive_buf = 0; + if( w_receive_buf == r_receive_buf ) + { + break; + } + } + if( len ) + { + int i; + for( i = 0; i < len; i ++ ) + { + data_begin[ i ] = data[ i ]; + } + } + return len; +} + +int data_analyze( ) +{ + unsigned char line[64]; + unsigned char *data; + int r_buf, len; + enum{ + STATE_IDLE, + STATE_RECIEVING + } state = STATE_IDLE; + + r_buf = r_receive_buf; + data = &receive_buf[ r_receive_buf ]; + len = 0; + for( ; ; ) + { + if( r_buf == w_receive_buf ) break; + line[ len ] = *data; + len ++; + + switch( state ) + { + case STATE_IDLE: + if( *data == COMMUNICATION_START_BYTE ) + { + len = 0; + state = STATE_RECIEVING; + } + + if( *data == COMMUNICATION_END_BYTE ) + { + line[ len - 1 ] = 0; + extended_command_analyze( (char*)line ); + len = 0; + r_receive_buf = r_buf; + state = STATE_IDLE; + } + break; + case STATE_RECIEVING: + if( *data == COMMUNICATION_END_BYTE ) + { + static unsigned char rawdata[16]; + int data_len; + + data_len = decord( line, len - 1, rawdata, 16 ); + command_analyze( rawdata, data_len ); + len = 0; + r_receive_buf = r_buf; + state = STATE_IDLE; + } + break; + } + data ++; + r_buf ++; + if( r_buf >= 2048 ) + { + r_buf = 0; + data = receive_buf; + } + } + return 0; +} + + +// ////////////////////////////////////////////////// +/* MYPSpurgR}h̉ */ +int extended_command_analyze( char *data ) +{ +// char line[64]; + static int i; + + if( driver_param.servo_level != SERVO_LEVEL_STOP ) + return 0; + + send_buf_pos = 0; + if( strstr( data, "VV" ) == data ) + { + send( data ); + send( "\n00P\nVEND:" ); + send( YP_VENDOR_NAME ); + send( "; \nPROD:" ); + send( YP_PRODUCT_NAME ); + send( "; \nFIRM:" ); + send( YP_FIRMWARE_NAME ); + send( "; \nPROT:" ); + send( YP_PROTOCOL_NAME ); + send( "; \nSERI:Reserved; \n\n" ); + + } + else if( strstr( data, "ADMASK" ) == data ) + { + unsigned char tmp; + + tmp = 0; + for ( i = 6; data[i] != 0 && data[i] != '\n' && data[i] != '\r'; i++ ) + { + tmp = tmp << 1; + if( data[i] == '1' ) + tmp |= 1; + } +// analog_mask = tmp; + send( data ); + send( "\n00P\n\n" ); + } + else if( strstr( data, "SETIODIR" ) == data ) + { + unsigned char tmp; + // PE0-3(0-3), PB2-5(4-7) + + tmp = 0; + for ( i = 8; data[i] != 0 && data[i] != '\n' && data[i] != '\r'; i++ ) + { + tmp = tmp << 1; + if( data[i] == '1' ) + tmp |= 1; + } +// PFC.PEIOR.WORD = ( PFC.PEIOR.WORD & 0xFFF0 ) | ( ( tmp & 0x0F ) << 0 ); +// PFC.PBIOR.WORD = ( PFC.PBIOR.WORD & 0xFFC3 ) | ( ( tmp & 0xF0 ) >> 2 ); + send( data ); + send( "\n00P\n\n" ); + } + else if( strstr( data, "GETIOVAL" ) == data ) + { + unsigned short tmp; + char num[3]; +// tmp = ( PE.DR.WORD & 0x0F ) | ( ( PB.DR.WORD & 0x3C ) << 2 ); + tmp = 0; + send( data ); + send( "\n" ); + if( ( tmp >> 4 ) > 9 ){ + num[0] = ( tmp >> 4 ) - 10 + 'A'; + }else{ + num[0] = ( tmp >> 4 ) + '0'; + } + if( ( tmp & 0xF ) > 9 ){ + num[1] = ( tmp & 0xF ) - 10 + 'A'; + }else{ + num[1] = ( tmp & 0xF ) + '0'; + } + num[2] = 0; + send( num ); + send( " \n\n" ); + } + else if( strstr( data, "GETIO" ) == data ) + { + if( data[5] == '1' ) + { +// dio_enable = 1; + } + else + { +// dio_enable = 0; + } + send( data ); + send( "\n00P\n\n" ); + } + else if( strstr( data, "OUTPUT" ) == data ) + { + unsigned char tmp; + // PA18-21(0-3), PB2-5(4-7) + + tmp = 0; + for ( i = 6; data[i] != 0 && data[i] != '\n' && data[i] != '\r'; i++ ) + { + tmp = tmp << 1; + if( data[i] == '1' ) + tmp |= 1; + } +// PE.DR.WORD = ( PE.DR.WORD & 0xFFF0 ) | ( ( tmp & 0x0F ) << 0 ); +// PB.DR.WORD = ( PB.DR.WORD & 0xFFC3 ) | ( ( tmp & 0xF0 ) >> 2 ); + send( data ); + send( "\n00P\n\n" ); + } + else if( strstr( data, "SS" ) == data ) + { + int tmp; +// volatile int lo; + +// cnt_updated = 0; + tmp = 0; + for ( i = 2; data[i] != 0 && data[i] != '\n' && data[i] != '\r'; i++ ) + { + tmp *= 10; + tmp += data[i] - '0'; + } + send( data ); + send( "\n00P\n\n" ); + // MI܂őҋ@ +// while( SCI_send_rp[channel] != SCI_send_wp[channel] ); +// for ( lo = 0; lo < 10000; lo++ ); /* wait more than 1bit time */ +// sci_init( tmp ); +// sci_start( ); // start SCI +// cnt_updated = 0; + } + else if( strstr( data, "STORE" ) == data ) + { + int chk = 0xAACC; + AT91C_BASE_EFC1->EFC_FMR = AT91C_MC_FWS_1FWS; + memcpy( (int*)0x0017FF00, &driver_param, sizeof(driver_param) ); + memcpy( (int*)( 0x0017FF00 + sizeof(driver_param) ), motor_param, sizeof(motor_param) ); + memcpy( (int*)( 0x0017FF00 + sizeof(driver_param) + sizeof(motor_param) ), &chk, sizeof(chk) ); + AT91C_BASE_EFC1->EFC_FCR = AT91C_MC_FCMD_START_PROG | ( 0x3FF << 8 ); + send( data ); + send( "\n00P\n\n" ); + } + else + { + if( data[0] == 0 || data[0] == '\n' || data[0] == '\r' ) + return 0; + send( data ); + send( "\n0Ee\n\n" ); + } + flush(); + + return 1; +} + +// ////////////////////////////////////////////////// +/* MR}h̉ */ +int command_analyze( unsigned char *data, int len ) +{ + static int imotor, j; + + static Integer4 i; + + i.byte[3] = data[2]; + i.byte[2] = data[3]; + i.byte[1] = data[4]; + i.byte[0] = data[5]; + + imotor = data[1]; + if( imotor < 0 || imotor >= 2 ) + return 0; + +// if(data[0] != PARAM_w_ref) +// printf("get %d %d %d\n\r",data[0],data[1],i.integer); + switch ( data[0] ) + { + case PARAM_w_ref: + motor[imotor].ref.vel = i.integer; + motor[imotor].ref.vel_changed = 1; + driver_param.watchdog = 0; + break; + case PARAM_p_ki: + motor_param[imotor].Kcurrent = i.integer; + break; + case PARAM_p_kv: + motor_param[imotor].Kvolt = i.integer; + break; + case PARAM_p_fr_plus: + motor_param[imotor].fr_plus = i.integer; + break; + case PARAM_p_fr_wplus: + motor_param[imotor].fr_wplus = i.integer; + break; + case PARAM_p_fr_minus: + motor_param[imotor].fr_minus = i.integer; + break; + case PARAM_p_fr_wminus: + motor_param[imotor].fr_wminus = i.integer; + break; + case PARAM_p_A: + driver_param.Kdynamics[0] = i.integer; + break; + case PARAM_p_B: + driver_param.Kdynamics[1] = i.integer; + break; + case PARAM_p_C: + driver_param.Kdynamics[2] = i.integer; + break; + case PARAM_p_D: + driver_param.Kdynamics[3] = i.integer; + break; + case PARAM_p_E: + driver_param.Kdynamics[4] = i.integer; + break; + case PARAM_p_F: + driver_param.Kdynamics[5] = i.integer; + break; + case PARAM_p_pi_kp: + motor_param[imotor].Kp = i.integer; + break; + case PARAM_p_pi_ki: + motor_param[imotor].Ki = i.integer; + break; + case PARAM_pwm_max: + driver_param.PWM_max = i.integer; + //THEVA.GENERAL.PWM.HALF_PERIOD = driver_param.PWM_max; + THEVA.GENERAL.PWM.DEADTIME = 100; + for( j = 0; j < 3; j ++ ) + { + THEVA.MOTOR[0].PWM[j].L = THEVA.GENERAL.PWM.HALF_PERIOD; + THEVA.MOTOR[1].PWM[j].L = THEVA.GENERAL.PWM.HALF_PERIOD; + } + break; + case PARAM_pwm_min: + driver_param.PWM_min = i.integer; + break; + case PARAM_toq_max: + motor_param[imotor].torque_max = i.integer; + break; + case PARAM_toq_min: + motor_param[imotor].torque_min = i.integer; + break; + case PARAM_p_toq_offset: + motor_param[imotor].torque_offset = i.integer; + driver_param.watchdog = 0; + break; + case PARAM_int_max: + driver_param.integ_max = i.integer; + break; + case PARAM_int_min: + driver_param.integ_min = i.integer; + break; + case PARAM_servo: + if( driver_param.servo_level < SERVO_LEVEL_TORQUE && i.integer >= SERVO_LEVEL_TORQUE ) + { + if( THEVA.GENERAL.ID != 0xA0 ){ + TRACE_ERROR("Invalid FPGA %u !\n\r", THEVA.GENERAL.ID ); + while( 1 ); + } + + printf("initialized\n\r" ); + THEVA.GENERAL.PWM.HALF_PERIOD = 2400; + controlPWM_config(); + printf("PWM Period: %d\n\r", THEVA.GENERAL.PWM.HALF_PERIOD); + printf("PWM Deadtime: %d\n\r", THEVA.GENERAL.PWM.DEADTIME); + + THEVA.GENERAL.PWM.COUNT_ENABLE = 1; + THEVA.GENERAL.OUTPUT_ENABLE = 1; + PIO_Clear( &pinPWMEnable ); + // AIC_EnableIT(AT91C_ID_TC0); + } + if( driver_param.servo_level < SERVO_LEVEL_VELOCITY && i.integer >= SERVO_LEVEL_VELOCITY ) + { // servo levelxɐڂ + motor[0].error_integ = 0; + motor[1].error_integ = 0; + } + driver_param.servo_level = i.integer; + break; + case PARAM_watch_dog_limit: + driver_param.watchdog_limit = 0; + break; + case PARAM_io_dir: + break; + case PARAM_io_data: + break; +/* + case PARAM_enc_rev: + motor_param[0].changed = 1; + motor_param[1].changed = 1; +*/ + default: + break; + } + return 0; +} + diff --git a/cdc-test/communication.h b/cdc-test/communication.h new file mode 100644 index 0000000..76fb43f --- /dev/null +++ b/cdc-test/communication.h @@ -0,0 +1,85 @@ +#ifndef __COMMUNICATION_H__ +#define __COMMUNICATION_H__ + +typedef union _Integer4 +{ + int integer; + char byte[4]; +} Integer4; + +typedef union _Integer2 +{ + short integer; + char byte[2]; +} Integer2; + +// typedef +typedef enum _YPSpur_servo_level +{ + SERVO_LEVEL_STOP = 0, + SERVO_LEVEL_COUNTER, + SERVO_LEVEL_TORQUE, + SERVO_LEVEL_VELOCITY, + SERVO_LEVEL_POSITION // n/a +} YPSpur_servo_level; + +typedef enum +{ + PARAM_w_ref = 0, + PARAM_w_ref_diff, + PARAM_p_ki, + PARAM_p_kv, + PARAM_p_fr_plus, + PARAM_p_fr_wplus, + PARAM_p_fr_minus, + PARAM_p_fr_wminus, + PARAM_p_A, + PARAM_p_B, + PARAM_p_C, + PARAM_p_D, + PARAM_p_E, + PARAM_p_F, + PARAM_p_pi_kp, + PARAM_p_pi_ki, + PARAM_pwm_max, + PARAM_pwm_min, + PARAM_toq_max, + PARAM_toq_min, + PARAM_int_max, + PARAM_int_min, + PARAM_p_toq_offset, + PARAM_servo = 64, + PARAM_watch_dog_limit, + PARAM_io_dir = 96, + PARAM_io_data +} YPSpur_loco_param; + + +#define COMMUNICATION_START_BYTE 0x09 +#define COMMUNICATION_END_BYTE 0x0a + + +/* firmware */ +#define YP_FIRMWARE_NAME "2010.11.04" +/* parametor files dir */ +#define YP_PARAMS_DIR "robot-params" +/* product */ +#define YP_PRODUCT_NAME "Yamabico Project - Spur" +/* protocol */ +#define YP_PROTOCOL_NAME "YPP:04:04" +/* vendor */ +#define YP_VENDOR_NAME "Univ. of Tsukuba - Intelligent Robot Lab." + + + + +int data_analyze( ); +int data_fetch( unsigned char *data, int len ); +int extended_command_analyze( char *data ); +int command_analyze( unsigned char *data, int len ); +int data_send( short cnt1, short cnt2, short pwm1, short pwm2, short *analog, unsigned short analog_mask ); +int decord( unsigned char *src, int len, unsigned char *dst, int buf_max ); +int encode( unsigned char *src, int len, unsigned char *dst, int buf_max ); + + +#endif diff --git a/cdc-test/controlPWM.c b/cdc-test/controlPWM.c new file mode 100644 index 0000000..f6f7a0d --- /dev/null +++ b/cdc-test/controlPWM.c @@ -0,0 +1,288 @@ +//----------------------------------------------------------------------------- +// Headers +//------------------------------------------------------------------------------ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define FP4_POINTBIT 17 + +#include "registerFPGA.h" +#include "fixpawd.h" +#include "fixpawd_math.h" +#include "controlPWM.h" +#include "controlVelocity.h" +#include "power.h" + + +static const Pin pinsLeds[] = {PINS_LEDS}; +static const unsigned int numLeds = PIO_LISTSIZE(pinsLeds); + +static const Pin pinPWMCycle = PIN_PWM_CYCLE; +static const Pin pinPWMCycle2 = PIN_PWM_CYCLE2; + +//static long enc2phase[2]; +short SinTB[2][4096]; +int phase_offset[2][2]; +int phase90[2]; + +void controlPWM_config( void ) +{ + static unsigned short hall[2]; + static int i, j; + + hall[0] = *(unsigned short*)&THEVA.MOTOR[0].ROT_DETECTER; + hall[1] = *(unsigned short*)&THEVA.MOTOR[1].ROT_DETECTER; + + PIO_Clear( &pinsLeds[USBD_LEDPOWER] ); + for( i = 0; i < 2; i ++ ) + { + // enc2phase[i] = 2000 / motor_param[i].enc_rev; + + THEVA.MOTOR[i].PWM[0].L = driver_param.PWM_max; + THEVA.MOTOR[i].PWM[1].L = driver_param.PWM_max; + THEVA.MOTOR[i].PWM[2].L = driver_param.PWM_max; + + if( hall[i] & HALL_U ) + { + if( hall[i] & HALL_V ) + { + motor_param[i].enc0 = motor[i].pos - motor_param[i].enc_rev * 5 / 12; // 150x + } + else if( hall[i] & HALL_W ) + { + motor_param[i].enc0 = motor[i].pos - motor_param[i].enc_rev / 12; // 30x + } + else + { + motor_param[i].enc0 = motor[i].pos - motor_param[i].enc_rev / 4; // 90x + } + } + else + { + if( !( hall[i] & HALL_V ) ) + { + motor_param[i].enc0 = motor[i].pos - motor_param[i].enc_rev * 11 / 12; // 330x + } + else if( !( hall[i] & HALL_W ) ) + { + motor_param[i].enc0 = motor[i].pos - motor_param[i].enc_rev * 7 / 12; // 210x + } + else + { + motor_param[i].enc0 = motor[i].pos - motor_param[i].enc_rev * 3 / 4; // 270x + } + } + phase90[i] = motor_param[i].enc_rev - motor_param[i].enc_rev / 4; + phase_offset[i][ 0 ] = motor_param[i].enc_rev / 3; + phase_offset[i][ 1 ] = motor_param[i].enc_rev * 2 / 3; + if( i == 1 && motor_param[1].enc_rev == motor_param[0].enc_rev ) + { + for( j = 0; j < motor_param[i].enc_rev; j ++ ) + { + SinTB[1][j] = SinTB[0][j]; + } + break; + } + for( j = 0; j < motor_param[i].enc_rev; j ++ ) + { + fixp4 val; + int ival; + val = ( fp4sin( FP4_PI2 * j / motor_param[i].enc_rev ) + + fp4mul( fp4sin( FP4_PI2 * 3 * j / motor_param[i].enc_rev ), DOUBLE2FP4(0.1547) ) );//( 2 / sqrt( 3 ) - FP4_ONE ) + + ival = val * 4730 / FP4_ONE; + + if( ival > 4096 ) ival = 4096; + else if( ival < -4096 ) ival = -4096; + + SinTB[i][j] = ival; + } + } + PIO_Set( &pinsLeds[USBD_LEDPOWER] ); +} + +//------------------------------------------------------------------------------ +/// PWM control interrupt (every PWM period) 20us/50us +//------------------------------------------------------------------------------ +//void FIQ_PWMPeriod( const Pin *pPin ) +void FIQ_PWMPeriod( void ) +{ + static unsigned short enc[2]; + static unsigned short _enc[2]; + static unsigned short hall[2]; + static unsigned short _hall[2]; + //static int test = 0; + static int i; + static int init = 0; + static int cnt = 0; + +// AT91C_BASE_AIC->AIC_ICCR = 1 << AT91C_ID_IRQ0; + + if( driver_param.servo_level < SERVO_LEVEL_TORQUE ) return; + //PIO_Clear( &pinsLeds[USBD_LEDPOWER] ); + + motor[0].enc = enc[0] = 0xFFFF - THEVA.MOTOR[0].ENCODER; + motor[1].enc = enc[1] = 0xFFFF - THEVA.MOTOR[1].ENCODER; + + hall[0] = *(unsigned short*)&THEVA.MOTOR[0].ROT_DETECTER; + hall[1] = *(unsigned short*)&THEVA.MOTOR[1].ROT_DETECTER; + + if( !init ) + { + init = 1; + _hall[0] = hall[0]; + _hall[1] = hall[1]; + _enc[0] = enc[0]; + _enc[1] = enc[1]; + return; + } + + motor[0].pos += (short)( enc[0] - _enc[0] ); + motor[1].pos += (short)( enc[1] - _enc[1] ); + if( motor[0].pos >= motor_param[0].enc_rev ) motor[0].pos -= motor_param[0].enc_rev; + if( motor[1].pos >= motor_param[1].enc_rev ) motor[1].pos -= motor_param[1].enc_rev; + if( motor[0].pos < 0 ) motor[0].pos += motor_param[0].enc_rev; + if( motor[1].pos < 0 ) motor[1].pos += motor_param[1].enc_rev; + + // PWMvZ + { + static int pwm[2][3]; + static int phase[3]; + static int j; + + for( j = 0; j < 2; j ++ ) + { + phase[0] = ( ( motor[j].pos - motor_param[j].enc0)/* * enc2phase[j]*/ ) - phase90[j]; + while( phase[0] < 0 ) phase[0] += motor_param[j].enc_rev; + while( phase[0] >= motor_param[j].enc_rev ) phase[0] -= motor_param[j].enc_rev; + + phase[1] = phase[0] - phase_offset[j][ 0 ]; + while( phase[1] < 0 ) phase[1] += motor_param[j].enc_rev; + while( phase[1] >= motor_param[j].enc_rev ) phase[1] -= motor_param[j].enc_rev; + + phase[2] = phase[0] - phase_offset[j][ 1 ]; + while( phase[2] < 0 ) phase[2] += motor_param[j].enc_rev; + while( phase[2] >= motor_param[j].enc_rev ) phase[2] -= motor_param[j].enc_rev; + + for( i = 0; i < 3; i ++ ) + { + pwm[j][i] = ( ( (int)SinTB[j][ phase[i] ] * motor[j].ref.rate ) / 8192 ) + driver_param.PWM_max / 2; + if( pwm[j][i] < 0 ) pwm[j][i] = 0; + if( pwm[j][i] >= driver_param.PWM_max ) pwm[j][i] = driver_param.PWM_max - 1; + } + } + for( j = 0; j < 2; j ++ ) + { + for( i = 0; i < 3; i ++ ) + { + THEVA.MOTOR[j].PWM[i].H = pwm[j][i]; + } + } + } + + // [_vZ + for( i = 0; i < 2; i ++ ) + { + static char u; + static char v; + static char w; + + if( -20 < motor[i].vel && motor[i].vel < 20 ) + { + u = v = w = 0; + + if( ( hall[i] & HALL_U ) ) + { + if( !( _hall[i] & HALL_U ) ) + u = 1; // ] Uオ 0x + }else{ + if( ( _hall[i] & HALL_U ) ) + u = -1; // ] U 180x + } + + if( ( hall[i] & HALL_V ) ) + { + if( !( _hall[i] & HALL_V ) ) + v = 1; // ] Vオ 120x + }else{ + if( ( _hall[i] & HALL_V ) ) + v = -1; // ] V 300x + } + + if( ( hall[i] & HALL_W ) ) + { + if( !( _hall[i] & HALL_W ) ) + w = 1; // ] Wオ 240x + }else{ + if( ( _hall[i] & HALL_W ) ) + w = -1; // ] W 60x + } + + // t] + if( motor[i].vel < 0 ) + { + u = -u; v = -v; w = -w; + } + + // [_vZ + + /*if( w == -1 ) + motor_param[i].enc0 = motor[i].pos - motor_param[i].enc_rev / 6; + else if( v == 1 ) + motor_param[i].enc0 = motor[i].pos - motor_param[i].enc_rev * 2 / 6; + else */if( u == -1 ) + motor_param[i].enc0 = motor[i].pos - motor_param[i].enc_rev * 3 / 6; + /*else if( w == 1 ) + motor_param[i].enc0 = motor[i].pos - motor_param[i].enc_rev * 4 / 6; + else if( v == -1 ) + motor_param[i].enc0 = motor[i].pos - motor_param[i].enc_rev * 5 / 6; + else if( u == 1 ) + motor_param[i].enc0 = motor[i].pos;*/ + } + } + + _hall[0] = hall[0]; + _hall[1] = hall[1]; + _enc[0] = enc[0]; + _enc[1] = enc[1]; + + if( cnt ++ % 10 == 0 ) ISR_VelocityControl(); + + //PIO_Set( &pinsLeds[USBD_LEDPOWER] ); + + return; +} + +//------------------------------------------------------------------------------ +/// Configure velocity control loop +//------------------------------------------------------------------------------ +void controlPWM_init( ) +{ +/* + PIO_Configure( &pinPWMCycle, 1 ); + AIC_ConfigureIT( AT91C_ID_FIQ, AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE, FIQ_PWMPeriod ); + +// AIC_EnableIT(AT91C_ID_FIQ); +*/ + + PIO_Configure( &pinPWMCycle2, 1 ); + AIC_ConfigureIT( AT91C_ID_IRQ0, 0 | AT91C_AIC_SRCTYPE_POSITIVE_EDGE, FIQ_PWMPeriod ); + AIC_EnableIT(AT91C_ID_IRQ0); + +/* + PIO_Configure(&pinPWMCycle, 1); + PIO_ConfigureIt(&pinPWMCycle, FIQ_PWMPeriod); + PIO_EnableIt(&pinPWMCycle); +*/ +} + + + diff --git a/cdc-test/controlPWM.h b/cdc-test/controlPWM.h new file mode 100644 index 0000000..9d348de --- /dev/null +++ b/cdc-test/controlPWM.h @@ -0,0 +1,9 @@ +#ifndef __CONTROL_PWM_H__ +#define __CONTROL_PWM_H__ + +void controlPWM_init( ); +void controlPWM_config( void ); +inline void FIQ_PWMPeriod( void ); + +#endif + diff --git a/cdc-test/controlVelocity.c b/cdc-test/controlVelocity.c new file mode 100644 index 0000000..6705ae9 --- /dev/null +++ b/cdc-test/controlVelocity.c @@ -0,0 +1,217 @@ +//----------------------------------------------------------------------------- +// Headers +//------------------------------------------------------------------------------ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "controlPWM.h" +#include "controlVelocity.h" +#include "registerFPGA.h" + +MotorState motor[2]; +MotorParam motor_param[2]; +DriverParam driver_param; + + +static const Pin pinsLeds[] = {PINS_LEDS}; +static const unsigned int numLeds = PIO_LISTSIZE(pinsLeds); + +/// PWM Enable pin instance. +static const Pin pinPWMEnable = PIN_PWM_ENABLE; + +//------------------------------------------------------------------------------ +/// Velocity control loop (1ms) +//------------------------------------------------------------------------------ +void ISR_VelocityControl( ) +{ +// volatile unsigned int status; + + static unsigned short enc[2]; + static unsigned short _enc[2]; + static int pwm_sum[2] = { 0, 0 }; + static int error[2]; + static int i; + static int vel[2]; + +// PIO_Clear(&pinsLeds[USBD_LEDOTHER]); + +// status = AT91C_BASE_TC0->TC_SR; + + enc[0] = motor[0].enc; + enc[1] = motor[1].enc; + + vel[0] = (short)( enc[0] - _enc[0] ); + vel[1] = (short)( enc[1] - _enc[1] ); + + if( driver_param.servo_level >= SERVO_LEVEL_TORQUE ) + { // servo_level 2(toque enable) + int toq[2], out_pwm[2]; + + if( driver_param.servo_level >= SERVO_LEVEL_VELOCITY ) + { // servo_level 3 (speed enable) + int toq_pi[2], s_a, s_b; + for ( i = 0; i < 2; i++ ) + { + motor[i].ref.vel_interval ++; + if( motor[i].ref.vel_changed ) + { + static int vel_buf[2] = { 0, 0 }; + + motor[i].ref.vel_buf = motor[i].ref.vel; + motor[i].ref.vel_diff = ( motor[i].ref.vel_buf - vel_buf[i] ) / motor[i].ref.vel_interval; + + vel_buf[i] = motor[i].ref.vel_buf; + motor[i].ref.vel_interval = 0; + + motor[i].ref.vel_changed = 0; + } + } + for ( i = 0; i < 2; i++ ) + { + // 積分 + error[i] = motor[i].ref.vel - vel[i]; + motor[i].error_integ += error[i]; + if( motor[i].error_integ > driver_param.integ_max ) + { + motor[i].error_integ = driver_param.integ_max; + } + else if( motor[i].error_integ < driver_param.integ_min ) + { + motor[i].error_integ = driver_param.integ_min; + } + + // PI制御分 + toq_pi[i] = error[i] * motor_param[i].Kp + motor[i].error_integ * motor_param[i].Ki; + } + + // PWSでの相互の影響を考慮したフィードフォワード + s_a = ( toq_pi[0] + motor[0].ref.vel_diff ); + s_b = ( toq_pi[1] + motor[1].ref.vel_diff ); + + toq[0] = ( s_a * driver_param.Kdynamics[0] + + s_b * driver_param.Kdynamics[2] + + motor[0].ref.vel * driver_param.Kdynamics[4] ) / 256; + toq[1] = ( s_b * driver_param.Kdynamics[1] + + s_a * driver_param.Kdynamics[3] + + motor[1].ref.vel * driver_param.Kdynamics[5] ) / 256; + } + else + { // servo_level 2(toque enable) + toq[0] = 0; + toq[1] = 0; + } + // 出力段 + for ( i = 0; i < 2; i++ ) + { + // 摩擦補償（線形） + if( vel[i] > 0 ) + { + toq[i] += ( motor_param[i].fr_wplus * vel[i] + motor_param[i].fr_plus ); + } + else if( vel[i] < 0 ) + { + toq[i] -= ( motor_param[i].fr_wminus * ( -vel[i] ) + motor_param[i].fr_minus ); + } + // トルク補償 + toq[i] += motor_param[i].torque_offset; + + // トルクでクリッピング + if( toq[i] >= motor_param[i].torque_max ) + { + toq[i] = motor_param[i].torque_max; + } + if( toq[i] <= motor_param[i].torque_min ) + { + toq[i] = motor_param[i].torque_min; + } + + // トルク→pwm変換 + out_pwm[i] = ( toq[i] * motor_param[i].Kcurrent + vel[i] * motor_param[i].Kvolt ) / 65536; + + // PWMでクリッピング + if( out_pwm[i] > driver_param.PWM_max - 1 ) + out_pwm[i] = driver_param.PWM_max - 1; + if( out_pwm[i] < driver_param.PWM_min + 1 ) + out_pwm[i] = driver_param.PWM_min + 1; + } + + // 出力 + motor[0].ref.rate = out_pwm[0]; + motor[1].ref.rate = out_pwm[1]; + + pwm_sum[0] += out_pwm[0]; + pwm_sum[1] += out_pwm[1]; + + + driver_param.cnt_updated ++; + driver_param.watchdog ++; + if( driver_param.watchdog > driver_param.watchdog_limit ) + { + driver_param.watchdog = 0; + driver_param.watchdog_limit = 200; + driver_param.cnt_updated = 0; + driver_param.servo_level = SERVO_LEVEL_STOP; + THEVA.GENERAL.PWM.COUNT_ENABLE = 0; + THEVA.GENERAL.OUTPUT_ENABLE = 0; + PIO_Set( &pinPWMEnable ); + //AIC_DisableIT(AT91C_ID_TC0); + } + if( driver_param.cnt_updated == 5 ) + { + // static long cnt = 0; + motor[0].enc_buf = enc[0]; + motor[1].enc_buf = enc[1]; + motor[0].ref.rate_buf = pwm_sum[0]; + motor[1].ref.rate_buf = pwm_sum[1]; + pwm_sum[0] = 0; + pwm_sum[1] = 0; + } + } // servo_level 2*/ + else + { + motor[0].ref.rate = 0; + motor[1].ref.rate = 0; + } + for ( i = 0; i < 2; i++ ) + { + motor[i].vel = vel[i]; + motor[i].pos += vel[i]; + if( motor[i].pos >= motor_param[i].enc_rev ) motor[i].pos -= motor_param[i].enc_rev; + if( motor[i].pos < 0 ) motor[i].pos += motor_param[i].enc_rev; + + _enc[i] = enc[i]; + } +// PIO_Set(&pinsLeds[USBD_LEDOTHER]); +} + +//------------------------------------------------------------------------------ +/// Configure velocity control loop +//------------------------------------------------------------------------------ +void controlVelocity_init( ) +{ + // Configure timer 0 +/* + AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0); + AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; + AT91C_BASE_TC0->TC_IDR = 0xFFFFFFFF; + AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK + | AT91C_TC_WAVESEL_UP_AUTO + | AT91C_TC_WAVE; + AT91C_BASE_TC0->TC_RC = 1500 / 8; // 1ms 1500 + AT91C_BASE_TC0->TC_IER = AT91C_TC_CPCS; + + AIC_ConfigureIT(AT91C_ID_TC0, 1, ISR_VelocityControl); + //AIC_EnableIT(AT91C_ID_TC0); + + AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; +*/ +} + diff --git a/cdc-test/controlVelocity.h b/cdc-test/controlVelocity.h new file mode 100644 index 0000000..0c9fa2f --- /dev/null +++ b/cdc-test/controlVelocity.h @@ -0,0 +1,65 @@ +#ifndef __CONTROL_VELOCITY_H__ +#define __CONTROL_VELOCITY_H__ + +#include "communication.h" + +typedef struct _MotorState +{ + int vel; // count/ms + int pos; // count + int enc_buf; // count + unsigned short enc; + + struct{ + int vel; // count/ms + int vel_buf; // count/ms + char vel_changed; + int vel_interval; + int vel_diff; // count/ms + int torque; // 1/100000 Nm + int rate; // -PWM_max < rate < PWM_max + int rate_buf; // + } ref; + int error_integ; +} MotorState; + +typedef struct _MotorParam +{ + unsigned short enc_rev; // count/rev + int enc0; // count + int vel_max; // count/ms + int Kcurrent; + int Kvolt; + int Kp; // 1/s + int Ki; // 1/ss + int torque_max; + int torque_min; + int torque_offset; + int fr_plus; + int fr_wplus; + int fr_minus; + int fr_wminus; +} MotorParam; + +typedef struct _DriverParam +{ + int PWM_max; // clock + int PWM_min; // clock + int integ_max; // + int integ_min; // + int Kdynamics[6]; + YPSpur_servo_level servo_level; + unsigned short watchdog_limit; + unsigned short watchdog; + unsigned char cnt_updated; +} DriverParam; + +extern MotorState motor[2]; +extern MotorParam motor_param[2]; +extern DriverParam driver_param; + +void controlVelocity_init( ); +void ISR_VelocityControl( ); + +#endif + diff --git a/cdc-test/fixpawd.c b/cdc-test/fixpawd.c new file mode 100644 index 0000000..6c9c49b --- /dev/null +++ b/cdc-test/fixpawd.c @@ -0,0 +1,82 @@ +/** + @file fixp.c + @brief Fixed point value operation + */ + +#include "fixpawd.h" + +/** + @brief Multiple fixed point values (fast var) + @param a [in] Input value A + @param b [in] Input value B + @return A*B + */ +fixp4 fp4mulf( fixp4 a, fixp4 b ) +{ + return (fixp4)( ( (long long) a * b ) / FP4_ONE ); +} + +/** + @brief Multiple fixed point values + @param a [in] Input value A + @param b [in] Input value B + @return A*B + */ +fixp4 fp4mul( fixp4 a, fixp4 b ) +{ + long long y; + + y = (long long) a * b; + y = y >> FP4_POINTBIT; + + if( y > 0x7FFFFFFF ) return 0x7FFFFFFF; + if( y < -0x7FFFFFFF ) return -0x7FFFFFFF; + return (fixp4)y; +} + +/** + @brief Divide Fixed point value + @param a [in] Input value A + @param b [in] Input value B + @return A/B + */ +fixp4 fp4div( fixp4 a, fixp4 b ) +{ + return (fixp4)( ( (long long)a * FP4_ONE ) / b ); +} + +/** + @brief Convert double value to fixed point value + @param a [in] Input value A + @return A expressed in fixed point + */ +fixp4 double2fp4( double a ) +{ + return (fixp4)( a * FP4_MUL + 0.5 ); +} + +/** + @brief Convert int value to fixed point value + @param a [in] Input value A + @return A expressed in fixed point + */ +fixp4 int2fp4( int a ) +{ + return (fixp4)( a * FP4_ONE ); +} + +/** + @brief Convert fixed point value to double value + @param a [in] Input value A + @return A expressed in double + */ +double fp42double( fixp4 a ) +{ + return (double)a * FP4_DIV; +} + + + + + + diff --git a/cdc-test/fixpawd.h b/cdc-test/fixpawd.h new file mode 100644 index 0000000..d336896 --- /dev/null +++ b/cdc-test/fixpawd.h @@ -0,0 +1,34 @@ +/** + @file fixp.h + @brief Fixed point value operation + */ + +#ifndef __FIX_POINT_AWD__ +#define __FIX_POINT_AWD__ + + +#define INLINE inline + +typedef int fixp4; + +#ifndef FP4_POINTBIT +# define FP4_POINTBIT 17 +#endif + +# define FP4_POINTBIT2 (FP4_POINTBIT*2) +# define FP4_DIV (1.0/(double)(1< FP4_PI2 ) x = x % (FP4_PI2); + } + + if( x > FP4_PI ){ + minus = 1; + x -= FP4_PI; + } + if( x > FP4_PI_2 ) y = fp4cos( x - FP4_PI_2 ); + else if( x > FP4_PI_4 ) y = 2*fp4mulf( fp4cosf( x/2 ), fp4sinf( x/2 ) ); + else y = fp4sinf(x); + + if( minus ) return -y; + return y; +} + +/** + @brief Calculate cos function (fast ver, 0 <= x <= PI/4) + @param x [in] Input value + @return cos(x) + */ +fixp4 fp4cosf( fixp4 x ) +{ + fixp4 x2; // x^2 + fixp4 xn; // x^2, x^4, ... + fixp4 res; // Output + + x2 = fp4mulf( x, x ); + xn = x2; + res = FP4_ONE - fp4mulf( xn, DOUBLE2FP4( 1.0/2.0 ) ); + xn = fp4mulf( xn, x2 ); + res += fp4mulf( xn, DOUBLE2FP4( 1.0/24.0 ) ); + xn = fp4mulf( xn, x2 ); + res -= fp4mulf( xn, DOUBLE2FP4( 1.0/720.0 ) ); + + return res; +} + +/** + @brief Calculate cos function + @param x [in] Input value + @return cos(x) + */ +fixp4 fp4cos( fixp4 x ) +{ + char minus; // Is output value < 0 + fixp4 res; // Output + + minus = 0; + + if( x < 0 ){ + if( x < -FP4_PI2 ) x = x % (FP4_PI2); + x = FP4_PI2 - x; + }else{ + if( x > FP4_PI2 ) x = x % (FP4_PI2); + } + if( x > FP4_PI ){ + minus = 1; + x -= FP4_PI; + } + + if( x > FP4_PI_2 ) res = -fp4sin( x - FP4_PI_2 ); + else if( x > FP4_PI_4 ){ + res = fp4sinf( x/2 ); + res = FP4_ONE - 2*fp4mulf( res, res ); + }else res = fp4cosf(x); + + if( minus ) return -res; + return res; +} + +/** + @brief Calculate arctan [5 digit .17bit] + @param x [in] Input value + @return atan(x) + */ +fixp4 fp4atan( fixp4 x ) +{ + fixp4 xn; // x^2, x^3, ... + fixp4 th; // Output + char minus; // Is output value < 0 + char inv; // Is output value > 45deg + + minus = 0; + inv = 0; + + if( x < 0 ){ + x = -x; + minus = 1; + } + if( x > FP4_ONE ){ + x = fp4div( FP4_ONE ,x ); + inv = 1; + } + xn = x; + + // 5 digit + if( x <= DOUBLE2FP4(0.005) ){ + th = x; + }else if( x <= DOUBLE2FP4(0.45) ){ + // 0.0947x^5 + 0.0631x^4 - 0.3489x^3 + 0.0018x^2 + 0.9999x + 0.000003 + th = DOUBLE2FP4(0.000009); + th += fp4mul( xn , DOUBLE2FP4(0.99991) ); + xn = fp4mul( xn, x ); + th += fp4mul( xn , DOUBLE2FP4(0.0018) ); + xn = fp4mul( xn, x ); + th -= fp4mul( xn , DOUBLE2FP4(0.3489) ); + xn = fp4mul( xn, x ); + th += fp4mul( xn , DOUBLE2FP4(0.0631) ); + xn = fp4mul( xn, x ); + th += fp4mul( xn , DOUBLE2FP4(0.0947) ); + }else if( x <= DOUBLE2FP4(0.995) ){ + // -0.0687x^5 + 0.3126x^4 - 0.4914x^3 + 0.0332x^2 + 1.0006x + 0.00092 + th = -DOUBLE2FP4(0.000919); + th += fp4mul( xn , DOUBLE2FP4(1.0006) ); + xn = fp4mul( xn, x ); + th += fp4mul( xn , DOUBLE2FP4(0.0332) ); + xn = fp4mul( xn, x ); + th -= fp4mul( xn , DOUBLE2FP4(0.4914) ); + xn = fp4mul( xn, x ); + th += fp4mul( xn , DOUBLE2FP4(0.3126) ); + xn = fp4mul( xn, x ); + th -= fp4mul( xn , DOUBLE2FP4(0.0687) ); + }else{ + th = FP4_PI_4 - FP4_ONE/2 + x/2; + } + + if( inv ) th = FP4_PI_2 - th; + if( minus ) return -th; + return th; +} + +/** + @brief Calculate arctan with quadrant info [5 digit .17bit] + @param y [in] Input value y + @param x [in] Input value x + @return atan2(y/x) + */ +fixp4 fp4atan2( fixp4 y, fixp4 x ) +{ + fixp4 th; // Output + + if( x > y ){ + th = fp4atan( abs( fp4div( y, x ) ) ); + }else{ + th = FP4_PI_2 - fp4atan( abs( fp4div( x, y ) ) ); + } + if( y >= 0 ){ + if( x >= 0 ){ + return th; + }else{ + return FP4_PI - th; + } + }else{ + if( x >= 0 ){ + return -th; + }else{ + return -FP4_PI + th; + } + } + return 0; +} + +/** + @brief Calculate sqrt function + @param x [in] Input value + @return sqrt(x) + */ +fixp4 fp4sqrt( fixp4 x ) +{ + fixp4 res; // Output + + res = fp4mulf( x, fp4sqrtinv( x ) ); + res = ( fp4div( x, res ) + res ) >> 1; + + return res; +/* + // Slow: + fixp4 s, res; + long long x1; + + x1 = ( (long long) x ) << FP4_POINTBIT; + s = 1 << FP4_POINTBIT; + res = x; + while( s < res ){ + s = s << 1; + res = res >> 1; + } + do{ + res = s; + s = ( x1 / s + s ) >> 1; + }while( s < res ); + + return s; +*/ +} + +/** + @brief Calculate sqrt function (fast ver) + @param x [in] Input value + @return sqrt(x) + */ +fixp4 fp4sqrtf( fixp4 x ) +{ + return fp4mulf( x, fp4sqrtinv( x ) ); +} + +/** + @brief Calculate 1/sqrt function + @param x [in] Input value + @return 1/sqrt(x) + */ +fixp4 fp4sqrtinv( fixp4 x ) +{ + fixp4 res; // Output + fixp4 h, t; // Temporary + // char i; // Loop + + if( x & 0x40000000 ) res = fp4_sqrt[ 32 - FP4_POINTBIT + 30 ]; + else if( x & 0x20000000 ) res = fp4_sqrt[ 32 - FP4_POINTBIT + 29 ]; + else if( x & 0x10000000 ) res = fp4_sqrt[ 32 - FP4_POINTBIT + 28 ]; + else if( x & 0x08000000 ) res = fp4_sqrt[ 32 - FP4_POINTBIT + 27 ]; + else if( x & 0x04000000 ) res = fp4_sqrt[ 32 - FP4_POINTBIT + 26 ]; + else if( x & 0x02000000 ) res = fp4_sqrt[ 32 - FP4_POINTBIT + 25 ]; + else if( x & 0x01000000 ) res = fp4_sqrt[ 32 - FP4_POINTBIT + 24 ]; + else if( x & 0x00800000 ) res = fp4_sqrt[ 32 - FP4_POINTBIT + 23 ]; + else if( x & 0x00400000 ) res = fp4_sqrt[ 32 - FP4_POINTBIT + 22 ]; + else if( x & 0x00200000 ) res = fp4_sqrt[ 32 - FP4_POINTBIT + 21 ]; + else if( x & 0x00100000 ) res = fp4_sqrt[ 32 - FP4_POINTBIT + 20 ]; + else if( x & 0x00080000 ) res = fp4_sqrt[ 32 - FP4_POINTBIT + 19 ]; + else if( x & 0x00040000 ) res = fp4_sqrt[ 32 - FP4_POINTBIT + 18 ]; + else if( x & 0x00020000 ) res = fp4_sqrt[ 32 - FP4_POINTBIT + 17 ]; + else if( x & 0x00010000 ) res = fp4_sqrt[ 32 - FP4_POINTBIT + 16 ]; + else if( x & 0x00008000 ) res = fp4_sqrt[ 32 - FP4_POINTBIT + 15 ]; + else if( x & 0x00004000 ) res = fp4_sqrt[ 32 - FP4_POINTBIT + 14 ]; + else if( x & 0x00002000 ) res = fp4_sqrt[ 32 - FP4_POINTBIT + 13 ]; + else if( x & 0x00001000 ) res = fp4_sqrt[ 32 - FP4_POINTBIT + 12 ]; + else if( x & 0x00000800 ) res = fp4_sqrt[ 32 - FP4_POINTBIT + 11 ]; + else if( x & 0x00000400 ) res = fp4_sqrt[ 32 - FP4_POINTBIT + 10 ]; + else if( x & 0x00000200 ) res = fp4_sqrt[ 32 - FP4_POINTBIT + 9 ]; + else if( x & 0x00000100 ) res = fp4_sqrt[ 32 - FP4_POINTBIT + 8 ]; + else if( x & 0x00000080 ) res = fp4_sqrt[ 32 - FP4_POINTBIT + 7 ]; + else if( x & 0x00000040 ) res = fp4_sqrt[ 32 - FP4_POINTBIT + 6 ]; + else if( x & 0x00000020 ) res = fp4_sqrt[ 32 - FP4_POINTBIT + 5 ]; + else if( x & 0x00000010 ) res = fp4_sqrt[ 32 - FP4_POINTBIT + 4 ]; + else if( x & 0x00000008 ) res = fp4_sqrt[ 32 - FP4_POINTBIT + 3 ]; + else if( x & 0x00000004 ) res = fp4_sqrt[ 32 - FP4_POINTBIT + 2 ]; + else if( x & 0x00000002 ) res = fp4_sqrt[ 32 - FP4_POINTBIT + 1 ]; + else if( x & 0x00000001 ) res = fp4_sqrt[ 32 - FP4_POINTBIT ]; + else return 0; + /* + // 'if' lines mean: + for( i = 30; i >= 0; i -- ){ + if( x & ( 1 << i ) ){ + res = fp4_sqrt[ 32 - FP4_POINTBIT + i ]; + break; + } + } + */ + do{ + h = FP4_ONE - ( ( ( ( (long long)x * res ) >> FP4_POINTBIT ) * res ) >> FP4_POINTBIT ); + + t = h * 3 + FP4_ONE * 4; + t = ( (long long)h * t ) >> ( FP4_POINTBIT + 3 ); + t += FP4_ONE; + + res = ( (long long)res * t ) >> FP4_POINTBIT; + }while( abs( h ) > res ); + res ++; // magic + +#if FP4_POINTBIT > 17 + h = ( ( ( ( ( (long long)x * res ) >> FP4_POINTBIT ) * res ) >> FP4_POINTBIT ) * res ) >> FP4_POINTBIT; + res = ( 3 * res - h ) >> 1; +#endif + + return res; +} + +/** + @brief Calculate log2 function [4 digit .17bit] + @param x [in] Input value + @return log2(x) + */ +fixp4 fp4log2( fixp4 x ) +{ + fixp4 res; // Output + fixp4 fp; // Fraction + + res = 0; + while( x < FP4_ONE ){ + res -= FP4_ONE; + x *= 2; + } + while( x >= FP4_ONE*2 ){ + res += FP4_ONE; + x /= 2; + } + + x <<= ( 32 - FP4_POINTBIT - 5 ); + fp = FP4_ONE << ( 32 - FP4_POINTBIT - 5 ); + res <<= ( 32 - FP4_POINTBIT - 5 ); + + while( fp >= ( 1 << ( 33 - FP4_POINTBIT - 5 ) ) ){ + fp /= 2; + x = ( (long long)x * x ) >> ( 32 - 5 ); + + if( x >= ( FP4_ONE << ( 32 - FP4_POINTBIT - 5 + 1 ) ) ){ + x /= 2; + res += fp; + } + } + return res >> ( 32 - FP4_POINTBIT - 5 ); +} + +/** + @brief Calculate log2 function (fast ver) [2 digit .17bit] + @param x [in] Input value + @return log2(x) + */ +fixp4 fp4log2f( fixp4 x ) +{ + fixp4 res; // Output + fixp4 fp; // Fraction + + res = 0; + while( x < FP4_ONE ){ + res -= FP4_ONE; + x *= 2; + } + while( x >= FP4_ONE*2 ){ + res += FP4_ONE; + x /= 2; + } + + x <<= ( 32 - FP4_POINTBIT - 5 ); + fp = FP4_ONE << ( 32 - FP4_POINTBIT - 5 ); + res <<= ( 32 - FP4_POINTBIT - 5 ); + + while( fp >= ( 1 << ( 33 - FP4_POINTBIT - 5 ) ) ){ + fp /= 2; + x = ( x >> 13 ) * ( x >> 14 ); + + if( x >= ( FP4_ONE << ( 32 - FP4_POINTBIT - 5 + 1 ) ) ){ + x /= 2; + res += fp; + } + } + return res >> ( 32 - FP4_POINTBIT - 5 ); +} + +/** + @brief Calculate ln function + @param x [in] Input value + @return ln(x) + */ +fixp4 fp4ln( fixp4 x ) +{ + return fp4mulf( fp4log2( x ), FP4_LOG2E ); +} + +/** + @brief Calculate log function + @param x [in] Input value + @return log(x) + */ +fixp4 fp4log( fixp4 x ) +{ + return fp4mulf( fp4log2( x ), FP4_LOG2T ); +} + +/** + @brief Calculate logn function + @param x [in] Input value + @param n [in] Base value + @return log(x) + */ +fixp4 fp4logn( fixp4 x, fixp4 n ) +{ + return fp4div( fp4log2( x ), fp4log2( n ) ); +} + +/** + @brief Calculate ln function (fast ver) + @param x [in] Input value + @return ln(x) + */ +fixp4 fp4lnf( fixp4 x ) +{ + return fp4mulf( fp4log2f( x ), FP4_LOG2E ); +} + +/** + @brief Calculate log function (fast ver) + @param x [in] Input value + @return log(x) + */ +fixp4 fp4logf( fixp4 x ) +{ + return fp4mulf( fp4log2f( x ), FP4_LOG2T ); +} + +/** + @brief Calculate logn function (fast ver) + @param x [in] Input value + @param n [in] Base value + @return log(x) + */ +fixp4 fp4lognf( fixp4 x, fixp4 n ) +{ + return fp4div( fp4log2f( x ), fp4log2f( n ) ); +} + +/** + @brief Calculate exp function + @param x [in] Input value + @return exp(x) + */ +fixp4 fp4exp( fixp4 x ) +{ + fixp4 res; // Output + fixp4 mask; + int i; + char inv; + + if( x < 0 ){ + x = -x; + inv = 1; + }else inv = 0; + + mask = 1; + res = FP4_ONE << ( 32 - FP4_POINTBIT - 6 ); + for( i = 31-FP4_POINTBIT; i < 33; i ++ ){ + if( x & mask ) res = fp4mulf( res, fp4_exp[i] ); + mask <<= 1; + } + res >>= ( 32 - FP4_POINTBIT - 6 ); + + if( x & ( 1 << ( 33 - 31 + FP4_POINTBIT + 0 ) ) ) res = fp4mul( res, fp4_exp[33] ); + if( x & ( 1 << ( 33 - 31 + FP4_POINTBIT + 1 ) ) ) res = fp4mul( res, fp4_exp[34] ); + if( x & ( 1 << ( 33 - 31 + FP4_POINTBIT + 2 ) ) ) res = fp4mul( res, fp4_exp[35] ); + + /* + // 'if' lines mean: + for( i = 33; i < 36; i ++ ){ + if( x & mask ) res = fp4mul( res, fp4_exp[i] ); + mask <<= 1; + } + */ + + if( inv ) return fp4div( FP4_ONE, res ); + return res; +} diff --git a/cdc-test/fixpawd_math.h b/cdc-test/fixpawd_math.h new file mode 100644 index 0000000..edbe7fe --- /dev/null +++ b/cdc-test/fixpawd_math.h @@ -0,0 +1,153 @@ +/** + @file fixpawd_math.c + @brief Fixed point value mathmatical functions + */ + +#ifndef __FIX_POINT_AWD_MATH__ +#define __FIX_POINT_AWD_MATH__ + +#include "fixpawd.h" + +#define FP4_PI DOUBLE2FP4(3.1415926535897932384626433832795) +#define FP4_PI2 DOUBLE2FP4(3.1415926535897932384626433832795*2.0) +#define FP4_PI3_4 DOUBLE2FP4(3.1415926535897932384626433832795*3.0/4.0) +#define FP4_PI_2 DOUBLE2FP4(3.1415926535897932384626433832795/2.0) +#define FP4_PI_4 DOUBLE2FP4(3.1415926535897932384626433832795/4.0) +#define FP4_PI_6 DOUBLE2FP4(3.1415926535897932384626433832795/6.0) +#define FP4_E DOUBLE2FP4(2.718281828459045235360287471352) +#define FP4_LOG2E DOUBLE2FP4(1.0/1.4426950408889634073599246810022) +#define FP4_LOG2T DOUBLE2FP4(1.0/3.3219280948873623478703194294948) + + +INLINE fixp4 fp4sinf( fixp4 x ); +INLINE fixp4 fp4cosf( fixp4 x ); +INLINE fixp4 fp4sin( fixp4 x ); +INLINE fixp4 fp4cos( fixp4 x ); +INLINE fixp4 fp4atan( fixp4 x ); +INLINE fixp4 fp4atan2( fixp4 y, fixp4 x ); +INLINE fixp4 fp4sqrt( fixp4 x ); +INLINE fixp4 fp4sqrtf( fixp4 x ); +INLINE fixp4 fp4sqrtinv( fixp4 x ); +INLINE fixp4 fp4log2( fixp4 x ); +INLINE fixp4 fp4ln( fixp4 x ); +INLINE fixp4 fp4log( fixp4 x ); +INLINE fixp4 fp4logn( fixp4 x, fixp4 n ); +INLINE fixp4 fp4log2f( fixp4 x ); +INLINE fixp4 fp4lnf( fixp4 x ); +INLINE fixp4 fp4logf( fixp4 x ); +INLINE fixp4 fp4lognf( fixp4 x, fixp4 n ); +INLINE fixp4 fp4exp( fixp4 x ); + + + +/** Table for calc exp */ +static const fixp4 fp4_exp[36] = +{ + DOUBLE2FP4(1.0000000004656613), + DOUBLE2FP4(1.0000000009313226), + DOUBLE2FP4(1.0000000018626451), + DOUBLE2FP4(1.0000000037252903), + DOUBLE2FP4(1.0000000074505806), + DOUBLE2FP4(1.0000000149011612), + DOUBLE2FP4(1.0000000298023228), + DOUBLE2FP4(1.0000000596046466), + DOUBLE2FP4(1.0000001192092967), + DOUBLE2FP4(1.0000002384186075), + DOUBLE2FP4(1.0000004768372719), + DOUBLE2FP4(1.0000009536747712), + DOUBLE2FP4(1.0000019073504518), + DOUBLE2FP4(1.0000038147045416), + DOUBLE2FP4(1.0000076294236351), + DOUBLE2FP4(1.0000152589054785), + DOUBLE2FP4(1.0000305180437910), + DOUBLE2FP4(1.0000610370189331), + DOUBLE2FP4(1.0001220777633837), + DOUBLE2FP4(1.0002441704297478), + DOUBLE2FP4(1.0004884004786945), + DOUBLE2FP4(1.0009770394924165), + DOUBLE2FP4(1.0019550335910028), + DOUBLE2FP4(1.0039138893383475), + DOUBLE2FP4(1.0078430972064480), + DOUBLE2FP4(1.0157477085866857), + DOUBLE2FP4(1.0317434074991028), + DOUBLE2FP4(1.0644944589178593), + DOUBLE2FP4(1.1331484530668263), + DOUBLE2FP4(1.2840254166877414), + DOUBLE2FP4(1.6487212707001282), + DOUBLE2FP4(2.7182818284590451), + DOUBLE2FP4(7.3890560989306504), + DOUBLE2FP4(54.598150033144236), + DOUBLE2FP4(2980.9579870417283), + DOUBLE2FP4(8886110.5205078721) +}; + +/** Table for calc sqrt */ +static const fixp4 fp4_sqrt[64] = +{ + DOUBLE2FP4(46340.950006), + DOUBLE2FP4(32767.999996), + DOUBLE2FP4(23170.475003), + DOUBLE2FP4(16383.999998), + DOUBLE2FP4(11585.237502), + DOUBLE2FP4(8191.999999), + DOUBLE2FP4(5792.618751), + DOUBLE2FP4(4096.000000), + DOUBLE2FP4(2896.309375), + DOUBLE2FP4(2048.000000), + DOUBLE2FP4(1448.154688), + DOUBLE2FP4(1024.000000), + DOUBLE2FP4(724.077344), + DOUBLE2FP4(512.000000), + DOUBLE2FP4(362.038672), + DOUBLE2FP4(256.000000), + DOUBLE2FP4(181.019336), + DOUBLE2FP4(128.000000), + DOUBLE2FP4(90.509668), + DOUBLE2FP4(64.000000), + DOUBLE2FP4(45.254834), + DOUBLE2FP4(32.000000), + DOUBLE2FP4(22.627417), + DOUBLE2FP4(16.000000), + DOUBLE2FP4(11.313708), + DOUBLE2FP4(8.000000), + DOUBLE2FP4(5.656854), + DOUBLE2FP4(4.000000), + DOUBLE2FP4(2.828427), + DOUBLE2FP4(2.000000), + DOUBLE2FP4(1.414214), + DOUBLE2FP4(1.000000), + DOUBLE2FP4(0.707107), + DOUBLE2FP4(0.500000), + DOUBLE2FP4(0.353553), + DOUBLE2FP4(0.250000), + DOUBLE2FP4(0.176777), + DOUBLE2FP4(0.125000), + DOUBLE2FP4(0.088388), + DOUBLE2FP4(0.062500), + DOUBLE2FP4(0.044194), + DOUBLE2FP4(0.031250), + DOUBLE2FP4(0.022097), + DOUBLE2FP4(0.015625), + DOUBLE2FP4(0.011049), + DOUBLE2FP4(0.007812), + DOUBLE2FP4(0.005524), + DOUBLE2FP4(0.003906), + DOUBLE2FP4(0.002762), + DOUBLE2FP4(0.001953), + DOUBLE2FP4(0.001381), + DOUBLE2FP4(0.000977), + DOUBLE2FP4(0.000691), + DOUBLE2FP4(0.000488), + DOUBLE2FP4(0.000345), + DOUBLE2FP4(0.000244), + DOUBLE2FP4(0.000173), + DOUBLE2FP4(0.000122), + DOUBLE2FP4(0.000086), + DOUBLE2FP4(0.000061), + DOUBLE2FP4(0.000043), + DOUBLE2FP4(0.000031), + DOUBLE2FP4(0.000022), + DOUBLE2FP4(0.000000) +}; + +#endif diff --git a/cdc-test/main.c b/cdc-test/main.c new file mode 100644 index 0000000..a0bdfdb --- /dev/null +++ b/cdc-test/main.c @@ -0,0 +1,376 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2008, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + + +//----------------------------------------------------------------------------- +// Headers +//------------------------------------------------------------------------------ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "power.h" +#include "controlPWM.h" +#include "controlVelocity.h" +#include "registerFPGA.h" +#include "communication.h" + + +extern int getStackPointer( void ); +extern int getIrqStackPointer( void ); + +static const Pin pinsLeds[] = {PINS_LEDS}; +static const unsigned int numLeds = PIO_LISTSIZE(pinsLeds); + +//------------------------------------------------------------------------------ +// Definitions +//------------------------------------------------------------------------------ + +/// Size in bytes of the buffer used for reading data from the USB & USART +#define DATABUFFERSIZE \ + BOARD_USB_ENDPOINTS_MAXPACKETSIZE(CDCDSerialDriverDescriptors_DATAIN) + + +//------------------------------------------------------------------------------ +// Internal variables +//------------------------------------------------------------------------------ + +char connecting = 0; + +/// List of pins that must be configured for use by the application. +static const Pin pins[] = { PIN_PWM_ENABLE }; + +/// VBus pin instance. +static const Pin pinVbus = PIN_USB_VBUS; + +/// PWM Enable pin instance. +const Pin pinPWMEnable = PIN_PWM_ENABLE; + +/// Buffer for storing incoming USB data. +static unsigned char usbBuffer[DATABUFFERSIZE]; + + +//------------------------------------------------------------------------------ +// Main +//------------------------------------------------------------------------------ + +void SRAM_Init() +{ + static const Pin pinsSram[] = {PINS_SRAM}; + + // Enable corresponding PIOs + PIO_Configure(pinsSram, PIO_LISTSIZE(pinsSram)); + + AT91C_BASE_SMC->SMC2_CSR[0] = 1 | AT91C_SMC2_WSEN | (0 << 8) | AT91C_SMC2_BAT | AT91C_SMC2_DBW_16 | (1 << 24) | (1 << 28); +} + +//------------------------------------------------------------------------------ +/// Handles interrupts coming from PIO controllers. +//------------------------------------------------------------------------------ +static void ISR_Vbus(const Pin *pPin) +{ + // Check current level on VBus + if ( PIO_Get(&pinVbus)) { + TRACE_INFO("VBUS conn\n\r"); + USBD_Connect(); + connecting = 1; + //LED_Set(USBD_LEDPOWER); + }else{ + TRACE_INFO("VBUS discon\n\r"); + USBD_Disconnect(); + //LED_Clear(USBD_LEDPOWER); + //LED_Clear(USBD_LEDUSB); + PIO_Set( &pinPWMEnable ); + } +} + +//------------------------------------------------------------------------------ +/// Configures the VBus pin to trigger an interrupt when the level on that pin +/// changes. +//------------------------------------------------------------------------------ +static void VBus_Configure( void ) +{ + TRACE_INFO("VBus configuration\n\r"); + + // Configure PIO + PIO_Configure(&pinVbus, 1); + PIO_ConfigureIt(&pinVbus, ISR_Vbus); + PIO_EnableIt(&pinVbus); + + ISR_Vbus(&pinVbus); +} + +int natoi( unsigned char *buf, int size ) +{ + int ret, i; + ret = 0; + for( i = 0; i < size; i ++ ){ + if( '0' <= *buf && *buf <= '9' ) + { + ret *= 16; + ret += *buf - '0'; + } + else if( 'A' <= *buf && *buf <= 'F' ) + { + ret *= 16; + ret += *buf - 'A' + 0xA; + } + buf ++; + } + return ret; +} +int nitoa( unsigned char *buf, int data, int len ) +{ + int i; + for( i = 0; i < len; i ++ ){ + *buf = ( ( (unsigned int)data >> ( ( len - i - 1 ) * 4 ) ) & 0xF ) + '0'; + if( *buf > '9' ){ + *buf = *buf - '9' - 1 + 'A'; + } + buf ++; + } + return len; +} + + +//------------------------------------------------------------------------------ +/// Callback invoked when data has been received on the USB. +//------------------------------------------------------------------------------ +static void UsbDataReceived(unsigned int unused, + unsigned char status, + unsigned int received, + unsigned int remaining) +{ + // Check that data has been received successfully + if (status == USBD_STATUS_SUCCESS) { + static int remain = 0; +/* + unsigned short *freg = (void*)0x10000000; + unsigned short data; + int addr; + + addr = 0; + if( received > 2 ){ + addr = natoi( usbBuffer, 2 ); + if( received > 7 ){ + data = natoi( usbBuffer + 3, 4 ); + freg[ addr ] = data; + usbBuffer[ received ++ ] = 'W'; + } + usbBuffer[ received ++ ] = '['; + received += nitoa( usbBuffer + received, freg[ addr ], 4 ); + usbBuffer[ received ++ ] = ']'; + usbBuffer[ received ++ ] = '\n'; + usbBuffer[ received ++ ] = '\n'; + } +*/ +/* + if( received > 1 ){ + motor[0].ref.vel = natoi( usbBuffer, received - 1 ); + } + received += nitoa( usbBuffer + received, motor[0].vel, 4 ); + usbBuffer[ received ++ ] = '\n'; + usbBuffer[ received ++ ] = '\n'; +*/ + //LED_Clear(USBD_LEDUSB); + remain = data_fetch( usbBuffer, received + remain ); + + CDCDSerialDriver_Read(usbBuffer + remain, + DATABUFFERSIZE - remain, + (TransferCallback) UsbDataReceived, + 0); + //LED_Set(USBD_LEDUSB); +/* + TRACE_ERROR( + "%d %d\n", + driver_param.watchdog, THEVA.GENERAL.PWM.COUNT_ENABLE); +*/ + // Check if bytes have been discarded + if ((received == DATABUFFERSIZE) && (remaining > 0)) { + + TRACE_WARNING( + "UsbDataReceived: %u bytes discarded\n\r", + remaining); + } + } + else { + + TRACE_WARNING( "UsbDataReceived: Transfer error\n\r"); + } +} + + +//------------------------------------------------------------------------------ +// Main +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// Initializes drivers and start the USB <-> Serial bridge. +//------------------------------------------------------------------------------ +int main() +{ + short analog[9]; + short enc_buf2[2]; + + TRACE_CONFIGURE(DBGU_STANDARD, 230400, BOARD_MCK); + printf("-- Locomotion Board %s --\n\r", SOFTPACK_VERSION); + printf("-- %s\n\r", BOARD_NAME); + printf("-- Compiled: %s %s --\n\r", __DATE__, __TIME__); + + // If they are present, configure Vbus & Wake-up pins + PIO_InitializeInterrupts(0); + + // Configure USART + PIO_Configure(pins, PIO_LISTSIZE(pins)); + + // Disable PWM Output + PIO_Set( &pinPWMEnable ); + + // BOT driver initialization + CDCDSerialDriver_Initialize(); + + LED_Configure(USBD_LEDPOWER); + LED_Configure(USBD_LEDUSB); + LED_Configure(USBD_LEDOTHER); + + // connect if needed + VBus_Configure(); + + printf("sizeof(int) = %d\n\r", (int)sizeof(int) ); + printf("sizeof(long int) = %d\n\r", (int)sizeof(long int) ); + printf("sizeof(long) = %d\n\r", (int)sizeof(long) ); + printf("sizeof(short) = %d\n\r", (int)sizeof(short) ); + + printf("SRAM init\n\r" ); + SRAM_Init(); + + printf("PWM control init\n\r" ); + // Configure PWM control + controlPWM_init(); + + printf("Velocity Control init\n\r" ); + // Configure velocity control loop + controlVelocity_init(); + + enc_buf2[0] = enc_buf2[1] = 0; + motor[0].pos = motor[1].pos = 0; + driver_param.cnt_updated = 0; + driver_param.watchdog = 0; + driver_param.watchdog_limit = 500; + driver_param.servo_level = SERVO_LEVEL_STOP; + + motor[0].ref.vel = 0; + motor[1].ref.vel = 0; + motor_param[0].enc0 = 0; + motor_param[1].enc0 = 0; + + motor_param[0].enc_rev = 800; + motor_param[1].enc_rev = 800; + + if( *(int*)( 0x0017FF00 + sizeof(driver_param) + sizeof(motor_param) ) == 0xAACC ) + { + memcpy( &driver_param, (int*)( 0x0017FF00 ), sizeof(driver_param) ); + memcpy( motor_param, (int*)( 0x0017FF00 + sizeof(driver_param) ), sizeof(motor_param) ); + } + + // Watchdog Enable +// AT91C_BASE_WDTC->WDTC_WDMR = 102 /*0.4s*/ | AT91C_WDTC_WDRSTEN | AT91C_WDTC_WDRPROC | ( 102 << 16 ) | AT91C_WDTC_WDDBGHLT | AT91C_WDTC_WDIDLEHLT; + + // PIO_Clear(&pinsLeds[USBD_LEDOTHER]); + // PIO_Set(&pinsLeds[USBD_LEDOTHER]); + // Driver loop + while (1) { + static int i; + //int j; + +// AT91C_BASE_WDTC->WDTC_WDCR = 1; + data_analyze( ); + if( ( i ++ ) % 50000 == 0 ) + { + // int i; +/* printf("SP 0x%x 0x%x\n\r", getStackPointer(), getIrqStackPointer() ); + for( i = 0; i < 2; i ++ ) + { + printf(" Motor %d: iref=%d vel=%d vref=%d pos=%d(%d) %d\n\r", + i, motor[i].ref.rate, motor[i].vel, motor[i].ref.vel, motor[i].pos, motor_param[i].enc0, motor[i].error_integ ); + printf(" Hall: %d %d %d %d\n", + (THEVA.MOTOR[i].ROT_DETECTER.HALL & 1)!=0, + (THEVA.MOTOR[i].ROT_DETECTER.HALL & 2)!=0, + (THEVA.MOTOR[i].ROT_DETECTER.HALL & 4)!=0, + (THEVA.MOTOR[i].ROT_DETECTER.HALL & 0x80)!=0 ); + for( j = 0; j < 3; j ++ ) + { + printf( " %dH:%d L:%d\n",j,THEVA.MOTOR[i].PWM[j].H,THEVA.MOTOR[i].PWM[j].L ); + } + } + printf("\n\r" );*/ + } + if( connecting ){ + if(USBD_GetState() < USBD_STATE_CONFIGURED) continue; + + // Start receiving data on the USB + CDCDSerialDriver_Read(usbBuffer, + DATABUFFERSIZE, + (TransferCallback) UsbDataReceived, + 0); + connecting = 0; + + + } + + if( driver_param.cnt_updated >= 5 ) + { + unsigned short mask; + //static long cnt = 0; + /* 約5msおき */ + + mask = 0;//analog_mask; + data_send( ( short )( ( short )motor[0].enc_buf - ( short )enc_buf2[0] ), + ( short )( ( short )motor[1].enc_buf - ( short )enc_buf2[1] ), + motor[0].ref.rate_buf, motor[1].ref.rate_buf, analog, mask ); + + enc_buf2[0] = motor[0].enc_buf; + enc_buf2[1] = motor[1].enc_buf; + + driver_param.cnt_updated = 0; + + } + } +} + diff --git a/cdc-test/mathSin.h b/cdc-test/mathSin.h new file mode 100644 index 0000000..bc0ca92 --- /dev/null +++ b/cdc-test/mathSin.h @@ -0,0 +1,8 @@ + +#ifndef __SIN_H__ +#define __SIN_H__ + +extern const short sin2000[2000]; +extern const short sin2048[2048]; + +#endif diff --git a/cdc-test/mathSin2000.c b/cdc-test/mathSin2000.c new file mode 100644 index 0000000..4f7e58e --- /dev/null +++ b/cdc-test/mathSin2000.c @@ -0,0 +1,2002 @@ +const short sin2000[2000] = { + 0, // 0(deg) 0.000000 + 173, // 0.18(deg) 0.005306 + 347, // 0.36(deg) 0.010612 + 521, // 0.54(deg) 0.015918 + 695, // 0.72(deg) 0.021223 + 869, // 0.9(deg) 0.026528 + 1043, // 1.08(deg) 0.031831 + 1216, // 1.26(deg) 0.037134 + 1390, // 1.44(deg) 0.042435 + 1564, // 1.62(deg) 0.047734 + 1737, // 1.8(deg) 0.053032 + 1911, // 1.98(deg) 0.058328 + 2084, // 2.16(deg) 0.063622 + 2258, // 2.34(deg) 0.068914 + 2431, // 2.52(deg) 0.074204 + 2604, // 2.7(deg) 0.079491 + 2777, // 2.88(deg) 0.084775 + 2950, // 3.06(deg) 0.090056 + 3123, // 3.24(deg) 0.095334 + 3296, // 3.42(deg) 0.100608 + 3469, // 3.6(deg) 0.105880 + 3642, // 3.78(deg) 0.111147 + 3814, // 3.96(deg) 0.116411 + 3986, // 4.14(deg) 0.121670 + 4159, // 4.32(deg) 0.126926 + 4331, // 4.5(deg) 0.132177 + 4503, // 4.68(deg) 0.137423 + 4674, // 4.86(deg) 0.142664 + 4846, // 5.04(deg) 0.147901 + 5017, // 5.22(deg) 0.153133 + 5189, // 5.4(deg) 0.158359 + 5360, // 5.58(deg) 0.163579 + 5531, // 5.76(deg) 0.168794 + 5701, // 5.94(deg) 0.174003 + 5872, // 6.12(deg) 0.179207 + 6042, // 6.3(deg) 0.184403 + 6212, // 6.48(deg) 0.189594 + 6382, // 6.66(deg) 0.194778 + 6552, // 6.84(deg) 0.199955 + 6721, // 7.02(deg) 0.205125 + 6890, // 7.2(deg) 0.210289 + 7059, // 7.38(deg) 0.215445 + 7228, // 7.56(deg) 0.220593 + 7396, // 7.74(deg) 0.225734 + 7565, // 7.92(deg) 0.230867 + 7732, // 8.1(deg) 0.235992 + 7900, // 8.28(deg) 0.241109 + 8068, // 8.46(deg) 0.246218 + 8235, // 8.64(deg) 0.251318 + 8402, // 8.82(deg) 0.256410 + 8568, // 9(deg) 0.261493 + 8734, // 9.18(deg) 0.266567 + 8900, // 9.36(deg) 0.271631 + 9066, // 9.54(deg) 0.276687 + 9231, // 9.72(deg) 0.281733 + 9396, // 9.9(deg) 0.286769 + 9561, // 10.08(deg) 0.291795 + 9725, // 10.26(deg) 0.296812 + 9889, // 10.44(deg) 0.301818 + 10053, // 10.62(deg) 0.306814 + 10217, // 10.8(deg) 0.311800 + 10380, // 10.98(deg) 0.316775 + 10542, // 11.16(deg) 0.321739 + 10705, // 11.34(deg) 0.326692 + 10866, // 11.52(deg) 0.331634 + 11028, // 11.7(deg) 0.336565 + 11189, // 11.88(deg) 0.341484 + 11350, // 12.06(deg) 0.346392 + 11511, // 12.24(deg) 0.351288 + 11671, // 12.42(deg) 0.356172 + 11830, // 12.6(deg) 0.361044 + 11989, // 12.78(deg) 0.365904 + 12148, // 12.96(deg) 0.370752 + 12307, // 13.14(deg) 0.375587 + 12465, // 13.32(deg) 0.380409 + 12622, // 13.5(deg) 0.385219 + 12780, // 13.68(deg) 0.390016 + 12936, // 13.86(deg) 0.394799 + 13093, // 14.04(deg) 0.399569 + 13248, // 14.22(deg) 0.404326 + 13404, // 14.4(deg) 0.409070 + 13559, // 14.58(deg) 0.413799 + 13713, // 14.76(deg) 0.418515 + 13867, // 14.94(deg) 0.423217 + 14021, // 15.12(deg) 0.427905 + 14174, // 15.3(deg) 0.432579 + 14327, // 15.48(deg) 0.437238 + 14479, // 15.66(deg) 0.441882 + 14631, // 15.84(deg) 0.446512 + 14782, // 16.02(deg) 0.451127 + 14933, // 16.2(deg) 0.455728 + 15083, // 16.38(deg) 0.460313 + 15233, // 16.56(deg) 0.464883 + 15382, // 16.74(deg) 0.469437 + 15531, // 16.92(deg) 0.473977 + 15679, // 17.1(deg) 0.478500 + 15827, // 17.28(deg) 0.483008 + 15974, // 17.46(deg) 0.487500 + 16121, // 17.64(deg) 0.491976 + 16267, // 17.82(deg) 0.496436 + 16412, // 18(deg) 0.500880 + 16557, // 18.18(deg) 0.505307 + 16702, // 18.36(deg) 0.509718 + 16846, // 18.54(deg) 0.514112 + 16989, // 18.72(deg) 0.518490 + 17132, // 18.9(deg) 0.522851 + 17275, // 19.08(deg) 0.527195 + 17416, // 19.26(deg) 0.531521 + 17558, // 19.44(deg) 0.535831 + 17698, // 19.62(deg) 0.540123 + 17838, // 19.8(deg) 0.544398 + 17978, // 19.98(deg) 0.548656 + 18117, // 20.16(deg) 0.552896 + 18255, // 20.34(deg) 0.557118 + 18393, // 20.52(deg) 0.561322 + 18530, // 20.7(deg) 0.565509 + 18667, // 20.88(deg) 0.569677 + 18803, // 21.06(deg) 0.573827 + 18938, // 21.24(deg) 0.577959 + 19073, // 21.42(deg) 0.582073 + 19207, // 21.6(deg) 0.586168 + 19341, // 21.78(deg) 0.590245 + 19474, // 21.96(deg) 0.594303 + 19606, // 22.14(deg) 0.598342 + 19738, // 22.32(deg) 0.602362 + 19869, // 22.5(deg) 0.606364 + 19999, // 22.68(deg) 0.610346 + 20129, // 22.86(deg) 0.614310 + 20258, // 23.04(deg) 0.618254 + 20387, // 23.22(deg) 0.622179 + 20515, // 23.4(deg) 0.626085 + 20642, // 23.58(deg) 0.629971 + 20769, // 23.76(deg) 0.633838 + 20895, // 23.94(deg) 0.637685 + 21021, // 24.12(deg) 0.641512 + 21145, // 24.3(deg) 0.645320 + 21269, // 24.48(deg) 0.649108 + 21393, // 24.66(deg) 0.652876 + 21516, // 24.84(deg) 0.656624 + 21638, // 25.02(deg) 0.660352 + 21759, // 25.2(deg) 0.664059 + 21880, // 25.38(deg) 0.667747 + 22000, // 25.56(deg) 0.671414 + 22120, // 25.74(deg) 0.675061 + 22239, // 25.92(deg) 0.678688 + 22357, // 26.1(deg) 0.682294 + 22474, // 26.28(deg) 0.685879 + 22591, // 26.46(deg) 0.689444 + 22707, // 26.64(deg) 0.692988 + 22823, // 26.82(deg) 0.696512 + 22938, // 27(deg) 0.700015 + 23052, // 27.18(deg) 0.703497 + 23165, // 27.36(deg) 0.706958 + 23278, // 27.54(deg) 0.710398 + 23390, // 27.72(deg) 0.713817 + 23501, // 27.9(deg) 0.717215 + 23612, // 28.08(deg) 0.720592 + 23722, // 28.26(deg) 0.723948 + 23831, // 28.44(deg) 0.727283 + 23940, // 28.62(deg) 0.730596 + 24048, // 28.8(deg) 0.733889 + 24155, // 28.98(deg) 0.737159 + 24261, // 29.16(deg) 0.740409 + 24367, // 29.34(deg) 0.743637 + 24472, // 29.52(deg) 0.746844 + 24576, // 29.7(deg) 0.750029 + 24680, // 29.88(deg) 0.753193 + 24783, // 30.06(deg) 0.756336 + 24885, // 30.24(deg) 0.759456 + 24987, // 30.42(deg) 0.762555 + 25088, // 30.6(deg) 0.765633 + 25188, // 30.78(deg) 0.768689 + 25287, // 30.96(deg) 0.771723 + 25386, // 31.14(deg) 0.774736 + 25484, // 31.32(deg) 0.777727 + 25581, // 31.5(deg) 0.780696 + 25678, // 31.68(deg) 0.783643 + 25774, // 31.86(deg) 0.786569 + 25869, // 32.04(deg) 0.789472 + 25963, // 32.22(deg) 0.792354 + 26057, // 32.4(deg) 0.795214 + 26150, // 32.58(deg) 0.798053 + 26242, // 32.76(deg) 0.800869 + 26334, // 32.94(deg) 0.803664 + 26425, // 33.12(deg) 0.806437 + 26515, // 33.3(deg) 0.809188 + 26604, // 33.48(deg) 0.811917 + 26693, // 33.66(deg) 0.814624 + 26781, // 33.84(deg) 0.817309 + 26868, // 34.02(deg) 0.819973 + 26955, // 34.2(deg) 0.822614 + 27041, // 34.38(deg) 0.825234 + 27126, // 34.56(deg) 0.827832 + 27210, // 34.74(deg) 0.830408 + 27294, // 34.92(deg) 0.832962 + 27377, // 35.1(deg) 0.835494 + 27459, // 35.28(deg) 0.838005 + 27541, // 35.46(deg) 0.840493 + 27622, // 35.64(deg) 0.842960 + 27702, // 35.82(deg) 0.845405 + 27781, // 36(deg) 0.847828 + 27860, // 36.18(deg) 0.850230 + 27938, // 36.36(deg) 0.852610 + 28015, // 36.54(deg) 0.854967 + 28092, // 36.72(deg) 0.857304 + 28167, // 36.9(deg) 0.859618 + 28243, // 37.08(deg) 0.861911 + 28317, // 37.26(deg) 0.864182 + 28391, // 37.44(deg) 0.866432 + 28464, // 37.62(deg) 0.868660 + 28536, // 37.8(deg) 0.870867 + 28608, // 37.98(deg) 0.873052 + 28679, // 38.16(deg) 0.875215 + 28749, // 38.34(deg) 0.877357 + 28818, // 38.52(deg) 0.879478 + 28887, // 38.7(deg) 0.881577 + 28955, // 38.88(deg) 0.883655 + 29022, // 39.06(deg) 0.885711 + 29089, // 39.24(deg) 0.887746 + 29155, // 39.42(deg) 0.889760 + 29220, // 39.6(deg) 0.891753 + 29285, // 39.78(deg) 0.893725 + 29349, // 39.96(deg) 0.895675 + 29412, // 40.14(deg) 0.897605 + 29475, // 40.32(deg) 0.899513 + 29537, // 40.5(deg) 0.901401 + 29598, // 40.68(deg) 0.903268 + 29658, // 40.86(deg) 0.905113 + 29718, // 41.04(deg) 0.906938 + 29777, // 41.22(deg) 0.908742 + 29836, // 41.4(deg) 0.910526 + 29893, // 41.58(deg) 0.912289 + 29950, // 41.76(deg) 0.914031 + 30007, // 41.94(deg) 0.915753 + 30063, // 42.12(deg) 0.917454 + 30118, // 42.3(deg) 0.919135 + 30172, // 42.48(deg) 0.920796 + 30226, // 42.66(deg) 0.922436 + 30279, // 42.84(deg) 0.924056 + 30331, // 43.02(deg) 0.925656 + 30383, // 43.2(deg) 0.927236 + 30434, // 43.38(deg) 0.928795 + 30485, // 43.56(deg) 0.930335 + 30535, // 43.74(deg) 0.931855 + 30584, // 43.92(deg) 0.933356 + 30632, // 44.1(deg) 0.934836 + 30680, // 44.28(deg) 0.936297 + 30727, // 44.46(deg) 0.937738 + 30774, // 44.64(deg) 0.939160 + 30820, // 44.82(deg) 0.940562 + 30865, // 45(deg) 0.941945 + 30910, // 45.18(deg) 0.943309 + 30954, // 45.36(deg) 0.944654 + 30997, // 45.54(deg) 0.945979 + 31040, // 45.72(deg) 0.947286 + 31082, // 45.9(deg) 0.948573 + 31124, // 46.08(deg) 0.949842 + 31165, // 46.26(deg) 0.951092 + 31205, // 46.44(deg) 0.952323 + 31245, // 46.62(deg) 0.953536 + 31284, // 46.8(deg) 0.954730 + 31323, // 46.98(deg) 0.955906 + 31361, // 47.16(deg) 0.957063 + 31398, // 47.34(deg) 0.958202 + 31435, // 47.52(deg) 0.959323 + 31471, // 47.7(deg) 0.960426 + 31506, // 47.88(deg) 0.961512 + 31541, // 48.06(deg) 0.962579 + 31576, // 48.24(deg) 0.963628 + 31609, // 48.42(deg) 0.964660 + 31643, // 48.6(deg) 0.965675 + 31675, // 48.78(deg) 0.966672 + 31707, // 48.96(deg) 0.967651 + 31739, // 49.14(deg) 0.968613 + 31770, // 49.32(deg) 0.969559 + 31800, // 49.5(deg) 0.970487 + 31830, // 49.68(deg) 0.971398 + 31860, // 49.86(deg) 0.972292 + 31888, // 50.04(deg) 0.973170 + 31917, // 50.22(deg) 0.974031 + 31944, // 50.4(deg) 0.974875 + 31971, // 50.58(deg) 0.975703 + 31998, // 50.76(deg) 0.976515 + 32024, // 50.94(deg) 0.977310 + 32050, // 51.12(deg) 0.978090 + 32075, // 51.3(deg) 0.978853 + 32099, // 51.48(deg) 0.979601 + 32123, // 51.66(deg) 0.980333 + 32147, // 51.84(deg) 0.981049 + 32169, // 52.02(deg) 0.981750 + 32192, // 52.2(deg) 0.982435 + 32214, // 52.38(deg) 0.983105 + 32235, // 52.56(deg) 0.983760 + 32256, // 52.74(deg) 0.984400 + 32277, // 52.92(deg) 0.985025 + 32297, // 53.1(deg) 0.985635 + 32316, // 53.28(deg) 0.986230 + 32335, // 53.46(deg) 0.986811 + 32354, // 53.64(deg) 0.987377 + 32372, // 53.82(deg) 0.987929 + 32390, // 54(deg) 0.988467 + 32407, // 54.18(deg) 0.988990 + 32423, // 54.36(deg) 0.989500 + 32440, // 54.54(deg) 0.989995 + 32455, // 54.72(deg) 0.990477 + 32471, // 54.9(deg) 0.990946 + 32486, // 55.08(deg) 0.991400 + 32500, // 55.26(deg) 0.991842 + 32514, // 55.44(deg) 0.992270 + 32528, // 55.62(deg) 0.992685 + 32541, // 55.8(deg) 0.993087 + 32554, // 55.98(deg) 0.993476 + 32566, // 56.16(deg) 0.993853 + 32578, // 56.34(deg) 0.994217 + 32590, // 56.52(deg) 0.994568 + 32601, // 56.7(deg) 0.994907 + 32611, // 56.88(deg) 0.995234 + 32622, // 57.06(deg) 0.995548 + 32632, // 57.24(deg) 0.995851 + 32641, // 57.42(deg) 0.996142 + 32650, // 57.6(deg) 0.996421 + 32659, // 57.78(deg) 0.996688 + 32667, // 57.96(deg) 0.996944 + 32675, // 58.14(deg) 0.997189 + 32683, // 58.32(deg) 0.997422 + 32690, // 58.5(deg) 0.997645 + 32697, // 58.68(deg) 0.997856 + 32704, // 58.86(deg) 0.998057 + 32710, // 59.04(deg) 0.998246 + 32716, // 59.22(deg) 0.998426 + 32721, // 59.4(deg) 0.998595 + 32727, // 59.58(deg) 0.998753 + 32732, // 59.76(deg) 0.998902 + 32736, // 59.94(deg) 0.999040 + 32740, // 60.12(deg) 0.999168 + 32744, // 60.3(deg) 0.999287 + 32748, // 60.48(deg) 0.999396 + 32751, // 60.66(deg) 0.999496 + 32754, // 60.84(deg) 0.999586 + 32757, // 61.02(deg) 0.999667 + 32759, // 61.2(deg) 0.999739 + 32761, // 61.38(deg) 0.999801 + 32763, // 61.56(deg) 0.999855 + 32764, // 61.74(deg) 0.999901 + 32765, // 61.92(deg) 0.999937 + 32766, // 62.1(deg) 0.999966 + 32767, // 62.28(deg) 0.999985 + 32767, // 62.46(deg) 0.999997 + 32767, // 62.64(deg) 1.000001 + 32767, // 62.82(deg) 0.999996 + 32767, // 63(deg) 0.999984 + 32766, // 63.18(deg) 0.999965 + 32765, // 63.36(deg) 0.999937 + 32764, // 63.54(deg) 0.999903 + 32763, // 63.72(deg) 0.999861 + 32761, // 63.9(deg) 0.999812 + 32759, // 64.08(deg) 0.999756 + 32757, // 64.26(deg) 0.999693 + 32755, // 64.44(deg) 0.999623 + 32753, // 64.62(deg) 0.999546 + 32750, // 64.8(deg) 0.999464 + 32747, // 64.98(deg) 0.999374 + 32744, // 65.16(deg) 0.999279 + 32741, // 65.34(deg) 0.999177 + 32737, // 65.52(deg) 0.999070 + 32733, // 65.7(deg) 0.998957 + 32729, // 65.88(deg) 0.998837 + 32725, // 66.06(deg) 0.998713 + 32721, // 66.24(deg) 0.998583 + 32717, // 66.42(deg) 0.998447 + 32712, // 66.6(deg) 0.998307 + 32707, // 66.78(deg) 0.998161 + 32702, // 66.96(deg) 0.998010 + 32697, // 67.14(deg) 0.997855 + 32692, // 67.32(deg) 0.997694 + 32687, // 67.5(deg) 0.997530 + 32681, // 67.68(deg) 0.997360 + 32675, // 67.86(deg) 0.997187 + 32669, // 68.04(deg) 0.997009 + 32664, // 68.22(deg) 0.996827 + 32657, // 68.4(deg) 0.996641 + 32651, // 68.58(deg) 0.996452 + 32645, // 68.76(deg) 0.996258 + 32638, // 68.94(deg) 0.996061 + 32632, // 69.12(deg) 0.995861 + 32625, // 69.3(deg) 0.995657 + 32618, // 69.48(deg) 0.995450 + 32612, // 69.66(deg) 0.995240 + 32605, // 69.84(deg) 0.995027 + 32597, // 70.02(deg) 0.994811 + 32590, // 70.2(deg) 0.994592 + 32583, // 70.38(deg) 0.994371 + 32576, // 70.56(deg) 0.994147 + 32568, // 70.74(deg) 0.993920 + 32561, // 70.92(deg) 0.993692 + 32553, // 71.1(deg) 0.993461 + 32546, // 71.28(deg) 0.993228 + 32538, // 71.46(deg) 0.992993 + 32530, // 71.64(deg) 0.992756 + 32522, // 71.82(deg) 0.992518 + 32514, // 72(deg) 0.992278 + 32507, // 72.18(deg) 0.992036 + 32499, // 72.36(deg) 0.991793 + 32491, // 72.54(deg) 0.991549 + 32483, // 72.72(deg) 0.991304 + 32474, // 72.9(deg) 0.991057 + 32466, // 73.08(deg) 0.990810 + 32458, // 73.26(deg) 0.990561 + 32450, // 73.44(deg) 0.990312 + 32442, // 73.62(deg) 0.990062 + 32434, // 73.8(deg) 0.989812 + 32425, // 73.98(deg) 0.989561 + 32417, // 74.16(deg) 0.989310 + 32409, // 74.34(deg) 0.989059 + 32401, // 74.52(deg) 0.988807 + 32392, // 74.7(deg) 0.988556 + 32384, // 74.88(deg) 0.988304 + 32376, // 75.06(deg) 0.988053 + 32368, // 75.24(deg) 0.987802 + 32360, // 75.42(deg) 0.987551 + 32351, // 75.6(deg) 0.987300 + 32343, // 75.78(deg) 0.987051 + 32335, // 75.96(deg) 0.986801 + 32327, // 76.14(deg) 0.986553 + 32319, // 76.32(deg) 0.986305 + 32311, // 76.5(deg) 0.986058 + 32303, // 76.68(deg) 0.985813 + 32295, // 76.86(deg) 0.985568 + 32287, // 77.04(deg) 0.985324 + 32279, // 77.22(deg) 0.985082 + 32271, // 77.4(deg) 0.984841 + 32263, // 77.58(deg) 0.984601 + 32255, // 77.76(deg) 0.984363 + 32247, // 77.94(deg) 0.984127 + 32240, // 78.12(deg) 0.983892 + 32232, // 78.3(deg) 0.983659 + 32224, // 78.48(deg) 0.983427 + 32217, // 78.66(deg) 0.983198 + 32209, // 78.84(deg) 0.982971 + 32202, // 79.02(deg) 0.982745 + 32195, // 79.2(deg) 0.982522 + 32188, // 79.38(deg) 0.982301 + 32180, // 79.56(deg) 0.982082 + 32173, // 79.74(deg) 0.981866 + 32166, // 79.92(deg) 0.981652 + 32159, // 80.1(deg) 0.981440 + 32152, // 80.28(deg) 0.981231 + 32146, // 80.46(deg) 0.981025 + 32139, // 80.64(deg) 0.980821 + 32132, // 80.82(deg) 0.980620 + 32126, // 81(deg) 0.980422 + 32120, // 81.18(deg) 0.980227 + 32113, // 81.36(deg) 0.980035 + 32107, // 81.54(deg) 0.979845 + 32101, // 81.72(deg) 0.979659 + 32095, // 81.9(deg) 0.979476 + 32089, // 82.08(deg) 0.979296 + 32083, // 82.26(deg) 0.979120 + 32078, // 82.44(deg) 0.978946 + 32072, // 82.62(deg) 0.978776 + 32067, // 82.8(deg) 0.978609 + 32061, // 82.98(deg) 0.978446 + 32056, // 83.16(deg) 0.978286 + 32051, // 83.34(deg) 0.978130 + 32046, // 83.52(deg) 0.977978 + 32041, // 83.7(deg) 0.977829 + 32036, // 83.88(deg) 0.977683 + 32032, // 84.06(deg) 0.977542 + 32027, // 84.24(deg) 0.977404 + 32023, // 84.42(deg) 0.977270 + 32018, // 84.6(deg) 0.977140 + 32014, // 84.78(deg) 0.977014 + 32010, // 84.96(deg) 0.976891 + 32006, // 85.14(deg) 0.976773 + 32003, // 85.32(deg) 0.976659 + 31999, // 85.5(deg) 0.976548 + 31996, // 85.68(deg) 0.976442 + 31992, // 85.86(deg) 0.976340 + 31989, // 86.04(deg) 0.976242 + 31986, // 86.22(deg) 0.976148 + 31983, // 86.4(deg) 0.976058 + 31980, // 86.58(deg) 0.975973 + 31978, // 86.76(deg) 0.975891 + 31975, // 86.94(deg) 0.975814 + 31973, // 87.12(deg) 0.975742 + 31970, // 87.3(deg) 0.975673 + 31968, // 87.48(deg) 0.975609 + 31966, // 87.66(deg) 0.975549 + 31964, // 87.84(deg) 0.975494 + 31963, // 88.02(deg) 0.975443 + 31961, // 88.2(deg) 0.975396 + 31960, // 88.38(deg) 0.975354 + 31959, // 88.56(deg) 0.975316 + 31958, // 88.74(deg) 0.975283 + 31957, // 88.92(deg) 0.975254 + 31956, // 89.1(deg) 0.975229 + 31955, // 89.28(deg) 0.975209 + 31955, // 89.46(deg) 0.975194 + 31954, // 89.64(deg) 0.975182 + 31954, // 89.82(deg) 0.975176 + 31954, // 90(deg) 0.975174 + 31954, // 90.18(deg) 0.975176 + 31954, // 90.36(deg) 0.975182 + 31955, // 90.54(deg) 0.975194 + 31955, // 90.72(deg) 0.975209 + 31956, // 90.9(deg) 0.975229 + 31957, // 91.08(deg) 0.975254 + 31958, // 91.26(deg) 0.975283 + 31959, // 91.44(deg) 0.975316 + 31960, // 91.62(deg) 0.975354 + 31961, // 91.8(deg) 0.975396 + 31963, // 91.98(deg) 0.975443 + 31964, // 92.16(deg) 0.975494 + 31966, // 92.34(deg) 0.975549 + 31968, // 92.52(deg) 0.975609 + 31970, // 92.7(deg) 0.975673 + 31973, // 92.88(deg) 0.975742 + 31975, // 93.06(deg) 0.975814 + 31978, // 93.24(deg) 0.975891 + 31980, // 93.42(deg) 0.975973 + 31983, // 93.6(deg) 0.976058 + 31986, // 93.78(deg) 0.976148 + 31989, // 93.96(deg) 0.976242 + 31992, // 94.14(deg) 0.976340 + 31996, // 94.32(deg) 0.976442 + 31999, // 94.5(deg) 0.976548 + 32003, // 94.68(deg) 0.976659 + 32006, // 94.86(deg) 0.976773 + 32010, // 95.04(deg) 0.976891 + 32014, // 95.22(deg) 0.977014 + 32018, // 95.4(deg) 0.977140 + 32023, // 95.58(deg) 0.977270 + 32027, // 95.76(deg) 0.977404 + 32032, // 95.94(deg) 0.977542 + 32036, // 96.12(deg) 0.977683 + 32041, // 96.3(deg) 0.977829 + 32046, // 96.48(deg) 0.977978 + 32051, // 96.66(deg) 0.978130 + 32056, // 96.84(deg) 0.978286 + 32061, // 97.02(deg) 0.978446 + 32067, // 97.2(deg) 0.978609 + 32072, // 97.38(deg) 0.978776 + 32078, // 97.56(deg) 0.978946 + 32083, // 97.74(deg) 0.979120 + 32089, // 97.92(deg) 0.979296 + 32095, // 98.1(deg) 0.979476 + 32101, // 98.28(deg) 0.979659 + 32107, // 98.46(deg) 0.979845 + 32113, // 98.64(deg) 0.980035 + 32120, // 98.82(deg) 0.980227 + 32126, // 99(deg) 0.980422 + 32132, // 99.18(deg) 0.980620 + 32139, // 99.36(deg) 0.980821 + 32146, // 99.54(deg) 0.981025 + 32152, // 99.72(deg) 0.981231 + 32159, // 99.9(deg) 0.981440 + 32166, // 100.08(deg) 0.981652 + 32173, // 100.26(deg) 0.981866 + 32180, // 100.44(deg) 0.982082 + 32188, // 100.62(deg) 0.982301 + 32195, // 100.8(deg) 0.982522 + 32202, // 100.98(deg) 0.982745 + 32209, // 101.16(deg) 0.982971 + 32217, // 101.34(deg) 0.983198 + 32224, // 101.52(deg) 0.983427 + 32232, // 101.7(deg) 0.983659 + 32240, // 101.88(deg) 0.983892 + 32247, // 102.06(deg) 0.984127 + 32255, // 102.24(deg) 0.984363 + 32263, // 102.42(deg) 0.984601 + 32271, // 102.6(deg) 0.984841 + 32279, // 102.78(deg) 0.985082 + 32287, // 102.96(deg) 0.985324 + 32295, // 103.14(deg) 0.985568 + 32303, // 103.32(deg) 0.985813 + 32311, // 103.5(deg) 0.986058 + 32319, // 103.68(deg) 0.986305 + 32327, // 103.86(deg) 0.986553 + 32335, // 104.04(deg) 0.986801 + 32343, // 104.22(deg) 0.987051 + 32351, // 104.4(deg) 0.987300 + 32360, // 104.58(deg) 0.987551 + 32368, // 104.76(deg) 0.987802 + 32376, // 104.94(deg) 0.988053 + 32384, // 105.12(deg) 0.988304 + 32392, // 105.3(deg) 0.988556 + 32401, // 105.48(deg) 0.988807 + 32409, // 105.66(deg) 0.989059 + 32417, // 105.84(deg) 0.989310 + 32425, // 106.02(deg) 0.989561 + 32434, // 106.2(deg) 0.989812 + 32442, // 106.38(deg) 0.990062 + 32450, // 106.56(deg) 0.990312 + 32458, // 106.74(deg) 0.990561 + 32466, // 106.92(deg) 0.990810 + 32474, // 107.1(deg) 0.991057 + 32483, // 107.28(deg) 0.991304 + 32491, // 107.46(deg) 0.991549 + 32499, // 107.64(deg) 0.991793 + 32507, // 107.82(deg) 0.992036 + 32514, // 108(deg) 0.992278 + 32522, // 108.18(deg) 0.992518 + 32530, // 108.36(deg) 0.992756 + 32538, // 108.54(deg) 0.992993 + 32546, // 108.72(deg) 0.993228 + 32553, // 108.9(deg) 0.993461 + 32561, // 109.08(deg) 0.993692 + 32568, // 109.26(deg) 0.993920 + 32576, // 109.44(deg) 0.994147 + 32583, // 109.62(deg) 0.994371 + 32590, // 109.8(deg) 0.994592 + 32597, // 109.98(deg) 0.994811 + 32605, // 110.16(deg) 0.995027 + 32612, // 110.34(deg) 0.995240 + 32618, // 110.52(deg) 0.995450 + 32625, // 110.7(deg) 0.995657 + 32632, // 110.88(deg) 0.995861 + 32638, // 111.06(deg) 0.996061 + 32645, // 111.24(deg) 0.996258 + 32651, // 111.42(deg) 0.996452 + 32657, // 111.6(deg) 0.996641 + 32664, // 111.78(deg) 0.996827 + 32669, // 111.96(deg) 0.997009 + 32675, // 112.14(deg) 0.997187 + 32681, // 112.32(deg) 0.997360 + 32687, // 112.5(deg) 0.997530 + 32692, // 112.68(deg) 0.997694 + 32697, // 112.86(deg) 0.997855 + 32702, // 113.04(deg) 0.998010 + 32707, // 113.22(deg) 0.998161 + 32712, // 113.4(deg) 0.998307 + 32717, // 113.58(deg) 0.998447 + 32721, // 113.76(deg) 0.998583 + 32725, // 113.94(deg) 0.998713 + 32729, // 114.12(deg) 0.998837 + 32733, // 114.3(deg) 0.998957 + 32737, // 114.48(deg) 0.999070 + 32741, // 114.66(deg) 0.999177 + 32744, // 114.84(deg) 0.999279 + 32747, // 115.02(deg) 0.999374 + 32750, // 115.2(deg) 0.999464 + 32753, // 115.38(deg) 0.999546 + 32755, // 115.56(deg) 0.999623 + 32757, // 115.74(deg) 0.999693 + 32759, // 115.92(deg) 0.999756 + 32761, // 116.1(deg) 0.999812 + 32763, // 116.28(deg) 0.999861 + 32764, // 116.46(deg) 0.999903 + 32765, // 116.64(deg) 0.999937 + 32766, // 116.82(deg) 0.999965 + 32767, // 117(deg) 0.999984 + 32767, // 117.18(deg) 0.999996 + 32767, // 117.36(deg) 1.000001 + 32767, // 117.54(deg) 0.999997 + 32767, // 117.72(deg) 0.999985 + 32766, // 117.9(deg) 0.999966 + 32765, // 118.08(deg) 0.999937 + 32764, // 118.26(deg) 0.999901 + 32763, // 118.44(deg) 0.999855 + 32761, // 118.62(deg) 0.999801 + 32759, // 118.8(deg) 0.999739 + 32757, // 118.98(deg) 0.999667 + 32754, // 119.16(deg) 0.999586 + 32751, // 119.34(deg) 0.999496 + 32748, // 119.52(deg) 0.999396 + 32744, // 119.7(deg) 0.999287 + 32740, // 119.88(deg) 0.999168 + 32736, // 120.06(deg) 0.999040 + 32732, // 120.24(deg) 0.998902 + 32727, // 120.42(deg) 0.998753 + 32721, // 120.6(deg) 0.998595 + 32716, // 120.78(deg) 0.998426 + 32710, // 120.96(deg) 0.998246 + 32704, // 121.14(deg) 0.998057 + 32697, // 121.32(deg) 0.997856 + 32690, // 121.5(deg) 0.997645 + 32683, // 121.68(deg) 0.997422 + 32675, // 121.86(deg) 0.997189 + 32667, // 122.04(deg) 0.996944 + 32659, // 122.22(deg) 0.996688 + 32650, // 122.4(deg) 0.996421 + 32641, // 122.58(deg) 0.996142 + 32632, // 122.76(deg) 0.995851 + 32622, // 122.94(deg) 0.995548 + 32611, // 123.12(deg) 0.995234 + 32601, // 123.3(deg) 0.994907 + 32590, // 123.48(deg) 0.994568 + 32578, // 123.66(deg) 0.994217 + 32566, // 123.84(deg) 0.993853 + 32554, // 124.02(deg) 0.993476 + 32541, // 124.2(deg) 0.993087 + 32528, // 124.38(deg) 0.992685 + 32514, // 124.56(deg) 0.992270 + 32500, // 124.74(deg) 0.991842 + 32486, // 124.92(deg) 0.991400 + 32471, // 125.1(deg) 0.990946 + 32455, // 125.28(deg) 0.990477 + 32440, // 125.46(deg) 0.989995 + 32423, // 125.64(deg) 0.989500 + 32407, // 125.82(deg) 0.988990 + 32390, // 126(deg) 0.988467 + 32372, // 126.18(deg) 0.987929 + 32354, // 126.36(deg) 0.987377 + 32335, // 126.54(deg) 0.986811 + 32316, // 126.72(deg) 0.986230 + 32297, // 126.9(deg) 0.985635 + 32277, // 127.08(deg) 0.985025 + 32256, // 127.26(deg) 0.984400 + 32235, // 127.44(deg) 0.983760 + 32214, // 127.62(deg) 0.983105 + 32192, // 127.8(deg) 0.982435 + 32169, // 127.98(deg) 0.981750 + 32147, // 128.16(deg) 0.981049 + 32123, // 128.34(deg) 0.980333 + 32099, // 128.52(deg) 0.979601 + 32075, // 128.7(deg) 0.978853 + 32050, // 128.88(deg) 0.978090 + 32024, // 129.06(deg) 0.977310 + 31998, // 129.24(deg) 0.976515 + 31971, // 129.42(deg) 0.975703 + 31944, // 129.6(deg) 0.974875 + 31917, // 129.78(deg) 0.974031 + 31888, // 129.96(deg) 0.973170 + 31860, // 130.14(deg) 0.972292 + 31830, // 130.32(deg) 0.971398 + 31800, // 130.5(deg) 0.970487 + 31770, // 130.68(deg) 0.969559 + 31739, // 130.86(deg) 0.968613 + 31707, // 131.04(deg) 0.967651 + 31675, // 131.22(deg) 0.966672 + 31643, // 131.4(deg) 0.965675 + 31609, // 131.58(deg) 0.964660 + 31576, // 131.76(deg) 0.963628 + 31541, // 131.94(deg) 0.962579 + 31506, // 132.12(deg) 0.961512 + 31471, // 132.3(deg) 0.960426 + 31435, // 132.48(deg) 0.959323 + 31398, // 132.66(deg) 0.958202 + 31361, // 132.84(deg) 0.957063 + 31323, // 133.02(deg) 0.955906 + 31284, // 133.2(deg) 0.954730 + 31245, // 133.38(deg) 0.953536 + 31205, // 133.56(deg) 0.952323 + 31165, // 133.74(deg) 0.951092 + 31124, // 133.92(deg) 0.949842 + 31082, // 134.1(deg) 0.948573 + 31040, // 134.28(deg) 0.947286 + 30997, // 134.46(deg) 0.945979 + 30954, // 134.64(deg) 0.944654 + 30910, // 134.82(deg) 0.943309 + 30865, // 135(deg) 0.941945 + 30820, // 135.18(deg) 0.940562 + 30774, // 135.36(deg) 0.939160 + 30727, // 135.54(deg) 0.937738 + 30680, // 135.72(deg) 0.936297 + 30632, // 135.9(deg) 0.934836 + 30584, // 136.08(deg) 0.933356 + 30535, // 136.26(deg) 0.931855 + 30485, // 136.44(deg) 0.930335 + 30434, // 136.62(deg) 0.928795 + 30383, // 136.8(deg) 0.927236 + 30331, // 136.98(deg) 0.925656 + 30279, // 137.16(deg) 0.924056 + 30226, // 137.34(deg) 0.922436 + 30172, // 137.52(deg) 0.920796 + 30118, // 137.7(deg) 0.919135 + 30063, // 137.88(deg) 0.917454 + 30007, // 138.06(deg) 0.915753 + 29950, // 138.24(deg) 0.914031 + 29893, // 138.42(deg) 0.912289 + 29836, // 138.6(deg) 0.910526 + 29777, // 138.78(deg) 0.908742 + 29718, // 138.96(deg) 0.906938 + 29658, // 139.14(deg) 0.905113 + 29598, // 139.32(deg) 0.903268 + 29537, // 139.5(deg) 0.901401 + 29475, // 139.68(deg) 0.899513 + 29412, // 139.86(deg) 0.897605 + 29349, // 140.04(deg) 0.895675 + 29285, // 140.22(deg) 0.893725 + 29220, // 140.4(deg) 0.891753 + 29155, // 140.58(deg) 0.889760 + 29089, // 140.76(deg) 0.887746 + 29022, // 140.94(deg) 0.885711 + 28955, // 141.12(deg) 0.883655 + 28887, // 141.3(deg) 0.881577 + 28818, // 141.48(deg) 0.879478 + 28749, // 141.66(deg) 0.877357 + 28679, // 141.84(deg) 0.875215 + 28608, // 142.02(deg) 0.873052 + 28536, // 142.2(deg) 0.870867 + 28464, // 142.38(deg) 0.868660 + 28391, // 142.56(deg) 0.866432 + 28317, // 142.74(deg) 0.864182 + 28243, // 142.92(deg) 0.861911 + 28167, // 143.1(deg) 0.859618 + 28092, // 143.28(deg) 0.857304 + 28015, // 143.46(deg) 0.854967 + 27938, // 143.64(deg) 0.852610 + 27860, // 143.82(deg) 0.850230 + 27781, // 144(deg) 0.847828 + 27702, // 144.18(deg) 0.845405 + 27622, // 144.36(deg) 0.842960 + 27541, // 144.54(deg) 0.840493 + 27459, // 144.72(deg) 0.838005 + 27377, // 144.9(deg) 0.835494 + 27294, // 145.08(deg) 0.832962 + 27210, // 145.26(deg) 0.830408 + 27126, // 145.44(deg) 0.827832 + 27041, // 145.62(deg) 0.825234 + 26955, // 145.8(deg) 0.822614 + 26868, // 145.98(deg) 0.819973 + 26781, // 146.16(deg) 0.817309 + 26693, // 146.34(deg) 0.814624 + 26604, // 146.52(deg) 0.811917 + 26515, // 146.7(deg) 0.809188 + 26425, // 146.88(deg) 0.806437 + 26334, // 147.06(deg) 0.803664 + 26242, // 147.24(deg) 0.800869 + 26150, // 147.42(deg) 0.798053 + 26057, // 147.6(deg) 0.795214 + 25963, // 147.78(deg) 0.792354 + 25869, // 147.96(deg) 0.789472 + 25774, // 148.14(deg) 0.786569 + 25678, // 148.32(deg) 0.783643 + 25581, // 148.5(deg) 0.780696 + 25484, // 148.68(deg) 0.777727 + 25386, // 148.86(deg) 0.774736 + 25287, // 149.04(deg) 0.771723 + 25188, // 149.22(deg) 0.768689 + 25088, // 149.4(deg) 0.765633 + 24987, // 149.58(deg) 0.762555 + 24885, // 149.76(deg) 0.759456 + 24783, // 149.94(deg) 0.756336 + 24680, // 150.12(deg) 0.753193 + 24576, // 150.3(deg) 0.750029 + 24472, // 150.48(deg) 0.746844 + 24367, // 150.66(deg) 0.743637 + 24261, // 150.84(deg) 0.740409 + 24155, // 151.02(deg) 0.737159 + 24048, // 151.2(deg) 0.733889 + 23940, // 151.38(deg) 0.730596 + 23831, // 151.56(deg) 0.727283 + 23722, // 151.74(deg) 0.723948 + 23612, // 151.92(deg) 0.720592 + 23501, // 152.1(deg) 0.717215 + 23390, // 152.28(deg) 0.713817 + 23278, // 152.46(deg) 0.710398 + 23165, // 152.64(deg) 0.706958 + 23052, // 152.82(deg) 0.703497 + 22938, // 153(deg) 0.700015 + 22823, // 153.18(deg) 0.696512 + 22707, // 153.36(deg) 0.692988 + 22591, // 153.54(deg) 0.689444 + 22474, // 153.72(deg) 0.685879 + 22357, // 153.9(deg) 0.682294 + 22239, // 154.08(deg) 0.678688 + 22120, // 154.26(deg) 0.675061 + 22000, // 154.44(deg) 0.671414 + 21880, // 154.62(deg) 0.667747 + 21759, // 154.8(deg) 0.664059 + 21638, // 154.98(deg) 0.660352 + 21516, // 155.16(deg) 0.656624 + 21393, // 155.34(deg) 0.652876 + 21269, // 155.52(deg) 0.649108 + 21145, // 155.7(deg) 0.645320 + 21021, // 155.88(deg) 0.641512 + 20895, // 156.06(deg) 0.637685 + 20769, // 156.24(deg) 0.633838 + 20642, // 156.42(deg) 0.629971 + 20515, // 156.6(deg) 0.626085 + 20387, // 156.78(deg) 0.622179 + 20258, // 156.96(deg) 0.618254 + 20129, // 157.14(deg) 0.614310 + 19999, // 157.32(deg) 0.610346 + 19869, // 157.5(deg) 0.606364 + 19738, // 157.68(deg) 0.602362 + 19606, // 157.86(deg) 0.598342 + 19474, // 158.04(deg) 0.594303 + 19341, // 158.22(deg) 0.590245 + 19207, // 158.4(deg) 0.586168 + 19073, // 158.58(deg) 0.582073 + 18938, // 158.76(deg) 0.577959 + 18803, // 158.94(deg) 0.573827 + 18667, // 159.12(deg) 0.569677 + 18530, // 159.3(deg) 0.565509 + 18393, // 159.48(deg) 0.561322 + 18255, // 159.66(deg) 0.557118 + 18117, // 159.84(deg) 0.552896 + 17978, // 160.02(deg) 0.548656 + 17838, // 160.2(deg) 0.544398 + 17698, // 160.38(deg) 0.540123 + 17558, // 160.56(deg) 0.535831 + 17416, // 160.74(deg) 0.531521 + 17275, // 160.92(deg) 0.527195 + 17132, // 161.1(deg) 0.522851 + 16989, // 161.28(deg) 0.518490 + 16846, // 161.46(deg) 0.514112 + 16702, // 161.64(deg) 0.509718 + 16557, // 161.82(deg) 0.505307 + 16412, // 162(deg) 0.500880 + 16267, // 162.18(deg) 0.496436 + 16121, // 162.36(deg) 0.491976 + 15974, // 162.54(deg) 0.487500 + 15827, // 162.72(deg) 0.483008 + 15679, // 162.9(deg) 0.478500 + 15531, // 163.08(deg) 0.473977 + 15382, // 163.26(deg) 0.469437 + 15233, // 163.44(deg) 0.464883 + 15083, // 163.62(deg) 0.460313 + 14933, // 163.8(deg) 0.455728 + 14782, // 163.98(deg) 0.451127 + 14631, // 164.16(deg) 0.446512 + 14479, // 164.34(deg) 0.441882 + 14327, // 164.52(deg) 0.437238 + 14174, // 164.7(deg) 0.432579 + 14021, // 164.88(deg) 0.427905 + 13867, // 165.06(deg) 0.423217 + 13713, // 165.24(deg) 0.418515 + 13559, // 165.42(deg) 0.413799 + 13404, // 165.6(deg) 0.409070 + 13248, // 165.78(deg) 0.404326 + 13093, // 165.96(deg) 0.399569 + 12936, // 166.14(deg) 0.394799 + 12780, // 166.32(deg) 0.390016 + 12622, // 166.5(deg) 0.385219 + 12465, // 166.68(deg) 0.380409 + 12307, // 166.86(deg) 0.375587 + 12148, // 167.04(deg) 0.370752 + 11989, // 167.22(deg) 0.365904 + 11830, // 167.4(deg) 0.361044 + 11671, // 167.58(deg) 0.356172 + 11511, // 167.76(deg) 0.351288 + 11350, // 167.94(deg) 0.346392 + 11189, // 168.12(deg) 0.341484 + 11028, // 168.3(deg) 0.336565 + 10866, // 168.48(deg) 0.331634 + 10705, // 168.66(deg) 0.326692 + 10542, // 168.84(deg) 0.321739 + 10380, // 169.02(deg) 0.316775 + 10217, // 169.2(deg) 0.311800 + 10053, // 169.38(deg) 0.306814 + 9889, // 169.56(deg) 0.301818 + 9725, // 169.74(deg) 0.296812 + 9561, // 169.92(deg) 0.291795 + 9396, // 170.1(deg) 0.286769 + 9231, // 170.28(deg) 0.281733 + 9066, // 170.46(deg) 0.276687 + 8900, // 170.64(deg) 0.271631 + 8734, // 170.82(deg) 0.266567 + 8568, // 171(deg) 0.261493 + 8402, // 171.18(deg) 0.256410 + 8235, // 171.36(deg) 0.251318 + 8068, // 171.54(deg) 0.246218 + 7900, // 171.72(deg) 0.241109 + 7732, // 171.9(deg) 0.235992 + 7565, // 172.08(deg) 0.230867 + 7396, // 172.26(deg) 0.225734 + 7228, // 172.44(deg) 0.220593 + 7059, // 172.62(deg) 0.215445 + 6890, // 172.8(deg) 0.210289 + 6721, // 172.98(deg) 0.205125 + 6552, // 173.16(deg) 0.199955 + 6382, // 173.34(deg) 0.194778 + 6212, // 173.52(deg) 0.189594 + 6042, // 173.7(deg) 0.184403 + 5872, // 173.88(deg) 0.179207 + 5701, // 174.06(deg) 0.174003 + 5531, // 174.24(deg) 0.168794 + 5360, // 174.42(deg) 0.163579 + 5189, // 174.6(deg) 0.158359 + 5017, // 174.78(deg) 0.153133 + 4846, // 174.96(deg) 0.147901 + 4674, // 175.14(deg) 0.142664 + 4503, // 175.32(deg) 0.137423 + 4331, // 175.5(deg) 0.132177 + 4159, // 175.68(deg) 0.126926 + 3986, // 175.86(deg) 0.121670 + 3814, // 176.04(deg) 0.116411 + 3642, // 176.22(deg) 0.111147 + 3469, // 176.4(deg) 0.105880 + 3296, // 176.58(deg) 0.100608 + 3123, // 176.76(deg) 0.095334 + 2950, // 176.94(deg) 0.090056 + 2777, // 177.12(deg) 0.084775 + 2604, // 177.3(deg) 0.079491 + 2431, // 177.48(deg) 0.074204 + 2258, // 177.66(deg) 0.068914 + 2084, // 177.84(deg) 0.063622 + 1911, // 178.02(deg) 0.058328 + 1737, // 178.2(deg) 0.053032 + 1564, // 178.38(deg) 0.047734 + 1390, // 178.56(deg) 0.042435 + 1216, // 178.74(deg) 0.037134 + 1043, // 178.92(deg) 0.031831 + 869, // 179.1(deg) 0.026528 + 695, // 179.28(deg) 0.021223 + 521, // 179.46(deg) 0.015918 + 347, // 179.64(deg) 0.010612 + 173, // 179.82(deg) 0.005306 + 0, // 180(deg) 0.000000 + -173, // 180.18(deg) -0.005306 + -347, // 180.36(deg) -0.010612 + -521, // 180.54(deg) -0.015918 + -695, // 180.72(deg) -0.021223 + -869, // 180.9(deg) -0.026528 + -1043, // 181.08(deg) -0.031831 + -1216, // 181.26(deg) -0.037134 + -1390, // 181.44(deg) -0.042435 + -1564, // 181.62(deg) -0.047734 + -1737, // 181.8(deg) -0.053032 + -1911, // 181.98(deg) -0.058328 + -2084, // 182.16(deg) -0.063622 + -2258, // 182.34(deg) -0.068914 + -2431, // 182.52(deg) -0.074204 + -2604, // 182.7(deg) -0.079491 + -2777, // 182.88(deg) -0.084775 + -2950, // 183.06(deg) -0.090056 + -3123, // 183.24(deg) -0.095334 + -3296, // 183.42(deg) -0.100608 + -3469, // 183.6(deg) -0.105880 + -3642, // 183.78(deg) -0.111147 + -3814, // 183.96(deg) -0.116411 + -3986, // 184.14(deg) -0.121670 + -4159, // 184.32(deg) -0.126926 + -4331, // 184.5(deg) -0.132177 + -4503, // 184.68(deg) -0.137423 + -4674, // 184.86(deg) -0.142664 + -4846, // 185.04(deg) -0.147901 + -5017, // 185.22(deg) -0.153133 + -5189, // 185.4(deg) -0.158359 + -5360, // 185.58(deg) -0.163579 + -5531, // 185.76(deg) -0.168794 + -5701, // 185.94(deg) -0.174003 + -5872, // 186.12(deg) -0.179207 + -6042, // 186.3(deg) -0.184403 + -6212, // 186.48(deg) -0.189594 + -6382, // 186.66(deg) -0.194778 + -6552, // 186.84(deg) -0.199955 + -6721, // 187.02(deg) -0.205125 + -6890, // 187.2(deg) -0.210289 + -7059, // 187.38(deg) -0.215445 + -7228, // 187.56(deg) -0.220593 + -7396, // 187.74(deg) -0.225734 + -7565, // 187.92(deg) -0.230867 + -7732, // 188.1(deg) -0.235992 + -7900, // 188.28(deg) -0.241109 + -8068, // 188.46(deg) -0.246218 + -8235, // 188.64(deg) -0.251318 + -8402, // 188.82(deg) -0.256410 + -8568, // 189(deg) -0.261493 + -8734, // 189.18(deg) -0.266567 + -8900, // 189.36(deg) -0.271631 + -9066, // 189.54(deg) -0.276687 + -9231, // 189.72(deg) -0.281733 + -9396, // 189.9(deg) -0.286769 + -9561, // 190.08(deg) -0.291795 + -9725, // 190.26(deg) -0.296812 + -9889, // 190.44(deg) -0.301818 + -10053, // 190.62(deg) -0.306814 + -10217, // 190.8(deg) -0.311800 + -10380, // 190.98(deg) -0.316775 + -10542, // 191.16(deg) -0.321739 + -10705, // 191.34(deg) -0.326692 + -10866, // 191.52(deg) -0.331634 + -11028, // 191.7(deg) -0.336565 + -11189, // 191.88(deg) -0.341484 + -11350, // 192.06(deg) -0.346392 + -11511, // 192.24(deg) -0.351288 + -11671, // 192.42(deg) -0.356172 + -11830, // 192.6(deg) -0.361044 + -11989, // 192.78(deg) -0.365904 + -12148, // 192.96(deg) -0.370752 + -12307, // 193.14(deg) -0.375587 + -12465, // 193.32(deg) -0.380409 + -12622, // 193.5(deg) -0.385219 + -12780, // 193.68(deg) -0.390016 + -12936, // 193.86(deg) -0.394799 + -13093, // 194.04(deg) -0.399569 + -13248, // 194.22(deg) -0.404326 + -13404, // 194.4(deg) -0.409070 + -13559, // 194.58(deg) -0.413799 + -13713, // 194.76(deg) -0.418515 + -13867, // 194.94(deg) -0.423217 + -14021, // 195.12(deg) -0.427905 + -14174, // 195.3(deg) -0.432579 + -14327, // 195.48(deg) -0.437238 + -14479, // 195.66(deg) -0.441882 + -14631, // 195.84(deg) -0.446512 + -14782, // 196.02(deg) -0.451127 + -14933, // 196.2(deg) -0.455728 + -15083, // 196.38(deg) -0.460313 + -15233, // 196.56(deg) -0.464883 + -15382, // 196.74(deg) -0.469437 + -15531, // 196.92(deg) -0.473977 + -15679, // 197.1(deg) -0.478500 + -15827, // 197.28(deg) -0.483008 + -15974, // 197.46(deg) -0.487500 + -16121, // 197.64(deg) -0.491976 + -16267, // 197.82(deg) -0.496436 + -16412, // 198(deg) -0.500880 + -16557, // 198.18(deg) -0.505307 + -16702, // 198.36(deg) -0.509718 + -16846, // 198.54(deg) -0.514112 + -16989, // 198.72(deg) -0.518490 + -17132, // 198.9(deg) -0.522851 + -17275, // 199.08(deg) -0.527195 + -17416, // 199.26(deg) -0.531521 + -17558, // 199.44(deg) -0.535831 + -17698, // 199.62(deg) -0.540123 + -17838, // 199.8(deg) -0.544398 + -17978, // 199.98(deg) -0.548656 + -18117, // 200.16(deg) -0.552896 + -18255, // 200.34(deg) -0.557118 + -18393, // 200.52(deg) -0.561322 + -18530, // 200.7(deg) -0.565509 + -18667, // 200.88(deg) -0.569677 + -18803, // 201.06(deg) -0.573827 + -18938, // 201.24(deg) -0.577959 + -19073, // 201.42(deg) -0.582073 + -19207, // 201.6(deg) -0.586168 + -19341, // 201.78(deg) -0.590245 + -19474, // 201.96(deg) -0.594303 + -19606, // 202.14(deg) -0.598342 + -19738, // 202.32(deg) -0.602362 + -19869, // 202.5(deg) -0.606364 + -19999, // 202.68(deg) -0.610346 + -20129, // 202.86(deg) -0.614310 + -20258, // 203.04(deg) -0.618254 + -20387, // 203.22(deg) -0.622179 + -20515, // 203.4(deg) -0.626085 + -20642, // 203.58(deg) -0.629971 + -20769, // 203.76(deg) -0.633838 + -20895, // 203.94(deg) -0.637685 + -21021, // 204.12(deg) -0.641512 + -21145, // 204.3(deg) -0.645320 + -21269, // 204.48(deg) -0.649108 + -21393, // 204.66(deg) -0.652876 + -21516, // 204.84(deg) -0.656624 + -21638, // 205.02(deg) -0.660352 + -21759, // 205.2(deg) -0.664059 + -21880, // 205.38(deg) -0.667747 + -22000, // 205.56(deg) -0.671414 + -22120, // 205.74(deg) -0.675061 + -22239, // 205.92(deg) -0.678688 + -22357, // 206.1(deg) -0.682294 + -22474, // 206.28(deg) -0.685879 + -22591, // 206.46(deg) -0.689444 + -22707, // 206.64(deg) -0.692988 + -22823, // 206.82(deg) -0.696512 + -22938, // 207(deg) -0.700015 + -23052, // 207.18(deg) -0.703497 + -23165, // 207.36(deg) -0.706958 + -23278, // 207.54(deg) -0.710398 + -23390, // 207.72(deg) -0.713817 + -23501, // 207.9(deg) -0.717215 + -23612, // 208.08(deg) -0.720592 + -23722, // 208.26(deg) -0.723948 + -23831, // 208.44(deg) -0.727283 + -23940, // 208.62(deg) -0.730596 + -24048, // 208.8(deg) -0.733889 + -24155, // 208.98(deg) -0.737159 + -24261, // 209.16(deg) -0.740409 + -24367, // 209.34(deg) -0.743637 + -24472, // 209.52(deg) -0.746844 + -24576, // 209.7(deg) -0.750029 + -24680, // 209.88(deg) -0.753193 + -24783, // 210.06(deg) -0.756336 + -24885, // 210.24(deg) -0.759456 + -24987, // 210.42(deg) -0.762555 + -25088, // 210.6(deg) -0.765633 + -25188, // 210.78(deg) -0.768689 + -25287, // 210.96(deg) -0.771723 + -25386, // 211.14(deg) -0.774736 + -25484, // 211.32(deg) -0.777727 + -25581, // 211.5(deg) -0.780696 + -25678, // 211.68(deg) -0.783643 + -25774, // 211.86(deg) -0.786569 + -25869, // 212.04(deg) -0.789472 + -25963, // 212.22(deg) -0.792354 + -26057, // 212.4(deg) -0.795214 + -26150, // 212.58(deg) -0.798053 + -26242, // 212.76(deg) -0.800869 + -26334, // 212.94(deg) -0.803664 + -26425, // 213.12(deg) -0.806437 + -26515, // 213.3(deg) -0.809188 + -26604, // 213.48(deg) -0.811917 + -26693, // 213.66(deg) -0.814624 + -26781, // 213.84(deg) -0.817309 + -26868, // 214.02(deg) -0.819973 + -26955, // 214.2(deg) -0.822614 + -27041, // 214.38(deg) -0.825234 + -27126, // 214.56(deg) -0.827832 + -27210, // 214.74(deg) -0.830408 + -27294, // 214.92(deg) -0.832962 + -27377, // 215.1(deg) -0.835494 + -27459, // 215.28(deg) -0.838005 + -27541, // 215.46(deg) -0.840493 + -27622, // 215.64(deg) -0.842960 + -27702, // 215.82(deg) -0.845405 + -27781, // 216(deg) -0.847828 + -27860, // 216.18(deg) -0.850230 + -27938, // 216.36(deg) -0.852610 + -28015, // 216.54(deg) -0.854967 + -28092, // 216.72(deg) -0.857304 + -28167, // 216.9(deg) -0.859618 + -28243, // 217.08(deg) -0.861911 + -28317, // 217.26(deg) -0.864182 + -28391, // 217.44(deg) -0.866432 + -28464, // 217.62(deg) -0.868660 + -28536, // 217.8(deg) -0.870867 + -28608, // 217.98(deg) -0.873052 + -28679, // 218.16(deg) -0.875215 + -28749, // 218.34(deg) -0.877357 + -28818, // 218.52(deg) -0.879478 + -28887, // 218.7(deg) -0.881577 + -28955, // 218.88(deg) -0.883655 + -29022, // 219.06(deg) -0.885711 + -29089, // 219.24(deg) -0.887746 + -29155, // 219.42(deg) -0.889760 + -29220, // 219.6(deg) -0.891753 + -29285, // 219.78(deg) -0.893725 + -29349, // 219.96(deg) -0.895675 + -29412, // 220.14(deg) -0.897605 + -29475, // 220.32(deg) -0.899513 + -29537, // 220.5(deg) -0.901401 + -29598, // 220.68(deg) -0.903268 + -29658, // 220.86(deg) -0.905113 + -29718, // 221.04(deg) -0.906938 + -29777, // 221.22(deg) -0.908742 + -29836, // 221.4(deg) -0.910526 + -29893, // 221.58(deg) -0.912289 + -29950, // 221.76(deg) -0.914031 + -30007, // 221.94(deg) -0.915753 + -30063, // 222.12(deg) -0.917454 + -30118, // 222.3(deg) -0.919135 + -30172, // 222.48(deg) -0.920796 + -30226, // 222.66(deg) -0.922436 + -30279, // 222.84(deg) -0.924056 + -30331, // 223.02(deg) -0.925656 + -30383, // 223.2(deg) -0.927236 + -30434, // 223.38(deg) -0.928795 + -30485, // 223.56(deg) -0.930335 + -30535, // 223.74(deg) -0.931855 + -30584, // 223.92(deg) -0.933356 + -30632, // 224.1(deg) -0.934836 + -30680, // 224.28(deg) -0.936297 + -30727, // 224.46(deg) -0.937738 + -30774, // 224.64(deg) -0.939160 + -30820, // 224.82(deg) -0.940562 + -30865, // 225(deg) -0.941945 + -30910, // 225.18(deg) -0.943309 + -30954, // 225.36(deg) -0.944654 + -30997, // 225.54(deg) -0.945979 + -31040, // 225.72(deg) -0.947286 + -31082, // 225.9(deg) -0.948573 + -31124, // 226.08(deg) -0.949842 + -31165, // 226.26(deg) -0.951092 + -31205, // 226.44(deg) -0.952323 + -31245, // 226.62(deg) -0.953536 + -31284, // 226.8(deg) -0.954730 + -31323, // 226.98(deg) -0.955906 + -31361, // 227.16(deg) -0.957063 + -31398, // 227.34(deg) -0.958202 + -31435, // 227.52(deg) -0.959323 + -31471, // 227.7(deg) -0.960426 + -31506, // 227.88(deg) -0.961512 + -31541, // 228.06(deg) -0.962579 + -31576, // 228.24(deg) -0.963628 + -31609, // 228.42(deg) -0.964660 + -31643, // 228.6(deg) -0.965675 + -31675, // 228.78(deg) -0.966672 + -31707, // 228.96(deg) -0.967651 + -31739, // 229.14(deg) -0.968613 + -31770, // 229.32(deg) -0.969559 + -31800, // 229.5(deg) -0.970487 + -31830, // 229.68(deg) -0.971398 + -31860, // 229.86(deg) -0.972292 + -31888, // 230.04(deg) -0.973170 + -31917, // 230.22(deg) -0.974031 + -31944, // 230.4(deg) -0.974875 + -31971, // 230.58(deg) -0.975703 + -31998, // 230.76(deg) -0.976515 + -32024, // 230.94(deg) -0.977310 + -32050, // 231.12(deg) -0.978090 + -32075, // 231.3(deg) -0.978853 + -32099, // 231.48(deg) -0.979601 + -32123, // 231.66(deg) -0.980333 + -32147, // 231.84(deg) -0.981049 + -32169, // 232.02(deg) -0.981750 + -32192, // 232.2(deg) -0.982435 + -32214, // 232.38(deg) -0.983105 + -32235, // 232.56(deg) -0.983760 + -32256, // 232.74(deg) -0.984400 + -32277, // 232.92(deg) -0.985025 + -32297, // 233.1(deg) -0.985635 + -32316, // 233.28(deg) -0.986230 + -32335, // 233.46(deg) -0.986811 + -32354, // 233.64(deg) -0.987377 + -32372, // 233.82(deg) -0.987929 + -32390, // 234(deg) -0.988467 + -32407, // 234.18(deg) -0.988990 + -32423, // 234.36(deg) -0.989500 + -32440, // 234.54(deg) -0.989995 + -32455, // 234.72(deg) -0.990477 + -32471, // 234.9(deg) -0.990946 + -32486, // 235.08(deg) -0.991400 + -32500, // 235.26(deg) -0.991842 + -32514, // 235.44(deg) -0.992270 + -32528, // 235.62(deg) -0.992685 + -32541, // 235.8(deg) -0.993087 + -32554, // 235.98(deg) -0.993476 + -32566, // 236.16(deg) -0.993853 + -32578, // 236.34(deg) -0.994217 + -32590, // 236.52(deg) -0.994568 + -32601, // 236.7(deg) -0.994907 + -32611, // 236.88(deg) -0.995234 + -32622, // 237.06(deg) -0.995548 + -32632, // 237.24(deg) -0.995851 + -32641, // 237.42(deg) -0.996142 + -32650, // 237.6(deg) -0.996421 + -32659, // 237.78(deg) -0.996688 + -32667, // 237.96(deg) -0.996944 + -32675, // 238.14(deg) -0.997189 + -32683, // 238.32(deg) -0.997422 + -32690, // 238.5(deg) -0.997645 + -32697, // 238.68(deg) -0.997856 + -32704, // 238.86(deg) -0.998057 + -32710, // 239.04(deg) -0.998246 + -32716, // 239.22(deg) -0.998426 + -32721, // 239.4(deg) -0.998595 + -32727, // 239.58(deg) -0.998753 + -32732, // 239.76(deg) -0.998902 + -32736, // 239.94(deg) -0.999040 + -32740, // 240.12(deg) -0.999168 + -32744, // 240.3(deg) -0.999287 + -32748, // 240.48(deg) -0.999396 + -32751, // 240.66(deg) -0.999496 + -32754, // 240.84(deg) -0.999586 + -32757, // 241.02(deg) -0.999667 + -32759, // 241.2(deg) -0.999739 + -32761, // 241.38(deg) -0.999801 + -32763, // 241.56(deg) -0.999855 + -32764, // 241.74(deg) -0.999901 + -32765, // 241.92(deg) -0.999937 + -32766, // 242.1(deg) -0.999966 + -32767, // 242.28(deg) -0.999985 + -32767, // 242.46(deg) -0.999997 + -32768, // 242.64(deg) -1.000001 + -32767, // 242.82(deg) -0.999996 + -32767, // 243(deg) -0.999984 + -32766, // 243.18(deg) -0.999965 + -32765, // 243.36(deg) -0.999937 + -32764, // 243.54(deg) -0.999903 + -32763, // 243.72(deg) -0.999861 + -32761, // 243.9(deg) -0.999812 + -32759, // 244.08(deg) -0.999756 + -32757, // 244.26(deg) -0.999693 + -32755, // 244.44(deg) -0.999623 + -32753, // 244.62(deg) -0.999546 + -32750, // 244.8(deg) -0.999464 + -32747, // 244.98(deg) -0.999374 + -32744, // 245.16(deg) -0.999279 + -32741, // 245.34(deg) -0.999177 + -32737, // 245.52(deg) -0.999070 + -32733, // 245.7(deg) -0.998957 + -32729, // 245.88(deg) -0.998837 + -32725, // 246.06(deg) -0.998713 + -32721, // 246.24(deg) -0.998583 + -32717, // 246.42(deg) -0.998447 + -32712, // 246.6(deg) -0.998307 + -32707, // 246.78(deg) -0.998161 + -32702, // 246.96(deg) -0.998010 + -32697, // 247.14(deg) -0.997855 + -32692, // 247.32(deg) -0.997694 + -32687, // 247.5(deg) -0.997530 + -32681, // 247.68(deg) -0.997360 + -32675, // 247.86(deg) -0.997187 + -32669, // 248.04(deg) -0.997009 + -32664, // 248.22(deg) -0.996827 + -32657, // 248.4(deg) -0.996641 + -32651, // 248.58(deg) -0.996452 + -32645, // 248.76(deg) -0.996258 + -32638, // 248.94(deg) -0.996061 + -32632, // 249.12(deg) -0.995861 + -32625, // 249.3(deg) -0.995657 + -32618, // 249.48(deg) -0.995450 + -32612, // 249.66(deg) -0.995240 + -32605, // 249.84(deg) -0.995027 + -32597, // 250.02(deg) -0.994811 + -32590, // 250.2(deg) -0.994592 + -32583, // 250.38(deg) -0.994371 + -32576, // 250.56(deg) -0.994147 + -32568, // 250.74(deg) -0.993920 + -32561, // 250.92(deg) -0.993692 + -32553, // 251.1(deg) -0.993461 + -32546, // 251.28(deg) -0.993228 + -32538, // 251.46(deg) -0.992993 + -32530, // 251.64(deg) -0.992756 + -32522, // 251.82(deg) -0.992518 + -32514, // 252(deg) -0.992278 + -32507, // 252.18(deg) -0.992036 + -32499, // 252.36(deg) -0.991793 + -32491, // 252.54(deg) -0.991549 + -32483, // 252.72(deg) -0.991304 + -32474, // 252.9(deg) -0.991057 + -32466, // 253.08(deg) -0.990810 + -32458, // 253.26(deg) -0.990561 + -32450, // 253.44(deg) -0.990312 + -32442, // 253.62(deg) -0.990062 + -32434, // 253.8(deg) -0.989812 + -32425, // 253.98(deg) -0.989561 + -32417, // 254.16(deg) -0.989310 + -32409, // 254.34(deg) -0.989059 + -32401, // 254.52(deg) -0.988807 + -32392, // 254.7(deg) -0.988556 + -32384, // 254.88(deg) -0.988304 + -32376, // 255.06(deg) -0.988053 + -32368, // 255.24(deg) -0.987802 + -32360, // 255.42(deg) -0.987551 + -32351, // 255.6(deg) -0.987300 + -32343, // 255.78(deg) -0.987051 + -32335, // 255.96(deg) -0.986801 + -32327, // 256.14(deg) -0.986553 + -32319, // 256.32(deg) -0.986305 + -32311, // 256.5(deg) -0.986058 + -32303, // 256.68(deg) -0.985813 + -32295, // 256.86(deg) -0.985568 + -32287, // 257.04(deg) -0.985324 + -32279, // 257.22(deg) -0.985082 + -32271, // 257.4(deg) -0.984841 + -32263, // 257.58(deg) -0.984601 + -32255, // 257.76(deg) -0.984363 + -32247, // 257.94(deg) -0.984127 + -32240, // 258.12(deg) -0.983892 + -32232, // 258.3(deg) -0.983659 + -32224, // 258.48(deg) -0.983427 + -32217, // 258.66(deg) -0.983198 + -32209, // 258.84(deg) -0.982971 + -32202, // 259.02(deg) -0.982745 + -32195, // 259.2(deg) -0.982522 + -32188, // 259.38(deg) -0.982301 + -32180, // 259.56(deg) -0.982082 + -32173, // 259.74(deg) -0.981866 + -32166, // 259.92(deg) -0.981652 + -32159, // 260.1(deg) -0.981440 + -32152, // 260.28(deg) -0.981231 + -32146, // 260.46(deg) -0.981025 + -32139, // 260.64(deg) -0.980821 + -32132, // 260.82(deg) -0.980620 + -32126, // 261(deg) -0.980422 + -32120, // 261.18(deg) -0.980227 + -32113, // 261.36(deg) -0.980035 + -32107, // 261.54(deg) -0.979845 + -32101, // 261.72(deg) -0.979659 + -32095, // 261.9(deg) -0.979476 + -32089, // 262.08(deg) -0.979296 + -32083, // 262.26(deg) -0.979120 + -32078, // 262.44(deg) -0.978946 + -32072, // 262.62(deg) -0.978776 + -32067, // 262.8(deg) -0.978609 + -32061, // 262.98(deg) -0.978446 + -32056, // 263.16(deg) -0.978286 + -32051, // 263.34(deg) -0.978130 + -32046, // 263.52(deg) -0.977978 + -32041, // 263.7(deg) -0.977829 + -32036, // 263.88(deg) -0.977683 + -32032, // 264.06(deg) -0.977542 + -32027, // 264.24(deg) -0.977404 + -32023, // 264.42(deg) -0.977270 + -32018, // 264.6(deg) -0.977140 + -32014, // 264.78(deg) -0.977014 + -32010, // 264.96(deg) -0.976891 + -32006, // 265.14(deg) -0.976773 + -32003, // 265.32(deg) -0.976659 + -31999, // 265.5(deg) -0.976548 + -31996, // 265.68(deg) -0.976442 + -31992, // 265.86(deg) -0.976340 + -31989, // 266.04(deg) -0.976242 + -31986, // 266.22(deg) -0.976148 + -31983, // 266.4(deg) -0.976058 + -31980, // 266.58(deg) -0.975973 + -31978, // 266.76(deg) -0.975891 + -31975, // 266.94(deg) -0.975814 + -31973, // 267.12(deg) -0.975742 + -31970, // 267.3(deg) -0.975673 + -31968, // 267.48(deg) -0.975609 + -31966, // 267.66(deg) -0.975549 + -31964, // 267.84(deg) -0.975494 + -31963, // 268.02(deg) -0.975443 + -31961, // 268.2(deg) -0.975396 + -31960, // 268.38(deg) -0.975354 + -31959, // 268.56(deg) -0.975316 + -31958, // 268.74(deg) -0.975283 + -31957, // 268.92(deg) -0.975254 + -31956, // 269.1(deg) -0.975229 + -31955, // 269.28(deg) -0.975209 + -31955, // 269.46(deg) -0.975194 + -31954, // 269.64(deg) -0.975182 + -31954, // 269.82(deg) -0.975176 + -31954, // 270(deg) -0.975174 + -31954, // 270.18(deg) -0.975176 + -31954, // 270.36(deg) -0.975182 + -31955, // 270.54(deg) -0.975194 + -31955, // 270.72(deg) -0.975209 + -31956, // 270.9(deg) -0.975229 + -31957, // 271.08(deg) -0.975254 + -31958, // 271.26(deg) -0.975283 + -31959, // 271.44(deg) -0.975316 + -31960, // 271.62(deg) -0.975354 + -31961, // 271.8(deg) -0.975396 + -31963, // 271.98(deg) -0.975443 + -31964, // 272.16(deg) -0.975494 + -31966, // 272.34(deg) -0.975549 + -31968, // 272.52(deg) -0.975609 + -31970, // 272.7(deg) -0.975673 + -31973, // 272.88(deg) -0.975742 + -31975, // 273.06(deg) -0.975814 + -31978, // 273.24(deg) -0.975891 + -31980, // 273.42(deg) -0.975973 + -31983, // 273.6(deg) -0.976058 + -31986, // 273.78(deg) -0.976148 + -31989, // 273.96(deg) -0.976242 + -31992, // 274.14(deg) -0.976340 + -31996, // 274.32(deg) -0.976442 + -31999, // 274.5(deg) -0.976548 + -32003, // 274.68(deg) -0.976659 + -32006, // 274.86(deg) -0.976773 + -32010, // 275.04(deg) -0.976891 + -32014, // 275.22(deg) -0.977014 + -32018, // 275.4(deg) -0.977140 + -32023, // 275.58(deg) -0.977270 + -32027, // 275.76(deg) -0.977404 + -32032, // 275.94(deg) -0.977542 + -32036, // 276.12(deg) -0.977683 + -32041, // 276.3(deg) -0.977829 + -32046, // 276.48(deg) -0.977978 + -32051, // 276.66(deg) -0.978130 + -32056, // 276.84(deg) -0.978286 + -32061, // 277.02(deg) -0.978446 + -32067, // 277.2(deg) -0.978609 + -32072, // 277.38(deg) -0.978776 + -32078, // 277.56(deg) -0.978946 + -32083, // 277.74(deg) -0.979120 + -32089, // 277.92(deg) -0.979296 + -32095, // 278.1(deg) -0.979476 + -32101, // 278.28(deg) -0.979659 + -32107, // 278.46(deg) -0.979845 + -32113, // 278.64(deg) -0.980035 + -32120, // 278.82(deg) -0.980227 + -32126, // 279(deg) -0.980422 + -32132, // 279.18(deg) -0.980620 + -32139, // 279.36(deg) -0.980821 + -32146, // 279.54(deg) -0.981025 + -32152, // 279.72(deg) -0.981231 + -32159, // 279.9(deg) -0.981440 + -32166, // 280.08(deg) -0.981652 + -32173, // 280.26(deg) -0.981866 + -32180, // 280.44(deg) -0.982082 + -32188, // 280.62(deg) -0.982301 + -32195, // 280.8(deg) -0.982522 + -32202, // 280.98(deg) -0.982745 + -32209, // 281.16(deg) -0.982971 + -32217, // 281.34(deg) -0.983198 + -32224, // 281.52(deg) -0.983427 + -32232, // 281.7(deg) -0.983659 + -32240, // 281.88(deg) -0.983892 + -32247, // 282.06(deg) -0.984127 + -32255, // 282.24(deg) -0.984363 + -32263, // 282.42(deg) -0.984601 + -32271, // 282.6(deg) -0.984841 + -32279, // 282.78(deg) -0.985082 + -32287, // 282.96(deg) -0.985324 + -32295, // 283.14(deg) -0.985568 + -32303, // 283.32(deg) -0.985813 + -32311, // 283.5(deg) -0.986058 + -32319, // 283.68(deg) -0.986305 + -32327, // 283.86(deg) -0.986553 + -32335, // 284.04(deg) -0.986801 + -32343, // 284.22(deg) -0.987051 + -32351, // 284.4(deg) -0.987300 + -32360, // 284.58(deg) -0.987551 + -32368, // 284.76(deg) -0.987802 + -32376, // 284.94(deg) -0.988053 + -32384, // 285.12(deg) -0.988304 + -32392, // 285.3(deg) -0.988556 + -32401, // 285.48(deg) -0.988807 + -32409, // 285.66(deg) -0.989059 + -32417, // 285.84(deg) -0.989310 + -32425, // 286.02(deg) -0.989561 + -32434, // 286.2(deg) -0.989812 + -32442, // 286.38(deg) -0.990062 + -32450, // 286.56(deg) -0.990312 + -32458, // 286.74(deg) -0.990561 + -32466, // 286.92(deg) -0.990810 + -32474, // 287.1(deg) -0.991057 + -32483, // 287.28(deg) -0.991304 + -32491, // 287.46(deg) -0.991549 + -32499, // 287.64(deg) -0.991793 + -32507, // 287.82(deg) -0.992036 + -32514, // 288(deg) -0.992278 + -32522, // 288.18(deg) -0.992518 + -32530, // 288.36(deg) -0.992756 + -32538, // 288.54(deg) -0.992993 + -32546, // 288.72(deg) -0.993228 + -32553, // 288.9(deg) -0.993461 + -32561, // 289.08(deg) -0.993692 + -32568, // 289.26(deg) -0.993920 + -32576, // 289.44(deg) -0.994147 + -32583, // 289.62(deg) -0.994371 + -32590, // 289.8(deg) -0.994592 + -32597, // 289.98(deg) -0.994811 + -32605, // 290.16(deg) -0.995027 + -32612, // 290.34(deg) -0.995240 + -32618, // 290.52(deg) -0.995450 + -32625, // 290.7(deg) -0.995657 + -32632, // 290.88(deg) -0.995861 + -32638, // 291.06(deg) -0.996061 + -32645, // 291.24(deg) -0.996258 + -32651, // 291.42(deg) -0.996452 + -32657, // 291.6(deg) -0.996641 + -32664, // 291.78(deg) -0.996827 + -32669, // 291.96(deg) -0.997009 + -32675, // 292.14(deg) -0.997187 + -32681, // 292.32(deg) -0.997360 + -32687, // 292.5(deg) -0.997530 + -32692, // 292.68(deg) -0.997694 + -32697, // 292.86(deg) -0.997855 + -32702, // 293.04(deg) -0.998010 + -32707, // 293.22(deg) -0.998161 + -32712, // 293.4(deg) -0.998307 + -32717, // 293.58(deg) -0.998447 + -32721, // 293.76(deg) -0.998583 + -32725, // 293.94(deg) -0.998713 + -32729, // 294.12(deg) -0.998837 + -32733, // 294.3(deg) -0.998957 + -32737, // 294.48(deg) -0.999070 + -32741, // 294.66(deg) -0.999177 + -32744, // 294.84(deg) -0.999279 + -32747, // 295.02(deg) -0.999374 + -32750, // 295.2(deg) -0.999464 + -32753, // 295.38(deg) -0.999546 + -32755, // 295.56(deg) -0.999623 + -32757, // 295.74(deg) -0.999693 + -32759, // 295.92(deg) -0.999756 + -32761, // 296.1(deg) -0.999812 + -32763, // 296.28(deg) -0.999861 + -32764, // 296.46(deg) -0.999903 + -32765, // 296.64(deg) -0.999937 + -32766, // 296.82(deg) -0.999965 + -32767, // 297(deg) -0.999984 + -32767, // 297.18(deg) -0.999996 + -32768, // 297.36(deg) -1.000001 + -32767, // 297.54(deg) -0.999997 + -32767, // 297.72(deg) -0.999985 + -32766, // 297.9(deg) -0.999966 + -32765, // 298.08(deg) -0.999937 + -32764, // 298.26(deg) -0.999901 + -32763, // 298.44(deg) -0.999855 + -32761, // 298.62(deg) -0.999801 + -32759, // 298.8(deg) -0.999739 + -32757, // 298.98(deg) -0.999667 + -32754, // 299.16(deg) -0.999586 + -32751, // 299.34(deg) -0.999496 + -32748, // 299.52(deg) -0.999396 + -32744, // 299.7(deg) -0.999287 + -32740, // 299.88(deg) -0.999168 + -32736, // 300.06(deg) -0.999040 + -32732, // 300.24(deg) -0.998902 + -32727, // 300.42(deg) -0.998753 + -32721, // 300.6(deg) -0.998595 + -32716, // 300.78(deg) -0.998426 + -32710, // 300.96(deg) -0.998246 + -32704, // 301.14(deg) -0.998057 + -32697, // 301.32(deg) -0.997856 + -32690, // 301.5(deg) -0.997645 + -32683, // 301.68(deg) -0.997422 + -32675, // 301.86(deg) -0.997189 + -32667, // 302.04(deg) -0.996944 + -32659, // 302.22(deg) -0.996688 + -32650, // 302.4(deg) -0.996421 + -32641, // 302.58(deg) -0.996142 + -32632, // 302.76(deg) -0.995851 + -32622, // 302.94(deg) -0.995548 + -32611, // 303.12(deg) -0.995234 + -32601, // 303.3(deg) -0.994907 + -32590, // 303.48(deg) -0.994568 + -32578, // 303.66(deg) -0.994217 + -32566, // 303.84(deg) -0.993853 + -32554, // 304.02(deg) -0.993476 + -32541, // 304.2(deg) -0.993087 + -32528, // 304.38(deg) -0.992685 + -32514, // 304.56(deg) -0.992270 + -32500, // 304.74(deg) -0.991842 + -32486, // 304.92(deg) -0.991400 + -32471, // 305.1(deg) -0.990946 + -32455, // 305.28(deg) -0.990477 + -32440, // 305.46(deg) -0.989995 + -32423, // 305.64(deg) -0.989500 + -32407, // 305.82(deg) -0.988990 + -32390, // 306(deg) -0.988467 + -32372, // 306.18(deg) -0.987929 + -32354, // 306.36(deg) -0.987377 + -32335, // 306.54(deg) -0.986811 + -32316, // 306.72(deg) -0.986230 + -32297, // 306.9(deg) -0.985635 + -32277, // 307.08(deg) -0.985025 + -32256, // 307.26(deg) -0.984400 + -32235, // 307.44(deg) -0.983760 + -32214, // 307.62(deg) -0.983105 + -32192, // 307.8(deg) -0.982435 + -32169, // 307.98(deg) -0.981750 + -32147, // 308.16(deg) -0.981049 + -32123, // 308.34(deg) -0.980333 + -32099, // 308.52(deg) -0.979601 + -32075, // 308.7(deg) -0.978853 + -32050, // 308.88(deg) -0.978090 + -32024, // 309.06(deg) -0.977310 + -31998, // 309.24(deg) -0.976515 + -31971, // 309.42(deg) -0.975703 + -31944, // 309.6(deg) -0.974875 + -31917, // 309.78(deg) -0.974031 + -31888, // 309.96(deg) -0.973170 + -31860, // 310.14(deg) -0.972292 + -31830, // 310.32(deg) -0.971398 + -31800, // 310.5(deg) -0.970487 + -31770, // 310.68(deg) -0.969559 + -31739, // 310.86(deg) -0.968613 + -31707, // 311.04(deg) -0.967651 + -31675, // 311.22(deg) -0.966672 + -31643, // 311.4(deg) -0.965675 + -31609, // 311.58(deg) -0.964660 + -31576, // 311.76(deg) -0.963628 + -31541, // 311.94(deg) -0.962579 + -31506, // 312.12(deg) -0.961512 + -31471, // 312.3(deg) -0.960426 + -31435, // 312.48(deg) -0.959323 + -31398, // 312.66(deg) -0.958202 + -31361, // 312.84(deg) -0.957063 + -31323, // 313.02(deg) -0.955906 + -31284, // 313.2(deg) -0.954730 + -31245, // 313.38(deg) -0.953536 + -31205, // 313.56(deg) -0.952323 + -31165, // 313.74(deg) -0.951092 + -31124, // 313.92(deg) -0.949842 + -31082, // 314.1(deg) -0.948573 + -31040, // 314.28(deg) -0.947286 + -30997, // 314.46(deg) -0.945979 + -30954, // 314.64(deg) -0.944654 + -30910, // 314.82(deg) -0.943309 + -30865, // 315(deg) -0.941945 + -30820, // 315.18(deg) -0.940562 + -30774, // 315.36(deg) -0.939160 + -30727, // 315.54(deg) -0.937738 + -30680, // 315.72(deg) -0.936297 + -30632, // 315.9(deg) -0.934836 + -30584, // 316.08(deg) -0.933356 + -30535, // 316.26(deg) -0.931855 + -30485, // 316.44(deg) -0.930335 + -30434, // 316.62(deg) -0.928795 + -30383, // 316.8(deg) -0.927236 + -30331, // 316.98(deg) -0.925656 + -30279, // 317.16(deg) -0.924056 + -30226, // 317.34(deg) -0.922436 + -30172, // 317.52(deg) -0.920796 + -30118, // 317.7(deg) -0.919135 + -30063, // 317.88(deg) -0.917454 + -30007, // 318.06(deg) -0.915753 + -29950, // 318.24(deg) -0.914031 + -29893, // 318.42(deg) -0.912289 + -29836, // 318.6(deg) -0.910526 + -29777, // 318.78(deg) -0.908742 + -29718, // 318.96(deg) -0.906938 + -29658, // 319.14(deg) -0.905113 + -29598, // 319.32(deg) -0.903268 + -29537, // 319.5(deg) -0.901401 + -29475, // 319.68(deg) -0.899513 + -29412, // 319.86(deg) -0.897605 + -29349, // 320.04(deg) -0.895675 + -29285, // 320.22(deg) -0.893725 + -29220, // 320.4(deg) -0.891753 + -29155, // 320.58(deg) -0.889760 + -29089, // 320.76(deg) -0.887746 + -29022, // 320.94(deg) -0.885711 + -28955, // 321.12(deg) -0.883655 + -28887, // 321.3(deg) -0.881577 + -28818, // 321.48(deg) -0.879478 + -28749, // 321.66(deg) -0.877357 + -28679, // 321.84(deg) -0.875215 + -28608, // 322.02(deg) -0.873052 + -28536, // 322.2(deg) -0.870867 + -28464, // 322.38(deg) -0.868660 + -28391, // 322.56(deg) -0.866432 + -28317, // 322.74(deg) -0.864182 + -28243, // 322.92(deg) -0.861911 + -28167, // 323.1(deg) -0.859618 + -28092, // 323.28(deg) -0.857304 + -28015, // 323.46(deg) -0.854967 + -27938, // 323.64(deg) -0.852610 + -27860, // 323.82(deg) -0.850230 + -27781, // 324(deg) -0.847828 + -27702, // 324.18(deg) -0.845405 + -27622, // 324.36(deg) -0.842960 + -27541, // 324.54(deg) -0.840493 + -27459, // 324.72(deg) -0.838005 + -27377, // 324.9(deg) -0.835494 + -27294, // 325.08(deg) -0.832962 + -27210, // 325.26(deg) -0.830408 + -27126, // 325.44(deg) -0.827832 + -27041, // 325.62(deg) -0.825234 + -26955, // 325.8(deg) -0.822614 + -26868, // 325.98(deg) -0.819973 + -26781, // 326.16(deg) -0.817309 + -26693, // 326.34(deg) -0.814624 + -26604, // 326.52(deg) -0.811917 + -26515, // 326.7(deg) -0.809188 + -26425, // 326.88(deg) -0.806437 + -26334, // 327.06(deg) -0.803664 + -26242, // 327.24(deg) -0.800869 + -26150, // 327.42(deg) -0.798053 + -26057, // 327.6(deg) -0.795214 + -25963, // 327.78(deg) -0.792354 + -25869, // 327.96(deg) -0.789472 + -25774, // 328.14(deg) -0.786569 + -25678, // 328.32(deg) -0.783643 + -25581, // 328.5(deg) -0.780696 + -25484, // 328.68(deg) -0.777727 + -25386, // 328.86(deg) -0.774736 + -25287, // 329.04(deg) -0.771723 + -25188, // 329.22(deg) -0.768689 + -25088, // 329.4(deg) -0.765633 + -24987, // 329.58(deg) -0.762555 + -24885, // 329.76(deg) -0.759456 + -24783, // 329.94(deg) -0.756336 + -24680, // 330.12(deg) -0.753193 + -24576, // 330.3(deg) -0.750029 + -24472, // 330.48(deg) -0.746844 + -24367, // 330.66(deg) -0.743637 + -24261, // 330.84(deg) -0.740409 + -24155, // 331.02(deg) -0.737159 + -24048, // 331.2(deg) -0.733889 + -23940, // 331.38(deg) -0.730596 + -23831, // 331.56(deg) -0.727283 + -23722, // 331.74(deg) -0.723948 + -23612, // 331.92(deg) -0.720592 + -23501, // 332.1(deg) -0.717215 + -23390, // 332.28(deg) -0.713817 + -23278, // 332.46(deg) -0.710398 + -23165, // 332.64(deg) -0.706958 + -23052, // 332.82(deg) -0.703497 + -22938, // 333(deg) -0.700015 + -22823, // 333.18(deg) -0.696512 + -22707, // 333.36(deg) -0.692988 + -22591, // 333.54(deg) -0.689444 + -22474, // 333.72(deg) -0.685879 + -22357, // 333.9(deg) -0.682294 + -22239, // 334.08(deg) -0.678688 + -22120, // 334.26(deg) -0.675061 + -22000, // 334.44(deg) -0.671414 + -21880, // 334.62(deg) -0.667747 + -21759, // 334.8(deg) -0.664059 + -21638, // 334.98(deg) -0.660352 + -21516, // 335.16(deg) -0.656624 + -21393, // 335.34(deg) -0.652876 + -21269, // 335.52(deg) -0.649108 + -21145, // 335.7(deg) -0.645320 + -21021, // 335.88(deg) -0.641512 + -20895, // 336.06(deg) -0.637685 + -20769, // 336.24(deg) -0.633838 + -20642, // 336.42(deg) -0.629971 + -20515, // 336.6(deg) -0.626085 + -20387, // 336.78(deg) -0.622179 + -20258, // 336.96(deg) -0.618254 + -20129, // 337.14(deg) -0.614310 + -19999, // 337.32(deg) -0.610346 + -19869, // 337.5(deg) -0.606364 + -19738, // 337.68(deg) -0.602362 + -19606, // 337.86(deg) -0.598342 + -19474, // 338.04(deg) -0.594303 + -19341, // 338.22(deg) -0.590245 + -19207, // 338.4(deg) -0.586168 + -19073, // 338.58(deg) -0.582073 + -18938, // 338.76(deg) -0.577959 + -18803, // 338.94(deg) -0.573827 + -18667, // 339.12(deg) -0.569677 + -18530, // 339.3(deg) -0.565509 + -18393, // 339.48(deg) -0.561322 + -18255, // 339.66(deg) -0.557118 + -18117, // 339.84(deg) -0.552896 + -17978, // 340.02(deg) -0.548656 + -17838, // 340.2(deg) -0.544398 + -17698, // 340.38(deg) -0.540123 + -17558, // 340.56(deg) -0.535831 + -17416, // 340.74(deg) -0.531521 + -17275, // 340.92(deg) -0.527195 + -17132, // 341.1(deg) -0.522851 + -16989, // 341.28(deg) -0.518490 + -16846, // 341.46(deg) -0.514112 + -16702, // 341.64(deg) -0.509718 + -16557, // 341.82(deg) -0.505307 + -16412, // 342(deg) -0.500880 + -16267, // 342.18(deg) -0.496436 + -16121, // 342.36(deg) -0.491976 + -15974, // 342.54(deg) -0.487500 + -15827, // 342.72(deg) -0.483008 + -15679, // 342.9(deg) -0.478500 + -15531, // 343.08(deg) -0.473977 + -15382, // 343.26(deg) -0.469437 + -15233, // 343.44(deg) -0.464883 + -15083, // 343.62(deg) -0.460313 + -14933, // 343.8(deg) -0.455728 + -14782, // 343.98(deg) -0.451127 + -14631, // 344.16(deg) -0.446512 + -14479, // 344.34(deg) -0.441882 + -14327, // 344.52(deg) -0.437238 + -14174, // 344.7(deg) -0.432579 + -14021, // 344.88(deg) -0.427905 + -13867, // 345.06(deg) -0.423217 + -13713, // 345.24(deg) -0.418515 + -13559, // 345.42(deg) -0.413799 + -13404, // 345.6(deg) -0.409070 + -13248, // 345.78(deg) -0.404326 + -13093, // 345.96(deg) -0.399569 + -12936, // 346.14(deg) -0.394799 + -12780, // 346.32(deg) -0.390016 + -12622, // 346.5(deg) -0.385219 + -12465, // 346.68(deg) -0.380409 + -12307, // 346.86(deg) -0.375587 + -12148, // 347.04(deg) -0.370752 + -11989, // 347.22(deg) -0.365904 + -11830, // 347.4(deg) -0.361044 + -11671, // 347.58(deg) -0.356172 + -11511, // 347.76(deg) -0.351288 + -11350, // 347.94(deg) -0.346392 + -11189, // 348.12(deg) -0.341484 + -11028, // 348.3(deg) -0.336565 + -10866, // 348.48(deg) -0.331634 + -10705, // 348.66(deg) -0.326692 + -10542, // 348.84(deg) -0.321739 + -10380, // 349.02(deg) -0.316775 + -10217, // 349.2(deg) -0.311800 + -10053, // 349.38(deg) -0.306814 + -9889, // 349.56(deg) -0.301818 + -9725, // 349.74(deg) -0.296812 + -9561, // 349.92(deg) -0.291795 + -9396, // 350.1(deg) -0.286769 + -9231, // 350.28(deg) -0.281733 + -9066, // 350.46(deg) -0.276687 + -8900, // 350.64(deg) -0.271631 + -8734, // 350.82(deg) -0.266567 + -8568, // 351(deg) -0.261493 + -8402, // 351.18(deg) -0.256410 + -8235, // 351.36(deg) -0.251318 + -8068, // 351.54(deg) -0.246218 + -7900, // 351.72(deg) -0.241109 + -7732, // 351.9(deg) -0.235992 + -7565, // 352.08(deg) -0.230867 + -7396, // 352.26(deg) -0.225734 + -7228, // 352.44(deg) -0.220593 + -7059, // 352.62(deg) -0.215445 + -6890, // 352.8(deg) -0.210289 + -6721, // 352.98(deg) -0.205125 + -6552, // 353.16(deg) -0.199955 + -6382, // 353.34(deg) -0.194778 + -6212, // 353.52(deg) -0.189594 + -6042, // 353.7(deg) -0.184403 + -5872, // 353.88(deg) -0.179207 + -5701, // 354.06(deg) -0.174003 + -5531, // 354.24(deg) -0.168794 + -5360, // 354.42(deg) -0.163579 + -5189, // 354.6(deg) -0.158359 + -5017, // 354.78(deg) -0.153133 + -4846, // 354.96(deg) -0.147901 + -4674, // 355.14(deg) -0.142664 + -4503, // 355.32(deg) -0.137423 + -4331, // 355.5(deg) -0.132177 + -4159, // 355.68(deg) -0.126926 + -3986, // 355.86(deg) -0.121670 + -3814, // 356.04(deg) -0.116411 + -3642, // 356.22(deg) -0.111147 + -3469, // 356.4(deg) -0.105880 + -3296, // 356.58(deg) -0.100608 + -3123, // 356.76(deg) -0.095334 + -2950, // 356.94(deg) -0.090056 + -2777, // 357.12(deg) -0.084775 + -2604, // 357.3(deg) -0.079491 + -2431, // 357.48(deg) -0.074204 + -2258, // 357.66(deg) -0.068914 + -2084, // 357.84(deg) -0.063622 + -1911, // 358.02(deg) -0.058328 + -1737, // 358.2(deg) -0.053032 + -1564, // 358.38(deg) -0.047734 + -1390, // 358.56(deg) -0.042435 + -1216, // 358.74(deg) -0.037134 + -1043, // 358.92(deg) -0.031831 + -869, // 359.1(deg) -0.026528 + -695, // 359.28(deg) -0.021223 + -521, // 359.46(deg) -0.015918 + -347, // 359.64(deg) -0.010612 + -173, // 359.82(deg) -0.005306 +}; diff --git a/cdc-test/mathSin2048.c b/cdc-test/mathSin2048.c new file mode 100644 index 0000000..a0626c5 --- /dev/null +++ b/cdc-test/mathSin2048.c @@ -0,0 +1,2050 @@ +const short sin2048[ 2048 ] = { + 0, // 0(deg) 0.000000 + 169, // 0.175781(deg) 0.005182 + 339, // 0.351562(deg) 0.010364 + 509, // 0.527344(deg) 0.015545 + 679, // 0.703125(deg) 0.020726 + 848, // 0.878906(deg) 0.025906 + 1018, // 1.05469(deg) 0.031085 + 1188, // 1.23047(deg) 0.036264 + 1357, // 1.40625(deg) 0.041441 + 1527, // 1.58203(deg) 0.046617 + 1697, // 1.75781(deg) 0.051791 + 1866, // 1.93359(deg) 0.056963 + 2035, // 2.10938(deg) 0.062134 + 2205, // 2.28516(deg) 0.067302 + 2374, // 2.46094(deg) 0.072468 + 2543, // 2.63672(deg) 0.077632 + 2712, // 2.8125(deg) 0.082793 + 2882, // 2.98828(deg) 0.087952 + 3050, // 3.16406(deg) 0.093107 + 3219, // 3.33984(deg) 0.098260 + 3388, // 3.51562(deg) 0.103409 + 3557, // 3.69141(deg) 0.108555 + 3725, // 3.86719(deg) 0.113697 + 3894, // 4.04297(deg) 0.118836 + 4062, // 4.21875(deg) 0.123970 + 4230, // 4.39453(deg) 0.129100 + 4398, // 4.57031(deg) 0.134226 + 4566, // 4.74609(deg) 0.139348 + 4733, // 4.92188(deg) 0.144465 + 4901, // 5.09766(deg) 0.149577 + 5068, // 5.27344(deg) 0.154685 + 5235, // 5.44922(deg) 0.159787 + 5402, // 5.625(deg) 0.164884 + 5569, // 5.80078(deg) 0.169975 + 5736, // 5.97656(deg) 0.175061 + 5902, // 6.15234(deg) 0.180141 + 6069, // 6.32812(deg) 0.185215 + 6235, // 6.50391(deg) 0.190283 + 6401, // 6.67969(deg) 0.195344 + 6566, // 6.85547(deg) 0.200400 + 6732, // 7.03125(deg) 0.205448 + 6897, // 7.20703(deg) 0.210490 + 7062, // 7.38281(deg) 0.215525 + 7227, // 7.55859(deg) 0.220553 + 7391, // 7.73438(deg) 0.225573 + 7555, // 7.91016(deg) 0.230587 + 7719, // 8.08594(deg) 0.235592 + 7883, // 8.26172(deg) 0.240590 + 8047, // 8.4375(deg) 0.245580 + 8210, // 8.61328(deg) 0.250562 + 8373, // 8.78906(deg) 0.255535 + 8536, // 8.96484(deg) 0.260501 + 8698, // 9.14062(deg) 0.265457 + 8860, // 9.31641(deg) 0.270406 + 9022, // 9.49219(deg) 0.275345 + 9184, // 9.66797(deg) 0.280275 + 9345, // 9.84375(deg) 0.285196 + 9506, // 10.0195(deg) 0.290108 + 9666, // 10.1953(deg) 0.295010 + 9827, // 10.3711(deg) 0.299903 + 9987, // 10.5469(deg) 0.304786 + 10146, // 10.7227(deg) 0.309659 + 10306, // 10.8984(deg) 0.314522 + 10465, // 11.0742(deg) 0.319374 + 10623, // 11.25(deg) 0.324217 + 10782, // 11.4258(deg) 0.329048 + 10940, // 11.6016(deg) 0.333870 + 11097, // 11.7773(deg) 0.338680 + 11255, // 11.9531(deg) 0.343479 + 11412, // 12.1289(deg) 0.348268 + 11568, // 12.3047(deg) 0.353045 + 11724, // 12.4805(deg) 0.357810 + 11880, // 12.6562(deg) 0.362564 + 12035, // 12.832(deg) 0.367307 + 12190, // 13.0078(deg) 0.372037 + 12345, // 13.1836(deg) 0.376756 + 12499, // 13.3594(deg) 0.381463 + 12653, // 13.5352(deg) 0.386157 + 12807, // 13.7109(deg) 0.390839 + 12960, // 13.8867(deg) 0.395508 + 13112, // 14.0625(deg) 0.400165 + 13264, // 14.2383(deg) 0.404809 + 13416, // 14.4141(deg) 0.409440 + 13567, // 14.5898(deg) 0.414058 + 13718, // 14.7656(deg) 0.418663 + 13869, // 14.9414(deg) 0.423254 + 14019, // 15.1172(deg) 0.427832 + 14168, // 15.293(deg) 0.432396 + 14317, // 15.4688(deg) 0.436947 + 14466, // 15.6445(deg) 0.441484 + 14614, // 15.8203(deg) 0.446007 + 14762, // 15.9961(deg) 0.450515 + 14909, // 16.1719(deg) 0.455010 + 15056, // 16.3477(deg) 0.459490 + 15202, // 16.5234(deg) 0.463956 + 15348, // 16.6992(deg) 0.468407 + 15494, // 16.875(deg) 0.472843 + 15639, // 17.0508(deg) 0.477265 + 15783, // 17.2266(deg) 0.481671 + 15927, // 17.4023(deg) 0.486063 + 16070, // 17.5781(deg) 0.490439 + 16213, // 17.7539(deg) 0.494800 + 16356, // 17.9297(deg) 0.499146 + 16497, // 18.1055(deg) 0.503476 + 16639, // 18.2812(deg) 0.507790 + 16780, // 18.457(deg) 0.512089 + 16920, // 18.6328(deg) 0.516372 + 17060, // 18.8086(deg) 0.520638 + 17199, // 18.9844(deg) 0.524889 + 17338, // 19.1602(deg) 0.529124 + 17476, // 19.3359(deg) 0.533342 + 17614, // 19.5117(deg) 0.537543 + 17751, // 19.6875(deg) 0.541729 + 17887, // 19.8633(deg) 0.545897 + 18024, // 20.0391(deg) 0.550049 + 18159, // 20.2148(deg) 0.554184 + 18294, // 20.3906(deg) 0.558302 + 18428, // 20.5664(deg) 0.562403 + 18562, // 20.7422(deg) 0.566487 + 18695, // 20.918(deg) 0.570554 + 18828, // 21.0938(deg) 0.574603 + 18960, // 21.2695(deg) 0.578635 + 19092, // 21.4453(deg) 0.582650 + 19223, // 21.6211(deg) 0.586647 + 19353, // 21.7969(deg) 0.590626 + 19483, // 21.9727(deg) 0.594587 + 19612, // 22.1484(deg) 0.598531 + 19741, // 22.3242(deg) 0.602456 + 19869, // 22.5(deg) 0.606364 + 19996, // 22.6758(deg) 0.610253 + 20123, // 22.8516(deg) 0.614125 + 20249, // 23.0273(deg) 0.617978 + 20375, // 23.2031(deg) 0.621812 + 20500, // 23.3789(deg) 0.625628 + 20625, // 23.5547(deg) 0.629426 + 20748, // 23.7305(deg) 0.633205 + 20872, // 23.9062(deg) 0.636965 + 20994, // 24.082(deg) 0.640707 + 21116, // 24.2578(deg) 0.644429 + 21238, // 24.4336(deg) 0.648133 + 21358, // 24.6094(deg) 0.651818 + 21478, // 24.7852(deg) 0.655484 + 21598, // 24.9609(deg) 0.659131 + 21717, // 25.1367(deg) 0.662758 + 21835, // 25.3125(deg) 0.666366 + 21953, // 25.4883(deg) 0.669955 + 22070, // 25.6641(deg) 0.673525 + 22186, // 25.8398(deg) 0.677075 + 22302, // 26.0156(deg) 0.680606 + 22417, // 26.1914(deg) 0.684117 + 22531, // 26.3672(deg) 0.687608 + 22645, // 26.543(deg) 0.691080 + 22758, // 26.7188(deg) 0.694532 + 22870, // 26.8945(deg) 0.697965 + 22982, // 27.0703(deg) 0.701377 + 23093, // 27.2461(deg) 0.704770 + 23204, // 27.4219(deg) 0.708143 + 23314, // 27.5977(deg) 0.711495 + 23423, // 27.7734(deg) 0.714828 + 23532, // 27.9492(deg) 0.718141 + 23639, // 28.125(deg) 0.721433 + 23747, // 28.3008(deg) 0.724705 + 23853, // 28.4766(deg) 0.727958 + 23959, // 28.6523(deg) 0.731189 + 24064, // 28.8281(deg) 0.734401 + 24169, // 29.0039(deg) 0.737592 + 24273, // 29.1797(deg) 0.740763 + 24376, // 29.3555(deg) 0.743914 + 24479, // 29.5312(deg) 0.747044 + 24581, // 29.707(deg) 0.750153 + 24682, // 29.8828(deg) 0.753242 + 24782, // 30.0586(deg) 0.756311 + 24882, // 30.2344(deg) 0.759359 + 24981, // 30.4102(deg) 0.762386 + 25080, // 30.5859(deg) 0.765393 + 25178, // 30.7617(deg) 0.768379 + 25275, // 30.9375(deg) 0.771345 + 25371, // 31.1133(deg) 0.774290 + 25467, // 31.2891(deg) 0.777214 + 25562, // 31.4648(deg) 0.780117 + 25657, // 31.6406(deg) 0.783000 + 25751, // 31.8164(deg) 0.785862 + 25844, // 31.9922(deg) 0.788703 + 25936, // 32.168(deg) 0.791523 + 26028, // 32.3438(deg) 0.794323 + 26119, // 32.5195(deg) 0.797102 + 26209, // 32.6953(deg) 0.799860 + 26299, // 32.8711(deg) 0.802597 + 26388, // 33.0469(deg) 0.805313 + 26476, // 33.2227(deg) 0.808008 + 26564, // 33.3984(deg) 0.810683 + 26651, // 33.5742(deg) 0.813337 + 26737, // 33.75(deg) 0.815969 + 26823, // 33.9258(deg) 0.818581 + 26908, // 34.1016(deg) 0.821172 + 26992, // 34.2773(deg) 0.823743 + 27075, // 34.4531(deg) 0.826292 + 27158, // 34.6289(deg) 0.828821 + 27240, // 34.8047(deg) 0.831328 + 27322, // 34.9805(deg) 0.833815 + 27403, // 35.1562(deg) 0.836281 + 27483, // 35.332(deg) 0.838726 + 27562, // 35.5078(deg) 0.841151 + 27641, // 35.6836(deg) 0.843554 + 27719, // 35.8594(deg) 0.845937 + 27797, // 36.0352(deg) 0.848299 + 27873, // 36.2109(deg) 0.850640 + 27949, // 36.3867(deg) 0.852961 + 28025, // 36.5625(deg) 0.855261 + 28099, // 36.7383(deg) 0.857540 + 28173, // 36.9141(deg) 0.859798 + 28247, // 37.0898(deg) 0.862036 + 28319, // 37.2656(deg) 0.864253 + 28391, // 37.4414(deg) 0.866450 + 28463, // 37.6172(deg) 0.868625 + 28533, // 37.793(deg) 0.870781 + 28603, // 37.9688(deg) 0.872916 + 28672, // 38.1445(deg) 0.875030 + 28741, // 38.3203(deg) 0.877124 + 28809, // 38.4961(deg) 0.879197 + 28876, // 38.6719(deg) 0.881250 + 28943, // 38.8477(deg) 0.883283 + 29009, // 39.0234(deg) 0.885295 + 29074, // 39.1992(deg) 0.887287 + 29139, // 39.375(deg) 0.889259 + 29203, // 39.5508(deg) 0.891210 + 29266, // 39.7266(deg) 0.893142 + 29329, // 39.9023(deg) 0.895053 + 29391, // 40.0781(deg) 0.896944 + 29452, // 40.2539(deg) 0.898815 + 29513, // 40.4297(deg) 0.900666 + 29573, // 40.6055(deg) 0.902497 + 29632, // 40.7812(deg) 0.904308 + 29691, // 40.957(deg) 0.906100 + 29749, // 41.1328(deg) 0.907871 + 29806, // 41.3086(deg) 0.909623 + 29863, // 41.4844(deg) 0.911355 + 29919, // 41.6602(deg) 0.913067 + 29974, // 41.8359(deg) 0.914760 + 30029, // 42.0117(deg) 0.916433 + 30083, // 42.1875(deg) 0.918087 + 30137, // 42.3633(deg) 0.919721 + 30190, // 42.5391(deg) 0.921336 + 30242, // 42.7148(deg) 0.922932 + 30294, // 42.8906(deg) 0.924508 + 30345, // 43.0664(deg) 0.926065 + 30395, // 43.2422(deg) 0.927603 + 30445, // 43.418(deg) 0.929122 + 30494, // 43.5938(deg) 0.930622 + 30543, // 43.7695(deg) 0.932103 + 30591, // 43.9453(deg) 0.933565 + 30638, // 44.1211(deg) 0.935008 + 30685, // 44.2969(deg) 0.936433 + 30731, // 44.4727(deg) 0.937839 + 30776, // 44.6484(deg) 0.939226 + 30821, // 44.8242(deg) 0.940595 + 30865, // 45(deg) 0.941945 + 30909, // 45.1758(deg) 0.943277 + 30952, // 45.3516(deg) 0.944591 + 30994, // 45.5273(deg) 0.945887 + 31036, // 45.7031(deg) 0.947164 + 31077, // 45.8789(deg) 0.948423 + 31118, // 46.0547(deg) 0.949665 + 31158, // 46.2305(deg) 0.950888 + 31198, // 46.4062(deg) 0.952094 + 31237, // 46.582(deg) 0.953281 + 31275, // 46.7578(deg) 0.954452 + 31313, // 46.9336(deg) 0.955604 + 31350, // 47.1094(deg) 0.956739 + 31387, // 47.2852(deg) 0.957857 + 31423, // 47.4609(deg) 0.958958 + 31458, // 47.6367(deg) 0.960041 + 31493, // 47.8125(deg) 0.961107 + 31527, // 47.9883(deg) 0.962156 + 31561, // 48.1641(deg) 0.963188 + 31595, // 48.3398(deg) 0.964203 + 31627, // 48.5156(deg) 0.965201 + 31659, // 48.6914(deg) 0.966183 + 31691, // 48.8672(deg) 0.967148 + 31722, // 49.043(deg) 0.968097 + 31753, // 49.2188(deg) 0.969029 + 31783, // 49.3945(deg) 0.969945 + 31812, // 49.5703(deg) 0.970845 + 31841, // 49.7461(deg) 0.971728 + 31870, // 49.9219(deg) 0.972596 + 31897, // 50.0977(deg) 0.973447 + 31925, // 50.2734(deg) 0.974283 + 31952, // 50.4492(deg) 0.975103 + 31978, // 50.625(deg) 0.975908 + 32004, // 50.8008(deg) 0.976697 + 32029, // 50.9766(deg) 0.977470 + 32054, // 51.1523(deg) 0.978228 + 32078, // 51.3281(deg) 0.978971 + 32102, // 51.5039(deg) 0.979699 + 32126, // 51.6797(deg) 0.980412 + 32149, // 51.8555(deg) 0.981110 + 32171, // 52.0312(deg) 0.981793 + 32193, // 52.207(deg) 0.982462 + 32214, // 52.3828(deg) 0.983116 + 32235, // 52.5586(deg) 0.983755 + 32256, // 52.7344(deg) 0.984380 + 32276, // 52.9102(deg) 0.984991 + 32295, // 53.0859(deg) 0.985588 + 32314, // 53.2617(deg) 0.986170 + 32333, // 53.4375(deg) 0.986739 + 32351, // 53.6133(deg) 0.987294 + 32369, // 53.7891(deg) 0.987835 + 32386, // 53.9648(deg) 0.988363 + 32403, // 54.1406(deg) 0.988877 + 32419, // 54.3164(deg) 0.989377 + 32435, // 54.4922(deg) 0.989865 + 32451, // 54.668(deg) 0.990339 + 32466, // 54.8438(deg) 0.990801 + 32481, // 55.0195(deg) 0.991249 + 32495, // 55.1953(deg) 0.991685 + 32509, // 55.3711(deg) 0.992108 + 32522, // 55.5469(deg) 0.992518 + 32535, // 55.7227(deg) 0.992916 + 32548, // 55.8984(deg) 0.993302 + 32560, // 56.0742(deg) 0.993675 + 32572, // 56.25(deg) 0.994036 + 32584, // 56.4258(deg) 0.994386 + 32595, // 56.6016(deg) 0.994723 + 32605, // 56.7773(deg) 0.995049 + 32616, // 56.9531(deg) 0.995363 + 32625, // 57.1289(deg) 0.995666 + 32635, // 57.3047(deg) 0.995957 + 32644, // 57.4805(deg) 0.996237 + 32653, // 57.6562(deg) 0.996506 + 32661, // 57.832(deg) 0.996763 + 32670, // 58.0078(deg) 0.997010 + 32677, // 58.1836(deg) 0.997246 + 32685, // 58.3594(deg) 0.997472 + 32692, // 58.5352(deg) 0.997687 + 32698, // 58.7109(deg) 0.997891 + 32705, // 58.8867(deg) 0.998085 + 32711, // 59.0625(deg) 0.998269 + 32716, // 59.2383(deg) 0.998443 + 32722, // 59.4141(deg) 0.998607 + 32727, // 59.5898(deg) 0.998762 + 32732, // 59.7656(deg) 0.998906 + 32736, // 59.9414(deg) 0.999041 + 32740, // 60.1172(deg) 0.999166 + 32744, // 60.293(deg) 0.999283 + 32747, // 60.4688(deg) 0.999390 + 32751, // 60.6445(deg) 0.999488 + 32754, // 60.8203(deg) 0.999576 + 32756, // 60.9961(deg) 0.999657 + 32759, // 61.1719(deg) 0.999728 + 32761, // 61.3477(deg) 0.999791 + 32762, // 61.5234(deg) 0.999845 + 32764, // 61.6992(deg) 0.999891 + 32765, // 61.875(deg) 0.999929 + 32766, // 62.0508(deg) 0.999959 + 32767, // 62.2266(deg) 0.999980 + 32767, // 62.4023(deg) 0.999994 + 32767, // 62.5781(deg) 1.000000 + 32767, // 62.7539(deg) 0.999999 + 32767, // 62.9297(deg) 0.999990 + 32767, // 63.1055(deg) 0.999974 + 32766, // 63.2812(deg) 0.999950 + 32765, // 63.457(deg) 0.999920 + 32764, // 63.6328(deg) 0.999882 + 32762, // 63.8086(deg) 0.999837 + 32760, // 63.9844(deg) 0.999786 + 32759, // 64.1602(deg) 0.999728 + 32756, // 64.3359(deg) 0.999664 + 32754, // 64.5117(deg) 0.999593 + 32752, // 64.6875(deg) 0.999516 + 32749, // 64.8633(deg) 0.999433 + 32746, // 65.0391(deg) 0.999344 + 32743, // 65.2148(deg) 0.999249 + 32740, // 65.3906(deg) 0.999148 + 32736, // 65.5664(deg) 0.999041 + 32732, // 65.7422(deg) 0.998929 + 32729, // 65.918(deg) 0.998812 + 32725, // 66.0938(deg) 0.998689 + 32720, // 66.2695(deg) 0.998561 + 32716, // 66.4453(deg) 0.998428 + 32711, // 66.6211(deg) 0.998290 + 32707, // 66.7969(deg) 0.998147 + 32702, // 66.9727(deg) 0.997999 + 32697, // 67.1484(deg) 0.997847 + 32692, // 67.3242(deg) 0.997691 + 32687, // 67.5(deg) 0.997530 + 32681, // 67.6758(deg) 0.997364 + 32676, // 67.8516(deg) 0.997195 + 32670, // 68.0273(deg) 0.997022 + 32664, // 68.2031(deg) 0.996844 + 32658, // 68.3789(deg) 0.996663 + 32652, // 68.5547(deg) 0.996479 + 32646, // 68.7305(deg) 0.996290 + 32640, // 68.9062(deg) 0.996099 + 32633, // 69.082(deg) 0.995903 + 32627, // 69.2578(deg) 0.995705 + 32620, // 69.4336(deg) 0.995504 + 32613, // 69.6094(deg) 0.995299 + 32607, // 69.7852(deg) 0.995092 + 32600, // 69.9609(deg) 0.994882 + 32593, // 70.1367(deg) 0.994669 + 32586, // 70.3125(deg) 0.994454 + 32579, // 70.4883(deg) 0.994236 + 32571, // 70.6641(deg) 0.994016 + 32564, // 70.8398(deg) 0.993794 + 32557, // 71.0156(deg) 0.993569 + 32549, // 71.1914(deg) 0.993343 + 32542, // 71.3672(deg) 0.993114 + 32534, // 71.543(deg) 0.992884 + 32527, // 71.7188(deg) 0.992652 + 32519, // 71.8945(deg) 0.992419 + 32511, // 72.0703(deg) 0.992184 + 32504, // 72.2461(deg) 0.991947 + 32496, // 72.4219(deg) 0.991709 + 32488, // 72.5977(deg) 0.991471 + 32480, // 72.7734(deg) 0.991231 + 32472, // 72.9492(deg) 0.990989 + 32464, // 73.125(deg) 0.990748 + 32456, // 73.3008(deg) 0.990505 + 32448, // 73.4766(deg) 0.990261 + 32440, // 73.6523(deg) 0.990017 + 32432, // 73.8281(deg) 0.989773 + 32424, // 74.0039(deg) 0.989528 + 32416, // 74.1797(deg) 0.989283 + 32408, // 74.3555(deg) 0.989037 + 32400, // 74.5312(deg) 0.988791 + 32392, // 74.707(deg) 0.988546 + 32384, // 74.8828(deg) 0.988300 + 32376, // 75.0586(deg) 0.988055 + 32368, // 75.2344(deg) 0.987809 + 32360, // 75.4102(deg) 0.987565 + 32352, // 75.5859(deg) 0.987320 + 32344, // 75.7617(deg) 0.987076 + 32336, // 75.9375(deg) 0.986833 + 32328, // 76.1133(deg) 0.986590 + 32320, // 76.2891(deg) 0.986348 + 32312, // 76.4648(deg) 0.986107 + 32304, // 76.6406(deg) 0.985866 + 32297, // 76.8164(deg) 0.985627 + 32289, // 76.9922(deg) 0.985389 + 32281, // 77.168(deg) 0.985152 + 32273, // 77.3438(deg) 0.984916 + 32266, // 77.5195(deg) 0.984682 + 32258, // 77.6953(deg) 0.984449 + 32250, // 77.8711(deg) 0.984217 + 32243, // 78.0469(deg) 0.983987 + 32235, // 78.2227(deg) 0.983759 + 32228, // 78.3984(deg) 0.983532 + 32221, // 78.5742(deg) 0.983307 + 32213, // 78.75(deg) 0.983084 + 32206, // 78.9258(deg) 0.982863 + 32199, // 79.1016(deg) 0.982644 + 32192, // 79.2773(deg) 0.982427 + 32185, // 79.4531(deg) 0.982212 + 32178, // 79.6289(deg) 0.981999 + 32171, // 79.8047(deg) 0.981789 + 32164, // 79.9805(deg) 0.981580 + 32157, // 80.1562(deg) 0.981375 + 32151, // 80.332(deg) 0.981171 + 32144, // 80.5078(deg) 0.980971 + 32137, // 80.6836(deg) 0.980772 + 32131, // 80.8594(deg) 0.980577 + 32125, // 81.0352(deg) 0.980384 + 32118, // 81.2109(deg) 0.980194 + 32112, // 81.3867(deg) 0.980006 + 32106, // 81.5625(deg) 0.979822 + 32100, // 81.7383(deg) 0.979641 + 32095, // 81.9141(deg) 0.979462 + 32089, // 82.0898(deg) 0.979286 + 32083, // 82.2656(deg) 0.979114 + 32078, // 82.4414(deg) 0.978945 + 32072, // 82.6172(deg) 0.978779 + 32067, // 82.793(deg) 0.978616 + 32062, // 82.9688(deg) 0.978456 + 32056, // 83.1445(deg) 0.978300 + 32051, // 83.3203(deg) 0.978147 + 32047, // 83.4961(deg) 0.977998 + 32042, // 83.6719(deg) 0.977852 + 32037, // 83.8477(deg) 0.977709 + 32033, // 84.0234(deg) 0.977570 + 32028, // 84.1992(deg) 0.977435 + 32024, // 84.375(deg) 0.977303 + 32020, // 84.5508(deg) 0.977175 + 32015, // 84.7266(deg) 0.977051 + 32012, // 84.9023(deg) 0.976930 + 32008, // 85.0781(deg) 0.976813 + 32004, // 85.2539(deg) 0.976700 + 32000, // 85.4297(deg) 0.976591 + 31997, // 85.6055(deg) 0.976486 + 31994, // 85.7812(deg) 0.976384 + 31990, // 85.957(deg) 0.976287 + 31987, // 86.1328(deg) 0.976193 + 31984, // 86.3086(deg) 0.976103 + 31982, // 86.4844(deg) 0.976018 + 31979, // 86.6602(deg) 0.975936 + 31976, // 86.8359(deg) 0.975858 + 31974, // 87.0117(deg) 0.975785 + 31972, // 87.1875(deg) 0.975716 + 31970, // 87.3633(deg) 0.975650 + 31968, // 87.5391(deg) 0.975589 + 31966, // 87.7148(deg) 0.975532 + 31964, // 87.8906(deg) 0.975479 + 31962, // 88.0664(deg) 0.975431 + 31961, // 88.2422(deg) 0.975386 + 31960, // 88.418(deg) 0.975346 + 31958, // 88.5938(deg) 0.975310 + 31957, // 88.7695(deg) 0.975278 + 31956, // 88.9453(deg) 0.975250 + 31956, // 89.1211(deg) 0.975227 + 31955, // 89.2969(deg) 0.975208 + 31955, // 89.4727(deg) 0.975193 + 31954, // 89.6484(deg) 0.975182 + 31954, // 89.8242(deg) 0.975176 + 31954, // 90(deg) 0.975174 + 31954, // 90.1758(deg) 0.975176 + 31954, // 90.3516(deg) 0.975182 + 31955, // 90.5273(deg) 0.975193 + 31955, // 90.7031(deg) 0.975208 + 31956, // 90.8789(deg) 0.975227 + 31956, // 91.0547(deg) 0.975250 + 31957, // 91.2305(deg) 0.975278 + 31958, // 91.4062(deg) 0.975310 + 31960, // 91.582(deg) 0.975346 + 31961, // 91.7578(deg) 0.975386 + 31962, // 91.9336(deg) 0.975431 + 31964, // 92.1094(deg) 0.975479 + 31966, // 92.2852(deg) 0.975532 + 31968, // 92.4609(deg) 0.975589 + 31970, // 92.6367(deg) 0.975650 + 31972, // 92.8125(deg) 0.975716 + 31974, // 92.9883(deg) 0.975785 + 31976, // 93.1641(deg) 0.975858 + 31979, // 93.3398(deg) 0.975936 + 31982, // 93.5156(deg) 0.976018 + 31984, // 93.6914(deg) 0.976103 + 31987, // 93.8672(deg) 0.976193 + 31990, // 94.043(deg) 0.976287 + 31994, // 94.2188(deg) 0.976384 + 31997, // 94.3945(deg) 0.976486 + 32000, // 94.5703(deg) 0.976591 + 32004, // 94.7461(deg) 0.976700 + 32008, // 94.9219(deg) 0.976813 + 32012, // 95.0977(deg) 0.976930 + 32015, // 95.2734(deg) 0.977051 + 32020, // 95.4492(deg) 0.977175 + 32024, // 95.625(deg) 0.977303 + 32028, // 95.8008(deg) 0.977435 + 32033, // 95.9766(deg) 0.977570 + 32037, // 96.1523(deg) 0.977709 + 32042, // 96.3281(deg) 0.977852 + 32047, // 96.5039(deg) 0.977998 + 32051, // 96.6797(deg) 0.978147 + 32056, // 96.8555(deg) 0.978300 + 32062, // 97.0312(deg) 0.978456 + 32067, // 97.207(deg) 0.978616 + 32072, // 97.3828(deg) 0.978779 + 32078, // 97.5586(deg) 0.978945 + 32083, // 97.7344(deg) 0.979114 + 32089, // 97.9102(deg) 0.979286 + 32095, // 98.0859(deg) 0.979462 + 32100, // 98.2617(deg) 0.979641 + 32106, // 98.4375(deg) 0.979822 + 32112, // 98.6133(deg) 0.980006 + 32118, // 98.7891(deg) 0.980194 + 32125, // 98.9648(deg) 0.980384 + 32131, // 99.1406(deg) 0.980577 + 32137, // 99.3164(deg) 0.980772 + 32144, // 99.4922(deg) 0.980971 + 32151, // 99.668(deg) 0.981171 + 32157, // 99.8438(deg) 0.981375 + 32164, // 100.02(deg) 0.981580 + 32171, // 100.195(deg) 0.981789 + 32178, // 100.371(deg) 0.981999 + 32185, // 100.547(deg) 0.982212 + 32192, // 100.723(deg) 0.982427 + 32199, // 100.898(deg) 0.982644 + 32206, // 101.074(deg) 0.982863 + 32213, // 101.25(deg) 0.983084 + 32221, // 101.426(deg) 0.983307 + 32228, // 101.602(deg) 0.983532 + 32235, // 101.777(deg) 0.983759 + 32243, // 101.953(deg) 0.983987 + 32250, // 102.129(deg) 0.984217 + 32258, // 102.305(deg) 0.984449 + 32266, // 102.48(deg) 0.984682 + 32273, // 102.656(deg) 0.984916 + 32281, // 102.832(deg) 0.985152 + 32289, // 103.008(deg) 0.985389 + 32297, // 103.184(deg) 0.985627 + 32304, // 103.359(deg) 0.985866 + 32312, // 103.535(deg) 0.986107 + 32320, // 103.711(deg) 0.986348 + 32328, // 103.887(deg) 0.986590 + 32336, // 104.062(deg) 0.986833 + 32344, // 104.238(deg) 0.987076 + 32352, // 104.414(deg) 0.987320 + 32360, // 104.59(deg) 0.987565 + 32368, // 104.766(deg) 0.987809 + 32376, // 104.941(deg) 0.988055 + 32384, // 105.117(deg) 0.988300 + 32392, // 105.293(deg) 0.988546 + 32400, // 105.469(deg) 0.988791 + 32408, // 105.645(deg) 0.989037 + 32416, // 105.82(deg) 0.989283 + 32424, // 105.996(deg) 0.989528 + 32432, // 106.172(deg) 0.989773 + 32440, // 106.348(deg) 0.990017 + 32448, // 106.523(deg) 0.990261 + 32456, // 106.699(deg) 0.990505 + 32464, // 106.875(deg) 0.990748 + 32472, // 107.051(deg) 0.990989 + 32480, // 107.227(deg) 0.991231 + 32488, // 107.402(deg) 0.991471 + 32496, // 107.578(deg) 0.991709 + 32504, // 107.754(deg) 0.991947 + 32511, // 107.93(deg) 0.992184 + 32519, // 108.105(deg) 0.992419 + 32527, // 108.281(deg) 0.992652 + 32534, // 108.457(deg) 0.992884 + 32542, // 108.633(deg) 0.993114 + 32549, // 108.809(deg) 0.993343 + 32557, // 108.984(deg) 0.993569 + 32564, // 109.16(deg) 0.993794 + 32571, // 109.336(deg) 0.994016 + 32579, // 109.512(deg) 0.994236 + 32586, // 109.688(deg) 0.994454 + 32593, // 109.863(deg) 0.994669 + 32600, // 110.039(deg) 0.994882 + 32607, // 110.215(deg) 0.995092 + 32613, // 110.391(deg) 0.995299 + 32620, // 110.566(deg) 0.995504 + 32627, // 110.742(deg) 0.995705 + 32633, // 110.918(deg) 0.995903 + 32640, // 111.094(deg) 0.996099 + 32646, // 111.27(deg) 0.996290 + 32652, // 111.445(deg) 0.996479 + 32658, // 111.621(deg) 0.996663 + 32664, // 111.797(deg) 0.996844 + 32670, // 111.973(deg) 0.997022 + 32676, // 112.148(deg) 0.997195 + 32681, // 112.324(deg) 0.997364 + 32687, // 112.5(deg) 0.997530 + 32692, // 112.676(deg) 0.997691 + 32697, // 112.852(deg) 0.997847 + 32702, // 113.027(deg) 0.997999 + 32707, // 113.203(deg) 0.998147 + 32711, // 113.379(deg) 0.998290 + 32716, // 113.555(deg) 0.998428 + 32720, // 113.73(deg) 0.998561 + 32725, // 113.906(deg) 0.998689 + 32729, // 114.082(deg) 0.998812 + 32732, // 114.258(deg) 0.998929 + 32736, // 114.434(deg) 0.999041 + 32740, // 114.609(deg) 0.999148 + 32743, // 114.785(deg) 0.999249 + 32746, // 114.961(deg) 0.999344 + 32749, // 115.137(deg) 0.999433 + 32752, // 115.312(deg) 0.999516 + 32754, // 115.488(deg) 0.999593 + 32756, // 115.664(deg) 0.999664 + 32759, // 115.84(deg) 0.999728 + 32760, // 116.016(deg) 0.999786 + 32762, // 116.191(deg) 0.999837 + 32764, // 116.367(deg) 0.999882 + 32765, // 116.543(deg) 0.999920 + 32766, // 116.719(deg) 0.999950 + 32767, // 116.895(deg) 0.999974 + 32767, // 117.07(deg) 0.999990 + 32767, // 117.246(deg) 0.999999 + 32767, // 117.422(deg) 1.000000 + 32767, // 117.598(deg) 0.999994 + 32767, // 117.773(deg) 0.999980 + 32766, // 117.949(deg) 0.999959 + 32765, // 118.125(deg) 0.999929 + 32764, // 118.301(deg) 0.999891 + 32762, // 118.477(deg) 0.999845 + 32761, // 118.652(deg) 0.999791 + 32759, // 118.828(deg) 0.999728 + 32756, // 119.004(deg) 0.999657 + 32754, // 119.18(deg) 0.999576 + 32751, // 119.355(deg) 0.999488 + 32747, // 119.531(deg) 0.999390 + 32744, // 119.707(deg) 0.999283 + 32740, // 119.883(deg) 0.999166 + 32736, // 120.059(deg) 0.999041 + 32732, // 120.234(deg) 0.998906 + 32727, // 120.41(deg) 0.998762 + 32722, // 120.586(deg) 0.998607 + 32716, // 120.762(deg) 0.998443 + 32711, // 120.938(deg) 0.998269 + 32705, // 121.113(deg) 0.998085 + 32698, // 121.289(deg) 0.997891 + 32692, // 121.465(deg) 0.997687 + 32685, // 121.641(deg) 0.997472 + 32677, // 121.816(deg) 0.997246 + 32670, // 121.992(deg) 0.997010 + 32661, // 122.168(deg) 0.996763 + 32653, // 122.344(deg) 0.996506 + 32644, // 122.52(deg) 0.996237 + 32635, // 122.695(deg) 0.995957 + 32625, // 122.871(deg) 0.995666 + 32616, // 123.047(deg) 0.995363 + 32605, // 123.223(deg) 0.995049 + 32595, // 123.398(deg) 0.994723 + 32584, // 123.574(deg) 0.994386 + 32572, // 123.75(deg) 0.994036 + 32560, // 123.926(deg) 0.993675 + 32548, // 124.102(deg) 0.993302 + 32535, // 124.277(deg) 0.992916 + 32522, // 124.453(deg) 0.992518 + 32509, // 124.629(deg) 0.992108 + 32495, // 124.805(deg) 0.991685 + 32481, // 124.98(deg) 0.991249 + 32466, // 125.156(deg) 0.990801 + 32451, // 125.332(deg) 0.990339 + 32435, // 125.508(deg) 0.989865 + 32419, // 125.684(deg) 0.989377 + 32403, // 125.859(deg) 0.988877 + 32386, // 126.035(deg) 0.988363 + 32369, // 126.211(deg) 0.987835 + 32351, // 126.387(deg) 0.987294 + 32333, // 126.562(deg) 0.986739 + 32314, // 126.738(deg) 0.986170 + 32295, // 126.914(deg) 0.985588 + 32276, // 127.09(deg) 0.984991 + 32256, // 127.266(deg) 0.984380 + 32235, // 127.441(deg) 0.983755 + 32214, // 127.617(deg) 0.983116 + 32193, // 127.793(deg) 0.982462 + 32171, // 127.969(deg) 0.981793 + 32149, // 128.145(deg) 0.981110 + 32126, // 128.32(deg) 0.980412 + 32102, // 128.496(deg) 0.979699 + 32078, // 128.672(deg) 0.978971 + 32054, // 128.848(deg) 0.978228 + 32029, // 129.023(deg) 0.977470 + 32004, // 129.199(deg) 0.976697 + 31978, // 129.375(deg) 0.975908 + 31952, // 129.551(deg) 0.975103 + 31925, // 129.727(deg) 0.974283 + 31897, // 129.902(deg) 0.973447 + 31870, // 130.078(deg) 0.972596 + 31841, // 130.254(deg) 0.971728 + 31812, // 130.43(deg) 0.970845 + 31783, // 130.605(deg) 0.969945 + 31753, // 130.781(deg) 0.969029 + 31722, // 130.957(deg) 0.968097 + 31691, // 131.133(deg) 0.967148 + 31659, // 131.309(deg) 0.966183 + 31627, // 131.484(deg) 0.965201 + 31595, // 131.66(deg) 0.964203 + 31561, // 131.836(deg) 0.963188 + 31527, // 132.012(deg) 0.962156 + 31493, // 132.188(deg) 0.961107 + 31458, // 132.363(deg) 0.960041 + 31423, // 132.539(deg) 0.958958 + 31387, // 132.715(deg) 0.957857 + 31350, // 132.891(deg) 0.956739 + 31313, // 133.066(deg) 0.955604 + 31275, // 133.242(deg) 0.954452 + 31237, // 133.418(deg) 0.953281 + 31198, // 133.594(deg) 0.952094 + 31158, // 133.77(deg) 0.950888 + 31118, // 133.945(deg) 0.949665 + 31077, // 134.121(deg) 0.948423 + 31036, // 134.297(deg) 0.947164 + 30994, // 134.473(deg) 0.945887 + 30952, // 134.648(deg) 0.944591 + 30909, // 134.824(deg) 0.943277 + 30865, // 135(deg) 0.941945 + 30821, // 135.176(deg) 0.940595 + 30776, // 135.352(deg) 0.939226 + 30731, // 135.527(deg) 0.937839 + 30685, // 135.703(deg) 0.936433 + 30638, // 135.879(deg) 0.935008 + 30591, // 136.055(deg) 0.933565 + 30543, // 136.23(deg) 0.932103 + 30494, // 136.406(deg) 0.930622 + 30445, // 136.582(deg) 0.929122 + 30395, // 136.758(deg) 0.927603 + 30345, // 136.934(deg) 0.926065 + 30294, // 137.109(deg) 0.924508 + 30242, // 137.285(deg) 0.922932 + 30190, // 137.461(deg) 0.921336 + 30137, // 137.637(deg) 0.919721 + 30083, // 137.812(deg) 0.918087 + 30029, // 137.988(deg) 0.916433 + 29974, // 138.164(deg) 0.914760 + 29919, // 138.34(deg) 0.913067 + 29863, // 138.516(deg) 0.911355 + 29806, // 138.691(deg) 0.909623 + 29749, // 138.867(deg) 0.907871 + 29691, // 139.043(deg) 0.906100 + 29632, // 139.219(deg) 0.904308 + 29573, // 139.395(deg) 0.902497 + 29513, // 139.57(deg) 0.900666 + 29452, // 139.746(deg) 0.898815 + 29391, // 139.922(deg) 0.896944 + 29329, // 140.098(deg) 0.895053 + 29266, // 140.273(deg) 0.893142 + 29203, // 140.449(deg) 0.891210 + 29139, // 140.625(deg) 0.889259 + 29074, // 140.801(deg) 0.887287 + 29009, // 140.977(deg) 0.885295 + 28943, // 141.152(deg) 0.883283 + 28876, // 141.328(deg) 0.881250 + 28809, // 141.504(deg) 0.879197 + 28741, // 141.68(deg) 0.877124 + 28672, // 141.855(deg) 0.875030 + 28603, // 142.031(deg) 0.872916 + 28533, // 142.207(deg) 0.870781 + 28463, // 142.383(deg) 0.868625 + 28391, // 142.559(deg) 0.866450 + 28319, // 142.734(deg) 0.864253 + 28247, // 142.91(deg) 0.862036 + 28173, // 143.086(deg) 0.859798 + 28099, // 143.262(deg) 0.857540 + 28025, // 143.438(deg) 0.855261 + 27949, // 143.613(deg) 0.852961 + 27873, // 143.789(deg) 0.850640 + 27797, // 143.965(deg) 0.848299 + 27719, // 144.141(deg) 0.845937 + 27641, // 144.316(deg) 0.843554 + 27562, // 144.492(deg) 0.841151 + 27483, // 144.668(deg) 0.838726 + 27403, // 144.844(deg) 0.836281 + 27322, // 145.02(deg) 0.833815 + 27240, // 145.195(deg) 0.831328 + 27158, // 145.371(deg) 0.828821 + 27075, // 145.547(deg) 0.826292 + 26992, // 145.723(deg) 0.823743 + 26908, // 145.898(deg) 0.821172 + 26823, // 146.074(deg) 0.818581 + 26737, // 146.25(deg) 0.815969 + 26651, // 146.426(deg) 0.813337 + 26564, // 146.602(deg) 0.810683 + 26476, // 146.777(deg) 0.808008 + 26388, // 146.953(deg) 0.805313 + 26299, // 147.129(deg) 0.802597 + 26209, // 147.305(deg) 0.799860 + 26119, // 147.48(deg) 0.797102 + 26028, // 147.656(deg) 0.794323 + 25936, // 147.832(deg) 0.791523 + 25844, // 148.008(deg) 0.788703 + 25751, // 148.184(deg) 0.785862 + 25657, // 148.359(deg) 0.783000 + 25562, // 148.535(deg) 0.780117 + 25467, // 148.711(deg) 0.777214 + 25371, // 148.887(deg) 0.774290 + 25275, // 149.062(deg) 0.771345 + 25178, // 149.238(deg) 0.768379 + 25080, // 149.414(deg) 0.765393 + 24981, // 149.59(deg) 0.762386 + 24882, // 149.766(deg) 0.759359 + 24782, // 149.941(deg) 0.756311 + 24682, // 150.117(deg) 0.753242 + 24581, // 150.293(deg) 0.750153 + 24479, // 150.469(deg) 0.747044 + 24376, // 150.645(deg) 0.743914 + 24273, // 150.82(deg) 0.740763 + 24169, // 150.996(deg) 0.737592 + 24064, // 151.172(deg) 0.734401 + 23959, // 151.348(deg) 0.731189 + 23853, // 151.523(deg) 0.727958 + 23747, // 151.699(deg) 0.724705 + 23639, // 151.875(deg) 0.721433 + 23532, // 152.051(deg) 0.718141 + 23423, // 152.227(deg) 0.714828 + 23314, // 152.402(deg) 0.711495 + 23204, // 152.578(deg) 0.708143 + 23093, // 152.754(deg) 0.704770 + 22982, // 152.93(deg) 0.701377 + 22870, // 153.105(deg) 0.697965 + 22758, // 153.281(deg) 0.694532 + 22645, // 153.457(deg) 0.691080 + 22531, // 153.633(deg) 0.687608 + 22417, // 153.809(deg) 0.684117 + 22302, // 153.984(deg) 0.680606 + 22186, // 154.16(deg) 0.677075 + 22070, // 154.336(deg) 0.673525 + 21953, // 154.512(deg) 0.669955 + 21835, // 154.688(deg) 0.666366 + 21717, // 154.863(deg) 0.662758 + 21598, // 155.039(deg) 0.659131 + 21478, // 155.215(deg) 0.655484 + 21358, // 155.391(deg) 0.651818 + 21238, // 155.566(deg) 0.648133 + 21116, // 155.742(deg) 0.644429 + 20994, // 155.918(deg) 0.640707 + 20872, // 156.094(deg) 0.636965 + 20748, // 156.27(deg) 0.633205 + 20625, // 156.445(deg) 0.629426 + 20500, // 156.621(deg) 0.625628 + 20375, // 156.797(deg) 0.621812 + 20249, // 156.973(deg) 0.617978 + 20123, // 157.148(deg) 0.614125 + 19996, // 157.324(deg) 0.610253 + 19869, // 157.5(deg) 0.606364 + 19741, // 157.676(deg) 0.602456 + 19612, // 157.852(deg) 0.598531 + 19483, // 158.027(deg) 0.594587 + 19353, // 158.203(deg) 0.590626 + 19223, // 158.379(deg) 0.586647 + 19092, // 158.555(deg) 0.582650 + 18960, // 158.73(deg) 0.578635 + 18828, // 158.906(deg) 0.574603 + 18695, // 159.082(deg) 0.570554 + 18562, // 159.258(deg) 0.566487 + 18428, // 159.434(deg) 0.562403 + 18294, // 159.609(deg) 0.558302 + 18159, // 159.785(deg) 0.554184 + 18024, // 159.961(deg) 0.550049 + 17887, // 160.137(deg) 0.545897 + 17751, // 160.312(deg) 0.541729 + 17614, // 160.488(deg) 0.537543 + 17476, // 160.664(deg) 0.533342 + 17338, // 160.84(deg) 0.529124 + 17199, // 161.016(deg) 0.524889 + 17060, // 161.191(deg) 0.520638 + 16920, // 161.367(deg) 0.516372 + 16780, // 161.543(deg) 0.512089 + 16639, // 161.719(deg) 0.507790 + 16497, // 161.895(deg) 0.503476 + 16356, // 162.07(deg) 0.499146 + 16213, // 162.246(deg) 0.494800 + 16070, // 162.422(deg) 0.490439 + 15927, // 162.598(deg) 0.486063 + 15783, // 162.773(deg) 0.481671 + 15639, // 162.949(deg) 0.477265 + 15494, // 163.125(deg) 0.472843 + 15348, // 163.301(deg) 0.468407 + 15202, // 163.477(deg) 0.463956 + 15056, // 163.652(deg) 0.459490 + 14909, // 163.828(deg) 0.455010 + 14762, // 164.004(deg) 0.450515 + 14614, // 164.18(deg) 0.446007 + 14466, // 164.355(deg) 0.441484 + 14317, // 164.531(deg) 0.436947 + 14168, // 164.707(deg) 0.432396 + 14019, // 164.883(deg) 0.427832 + 13869, // 165.059(deg) 0.423254 + 13718, // 165.234(deg) 0.418663 + 13567, // 165.41(deg) 0.414058 + 13416, // 165.586(deg) 0.409440 + 13264, // 165.762(deg) 0.404809 + 13112, // 165.938(deg) 0.400165 + 12960, // 166.113(deg) 0.395508 + 12807, // 166.289(deg) 0.390839 + 12653, // 166.465(deg) 0.386157 + 12499, // 166.641(deg) 0.381463 + 12345, // 166.816(deg) 0.376756 + 12190, // 166.992(deg) 0.372037 + 12035, // 167.168(deg) 0.367307 + 11880, // 167.344(deg) 0.362564 + 11724, // 167.52(deg) 0.357810 + 11568, // 167.695(deg) 0.353045 + 11412, // 167.871(deg) 0.348268 + 11255, // 168.047(deg) 0.343479 + 11097, // 168.223(deg) 0.338680 + 10940, // 168.398(deg) 0.333870 + 10782, // 168.574(deg) 0.329048 + 10623, // 168.75(deg) 0.324217 + 10465, // 168.926(deg) 0.319374 + 10306, // 169.102(deg) 0.314522 + 10146, // 169.277(deg) 0.309659 + 9987, // 169.453(deg) 0.304786 + 9827, // 169.629(deg) 0.299903 + 9666, // 169.805(deg) 0.295010 + 9506, // 169.98(deg) 0.290108 + 9345, // 170.156(deg) 0.285196 + 9184, // 170.332(deg) 0.280275 + 9022, // 170.508(deg) 0.275345 + 8860, // 170.684(deg) 0.270406 + 8698, // 170.859(deg) 0.265457 + 8536, // 171.035(deg) 0.260501 + 8373, // 171.211(deg) 0.255535 + 8210, // 171.387(deg) 0.250562 + 8047, // 171.562(deg) 0.245580 + 7883, // 171.738(deg) 0.240590 + 7719, // 171.914(deg) 0.235592 + 7555, // 172.09(deg) 0.230587 + 7391, // 172.266(deg) 0.225573 + 7227, // 172.441(deg) 0.220553 + 7062, // 172.617(deg) 0.215525 + 6897, // 172.793(deg) 0.210490 + 6732, // 172.969(deg) 0.205448 + 6566, // 173.145(deg) 0.200400 + 6401, // 173.32(deg) 0.195344 + 6235, // 173.496(deg) 0.190283 + 6069, // 173.672(deg) 0.185215 + 5902, // 173.848(deg) 0.180141 + 5736, // 174.023(deg) 0.175061 + 5569, // 174.199(deg) 0.169975 + 5402, // 174.375(deg) 0.164884 + 5235, // 174.551(deg) 0.159787 + 5068, // 174.727(deg) 0.154685 + 4901, // 174.902(deg) 0.149577 + 4733, // 175.078(deg) 0.144465 + 4566, // 175.254(deg) 0.139348 + 4398, // 175.43(deg) 0.134226 + 4230, // 175.605(deg) 0.129100 + 4062, // 175.781(deg) 0.123970 + 3894, // 175.957(deg) 0.118836 + 3725, // 176.133(deg) 0.113697 + 3557, // 176.309(deg) 0.108555 + 3388, // 176.484(deg) 0.103409 + 3219, // 176.66(deg) 0.098260 + 3050, // 176.836(deg) 0.093107 + 2882, // 177.012(deg) 0.087952 + 2712, // 177.188(deg) 0.082793 + 2543, // 177.363(deg) 0.077632 + 2374, // 177.539(deg) 0.072468 + 2205, // 177.715(deg) 0.067302 + 2035, // 177.891(deg) 0.062134 + 1866, // 178.066(deg) 0.056963 + 1697, // 178.242(deg) 0.051791 + 1527, // 178.418(deg) 0.046617 + 1357, // 178.594(deg) 0.041441 + 1188, // 178.77(deg) 0.036264 + 1018, // 178.945(deg) 0.031085 + 848, // 179.121(deg) 0.025906 + 679, // 179.297(deg) 0.020726 + 509, // 179.473(deg) 0.015545 + 339, // 179.648(deg) 0.010364 + 169, // 179.824(deg) 0.005182 + 0, // 180(deg) 0.000000 + -169, // 180.176(deg) -0.005182 + -339, // 180.352(deg) -0.010364 + -509, // 180.527(deg) -0.015545 + -679, // 180.703(deg) -0.020726 + -848, // 180.879(deg) -0.025906 + -1018, // 181.055(deg) -0.031085 + -1188, // 181.23(deg) -0.036264 + -1357, // 181.406(deg) -0.041441 + -1527, // 181.582(deg) -0.046617 + -1697, // 181.758(deg) -0.051791 + -1866, // 181.934(deg) -0.056963 + -2035, // 182.109(deg) -0.062134 + -2205, // 182.285(deg) -0.067302 + -2374, // 182.461(deg) -0.072468 + -2543, // 182.637(deg) -0.077632 + -2712, // 182.812(deg) -0.082793 + -2882, // 182.988(deg) -0.087952 + -3050, // 183.164(deg) -0.093107 + -3219, // 183.34(deg) -0.098260 + -3388, // 183.516(deg) -0.103409 + -3557, // 183.691(deg) -0.108555 + -3725, // 183.867(deg) -0.113697 + -3894, // 184.043(deg) -0.118836 + -4062, // 184.219(deg) -0.123970 + -4230, // 184.395(deg) -0.129100 + -4398, // 184.57(deg) -0.134226 + -4566, // 184.746(deg) -0.139348 + -4733, // 184.922(deg) -0.144465 + -4901, // 185.098(deg) -0.149577 + -5068, // 185.273(deg) -0.154685 + -5235, // 185.449(deg) -0.159787 + -5402, // 185.625(deg) -0.164884 + -5569, // 185.801(deg) -0.169975 + -5736, // 185.977(deg) -0.175061 + -5902, // 186.152(deg) -0.180141 + -6069, // 186.328(deg) -0.185215 + -6235, // 186.504(deg) -0.190283 + -6401, // 186.68(deg) -0.195344 + -6566, // 186.855(deg) -0.200400 + -6732, // 187.031(deg) -0.205448 + -6897, // 187.207(deg) -0.210490 + -7062, // 187.383(deg) -0.215525 + -7227, // 187.559(deg) -0.220553 + -7391, // 187.734(deg) -0.225573 + -7555, // 187.91(deg) -0.230587 + -7719, // 188.086(deg) -0.235592 + -7883, // 188.262(deg) -0.240590 + -8047, // 188.438(deg) -0.245580 + -8210, // 188.613(deg) -0.250562 + -8373, // 188.789(deg) -0.255535 + -8536, // 188.965(deg) -0.260501 + -8698, // 189.141(deg) -0.265457 + -8860, // 189.316(deg) -0.270406 + -9022, // 189.492(deg) -0.275345 + -9184, // 189.668(deg) -0.280275 + -9345, // 189.844(deg) -0.285196 + -9506, // 190.02(deg) -0.290108 + -9666, // 190.195(deg) -0.295010 + -9827, // 190.371(deg) -0.299903 + -9987, // 190.547(deg) -0.304786 + -10146, // 190.723(deg) -0.309659 + -10306, // 190.898(deg) -0.314522 + -10465, // 191.074(deg) -0.319374 + -10623, // 191.25(deg) -0.324217 + -10782, // 191.426(deg) -0.329048 + -10940, // 191.602(deg) -0.333870 + -11097, // 191.777(deg) -0.338680 + -11255, // 191.953(deg) -0.343479 + -11412, // 192.129(deg) -0.348268 + -11568, // 192.305(deg) -0.353045 + -11724, // 192.48(deg) -0.357810 + -11880, // 192.656(deg) -0.362564 + -12035, // 192.832(deg) -0.367307 + -12190, // 193.008(deg) -0.372037 + -12345, // 193.184(deg) -0.376756 + -12499, // 193.359(deg) -0.381463 + -12653, // 193.535(deg) -0.386157 + -12807, // 193.711(deg) -0.390839 + -12960, // 193.887(deg) -0.395508 + -13112, // 194.062(deg) -0.400165 + -13264, // 194.238(deg) -0.404809 + -13416, // 194.414(deg) -0.409440 + -13567, // 194.59(deg) -0.414058 + -13718, // 194.766(deg) -0.418663 + -13869, // 194.941(deg) -0.423254 + -14019, // 195.117(deg) -0.427832 + -14168, // 195.293(deg) -0.432396 + -14317, // 195.469(deg) -0.436947 + -14466, // 195.645(deg) -0.441484 + -14614, // 195.82(deg) -0.446007 + -14762, // 195.996(deg) -0.450515 + -14909, // 196.172(deg) -0.455010 + -15056, // 196.348(deg) -0.459490 + -15202, // 196.523(deg) -0.463956 + -15348, // 196.699(deg) -0.468407 + -15494, // 196.875(deg) -0.472843 + -15639, // 197.051(deg) -0.477265 + -15783, // 197.227(deg) -0.481671 + -15927, // 197.402(deg) -0.486063 + -16070, // 197.578(deg) -0.490439 + -16213, // 197.754(deg) -0.494800 + -16356, // 197.93(deg) -0.499146 + -16497, // 198.105(deg) -0.503476 + -16639, // 198.281(deg) -0.507790 + -16780, // 198.457(deg) -0.512089 + -16920, // 198.633(deg) -0.516372 + -17060, // 198.809(deg) -0.520638 + -17199, // 198.984(deg) -0.524889 + -17338, // 199.16(deg) -0.529124 + -17476, // 199.336(deg) -0.533342 + -17614, // 199.512(deg) -0.537543 + -17751, // 199.688(deg) -0.541729 + -17887, // 199.863(deg) -0.545897 + -18024, // 200.039(deg) -0.550049 + -18159, // 200.215(deg) -0.554184 + -18294, // 200.391(deg) -0.558302 + -18428, // 200.566(deg) -0.562403 + -18562, // 200.742(deg) -0.566487 + -18695, // 200.918(deg) -0.570554 + -18828, // 201.094(deg) -0.574603 + -18960, // 201.27(deg) -0.578635 + -19092, // 201.445(deg) -0.582650 + -19223, // 201.621(deg) -0.586647 + -19353, // 201.797(deg) -0.590626 + -19483, // 201.973(deg) -0.594587 + -19612, // 202.148(deg) -0.598531 + -19741, // 202.324(deg) -0.602456 + -19869, // 202.5(deg) -0.606364 + -19996, // 202.676(deg) -0.610253 + -20123, // 202.852(deg) -0.614125 + -20249, // 203.027(deg) -0.617978 + -20375, // 203.203(deg) -0.621812 + -20500, // 203.379(deg) -0.625628 + -20625, // 203.555(deg) -0.629426 + -20748, // 203.73(deg) -0.633205 + -20872, // 203.906(deg) -0.636965 + -20994, // 204.082(deg) -0.640707 + -21116, // 204.258(deg) -0.644429 + -21238, // 204.434(deg) -0.648133 + -21358, // 204.609(deg) -0.651818 + -21478, // 204.785(deg) -0.655484 + -21598, // 204.961(deg) -0.659131 + -21717, // 205.137(deg) -0.662758 + -21835, // 205.312(deg) -0.666366 + -21953, // 205.488(deg) -0.669955 + -22070, // 205.664(deg) -0.673525 + -22186, // 205.84(deg) -0.677075 + -22302, // 206.016(deg) -0.680606 + -22417, // 206.191(deg) -0.684117 + -22531, // 206.367(deg) -0.687608 + -22645, // 206.543(deg) -0.691080 + -22758, // 206.719(deg) -0.694532 + -22870, // 206.895(deg) -0.697965 + -22982, // 207.07(deg) -0.701377 + -23093, // 207.246(deg) -0.704770 + -23204, // 207.422(deg) -0.708143 + -23314, // 207.598(deg) -0.711495 + -23423, // 207.773(deg) -0.714828 + -23532, // 207.949(deg) -0.718141 + -23639, // 208.125(deg) -0.721433 + -23747, // 208.301(deg) -0.724705 + -23853, // 208.477(deg) -0.727958 + -23959, // 208.652(deg) -0.731189 + -24064, // 208.828(deg) -0.734401 + -24169, // 209.004(deg) -0.737592 + -24273, // 209.18(deg) -0.740763 + -24376, // 209.355(deg) -0.743914 + -24479, // 209.531(deg) -0.747044 + -24581, // 209.707(deg) -0.750153 + -24682, // 209.883(deg) -0.753242 + -24782, // 210.059(deg) -0.756311 + -24882, // 210.234(deg) -0.759359 + -24981, // 210.41(deg) -0.762386 + -25080, // 210.586(deg) -0.765393 + -25178, // 210.762(deg) -0.768379 + -25275, // 210.938(deg) -0.771345 + -25371, // 211.113(deg) -0.774290 + -25467, // 211.289(deg) -0.777214 + -25562, // 211.465(deg) -0.780117 + -25657, // 211.641(deg) -0.783000 + -25751, // 211.816(deg) -0.785862 + -25844, // 211.992(deg) -0.788703 + -25936, // 212.168(deg) -0.791523 + -26028, // 212.344(deg) -0.794323 + -26119, // 212.52(deg) -0.797102 + -26209, // 212.695(deg) -0.799860 + -26299, // 212.871(deg) -0.802597 + -26388, // 213.047(deg) -0.805313 + -26476, // 213.223(deg) -0.808008 + -26564, // 213.398(deg) -0.810683 + -26651, // 213.574(deg) -0.813337 + -26737, // 213.75(deg) -0.815969 + -26823, // 213.926(deg) -0.818581 + -26908, // 214.102(deg) -0.821172 + -26992, // 214.277(deg) -0.823743 + -27075, // 214.453(deg) -0.826292 + -27158, // 214.629(deg) -0.828821 + -27240, // 214.805(deg) -0.831328 + -27322, // 214.98(deg) -0.833815 + -27403, // 215.156(deg) -0.836281 + -27483, // 215.332(deg) -0.838726 + -27562, // 215.508(deg) -0.841151 + -27641, // 215.684(deg) -0.843554 + -27719, // 215.859(deg) -0.845937 + -27797, // 216.035(deg) -0.848299 + -27873, // 216.211(deg) -0.850640 + -27949, // 216.387(deg) -0.852961 + -28025, // 216.562(deg) -0.855261 + -28099, // 216.738(deg) -0.857540 + -28173, // 216.914(deg) -0.859798 + -28247, // 217.09(deg) -0.862036 + -28319, // 217.266(deg) -0.864253 + -28391, // 217.441(deg) -0.866450 + -28463, // 217.617(deg) -0.868625 + -28533, // 217.793(deg) -0.870781 + -28603, // 217.969(deg) -0.872916 + -28672, // 218.145(deg) -0.875030 + -28741, // 218.32(deg) -0.877124 + -28809, // 218.496(deg) -0.879197 + -28876, // 218.672(deg) -0.881250 + -28943, // 218.848(deg) -0.883283 + -29009, // 219.023(deg) -0.885295 + -29074, // 219.199(deg) -0.887287 + -29139, // 219.375(deg) -0.889259 + -29203, // 219.551(deg) -0.891210 + -29266, // 219.727(deg) -0.893142 + -29329, // 219.902(deg) -0.895053 + -29391, // 220.078(deg) -0.896944 + -29452, // 220.254(deg) -0.898815 + -29513, // 220.43(deg) -0.900666 + -29573, // 220.605(deg) -0.902497 + -29632, // 220.781(deg) -0.904308 + -29691, // 220.957(deg) -0.906100 + -29749, // 221.133(deg) -0.907871 + -29806, // 221.309(deg) -0.909623 + -29863, // 221.484(deg) -0.911355 + -29919, // 221.66(deg) -0.913067 + -29974, // 221.836(deg) -0.914760 + -30029, // 222.012(deg) -0.916433 + -30083, // 222.188(deg) -0.918087 + -30137, // 222.363(deg) -0.919721 + -30190, // 222.539(deg) -0.921336 + -30242, // 222.715(deg) -0.922932 + -30294, // 222.891(deg) -0.924508 + -30345, // 223.066(deg) -0.926065 + -30395, // 223.242(deg) -0.927603 + -30445, // 223.418(deg) -0.929122 + -30494, // 223.594(deg) -0.930622 + -30543, // 223.77(deg) -0.932103 + -30591, // 223.945(deg) -0.933565 + -30638, // 224.121(deg) -0.935008 + -30685, // 224.297(deg) -0.936433 + -30731, // 224.473(deg) -0.937839 + -30776, // 224.648(deg) -0.939226 + -30821, // 224.824(deg) -0.940595 + -30865, // 225(deg) -0.941945 + -30909, // 225.176(deg) -0.943277 + -30952, // 225.352(deg) -0.944591 + -30994, // 225.527(deg) -0.945887 + -31036, // 225.703(deg) -0.947164 + -31077, // 225.879(deg) -0.948423 + -31118, // 226.055(deg) -0.949665 + -31158, // 226.23(deg) -0.950888 + -31198, // 226.406(deg) -0.952094 + -31237, // 226.582(deg) -0.953281 + -31275, // 226.758(deg) -0.954452 + -31313, // 226.934(deg) -0.955604 + -31350, // 227.109(deg) -0.956739 + -31387, // 227.285(deg) -0.957857 + -31423, // 227.461(deg) -0.958958 + -31458, // 227.637(deg) -0.960041 + -31493, // 227.812(deg) -0.961107 + -31527, // 227.988(deg) -0.962156 + -31561, // 228.164(deg) -0.963188 + -31595, // 228.34(deg) -0.964203 + -31627, // 228.516(deg) -0.965201 + -31659, // 228.691(deg) -0.966183 + -31691, // 228.867(deg) -0.967148 + -31722, // 229.043(deg) -0.968097 + -31753, // 229.219(deg) -0.969029 + -31783, // 229.395(deg) -0.969945 + -31812, // 229.57(deg) -0.970845 + -31841, // 229.746(deg) -0.971728 + -31870, // 229.922(deg) -0.972596 + -31897, // 230.098(deg) -0.973447 + -31925, // 230.273(deg) -0.974283 + -31952, // 230.449(deg) -0.975103 + -31978, // 230.625(deg) -0.975908 + -32004, // 230.801(deg) -0.976697 + -32029, // 230.977(deg) -0.977470 + -32054, // 231.152(deg) -0.978228 + -32078, // 231.328(deg) -0.978971 + -32102, // 231.504(deg) -0.979699 + -32126, // 231.68(deg) -0.980412 + -32149, // 231.855(deg) -0.981110 + -32171, // 232.031(deg) -0.981793 + -32193, // 232.207(deg) -0.982462 + -32214, // 232.383(deg) -0.983116 + -32235, // 232.559(deg) -0.983755 + -32256, // 232.734(deg) -0.984380 + -32276, // 232.91(deg) -0.984991 + -32295, // 233.086(deg) -0.985588 + -32314, // 233.262(deg) -0.986170 + -32333, // 233.438(deg) -0.986739 + -32351, // 233.613(deg) -0.987294 + -32369, // 233.789(deg) -0.987835 + -32386, // 233.965(deg) -0.988363 + -32403, // 234.141(deg) -0.988877 + -32419, // 234.316(deg) -0.989377 + -32435, // 234.492(deg) -0.989865 + -32451, // 234.668(deg) -0.990339 + -32466, // 234.844(deg) -0.990801 + -32481, // 235.02(deg) -0.991249 + -32495, // 235.195(deg) -0.991685 + -32509, // 235.371(deg) -0.992108 + -32522, // 235.547(deg) -0.992518 + -32535, // 235.723(deg) -0.992916 + -32548, // 235.898(deg) -0.993302 + -32560, // 236.074(deg) -0.993675 + -32572, // 236.25(deg) -0.994036 + -32584, // 236.426(deg) -0.994386 + -32595, // 236.602(deg) -0.994723 + -32605, // 236.777(deg) -0.995049 + -32616, // 236.953(deg) -0.995363 + -32625, // 237.129(deg) -0.995666 + -32635, // 237.305(deg) -0.995957 + -32644, // 237.48(deg) -0.996237 + -32653, // 237.656(deg) -0.996506 + -32661, // 237.832(deg) -0.996763 + -32670, // 238.008(deg) -0.997010 + -32677, // 238.184(deg) -0.997246 + -32685, // 238.359(deg) -0.997472 + -32692, // 238.535(deg) -0.997687 + -32698, // 238.711(deg) -0.997891 + -32705, // 238.887(deg) -0.998085 + -32711, // 239.062(deg) -0.998269 + -32716, // 239.238(deg) -0.998443 + -32722, // 239.414(deg) -0.998607 + -32727, // 239.59(deg) -0.998762 + -32732, // 239.766(deg) -0.998906 + -32736, // 239.941(deg) -0.999041 + -32740, // 240.117(deg) -0.999166 + -32744, // 240.293(deg) -0.999283 + -32747, // 240.469(deg) -0.999390 + -32751, // 240.645(deg) -0.999488 + -32754, // 240.82(deg) -0.999576 + -32756, // 240.996(deg) -0.999657 + -32759, // 241.172(deg) -0.999728 + -32761, // 241.348(deg) -0.999791 + -32762, // 241.523(deg) -0.999845 + -32764, // 241.699(deg) -0.999891 + -32765, // 241.875(deg) -0.999929 + -32766, // 242.051(deg) -0.999959 + -32767, // 242.227(deg) -0.999980 + -32767, // 242.402(deg) -0.999994 + -32768, // 242.578(deg) -1.000000 + -32767, // 242.754(deg) -0.999999 + -32767, // 242.93(deg) -0.999990 + -32767, // 243.105(deg) -0.999974 + -32766, // 243.281(deg) -0.999950 + -32765, // 243.457(deg) -0.999920 + -32764, // 243.633(deg) -0.999882 + -32762, // 243.809(deg) -0.999837 + -32760, // 243.984(deg) -0.999786 + -32759, // 244.16(deg) -0.999728 + -32756, // 244.336(deg) -0.999664 + -32754, // 244.512(deg) -0.999593 + -32752, // 244.688(deg) -0.999516 + -32749, // 244.863(deg) -0.999433 + -32746, // 245.039(deg) -0.999344 + -32743, // 245.215(deg) -0.999249 + -32740, // 245.391(deg) -0.999148 + -32736, // 245.566(deg) -0.999041 + -32732, // 245.742(deg) -0.998929 + -32729, // 245.918(deg) -0.998812 + -32725, // 246.094(deg) -0.998689 + -32720, // 246.27(deg) -0.998561 + -32716, // 246.445(deg) -0.998428 + -32711, // 246.621(deg) -0.998290 + -32707, // 246.797(deg) -0.998147 + -32702, // 246.973(deg) -0.997999 + -32697, // 247.148(deg) -0.997847 + -32692, // 247.324(deg) -0.997691 + -32687, // 247.5(deg) -0.997530 + -32681, // 247.676(deg) -0.997364 + -32676, // 247.852(deg) -0.997195 + -32670, // 248.027(deg) -0.997022 + -32664, // 248.203(deg) -0.996844 + -32658, // 248.379(deg) -0.996663 + -32652, // 248.555(deg) -0.996479 + -32646, // 248.73(deg) -0.996290 + -32640, // 248.906(deg) -0.996099 + -32633, // 249.082(deg) -0.995903 + -32627, // 249.258(deg) -0.995705 + -32620, // 249.434(deg) -0.995504 + -32613, // 249.609(deg) -0.995299 + -32607, // 249.785(deg) -0.995092 + -32600, // 249.961(deg) -0.994882 + -32593, // 250.137(deg) -0.994669 + -32586, // 250.312(deg) -0.994454 + -32579, // 250.488(deg) -0.994236 + -32571, // 250.664(deg) -0.994016 + -32564, // 250.84(deg) -0.993794 + -32557, // 251.016(deg) -0.993569 + -32549, // 251.191(deg) -0.993343 + -32542, // 251.367(deg) -0.993114 + -32534, // 251.543(deg) -0.992884 + -32527, // 251.719(deg) -0.992652 + -32519, // 251.895(deg) -0.992419 + -32511, // 252.07(deg) -0.992184 + -32504, // 252.246(deg) -0.991947 + -32496, // 252.422(deg) -0.991709 + -32488, // 252.598(deg) -0.991471 + -32480, // 252.773(deg) -0.991231 + -32472, // 252.949(deg) -0.990989 + -32464, // 253.125(deg) -0.990748 + -32456, // 253.301(deg) -0.990505 + -32448, // 253.477(deg) -0.990261 + -32440, // 253.652(deg) -0.990017 + -32432, // 253.828(deg) -0.989773 + -32424, // 254.004(deg) -0.989528 + -32416, // 254.18(deg) -0.989283 + -32408, // 254.355(deg) -0.989037 + -32400, // 254.531(deg) -0.988791 + -32392, // 254.707(deg) -0.988546 + -32384, // 254.883(deg) -0.988300 + -32376, // 255.059(deg) -0.988055 + -32368, // 255.234(deg) -0.987809 + -32360, // 255.41(deg) -0.987565 + -32352, // 255.586(deg) -0.987320 + -32344, // 255.762(deg) -0.987076 + -32336, // 255.938(deg) -0.986833 + -32328, // 256.113(deg) -0.986590 + -32320, // 256.289(deg) -0.986348 + -32312, // 256.465(deg) -0.986107 + -32304, // 256.641(deg) -0.985866 + -32297, // 256.816(deg) -0.985627 + -32289, // 256.992(deg) -0.985389 + -32281, // 257.168(deg) -0.985152 + -32273, // 257.344(deg) -0.984916 + -32266, // 257.52(deg) -0.984682 + -32258, // 257.695(deg) -0.984449 + -32250, // 257.871(deg) -0.984217 + -32243, // 258.047(deg) -0.983987 + -32235, // 258.223(deg) -0.983759 + -32228, // 258.398(deg) -0.983532 + -32221, // 258.574(deg) -0.983307 + -32213, // 258.75(deg) -0.983084 + -32206, // 258.926(deg) -0.982863 + -32199, // 259.102(deg) -0.982644 + -32192, // 259.277(deg) -0.982427 + -32185, // 259.453(deg) -0.982212 + -32178, // 259.629(deg) -0.981999 + -32171, // 259.805(deg) -0.981789 + -32164, // 259.98(deg) -0.981580 + -32157, // 260.156(deg) -0.981375 + -32151, // 260.332(deg) -0.981171 + -32144, // 260.508(deg) -0.980971 + -32137, // 260.684(deg) -0.980772 + -32131, // 260.859(deg) -0.980577 + -32125, // 261.035(deg) -0.980384 + -32118, // 261.211(deg) -0.980194 + -32112, // 261.387(deg) -0.980006 + -32106, // 261.562(deg) -0.979822 + -32100, // 261.738(deg) -0.979641 + -32095, // 261.914(deg) -0.979462 + -32089, // 262.09(deg) -0.979286 + -32083, // 262.266(deg) -0.979114 + -32078, // 262.441(deg) -0.978945 + -32072, // 262.617(deg) -0.978779 + -32067, // 262.793(deg) -0.978616 + -32062, // 262.969(deg) -0.978456 + -32056, // 263.145(deg) -0.978300 + -32051, // 263.32(deg) -0.978147 + -32047, // 263.496(deg) -0.977998 + -32042, // 263.672(deg) -0.977852 + -32037, // 263.848(deg) -0.977709 + -32033, // 264.023(deg) -0.977570 + -32028, // 264.199(deg) -0.977435 + -32024, // 264.375(deg) -0.977303 + -32020, // 264.551(deg) -0.977175 + -32015, // 264.727(deg) -0.977051 + -32012, // 264.902(deg) -0.976930 + -32008, // 265.078(deg) -0.976813 + -32004, // 265.254(deg) -0.976700 + -32000, // 265.43(deg) -0.976591 + -31997, // 265.605(deg) -0.976486 + -31994, // 265.781(deg) -0.976384 + -31990, // 265.957(deg) -0.976287 + -31987, // 266.133(deg) -0.976193 + -31984, // 266.309(deg) -0.976103 + -31982, // 266.484(deg) -0.976018 + -31979, // 266.66(deg) -0.975936 + -31976, // 266.836(deg) -0.975858 + -31974, // 267.012(deg) -0.975785 + -31972, // 267.188(deg) -0.975716 + -31970, // 267.363(deg) -0.975650 + -31968, // 267.539(deg) -0.975589 + -31966, // 267.715(deg) -0.975532 + -31964, // 267.891(deg) -0.975479 + -31962, // 268.066(deg) -0.975431 + -31961, // 268.242(deg) -0.975386 + -31960, // 268.418(deg) -0.975346 + -31958, // 268.594(deg) -0.975310 + -31957, // 268.77(deg) -0.975278 + -31956, // 268.945(deg) -0.975250 + -31956, // 269.121(deg) -0.975227 + -31955, // 269.297(deg) -0.975208 + -31955, // 269.473(deg) -0.975193 + -31954, // 269.648(deg) -0.975182 + -31954, // 269.824(deg) -0.975176 + -31954, // 270(deg) -0.975174 + -31954, // 270.176(deg) -0.975176 + -31954, // 270.352(deg) -0.975182 + -31955, // 270.527(deg) -0.975193 + -31955, // 270.703(deg) -0.975208 + -31956, // 270.879(deg) -0.975227 + -31956, // 271.055(deg) -0.975250 + -31957, // 271.23(deg) -0.975278 + -31958, // 271.406(deg) -0.975310 + -31960, // 271.582(deg) -0.975346 + -31961, // 271.758(deg) -0.975386 + -31962, // 271.934(deg) -0.975431 + -31964, // 272.109(deg) -0.975479 + -31966, // 272.285(deg) -0.975532 + -31968, // 272.461(deg) -0.975589 + -31970, // 272.637(deg) -0.975650 + -31972, // 272.812(deg) -0.975716 + -31974, // 272.988(deg) -0.975785 + -31976, // 273.164(deg) -0.975858 + -31979, // 273.34(deg) -0.975936 + -31982, // 273.516(deg) -0.976018 + -31984, // 273.691(deg) -0.976103 + -31987, // 273.867(deg) -0.976193 + -31990, // 274.043(deg) -0.976287 + -31994, // 274.219(deg) -0.976384 + -31997, // 274.395(deg) -0.976486 + -32000, // 274.57(deg) -0.976591 + -32004, // 274.746(deg) -0.976700 + -32008, // 274.922(deg) -0.976813 + -32012, // 275.098(deg) -0.976930 + -32015, // 275.273(deg) -0.977051 + -32020, // 275.449(deg) -0.977175 + -32024, // 275.625(deg) -0.977303 + -32028, // 275.801(deg) -0.977435 + -32033, // 275.977(deg) -0.977570 + -32037, // 276.152(deg) -0.977709 + -32042, // 276.328(deg) -0.977852 + -32047, // 276.504(deg) -0.977998 + -32051, // 276.68(deg) -0.978147 + -32056, // 276.855(deg) -0.978300 + -32062, // 277.031(deg) -0.978456 + -32067, // 277.207(deg) -0.978616 + -32072, // 277.383(deg) -0.978779 + -32078, // 277.559(deg) -0.978945 + -32083, // 277.734(deg) -0.979114 + -32089, // 277.91(deg) -0.979286 + -32095, // 278.086(deg) -0.979462 + -32100, // 278.262(deg) -0.979641 + -32106, // 278.438(deg) -0.979822 + -32112, // 278.613(deg) -0.980006 + -32118, // 278.789(deg) -0.980194 + -32125, // 278.965(deg) -0.980384 + -32131, // 279.141(deg) -0.980577 + -32137, // 279.316(deg) -0.980772 + -32144, // 279.492(deg) -0.980971 + -32151, // 279.668(deg) -0.981171 + -32157, // 279.844(deg) -0.981375 + -32164, // 280.02(deg) -0.981580 + -32171, // 280.195(deg) -0.981789 + -32178, // 280.371(deg) -0.981999 + -32185, // 280.547(deg) -0.982212 + -32192, // 280.723(deg) -0.982427 + -32199, // 280.898(deg) -0.982644 + -32206, // 281.074(deg) -0.982863 + -32213, // 281.25(deg) -0.983084 + -32221, // 281.426(deg) -0.983307 + -32228, // 281.602(deg) -0.983532 + -32235, // 281.777(deg) -0.983759 + -32243, // 281.953(deg) -0.983987 + -32250, // 282.129(deg) -0.984217 + -32258, // 282.305(deg) -0.984449 + -32266, // 282.48(deg) -0.984682 + -32273, // 282.656(deg) -0.984916 + -32281, // 282.832(deg) -0.985152 + -32289, // 283.008(deg) -0.985389 + -32297, // 283.184(deg) -0.985627 + -32304, // 283.359(deg) -0.985866 + -32312, // 283.535(deg) -0.986107 + -32320, // 283.711(deg) -0.986348 + -32328, // 283.887(deg) -0.986590 + -32336, // 284.062(deg) -0.986833 + -32344, // 284.238(deg) -0.987076 + -32352, // 284.414(deg) -0.987320 + -32360, // 284.59(deg) -0.987565 + -32368, // 284.766(deg) -0.987809 + -32376, // 284.941(deg) -0.988055 + -32384, // 285.117(deg) -0.988300 + -32392, // 285.293(deg) -0.988546 + -32400, // 285.469(deg) -0.988791 + -32408, // 285.645(deg) -0.989037 + -32416, // 285.82(deg) -0.989283 + -32424, // 285.996(deg) -0.989528 + -32432, // 286.172(deg) -0.989773 + -32440, // 286.348(deg) -0.990017 + -32448, // 286.523(deg) -0.990261 + -32456, // 286.699(deg) -0.990505 + -32464, // 286.875(deg) -0.990748 + -32472, // 287.051(deg) -0.990989 + -32480, // 287.227(deg) -0.991231 + -32488, // 287.402(deg) -0.991471 + -32496, // 287.578(deg) -0.991709 + -32504, // 287.754(deg) -0.991947 + -32511, // 287.93(deg) -0.992184 + -32519, // 288.105(deg) -0.992419 + -32527, // 288.281(deg) -0.992652 + -32534, // 288.457(deg) -0.992884 + -32542, // 288.633(deg) -0.993114 + -32549, // 288.809(deg) -0.993343 + -32557, // 288.984(deg) -0.993569 + -32564, // 289.16(deg) -0.993794 + -32571, // 289.336(deg) -0.994016 + -32579, // 289.512(deg) -0.994236 + -32586, // 289.688(deg) -0.994454 + -32593, // 289.863(deg) -0.994669 + -32600, // 290.039(deg) -0.994882 + -32607, // 290.215(deg) -0.995092 + -32613, // 290.391(deg) -0.995299 + -32620, // 290.566(deg) -0.995504 + -32627, // 290.742(deg) -0.995705 + -32633, // 290.918(deg) -0.995903 + -32640, // 291.094(deg) -0.996099 + -32646, // 291.27(deg) -0.996290 + -32652, // 291.445(deg) -0.996479 + -32658, // 291.621(deg) -0.996663 + -32664, // 291.797(deg) -0.996844 + -32670, // 291.973(deg) -0.997022 + -32676, // 292.148(deg) -0.997195 + -32681, // 292.324(deg) -0.997364 + -32687, // 292.5(deg) -0.997530 + -32692, // 292.676(deg) -0.997691 + -32697, // 292.852(deg) -0.997847 + -32702, // 293.027(deg) -0.997999 + -32707, // 293.203(deg) -0.998147 + -32711, // 293.379(deg) -0.998290 + -32716, // 293.555(deg) -0.998428 + -32720, // 293.73(deg) -0.998561 + -32725, // 293.906(deg) -0.998689 + -32729, // 294.082(deg) -0.998812 + -32732, // 294.258(deg) -0.998929 + -32736, // 294.434(deg) -0.999041 + -32740, // 294.609(deg) -0.999148 + -32743, // 294.785(deg) -0.999249 + -32746, // 294.961(deg) -0.999344 + -32749, // 295.137(deg) -0.999433 + -32752, // 295.312(deg) -0.999516 + -32754, // 295.488(deg) -0.999593 + -32756, // 295.664(deg) -0.999664 + -32759, // 295.84(deg) -0.999728 + -32760, // 296.016(deg) -0.999786 + -32762, // 296.191(deg) -0.999837 + -32764, // 296.367(deg) -0.999882 + -32765, // 296.543(deg) -0.999920 + -32766, // 296.719(deg) -0.999950 + -32767, // 296.895(deg) -0.999974 + -32767, // 297.07(deg) -0.999990 + -32767, // 297.246(deg) -0.999999 + -32768, // 297.422(deg) -1.000000 + -32767, // 297.598(deg) -0.999994 + -32767, // 297.773(deg) -0.999980 + -32766, // 297.949(deg) -0.999959 + -32765, // 298.125(deg) -0.999929 + -32764, // 298.301(deg) -0.999891 + -32762, // 298.477(deg) -0.999845 + -32761, // 298.652(deg) -0.999791 + -32759, // 298.828(deg) -0.999728 + -32756, // 299.004(deg) -0.999657 + -32754, // 299.18(deg) -0.999576 + -32751, // 299.355(deg) -0.999488 + -32747, // 299.531(deg) -0.999390 + -32744, // 299.707(deg) -0.999283 + -32740, // 299.883(deg) -0.999166 + -32736, // 300.059(deg) -0.999041 + -32732, // 300.234(deg) -0.998906 + -32727, // 300.41(deg) -0.998762 + -32722, // 300.586(deg) -0.998607 + -32716, // 300.762(deg) -0.998443 + -32711, // 300.938(deg) -0.998269 + -32705, // 301.113(deg) -0.998085 + -32698, // 301.289(deg) -0.997891 + -32692, // 301.465(deg) -0.997687 + -32685, // 301.641(deg) -0.997472 + -32677, // 301.816(deg) -0.997246 + -32670, // 301.992(deg) -0.997010 + -32661, // 302.168(deg) -0.996763 + -32653, // 302.344(deg) -0.996506 + -32644, // 302.52(deg) -0.996237 + -32635, // 302.695(deg) -0.995957 + -32625, // 302.871(deg) -0.995666 + -32616, // 303.047(deg) -0.995363 + -32605, // 303.223(deg) -0.995049 + -32595, // 303.398(deg) -0.994723 + -32584, // 303.574(deg) -0.994386 + -32572, // 303.75(deg) -0.994036 + -32560, // 303.926(deg) -0.993675 + -32548, // 304.102(deg) -0.993302 + -32535, // 304.277(deg) -0.992916 + -32522, // 304.453(deg) -0.992518 + -32509, // 304.629(deg) -0.992108 + -32495, // 304.805(deg) -0.991685 + -32481, // 304.98(deg) -0.991249 + -32466, // 305.156(deg) -0.990801 + -32451, // 305.332(deg) -0.990339 + -32435, // 305.508(deg) -0.989865 + -32419, // 305.684(deg) -0.989377 + -32403, // 305.859(deg) -0.988877 + -32386, // 306.035(deg) -0.988363 + -32369, // 306.211(deg) -0.987835 + -32351, // 306.387(deg) -0.987294 + -32333, // 306.562(deg) -0.986739 + -32314, // 306.738(deg) -0.986170 + -32295, // 306.914(deg) -0.985588 + -32276, // 307.09(deg) -0.984991 + -32256, // 307.266(deg) -0.984380 + -32235, // 307.441(deg) -0.983755 + -32214, // 307.617(deg) -0.983116 + -32193, // 307.793(deg) -0.982462 + -32171, // 307.969(deg) -0.981793 + -32149, // 308.145(deg) -0.981110 + -32126, // 308.32(deg) -0.980412 + -32102, // 308.496(deg) -0.979699 + -32078, // 308.672(deg) -0.978971 + -32054, // 308.848(deg) -0.978228 + -32029, // 309.023(deg) -0.977470 + -32004, // 309.199(deg) -0.976697 + -31978, // 309.375(deg) -0.975908 + -31952, // 309.551(deg) -0.975103 + -31925, // 309.727(deg) -0.974283 + -31897, // 309.902(deg) -0.973447 + -31870, // 310.078(deg) -0.972596 + -31841, // 310.254(deg) -0.971728 + -31812, // 310.43(deg) -0.970845 + -31783, // 310.605(deg) -0.969945 + -31753, // 310.781(deg) -0.969029 + -31722, // 310.957(deg) -0.968097 + -31691, // 311.133(deg) -0.967148 + -31659, // 311.309(deg) -0.966183 + -31627, // 311.484(deg) -0.965201 + -31595, // 311.66(deg) -0.964203 + -31561, // 311.836(deg) -0.963188 + -31527, // 312.012(deg) -0.962156 + -31493, // 312.188(deg) -0.961107 + -31458, // 312.363(deg) -0.960041 + -31423, // 312.539(deg) -0.958958 + -31387, // 312.715(deg) -0.957857 + -31350, // 312.891(deg) -0.956739 + -31313, // 313.066(deg) -0.955604 + -31275, // 313.242(deg) -0.954452 + -31237, // 313.418(deg) -0.953281 + -31198, // 313.594(deg) -0.952094 + -31158, // 313.77(deg) -0.950888 + -31118, // 313.945(deg) -0.949665 + -31077, // 314.121(deg) -0.948423 + -31036, // 314.297(deg) -0.947164 + -30994, // 314.473(deg) -0.945887 + -30952, // 314.648(deg) -0.944591 + -30909, // 314.824(deg) -0.943277 + -30865, // 315(deg) -0.941945 + -30821, // 315.176(deg) -0.940595 + -30776, // 315.352(deg) -0.939226 + -30731, // 315.527(deg) -0.937839 + -30685, // 315.703(deg) -0.936433 + -30638, // 315.879(deg) -0.935008 + -30591, // 316.055(deg) -0.933565 + -30543, // 316.23(deg) -0.932103 + -30494, // 316.406(deg) -0.930622 + -30445, // 316.582(deg) -0.929122 + -30395, // 316.758(deg) -0.927603 + -30345, // 316.934(deg) -0.926065 + -30294, // 317.109(deg) -0.924508 + -30242, // 317.285(deg) -0.922932 + -30190, // 317.461(deg) -0.921336 + -30137, // 317.637(deg) -0.919721 + -30083, // 317.812(deg) -0.918087 + -30029, // 317.988(deg) -0.916433 + -29974, // 318.164(deg) -0.914760 + -29919, // 318.34(deg) -0.913067 + -29863, // 318.516(deg) -0.911355 + -29806, // 318.691(deg) -0.909623 + -29749, // 318.867(deg) -0.907871 + -29691, // 319.043(deg) -0.906100 + -29632, // 319.219(deg) -0.904308 + -29573, // 319.395(deg) -0.902497 + -29513, // 319.57(deg) -0.900666 + -29452, // 319.746(deg) -0.898815 + -29391, // 319.922(deg) -0.896944 + -29329, // 320.098(deg) -0.895053 + -29266, // 320.273(deg) -0.893142 + -29203, // 320.449(deg) -0.891210 + -29139, // 320.625(deg) -0.889259 + -29074, // 320.801(deg) -0.887287 + -29009, // 320.977(deg) -0.885295 + -28943, // 321.152(deg) -0.883283 + -28876, // 321.328(deg) -0.881250 + -28809, // 321.504(deg) -0.879197 + -28741, // 321.68(deg) -0.877124 + -28672, // 321.855(deg) -0.875030 + -28603, // 322.031(deg) -0.872916 + -28533, // 322.207(deg) -0.870781 + -28463, // 322.383(deg) -0.868625 + -28391, // 322.559(deg) -0.866450 + -28319, // 322.734(deg) -0.864253 + -28247, // 322.91(deg) -0.862036 + -28173, // 323.086(deg) -0.859798 + -28099, // 323.262(deg) -0.857540 + -28025, // 323.438(deg) -0.855261 + -27949, // 323.613(deg) -0.852961 + -27873, // 323.789(deg) -0.850640 + -27797, // 323.965(deg) -0.848299 + -27719, // 324.141(deg) -0.845937 + -27641, // 324.316(deg) -0.843554 + -27562, // 324.492(deg) -0.841151 + -27483, // 324.668(deg) -0.838726 + -27403, // 324.844(deg) -0.836281 + -27322, // 325.02(deg) -0.833815 + -27240, // 325.195(deg) -0.831328 + -27158, // 325.371(deg) -0.828821 + -27075, // 325.547(deg) -0.826292 + -26992, // 325.723(deg) -0.823743 + -26908, // 325.898(deg) -0.821172 + -26823, // 326.074(deg) -0.818581 + -26737, // 326.25(deg) -0.815969 + -26651, // 326.426(deg) -0.813337 + -26564, // 326.602(deg) -0.810683 + -26476, // 326.777(deg) -0.808008 + -26388, // 326.953(deg) -0.805313 + -26299, // 327.129(deg) -0.802597 + -26209, // 327.305(deg) -0.799860 + -26119, // 327.48(deg) -0.797102 + -26028, // 327.656(deg) -0.794323 + -25936, // 327.832(deg) -0.791523 + -25844, // 328.008(deg) -0.788703 + -25751, // 328.184(deg) -0.785862 + -25657, // 328.359(deg) -0.783000 + -25562, // 328.535(deg) -0.780117 + -25467, // 328.711(deg) -0.777214 + -25371, // 328.887(deg) -0.774290 + -25275, // 329.062(deg) -0.771345 + -25178, // 329.238(deg) -0.768379 + -25080, // 329.414(deg) -0.765393 + -24981, // 329.59(deg) -0.762386 + -24882, // 329.766(deg) -0.759359 + -24782, // 329.941(deg) -0.756311 + -24682, // 330.117(deg) -0.753242 + -24581, // 330.293(deg) -0.750153 + -24479, // 330.469(deg) -0.747044 + -24376, // 330.645(deg) -0.743914 + -24273, // 330.82(deg) -0.740763 + -24169, // 330.996(deg) -0.737592 + -24064, // 331.172(deg) -0.734401 + -23959, // 331.348(deg) -0.731189 + -23853, // 331.523(deg) -0.727958 + -23747, // 331.699(deg) -0.724705 + -23639, // 331.875(deg) -0.721433 + -23532, // 332.051(deg) -0.718141 + -23423, // 332.227(deg) -0.714828 + -23314, // 332.402(deg) -0.711495 + -23204, // 332.578(deg) -0.708143 + -23093, // 332.754(deg) -0.704770 + -22982, // 332.93(deg) -0.701377 + -22870, // 333.105(deg) -0.697965 + -22758, // 333.281(deg) -0.694532 + -22645, // 333.457(deg) -0.691080 + -22531, // 333.633(deg) -0.687608 + -22417, // 333.809(deg) -0.684117 + -22302, // 333.984(deg) -0.680606 + -22186, // 334.16(deg) -0.677075 + -22070, // 334.336(deg) -0.673525 + -21953, // 334.512(deg) -0.669955 + -21835, // 334.688(deg) -0.666366 + -21717, // 334.863(deg) -0.662758 + -21598, // 335.039(deg) -0.659131 + -21478, // 335.215(deg) -0.655484 + -21358, // 335.391(deg) -0.651818 + -21238, // 335.566(deg) -0.648133 + -21116, // 335.742(deg) -0.644429 + -20994, // 335.918(deg) -0.640707 + -20872, // 336.094(deg) -0.636965 + -20748, // 336.27(deg) -0.633205 + -20625, // 336.445(deg) -0.629426 + -20500, // 336.621(deg) -0.625628 + -20375, // 336.797(deg) -0.621812 + -20249, // 336.973(deg) -0.617978 + -20123, // 337.148(deg) -0.614125 + -19996, // 337.324(deg) -0.610253 + -19869, // 337.5(deg) -0.606364 + -19741, // 337.676(deg) -0.602456 + -19612, // 337.852(deg) -0.598531 + -19483, // 338.027(deg) -0.594587 + -19353, // 338.203(deg) -0.590626 + -19223, // 338.379(deg) -0.586647 + -19092, // 338.555(deg) -0.582650 + -18960, // 338.73(deg) -0.578635 + -18828, // 338.906(deg) -0.574603 + -18695, // 339.082(deg) -0.570554 + -18562, // 339.258(deg) -0.566487 + -18428, // 339.434(deg) -0.562403 + -18294, // 339.609(deg) -0.558302 + -18159, // 339.785(deg) -0.554184 + -18024, // 339.961(deg) -0.550049 + -17887, // 340.137(deg) -0.545897 + -17751, // 340.312(deg) -0.541729 + -17614, // 340.488(deg) -0.537543 + -17476, // 340.664(deg) -0.533342 + -17338, // 340.84(deg) -0.529124 + -17199, // 341.016(deg) -0.524889 + -17060, // 341.191(deg) -0.520638 + -16920, // 341.367(deg) -0.516372 + -16780, // 341.543(deg) -0.512089 + -16639, // 341.719(deg) -0.507790 + -16497, // 341.895(deg) -0.503476 + -16356, // 342.07(deg) -0.499146 + -16213, // 342.246(deg) -0.494800 + -16070, // 342.422(deg) -0.490439 + -15927, // 342.598(deg) -0.486063 + -15783, // 342.773(deg) -0.481671 + -15639, // 342.949(deg) -0.477265 + -15494, // 343.125(deg) -0.472843 + -15348, // 343.301(deg) -0.468407 + -15202, // 343.477(deg) -0.463956 + -15056, // 343.652(deg) -0.459490 + -14909, // 343.828(deg) -0.455010 + -14762, // 344.004(deg) -0.450515 + -14614, // 344.18(deg) -0.446007 + -14466, // 344.355(deg) -0.441484 + -14317, // 344.531(deg) -0.436947 + -14168, // 344.707(deg) -0.432396 + -14019, // 344.883(deg) -0.427832 + -13869, // 345.059(deg) -0.423254 + -13718, // 345.234(deg) -0.418663 + -13567, // 345.41(deg) -0.414058 + -13416, // 345.586(deg) -0.409440 + -13264, // 345.762(deg) -0.404809 + -13112, // 345.938(deg) -0.400165 + -12960, // 346.113(deg) -0.395508 + -12807, // 346.289(deg) -0.390839 + -12653, // 346.465(deg) -0.386157 + -12499, // 346.641(deg) -0.381463 + -12345, // 346.816(deg) -0.376756 + -12190, // 346.992(deg) -0.372037 + -12035, // 347.168(deg) -0.367307 + -11880, // 347.344(deg) -0.362564 + -11724, // 347.52(deg) -0.357810 + -11568, // 347.695(deg) -0.353045 + -11412, // 347.871(deg) -0.348268 + -11255, // 348.047(deg) -0.343479 + -11097, // 348.223(deg) -0.338680 + -10940, // 348.398(deg) -0.333870 + -10782, // 348.574(deg) -0.329048 + -10623, // 348.75(deg) -0.324217 + -10465, // 348.926(deg) -0.319374 + -10306, // 349.102(deg) -0.314522 + -10146, // 349.277(deg) -0.309659 + -9987, // 349.453(deg) -0.304786 + -9827, // 349.629(deg) -0.299903 + -9666, // 349.805(deg) -0.295010 + -9506, // 349.98(deg) -0.290108 + -9345, // 350.156(deg) -0.285196 + -9184, // 350.332(deg) -0.280275 + -9022, // 350.508(deg) -0.275345 + -8860, // 350.684(deg) -0.270406 + -8698, // 350.859(deg) -0.265457 + -8536, // 351.035(deg) -0.260501 + -8373, // 351.211(deg) -0.255535 + -8210, // 351.387(deg) -0.250562 + -8047, // 351.562(deg) -0.245580 + -7883, // 351.738(deg) -0.240590 + -7719, // 351.914(deg) -0.235592 + -7555, // 352.09(deg) -0.230587 + -7391, // 352.266(deg) -0.225573 + -7227, // 352.441(deg) -0.220553 + -7062, // 352.617(deg) -0.215525 + -6897, // 352.793(deg) -0.210490 + -6732, // 352.969(deg) -0.205448 + -6566, // 353.145(deg) -0.200400 + -6401, // 353.32(deg) -0.195344 + -6235, // 353.496(deg) -0.190283 + -6069, // 353.672(deg) -0.185215 + -5902, // 353.848(deg) -0.180141 + -5736, // 354.023(deg) -0.175061 + -5569, // 354.199(deg) -0.169975 + -5402, // 354.375(deg) -0.164884 + -5235, // 354.551(deg) -0.159787 + -5068, // 354.727(deg) -0.154685 + -4901, // 354.902(deg) -0.149577 + -4733, // 355.078(deg) -0.144465 + -4566, // 355.254(deg) -0.139348 + -4398, // 355.43(deg) -0.134226 + -4230, // 355.605(deg) -0.129100 + -4062, // 355.781(deg) -0.123970 + -3894, // 355.957(deg) -0.118836 + -3725, // 356.133(deg) -0.113697 + -3557, // 356.309(deg) -0.108555 + -3388, // 356.484(deg) -0.103409 + -3219, // 356.66(deg) -0.098260 + -3050, // 356.836(deg) -0.093107 + -2882, // 357.012(deg) -0.087952 + -2712, // 357.188(deg) -0.082793 + -2543, // 357.363(deg) -0.077632 + -2374, // 357.539(deg) -0.072468 + -2205, // 357.715(deg) -0.067302 + -2035, // 357.891(deg) -0.062134 + -1866, // 358.066(deg) -0.056963 + -1697, // 358.242(deg) -0.051791 + -1527, // 358.418(deg) -0.046617 + -1357, // 358.594(deg) -0.041441 + -1188, // 358.77(deg) -0.036264 + -1018, // 358.945(deg) -0.031085 + -848, // 359.121(deg) -0.025906 + -679, // 359.297(deg) -0.020726 + -509, // 359.473(deg) -0.015545 + -339, // 359.648(deg) -0.010364 + -169, // 359.824(deg) -0.005182 +}; diff --git a/cdc-test/power.c b/cdc-test/power.c new file mode 100644 index 0000000..9bd73b3 --- /dev/null +++ b/cdc-test/power.c @@ -0,0 +1,81 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "power.h" + +//------------------------------------------------------------------------------ +/// Put the CPU in 32kHz, disable PLL, main oscillator +/// Put voltage regulator in standby mode +//------------------------------------------------------------------------------ +void LowPowerMode(void) +{ + // MCK=48MHz to MCK=32kHz + // MCK = SLCK/2 : change source first from 48 000 000 to 18. / 2 = 9M + AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2; + while( !( AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY ) ); + // MCK=SLCK : then change prescaler + AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_CSS_SLOW_CLK; + while( !( AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY ) ); + // disable PLL + AT91C_BASE_PMC->PMC_PLLR = 0; + // Disable Main Oscillator + AT91C_BASE_PMC->PMC_MOR = 0; + + // Voltage regulator in standby mode : Enable VREG Low Power Mode + AT91C_BASE_VREG->VREG_MR |= AT91C_VREG_PSTDBY; + + PMC_DisableProcessorClock(); +} +//------------------------------------------------------------------------------ +/// Put voltage regulator in normal mode +/// Return the CPU to normal speed 48MHz, enable PLL, main oscillator +//------------------------------------------------------------------------------ +void NormalPowerMode(void) +{ + // Voltage regulator in normal mode : Disable VREG Low Power Mode + AT91C_BASE_VREG->VREG_MR &= ~AT91C_VREG_PSTDBY; + + // MCK=32kHz to MCK=48MHz + // enable Main Oscillator + AT91C_BASE_PMC->PMC_MOR = (( (AT91C_CKGR_OSCOUNT & (0x06 <<8)) | AT91C_CKGR_MOSCEN )); + while( !( AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS ) ); + + // enable PLL@96MHz + AT91C_BASE_PMC->PMC_PLLR = ((AT91C_CKGR_DIV & 0x0E) | + (AT91C_CKGR_PLLCOUNT & (28<<8)) | + (AT91C_CKGR_MUL & (0x48<<16))); + while( !( AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK ) ); + while( !( AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY ) ); + AT91C_BASE_CKGR->CKGR_PLLR |= AT91C_CKGR_USBDIV_1 ; + // MCK=SLCK/2 : change prescaler first + AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2; + while( !( AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY ) ); + // MCK=PLLCK/2 : then change source + AT91C_BASE_PMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK ; + while( !( AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY ) ); +} + +//------------------------------------------------------------------------------ +// Callbacks re-implementation +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +/// Invoked when the USB device leaves the Suspended state. By default, +/// configures the LEDs. +//------------------------------------------------------------------------------ +void USBDCallbacks_Resumed(void) +{ +} + +//------------------------------------------------------------------------------ +/// Invoked when the USB device gets suspended. By default, turns off all LEDs. +//------------------------------------------------------------------------------ +void USBDCallbacks_Suspended(void) +{ +} diff --git a/cdc-test/power.h b/cdc-test/power.h new file mode 100644 index 0000000..5e06225 --- /dev/null +++ b/cdc-test/power.h @@ -0,0 +1,7 @@ +#ifndef __POWER_H__ +#define __POWER_H__ + +void LowPowerMode(void); +void NormalPowerMode(void); + +#endif \ No newline at end of file diff --git a/cdc-test/registerFPGA.h b/cdc-test/registerFPGA.h new file mode 100644 index 0000000..8465b5b --- /dev/null +++ b/cdc-test/registerFPGA.h @@ -0,0 +1,62 @@ + +#ifndef __REGISTER_FPGA_H__ +#define __REGISTER_FPGA_H__ + + +typedef volatile unsigned short TVREG; + +// Mapping(0x00-0x7F) +// 0x00-0x0F General Information +// 0x10-0x1F Motor1 Control Registers +// 0x20-0x2F Motor2 Control Registers + +typedef struct _REG_GENERAL +{ + TVREG ID; // 0x0 FPGA識別用 + TVREG OUTPUT_ENABLE; // 0x1 モータ出力有効/無効 + TVREG Reserved0[6]; // 0x2-0x7 予約 + struct + { + TVREG COUNT_ENABLE; // 0x8 三角波カウント有効/無効 + TVREG HALF_PERIOD; // 0x9 PWM半周期クロック数(48MHz) + TVREG COUNT; // 0xA 三角波カウント値 + TVREG DEADTIME; // 0xB デッドタイム生成長 + } PWM; + TVREG Reserved1[4]; // 0xC-0xF 予約 +} REG_GENERAL; + +typedef struct _REG_MOTOR +{ + TVREG ENCODER; // 0x0 エンコーダ4逓倍アップダウンカウント値 + TVREG Reserved0[2]; // 0x1-0x2 予約 + struct{ + unsigned HALL : 3;// - ホール素子状態 + unsigned Reserved :12;// - 予約 + unsigned Z : 1;// - Z相信号 + } __attribute__ ((packed)) ROT_DETECTER; // 0x3 絶対角信号 + struct{ + TVREG H; // ハイサイドコンパレートレベル + TVREG L; // ハイサイドコンパレートレベル + } PWM[3]; // 0x4-0x9 + TVREG Reserved1[5]; // 0xA-0xE 予約 + TVREG INVERT; // 0xF 反転 +} REG_MOTOR; + +typedef struct _THEVA_REG{ + REG_GENERAL GENERAL; // 0x00 + TVREG Reserved0[16]; // 0x10-0x1F + REG_MOTOR MOTOR[2]; // 0x20-0x3F + TVREG Reserved1[63]; // 0x40-0x6F + TVREG PORT[16]; // 0x70-0x7F +} THEVA_REG; + + +#define THEVA (*((THEVA_REG*)0x10000000)) + + +#define HALL_U (0x01) +#define HALL_V (0x02) +#define HALL_W (0x04) +#define HALL_Z (0x80) + +#endif diff --git a/icart1.param b/icart1.param new file mode 100644 index 0000000..712cc05 --- /dev/null +++ b/icart1.param @@ -0,0 +1,43 @@ + VERSION 1.00000000 + TORQUE_UNIT 100000.00000000 #[Integer Nm/Nm] + VOLT_UNIT 1000.00000000 #[Integer V/V] + METER_UNIT 1000.00000000 #[Integer m/m] + ANPERE_UNIT 1000.00000000 #[Integer A/A] + AVEL_UNIT 1.00000000 #[Integer rad/s / rad/s] + PWM_MAX 2400.00000000 #(28000000/DUTY) + COUNT_REV 800.00000000 #[Counts/rev] + VOLT 24.00000000 #[V] + CYCLE 0.00100000 #[s] + GEAR 150.00000000 #[in/out] 5*30 + MOTOR_R 0.80000000 #[ohm] + MOTOR_TC 0.01693498 #[Nm/A] + MOTOR_VC 563.88000000 #[rpm/V] + MOTOR_VTC 490000.00000000 # + RADIUS_R 0.20000000 #[m] + RADIUS_L 0.20000000 #[m] + TREAD 0.34080000 #[m] + CONTROL_CYCLE 0.02000000 #[s] + MAX_VEL 0.50000000 #[m/s] + MAX_W 3.14000000 #[rad/s] + MAX_ACC_V 1.00000000 #[m/ss] + MAX_ACC_W 6.28000000 #[rad/ss] + MAX_CENTRI_ACC 2.45000000 #0.25G + L_C1 0.01000000 # + L_K1 800.00000000 # + L_K2 300.00000000 # + L_K3 200.00000000 # + L_DIST 0.60000000 # + GAIN_KP 800.00000000 #PI control parameter Kp + GAIN_KI 1.00000000 #PI control parameter Ki + TORQUE_MAX 0.30000000 #[Nm] + TORQUE_NEWTON 0.00000000 #[Nm] + TORQUE_VISCOS 0.00000000 #[Nm/(count/1ms)] + INTEGRAL_MAX 10000.00000000 # + GAIN_A 256.00000000 #PWS parameter A + GAIN_B 256.00000000 #PWS parameter B + GAIN_C 0.00000000 #PWS parameter C + GAIN_D 0.00000000 #PWS parameter D + GAIN_E 0.00000000 #PWS parameter E + GAIN_F 0.00000000 #PWS parameter F + TORQUE_OFFSET 0.00000000 #[Nm] + MASS 10.00000000 #[kg] diff --git a/resources/gdb/at91cap9-dk-bcram.gdb b/resources/gdb/at91cap9-dk-bcram.gdb new file mode 100644 index 0000000..faf8210 --- /dev/null +++ b/resources/gdb/at91cap9-dk-bcram.gdb @@ -0,0 +1,60 @@ +# BCRAM initialization script for the AT91CAP9-DK +#------------------------------------------------ +# Configure master clock +echo Configuring the master clock...\n +# Enable main oscillator +set *0xFFFFFC20 = 0x00004001 +while ((*0xFFFFFC68 & 0x1) == 0) +end + +# set PLLA to 200MHz +set *0xFFFFFC28 = 0x2031BF03 +while ((*0xFFFFFC68 & 0x2) == 0) +end + +# Select prescaler +set *0xFFFFFC30 = 0x00000100 +while ((*0xFFFFFC68 & 0x8) == 0) +end + +# Select master clock +set *0xFFFFFC30 = 0x00000102 +while ((*0xFFFFFC68 & 0x8) == 0) +end + +echo Master clock ok.\n +echo Configuring the BCRAM controller...\n + +# Select EBI CSA +set *0xFFFFEB20 = 0x00000002 + +# Configure A23 and A24 PIO as Periph A +set *0xFFFFF804 = 0x00003000 +set *0xFFFFF870 = 0x00003000 + +# The Cellular Ram memory type must be set in the BCRAMC Memory Device Register. +# Burst CellularRAM Version 1.5 +set *0xFFFFE410 = 0x00000001 + +# Temperature compensated self refresh (TCSR) and partial array +# refresh (PAR) must be set in the BCRAMC Low Power register. +set *0xFFFFE40C = 0x00000000 + +# High Speed Register +set *0xFFFFE408 = 0x00000000 + +# Asynchronous timings (TCKA, TCRE..) must be set in the BCRAMC Timing Register. +set *0xFFFFE404 = 0x00000023 + +# Cellular Ram features must be set in the HBCRAMC Configuration Register: +# number rows, latency, drive strength (DS), the data bus width and cram_enabled bit must be high. +set *0xFFFFE400 = 0x00001131 + +# __sleep(100000); + +# Perform a write to the Cellular Ram device and the Bus Configuration Register (BCR) and +# Refresh Configuration Register (RCR) are programmed automatically. +# Dummy write to access BCRAM : validate preceeding command +set *0x20000000 = 0x00000000 + +echo BCRAM configuration ok.\n diff --git a/resources/gdb/at91cap9-dk-ddram.gdb b/resources/gdb/at91cap9-dk-ddram.gdb new file mode 100644 index 0000000..7671cc7 --- /dev/null +++ b/resources/gdb/at91cap9-dk-ddram.gdb @@ -0,0 +1,112 @@ +# SDRAM initialization script for the AT91CAP9-DK +#------------------------------------------------ +# Configure master clock +echo Configuring the master clock...\n +# Enable main oscillator +set *0xFFFFFC20 = 0x00004001 +while ((*0xFFFFFC68 & 0x1) == 0) +end + +# set PLLA to 200MHz +set *0xFFFFFC28 = 0x2031BF03 +while ((*0xFFFFFC68 & 0x2) == 0) +end + +# Select prescaler +set *0xFFFFFC30 = 0x00000100 +while ((*0xFFFFFC68 & 0x8) == 0) +end + +# Select master clock +set *0xFFFFFC30 = 0x00000102 +while ((*0xFFFFFC68 & 0x8) == 0) +end + +echo Master clock ok.\n +echo Configuring the DDRAM controller...\n + +# AT91C_BASE_PMC->PMC_SCER = (0x1 << 2); +set *0xFFFFFC00 = 0x00000002 + +# Ensure that Matrix is connected to enable fetch Data & PDC +set *0xFFFFEB00 = 0x00000007 + +# First, enable the clock of the PIO / Enable PIO A B C D +set *0xFFFFFC00 = 0x00000085 + +#------------------------------------------------------------------------------------ + +# Memory Device Register +# Mobile DDRAM type | 16bit MODE +# ddrc->SDDRC_MDR = 0x00000013; +set *0xFFFFE61C = 0x00000013 + +# Configuration Register +# Weak driver strength(1) | Disable DLL reset(0) | SDRAM CAS = 3 | row = 13 | column = 9 +# ddrc->SDDRC_CR = 0x00000138; +set *0xFFFFE608 = 0x00000138 + +# Timing 0 Parameter Register +# tmrd = 2 | twtr = 1 | trrd = 2 | trrd = 2 | trp = 3 | trc = 8 | twr = 2 | trcd = 3 | tras = 5 +# ddrc->SDDRC_T0PR = 0x21238235; +set *0xFFFFE60C = 0x21238235 + +# Timing 1 Parameter Register +# txp = 4 | txsrd = 0xC | txsnr = 0xC | trfc = 9 +# ddrc->SDDRC_T1PR = 0x040C0C09; +set *0xFFFFE610 = 0x040D0D09 + +# Low-power Register +# Low power register => Low-power is inhibited +# all bank refresh during self refresh (PASR = b000) +# ddrc->SDDRC_LPR = 0x00000000; +set *0xFFFFE618 = 0x00000000 + +#------------------------------------------------------------------------------------ + +# NOP command +# ddrc->SDDRC_MR = 0x00000001; +set *0xFFFFE600 = 0x00000001 +set *0x70000000 = 0x00000000 + +# Precharge All Banks command +# ddrc->SDDRC_MR = 0x00000002; +set *0xFFFFE600 = 0x00000002 +set *0x70000000 = 0x00000000 + +# AutoRefresh command +# ddrc->SDDRC_MR = 0x00000004; +set *0xFFFFE600 = 0x00000004 +set *0x70000000 = 0x00000000 + +# AutoRefresh command +# ddrc->SDDRC_MR = 0x00000004; +set *0xFFFFE600 = 0x00000004 +set *0x70000000 = 0x00000000 + +#---------------------------------------------------------------------------------- + +# Mode Register Set command +# ddrc->SDDRC_MR = 0x00000003; +set *0xFFFFE600 = 0x00000003 +set *0x70000000 = 0x00000000 + +# Extended Mode Register Set command +# ddrc->SDDRC_MR = 0x00000005; +set *0xFFFFE600 = 0x00000005 +set *0x100000 = *0x71000000 + +# Set Normal mode +# ddrc->SDDRC_MR = 0x00000000; +set *0xFFFFE600 = 0x00000000 +set *0x100000 = *0x70000000 +set *0x70000000 = 0x00000000 + +# Set Refresh Timer : ((64 x 10^-3)/8192) x 48 x 10^6 ---> 375 for 48 MHz +# Set Refresh Timer : ((64 x 10^-3)/8192) x 100 x 10^6 ---> 781 for 100 MHz +set *0xFFFFE604 = 0x0000044C + +# High speed register : Optimization is enabled +set *0xFFFFE614 = 0x00000000 + +echo DDRAM configuration ok.\n diff --git a/resources/gdb/at91cap9-dk-sdram.gdb b/resources/gdb/at91cap9-dk-sdram.gdb new file mode 100644 index 0000000..87bdca6 --- /dev/null +++ b/resources/gdb/at91cap9-dk-sdram.gdb @@ -0,0 +1,80 @@ +# SDRAM initialization script for the AT91CAP9-DK +#------------------------------------------------ +# Configure master clock +echo Configuring the master clock...\n +# Enable main oscillator +set *0xFFFFFC20 = 0x00004001 +while ((*0xFFFFFC68 & 0x1) == 0) +end + +# set PLLA to 200MHz +set *0xFFFFFC28 = 0x2031BF03 +while ((*0xFFFFFC68 & 0x2) == 0) +end + +# Select prescaler +set *0xFFFFFC30 = 0x00000100 +while ((*0xFFFFFC68 & 0x8) == 0) +end + +# Select master clock +set *0xFFFFFC30 = 0x00000102 +while ((*0xFFFFFC68 & 0x8) == 0) +end + +echo Master clock ok.\n +echo Configuring the SDRAM controller...\n + +# configure pins Sdram +set *0xFFFFF870 = 0xFFFF0000 +set *0xFFFFF874 = 0x00000000 +set *0xFFFFF804 = 0xFFFF0000 + +# 32bit MODE; SDRAM type +set *0xFFFFE61C = 0x00000000 + +# row = 13 = column = 9 SDRAM CAS = 3 +set *0xFFFFE608 = 0x00000039 + +# Low power register => Low-power is inhibited +set *0xFFFFE618 = 0x00000000 + +# NOP command +set *0xFFFFE600 = 0x1 +set *0x70000000 = 0 + +# NOP command +set *0xFFFFE600 = 0x1 +set *0x70000000 = 0 + +# NOP command +set *0xFFFFE600 = 0x1 +set *0x70000000 = 0 + +# Precharge All Banks command +set *0xFFFFE600 = 0x2 +set *0x70000000 = 0 + +# AutoRefresh command +set *0xFFFFE600 = 0x4 +set *0x70000000 = 0 + +# AutoRefresh command +set *0xFFFFE600 = 0x4 +set *0x70000000 = 0 + +# set MR JEDEC compliant : Load mode Register command +set *0xFFFFE600 = 0x3 +set *0x70000000 = 0 + +# set Normal mode : Any access to the DDRSDRAMC is decoded normally +set *0xFFFFE600 = 0x0 +set *0x70000000 = 0 + +# set Refresh Timer (ex: ((64 x 10^-3)/8192) x 50 x 10^6 ) # 781 for 100 MHz +set *0xFFFFE604 = 781 + +# High speed register : Optimization is disabled +set *0xFFFFE614 = 0x2 + +echo SDRAM configuration ok.\n diff --git a/resources/gdb/at91cap9-dk-sram.gdb b/resources/gdb/at91cap9-dk-sram.gdb new file mode 100644 index 0000000..d72494d --- /dev/null +++ b/resources/gdb/at91cap9-dk-sram.gdb @@ -0,0 +1,25 @@ +# MCK initialization script for the AT91CAP9-DK +#------------------------------------------------ + +echo Configuring the master clock...\n +# Enable main oscillator +set *0xFFFFFC20 = 0x00004001 +while ((*0xFFFFFC68 & 0x1) == 0) +end + +# Set PLLA to 200MHz +set *0xFFFFFC28 = 0x2031BF03 +while ((*0xFFFFFC68 & 0x2) == 0) +end + +# Select prescaler +set *0xFFFFFC30 = 0x00000100 +while ((*0xFFFFFC68 & 0x8) == 0) +end + +# Select master clock +set *0xFFFFFC30 = 0x00000102 +while ((*0xFFFFFC68 & 0x8) == 0) +end + +echo Master clock ok.\n diff --git a/resources/gdb/at91sam7se-ek-sdram.gdb b/resources/gdb/at91sam7se-ek-sdram.gdb new file mode 100644 index 0000000..3fba949 --- /dev/null +++ b/resources/gdb/at91sam7se-ek-sdram.gdb @@ -0,0 +1,78 @@ +# SDRAM initialization script for the AT91SAM7SE +#----------------------------------------------- +# Configure master clock +echo Configuring the master clock...\n +# Enable main oscillator +set *0xFFFFFC20 = 0x00004001 +while ((*0xFFFFFC68 & 0x1) == 0) +end + +# Enable PLL +set *0xFFFFFC2C = 0x1048100E +while ((*0xFFFFFC68 & 0x4) == 0) +end + +# Select prescaler value +set *0xFFFFFC30 = 0x00000004 +while ((*0xFFFFFC68 & 0x8) == 0) +end + +# Select master clock +set *0xFFFFFC30 = 0x00000007 +while ((*0xFFFFFC68 & 0x8) == 0) +end + +echo Master clock ok.\n +echo Configuring the SDRAM controller...\n + +# Enable EBI chip select for the SDRAM +set *0xFFFFFF80 = 0x2 + +# Enable EBI pios +# PMC +set *0xFFFFFC10 = 0x1C +# PIOA +set *0xFFFFF404 = 0x3F800000 +set *0xFFFFF474 = 0x3F800000 +# PIOB +set *0xFFFFF604 = 0x0003FFFF +set *0xFFFFF674 = 0x0003FFFF +# PIOC +set *0xFFFFF804 = 0x0000FFFF +set *0xFFFFF870 = 0x0000FFFF + +# SDRAM configuration (see corresponding application note) +set *0xFFFFFFB8 = 0x21922159 + +set *0xFFFFFFB0 = 0x11 +set *0x20000000 = 0 + +set *0xFFFFFFB0 = 0x12 +set *0x20000000 = 0 + +set *0xFFFFFFB0 = 0x14 +set *0x20000000 = 0 +set *0xFFFFFFB0 = 0x14 +set *0x20000000 = 0 +set *0xFFFFFFB0 = 0x14 +set *0x20000000 = 0 +set *0xFFFFFFB0 = 0x14 +set *0x20000000 = 0 +set *0xFFFFFFB0 = 0x14 +set *0x20000000 = 0 +set *0xFFFFFFB0 = 0x14 +set *0x20000000 = 0 +set *0xFFFFFFB0 = 0x14 +set *0x20000000 = 0 +set *0xFFFFFFB0 = 0x14 +set *0x20000000 = 0 + +set *0xFFFFFFB0 = 0x13 +set *0x20000000 = 0 + +set *0xFFFFFFB0 = 0x10 +set *0x20000000 = 0 + +set *0xFFFFFFB4 = 0x150 + +echo SDRAM configuration ok.\n \ No newline at end of file diff --git a/resources/gdb/at91sam9260-ek-sdram.gdb b/resources/gdb/at91sam9260-ek-sdram.gdb new file mode 100644 index 0000000..29aa5a0 --- /dev/null +++ b/resources/gdb/at91sam9260-ek-sdram.gdb @@ -0,0 +1,70 @@ +# SDRAM initialization script for the AT91SAM9260 +#------------------------------------------------ +# Configure master clock +echo Configuring the master clock...\n +# Enable main oscillator +set *0xFFFFFC20 = 0x00004001 +while ((*0xFFFFFC68 & 0x1) == 0) +end + +# Set PLLA to 200MHz +set *0xFFFFFC28 = 0x2060BF09 +while ((*0xFFFFFC68 & 0x2) == 0) +end + +# Set PLLB for USB usage +set *0xFFFFFC2C = 0x207C3F0C +while ((*0xFFFFFC68 & 0x4) == 0) +end + +# Select prescaler +set *0xFFFFFC30 = 0x00000100 +while ((*0xFFFFFC68 & 0x8) == 0) +end + +# Select master clock +set *0xFFFFFC30 = 0x00000102 +while ((*0xFFFFFC68 & 0x8) == 0) +end + +echo Master clock ok.\n +echo Configuring the SDRAM controller...\n + +# Enable EBI chip select for the SDRAM +set *0xFFFFEF1C = 0x2 + +# SDRAM configuration +set *0xFFFFEA08 = 0x85227259 + +set *0xFFFFEA00 = 0x1 +set *0x20000000 = 0 + +set *0xFFFFEA00 = 0x2 +set *0x20000000 = 0 + +set *0xFFFFEA00 = 0x4 +set *0x20000000 = 0 +set *0xFFFFEA00 = 0x4 +set *0x20000000 = 0 +set *0xFFFFEA00 = 0x4 +set *0x20000000 = 0 +set *0xFFFFEA00 = 0x4 +set *0x20000000 = 0 +set *0xFFFFEA00 = 0x4 +set *0x20000000 = 0 +set *0xFFFFEA00 = 0x4 +set *0x20000000 = 0 +set *0xFFFFEA00 = 0x4 +set *0x20000000 = 0 +set *0xFFFFEA00 = 0x4 +set *0x20000000 = 0 + +set *0xFFFFEA00 = 0x3 +set *0x20000000 = 0 + +set *0xFFFFEA00 = 0x0 +set *0x20000000 = 0 + +set *0xFFFFEA04 = 0x2B7 + +echo SDRAM configuration ok.\n \ No newline at end of file diff --git a/resources/gdb/at91sam9260-ek-sram.gdb b/resources/gdb/at91sam9260-ek-sram.gdb new file mode 100644 index 0000000..05355e0 --- /dev/null +++ b/resources/gdb/at91sam9260-ek-sram.gdb @@ -0,0 +1,26 @@ +# MCK initialization script for the AT91SAM9260 +#------------------------------------------------ +# Configure master clock +echo Configuring the master clock...\n +# Enable main oscillator +set *0xFFFFFC20 = 0x00004001 +while ((*0xFFFFFC68 & 0x1) == 0) +end + +# Set PLLA to 200MHz +set *0xFFFFFC28 = 0x2060BF09 +while ((*0xFFFFFC68 & 0x2) == 0) +end + +# Select prescaler +set *0xFFFFFC30 = 0x00000100 +while ((*0xFFFFFC68 & 0x8) == 0) +end + +# Select master clock +set *0xFFFFFC30 = 0x00000102 +while ((*0xFFFFFC68 & 0x8) == 0) +end + +echo Master clock ok.\n + diff --git a/resources/gdb/at91sam9263-ek-sdram.gdb b/resources/gdb/at91sam9263-ek-sdram.gdb new file mode 100644 index 0000000..b0e139f --- /dev/null +++ b/resources/gdb/at91sam9263-ek-sdram.gdb @@ -0,0 +1,78 @@ +# SDRAM initialization script for the AT91SAM9263 +#------------------------------------------------ +# Configure master clock +echo Configuring the master clock...\n +# Enable main oscillator +set *0xFFFFFC20 = 0x00004001 +while ((*0xFFFFFC68 & 0x1) == 0) +end + +# Set PLLA to 200MHz +set *0xFFFFFC28 = 0x206DBF09 +while ((*0xFFFFFC68 & 0x2) == 0) +end + +# Set PLLB for USB usage +set *0xFFFFFC2C = 0x20AF3F0F +while ((*0xFFFFFC68 & 0x4) == 0) +end + +# Select prescaler +set *0xFFFFFC30 = 0x00000100 +while ((*0xFFFFFC68 & 0x8) == 0) +end + +# Select master clock +set *0xFFFFFC30 = 0x00000102 +while ((*0xFFFFFC68 & 0x8) == 0) +end + +echo Master clock ok.\n +echo Configuring the SDRAM controller...\n + +# Configure PIOD as peripheral (D16/D31) +# __writeMemory32(0xFFFF0000,0xFFFFF870,"Memory"); +set *0xFFFFF870 = 0xFFFF0000 +# __writeMemory32(0x00000000,0xFFFFF874,"Memory"); +set *0xFFFFF874 = 0x00000000 +# __writeMemory32(0xFFFF0000,0xFFFFF804,"Memory"); +set *0xFFFFF804 = 0xFFFF0000 + +# Enable EBI chip select for the SDRAM +set *0xFFFFED20 = 0x2 + +# SDRAM configuration +set *0xFFFFE208 = 0x85227259 + +set *0xFFFFE200 = 0x1 +set *0x20000000 = 0 + +set *0xFFFFE200 = 0x2 +set *0x20000000 = 0 + +set *0xFFFFE200 = 0x4 +set *0x20000000 = 0 +set *0xFFFFE200 = 0x4 +set *0x20000000 = 0 +set *0xFFFFE200 = 0x4 +set *0x20000000 = 0 +set *0xFFFFE200 = 0x4 +set *0x20000000 = 0 +set *0xFFFFE200 = 0x4 +set *0x20000000 = 0 +set *0xFFFFE200 = 0x4 +set *0x20000000 = 0 +set *0xFFFFE200 = 0x4 +set *0x20000000 = 0 +set *0xFFFFE200 = 0x4 +set *0x20000000 = 0 + +set *0xFFFFE200 = 0x3 +set *0x20000000 = 0 + +set *0xFFFFE200 = 0x0 +set *0x20000000 = 0 + +set *0xFFFFE204 = 0x2B7 + +echo SDRAM configuration ok.\n diff --git a/resources/gdb/at91sam9263-ek-sram.gdb b/resources/gdb/at91sam9263-ek-sram.gdb new file mode 100644 index 0000000..a1627c9 --- /dev/null +++ b/resources/gdb/at91sam9263-ek-sram.gdb @@ -0,0 +1,25 @@ +# MCK initialization script for the AT91SAM9263 +#------------------------------------------------ + +echo Configuring the master clock...\n +# Enable main oscillator +set *0xFFFFFC20 = 0x00004001 +while ((*0xFFFFFC68 & 0x1) == 0) +end + +# Set PLLA to 200MHz +set *0xFFFFFC28 = 0x206DBF09 +while ((*0xFFFFFC68 & 0x2) == 0) +end + +# Select prescaler +set *0xFFFFFC30 = 0x00000100 +while ((*0xFFFFFC68 & 0x8) == 0) +end + +# Select master clock +set *0xFFFFFC30 = 0x00000102 +while ((*0xFFFFFC68 & 0x8) == 0) +end + +echo Master clock ok.\n diff --git a/resources/gdb/at91sam9g20-ek-sdram.gdb b/resources/gdb/at91sam9g20-ek-sdram.gdb new file mode 100644 index 0000000..a3e685b --- /dev/null +++ b/resources/gdb/at91sam9g20-ek-sdram.gdb @@ -0,0 +1,75 @@ +# SDRAM initialization script for the AT91SAM9G20 +#------------------------------------------------ +# Configure master clock +echo Configuring the master clock...\n +# Enable main oscillator +set *0xFFFFFC20 = 0x00004001 +while ((*0xFFFFFC68 & 0x1) == 0) +end + +# Set PLLA to 800MHz +set *0xFFFFFC28 = 0x202A3F01 +while ((*0xFFFFFC68 & 0x2) == 0) +end + +# Set PLLB for USB usage +set *0xFFFFFC2C = 0x10193F05 +while ((*0xFFFFFC68 & 0x4) == 0) +end + +# Select prescaler +set *0xFFFFFC30 = 0x00001300 +while ((*0xFFFFFC68 & 0x8) == 0) +end + +# Select master clock +set *0xFFFFFC30 = 0x00001302 +while ((*0xFFFFFC68 & 0x8) == 0) +end + +echo Master clock ok.\n +echo Configuring the SDRAM controller...\n + +# Enable EBI chip select for the SDRAM +set *0xFFFFEF1C = 0x2 + +# Enable PC16-PC31 pins +set *0xFFFFF870 = 0xFFFF0000 +set *0xFFFFF874 = 0x00000000 +set *0xFFFFF804 = 0xFFFF0000 + +# SDRAM configuration +set *0xFFFFEA08 = 0x96338379 + +set *0xFFFFEA00 = 0x1 +set *0x20000000 = 0 + +set *0xFFFFEA00 = 0x2 +set *0x20000000 = 0 + +set *0xFFFFEA00 = 0x4 +set *0x20000000 = 0 +set *0xFFFFEA00 = 0x4 +set *0x20000000 = 0 +set *0xFFFFEA00 = 0x4 +set *0x20000000 = 0 +set *0xFFFFEA00 = 0x4 +set *0x20000000 = 0 +set *0xFFFFEA00 = 0x4 +set *0x20000000 = 0 +set *0xFFFFEA00 = 0x4 +set *0x20000000 = 0 +set *0xFFFFEA00 = 0x4 +set *0x20000000 = 0 +set *0xFFFFEA00 = 0x4 +set *0x20000000 = 0 + +set *0xFFFFEA00 = 0x3 +set *0x20000000 = 0 + +set *0xFFFFEA00 = 0x0 +set *0x20000000 = 0 + +set *0xFFFFEA04 = 0x39D + +echo SDRAM configuration ok.\n diff --git a/resources/gdb/at91sam9g20-ek-sram.gdb b/resources/gdb/at91sam9g20-ek-sram.gdb new file mode 100644 index 0000000..4dc6ea1 --- /dev/null +++ b/resources/gdb/at91sam9g20-ek-sram.gdb @@ -0,0 +1,26 @@ +# MCK initialization script for the AT91SAM9G20 +#------------------------------------------------ +# Configure master clock +echo Configuring the master clock...\n +# Enable main oscillator +set *0xFFFFFC20 = 0x00004001 +while ((*0xFFFFFC68 & 0x1) == 0) +end + +# Set PLLA to 800MHz +set *0xFFFFFC28 = 0x202A3F01 +while ((*0xFFFFFC68 & 0x2) == 0) +end + +# Select prescaler +set *0xFFFFFC30 = 0x00001300 +while ((*0xFFFFFC68 & 0x8) == 0) +end + +# Select master clock +set *0xFFFFFC30 = 0x00001302 +while ((*0xFFFFFC68 & 0x8) == 0) +end + +echo Master clock ok.\n + diff --git a/resources/gdb/at91sam9m10-ek-ddram.gdb b/resources/gdb/at91sam9m10-ek-ddram.gdb new file mode 100644 index 0000000..46cb2ca --- /dev/null +++ b/resources/gdb/at91sam9m10-ek-ddram.gdb @@ -0,0 +1,217 @@ +#------------------------------------------------ +# DDRAM initialization script for the AT91SAM9M10 +#------------------------------------------------ + +echo Configuring the master clock...\n +# Enable main oscillator +# CKGR_MOR +set *0xFFFFFC20 = 0x00004001 +# PMC_SR +while ((*0xFFFFFC68 & 0x1) == 0) +end + +echo set plla\n +# Set PLLA to 800MHz +# CKGR_PLLAR +set *0xFFFFFC28 = 0x20C73F03 +# PMC_SR +while ((*0xFFFFFC68 & 0x2) == 0) +end +while ((*0xFFFFFC68 & 0x8) == 0) +end + +echo select prescaler\n +# Select prescaler +# PMC_MCKR +set *0xFFFFFC30 = 0x00001300 +# PMC_SR +while ((*0xFFFFFC68 & 0x8) == 0) +end + +echo select master clock\n +# Select master clock +# PMC_MCKR +set *0xFFFFFC30 = 0x00001302 +# PMC_SR +while ((*0xFFFFFC68 & 0x8) == 0) +end + +echo Master clock ok.\n + +echo Configuring the DDRAM controller...\n +echo MICRON DDRAM configuration\n +# 0xFFFFE600 DDR2C Base Address + +# Enable DDR2 clock x2 in PMC +# AT91C_BASE_PMC, PMC_SCER, AT91C_PMC_DDR +set *0xFFFFFC00 = 0x04 + +# Configure the DDR controller +# HDDRSDRC2_MDR, AT91C_DDRC2_DBW_16_BITS | // 16-bit DDR +# AT91C_DDRC2_MD_DDR2_SDRAM // DDR2 +set *0xFFFFE620 = 0x16 + +# Program the DDR Controller +# HDDRSDRC2_CR, AT91C_DDRC2_NC_DDR10_SDR9 | // 10 column bits (1K) +# AT91C_DDRC2_NR_14 | // 14 row bits (8K) +# AT91C_DDRC2_CAS_3 | // CAS Latency 3 +# AT91C_DDRC2_DLL_RESET_DISABLED // DLL not reset +set *0xFFFFE608 = 0x3D + +# assume timings for 7.5ns min clock period +# HDDRSDRC2_T0PR, AT91C_DDRC2_TRAS_6 | // 6 * 7.5 = 45 ns +# AT91C_DDRC2_TRCD_2 | // 3 * 7.5 = 22.5 ns +# AT91C_DDRC2_TWR_2 | // 2 * 7.5 = 15 ns +# AT91C_DDRC2_TRC_8 | // 10 * 7.5 = 75 ns +# AT91C_DDRC2_TRP_2 | // 3 * 7.5 = 22.5 ns +# AT91C_DDRC2_TRRD_1 | // 2 * 7.5 = 15 ns +# AT91C_DDRC2_TWTR_1 | // 1 clock cycle +# AT91C_DDRC2_TMRD_2 // 2 clock cycles +set *0xFFFFE60C = 0x21128226 + +# pSDDRC->HDDRSDRC2_T1PR = 0x00000008; +# HDDRSDRC2_T1PR, AT91C_DDRC2_TXP_2 | // 2 * 7.5 = 15 ns +# 200 << 16 | // 200 clock cycles, TXSRD: Exit self refresh delay to Read command +# 27 << 8 | // 27 * 7.5 = 202 ns TXSNR: Exit self refresh delay to non read command +# AT91C_DDRC2_TRFC_14 << 0 // 19 * 7.5 = 142 ns (must be 140 ns for 1Gb DDR) +set *0xFFFFE610 = 0x02C81B0E + +# HDDRSDRC2_T2PR, AT91C_DDRC2_TRTP_2 | // 2 * 7.5 = 15 ns +# AT91C_DDRC2_TRPA_2 | // 2 * 7.5 = 15 ns +# AT91C_DDRC2_TXARDS_7 | // 7 clock cycles +# AT91C_DDRC2_TXARD_7 // 2 clock cycles +set *0xFFFFE614 = 0x02020707 + +# Initialization Step 1 + 2: NOP command -> allow to enable clk +# HDDRSDRC2_MR, AT91C_DDRC2_MODE_NOP_CMD +set *0xFFFFE600 = 0x1 +set *0x70000000 = 0 + +# TODO Initialization Step 3 (must wait 200 us) (6 core cycles per iteration, core is at 396MHz: min 13200 loops) +# for (i = 0; i < 13300; i++) { +# asm(" nop" +# } + +# NOP command -> allow to enable cke +# HDDRSDRC2_MR, AT91C_DDRC2_MODE_NOP_CMD +set *0xFFFFE600 = 0x1 +set *0x70000000 = 0 + +# wait 400 ns min +# for (i = 0; i < 100; i++) { +# asm(" nop" +# } + +# Initialization Step 4: Set All Bank Precharge +# HDDRSDRC2_MR, AT91C_DDRC2_MODE_PRCGALL_CMD +set *0xFFFFE600 = 0x2 +set *0x70000000 = 0 + +# wait 400 ns min +# for (i = 0; i < 100; i++) { +# asm(" nop" +# } + +# Initialization Step 5: Set EMR operation (EMRS2) +# HDDRSDRC2_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD +set *0xFFFFE600 = 0x5 +set *0x74000000 = 0x0 + +# wait 2 cycles min +# for (i = 0; i < 100; i++) { +# asm(" nop" +# } + +# Initialization Step 6: Set EMR operation (EMRS3) +# HDDRSDRC2_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD +set *0xFFFFE600 = 0x5 +set *0x76000000 = 0x0 + +# wait 2 cycles min +# for (i = 0; i < 100; i++) { +# asm(" nop" +# } + +# Initialization Step 7: Set EMR operation (EMRS1) +# HDDRSDRC2_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD +set *0xFFFFE600 = 0x5 +set *0x72000000 = 0x0 + +# wait 2 cycles min +# for (i = 0; i < 100; i++) { +# asm(" nop" +# } + +# Initialization Step 8a: enable DLL reset +# HDDRSDRC2_CR, cr | AT91C_DDRC2_DLL_RESET_ENABLED +set *0xFFFFE608 |= 0xBD + +# Initialization Step 8b: reset DLL +# HDDRSDRC2_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD +set *0xFFFFE600 = 0x5 +set *0x70000000 = 0 + +# wait 2 cycles min +# for (i = 0; i < 100; i++) { +# asm(" nop" +# } + +# Initialization Step 9: Set All Bank Precharge +# HDDRSDRC2_MR, AT91C_DDRC2_MODE_PRCGALL_CMD +set *0xFFFFE600 = 0x2 +set *0x70000000 = 0 + +# wait 2 cycles min +# for (i = 0; i < 100; i++) { +# asm(" nop" +# } + +# Initialization Step 11: Set 1st CBR +# HDDRSDRC2_MR, AT91C_DDRC2_MODE_RFSH_CMD +set *0xFFFFE600 = 0x4 +set *0x70000000 = 0 + +# wait 2 cycles min +# for (i = 0; i < 100; i++) { +# asm(" nop" +# } + +# Set 2nd CBR +# HDDRSDRC2_MR, AT91C_DDRC2_MODE_RFSH_CMD +set *0xFFFFE600 = 0x4 +set *0x70000000 = 0 + +# wait 2 cycles min +# for (i = 0; i < 100; i++) { +# asm(" nop" +# } + +# Initialization Step 12: disable DLL reset +# HDDRSDRC2_CR, cr & (~AT91C_DDRC2_DLL_RESET_ENABLED) +set *0xFFFFE608 = 0x3D + +# Initialization Step 13: Set LMR operation +# HDDRSDRC2_MR, AT91C_DDRC2_MODE_LMR_CMD +set *0xFFFFE600 = 0x3 +set *0x70000000 = 0 + +# Skip Initialization Step 14 to 17 (not supported by the DDR2 model) + +# Initialization Step 18: Set Normal mode +# HDDRSDRC2_MR, AT91C_DDRC2_MODE_NORMAL_CMD +set *0xFFFFE600 = 0x0 +set *0x70000000 = 0 + +# Set Refresh timer +# HDDRSDRC2_RTR, 0x00000520 +set *0xFFFFE604 = 0x00000520 + +# OK now we are ready to work on the DDRSDR + +# wait for end of calibration +# for (i = 0; i < 500; i++) { +# asm(" nop" +# } + +echo DDRAM configuration ok.\n + diff --git a/resources/gdb/at91sam9m10-ek-sram.gdb b/resources/gdb/at91sam9m10-ek-sram.gdb new file mode 100644 index 0000000..a6b0abe --- /dev/null +++ b/resources/gdb/at91sam9m10-ek-sram.gdb @@ -0,0 +1,40 @@ +#------------------------------------------------ +# MCK initialization script for the AT91SAM9M10 +#------------------------------------------------ + +echo Configuring the master clock...\n +# Enable main oscillator +# CKGR_MOR +set *0xFFFFFC20 = 0x00004001 +# PMC_SR +while ((*0xFFFFFC68 & 0x1) == 0) +end + +echo set plla\n +# Set PLLA to 800MHz +# CKGR_PLLAR +set *0xFFFFFC28 = 0x20C73F03 +# PMC_SR +while ((*0xFFFFFC68 & 0x2) == 0) +end +while ((*0xFFFFFC68 & 0x8) == 0) +end + +echo select prescaler\n +# Select prescaler +# PMC_MCKR +set *0xFFFFFC30 = 0x00001300 +# PMC_SR +while ((*0xFFFFFC68 & 0x8) == 0) +end + +echo select master clock\n +# Select master clock +# PMC_MCKR +set *0xFFFFFC30 = 0x00001302 +# PMC_SR +while ((*0xFFFFFC68 & 0x8) == 0) +end + +echo Master clock ok.\n + diff --git a/resources/gdb/at91sam9rl-ek-sdram.gdb b/resources/gdb/at91sam9rl-ek-sdram.gdb new file mode 100644 index 0000000..b80fb7f --- /dev/null +++ b/resources/gdb/at91sam9rl-ek-sdram.gdb @@ -0,0 +1,65 @@ +# SDRAM initialization script for the AT91SAM9RL +#------------------------------------------------ +# Configure master clock +echo Configuring the master clock...\n +# Enable main oscillator +set *0xFFFFFC20 = 0x00004001 +while ((*0xFFFFFC68 & 0x1) == 0) +end + +# Set PLL to 200MHz +set *0xFFFFFC28 = 0x2031BF03 +while ((*0xFFFFFC68 & 0x2) == 0) +end + +# Select prescaler +set *0xFFFFFC30 = 0x00000100 +while ((*0xFFFFFC68 & 0x8) == 0) +end + +# Select master clock +set *0xFFFFFC30 = 0x00000102 +while ((*0xFFFFFC68 & 0x8) == 0) +end + +echo Master clock ok.\n +echo Configuring the SDRAM controller...\n + +# Enable EBI chip select for the SDRAM +set *0xFFFFEF20 = 0x2 + +# SDRAM configuration +set *0xFFFFEA08 = 0x85227259 + +set *0xFFFFEA00 = 0x1 +set *0x20000000 = 0 + +set *0xFFFFEA00 = 0x2 +set *0x20000000 = 0 + +set *0xFFFFEA00 = 0x4 +set *0x20000000 = 0 +set *0xFFFFEA00 = 0x4 +set *0x20000000 = 0 +set *0xFFFFEA00 = 0x4 +set *0x20000000 = 0 +set *0xFFFFEA00 = 0x4 +set *0x20000000 = 0 +set *0xFFFFEA00 = 0x4 +set *0x20000000 = 0 +set *0xFFFFEA00 = 0x4 +set *0x20000000 = 0 +set *0xFFFFEA00 = 0x4 +set *0x20000000 = 0 +set *0xFFFFEA00 = 0x4 +set *0x20000000 = 0 + +set *0xFFFFEA00 = 0x3 +set *0x20000000 = 0 + +set *0xFFFFEA00 = 0x0 +set *0x20000000 = 0 + +set *0xFFFFEA04 = 0x2BC + +echo SDRAM configuration ok.\n \ No newline at end of file diff --git a/resources/gdb/at91sam9rl-ek-sram.gdb b/resources/gdb/at91sam9rl-ek-sram.gdb new file mode 100644 index 0000000..bb9d667 --- /dev/null +++ b/resources/gdb/at91sam9rl-ek-sram.gdb @@ -0,0 +1,25 @@ +# MCK initialization script for the AT91SAM9RL +#------------------------------------------------ + +echo Configuring the master clock...\n +# Enable main oscillator +set *0xFFFFFC20 = 0x00004001 +while ((*0xFFFFFC68 & 0x1) == 0) +end + +# Set PLL to 200MHz +set *0xFFFFFC28 = 0x0031BF03 +while ((*0xFFFFFC68 & 0x2) == 0) +end + +# Select prescaler +set *0xFFFFFC30 = 0x00000100 +while ((*0xFFFFFC68 & 0x8) == 0) +end + +# Select master clock +set *0xFFFFFC30 = 0x00000102 +while ((*0xFFFFFC68 & 0x8) == 0) +end + +echo Master clock ok.\n diff --git a/resources/gdb/at91sam9xe-ek-sdram.gdb b/resources/gdb/at91sam9xe-ek-sdram.gdb new file mode 100644 index 0000000..cf2cb3c --- /dev/null +++ b/resources/gdb/at91sam9xe-ek-sdram.gdb @@ -0,0 +1,70 @@ +# SDRAM initialization script for the AT91SAM9XE +#------------------------------------------------ +# Configure master clock +echo Configuring the master clock...\n +# Enable main oscillator +set *0xFFFFFC20 = 0x00004001 +while ((*0xFFFFFC68 & 0x1) == 0) +end + +# Set PLLA to 200MHz +set *0xFFFFFC28 = 0x2060BF09 +while ((*0xFFFFFC68 & 0x2) == 0) +end + +# Set PLLB for USB usage +set *0xFFFFFC2C = 0x207C7F0C +while ((*0xFFFFFC68 & 0x4) == 0) +end + +# Select prescaler +set *0xFFFFFC30 = 0x00000100 +while ((*0xFFFFFC68 & 0x8) == 0) +end + +# Select master clock +set *0xFFFFFC30 = 0x00000102 +while ((*0xFFFFFC68 & 0x8) == 0) +end + +echo Master clock ok.\n +echo Configuring the SDRAM controller...\n + +# Enable EBI chip select for the SDRAM +set *0xFFFFEF1C = 0x2 + +# SDRAM configuration +set *0xFFFFEA08 = 0x85227259 + +set *0xFFFFEA00 = 0x1 +set *0x20000000 = 0 + +set *0xFFFFEA00 = 0x2 +set *0x20000000 = 0 + +set *0xFFFFEA00 = 0x4 +set *0x20000000 = 0 +set *0xFFFFEA00 = 0x4 +set *0x20000000 = 0 +set *0xFFFFEA00 = 0x4 +set *0x20000000 = 0 +set *0xFFFFEA00 = 0x4 +set *0x20000000 = 0 +set *0xFFFFEA00 = 0x4 +set *0x20000000 = 0 +set *0xFFFFEA00 = 0x4 +set *0x20000000 = 0 +set *0xFFFFEA00 = 0x4 +set *0x20000000 = 0 +set *0xFFFFEA00 = 0x4 +set *0x20000000 = 0 + +set *0xFFFFEA00 = 0x3 +set *0x20000000 = 0 + +set *0xFFFFEA00 = 0x0 +set *0x20000000 = 0 + +set *0xFFFFEA04 = 0x2B7 + +echo SDRAM configuration ok.\n diff --git a/resources/gdb/at91sam9xe-ek-sram.gdb b/resources/gdb/at91sam9xe-ek-sram.gdb new file mode 100644 index 0000000..24fadd0 --- /dev/null +++ b/resources/gdb/at91sam9xe-ek-sram.gdb @@ -0,0 +1,26 @@ +# MCK initialization script for the AT91SAM9XE +#------------------------------------------------ +# Configure master clock +echo Configuring the master clock...\n +# Enable main oscillator +set *0xFFFFFC20 = 0x00004001 +while ((*0xFFFFFC68 & 0x1) == 0) +end + +# Set PLLA to 200MHz +set *0xFFFFFC28 = 0x2060BF09 +while ((*0xFFFFFC68 & 0x2) == 0) +end + +# Select prescaler +set *0xFFFFFC30 = 0x00000100 +while ((*0xFFFFFC68 & 0x8) == 0) +end + +# Select master clock +set *0xFFFFFC30 = 0x00000102 +while ((*0xFFFFFC68 & 0x8) == 0) +end + +echo Master clock ok.\n + diff --git a/resources/gdb/debug.pl b/resources/gdb/debug.pl new file mode 100644 index 0000000..5bca69a --- /dev/null +++ b/resources/gdb/debug.pl @@ -0,0 +1,93 @@ +# Perl script to easily launch AT91 debug sessions. + +use File::Basename; + +# List of supported boards +my @boards = ("at91sam7se-ek", + "at91sam9260-ek", + "at91sam9261-ek", + "at91sam9263-ek", + "at91sam9rl-ek", + "at91sam9xe-ek", + "at91sam9g20-ek", + "at91sam9m10-ek", + "at91cap9-dk", + "at91cap9-stk" + ); + +# Check that an argument has been provided +if (!@ARGV[0]) { + + print("Usage: " . basename($0) . " \n"); + exit(1); +} + +# Parse file name +my $file = @ARGV[0]; +my $script = ""; +my $gdb = dirname($0); + +# Check #2: this must be an elf file +if ($file !~ m/.*.elf/i) { + + print(".elf file expected.\n"); + exit(2); +} + +# Check #1: 'sdram' or 'ddram' or 'bcram' token in filename +if (($file =~ m/.*sdram.*/i) or ($file =~ m/.*ddram.*/i) or ($file =~ m/.*bcram.*/i) or ($file =~ m/.*sam9.*/i) or ($file =~ m/.*cap9.*/i) ) { + + # Find board basename + foreach $board (@boards) { + + if (index($file, $board) != -1) { + + $script = "$gdb\\$board"; + } + } + + # Add -ek-mck or -ek-sdram depending on need + if ($file =~ m/.*sdram.*/i) { + + $script .= "-sdram.gdb"; + } + elsif ($file =~ m/.*ddram.*/i) { + + $script .= "-ddram.gdb"; + } + elsif ($file =~ m/.*bcram.*/i) { + + $script .= "-bcram.gdb"; + } + else { + + $script .= "-sram.gdb"; + } +} + +# Create command file to define "reset" command +open(CMD, ">cmd.gdb") or die("Could not create command file:\n$!"); +print(CMD "define reset\n"); +print(CMD " target remote localhost:2331\n"); +print(CMD " monitor reset\n"); +if ($script) { + + print(CMD " source $script\n"); +} +print(CMD " load\n"); +print(CMD "end"); +close(CMD); + +# Launch GDB +$pid = fork(); +if ($pid == 0) { + + exec("arm-none-eabi-gdb -x cmd.gdb -ex \"reset\" $file"); +} +else { + + $SIG{INT} = 'IGNORE'; + $res = waitpid($pid, 0); +} +print("Done\n"); +unlink("cmd.gdb");