diff --git a/conf/machine/imx8mpsolidrun.conf b/conf/machine/imx8mpsolidrun.conf index 2c7bee9..3ebf913 100644 --- a/conf/machine/imx8mpsolidrun.conf +++ b/conf/machine/imx8mpsolidrun.conf @@ -21,11 +21,14 @@ MACHINE_ESSENTIAL_EXTRA_RRECOMMENDS:append = " kernel-modules firmware-imx-sdma- require conf/machine/include/imx-base.inc require conf/machine/include/arm/armv8a/tune-cortexa53.inc -KERNEL_DEVICETREE ?= "freescale/imx8mp-cubox-m.dtb \ - freescale/imx8mp-hummingboard-extended.dtb \ - freescale/imx8mp-hummingboard-mate.dtb \ - freescale/imx8mp-hummingboard-pulse.dtb \ - freescale/imx8mp-hummingboard-ripple.dtb \ +KERNEL_DEVICETREE ?= " \ + freescale/imx8mp-cubox-m.dtb \ + freescale/imx8mp-hummingboard-extended.dtb \ + freescale/imx8mp-hummingboard-iiot-main.dtb \ + freescale/imx8mp-hummingboard-mate.dtb \ + freescale/imx8mp-hummingboard-pro.dtb \ + freescale/imx8mp-hummingboard-pulse.dtb \ + freescale/imx8mp-hummingboard-ripple.dtb \ " WKS_FILE_DEPENDS:append:imx8mp-solidrun = " imx-m7-demos" diff --git a/recipes-bsp/u-boot/u-boot-imx/0041-imx8mp_solidrun-update-SKU-parsing-to-detect-SRHBIIOT.patch b/recipes-bsp/u-boot/u-boot-imx/0041-imx8mp_solidrun-update-SKU-parsing-to-detect-SRHBIIOT.patch new file mode 100644 index 0000000..a49181d --- /dev/null +++ b/recipes-bsp/u-boot/u-boot-imx/0041-imx8mp_solidrun-update-SKU-parsing-to-detect-SRHBIIOT.patch @@ -0,0 +1,38 @@ +From 73f8958bfce39a69819063cc788a8021f398520a Mon Sep 17 00:00:00 2001 +From: Yazan Shhady +Date: Mon, 2 Dec 2024 14:57:22 +0200 +Subject: [PATCH] imx8mp_solidrun: update SKU parsing to detect SRHBIIOTIVxx + (HB-IIOT) + +Enhanced the `board_id_from_tlv_info` function to include detection of the HB-IIOT board. +Added a check for the "HBI" identifier in the TLV part number array, +ensuring proper recognition of SRHBIIOTIVxx as HB-IIOT. +--- + board/solidrun/imx8mp_solidrun/imx8mp_solidrun.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/board/solidrun/imx8mp_solidrun/imx8mp_solidrun.c b/board/solidrun/imx8mp_solidrun/imx8mp_solidrun.c +index ac4d56b6dc..d4b675e248 100644 +--- a/board/solidrun/imx8mp_solidrun/imx8mp_solidrun.c ++++ b/board/solidrun/imx8mp_solidrun/imx8mp_solidrun.c +@@ -473,7 +473,8 @@ static void board_id_from_tlv_info(void) { + + for(int i = 0; i < TLV_MAX_DEVICES; i++) { + // parse sku - processor or carrier indicated at index 2-6 +- if(memcmp(&hb_tlv_data.tlv_part_number[i][2], "HBC", 3) == 0) { ++ if(memcmp(&hb_tlv_data.tlv_part_number[i][2], "HBC", 3) == 0 || ++ memcmp(&hb_tlv_data.tlv_part_number[i][2], "HBI", 3) == 0 ) { + /* + HummingBoard: + SKU - Board_Name {xx: board version}: +@@ -482,6 +483,7 @@ static void board_id_from_tlv_info(void) { + SRHBCUPRO0IVxx HB-Pro + SRHBCME000CVxx HB-Mate + SRHBCRE000CVxx HB-Ripple ++ SRHBIIOTIVxx HB-IIOT + */ + switch(hb_tlv_data.tlv_part_number[i][5]) { + case 'M': // Mate +-- +2.25.1 + diff --git a/recipes-bsp/u-boot/u-boot-imx_2022.04.bbappend b/recipes-bsp/u-boot/u-boot-imx_2022.04.bbappend index 28bb45a..3c17aaf 100644 --- a/recipes-bsp/u-boot/u-boot-imx_2022.04.bbappend +++ b/recipes-bsp/u-boot/u-boot-imx_2022.04.bbappend @@ -40,6 +40,7 @@ SRC_URI += " \ file://0038-board-solidrun-imx8mp-Add-HummingBoard-IIOT-tlv-base.patch \ file://0039-imx8mp_solidrun-update-SKU-parsing-for-HummingBoard-.patch \ file://0040-board-solidrun-imx8mp-configure-phy-reset-lines-open.patch \ + file://0041-imx8mp_solidrun-update-SKU-parsing-to-detect-SRHBIIOT.patch \ file://0201-HACK-fastboot-emmc_dev-default-to-0.patch \ file://0202-HACK-usb-ci_udc-ignore-ID-pin-value.patch \ file://0203-board-solidrun-add-imx8dxl-som.patch \ diff --git a/recipes-kernel/linux/linux-imx/0015-arm64-dts-add-support-for-imx8mp-hummingboard-pro.patch b/recipes-kernel/linux/linux-imx/0015-arm64-dts-add-support-for-imx8mp-hummingboard-pro.patch new file mode 100644 index 0000000..d625b03 --- /dev/null +++ b/recipes-kernel/linux/linux-imx/0015-arm64-dts-add-support-for-imx8mp-hummingboard-pro.patch @@ -0,0 +1,118 @@ +From 01a1da6f877db1c034317810479d5435c7784152 Mon Sep 17 00:00:00 2001 +From: Yazan Shhady +Date: Wed, 27 Dec 2023 15:48:06 +0200 +Subject: [PATCH 2/2] arm64: dts: add support for imx8mp hummingboard pro + +imx8mp-hummingboard-pro.dts entry added and imx8mp-hummingboard-extended.dts +just includes this file for backward compatibiltiy as the board name changed + +Signed-off-by: Yazan Shhady +--- + arch/arm64/boot/dts/freescale/Makefile | 1 + + .../imx8mp-hummingboard-extended.dts | 36 +++---------------- + .../dts/freescale/imx8mp-hummingboard-pro.dts | 36 +++++++++++++++++++ + 3 files changed, 41 insertions(+), 32 deletions(-) + create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pro.dts + +diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile +index 421faf67edc9..f91e289abbe6 100644 +--- a/arch/arm64/boot/dts/freescale/Makefile ++++ b/arch/arm64/boot/dts/freescale/Makefile +@@ -121,6 +121,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-ddr4-evk.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-ndm.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8mp-cubox-m.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-extended.dtb ++dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-pro.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-mate.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-pulse.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-ripple.dtb +diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-extended.dts b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-extended.dts +index f1c47092bddd..0bed70d7db06 100644 +--- a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-extended.dts ++++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-extended.dts +@@ -1,36 +1,8 @@ + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) + /* +- * Copyright 2023 Josua Mayer ++ * Device Tree Source for the i.MX8MP HummingBoard Pro/Extended ++ * ++ * Copyright (C) 2023 SolidRun Ltd. + */ + +-/dts-v1/; +- +-#include +-#include "imx8mp-sr-som.dtsi" +-#include "imx8mp-hummingboard-pulse.dtsi" +- +-/ { +- model = "SolidRun i.MX8MP HummingBoard Extended"; +- compatible = "fsl,imx8mp-sr-som", "fsl,imx8mp"; +- +- /* +- * leave m.2 W_DISABLE signal floating to improve +- * compatibility with certain pcie cards; +- */ +- /delete-node/ rfkill_m2_wdis; +-}; +- +-&fec { +- status = "okay"; +-}; +- +-&iomuxc { +- pinctrl_pcie: pciegrp { +- fsl,pins = ; +- }; +-}; +- +-&pcie{ +- pinctrl-0 = <&pinctrl_pcie>; +- reset-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>; +-}; ++#include "imx8mp-hummingboard-pro.dts" +diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pro.dts b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pro.dts +new file mode 100644 +index 000000000000..8699053b31ca +--- /dev/null ++++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pro.dts +@@ -0,0 +1,36 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++* Device Tree Source for the i.MX8MP HummingBoard Pro ++*/ ++ ++/dts-v1/; ++ ++#include ++#include "imx8mp-sr-som.dtsi" ++#include "imx8mp-hummingboard-pulse.dtsi" ++ ++/ { ++ model = "SolidRun i.MX8MP HummingBoard Pro"; ++ compatible = "fsl,imx8mp-sr-som", "fsl,imx8mp"; ++ ++ /* ++ * leave m.2 W_DISABLE signal floating to improve ++ * compatibility with certain pcie cards; ++ */ ++ /delete-node/ rfkill_m2_wdis; ++}; ++ ++&fec { ++ status = "okay"; ++}; ++ ++&iomuxc { ++ pinctrl_pcie: pciegrp { ++ fsl,pins = ; ++ }; ++}; ++ ++&pcie{ ++ pinctrl-0 = <&pinctrl_pcie>; ++ reset-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>; ++}; +-- +2.25.1 + diff --git a/recipes-kernel/linux/linux-imx/0022-arm64-dts-imx8mp-sr-som-fix-phy-interrupt-support.patch b/recipes-kernel/linux/linux-imx/0022-arm64-dts-imx8mp-sr-som-fix-phy-interrupt-support.patch new file mode 100644 index 0000000..bbfd704 --- /dev/null +++ b/recipes-kernel/linux/linux-imx/0022-arm64-dts-imx8mp-sr-som-fix-phy-interrupt-support.patch @@ -0,0 +1,47 @@ +From 875fcc390bb774942b76857da0b2cac6c5f1c04a Mon Sep 17 00:00:00 2001 +From: Josua Mayer +Date: Sun, 10 Nov 2024 17:16:25 +0100 +Subject: [PATCH] arm64: dts: imx8mp-sr-som: fix phy interrupt support + +Contrary to previous change description, the interrupt lines do not +have external pull-up and require the CPU to activate internal pull-up +on the pads. + +Signed-off-by: Josua Mayer +--- + arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +diff --git a/arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi +index 5ab7c33fb..375265829 100644 +--- a/arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi ++++ b/arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi +@@ -547,9 +547,9 @@ MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f + + pinctrl_phy0: phy0grp { + fsl,pins = < +- /* INT_N: weak i/o, external 1.5k pull-up */ +- MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x0 +- /* RESET_N: weak i/o, open drain, external 1k pull-up */ ++ /* INT_N: weak i/o, pull-up */ ++ MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x140 ++ /* RESET_N: weak i/o, open drain, external 10k pull-up */ + MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x20 + >; + }; +@@ -575,9 +575,9 @@ MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f + + pinctrl_phy1: phy1grp { + fsl,pins = < +- /* INT_N: weak i/o, external 1.5k pull-up */ +- MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x0 +- /* RESET_N: weak i/o, open drain, external 1k pull-up */ ++ /* INT_N: weak i/o, pull-up */ ++ MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x140 ++ /* RESET_N: weak i/o, open drain, external 10k pull-up */ + MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x20 + >; + }; +-- +2.43.0 + diff --git a/recipes-kernel/linux/linux-imx/0023-net-stmmac-don-t-reject-VLANs-when-IFF_PROMISC-is-se.patch b/recipes-kernel/linux/linux-imx/0023-net-stmmac-don-t-reject-VLANs-when-IFF_PROMISC-is-se.patch new file mode 100644 index 0000000..14301dc --- /dev/null +++ b/recipes-kernel/linux/linux-imx/0023-net-stmmac-don-t-reject-VLANs-when-IFF_PROMISC-is-se.patch @@ -0,0 +1,284 @@ +From 1a57b1cc05c072e8822a6240d8c9acf669b96e88 Mon Sep 17 00:00:00 2001 +From: Vladimir Oltean +Date: Sat, 25 Mar 2023 13:28:15 +0200 +Subject: [PATCH] net: stmmac: don't reject VLANs when IFF_PROMISC is set + +The blamed commit has introduced the following tests to +dwmac4_add_hw_vlan_rx_fltr(), called from stmmac_vlan_rx_add_vid(): + + if (hw->promisc) { + netdev_err(dev, + "Adding VLAN in promisc mode not supported\n"); + return -EPERM; + } + +"VLAN promiscuous" mode is keyed in this driver to IFF_PROMISC, and so, +vlan_vid_add() and vlan_vid_del() calls cannot take place in IFF_PROMISC +mode. I have the following 2 arguments that this restriction is.... hm, +how shall I put it nicely... unproductive :) + +First, take the case of a Linux bridge. If the kernel is compiled with +CONFIG_BRIDGE_VLAN_FILTERING=y, then this bridge shall have a VLAN +database. The bridge shall try to call vlan_add_vid() on its bridge +ports for each VLAN in the VLAN table. It will do this irrespectively of +whether that port is *currently* VLAN-aware or not. So it will do this +even when the bridge was created with vlan_filtering 0. +But the Linux bridge, in VLAN-unaware mode, configures its ports in +promiscuous (IFF_PROMISC) mode, so that they accept packets with any +MAC DA (a switch must do this in order to forward those packets which +are not directly targeted to its MAC address). + +As a result, the stmmac driver does not work as a bridge port, when the +kernel is compiled with CONFIG_BRIDGE_VLAN_FILTERING=y. + +$ ip link add br0 type bridge && ip link set br0 up +$ ip link set eth0 master br0 && ip link set eth0 up +[ 2333.943296] br0: port 1(eth0) entered blocking state +[ 2333.943381] br0: port 1(eth0) entered disabled state +[ 2333.943782] device eth0 entered promiscuous mode +[ 2333.944080] 4033c000.ethernet eth0: Adding VLAN in promisc mode not supported +[ 2333.976509] 4033c000.ethernet eth0: failed to initialize vlan filtering on this port +RTNETLINK answers: Operation not permitted + +Secondly, take the case of stmmac as DSA master. Some switch tagging +protocols are based on 802.1Q VLANs (tag_sja1105.c), and as such, +tag_8021q.c uses vlan_vid_add() to work with VLAN-filtering DSA masters. +But also, when a DSA port becomes promiscuous (for example when it joins +a bridge), the DSA framework also makes the DSA master promiscuous. + +Moreover, for every VLAN that a DSA switch sends to the CPU, DSA also +programs a VLAN filter on the DSA master, because if the the DSA switch +uses a tail tag, then the hardware frame parser of the DSA master will +see VLAN as VLAN, and might filter them out, for being unknown. + +Due to the above 2 reasons, my belief is that the stmmac driver does not +get to choose to not accept vlan_vid_add() calls while IFF_PROMISC is +enabled, because the 2 are completely independent and there are code +paths in the network stack which directly lead to this situation +occurring, without the user's direct input. + +In fact, my belief is that "VLAN promiscuous" mode should have never +been keyed on IFF_PROMISC in the first place, but rather, on the +NETIF_F_HW_VLAN_CTAG_FILTER feature flag which can be toggled by the +user through ethtool -k, when present in netdev->hw_features. + +In the stmmac driver, NETIF_F_HW_VLAN_CTAG_FILTER is only present in +"features", making this feature "on [fixed]". + +I have this belief because I am unaware of any definition of promiscuity +which implies having an effect on anything other than MAC DA (therefore +not VLAN). However, I seem to be rather alone in having this opinion, +looking back at the disagreements from this discussion: +https://lore.kernel.org/netdev/20201110153958.ci5ekor3o2ekg3ky@ipetronik.com/ + +In any case, to remove the vlan_vid_add() dependency on !IFF_PROMISC, +one would need to remove the check and see what fails. I guess the test +was there because of the way in which dwmac4_vlan_promisc_enable() is +implemented. + +For context, the dwmac4 supports Perfect Filtering for a limited number +of VLANs - dwmac4_get_num_vlan(), priv->hw->num_vlan, with a fallback on +Hash Filtering - priv->dma_cap.vlhash - see stmmac_vlan_update(), also +visible in cat /sys/kernel/debug/stmmaceth/eth0/dma_cap | grep 'VLAN +Hash Filtering'. + +The perfect filtering is based on MAC_VLAN_Tag_Filter/MAC_VLAN_Tag_Data +registers, accessed in the driver through dwmac4_write_vlan_filter(). + +The hash filtering is based on the MAC_VLAN_Hash_Table register, named +GMAC_VLAN_HASH_TABLE in the driver and accessed by dwmac4_update_vlan_hash(). +The control bit for enabling hash filtering is GMAC_VLAN_VTHM +(MAC_VLAN_Tag_Ctrl bit VTHM: VLAN Tag Hash Table Match Enable). + +Now, the description of dwmac4_vlan_promisc_enable() is that it iterates +through the driver's cache of perfect filter entries (hw->vlan_filter[i], +added by dwmac4_add_hw_vlan_rx_fltr()), and evicts them from hardware by +unsetting their GMAC_VLAN_TAG_DATA_VEN (MAC_VLAN_Tag_Data bit VEN - VLAN +Tag Enable) bit. Then it unsets the GMAC_VLAN_VTHM bit, which disables +hash matching. + +This leaves the MAC, according to table "VLAN Match Status" from the +documentation, to always enter these data paths: + +VID |VLAN Perfect Filter |VTHM Bit |VLAN Hash Filter |Final VLAN Match + |Match Result | |Match Result |Status +-------|--------------------|---------|-----------------|---------------- +VID!=0 |Fail |0 |don't care |Pass + +So, dwmac4_vlan_promisc_enable() does its job, but by unsetting +GMAC_VLAN_VTHM, it conflicts with the other code path which controls +this bit: dwmac4_update_vlan_hash(), called through stmmac_update_vlan_hash() +from stmmac_vlan_rx_add_vid() and from stmmac_vlan_rx_kill_vid(). +This is, I guess, why dwmac4_add_hw_vlan_rx_fltr() is not allowed to run +after dwmac4_vlan_promisc_enable() has unset GMAC_VLAN_VTHM: because if +it did, then dwmac4_update_vlan_hash() would set GMAC_VLAN_VTHM again, +breaking the "VLAN promiscuity". + +It turns out that dwmac4_vlan_promisc_enable() is way too complicated +for what needs to be done. The MAC_Packet_Filter register also has the +VTFE bit (VLAN Tag Filter Enable), which simply controls whether VLAN +tagged packets which don't match the filtering tables (either perfect or +hash) are dropped or not. At the moment, this driver unconditionally +sets GMAC_PACKET_FILTER_VTFE if NETIF_F_HW_VLAN_CTAG_FILTER was detected +through the priv->dma_cap.vlhash capability bits of the device, in +stmmac_dvr_probe(). + +I would suggest deleting the unnecessarily complex logic from +dwmac4_vlan_promisc_enable(), and simply unsetting GMAC_PACKET_FILTER_VTFE +when becoming IFF_PROMISC, which has the same effect of allowing packets +with any VLAN tags, but has the additional benefit of being able to run +concurrently with stmmac_vlan_rx_add_vid() and stmmac_vlan_rx_kill_vid(). + +As much as I believe that the VTFE bit should have been exclusively +controlled by NETIF_F_HW_VLAN_CTAG_FILTER through ethtool, and not by +IFF_PROMISC, changing that is not a punctual fix to the problem, and it +would probably break the VFFQ feature added by the later commit +e0f9956a3862 ("net: stmmac: Add option for VLAN filter fail queue +enable"). From the commit description, VFFQ needs IFF_PROMISC=on and +VTFE=off in order to work (and this change respects that). But if VTFE +was changed to be controlled through ethtool -k, then a user-visible +change would have been introduced in Intel's scripts (a need to run +"ethtool -k eth0 rx-vlan-filter off" which did not exist before). + +The patch was tested with this set of commands: + + ip link set eth0 up + ip link add link eth0 name eth0.100 type vlan id 100 + ip addr add 192.168.100.2/24 dev eth0.100 && ip link set eth0.100 up + ip link set eth0 promisc on + ip link add link eth0 name eth0.101 type vlan id 101 + ip addr add 192.168.101.2/24 dev eth0.101 && ip link set eth0.101 up + ip link set eth0 promisc off + ping -c 5 192.168.100.1 + ping -c 5 192.168.101.1 + ip link set eth0 promisc on + ping -c 5 192.168.100.1 + ping -c 5 192.168.101.1 + ip link del eth0.100 + ip link del eth0.101 + # Wait for VLAN-tagged pings from the other end... + # Check with "tcpdump -i eth0 -e -n -p" and we should see them + ip link set eth0 promisc off + # Wait for VLAN-tagged pings from the other end... + # Check with "tcpdump -i eth0 -e -n -p" and we shouldn't see them + # anymore, but remove the "-p" argument from tcpdump and they're there. + +Fixes: c89f44ff10fd ("net: stmmac: Add support for VLAN promiscuous mode") +Signed-off-by: Vladimir Oltean +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/stmicro/stmmac/common.h | 1 - + .../net/ethernet/stmicro/stmmac/dwmac4_core.c | 61 +------------------ + 2 files changed, 3 insertions(+), 59 deletions(-) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h +index 4f8948da325c..47ff72e95599 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/common.h ++++ b/drivers/net/ethernet/stmicro/stmmac/common.h +@@ -531,7 +531,6 @@ struct mac_device_info { + unsigned int xlgmac; + unsigned int num_vlan; + u32 vlan_filter[32]; +- unsigned int promisc; + bool vlan_fail_q_en; + u8 vlan_fail_q; + }; +diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c +index 412abfabd28b..b4c464643cb6 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c +@@ -478,12 +478,6 @@ static int dwmac4_add_hw_vlan_rx_fltr(struct net_device *dev, + if (vid > 4095) + return -EINVAL; + +- if (hw->promisc) { +- netdev_err(dev, +- "Adding VLAN in promisc mode not supported\n"); +- return -EPERM; +- } +- + /* Single Rx VLAN Filter */ + if (hw->num_vlan == 1) { + /* For single VLAN filter, VID 0 means VLAN promiscuous */ +@@ -533,12 +527,6 @@ static int dwmac4_del_hw_vlan_rx_fltr(struct net_device *dev, + { + int i, ret = 0; + +- if (hw->promisc) { +- netdev_err(dev, +- "Deleting VLAN in promisc mode not supported\n"); +- return -EPERM; +- } +- + /* Single Rx VLAN Filter */ + if (hw->num_vlan == 1) { + if ((hw->vlan_filter[0] & GMAC_VLAN_TAG_VID) == vid) { +@@ -563,39 +551,6 @@ static int dwmac4_del_hw_vlan_rx_fltr(struct net_device *dev, + return ret; + } + +-static void dwmac4_vlan_promisc_enable(struct net_device *dev, +- struct mac_device_info *hw) +-{ +- void __iomem *ioaddr = hw->pcsr; +- u32 value; +- u32 hash; +- u32 val; +- int i; +- +- /* Single Rx VLAN Filter */ +- if (hw->num_vlan == 1) { +- dwmac4_write_single_vlan(dev, 0); +- return; +- } +- +- /* Extended Rx VLAN Filter Enable */ +- for (i = 0; i < hw->num_vlan; i++) { +- if (hw->vlan_filter[i] & GMAC_VLAN_TAG_DATA_VEN) { +- val = hw->vlan_filter[i] & ~GMAC_VLAN_TAG_DATA_VEN; +- dwmac4_write_vlan_filter(dev, hw, i, val); +- } +- } +- +- hash = readl(ioaddr + GMAC_VLAN_HASH_TABLE); +- if (hash & GMAC_VLAN_VLHT) { +- value = readl(ioaddr + GMAC_VLAN_TAG); +- if (value & GMAC_VLAN_VTHM) { +- value &= ~GMAC_VLAN_VTHM; +- writel(value, ioaddr + GMAC_VLAN_TAG); +- } +- } +-} +- + static void dwmac4_restore_hw_vlan_rx_fltr(struct net_device *dev, + struct mac_device_info *hw) + { +@@ -715,22 +670,12 @@ static void dwmac4_set_filter(struct mac_device_info *hw, + } + + /* VLAN filtering */ +- if (dev->features & NETIF_F_HW_VLAN_CTAG_FILTER) ++ if (dev->flags & IFF_PROMISC && !hw->vlan_fail_q_en) ++ value &= ~GMAC_PACKET_FILTER_VTFE; ++ else if (dev->features & NETIF_F_HW_VLAN_CTAG_FILTER) + value |= GMAC_PACKET_FILTER_VTFE; + + writel(value, ioaddr + GMAC_PACKET_FILTER); +- +- if (dev->flags & IFF_PROMISC && !hw->vlan_fail_q_en) { +- if (!hw->promisc) { +- hw->promisc = 1; +- dwmac4_vlan_promisc_enable(dev, hw); +- } +- } else { +- if (hw->promisc) { +- hw->promisc = 0; +- dwmac4_restore_hw_vlan_rx_fltr(dev, hw); +- } +- } + } + + static void dwmac4_flow_ctrl(struct mac_device_info *hw, unsigned int duplex, +-- +2.43.0 + diff --git a/recipes-kernel/linux/linux-imx/0024-USB-serial-option-add-Quectel-EM05GV2.patch b/recipes-kernel/linux/linux-imx/0024-USB-serial-option-add-Quectel-EM05GV2.patch new file mode 100644 index 0000000..30832ca --- /dev/null +++ b/recipes-kernel/linux/linux-imx/0024-USB-serial-option-add-Quectel-EM05GV2.patch @@ -0,0 +1,33 @@ +From 8b4e29d32e8abb31c2b5040b2b90d2c1bac04dd7 Mon Sep 17 00:00:00 2001 +From: Yazan Shhady +Date: Tue, 6 Aug 2024 19:56:49 +0300 +Subject: [PATCH] USB: serial: option: add Quectel EM05GV2 + +--- + drivers/usb/serial/option.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c +index 697683e3fbff..54a441693dee 100644 +--- a/drivers/usb/serial/option.c ++++ b/drivers/usb/serial/option.c +@@ -254,6 +254,7 @@ static void option_instat_callback(struct urb *urb); + #define QUECTEL_PRODUCT_EP06 0x0306 + #define QUECTEL_PRODUCT_EM05G 0x030a + #define QUECTEL_PRODUCT_EM060K 0x030b ++#define QUECTEL_PRODUCT_EM05GV2 0x030e + #define QUECTEL_PRODUCT_EM12 0x0512 + #define QUECTEL_PRODUCT_RM500Q 0x0800 + #define QUECTEL_PRODUCT_RM520N 0x0801 +@@ -1148,6 +1149,8 @@ static const struct usb_device_id option_ids[] = { + { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EP06, 0xff, 0, 0) }, + { USB_DEVICE_INTERFACE_CLASS(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM05G, 0xff), + .driver_info = RSVD(6) | ZLP }, ++ { USB_DEVICE_INTERFACE_CLASS(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM05GV2, 0xff), ++ .driver_info = RSVD(4) | ZLP }, + { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM060K, 0xff, 0x00, 0x40) }, + { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM060K, 0xff, 0xff, 0x30) }, + { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM060K, 0xff, 0xff, 0x40) }, +-- +2.25.1 + diff --git a/recipes-kernel/linux/linux-imx/0025-arm64-dts-add-support-for-imx8mp-hummingboard-iiot.patch b/recipes-kernel/linux/linux-imx/0025-arm64-dts-add-support-for-imx8mp-hummingboard-iiot.patch new file mode 100644 index 0000000..8fa8935 --- /dev/null +++ b/recipes-kernel/linux/linux-imx/0025-arm64-dts-add-support-for-imx8mp-hummingboard-iiot.patch @@ -0,0 +1,1252 @@ +From fbb91f1f68c7871da965a935f906c6bd0fefd2d0 Mon Sep 17 00:00:00 2001 +From: Yazan Shhady +Date: Tue, 6 Aug 2024 20:01:08 +0300 +Subject: [PATCH] arm64: dts: add support for imx8mp hummingboard iiot + +--- + arch/arm64/boot/dts/freescale/Makefile | 1 + + .../imx8mp-hummingboard-iiot-main.dts | 10 + + .../freescale/imx8mp-hummingboard-iiot.dtsi | 1201 +++++++++++++++++ + 3 files changed, 1212 insertions(+) + create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot-main.dts + create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot.dtsi + +diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile +index f91e289abbe6..5cf46a9d4bcf 100644 +--- a/arch/arm64/boot/dts/freescale/Makefile ++++ b/arch/arm64/boot/dts/freescale/Makefile +@@ -125,6 +125,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-pro.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-mate.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-pulse.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-ripple.dtb ++dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-iiot-main.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb imx8mq-evk-rpmsg.dtb imx8mq-evk-pcie1-m2.dtb imx8mq-evk-usd-wifi.dtb \ + imx8mq-evk-usdhc2-m2.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-ak4497.dtb imx8mq-evk-audio-tdm.dtb imx8mq-evk-pdm.dtb +diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot-main.dts b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot-main.dts +new file mode 100644 +index 000000000000..783cc7101bee +--- /dev/null ++++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot-main.dts +@@ -0,0 +1,10 @@ ++/dts-v1/; ++ ++#include ++#include "imx8mp-sr-som.dtsi" ++#include "imx8mp-hummingboard-iiot.dtsi" ++ ++/ { ++ model = "SolidRun i.MX8MP HummingBoard IIOT Main Board"; ++ compatible = "fsl,imx8mp-sr-som", "fsl,imx8mp"; ++}; +diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot.dtsi +new file mode 100644 +index 000000000000..e3c449c4a57a +--- /dev/null ++++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot.dtsi +@@ -0,0 +1,1201 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2024 SolidRun Ltd. ++ */ ++ ++#include ++#include ++#include ++#include ++#include "imx8mp-sr-som.dtsi" ++ ++/* UARTA (UART3): Select RS232 or RS485 */ ++#define UARTA_SEL_RS232_RS485 1 // {0:RS323,1:RS485} ++/* UARTB (UART4): Select RS232 or RS485 */ ++#define UARTB_SEL_RS232_RS485 1 // {0:RS323,1:RS485} ++/* UARTA and UARTB: Select Internal or External */ ++#define UARTA_UARTB_SEL_INT_EXT 0 // {0:INT,1:EXT} ++/* CANA and CANB: Select Internal or External */ ++#define CANA_CANB_SEL_INT_EXT 0 // {0:INT,1:EXT} ++/* SPI MUX TPM/EXT {Select TPM or EXTERNAL_SPI_DEVICE} */ ++#define SPI_SEL_TPM_EXT 0 // {0:TPM,1:EXT} ++ ++/ { ++ /* USB1_VBUS */ ++ power-usb-port1 { ++ compatible = "reg-userspace-consumer"; ++ regulator-name = "usb-port1-pwr-consumer"; ++ regulator-boot-on; ++ regulator-supplies = "vcc"; ++ vcc-supply = <®_usb1_vbus>; ++ comment = "USB Port1 vbus power switch"; ++ }; ++ ++ /* USB_HOST3_VBUS */ ++ power-usb-port2 { ++ compatible = "reg-userspace-consumer"; ++ regulator-name = "usb-port2-pwr-consumer"; ++ regulator-boot-on; ++ regulator-supplies = "vcc"; ++ vcc-supply = <®_usb_host3_vbus>; ++ comment = "USB Port2 vbus power switch"; ++ }; ++ ++ /* USB_HOST4_VBUS */ ++ power-usb-port3 { ++ compatible = "reg-userspace-consumer"; ++ regulator-name = "usb-port3-pwr-consumer"; ++ regulator-boot-on; ++ regulator-supplies = "vcc"; ++ vcc-supply = <®_usb_host4_vbus>; ++ comment = "USB Port3 vbus power switch"; ++ }; ++ ++ /* USB1_PWR_EN (USB1_VBUS) */ ++ reg_usb1_vbus: regulator-usb1-vbus { ++ compatible = "regulator-fixed"; ++ regulator-name = "usb1_vbus"; ++ pinctrl-names = "default"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ gpio = <&io_expander_u20 14 GPIO_ACTIVE_HIGH>; /* TBD - USB1_PWR_EN */ ++ enable-active-high; ++ }; ++ ++ /* USB_HUB3_PWR_EN (USB_HOST3_VBUS) */ ++ reg_usb_host3_vbus: regulator-usb1-vbus { ++ compatible = "regulator-fixed"; ++ regulator-name = "usb_host3_vbus"; ++ pinctrl-names = "default"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ gpio = <&io_expander_u20 12 GPIO_ACTIVE_HIGH>; /* TBD - USB1_PWR_EN */ ++ enable-active-high; ++ }; ++ ++ /* USB_HUB4_PWR_EN (USB_HOST4_VBUS) */ ++ reg_usb_host4_vbus: regulator-usb1-host-vbus { ++ compatible = "regulator-fixed"; ++ regulator-name = "usb_host4_vbus"; ++ pinctrl-names = "default"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ gpio = <&io_expander_u20 13 GPIO_ACTIVE_HIGH>; /* TBD - USB_HUB3_PWR_EN */ ++ enable-active-high; ++ }; ++ ++ /* uSD regulator */ ++ reg_usdhc2_vmmc: regulator-usdhc2 { ++ compatible = "regulator-fixed"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; ++ regulator-name = "VSD_3V3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ //gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; ++ regulator-always-on; ++ }; ++ ++ reg_vdd_1v8: regulator-vdd-1v8 { ++ compatible = "regulator-fixed"; ++ regulator-name = "VDD_1V8"; ++ vdd-3v3-supply = <&buck4>; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ }; ++ ++ /* CAN-1 Regulator */ ++ reg_can1_stby: regulator-can1-stby { ++ compatible = "regulator-fixed"; ++ regulator-name = "can1-stby"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_flexcan1_reg>; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ ++ /* CAN-2 Regulator */ ++ reg_can2_stby: regulator-can2-stby { ++ compatible = "regulator-fixed"; ++ regulator-name = "can2-stby"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_flexcan2_reg>; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ ++ /* ++ * J4: M.2 Support PCIe only (M.2 KEY-M) ++ * J6: M.2 Support USB3.0/USB2.0 (M.2 KEY-B) ++ * ++ */ ++ ++ /* J4: M.2M_3V3_EN */ ++ reg_m2_pcie_j4_pwr: regulator-m2-pcie-j4-pwr { ++ compatible = "regulator-fixed"; ++ regulator-name = "m2-j4-pcie-pwr"; ++ pinctrl-names = "default"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&io_expander_u20 6 GPIO_ACTIVE_HIGH>; // U20[P6] ++ enable-active-high; ++ }; ++ ++ /* J6: M.2B_3V3 */ ++ power-m2-j6 { ++ compatible = "reg-userspace-consumer"; ++ regulator-name = "m2-j6-pwr-consumer"; ++ regulator-boot-on; ++ regulator-supplies = "vcc"; ++ vcc-supply = <®_m2_j6_pwr>; ++ comment = "m.2 j6 3.3V connector switch"; ++ }; ++ ++ /* J6: M.2B_3V3_EN */ ++ reg_m2_j6_pwr: regulator-m2-j6-pwr { ++ compatible = "regulator-fixed"; ++ regulator-name = "m2-j6-pwr"; ++ pinctrl-names = "default"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ gpio = <&io_expander_u20 5 GPIO_ACTIVE_HIGH>; // U20[P5] ++ enable-active-high; ++ }; ++ ++ /* Enable this node for M.2 LTE modem rfkill support (M.2 J6) */ ++ rfkill_m2_wdis { ++ compatible = "rfkill-gpio"; ++ pinctrl-names = "default"; ++ rfkill-name = "m2_wdis"; ++ rfkill-type = <5>; ++ shutdown-gpio = <&io_expander_u20 9 GPIO_ACTIVE_HIGH>; // M.2B_W_DIS U20_P[11] ++ status = "okay"; ++ }; ++ ++ /* GPIO Controll M.2-J6 rfkill */ ++ rfkill_m2_gps { ++ compatible = "rfkill-gpio"; ++ pinctrl-names = "default"; ++ rfkill-name = "m2_gps"; ++ rfkill-type = <6>; ++ shutdown-gpio = <&io_expander_u20 10 GPIO_ACTIVE_HIGH>;// M.2B_GPS_EN U20_P[12] ++ status = "okay"; ++ }; ++ ++ /* M.2M-J4 PCIe Wake-On LAN */ ++ gpio-m2m-wakew-on-lan-hog { ++ gpio-hog; ++ gpios = <&io_expander_u21 11 GPIO_ACTIVE_HIGH>;// M.2M_WAKW_ON_LAN U21_P[13] ++ input; ++ line-name = "M.2M_WAKW_ON_LAN-J4"; ++ }; ++ ++ /* M.2M-J4 PCIe CLKREQ */ ++ gpio-m2m-clkreq-hog { ++ gpio-hog; ++ gpios = <&io_expander_u21 12 GPIO_ACTIVE_HIGH>; // M.2M_CLKREQ U21_P[14] ++ input; ++ line-name = "M.2M_CLKREQ-J4"; ++ }; ++ ++ /* M.2B-J4 Reset */ ++ lte-reset { ++ compatible = "gpio-reset"; ++ reset-gpios = <&io_expander_u20 8 GPIO_ACTIVE_LOW>; // M.2B_RESET U20_P[10] ++ reset-delay-us = <2000>; ++ reset-post-delay-ms = <40>; ++ #reset-cells = <0>; ++ }; ++ ++ /* UARTA (UART3): Select RS232 or RS485 */ ++ carrier_uarta_mux: uarta-mux-controller_carrier { ++ compatible = "gpio-mux"; ++ #mux-control-cells = <0>; ++ mux-gpios = <&io_expander_u20 1 GPIO_ACTIVE_HIGH>; // UARTA_232/485 U20_P[1] ++ #if UARTA_SEL_RS232_RS485 ++ idle-state = <1>; /* RS485 */ ++ #else ++ idle-state = <0>; /* RS232 */ ++ #endif ++ }; ++ ++ /* UARTB (UART4): Select RS232 or RS485 */ ++ carrier_uartb_mux: uartb-mux-controller_carrier { ++ compatible = "gpio-mux"; ++ #mux-control-cells = <0>; ++ mux-gpios = <&io_expander_u20 2 GPIO_ACTIVE_HIGH>; // UARTB_232/485 U20_P[2] ++ #if UARTB_SEL_RS232_RS485 ++ idle-state = <1>; /* RS485 */ ++ #else ++ idle-state = <0>; /* RS232 */ ++ #endif ++ }; ++ ++ /* UARTA and UARTB: Select Internal or External */ ++ carrier_int_ext_uart_mux: int-ext-uart-mux-controller_carrier { ++ compatible = "gpio-mux"; ++ #mux-control-cells = <0>; ++ mux-gpios = <&io_expander_u20 0 GPIO_ACTIVE_HIGH>; // INT/EXT_UART U20_P[0] ++ #if UARTA_UARTB_SEL_INT_EXT ++ idle-state = <1>; /* External */ ++ #else ++ idle-state = <0>; /* Internal */ ++ #endif ++ }; ++ ++ /* CANA and CANB: Select Internal or External */ ++ carrier_int_ext_can_mux: int-ext-can-mux-controller_carrier { ++ compatible = "gpio-mux"; ++ #mux-control-cells = <0>; ++ mux-gpios = <&io_expander_u20 3 GPIO_ACTIVE_HIGH>; // INT/EXT_CAN U20_P[3] ++ #if CANA_CANB_SEL_INT_EXT ++ idle-state = <1>; /* External */ ++ #else ++ idle-state = <0>; /* Internal */ ++ #endif ++ }; ++ ++ /* SPI MUX TPM/EXT {Select TPM or EXTERNAL_SPI_DEVICE} */ ++ carrier_spi_mux: spi-mux-controller_carrier { ++ compatible = "gpio-mux"; // MUX Type: 'TMUX1574Dx' ++ #mux-control-cells = <0>; ++ mux-gpios = <&io_expander_u21 3 GPIO_ACTIVE_HIGH>; // SPI_TPM/EXT U21_P[0] ++ #if SPI_SEL_TPM_EXT ++ idle-state = <1>; /* External */ ++ #else ++ idle-state = <0>; /* Internal */ ++ #endif ++ }; ++ ++ /* MIPI-DSI and LVDS I/O Exapnders (U37, U48) Reset */ ++ lcd_i2c_rst: lcd-i2c-rst { ++ compatible = "regulator-fixed"; ++ regulator-name = "lcd_i2c_rst"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ gpios = <&io_expander_u21 4 GPIO_ACTIVE_HIGH>; // ++ enable-active-high; ++ }; ++ ++ /* LVDS [J24] */ ++ /* Setting for Winstar Display 'WF70A8SYJHLNGA' */ ++ lvds0_panel { ++ compatible = "panel-lvds"; ++ status = "okay"; ++ width-mm = <154>; ++ height-mm = <86>; ++ //backlight = <&backlight_lvds>; ++ data-mapping = "vesa-24"; ++ ++ panel-timing { ++ /* timing for panel WF70A8SYJHLNGA */ ++ /* 1024x600@60Hz */ ++ clock-frequency = <51200000>; ++ hactive = <1024>; ++ vactive = <600>; ++ hfront-porch = <90>; ++ hback-porch = <160>; ++ hsync-len = <70>; ++ vfront-porch = <10>; ++ vback-porch = <23>; ++ vsync-len = <2>; ++ }; ++ ++ port { ++ panel_lvds_in: endpoint { ++ remote-endpoint = <&lvds_out>; ++ }; ++ }; ++ }; ++ ++ dsi_reset: dsi-reset { ++ compatible = "gpio-reset"; // "regulator-fixed"; ++ reset-gpios = <&gpio_dsi_expander 1 GPIO_ACTIVE_LOW>; ++ reset-delay-us = <2000>; ++ reset-post-delay-ms = <40>; ++ #reset-cells = <0>; ++ }; ++ ++ vdd_panel: vdd-panel { ++ compatible = "regulator-fixed"; ++ regulator-name = "vdd_panel"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ #if 0 // ++ gpios = <&io_expander_u20 15 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ #endif ++ }; ++ ++#if 1 ++ /* DSI Panel - Winstar WJ70N3TYJHMNG0 [J25] */ ++ panel_dsi: panel-dsi { ++ status = "okay"; ++ compatible = "winstar,wj70n3tyjhmng0"; // "panel-simple-dsi" ++ //reg = <0>; ++ power-supply = <&vdd_panel>; ++ dsi-lanes = <4>; ++ port { ++ panel0_in: endpoint { ++ remote-endpoint = <&mipi0_panel_out>; ++ }; ++ }; ++ }; ++#endif ++}; ++ ++&ldb { ++ status = "okay"; ++ lvds-channel@0 { ++ fsl,data-mapping = "spwg"; ++ fsl,data-width = <24>; ++ status = "okay"; ++ ++ port@1 { ++ reg = <1>; ++ ++ lvds_out: endpoint { ++ remote-endpoint = <&panel_lvds_in>; ++ }; ++ }; ++ }; ++}; ++ ++&ldb_phy { ++ status = "okay"; ++}; ++ ++&i2c2 { ++ clock-frequency = <100000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c2>; ++ status = "okay"; ++ ++ /* I2C Swich - PCA9546x */ ++ i2c-switch@70 { ++ /* ++ * channel0: External I2C ++ * channel1: CSI I2C ++ * channel2: DSI I2C ++ * channel3: LVDS I2C ++ */ ++ compatible = "nxp,pca9546"; ++ reg = <0x70>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reset-gpios = <&io_expander_u21 2 GPIO_ACTIVE_LOW>; ++ ++ /* channel0: External I2C */ ++ i2c_ext: i2c@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ }; ++ ++ /* channel1: CSI I2C */ ++ i2c_csi: i2c@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <1>; ++ ++ basler_0: basler_camera_vvcam@36 { ++ compatible = "basler,basler-camera-vvcam", "basler-camera-vvcam"; ++ reg = <0x36>; ++ csi_id = <0x00>; ++ status = "okay"; ++ ++ port { ++ basler_ep_0: endpoint { ++ data-lanes = <1 2 3 4>; ++ clock-lanes = <0>; ++ link-frequencies = /bits/ 64 <750000000>; ++ ++ max-lane-frequency = /bits/ 64 <750000000>; ++ max-pixel-frequency = /bits/ 64 <266000000>; ++ max-data-rate = /bits/ 64 <0>; ++ ++ remote-endpoint = <&mipi_csi0_ep>; ++ }; ++ }; ++ }; ++ }; ++ ++ /* channel2: DSI I2C */ ++ i2c_dsi: i2c@2 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <2>; ++ ++ /* DSI Touch Screen [J25] */ ++ touchscreen@41 { ++ /* ili2520 part of the Winstart Display WJ70N3TYJHMNG0 */ ++ compatible = "ilitek,ili2520"; ++ reg = <0x41>; ++ ++ interrupt-parent = <&io_expander_u21>; ++ interrupts = <13 IRQ_TYPE_LEVEL_LOW>; // U21_P[15]=LVDS_INT (shared INT for DSI and LVDS) ++ reset-gpios = <&gpio_dsi_expander 6 GPIO_ACTIVE_LOW>; // DSI_CTP/RST U48_P[6] (External Reset, Low is active) ++ //touchscreen-inverted-y; ++ //wakeup-source; ++ }; ++ }; ++ ++ /* channel3: LVDS I2C */ ++ i2c_lvds: i2c@3 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <3>; ++ ++ /* io_expander_u37 */ ++ gpio_lvds_expander: tca6408@20 { ++ compatible = "ti,tca6408"; ++ reg = <0x20>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ vcc-supply = <&lcd_i2c_rst>; ++ gpio-line-names = ++ "SELB", ++ "LVDS_RESET", ++ "LVDS_STBYB", ++ "LVDS_PWM_BL", ++ "LVDS_L/R", ++ "LVDS_U/D", ++ "LVDS_CTP_/RST", ++ "NC-7"; ++ SELB_hog { ++ gpio-hog; ++ gpios = <0 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "SELB"; ++ }; ++ #if 1 ++ LVDS_RESET_hog { ++ gpio-hog; ++ gpios = <1 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "LVDS_RESET"; ++ }; ++ LVDS_STBYB_hog { ++ gpio-hog; ++ gpios = <2 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "LVDS_STBYB"; ++ }; ++ #endif ++ /* Display Backlight control signal*/ ++ LVDS_PWM_BL_hog { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_LOW>; ++ output-high; ++ line-name = "LVDS_PWM_BL"; ++ }; ++ LVDS_LR_hog { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "LVDS_L/R"; ++ }; ++ LVDS_UD_hog { ++ gpio-hog; ++ gpios = <5 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "LVDS_U/D"; ++ }; ++ /* // ++ LVDS_CTP_RST_hog { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "LVDS_CTP_/RST"; ++ }; ++ */ ++ }; ++ ++ /* io_expander_u48 */ ++ gpio_dsi_expander: tca6408@21 { ++ compatible = "ti,tca6408"; ++ reg = <0x21>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ vcc-supply = <&lcd_i2c_rst>; ++ gpio-line-names = ++ "NC-0", ++ "DSI_RESET", ++ "DSI_STBYB", ++ "DSI_PWM_BL", ++ "DSI_L/R", ++ "DSI_U/D", ++ "DSI_CTP_/RST", ++ "NC-7"; ++ #if 1 // ++ DSI_RESET_hog { ++ gpio-hog; ++ gpios = <1 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "DSI_RESET"; ++ }; ++ ++ DSI_STBYB_hog { ++ gpio-hog; ++ gpios = <2 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "DSI_STBYB"; ++ }; ++ #endif ++ /* Display Backlight control signal*/ ++ DSI_PWM_BL_hog { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_LOW>; ++ output-high; ++ line-name = "DSI_PWM_BL"; ++ }; ++ DSI_LR_hog { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "DSI_L/R"; ++ }; ++ DSI_UD_hog { ++ gpio-hog; ++ gpios = <5 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "DSI_U/D"; ++ }; ++ /* ++ DSI_CTP_RST_hog { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "DSI_CTP_/RST"; ++ }; ++ */ ++ }; ++ ++ /* LVDS Touch Screen [J24] */ ++ touchscreen@41 { ++ /* ili2520 part of the Winstart Display WF70A8SYJHLNGA */ ++ compatible = "ilitek,ili2520"; ++ reg = <0x41>; ++ ++ interrupt-parent = <&io_expander_u21>; ++ interrupts = <15 IRQ_TYPE_LEVEL_LOW>; // U21_P[15]=LVDS_INT (shared INT for DSI and LVDS) ++ reset-gpios = <&gpio_lvds_expander 6 GPIO_ACTIVE_LOW>; // LVDS_CTP/RST U37_P[6] (External Reset, Low is active) ++ //touchscreen-inverted-y; ++ //wakeup-source; ++ }; ++ }; ++ }; ++}; ++ ++&i2c3 { ++ clock-frequency = <100000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c3>; ++ status = "okay"; ++ ++ /* io_expander_u20 */ ++ io_expander_u20: gpio@20 { ++ compatible = "ti,tca6416"; ++ reg = <0x20>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ gpio-line-names = ++ "TCA_INT/EXT_UART", ++ "TCA_UARTA_232/485", ++ "TCA_UARTB_232/485", ++ "TCA_INT/EXT_CAN", ++ "TCA_NXP/REN", ++ "TCA_M.2B_3V3_EN", ++ "TCA_M.2M_3V3_EN", ++ "TCA_M.2M_RESET#", ++ "TCA_M.2B_RESET#", ++ "TCA_M.2B_W_DIS#", ++ "TCA_M.2B_GPS_EN#", ++ "TCA_USB-HUB_RST#", ++ "TCA_USB_HUB3_PWR_EN", ++ "TCA_USB_HUB4_PWR_EN", ++ "TCA_USB1_PWR_EN", ++ "TCA_VIDEO_PWR_EN"; ++ ++ NXP_REN_hog { ++ gpio-hog; ++ gpios = <4 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "NXP_REN"; ++ }; ++ ++ #if 1 ++ VIDEO_PWR_EN_hog { ++ gpio-hog; ++ gpios = <15 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "VIDEO_PWR_EN"; ++ }; ++ #endif ++ }; ++ ++ /* io_expander_u21 */ ++ io_expander_u21: gpio@21 { ++ compatible = "ti,tca6416"; ++ reg = <0x21>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ interrupt-parent = <&gpio1>; //GPIO1_IO15 ++ interrupts = <15 IRQ_TYPE_EDGE_FALLING>;//IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_EDGE_FALLING, xxIRQ_TYPE_EDGE_RISING, ++ gpio-line-names = ++ "TCA_SPI_TPM/EXT", ++ "TCA_TPM_RST#", ++ "TCA_I2C_RST", ++ "TCA_RS232_SHTD#", ++ "TCA_LCD_I2C_RST", ++ "TCA_DIG_OUT1", ++ "TCA_bDIG_IN1", ++ "TCA_SENS_INT", ++ "TCA_ALERT#", ++ "TCA_TPM_PIRQ#", ++ "TCA_RTC_INT", ++ "TCA_M.2M_WAKW_ON_LAN", ++ "TCA_M.2M_CLKREQ#", ++ "TCA_LVDS_INT#", ++ "TCA_NC", ++ "TCA_POE_AT"; ++ ++ TCA_POE_AT_hog { ++ gpio-hog; ++ gpios = <15 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "TCA_POE_AT"; ++ }; ++ }; ++ ++ carrier_eeprom: eeprom_at24c02@57 { ++ compatible = "st,24c02", "atmel,24c02"; ++ reg = <0x57>; ++ pagesize = <8>; ++ }; ++ ++ rtc: rtc_am1805@69 { ++ compatible = "abracon,ab1805"; ++ reg = <0x69>; ++ abracon,tc-diode = "schottky"; ++ abracon,tc-resistor = <3>; ++ }; ++ ++ charger: battery-charger@68 { ++ // Not assembled ++ status = "disabled"; ++ compatible = "lltc,ltc4162-l"; ++ reg = <0x68>; ++ // lltc,rsnsb-micro-ohms = <10000>; ++ // lltc,rsnsi-micro-ohms = <16000>; ++ // lltc,cell-count = <2>; ++ }; ++ ++ accelerometer: accelerometer@2a { ++ // Not assembled ++ status = "disabled"; ++ compatible = "adi,adxl345"; ++ reg = <0x2a>; ++ // interrupt-parent = <&io_expander_u21>; ++ // interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; ++ }; ++ ++ ambient_light: ambient_light@44 { ++ // Not assembled ++ status = "disabled"; ++ compatible = "isil,isl29023"; ++ reg = <0x44>; ++ // interrupt-parent = <&io_expander_u21>; ++ // interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; ++ }; ++ ++ leds: led-controller@30 { ++ compatible = "ti,lp5562"; ++ reg = <0x30>; ++ clock-mode = /bits/ 8 <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pwr-sel = <0>; ++ ++ chan@0 { ++ chan-name = "R"; ++ led-cur = /bits/ 8 <0x20>; ++ max-cur = /bits/ 8 <0x60>; ++ reg = <0>; ++ color = ; ++ }; ++ ++ chan@1 { ++ chan-name = "G"; ++ led-cur = /bits/ 8 <0x20>; ++ max-cur = /bits/ 8 <0x60>; ++ reg = <1>; ++ color = ; ++ }; ++ ++ chan@2 { ++ chan-name = "B"; ++ led-cur = /bits/ 8 <0x20>; ++ max-cur = /bits/ 8 <0x60>; ++ reg = <2>; ++ color = ; ++ }; ++ ++ chan@3 { ++ chan-name = "D8"; ++ led-cur = /bits/ 8 <0x20>; ++ max-cur = /bits/ 8 <0x60>; ++ reg = <3>; ++ color = ; ++ }; ++ }; ++}; ++ ++&ecspi2 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ fsl,spi-num-chipselects = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; ++ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; ++ status = "okay"; ++ ++ carrier_spi_muxed: spi@0 { ++ compatible = "spi-mux"; ++ reg = <0>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spi-max-frequency = <12000000>; ++ mux-controls = <&carrier_spi_mux>; ++ ++ carrier_tpm: tpm@0 { ++ compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; ++ reg = <0>; ++ spi-max-frequency = <10000000>; ++ }; ++ ++ carrier_conn: carrier_conn_spi@1 { ++ status = "okay"; ++ compatible = "linux,spidev"; ++ reg = <1>; ++ spi-max-frequency = <10000000>; ++ }; ++ }; ++}; ++ ++/* eth0 */ ++&eqos { ++ status = "okay"; ++}; ++ ++/* eth1 */ ++&fec { ++ status = "okay"; ++}; ++ ++&flexspi { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_flexspi0>; ++ status = "okay"; ++}; ++ ++&aud2htx { ++ status = "okay"; ++}; ++ ++&basler_1 { ++ status = "okay"; ++}; ++ ++&easrc { ++ fsl,asrc-rate = <48000>; ++ status = "okay"; ++}; ++ ++&irqsteer_hdmi { ++ status = "disabled"; ++}; ++ ++&hdmi { ++ status = "disabled"; ++}; ++ ++&hdmi_blk_ctrl { ++ status = "disabled"; ++}; ++ ++&hdmi_pavi { ++ status = "disabled"; ++}; ++ ++&hdmiphy { ++ status = "disabled"; ++}; ++ ++&isp_0 { ++ status = "okay"; ++}; ++ ++&isp_1 { ++ status = "okay"; ++}; ++ ++/* mipi-dsi */ ++&lcdif1 { ++ status = "okay"; ++}; ++ ++&lcdif3 { ++ status = "disabled"; ++}; ++ ++&micfil { ++ pinctrl-names = "default"; ++ assigned-clocks = <&clk IMX8MP_CLK_PDM>; ++ assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; ++ assigned-clock-rates = <196608000>; ++ status = "disabled"; ++}; ++ ++&mipi_csi_0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clock-frequency = <266000000>; ++ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>; ++ assigned-clock-rates = <266000000>; ++ status = "okay"; ++ ++ port@0 { ++ reg = <0>; ++ mipi_csi0_ep: endpoint { ++ remote-endpoint = <&basler_ep_0>; ++ data-lanes = <4>; ++ csis-hs-settle = <16>; ++ }; ++ }; ++ ++}; ++ ++&mipi_csi_1 { ++ status = "okay"; ++}; ++ ++&mipi_dsi { ++ status = "disabled"; ++ #if 0 // ++ panel@0 { ++ /* Winstart Display WJ70N3TYJHMNG0 [J25] */ ++ status = "okay"; ++ compatible = "winstar,wj70n3tyjhmng0"; ++ reg = <0>; ++ power-supply = <&vdd_panel>; ++ dsi-lanes = <4>; ++ port { ++ panel0_in: endpoint { ++ remote-endpoint = <&mipi0_panel_out>; ++ }; ++ }; ++ }; ++ #endif ++ ++ port@1 { ++ reg = <1>; ++ mipi0_panel_out: endpoint { ++ remote-endpoint = <&panel0_in>; ++ //attach-bridge; ++ }; ++ }; ++}; ++ ++&pcie{ ++ pinctrl-names = "default"; ++ ext_osc = <0>; ++ clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, ++ <&clk IMX8MP_CLK_PCIE_AUX>, ++ <&clk IMX8MP_CLK_HSIO_AXI>, ++ <&clk IMX8MP_CLK_PCIE_ROOT>; ++ clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; ++ assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>, ++ <&clk IMX8MP_CLK_PCIE_AUX>; ++ assigned-clock-rates = <500000000>, <10000000>; ++ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>, ++ <&clk IMX8MP_SYS_PLL2_50M>; ++ vpcie-supply = <®_m2_pcie_j4_pwr>; ++ reset-gpio = <&io_expander_u20 7 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++}; ++ ++&pcie_phy{ ++ ext_osc = <0>; ++ status = "okay"; ++}; ++ ++&pwm4 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_pwm4>; ++ status = "okay"; ++}; ++ ++&sai3 { ++ status = "disabled"; ++}; ++ ++&sdma2 { ++ status = "okay"; ++}; ++ ++/* UARTA: RS485-A / RS232-A */ ++&uart3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart3>; ++ assigned-clocks = <&clk IMX8MP_CLK_UART3>; ++ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; ++ status = "okay"; ++ ++#if UARTA_SEL_RS232_RS485 ++ /*RS485-A (UARTA_TX/UARTA_RX)*/ ++ rts-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; ++ linux,rs485-enabled-at-boot-time; ++ //rs485-rts-delay; ++#endif ++}; ++ ++/* UARTB: RS485-B / RS232-B */ ++&uart4 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart4>; ++ assigned-clocks = <&clk IMX8MP_CLK_UART4>; ++ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; // <&clk IMX8MP_CLK_24M>; ++ status = "okay"; ++ ++#if UARTB_SEL_RS232_RS485 ++ /*RS485-B (UARTB_TX/UARTB_RX)*/ ++ rts-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>; ++ linux,rs485-enabled-at-boot-time; ++ //rs485-rts-delay; ++#endif ++}; ++ ++&usb3_phy0 { ++ fsl,phy-tx-vref-tune = <0xe>; ++ fsl,phy-tx-preemp-amp-tune = <3>; ++ fsl,phy-tx-vboost-level = <5>; ++ fsl,phy-comp-dis-tune = <7>; ++ fsl,pcs-tx-deemph-3p5db = <0x21>; ++ fsl,phy-pcs-tx-swing-full = <0x7f>; ++ status = "okay"; ++}; ++ ++&usb3_0 { ++ status = "okay"; ++}; ++ ++&usb_dwc3_0 { ++ dr_mode = "host"; ++ snps,dis-u1-entry-quirk; ++ snps,dis-u2-entry-quirk; ++ status = "okay"; ++}; ++ ++&usb3_phy1 { ++ fsl,phy-tx-preemp-amp-tune = <3>; ++ fsl,phy-tx-vref-tune = <0xb>; ++ status = "okay"; ++}; ++ ++&usb3_1 { ++ status = "okay"; ++}; ++ ++&usb_dwc3_1 { ++ dr_mode = "host"; ++ snps,parkmode-disable-ss-quirk; ++ status = "okay"; ++}; ++ ++&usdhc2 { ++ assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; ++ assigned-clock-rates = <400000000>; ++ pinctrl-names = "default", "state_100mhz", "state_200mhz"; ++ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; ++ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; ++ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; ++ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; ++ vmmc-supply = <®_usdhc2_vmmc>; ++ voltage-ranges = <1800 1800 3300 3300>; ++ bus-width = <4>; ++ status = "okay"; ++}; ++ ++/* ++CAN MUX: ++ EXT_CAN = 0 ++ NXP/REN = 1 ++*/ ++&flexcan1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_flexcan1>; ++ xceiver-supply = <®_can1_stby>; ++ status = "okay"; ++}; ++ ++&flexcan2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_flexcan2>; ++ xceiver-supply = <®_can2_stby>; ++ status = "okay"; ++}; ++ ++&iomuxc { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_hog>; ++ ++ pinctrl_ecspi2: ecspi2grp { ++ fsl,pins = < ++ MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 ++ MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 ++ MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 ++ >; ++ }; ++ ++ pinctrl_ecspi2_cs: ecspi2cs { ++ fsl,pins = < ++ MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40000 ++ >; ++ }; ++ ++ pinctrl_hog: hoggrp { ++ fsl,pins = < ++ >; ++ }; ++ ++ pinctrl_i2c2: i2c2grp { ++ fsl,pins = < ++ MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 ++ MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3 ++ >; ++ }; ++ ++ pinctrl_i2c3: i2c3grp { ++ fsl,pins = < ++ MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 ++ MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 ++ >; ++ }; ++ ++ pinctrl_flexspi0: flexspi0grp { ++ fsl,pins = < ++ MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 ++ MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 ++ MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 ++ MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 ++ MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 ++ >; ++ }; ++ ++ pinctrl_pwm4: pwm4grp { ++ fsl,pins = < ++ MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x116 ++ >; ++ }; ++ ++ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { ++ fsl,pins = < ++ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 ++ >; ++ }; ++ ++ pinctrl_uart3: uart3grp { ++ fsl,pins = < ++ MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 ++ MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 ++ //MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x40 ++ >; ++ }; ++ ++ pinctrl_uart4: uart4grp { ++ fsl,pins = < ++ MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140 ++ MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140 ++ //MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x40 ++ >; ++ }; ++ ++ pinctrl_usdhc2: usdhc2grp { ++ fsl,pins = < ++ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 ++ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 ++ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 ++ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 ++ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 ++ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 ++ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 ++ >; ++ }; ++ ++ pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { ++ fsl,pins = < ++ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 ++ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 ++ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 ++ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 ++ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 ++ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 ++ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 ++ >; ++ }; ++ ++ pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { ++ fsl,pins = < ++ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 ++ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 ++ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 ++ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 ++ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 ++ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 ++ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 ++ >; ++ }; ++ ++ pinctrl_usdhc2_gpio: usdhc2grp-gpio { ++ fsl,pins = < ++ MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 ++ >; ++ }; ++ ++ /* CANBUS */ ++ ++ pinctrl_flexcan1: flexcan1grp { ++ fsl,pins = < ++ MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 ++ MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 ++ >; ++ }; ++ ++ pinctrl_flexcan2: flexcan2grp { ++ fsl,pins = < ++ MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 ++ MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 ++ >; ++ }; ++ ++ pinctrl_flexcan1_reg: flexcan1reggrp { ++ fsl,pins = < ++ MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */ ++ >; ++ }; ++ ++ pinctrl_flexcan2_reg: flexcan2reggrp { ++ fsl,pins = < ++ MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */ ++ >; ++ }; ++ ++}; +\ No newline at end of file +-- +2.25.1 + diff --git a/recipes-kernel/linux/linux-imx_5.15.bbappend b/recipes-kernel/linux/linux-imx_5.15.bbappend index e3a6bbd..7a807bb 100644 --- a/recipes-kernel/linux/linux-imx_5.15.bbappend +++ b/recipes-kernel/linux/linux-imx_5.15.bbappend @@ -17,12 +17,17 @@ SRC_URI += " \ file://0012-arm64-dts-add-support-for-imx8mp-hummingboard-extend.patch \ file://0013-arm64-dts-split-pcie-reset-signals-for-hb-pulse-and-.patch \ file://0014-adv7511-driver-update.patch \ + file://0015-arm64-dts-add-support-for-imx8mp-hummingboard-pro.patch \ file://0016-Revert-net-rfkill-gpio-add-device-tree-support.patch \ file://0017-net-rfkill-gpio-add-DT-support.patch \ file://0018-net-rfkill-gpio-prevent-value-glitch-during-probe.patch \ file://0019-net-rfkill-gpio-set-GPIO-direction.patch \ file://0020-arm64-dts-imx8mp-hummingboard-pulse-use-upstream-rfk.patch \ file://0021-arm64-dts-imx8mp-sr-som-add-ethernet-phy-interrupt-s.patch \ + file://0022-arm64-dts-imx8mp-sr-som-fix-phy-interrupt-support.patch \ + file://0023-net-stmmac-don-t-reject-VLANs-when-IFF_PROMISC-is-se.patch \ + file://0024-USB-serial-option-add-Quectel-EM05GV2.patch \ + file://0025-arm64-dts-add-support-for-imx8mp-hummingboard-iiot.patch \ file://0100-dt-bindings-net-adin-document-phy-clock-output-prope.patch \ file://0101-dt-bindings-net-adin-add-pin-polarity-properties-for.patch \ file://0102-net-phy-adin-add-support-for-setting-led-link-status.patch \