MUX4T1_32.v

`timescale 1ns / 1ps
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// Company: 
// Engineer: 
// 
// Create Date:    00:52:55 12/28/2015 
// Design Name: 
// Module Name:    MUX8T1_32 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
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module   MUX4T1_32(input [1:0]s,
						 input [31:0]I0,
						 input [31:0]I1,
						 input [31:0]I2,
						 input [31:0]I3,						
						 output reg [31:0]o
						 );

		always @ * //32位4选一,I0、I1、I2、I3对应选择通道0、1、2、3
			case(s)
				2'd0: o = I0;
				2'd1: o = I1;
				2'd2: o = I2;
				2'd3: o = I3;
			endcase	
endmodule