Skip to content

Latest commit

 

History

History
37 lines (22 loc) · 1.01 KB

README.md

File metadata and controls

37 lines (22 loc) · 1.01 KB

Rydev Blog

Welcome to the Rydev Blog code repository. Here you will find all the resources and documentation needed to understand and navigate the project.

Table of Contents

  • Project Description
  • Getting Started
  • Tests
  • Deployment
  • Contributing
  • License

Project Description

Rydev Blog is designed to showcase our progress in ASIC and FPGA Design and Verification to the community. So that anyone interested can delve into this world with the latest tools.

Getting Started

These are the steps to set up the project locally...

Prerequisites

  • You can run this repo on both Windows and Linux. This project will use open software to simulate and test the designs.

Installation

  1. Clone the repository git clone https://github.com/username/rydev-blog.git

Contributing

For more information please go to the wiki, currently in development Simulate RTL Designs with Ease

License

Open source.