From b03470b81485281d9f2bdce5e44cc2cac4220d97 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper@sifive.com>
Date: Thu, 12 Dec 2024 11:46:47 -0800
Subject: [PATCH] [RISCV] Use a switch instead of an if/else chain. NFC

---
 llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 01dc9b9c3efcbd..91f8a2f47e21c9 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -3199,21 +3199,27 @@ std::string RISCVInstrInfo::createMIROperandComment(
 
   // Print the full VType operand of vsetvli/vsetivli instructions, and the SEW
   // operand of vector codegen pseudos.
-  if (OpInfo.OperandType == RISCVOp::OPERAND_VTYPEI10 ||
-      OpInfo.OperandType == RISCVOp::OPERAND_VTYPEI11) {
+  switch (OpInfo.OperandType) {
+  case RISCVOp::OPERAND_VTYPEI10:
+  case RISCVOp::OPERAND_VTYPEI11: {
     unsigned Imm = Op.getImm();
     RISCVVType::printVType(Imm, OS);
-  } else if (OpInfo.OperandType == RISCVOp::OPERAND_SEW) {
+    break;
+  }
+  case RISCVOp::OPERAND_SEW: {
     unsigned Log2SEW = Op.getImm();
     unsigned SEW = Log2SEW ? 1 << Log2SEW : 8;
     assert(RISCVVType::isValidSEW(SEW) && "Unexpected SEW");
     OS << "e" << SEW;
-  } else if (OpInfo.OperandType == RISCVOp::OPERAND_VEC_POLICY) {
+    break;
+  }
+  case RISCVOp::OPERAND_VEC_POLICY:
     unsigned Policy = Op.getImm();
     assert(Policy <= (RISCVII::TAIL_AGNOSTIC | RISCVII::MASK_AGNOSTIC) &&
            "Invalid Policy Value");
     OS << (Policy & RISCVII::TAIL_AGNOSTIC ? "ta" : "tu") << ", "
        << (Policy & RISCVII::MASK_AGNOSTIC ? "ma" : "mu");
+    break;
   }
 
   return Comment;