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Verify post-pnr simulation for PP3 #498

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mkurc-ant opened this issue Sep 2, 2021 · 1 comment
Open

Verify post-pnr simulation for PP3 #498

mkurc-ant opened this issue Sep 2, 2021 · 1 comment

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@mkurc-ant
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Once PP3 support is merged to master verify that post-pnr simulation using Verilog netlist and SDF timing annotation generated by VPR can be used to simulate a design.
@mkurc-ant
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A PR is open (#504) with all the necessary fixes required for running post-pnr simulations for PP3

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