From 9eca323ee581b7a940dd9f445f2bea81821a96ad Mon Sep 17 00:00:00 2001 From: Tony Wu Date: Tue, 2 May 2023 20:01:56 +1000 Subject: [PATCH] Alveo U250 support --- Makefile | 9 +- hw/shells/xilinx_u250/xdma_gen3x8/build.tcl | 42 + hw/shells/xilinx_u250/xdma_gen3x8/edit.tcl | 21 + .../xilinx_u250/xdma_gen3x8/floorplan.xdc | 12 + hw/shells/xilinx_u250/xdma_gen3x8/io.xdc | 55 + hw/shells/xilinx_u250/xdma_gen3x8/misc.xdc | 12 + hw/shells/xilinx_u250/xdma_gen3x8/shell.bd | 2258 +++++++++++++++++ hw/shells/xilinx_u250/xdma_gen3x8/top.v | 242 ++ hw/shells/xilinx_u250/xdma_gen3x8/user.bd | 933 +++++++ 9 files changed, 3581 insertions(+), 3 deletions(-) create mode 100644 hw/shells/xilinx_u250/xdma_gen3x8/build.tcl create mode 100644 hw/shells/xilinx_u250/xdma_gen3x8/edit.tcl create mode 100644 hw/shells/xilinx_u250/xdma_gen3x8/floorplan.xdc create mode 100644 hw/shells/xilinx_u250/xdma_gen3x8/io.xdc create mode 100644 hw/shells/xilinx_u250/xdma_gen3x8/misc.xdc create mode 100644 hw/shells/xilinx_u250/xdma_gen3x8/shell.bd create mode 100644 hw/shells/xilinx_u250/xdma_gen3x8/top.v create mode 100644 hw/shells/xilinx_u250/xdma_gen3x8/user.bd diff --git a/Makefile b/Makefile index 78c8812..bbf0e5c 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,10 @@ +# Supported boards and targets: +# xilinx_u55n [xdma_gen3x8 xdma_gen4x4] +# xilinx_u250 [xdma_gen3x8] +# sqrl_cle215 [xdma_gen2x4] + TARGET_BOARD=xilinx_u55n -TARGET_SHELL=xdma_gen3x8 -# TARGET_BOARD=sqrl_cle215 -# TARGET_SHELL=xdma_gen2x4 +TARGET_SHELL=xdma_gen4x4 build_shell: mkdir -p ./build/$(TARGET_BOARD)/$(TARGET_SHELL)/ diff --git a/hw/shells/xilinx_u250/xdma_gen3x8/build.tcl b/hw/shells/xilinx_u250/xdma_gen3x8/build.tcl new file mode 100644 index 0000000..888c5f2 --- /dev/null +++ b/hw/shells/xilinx_u250/xdma_gen3x8/build.tcl @@ -0,0 +1,42 @@ +set script_path [file dirname [file normalize [info script]]] + +create_project -part xcu250-figd2104-2-e synth synth +set_property source_mgmt_mode All [current_project] + +# -- [READ FILES] ------------------------------------------------------------- +import_files ${script_path}/shell.bd +import_files ${script_path}/user.bd +import_files "${script_path}/io.xdc" +import_files "${script_path}/misc.xdc" +import_files "${script_path}/floorplan.xdc" +import_files "${script_path}/top.v" +# ----------------------------------------------------------------------------- + +# -- [GENERATE BDS] ----------------------------------------------------------- +set_property synth_checkpoint_mode Hierarchical [get_files shell.bd] +set_property synth_checkpoint_mode Hierarchical [get_files user.bd] +generate_target all [get_files shell.bd] +generate_target all [get_files user.bd] +# ----------------------------------------------------------------------------- + +# -- [COMPILE] ---------------------------------------------------------------- +export_ip_user_files -of_objects [get_files shell.bd] -no_script -sync -force -quiet +export_ip_user_files -of_objects [get_files user.bd] -no_script -sync -force -quiet +create_ip_run [get_files -of_objects [get_fileset sources_1] shell.bd] +create_ip_run [get_files -of_objects [get_fileset sources_1] user.bd] + +launch_runs synth_1 -jobs 16 +wait_on_runs synth_1 + +open_run synth_1 +write_checkpoint -force ./post_synth_xilinx_u250_xdma_gen3x8.dcp +opt_design -directive Explore +place_design -directive Auto_1 +phys_opt_design -directive ExploreWithAggressiveHoldFix +route_design -directive AggressiveExplore +phys_opt_design -directive ExploreWithAggressiveHoldFix +write_checkpoint ./post_route_xilinx_u250_xdma_gen3x8.dcp +write_bitstream -bin_file -force ./warpshell_xilinx_u250_xdma_gen3x8.bit +write_abstract_shell -cell user_partition -force ./abstract_warpshell_xilinx_u250_xdma_gen3x8.dcp +write_cfgmem -force -format mcs -interface spix4 -size 128 -loadbit "up 0x01002000 warpshell_xilinx_u250_xdma_gen3x8.bit" -file "warpshell_xilinx_u250_xdma_gen3x8.mcs" +# ----------------------------------------------------------------------------- diff --git a/hw/shells/xilinx_u250/xdma_gen3x8/edit.tcl b/hw/shells/xilinx_u250/xdma_gen3x8/edit.tcl new file mode 100644 index 0000000..6ac5cea --- /dev/null +++ b/hw/shells/xilinx_u250/xdma_gen3x8/edit.tcl @@ -0,0 +1,21 @@ +set script_path [file dirname [file normalize [info script]]] + +create_project -in_memory -part xcu250-figd2104-2-e +set_property source_mgmt_mode All [current_project] + +proc commit {} { + validate_bd_design + save_bd_design + set bd [current_bd_design] + puts "Writing to: $::script_path/${bd}.bd" + file copy -force ./${bd}/${bd}.bd $::script_path/ +} + +file mkdir ./shell/ +file mkdir ./user/ +file copy ${script_path}/shell.bd ./shell/shell.bd +file copy ${script_path}/user.bd ./user/user.bd +read_bd ./shell/shell.bd +read_bd ./user/user.bd + +start_gui diff --git a/hw/shells/xilinx_u250/xdma_gen3x8/floorplan.xdc b/hw/shells/xilinx_u250/xdma_gen3x8/floorplan.xdc new file mode 100644 index 0000000..f2e6cd0 --- /dev/null +++ b/hw/shells/xilinx_u250/xdma_gen3x8/floorplan.xdc @@ -0,0 +1,12 @@ +create_pblock shell_partition +resize_pblock shell_partition -add {CLOCKREGION_X7Y4:CLOCKREGION_X7Y7} +add_cells_to_pblock shell_partition [get_cells shell_partition] + +create_pblock user_partition +resize_pblock user_partition -add {CLOCKREGION_X0Y0:CLOCKREGION_X7Y3} +resize_pblock user_partition -add {CLOCKREGION_X0Y4:CLOCKREGION_X6Y7} +resize_pblock user_partition -add {CLOCKREGION_X0Y8:CLOCKREGION_X7Y11} +resize_pblock user_partition -add {CLOCKREGION_X0Y12:CLOCKREGION_X7Y15} +resize_pblock user_partition -remove {IOB_X0Y217 IOB_X0Y218 IOB_X0Y219 IOB_X0Y220 IOB_X0Y255 IOB_X0Y244 IOB_X0Y245} +add_cells_to_pblock user_partition [get_cells user_partition] +set_property HD.RECONFIGURABLE TRUE [get_cells user_partition] diff --git a/hw/shells/xilinx_u250/xdma_gen3x8/io.xdc b/hw/shells/xilinx_u250/xdma_gen3x8/io.xdc new file mode 100644 index 0000000..040d745 --- /dev/null +++ b/hw/shells/xilinx_u250/xdma_gen3x8/io.xdc @@ -0,0 +1,55 @@ +# -- [Clocks] ------------------------------------------------------------------ +# pcie refclock +create_clock -period 10.000 -name pcie_refclk [get_ports pcie_refclk_clk_p] +# ------------------------------------------------------------------------------ + +# -- [Clock Pins] -------------------------------------------------------------- +set_property PACKAGE_PIN AM10 [get_ports pcie_refclk_clk_n] +set_property PACKAGE_PIN AM11 [get_ports pcie_refclk_clk_p] +# ------------------------------------------------------------------------------ + +# -- [PCIE Pins] --------------------------------------------------------------- +set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN BD21} [get_ports pcie_rstn] + +set_property PACKAGE_PIN AN8 [get_ports { pcie_mgt_txn[7] }] +set_property PACKAGE_PIN AN9 [get_ports { pcie_mgt_txp[7] }] +set_property PACKAGE_PIN AN3 [get_ports { pcie_mgt_rxn[7] }] +set_property PACKAGE_PIN AN4 [get_ports { pcie_mgt_rxp[7] }] +set_property PACKAGE_PIN AM6 [get_ports { pcie_mgt_txn[6] }] +set_property PACKAGE_PIN AM7 [get_ports { pcie_mgt_txp[6] }] +set_property PACKAGE_PIN AM1 [get_ports { pcie_mgt_rxn[6] }] +set_property PACKAGE_PIN AM2 [get_ports { pcie_mgt_rxp[6] }] +set_property PACKAGE_PIN AL8 [get_ports { pcie_mgt_txn[5] }] +set_property PACKAGE_PIN AL9 [get_ports { pcie_mgt_txp[5] }] +set_property PACKAGE_PIN AL3 [get_ports { pcie_mgt_rxn[5] }] +set_property PACKAGE_PIN AL4 [get_ports { pcie_mgt_rxp[5] }] +set_property PACKAGE_PIN AK6 [get_ports { pcie_mgt_txn[4] }] +set_property PACKAGE_PIN AK7 [get_ports { pcie_mgt_txp[4] }] +set_property PACKAGE_PIN AK1 [get_ports { pcie_mgt_rxn[4] }] +set_property PACKAGE_PIN AK2 [get_ports { pcie_mgt_rxp[4] }] +set_property PACKAGE_PIN AJ8 [get_ports { pcie_mgt_txn[3] }] +set_property PACKAGE_PIN AJ9 [get_ports { pcie_mgt_txp[3] }] +set_property PACKAGE_PIN AJ3 [get_ports { pcie_mgt_rxn[3] }] +set_property PACKAGE_PIN AJ4 [get_ports { pcie_mgt_rxp[3] }] +set_property PACKAGE_PIN AH6 [get_ports { pcie_mgt_txn[2] }] +set_property PACKAGE_PIN AH7 [get_ports { pcie_mgt_txp[2] }] +set_property PACKAGE_PIN AH1 [get_ports { pcie_mgt_rxn[2] }] +set_property PACKAGE_PIN AH2 [get_ports { pcie_mgt_rxp[2] }] +set_property PACKAGE_PIN AG8 [get_ports { pcie_mgt_txn[1] }] +set_property PACKAGE_PIN AG9 [get_ports { pcie_mgt_txp[1] }] +set_property PACKAGE_PIN AG3 [get_ports { pcie_mgt_rxn[1] }] +set_property PACKAGE_PIN AG4 [get_ports { pcie_mgt_rxp[1] }] +set_property PACKAGE_PIN AF6 [get_ports { pcie_mgt_txn[0] }] +set_property PACKAGE_PIN AF7 [get_ports { pcie_mgt_txp[0] }] +set_property PACKAGE_PIN AF1 [get_ports { pcie_mgt_rxn[0] }] +set_property PACKAGE_PIN AF2 [get_ports { pcie_mgt_rxp[0] }] +# ------------------------------------------------------------------------------ + +# -- [Satellite Controller Pins] ----------------------------------------------- +set_property -dict { IOSTANDARD LVCMOS12 PACKAGE_PIN AN21 } [get_ports { satellite_gpio[3] }] +set_property -dict { IOSTANDARD LVCMOS12 PACKAGE_PIN AM21 } [get_ports { satellite_gpio[2] }] +set_property -dict { IOSTANDARD LVCMOS12 PACKAGE_PIN AM20 } [get_ports { satellite_gpio[1] }] +set_property -dict { IOSTANDARD LVCMOS12 PACKAGE_PIN AR20 } [get_ports { satellite_gpio[0] }] +set_property -dict { IOSTANDARD LVCMOS12 PACKAGE_PIN BA19 } [get_ports satellite_uart_rxd] +set_property -dict { IOSTANDARD LVCMOS12 PACKAGE_PIN BB19 } [get_ports satellite_uart_txd] +# ------------------------------------------------------------------------------ diff --git a/hw/shells/xilinx_u250/xdma_gen3x8/misc.xdc b/hw/shells/xilinx_u250/xdma_gen3x8/misc.xdc new file mode 100644 index 0000000..f995ab2 --- /dev/null +++ b/hw/shells/xilinx_u250/xdma_gen3x8/misc.xdc @@ -0,0 +1,12 @@ +# -- [CONFIG] ----------------------------------------------------------------- +set_property CONFIG_VOLTAGE 1.8 [current_design] +set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design] +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +set_property CONFIG_MODE SPIx4 [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 63.8 [current_design] +set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design] +set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] +set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] +set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] +# ----------------------------------------------------------------------------- diff --git a/hw/shells/xilinx_u250/xdma_gen3x8/shell.bd b/hw/shells/xilinx_u250/xdma_gen3x8/shell.bd new file mode 100644 index 0000000..5e2d885 --- /dev/null +++ b/hw/shells/xilinx_u250/xdma_gen3x8/shell.bd @@ -0,0 +1,2258 @@ +{ + "design": { + "design_info": { + "boundary_crc": "0x2C264B02CCACC96", + "device": "xcu250-figd2104-2-e", + "name": "shell", + "rev_ctrl_bd_flag": "RevCtrlBdOff", + "synth_flow_mode": "None", + "tool_version": "2022.2", + "validated": "true" + }, + "design_tree": { + "xdma": "", + "pcie_refclk_buf": "", + "debug_bridge": "", + "mgmt_clk_wiz": "", + "hbicap": "", + "qspi": "", + "axi_interconnect_dma": { + "xbar": "", + "s00_couplers": {}, + "m00_couplers": { + "auto_ds": "" + }, + "m01_couplers": {} + }, + "smartconnect_ctrl": "", + "cms": "", + "mgmt_ram": "", + "mgmt_ram_bram": "", + "ctrl_firewall": "", + "dma_firewall": "", + "dfx_decoupler": "", + "inv_decouple_status": "", + "shell_resetn": "" + }, + "interface_ports": { + "pcie_refclk": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:diff_clock:1.0", + "vlnv": "xilinx.com:interface:diff_clock_rtl:1.0", + "parameters": { + "CAN_DEBUG": { + "value": "false", + "value_src": "default" + }, + "FREQ_HZ": { + "value": "100000000", + "value_src": "default" + } + }, + "port_maps": { + "CLK_P": { + "physical_name": "pcie_refclk_clk_p", + "direction": "I", + "left": "0", + "right": "0" + }, + "CLK_N": { + "physical_name": "pcie_refclk_clk_n", + "direction": "I", + "left": "0", + "right": "0" + } + } + }, + "bscan": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:bscan:1.0", + "vlnv": "xilinx.com:interface:bscan_rtl:1.0", + "port_maps": { + "BSCANID_EN": { + "physical_name": "bscan_bscanid_en", + "direction": "O" + }, + "CAPTURE": { + "physical_name": "bscan_capture", + "direction": "O" + }, + "DRCK": { + "physical_name": "bscan_drck", + "direction": "O" + }, + "RESET": { + "physical_name": "bscan_reset", + "direction": "O" + }, + "RUNTEST": { + "physical_name": "bscan_runtest", + "direction": "O" + }, + "SEL": { + "physical_name": "bscan_sel", + "direction": "O" + }, + "SHIFT": { + "physical_name": "bscan_shift", + "direction": "O" + }, + "TCK": { + "physical_name": "bscan_tck", + "direction": "O" + }, + "TDI": { + "physical_name": "bscan_tdi", + "direction": "O" + }, + "TDO": { + "physical_name": "bscan_tdo", + "direction": "I" + }, + "TMS": { + "physical_name": "bscan_tms", + "direction": "O" + }, + "UPDATE": { + "physical_name": "bscan_update", + "direction": "O" + } + } + }, + "pcie_mgt": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:pcie_7x_mgt:1.0", + "vlnv": "xilinx.com:interface:pcie_7x_mgt_rtl:1.0", + "port_maps": { + "rxn": { + "physical_name": "pcie_mgt_rxn", + "direction": "I", + "left": "7", + "right": "0" + }, + "rxp": { + "physical_name": "pcie_mgt_rxp", + "direction": "I", + "left": "7", + "right": "0" + }, + "txn": { + "physical_name": "pcie_mgt_txn", + "direction": "O", + "left": "7", + "right": "0" + }, + "txp": { + "physical_name": "pcie_mgt_txp", + "direction": "O", + "left": "7", + "right": "0" + } + } + }, + "satellite_uart": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:uart:1.0", + "vlnv": "xilinx.com:interface:uart_rtl:1.0", + "port_maps": { + "RxD": { + "physical_name": "satellite_uart_rxd", + "direction": "I" + }, + "TxD": { + "physical_name": "satellite_uart_txd", + "direction": "O" + } + } + }, + "shell_axil_ctrl": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "parameters": { + "ADDR_WIDTH": { + "value": "32" + }, + "ARUSER_WIDTH": { + "value": "0", + "value_src": "ip_prop" + }, + "AWUSER_WIDTH": { + "value": "0", + "value_src": "ip_prop" + }, + "BUSER_WIDTH": { + "value": "0", + "value_src": "ip_prop" + }, + "CLK_DOMAIN": { + "value": "shell_xdma_0_axi_aclk", + "value_src": "default_prop" + }, + "DATA_WIDTH": { + "value": "32" + }, + "FREQ_HZ": { + "value": "250000000", + "value_src": "user_prop" + }, + "HAS_BRESP": { + "value": "1", + "value_src": "default" + }, + "HAS_BURST": { + "value": "0" + }, + "HAS_CACHE": { + "value": "0", + "value_src": "default" + }, + "HAS_LOCK": { + "value": "0" + }, + "HAS_PROT": { + "value": "1", + "value_src": "default" + }, + "HAS_QOS": { + "value": "0", + "value_src": "default" + }, + "HAS_REGION": { + "value": "0", + "value_src": "const_prop" + }, + "HAS_RRESP": { + "value": "1", + "value_src": "default" + }, + "HAS_WSTRB": { + "value": "1", + "value_src": "default" + }, + "ID_WIDTH": { + "value": "0", + "value_src": "ip_prop" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "MAX_BURST_LENGTH": { + "value": "1", + "value_src": "user_prop" + }, + "NUM_READ_OUTSTANDING": { + "value": "1" + }, + "NUM_READ_THREADS": { + "value": "1", + "value_src": "user_prop" + }, + "NUM_WRITE_OUTSTANDING": { + "value": "1" + }, + "NUM_WRITE_THREADS": { + "value": "1", + "value_src": "user_prop" + }, + "PHASE": { + "value": "0.0", + "value_src": "default" + }, + "PROTOCOL": { + "value": "AXI4LITE" + }, + "READ_WRITE_MODE": { + "value": "READ_WRITE", + "value_src": "ip_prop" + }, + "RUSER_BITS_PER_BYTE": { + "value": "0", + "value_src": "user_prop" + }, + "RUSER_WIDTH": { + "value": "0", + "value_src": "ip_prop" + }, + "SUPPORTS_NARROW_BURST": { + "value": "0", + "value_src": "default_prop" + }, + "WUSER_BITS_PER_BYTE": { + "value": "0", + "value_src": "user_prop" + }, + "WUSER_WIDTH": { + "value": "0", + "value_src": "ip_prop" + } + }, + "memory_map_ref": "shell_axil_ctrl", + "port_maps": { + "ARADDR": { + "physical_name": "shell_axil_ctrl_araddr", + "direction": "O", + "left": "31", + "right": "0" + }, + "ARPROT": { + "physical_name": "shell_axil_ctrl_arprot", + "direction": "O", + "left": "2", + "right": "0" + }, + "ARREADY": { + "physical_name": "shell_axil_ctrl_arready", + "direction": "I" + }, + "ARVALID": { + "physical_name": "shell_axil_ctrl_arvalid", + "direction": "O" + }, + "AWADDR": { + "physical_name": "shell_axil_ctrl_awaddr", + "direction": "O", + "left": "31", + "right": "0" + }, + "AWPROT": { + "physical_name": "shell_axil_ctrl_awprot", + "direction": "O", + "left": "2", + "right": "0" + }, + "AWREADY": { + "physical_name": "shell_axil_ctrl_awready", + "direction": "I" + }, + "AWVALID": { + "physical_name": "shell_axil_ctrl_awvalid", + "direction": "O" + }, + "BREADY": { + "physical_name": "shell_axil_ctrl_bready", + "direction": "O" + }, + "BRESP": { + "physical_name": "shell_axil_ctrl_bresp", + "direction": "I", + "left": "1", + "right": "0" + }, + "BVALID": { + "physical_name": "shell_axil_ctrl_bvalid", + "direction": "I" + }, + "RDATA": { + "physical_name": "shell_axil_ctrl_rdata", + "direction": "I", + "left": "31", + "right": "0" + }, + "RREADY": { + "physical_name": "shell_axil_ctrl_rready", + "direction": "O" + }, + "RRESP": { + "physical_name": "shell_axil_ctrl_rresp", + "direction": "I", + "left": "1", + "right": "0" + }, + "RVALID": { + "physical_name": "shell_axil_ctrl_rvalid", + "direction": "I" + }, + "WDATA": { + "physical_name": "shell_axil_ctrl_wdata", + "direction": "O", + "left": "31", + "right": "0" + }, + "WREADY": { + "physical_name": "shell_axil_ctrl_wready", + "direction": "I" + }, + "WSTRB": { + "physical_name": "shell_axil_ctrl_wstrb", + "direction": "O", + "left": "3", + "right": "0" + }, + "WVALID": { + "physical_name": "shell_axil_ctrl_wvalid", + "direction": "O" + } + } + }, + "shell_axi_dma": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "parameters": { + "ADDR_WIDTH": { + "value": "64" + }, + "ARUSER_WIDTH": { + "value": "0", + "value_src": "ip_prop" + }, + "AWUSER_WIDTH": { + "value": "0", + "value_src": "ip_prop" + }, + "BUSER_WIDTH": { + "value": "0", + "value_src": "ip_prop" + }, + "CLK_DOMAIN": { + "value": "shell_xdma_0_axi_aclk", + "value_src": "default_prop" + }, + "DATA_WIDTH": { + "value": "256" + }, + "FREQ_HZ": { + "value": "250000000", + "value_src": "user_prop" + }, + "HAS_BRESP": { + "value": "1", + "value_src": "const_prop" + }, + "HAS_BURST": { + "value": "1" + }, + "HAS_CACHE": { + "value": "1", + "value_src": "const_prop" + }, + "HAS_LOCK": { + "value": "1", + "value_src": "const_prop" + }, + "HAS_PROT": { + "value": "1", + "value_src": "const_prop" + }, + "HAS_QOS": { + "value": "1" + }, + "HAS_REGION": { + "value": "0" + }, + "HAS_RRESP": { + "value": "1", + "value_src": "const_prop" + }, + "HAS_WSTRB": { + "value": "1", + "value_src": "const_prop" + }, + "ID_WIDTH": { + "value": "4", + "value_src": "ip_prop" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "MAX_BURST_LENGTH": { + "value": "256", + "value_src": "ip_prop" + }, + "NUM_READ_OUTSTANDING": { + "value": "32" + }, + "NUM_READ_THREADS": { + "value": "1", + "value_src": "ip_prop" + }, + "NUM_WRITE_OUTSTANDING": { + "value": "16" + }, + "NUM_WRITE_THREADS": { + "value": "1", + "value_src": "ip_prop" + }, + "PHASE": { + "value": "0.0", + "value_src": "default" + }, + "PROTOCOL": { + "value": "AXI4" + }, + "READ_WRITE_MODE": { + "value": "READ_WRITE", + "value_src": "ip_prop" + }, + "RUSER_BITS_PER_BYTE": { + "value": "0", + "value_src": "ip_prop" + }, + "RUSER_WIDTH": { + "value": "0", + "value_src": "ip_prop" + }, + "SUPPORTS_NARROW_BURST": { + "value": "0", + "value_src": "default_prop" + }, + "WUSER_BITS_PER_BYTE": { + "value": "0", + "value_src": "ip_prop" + }, + "WUSER_WIDTH": { + "value": "0", + "value_src": "ip_prop" + } + }, + "memory_map_ref": "shell_axi_dma", + "port_maps": { + "ARADDR": { + "physical_name": "shell_axi_dma_araddr", + "direction": "O", + "left": "63", + "right": "0" + }, + "ARBURST": { + "physical_name": "shell_axi_dma_arburst", + "direction": "O", + "left": "1", + "right": "0" + }, + "ARCACHE": { + "physical_name": "shell_axi_dma_arcache", + "direction": "O", + "left": "3", + "right": "0" + }, + "ARLEN": { + "physical_name": "shell_axi_dma_arlen", + "direction": "O", + "left": "7", + "right": "0" + }, + "ARLOCK": { + "physical_name": "shell_axi_dma_arlock", + "direction": "O", + "left": "0", + "right": "0" + }, + "ARPROT": { + "physical_name": "shell_axi_dma_arprot", + "direction": "O", + "left": "2", + "right": "0" + }, + "ARQOS": { + "physical_name": "shell_axi_dma_arqos", + "direction": "O", + "left": "3", + "right": "0" + }, + "ARREADY": { + "physical_name": "shell_axi_dma_arready", + "direction": "I" + }, + "ARREGION": { + "physical_name": "shell_axi_dma_arregion", + "direction": "O", + "left": "3", + "right": "0" + }, + "ARSIZE": { + "physical_name": "shell_axi_dma_arsize", + "direction": "O", + "left": "2", + "right": "0" + }, + "ARVALID": { + "physical_name": "shell_axi_dma_arvalid", + "direction": "O" + }, + "AWADDR": { + "physical_name": "shell_axi_dma_awaddr", + "direction": "O", + "left": "63", + "right": "0" + }, + "AWBURST": { + "physical_name": "shell_axi_dma_awburst", + "direction": "O", + "left": "1", + "right": "0" + }, + "AWCACHE": { + "physical_name": "shell_axi_dma_awcache", + "direction": "O", + "left": "3", + "right": "0" + }, + "AWLEN": { + "physical_name": "shell_axi_dma_awlen", + "direction": "O", + "left": "7", + "right": "0" + }, + "AWLOCK": { + "physical_name": "shell_axi_dma_awlock", + "direction": "O", + "left": "0", + "right": "0" + }, + "AWPROT": { + "physical_name": "shell_axi_dma_awprot", + "direction": "O", + "left": "2", + "right": "0" + }, + "AWQOS": { + "physical_name": "shell_axi_dma_awqos", + "direction": "O", + "left": "3", + "right": "0" + }, + "AWREADY": { + "physical_name": "shell_axi_dma_awready", + "direction": "I" + }, + "AWREGION": { + "physical_name": "shell_axi_dma_awregion", + "direction": "O", + "left": "3", + "right": "0" + }, + "AWSIZE": { + "physical_name": "shell_axi_dma_awsize", + "direction": "O", + "left": "2", + "right": "0" + }, + "AWVALID": { + "physical_name": "shell_axi_dma_awvalid", + "direction": "O" + }, + "BREADY": { + "physical_name": "shell_axi_dma_bready", + "direction": "O" + }, + "BRESP": { + "physical_name": "shell_axi_dma_bresp", + "direction": "I", + "left": "1", + "right": "0" + }, + "BVALID": { + "physical_name": "shell_axi_dma_bvalid", + "direction": "I" + }, + "RDATA": { + "physical_name": "shell_axi_dma_rdata", + "direction": "I", + "left": "255", + "right": "0" + }, + "RLAST": { + "physical_name": "shell_axi_dma_rlast", + "direction": "I" + }, + "RREADY": { + "physical_name": "shell_axi_dma_rready", + "direction": "O" + }, + "RRESP": { + "physical_name": "shell_axi_dma_rresp", + "direction": "I", + "left": "1", + "right": "0" + }, + "RVALID": { + "physical_name": "shell_axi_dma_rvalid", + "direction": "I" + }, + "WDATA": { + "physical_name": "shell_axi_dma_wdata", + "direction": "O", + "left": "255", + "right": "0" + }, + "WLAST": { + "physical_name": "shell_axi_dma_wlast", + "direction": "O" + }, + "WREADY": { + "physical_name": "shell_axi_dma_wready", + "direction": "I" + }, + "WSTRB": { + "physical_name": "shell_axi_dma_wstrb", + "direction": "O", + "left": "31", + "right": "0" + }, + "WVALID": { + "physical_name": "shell_axi_dma_wvalid", + "direction": "O" + }, + "ARID": { + "physical_name": "shell_axi_dma_arid", + "direction": "O", + "left": "3", + "right": "0" + }, + "AWID": { + "physical_name": "shell_axi_dma_awid", + "direction": "O", + "left": "3", + "right": "0" + }, + "BID": { + "physical_name": "shell_axi_dma_bid", + "direction": "I", + "left": "3", + "right": "0" + }, + "RID": { + "physical_name": "shell_axi_dma_rid", + "direction": "I", + "left": "3", + "right": "0" + } + } + } + }, + "ports": { + "pcie_rstn": { + "type": "rst", + "direction": "I", + "parameters": { + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "POLARITY": { + "value": "ACTIVE_LOW", + "value_src": "default" + } + } + }, + "satellite_gpio": { + "type": "intr", + "direction": "I", + "left": "3", + "right": "0", + "parameters": { + "PortWidth": { + "value": "4" + }, + "SENSITIVITY": { + "value": "EDGE_RISING" + } + } + }, + "shell_rstn": { + "type": "rst", + "direction": "O", + "left": "0", + "right": "0", + "parameters": { + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "POLARITY": { + "value": "ACTIVE_LOW", + "value_src": "const_prop" + } + } + }, + "shell_axi_clk": { + "type": "clk", + "direction": "O", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "shell_axil_ctrl:shell_axi_dma" + }, + "ASSOCIATED_RESET": { + "value": "shell_rstn" + }, + "CLK_DOMAIN": { + "value": "shell_xdma_0_axi_aclk", + "value_src": "default_prop" + }, + "FREQ_HZ": { + "value": "250000000", + "value_src": "user_prop" + }, + "FREQ_TOLERANCE_HZ": { + "value": "0", + "value_src": "default" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "PHASE": { + "value": "0.0", + "value_src": "default" + } + } + } + }, + "components": { + "xdma": { + "vlnv": "xilinx.com:ip:xdma:4.1", + "xci_name": "shell_xdma_0", + "xci_path": "ip/shell_xdma_0/shell_xdma_0.xci", + "inst_hier_path": "xdma", + "parameters": { + "axil_master_64bit_en": { + "value": "false" + }, + "axilite_master_en": { + "value": "true" + }, + "axilite_master_size": { + "value": "128" + }, + "cfg_ext_if": { + "value": "true" + }, + "cfg_mgmt_if": { + "value": "false" + }, + "pcie_blk_locn": { + "value": "X0Y1" + }, + "pf0_Use_Class_Code_Lookup_Assistant": { + "value": "true" + }, + "pf0_base_class_menu": { + "value": "Processing_accelerators" + }, + "pl_link_cap_max_link_speed": { + "value": "8.0_GT/s" + }, + "pl_link_cap_max_link_width": { + "value": "X8" + } + }, + "interface_ports": { + "M_AXI": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Master", + "address_space_ref": "M_AXI", + "base_address": { + "minimum": "0x00000000", + "maximum": "0xFFFFFFFFFFFFFFFF", + "width": "64" + } + }, + "M_AXI_LITE": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Master", + "address_space_ref": "M_AXI_LITE", + "base_address": { + "minimum": "0x00000000", + "maximum": "0xFFFFFFFF", + "width": "32" + }, + "parameters": { + "master_id": { + "value": "1" + } + } + } + }, + "addressing": { + "address_spaces": { + "M_AXI": { + "range": "16E", + "width": "64" + }, + "M_AXI_LITE": { + "range": "4G", + "width": "32" + } + } + } + }, + "pcie_refclk_buf": { + "vlnv": "xilinx.com:ip:util_ds_buf:2.2", + "xci_name": "shell_pcie_refclk_buf_0", + "xci_path": "ip/shell_pcie_refclk_buf_0/shell_pcie_refclk_buf_0.xci", + "inst_hier_path": "pcie_refclk_buf", + "parameters": { + "C_BUF_TYPE": { + "value": "IBUFDSGTE" + } + } + }, + "debug_bridge": { + "vlnv": "xilinx.com:ip:debug_bridge:3.0", + "xci_name": "shell_debug_bridge_0", + "xci_path": "ip/shell_debug_bridge_0/shell_debug_bridge_0.xci", + "inst_hier_path": "debug_bridge", + "parameters": { + "C_BSCAN_MUX": { + "value": "2" + }, + "C_DEBUG_MODE": { + "value": "5" + } + }, + "interface_ports": { + "pcie3_cfg_ext": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:pcie3_cfg_ext:1.0", + "vlnv": "xilinx.com:interface:pcie3_cfg_ext_rtl:1.0" + }, + "m0_bscan": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:bscan:1.0", + "vlnv": "xilinx.com:interface:bscan_rtl:1.0" + } + } + }, + "mgmt_clk_wiz": { + "vlnv": "xilinx.com:ip:clk_wiz:6.0", + "xci_name": "shell_mgmt_clk_wiz_0", + "xci_path": "ip/shell_mgmt_clk_wiz_0/shell_mgmt_clk_wiz_0.xci", + "inst_hier_path": "mgmt_clk_wiz", + "parameters": { + "CLKOUT1_JITTER": { + "value": "102.484" + }, + "CLKOUT1_PHASE_ERROR": { + "value": "79.008" + }, + "CLKOUT2_JITTER": { + "value": "98.122" + }, + "CLKOUT2_PHASE_ERROR": { + "value": "79.008" + }, + "CLKOUT2_REQUESTED_OUT_FREQ": { + "value": "125.000" + }, + "CLKOUT2_USED": { + "value": "true" + }, + "CLK_OUT1_PORT": { + "value": "spi_clk" + }, + "CLK_OUT2_PORT": { + "value": "icap_clk" + }, + "MMCM_CLKFBOUT_MULT_F": { + "value": "5.000" + }, + "MMCM_CLKOUT0_DIVIDE_F": { + "value": "12.500" + }, + "MMCM_CLKOUT1_DIVIDE": { + "value": "10" + }, + "NUM_OUT_CLKS": { + "value": "2" + }, + "RESET_PORT": { + "value": "resetn" + }, + "RESET_TYPE": { + "value": "ACTIVE_LOW" + } + } + }, + "hbicap": { + "vlnv": "xilinx.com:ip:axi_hbicap:1.0", + "xci_name": "shell_hbicap_0", + "xci_path": "ip/shell_hbicap_0/shell_hbicap_0.xci", + "inst_hier_path": "hbicap", + "parameters": { + "C_WRITE_FIFO_DEPTH": { + "value": "1024" + } + } + }, + "qspi": { + "vlnv": "xilinx.com:ip:axi_quad_spi:3.2", + "xci_name": "shell_qspi_0", + "xci_path": "ip/shell_qspi_0/shell_qspi_0.xci", + "inst_hier_path": "qspi", + "parameters": { + "C_FIFO_DEPTH": { + "value": "256" + }, + "C_SPI_MEMORY": { + "value": "2" + }, + "C_SPI_MODE": { + "value": "2" + }, + "C_USE_STARTUP": { + "value": "1" + }, + "C_USE_STARTUP_INT": { + "value": "1" + } + } + }, + "axi_interconnect_dma": { + "vlnv": "xilinx.com:ip:axi_interconnect:2.1", + "xci_path": "ip/shell_axi_interconnect_dma_0/shell_axi_interconnect_dma_0.xci", + "inst_hier_path": "axi_interconnect_dma", + "xci_name": "shell_axi_interconnect_dma_0", + "interface_ports": { + "S00_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M00_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M01_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_RESET": { + "value": "ARESETN" + } + } + }, + "ARESETN": { + "type": "rst", + "direction": "I" + }, + "S00_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S00_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S00_ARESETN" + } + } + }, + "S00_ARESETN": { + "type": "rst", + "direction": "I" + }, + "M00_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M00_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M00_ARESETN" + } + } + }, + "M00_ARESETN": { + "type": "rst", + "direction": "I" + }, + "M01_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M01_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M01_ARESETN" + } + } + }, + "M01_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "components": { + "xbar": { + "vlnv": "xilinx.com:ip:axi_crossbar:2.1", + "xci_name": "shell_xbar_0", + "xci_path": "ip/shell_xbar_0/shell_xbar_0.xci", + "inst_hier_path": "axi_interconnect_dma/xbar", + "parameters": { + "NUM_MI": { + "value": "2" + }, + "NUM_SI": { + "value": "1" + }, + "STRATEGY": { + "value": "0" + } + }, + "interface_ports": { + "S00_AXI": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "bridges": [ + "M00_AXI", + "M01_AXI" + ] + } + } + }, + "s00_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "s00_couplers_to_s00_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + }, + "m00_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "components": { + "auto_ds": { + "vlnv": "xilinx.com:ip:axi_dwidth_converter:2.1", + "xci_name": "shell_auto_ds_0", + "xci_path": "ip/shell_auto_ds_0/shell_auto_ds_0.xci", + "inst_hier_path": "axi_interconnect_dma/m00_couplers/auto_ds", + "parameters": { + "MI_DATA_WIDTH": { + "value": "32" + }, + "SI_DATA_WIDTH": { + "value": "256" + } + }, + "interface_ports": { + "S_AXI": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "bridges": [ + "M_AXI" + ] + } + } + } + }, + "interface_nets": { + "auto_ds_to_m00_couplers": { + "interface_ports": [ + "M_AXI", + "auto_ds/M_AXI" + ] + }, + "m00_couplers_to_auto_ds": { + "interface_ports": [ + "S_AXI", + "auto_ds/S_AXI" + ] + } + }, + "nets": { + "S_ACLK_1": { + "ports": [ + "S_ACLK", + "auto_ds/s_axi_aclk" + ] + }, + "S_ARESETN_1": { + "ports": [ + "S_ARESETN", + "auto_ds/s_axi_aresetn" + ] + } + } + }, + "m01_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "interface_nets": { + "m01_couplers_to_m01_couplers": { + "interface_ports": [ + "S_AXI", + "M_AXI" + ] + } + } + } + }, + "interface_nets": { + "axi_interconnect_dma_to_s00_couplers": { + "interface_ports": [ + "S00_AXI", + "s00_couplers/S_AXI" + ] + }, + "m00_couplers_to_axi_interconnect_dma": { + "interface_ports": [ + "M00_AXI", + "m00_couplers/M_AXI" + ] + }, + "m01_couplers_to_axi_interconnect_dma": { + "interface_ports": [ + "M01_AXI", + "m01_couplers/M_AXI" + ] + }, + "s00_couplers_to_xbar": { + "interface_ports": [ + "s00_couplers/M_AXI", + "xbar/S00_AXI" + ] + }, + "xbar_to_m00_couplers": { + "interface_ports": [ + "xbar/M00_AXI", + "m00_couplers/S_AXI" + ] + }, + "xbar_to_m01_couplers": { + "interface_ports": [ + "xbar/M01_AXI", + "m01_couplers/S_AXI" + ] + } + }, + "nets": { + "axi_interconnect_dma_ACLK_net": { + "ports": [ + "ACLK", + "xbar/aclk", + "s00_couplers/S_ACLK", + "s00_couplers/M_ACLK", + "m00_couplers/M_ACLK", + "m01_couplers/M_ACLK", + "m00_couplers/S_ACLK", + "m01_couplers/S_ACLK" + ] + }, + "axi_interconnect_dma_ARESETN_net": { + "ports": [ + "ARESETN", + "xbar/aresetn", + "s00_couplers/S_ARESETN", + "s00_couplers/M_ARESETN", + "m00_couplers/M_ARESETN", + "m01_couplers/M_ARESETN", + "m00_couplers/S_ARESETN", + "m01_couplers/S_ARESETN" + ] + } + } + }, + "smartconnect_ctrl": { + "vlnv": "xilinx.com:ip:smartconnect:1.0", + "xci_name": "shell_smartconnect_ctrl_0", + "xci_path": "ip/shell_smartconnect_ctrl_0/shell_smartconnect_ctrl_0.xci", + "inst_hier_path": "smartconnect_ctrl", + "parameters": { + "NUM_MI": { + "value": "8" + }, + "NUM_SI": { + "value": "1" + } + }, + "interface_ports": { + "S00_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "parameters": { + "NUM_READ_OUTSTANDING": { + "value": "1" + }, + "NUM_WRITE_OUTSTANDING": { + "value": "1" + } + }, + "bridges": [ + "M00_AXI", + "M01_AXI", + "M02_AXI", + "M03_AXI", + "M04_AXI", + "M05_AXI", + "M06_AXI", + "M07_AXI" + ] + }, + "M00_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "parameters": { + "MAX_BURST_LENGTH": { + "value": "1" + }, + "NUM_READ_OUTSTANDING": { + "value": "1" + }, + "NUM_READ_THREADS": { + "value": "1" + }, + "NUM_WRITE_OUTSTANDING": { + "value": "1" + }, + "NUM_WRITE_THREADS": { + "value": "1" + }, + "RUSER_BITS_PER_BYTE": { + "value": "0" + }, + "SUPPORTS_NARROW_BURST": { + "value": "0" + }, + "WUSER_BITS_PER_BYTE": { + "value": "0" + } + } + }, + "M01_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "parameters": { + "MAX_BURST_LENGTH": { + "value": "1" + }, + "NUM_READ_OUTSTANDING": { + "value": "1" + }, + "NUM_READ_THREADS": { + "value": "1" + }, + "NUM_WRITE_OUTSTANDING": { + "value": "1" + }, + "NUM_WRITE_THREADS": { + "value": "1" + }, + "RUSER_BITS_PER_BYTE": { + "value": "0" + }, + "SUPPORTS_NARROW_BURST": { + "value": "0" + }, + "WUSER_BITS_PER_BYTE": { + "value": "0" + } + } + }, + "M02_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "parameters": { + "MAX_BURST_LENGTH": { + "value": "1" + }, + "NUM_READ_OUTSTANDING": { + "value": "1" + }, + "NUM_READ_THREADS": { + "value": "1" + }, + "NUM_WRITE_OUTSTANDING": { + "value": "1" + }, + "NUM_WRITE_THREADS": { + "value": "1" + }, + "RUSER_BITS_PER_BYTE": { + "value": "0" + }, + "SUPPORTS_NARROW_BURST": { + "value": "0" + }, + "WUSER_BITS_PER_BYTE": { + "value": "0" + } + } + }, + "M03_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "parameters": { + "MAX_BURST_LENGTH": { + "value": "1" + }, + "NUM_READ_OUTSTANDING": { + "value": "1" + }, + "NUM_READ_THREADS": { + "value": "1" + }, + "NUM_WRITE_OUTSTANDING": { + "value": "1" + }, + "NUM_WRITE_THREADS": { + "value": "1" + }, + "RUSER_BITS_PER_BYTE": { + "value": "0" + }, + "SUPPORTS_NARROW_BURST": { + "value": "0" + }, + "WUSER_BITS_PER_BYTE": { + "value": "0" + } + } + }, + "M04_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "parameters": { + "MAX_BURST_LENGTH": { + "value": "1" + }, + "NUM_READ_OUTSTANDING": { + "value": "1" + }, + "NUM_READ_THREADS": { + "value": "1" + }, + "NUM_WRITE_OUTSTANDING": { + "value": "1" + }, + "NUM_WRITE_THREADS": { + "value": "1" + }, + "RUSER_BITS_PER_BYTE": { + "value": "0" + }, + "SUPPORTS_NARROW_BURST": { + "value": "0" + }, + "WUSER_BITS_PER_BYTE": { + "value": "0" + } + } + }, + "M05_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "parameters": { + "MAX_BURST_LENGTH": { + "value": "1" + }, + "NUM_READ_OUTSTANDING": { + "value": "1" + }, + "NUM_READ_THREADS": { + "value": "1" + }, + "NUM_WRITE_OUTSTANDING": { + "value": "1" + }, + "NUM_WRITE_THREADS": { + "value": "1" + }, + "RUSER_BITS_PER_BYTE": { + "value": "0" + }, + "SUPPORTS_NARROW_BURST": { + "value": "0" + }, + "WUSER_BITS_PER_BYTE": { + "value": "0" + } + } + }, + "M06_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "parameters": { + "MAX_BURST_LENGTH": { + "value": "1" + }, + "NUM_READ_OUTSTANDING": { + "value": "1" + }, + "NUM_READ_THREADS": { + "value": "1" + }, + "NUM_WRITE_OUTSTANDING": { + "value": "1" + }, + "NUM_WRITE_THREADS": { + "value": "1" + }, + "RUSER_BITS_PER_BYTE": { + "value": "0" + }, + "SUPPORTS_NARROW_BURST": { + "value": "0" + }, + "WUSER_BITS_PER_BYTE": { + "value": "0" + } + } + }, + "M07_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "parameters": { + "MAX_BURST_LENGTH": { + "value": "1" + }, + "NUM_READ_OUTSTANDING": { + "value": "1" + }, + "NUM_READ_THREADS": { + "value": "1" + }, + "NUM_WRITE_OUTSTANDING": { + "value": "1" + }, + "NUM_WRITE_THREADS": { + "value": "1" + }, + "RUSER_BITS_PER_BYTE": { + "value": "0" + }, + "SUPPORTS_NARROW_BURST": { + "value": "0" + }, + "WUSER_BITS_PER_BYTE": { + "value": "0" + } + } + } + } + }, + "cms": { + "vlnv": "xilinx.com:ip:cms_subsystem:4.0", + "xci_name": "shell_cms_0", + "xci_path": "ip/shell_cms_0/shell_cms_0.xci", + "inst_hier_path": "cms", + "interface_ports": { + "s_axi_ctrl": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "parameters": { + "ADDR_WIDTH": { + "value": "18" + }, + "ARUSER_WIDTH": { + "value": "0" + }, + "AWUSER_WIDTH": { + "value": "0" + }, + "BUSER_WIDTH": { + "value": "0" + }, + "DATA_WIDTH": { + "value": "32" + }, + "HAS_BRESP": { + "value": "1" + }, + "HAS_BURST": { + "value": "0" + }, + "HAS_CACHE": { + "value": "0" + }, + "HAS_LOCK": { + "value": "0" + }, + "HAS_PROT": { + "value": "0" + }, + "HAS_QOS": { + "value": "0" + }, + "HAS_REGION": { + "value": "0" + }, + "HAS_RRESP": { + "value": "1" + }, + "HAS_WSTRB": { + "value": "1" + }, + "INSERT_VIP": { + "value": "1" + }, + "MAX_BURST_LENGTH": { + "value": "1" + }, + "NUM_READ_OUTSTANDING": { + "value": "2" + }, + "NUM_READ_THREADS": { + "value": "1" + }, + "NUM_WRITE_OUTSTANDING": { + "value": "2" + }, + "NUM_WRITE_THREADS": { + "value": "1" + }, + "PROTOCOL": { + "value": "AXI4LITE" + }, + "READ_WRITE_MODE": { + "value": "READ_WRITE" + }, + "RUSER_BITS_PER_BYTE": { + "value": "0" + }, + "RUSER_WIDTH": { + "value": "0" + }, + "SUPPORTS_NARROW_BURST": { + "value": "0" + }, + "WUSER_BITS_PER_BYTE": { + "value": "0" + }, + "WUSER_WIDTH": { + "value": "0" + } + }, + "memory_map_ref": "s_axi_ctrl" + }, + "satellite_uart": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:uart:1.0", + "vlnv": "xilinx.com:interface:uart_rtl:1.0" + } + }, + "addressing": { + "memory_maps": { + "s_axi_ctrl": { + "address_blocks": { + "Mem": { + "base_address": "0x00000", + "range": "256K", + "width": "18", + "usage": "memory", + "bank_blocks": { + "SEG_axi_bram_ctrl_firmware_Mem0;/axi_bram_ctrl_firmware/S_AXI/Mem0;xilinx.com:ip:axi_bram_ctrl:4.1;/axi_bram_ctrl_firmware;S_AXI;NONE;NONE": { + "base_address": "0x00000", + "range": "128K", + "width": "17", + "usage": "memory" + }, + "SEG_axi_gpio_cmc_mb_rst_n_Reg;/axi_gpio_cmc_mb_rst_n/S_AXI/Reg;xilinx.com:ip:axi_gpio:2.0;/axi_gpio_cmc_mb_rst_n;S_AXI;NONE;NONE": { + "base_address": "0x20000", + "range": "4K", + "width": "12", + "usage": "register" + }, + "SEG_axi_gpio_mutex_host_Reg;/axi_gpio_mutex_host/S_AXI/Reg;xilinx.com:ip:axi_gpio:2.0;/axi_gpio_mutex_host;S_AXI;NONE;NONE": { + "base_address": "0x21000", + "range": "4K", + "width": "12", + "usage": "register" + }, + "SEG_axi_intc_host_Reg;/axi_intc_host/S_AXI/Reg;xilinx.com:ip:axi_intc:4.1;/axi_intc_host;s_axi;NONE;NONE": { + "base_address": "0x22000", + "range": "4K", + "width": "12", + "usage": "register" + }, + "SEG_axi_bram_ctrl_regmap_host_Mem0;/axi_bram_ctrl_regmap_host/S_AXI/Mem0;xilinx.com:ip:axi_bram_ctrl:4.1;/axi_bram_ctrl_regmap_host;S_AXI;NONE;NONE": { + "base_address": "0x28000", + "range": "8K", + "width": "13", + "usage": "memory" + }, + "SEG_build_info_host_reg0;/build_info_host/S_AXI/reg0;xilinx.com:ip:shell_utils_build_info:1.0;/build_info_host;S_AXI;NONE;NONE": { + "base_address": "0x2A000", + "range": "4K", + "width": "12", + "usage": "register" + } + } + } + } + } + } + } + }, + "mgmt_ram": { + "vlnv": "xilinx.com:ip:axi_bram_ctrl:4.1", + "xci_name": "shell_mgmt_ram_0", + "xci_path": "ip/shell_mgmt_ram_0/shell_mgmt_ram_0.xci", + "inst_hier_path": "mgmt_ram", + "parameters": { + "PROTOCOL": { + "value": "AXI4LITE" + }, + "SINGLE_PORT_BRAM": { + "value": "1" + } + } + }, + "mgmt_ram_bram": { + "vlnv": "xilinx.com:ip:blk_mem_gen:8.4", + "xci_name": "shell_mgmt_ram_bram_0", + "xci_path": "ip/shell_mgmt_ram_bram_0/shell_mgmt_ram_bram_0.xci", + "inst_hier_path": "mgmt_ram_bram" + }, + "ctrl_firewall": { + "vlnv": "xilinx.com:ip:axi_firewall:1.2", + "xci_name": "shell_ctrl_firewall_0", + "xci_path": "ip/shell_ctrl_firewall_0/shell_ctrl_firewall_0.xci", + "inst_hier_path": "ctrl_firewall", + "interface_ports": { + "S_AXI": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "bridges": [ + "M_AXI" + ] + } + } + }, + "dma_firewall": { + "vlnv": "xilinx.com:ip:axi_firewall:1.2", + "xci_name": "shell_dma_firewall_0", + "xci_path": "ip/shell_dma_firewall_0/shell_dma_firewall_0.xci", + "inst_hier_path": "dma_firewall", + "interface_ports": { + "S_AXI": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "bridges": [ + "M_AXI" + ] + } + } + }, + "dfx_decoupler": { + "vlnv": "xilinx.com:ip:dfx_decoupler:1.0", + "xci_name": "shell_dfx_decoupler_0", + "xci_path": "ip/shell_dfx_decoupler_0/shell_dfx_decoupler_0.xci", + "inst_hier_path": "dfx_decoupler", + "parameters": { + "ALL_PARAMS": { + "value": "HAS_SIGNAL_CONTROL 0 HAS_AXI_LITE 1" + } + }, + "interface_ports": { + "s_axi_reg": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "memory_map_ref": "s_axi_reg" + } + }, + "addressing": { + "memory_maps": { + "s_axi_reg": { + "address_blocks": { + "Reg": { + "base_address": "0", + "range": "64K", + "width": "16", + "usage": "register" + } + } + } + } + } + }, + "inv_decouple_status": { + "vlnv": "xilinx.com:ip:util_vector_logic:2.0", + "xci_name": "shell_inv_decouple_status_0", + "xci_path": "ip/shell_inv_decouple_status_0/shell_inv_decouple_status_0.xci", + "inst_hier_path": "inv_decouple_status", + "parameters": { + "C_OPERATION": { + "value": "not" + }, + "C_SIZE": { + "value": "1" + } + } + }, + "shell_resetn": { + "vlnv": "xilinx.com:ip:proc_sys_reset:5.0", + "xci_name": "shell_shell_resetn_0", + "xci_path": "ip/shell_shell_resetn_0/shell_shell_resetn_0.xci", + "inst_hier_path": "shell_resetn" + } + }, + "interface_nets": { + "S00_AXI_1": { + "interface_ports": [ + "axi_interconnect_dma/S00_AXI", + "xdma/M_AXI" + ] + }, + "axi_interconnect_dma_M00_AXI": { + "interface_ports": [ + "axi_interconnect_dma/M00_AXI", + "hbicap/S_AXI" + ] + }, + "axi_interconnect_dma_M01_AXI": { + "interface_ports": [ + "axi_interconnect_dma/M01_AXI", + "dma_firewall/S_AXI" + ] + }, + "bscan": { + "interface_ports": [ + "bscan", + "debug_bridge/m0_bscan" + ] + }, + "cms_satellite_uart": { + "interface_ports": [ + "satellite_uart", + "cms/satellite_uart" + ] + }, + "ctrl_firewall_M_AXI": { + "interface_ports": [ + "shell_axil_ctrl", + "ctrl_firewall/M_AXI" + ] + }, + "dma_firewall_M_AXI": { + "interface_ports": [ + "shell_axi_dma", + "dma_firewall/M_AXI" + ] + }, + "mgmt_ram_BRAM_PORTA": { + "interface_ports": [ + "mgmt_ram_bram/BRAM_PORTA", + "mgmt_ram/BRAM_PORTA" + ] + }, + "pcie_refclk": { + "interface_ports": [ + "pcie_refclk", + "pcie_refclk_buf/CLK_IN_D" + ] + }, + "smartconnect_ctrl_M00_AXI": { + "interface_ports": [ + "cms/s_axi_ctrl", + "smartconnect_ctrl/M00_AXI" + ] + }, + "smartconnect_ctrl_M01_AXI": { + "interface_ports": [ + "smartconnect_ctrl/M01_AXI", + "qspi/AXI_LITE" + ] + }, + "smartconnect_ctrl_M02_AXI": { + "interface_ports": [ + "smartconnect_ctrl/M02_AXI", + "hbicap/S_AXI_CTRL" + ] + }, + "smartconnect_ctrl_M03_AXI": { + "interface_ports": [ + "mgmt_ram/S_AXI", + "smartconnect_ctrl/M03_AXI" + ] + }, + "smartconnect_ctrl_M04_AXI": { + "interface_ports": [ + "ctrl_firewall/S_AXI_CTL", + "smartconnect_ctrl/M04_AXI" + ] + }, + "smartconnect_ctrl_M05_AXI": { + "interface_ports": [ + "dma_firewall/S_AXI_CTL", + "smartconnect_ctrl/M05_AXI" + ] + }, + "smartconnect_ctrl_M06_AXI": { + "interface_ports": [ + "dfx_decoupler/s_axi_reg", + "smartconnect_ctrl/M06_AXI" + ] + }, + "smartconnect_ctrl_M07_AXI": { + "interface_ports": [ + "smartconnect_ctrl/M07_AXI", + "ctrl_firewall/S_AXI" + ] + }, + "xdma_M_AXI_LITE": { + "interface_ports": [ + "smartconnect_ctrl/S00_AXI", + "xdma/M_AXI_LITE" + ] + }, + "xdma_pcie_cfg_ext": { + "interface_ports": [ + "debug_bridge/pcie3_cfg_ext", + "xdma/pcie_cfg_ext" + ] + }, + "xdma_pcie_mgt": { + "interface_ports": [ + "pcie_mgt", + "xdma/pcie_mgt" + ] + } + }, + "nets": { + "dfx_decoupler_decouple_status": { + "ports": [ + "dfx_decoupler/decouple_status", + "inv_decouple_status/Op1" + ] + }, + "icap_clk": { + "ports": [ + "mgmt_clk_wiz/icap_clk", + "hbicap/icap_clk" + ] + }, + "inv_decouple_status_Res": { + "ports": [ + "inv_decouple_status/Res", + "shell_resetn/ext_reset_in" + ] + }, + "mgmt_clk_wiz_spi_clk": { + "ports": [ + "mgmt_clk_wiz/spi_clk", + "qspi/ext_spi_clk" + ] + }, + "pcie_refclk_buf_IBUF_DS_ODIV2": { + "ports": [ + "pcie_refclk_buf/IBUF_DS_ODIV2", + "xdma/sys_clk" + ] + }, + "pcie_refclk_buf_IBUF_OUT": { + "ports": [ + "pcie_refclk_buf/IBUF_OUT", + "xdma/sys_clk_gt" + ] + }, + "pcie_rstn": { + "ports": [ + "pcie_rstn", + "xdma/sys_rst_n" + ] + }, + "qspi_eos": { + "ports": [ + "qspi/eos", + "hbicap/eos_in" + ] + }, + "satellite_gpio": { + "ports": [ + "satellite_gpio", + "cms/satellite_gpio" + ] + }, + "shell_resetn_peripheral_aresetn": { + "ports": [ + "shell_resetn/peripheral_aresetn", + "shell_rstn" + ] + }, + "xdma_axi_aclk": { + "ports": [ + "xdma/axi_aclk", + "debug_bridge/clk", + "mgmt_clk_wiz/clk_in1", + "hbicap/s_axi_aclk", + "hbicap/s_axi_mm_aclk", + "qspi/s_axi_aclk", + "axi_interconnect_dma/ACLK", + "axi_interconnect_dma/S00_ACLK", + "axi_interconnect_dma/M00_ACLK", + "axi_interconnect_dma/M01_ACLK", + "smartconnect_ctrl/aclk", + "cms/aclk_ctrl", + "mgmt_ram/s_axi_aclk", + "ctrl_firewall/aclk", + "dma_firewall/aclk", + "dfx_decoupler/aclk", + "shell_resetn/slowest_sync_clk", + "shell_axi_clk" + ] + }, + "xdma_axi_aresetn": { + "ports": [ + "xdma/axi_aresetn", + "mgmt_clk_wiz/resetn", + "hbicap/s_axi_aresetn", + "hbicap/s_axi_mm_aresetn", + "qspi/s_axi_aresetn", + "axi_interconnect_dma/M01_ARESETN", + "axi_interconnect_dma/M00_ARESETN", + "axi_interconnect_dma/S00_ARESETN", + "axi_interconnect_dma/ARESETN", + "smartconnect_ctrl/aresetn", + "cms/aresetn_ctrl", + "mgmt_ram/s_axi_aresetn", + "ctrl_firewall/aresetn", + "dma_firewall/aresetn", + "dfx_decoupler/s_axi_reg_aresetn" + ] + } + }, + "addressing": { + "/": { + "memory_maps": { + "shell_axi_dma": { + "address_blocks": { + "Reg": { + "base_address": "0", + "range": "64K", + "width": "16", + "usage": "register" + } + } + }, + "shell_axil_ctrl": { + "address_blocks": { + "Reg": { + "base_address": "0", + "range": "64K", + "width": "16", + "usage": "register" + } + } + } + } + }, + "/xdma": { + "address_spaces": { + "M_AXI": { + "segments": { + "SEG_hbicap_Mem0": { + "address_block": "/hbicap/S_AXI/Mem0", + "offset": "0x1000000000000000", + "range": "1G", + "offset_base_param": "C_S_AXI_BASEADDR", + "offset_high_param": "C_S_AXI_HIGHADDR" + }, + "SEG_shell_axi_dma_Reg": { + "address_block": "/shell_axi_dma/Reg", + "offset": "0x0000000000000000", + "range": "256T" + } + } + }, + "M_AXI_LITE": { + "segments": { + "SEG_cms_Mem": { + "address_block": "/cms/s_axi_ctrl/Mem", + "offset": "0x04000000", + "range": "256K" + }, + "SEG_ctrl_firewall_Control": { + "address_block": "/ctrl_firewall/S_AXI_CTL/Control", + "offset": "0x04070000", + "range": "64K" + }, + "SEG_dfx_decoupler_Reg": { + "address_block": "/dfx_decoupler/s_axi_reg/Reg", + "offset": "0x04090000", + "range": "64K" + }, + "SEG_dma_firewall_Control": { + "address_block": "/dma_firewall/S_AXI_CTL/Control", + "offset": "0x04080000", + "range": "64K" + }, + "SEG_hbicap_Reg0": { + "address_block": "/hbicap/S_AXI_CTRL/Reg0", + "offset": "0x04050000", + "range": "64K", + "offset_base_param": "C_S_AXI_CTRL_BASEADDR", + "offset_high_param": "C_S_AXI_CTRL_HIGHADDR" + }, + "SEG_mgmt_ram_Mem0": { + "address_block": "/mgmt_ram/S_AXI/Mem0", + "offset": "0x04060000", + "range": "8K" + }, + "SEG_qspi_Reg": { + "address_block": "/qspi/AXI_LITE/Reg", + "offset": "0x04040000", + "range": "64K", + "offset_high_param": "C_HIGHADDR" + }, + "SEG_shell_axil_ctrl_Reg": { + "address_block": "/shell_axil_ctrl/Reg", + "offset": "0x00000000", + "range": "64M" + } + } + } + } + } + } + } +} \ No newline at end of file diff --git a/hw/shells/xilinx_u250/xdma_gen3x8/top.v b/hw/shells/xilinx_u250/xdma_gen3x8/top.v new file mode 100644 index 0000000..983fb7c --- /dev/null +++ b/hw/shells/xilinx_u250/xdma_gen3x8/top.v @@ -0,0 +1,242 @@ +module top ( + // -- PCIE -------------------------------------------------------------------------------------------------------- + input pcie_refclk_clk_n, + input pcie_refclk_clk_p, + input pcie_rstn, + input [7:0] pcie_mgt_rxn, + input [7:0] pcie_mgt_rxp, + output [7:0] pcie_mgt_txn, + output [7:0] pcie_mgt_txp, + // ---------------------------------------------------------------------------------------------------------------- + // -- SATELLITE CONTROLLER ---------------------------------------------------------------------------------------- + input [3:0] satellite_gpio, + input satellite_uart_rxd, + output satellite_uart_txd + // ---------------------------------------------------------------------------------------------------------------- +); +wire shell_axi_clk; +wire [63:0]shell_axi_dma_araddr; +wire [1:0]shell_axi_dma_arburst; +wire [3:0]shell_axi_dma_arcache; +wire [7:0]shell_axi_dma_arlen; +wire [0:0]shell_axi_dma_arlock; +wire [2:0]shell_axi_dma_arprot; +wire [3:0]shell_axi_dma_arqos; +wire shell_axi_dma_arready; +wire [2:0]shell_axi_dma_arsize; +wire shell_axi_dma_arvalid; +wire [63:0]shell_axi_dma_awaddr; +wire [1:0]shell_axi_dma_awburst; +wire [3:0]shell_axi_dma_awcache; +wire [7:0]shell_axi_dma_awlen; +wire [0:0]shell_axi_dma_awlock; +wire [2:0]shell_axi_dma_awprot; +wire [3:0]shell_axi_dma_awqos; +wire shell_axi_dma_awready; +wire [2:0]shell_axi_dma_awsize; +wire shell_axi_dma_awvalid; +wire shell_axi_dma_bready; +wire [1:0]shell_axi_dma_bresp; +wire shell_axi_dma_bvalid; +wire [255:0]shell_axi_dma_rdata; +wire shell_axi_dma_rlast; +wire shell_axi_dma_rready; +wire [1:0]shell_axi_dma_rresp; +wire shell_axi_dma_rvalid; +wire [255:0]shell_axi_dma_wdata; +wire shell_axi_dma_wlast; +wire shell_axi_dma_wready; +wire [31:0]shell_axi_dma_wstrb; +wire shell_axi_dma_wvalid; +wire [31:0]shell_axil_ctrl_araddr; +wire [2:0]shell_axil_ctrl_arprot; +wire shell_axil_ctrl_arready; +wire shell_axil_ctrl_arvalid; +wire [31:0]shell_axil_ctrl_awaddr; +wire [2:0]shell_axil_ctrl_awprot; +wire shell_axil_ctrl_awready; +wire shell_axil_ctrl_awvalid; +wire shell_axil_ctrl_bready; +wire [1:0]shell_axil_ctrl_bresp; +wire shell_axil_ctrl_bvalid; +wire [31:0]shell_axil_ctrl_rdata; +wire shell_axil_ctrl_rready; +wire [1:0]shell_axil_ctrl_rresp; +wire shell_axil_ctrl_rvalid; +wire [31:0]shell_axil_ctrl_wdata; +wire shell_axil_ctrl_wready; +wire [3:0]shell_axil_ctrl_wstrb; +wire shell_axil_ctrl_wvalid; +wire [0:0]shell_rstn; + +wire bscan_bscanid_en; +wire bscan_capture; +wire bscan_drck; +wire bscan_reset; +wire bscan_runtest; +wire bscan_sel; +wire bscan_shift; +wire bscan_tck; +wire bscan_tdi; +wire bscan_tdo; +wire bscan_tms; +wire bscan_update; + +user user_partition ( + // -- BSCAN -- + .bscan_bscanid_en(bscan_bscanid_en), + .bscan_capture(bscan_capture), + .bscan_drck(bscan_drck), + .bscan_reset(bscan_reset), + .bscan_runtest(bscan_runtest), + .bscan_sel(bscan_sel), + .bscan_shift(bscan_shift), + .bscan_tck(bscan_tck), + .bscan_tdi(bscan_tdi), + .bscan_tdo(bscan_tdo), + .bscan_tms(bscan_tms), + .bscan_update(bscan_update), + // -- SHELL <> USER -- + .shell_axi_clk(shell_axi_clk), + .shell_rstn(shell_rstn), + // -- SHELL AXIL CTRL -- + .shell_axil_ctrl_araddr(shell_axil_ctrl_araddr), + .shell_axil_ctrl_arprot(shell_axil_ctrl_arprot), + .shell_axil_ctrl_arready(shell_axil_ctrl_arready), + .shell_axil_ctrl_arvalid(shell_axil_ctrl_arvalid), + .shell_axil_ctrl_awaddr(shell_axil_ctrl_awaddr), + .shell_axil_ctrl_awprot(shell_axil_ctrl_awprot), + .shell_axil_ctrl_awready(shell_axil_ctrl_awready), + .shell_axil_ctrl_awvalid(shell_axil_ctrl_awvalid), + .shell_axil_ctrl_bready(shell_axil_ctrl_bready), + .shell_axil_ctrl_bresp(shell_axil_ctrl_bresp), + .shell_axil_ctrl_bvalid(shell_axil_ctrl_bvalid), + .shell_axil_ctrl_rdata(shell_axil_ctrl_rdata), + .shell_axil_ctrl_rready(shell_axil_ctrl_rready), + .shell_axil_ctrl_rresp(shell_axil_ctrl_rresp), + .shell_axil_ctrl_rvalid(shell_axil_ctrl_rvalid), + .shell_axil_ctrl_wdata(shell_axil_ctrl_wdata), + .shell_axil_ctrl_wready(shell_axil_ctrl_wready), + .shell_axil_ctrl_wstrb(shell_axil_ctrl_wstrb), + .shell_axil_ctrl_wvalid(shell_axil_ctrl_wvalid), + // -- SHELL AXI DMA -- + .shell_axi_dma_araddr(shell_axi_dma_araddr), + .shell_axi_dma_arburst(shell_axi_dma_arburst), + .shell_axi_dma_arcache(shell_axi_dma_arcache), + .shell_axi_dma_arlen(shell_axi_dma_arlen), + .shell_axi_dma_arlock(shell_axi_dma_arlock), + .shell_axi_dma_arprot(shell_axi_dma_arprot), + .shell_axi_dma_arqos(shell_axi_dma_arqos), + .shell_axi_dma_arready(shell_axi_dma_arready), + .shell_axi_dma_arsize(shell_axi_dma_arsize), + .shell_axi_dma_arvalid(shell_axi_dma_arvalid), + .shell_axi_dma_awaddr(shell_axi_dma_awaddr), + .shell_axi_dma_awburst(shell_axi_dma_awburst), + .shell_axi_dma_awcache(shell_axi_dma_awcache), + .shell_axi_dma_awlen(shell_axi_dma_awlen), + .shell_axi_dma_awlock(shell_axi_dma_awlock), + .shell_axi_dma_awprot(shell_axi_dma_awprot), + .shell_axi_dma_awqos(shell_axi_dma_awqos), + .shell_axi_dma_awready(shell_axi_dma_awready), + .shell_axi_dma_awsize(shell_axi_dma_awsize), + .shell_axi_dma_awvalid(shell_axi_dma_awvalid), + .shell_axi_dma_bready(shell_axi_dma_bready), + .shell_axi_dma_bresp(shell_axi_dma_bresp), + .shell_axi_dma_bvalid(shell_axi_dma_bvalid), + .shell_axi_dma_rdata(shell_axi_dma_rdata), + .shell_axi_dma_rlast(shell_axi_dma_rlast), + .shell_axi_dma_rready(shell_axi_dma_rready), + .shell_axi_dma_rresp(shell_axi_dma_rresp), + .shell_axi_dma_rvalid(shell_axi_dma_rvalid), + .shell_axi_dma_wdata(shell_axi_dma_wdata), + .shell_axi_dma_wlast(shell_axi_dma_wlast), + .shell_axi_dma_wready(shell_axi_dma_wready), + .shell_axi_dma_wstrb(shell_axi_dma_wstrb), + .shell_axi_dma_wvalid(shell_axi_dma_wvalid) +); + +shell shell_partition ( + // -- BSCAN -- + .bscan_bscanid_en(bscan_bscanid_en), + .bscan_capture(bscan_capture), + .bscan_drck(bscan_drck), + .bscan_reset(bscan_reset), + .bscan_runtest(bscan_runtest), + .bscan_sel(bscan_sel), + .bscan_shift(bscan_shift), + .bscan_tck(bscan_tck), + .bscan_tdi(bscan_tdi), + .bscan_tdo(bscan_tdo), + .bscan_tms(bscan_tms), + .bscan_update(bscan_update), + // -- PCIE -- + .pcie_refclk_clk_n(pcie_refclk_clk_n), + .pcie_refclk_clk_p(pcie_refclk_clk_p), + .pcie_rstn(pcie_rstn), + .pcie_mgt_rxn(pcie_mgt_rxn), + .pcie_mgt_rxp(pcie_mgt_rxp), + .pcie_mgt_txn(pcie_mgt_txn), + .pcie_mgt_txp(pcie_mgt_txp), + // -- SATELLITE CONTROLLER -- + .satellite_gpio(satellite_gpio), + .satellite_uart_rxd(satellite_uart_rxd), + .satellite_uart_txd(satellite_uart_txd), + // -- SHELL <> USER -- + .shell_axi_clk(shell_axi_clk), + .shell_rstn(shell_rstn), + // -- SHELL AXIL CTRL -- + .shell_axil_ctrl_araddr(shell_axil_ctrl_araddr), + .shell_axil_ctrl_arprot(shell_axil_ctrl_arprot), + .shell_axil_ctrl_arready(shell_axil_ctrl_arready), + .shell_axil_ctrl_arvalid(shell_axil_ctrl_arvalid), + .shell_axil_ctrl_awaddr(shell_axil_ctrl_awaddr), + .shell_axil_ctrl_awprot(shell_axil_ctrl_awprot), + .shell_axil_ctrl_awready(shell_axil_ctrl_awready), + .shell_axil_ctrl_awvalid(shell_axil_ctrl_awvalid), + .shell_axil_ctrl_bready(shell_axil_ctrl_bready), + .shell_axil_ctrl_bresp(shell_axil_ctrl_bresp), + .shell_axil_ctrl_bvalid(shell_axil_ctrl_bvalid), + .shell_axil_ctrl_rdata(shell_axil_ctrl_rdata), + .shell_axil_ctrl_rready(shell_axil_ctrl_rready), + .shell_axil_ctrl_rresp(shell_axil_ctrl_rresp), + .shell_axil_ctrl_rvalid(shell_axil_ctrl_rvalid), + .shell_axil_ctrl_wdata(shell_axil_ctrl_wdata), + .shell_axil_ctrl_wready(shell_axil_ctrl_wready), + .shell_axil_ctrl_wstrb(shell_axil_ctrl_wstrb), + .shell_axil_ctrl_wvalid(shell_axil_ctrl_wvalid), + // -- SHELL AXI DMA -- + .shell_axi_dma_araddr(shell_axi_dma_araddr), + .shell_axi_dma_arburst(shell_axi_dma_arburst), + .shell_axi_dma_arcache(shell_axi_dma_arcache), + .shell_axi_dma_arlen(shell_axi_dma_arlen), + .shell_axi_dma_arlock(shell_axi_dma_arlock), + .shell_axi_dma_arprot(shell_axi_dma_arprot), + .shell_axi_dma_arqos(shell_axi_dma_arqos), + .shell_axi_dma_arready(shell_axi_dma_arready), + .shell_axi_dma_arsize(shell_axi_dma_arsize), + .shell_axi_dma_arvalid(shell_axi_dma_arvalid), + .shell_axi_dma_awaddr(shell_axi_dma_awaddr), + .shell_axi_dma_awburst(shell_axi_dma_awburst), + .shell_axi_dma_awcache(shell_axi_dma_awcache), + .shell_axi_dma_awlen(shell_axi_dma_awlen), + .shell_axi_dma_awlock(shell_axi_dma_awlock), + .shell_axi_dma_awprot(shell_axi_dma_awprot), + .shell_axi_dma_awqos(shell_axi_dma_awqos), + .shell_axi_dma_awready(shell_axi_dma_awready), + .shell_axi_dma_awsize(shell_axi_dma_awsize), + .shell_axi_dma_awvalid(shell_axi_dma_awvalid), + .shell_axi_dma_bready(shell_axi_dma_bready), + .shell_axi_dma_bresp(shell_axi_dma_bresp), + .shell_axi_dma_bvalid(shell_axi_dma_bvalid), + .shell_axi_dma_rdata(shell_axi_dma_rdata), + .shell_axi_dma_rlast(shell_axi_dma_rlast), + .shell_axi_dma_rready(shell_axi_dma_rready), + .shell_axi_dma_rresp(shell_axi_dma_rresp), + .shell_axi_dma_rvalid(shell_axi_dma_rvalid), + .shell_axi_dma_wdata(shell_axi_dma_wdata), + .shell_axi_dma_wlast(shell_axi_dma_wlast), + .shell_axi_dma_wready(shell_axi_dma_wready), + .shell_axi_dma_wstrb(shell_axi_dma_wstrb), + .shell_axi_dma_wvalid(shell_axi_dma_wvalid) +); +endmodule diff --git a/hw/shells/xilinx_u250/xdma_gen3x8/user.bd b/hw/shells/xilinx_u250/xdma_gen3x8/user.bd new file mode 100644 index 0000000..ae04381 --- /dev/null +++ b/hw/shells/xilinx_u250/xdma_gen3x8/user.bd @@ -0,0 +1,933 @@ +{ + "design": { + "design_info": { + "boundary_crc": "0x9F0EE1D921DEB20C", + "device": "xcu250-figd2104-2-e", + "name": "user", + "rev_ctrl_bd_flag": "RevCtrlBdOff", + "synth_flow_mode": "None", + "tool_version": "2022.2", + "validated": "true" + }, + "design_tree": { + "debug_bridge": "", + "dummy_ctrl_target": "", + "smartconnect_ctrl": "", + "dummy_ctrl_target_bram": "", + "dummy_dma_target": "", + "dummy_dma_target_bram": "", + "smartconnect_dma": "" + }, + "interface_ports": { + "bscan": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:bscan:1.0", + "vlnv": "xilinx.com:interface:bscan_rtl:1.0", + "port_maps": { + "BSCANID_EN": { + "physical_name": "bscan_bscanid_en", + "direction": "I" + }, + "CAPTURE": { + "physical_name": "bscan_capture", + "direction": "I" + }, + "DRCK": { + "physical_name": "bscan_drck", + "direction": "I" + }, + "RESET": { + "physical_name": "bscan_reset", + "direction": "I" + }, + "RUNTEST": { + "physical_name": "bscan_runtest", + "direction": "I" + }, + "SEL": { + "physical_name": "bscan_sel", + "direction": "I" + }, + "SHIFT": { + "physical_name": "bscan_shift", + "direction": "I" + }, + "TCK": { + "physical_name": "bscan_tck", + "direction": "I" + }, + "TDI": { + "physical_name": "bscan_tdi", + "direction": "I" + }, + "TDO": { + "physical_name": "bscan_tdo", + "direction": "O" + }, + "TMS": { + "physical_name": "bscan_tms", + "direction": "I" + }, + "UPDATE": { + "physical_name": "bscan_update", + "direction": "I" + } + } + }, + "shell_axil_ctrl": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "parameters": { + "ADDR_WIDTH": { + "value": "32" + }, + "ARUSER_WIDTH": { + "value": "0" + }, + "AWUSER_WIDTH": { + "value": "0" + }, + "BUSER_WIDTH": { + "value": "0" + }, + "CLK_DOMAIN": { + "value": "user_shell_axi_clk", + "value_src": "default" + }, + "DATA_WIDTH": { + "value": "32" + }, + "FREQ_HZ": { + "value": "250000000" + }, + "HAS_BRESP": { + "value": "1" + }, + "HAS_BURST": { + "value": "0" + }, + "HAS_CACHE": { + "value": "0" + }, + "HAS_LOCK": { + "value": "0" + }, + "HAS_PROT": { + "value": "1" + }, + "HAS_QOS": { + "value": "0" + }, + "HAS_REGION": { + "value": "0" + }, + "HAS_RRESP": { + "value": "1" + }, + "HAS_WSTRB": { + "value": "1" + }, + "ID_WIDTH": { + "value": "0" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "MAX_BURST_LENGTH": { + "value": "1" + }, + "NUM_READ_OUTSTANDING": { + "value": "1" + }, + "NUM_READ_THREADS": { + "value": "1" + }, + "NUM_WRITE_OUTSTANDING": { + "value": "1" + }, + "NUM_WRITE_THREADS": { + "value": "1" + }, + "PHASE": { + "value": "0.0", + "value_src": "default" + }, + "PROTOCOL": { + "value": "AXI4LITE" + }, + "READ_WRITE_MODE": { + "value": "READ_WRITE" + }, + "RUSER_BITS_PER_BYTE": { + "value": "0" + }, + "RUSER_WIDTH": { + "value": "0" + }, + "SUPPORTS_NARROW_BURST": { + "value": "0" + }, + "WUSER_BITS_PER_BYTE": { + "value": "0" + }, + "WUSER_WIDTH": { + "value": "0" + }, + "master_id": { + "value": "1" + } + }, + "address_space_ref": "shell_axil_ctrl", + "base_address": { + "minimum": "0x00000000", + "maximum": "0xFFFFFFFF", + "width": "32" + }, + "port_maps": { + "ARADDR": { + "physical_name": "shell_axil_ctrl_araddr", + "direction": "I", + "left": "31", + "right": "0" + }, + "ARPROT": { + "physical_name": "shell_axil_ctrl_arprot", + "direction": "I", + "left": "2", + "right": "0" + }, + "ARREADY": { + "physical_name": "shell_axil_ctrl_arready", + "direction": "O" + }, + "ARVALID": { + "physical_name": "shell_axil_ctrl_arvalid", + "direction": "I" + }, + "AWADDR": { + "physical_name": "shell_axil_ctrl_awaddr", + "direction": "I", + "left": "31", + "right": "0" + }, + "AWPROT": { + "physical_name": "shell_axil_ctrl_awprot", + "direction": "I", + "left": "2", + "right": "0" + }, + "AWREADY": { + "physical_name": "shell_axil_ctrl_awready", + "direction": "O" + }, + "AWVALID": { + "physical_name": "shell_axil_ctrl_awvalid", + "direction": "I" + }, + "BREADY": { + "physical_name": "shell_axil_ctrl_bready", + "direction": "I" + }, + "BRESP": { + "physical_name": "shell_axil_ctrl_bresp", + "direction": "O", + "left": "1", + "right": "0" + }, + "BVALID": { + "physical_name": "shell_axil_ctrl_bvalid", + "direction": "O" + }, + "RDATA": { + "physical_name": "shell_axil_ctrl_rdata", + "direction": "O", + "left": "31", + "right": "0" + }, + "RREADY": { + "physical_name": "shell_axil_ctrl_rready", + "direction": "I" + }, + "RRESP": { + "physical_name": "shell_axil_ctrl_rresp", + "direction": "O", + "left": "1", + "right": "0" + }, + "RVALID": { + "physical_name": "shell_axil_ctrl_rvalid", + "direction": "O" + }, + "WDATA": { + "physical_name": "shell_axil_ctrl_wdata", + "direction": "I", + "left": "31", + "right": "0" + }, + "WREADY": { + "physical_name": "shell_axil_ctrl_wready", + "direction": "O" + }, + "WSTRB": { + "physical_name": "shell_axil_ctrl_wstrb", + "direction": "I", + "left": "3", + "right": "0" + }, + "WVALID": { + "physical_name": "shell_axil_ctrl_wvalid", + "direction": "I" + } + } + }, + "shell_axi_dma": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "parameters": { + "ADDR_WIDTH": { + "value": "64" + }, + "ARUSER_WIDTH": { + "value": "0" + }, + "AWUSER_WIDTH": { + "value": "0" + }, + "BUSER_WIDTH": { + "value": "0" + }, + "CLK_DOMAIN": { + "value": "user_shell_axi_clk", + "value_src": "default" + }, + "DATA_WIDTH": { + "value": "256" + }, + "FREQ_HZ": { + "value": "250000000" + }, + "HAS_BRESP": { + "value": "1" + }, + "HAS_BURST": { + "value": "1" + }, + "HAS_CACHE": { + "value": "1" + }, + "HAS_LOCK": { + "value": "1" + }, + "HAS_PROT": { + "value": "1" + }, + "HAS_QOS": { + "value": "1" + }, + "HAS_REGION": { + "value": "0" + }, + "HAS_RRESP": { + "value": "1" + }, + "HAS_WSTRB": { + "value": "1" + }, + "ID_WIDTH": { + "value": "4" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "MAX_BURST_LENGTH": { + "value": "256" + }, + "NUM_READ_OUTSTANDING": { + "value": "32" + }, + "NUM_READ_THREADS": { + "value": "1" + }, + "NUM_WRITE_OUTSTANDING": { + "value": "16" + }, + "NUM_WRITE_THREADS": { + "value": "1" + }, + "PHASE": { + "value": "0.0", + "value_src": "default" + }, + "PROTOCOL": { + "value": "AXI4" + }, + "READ_WRITE_MODE": { + "value": "READ_WRITE" + }, + "RUSER_BITS_PER_BYTE": { + "value": "0" + }, + "RUSER_WIDTH": { + "value": "0" + }, + "SUPPORTS_NARROW_BURST": { + "value": "0" + }, + "WUSER_BITS_PER_BYTE": { + "value": "0" + }, + "WUSER_WIDTH": { + "value": "0" + }, + "master_id": { + "value": "1" + } + }, + "address_space_ref": "shell_axi_dma", + "base_address": { + "minimum": "0x00000000", + "maximum": "0xFFFFFFFFFFFFFFFF", + "width": "64" + }, + "port_maps": { + "AWADDR": { + "physical_name": "shell_axi_dma_awaddr", + "direction": "I", + "left": "63", + "right": "0" + }, + "AWLEN": { + "physical_name": "shell_axi_dma_awlen", + "direction": "I", + "left": "7", + "right": "0" + }, + "AWSIZE": { + "physical_name": "shell_axi_dma_awsize", + "direction": "I", + "left": "2", + "right": "0" + }, + "AWBURST": { + "physical_name": "shell_axi_dma_awburst", + "direction": "I", + "left": "1", + "right": "0" + }, + "AWLOCK": { + "physical_name": "shell_axi_dma_awlock", + "direction": "I", + "left": "0", + "right": "0" + }, + "AWCACHE": { + "physical_name": "shell_axi_dma_awcache", + "direction": "I", + "left": "3", + "right": "0" + }, + "AWPROT": { + "physical_name": "shell_axi_dma_awprot", + "direction": "I", + "left": "2", + "right": "0" + }, + "AWVALID": { + "physical_name": "shell_axi_dma_awvalid", + "direction": "I" + }, + "AWREADY": { + "physical_name": "shell_axi_dma_awready", + "direction": "O" + }, + "WDATA": { + "physical_name": "shell_axi_dma_wdata", + "direction": "I", + "left": "255", + "right": "0" + }, + "WSTRB": { + "physical_name": "shell_axi_dma_wstrb", + "direction": "I", + "left": "31", + "right": "0" + }, + "WLAST": { + "physical_name": "shell_axi_dma_wlast", + "direction": "I" + }, + "WVALID": { + "physical_name": "shell_axi_dma_wvalid", + "direction": "I" + }, + "WREADY": { + "physical_name": "shell_axi_dma_wready", + "direction": "O" + }, + "BRESP": { + "physical_name": "shell_axi_dma_bresp", + "direction": "O", + "left": "1", + "right": "0" + }, + "BVALID": { + "physical_name": "shell_axi_dma_bvalid", + "direction": "O" + }, + "BREADY": { + "physical_name": "shell_axi_dma_bready", + "direction": "I" + }, + "ARADDR": { + "physical_name": "shell_axi_dma_araddr", + "direction": "I", + "left": "63", + "right": "0" + }, + "ARLEN": { + "physical_name": "shell_axi_dma_arlen", + "direction": "I", + "left": "7", + "right": "0" + }, + "ARSIZE": { + "physical_name": "shell_axi_dma_arsize", + "direction": "I", + "left": "2", + "right": "0" + }, + "ARBURST": { + "physical_name": "shell_axi_dma_arburst", + "direction": "I", + "left": "1", + "right": "0" + }, + "ARLOCK": { + "physical_name": "shell_axi_dma_arlock", + "direction": "I", + "left": "0", + "right": "0" + }, + "ARCACHE": { + "physical_name": "shell_axi_dma_arcache", + "direction": "I", + "left": "3", + "right": "0" + }, + "ARPROT": { + "physical_name": "shell_axi_dma_arprot", + "direction": "I", + "left": "2", + "right": "0" + }, + "ARVALID": { + "physical_name": "shell_axi_dma_arvalid", + "direction": "I" + }, + "ARREADY": { + "physical_name": "shell_axi_dma_arready", + "direction": "O" + }, + "RDATA": { + "physical_name": "shell_axi_dma_rdata", + "direction": "O", + "left": "255", + "right": "0" + }, + "RRESP": { + "physical_name": "shell_axi_dma_rresp", + "direction": "O", + "left": "1", + "right": "0" + }, + "RLAST": { + "physical_name": "shell_axi_dma_rlast", + "direction": "O" + }, + "RVALID": { + "physical_name": "shell_axi_dma_rvalid", + "direction": "O" + }, + "RREADY": { + "physical_name": "shell_axi_dma_rready", + "direction": "I" + }, + "ARID": { + "physical_name": "shell_axi_dma_arid", + "direction": "I", + "left": "3", + "right": "0" + }, + "AWID": { + "physical_name": "shell_axi_dma_awid", + "direction": "I", + "left": "3", + "right": "0" + }, + "BID": { + "physical_name": "shell_axi_dma_bid", + "direction": "O", + "left": "3", + "right": "0" + }, + "RID": { + "physical_name": "shell_axi_dma_rid", + "direction": "O", + "left": "3", + "right": "0" + }, + "ARQOS": { + "physical_name": "shell_axi_dma_arqos", + "direction": "I", + "left": "3", + "right": "0" + }, + "AWQOS": { + "physical_name": "shell_axi_dma_awqos", + "direction": "I", + "left": "3", + "right": "0" + } + } + } + }, + "ports": { + "shell_axi_clk": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "shell_axil_ctrl:shell_axi_dma" + }, + "ASSOCIATED_RESET": { + "value": "shell_rstn" + }, + "CLK_DOMAIN": { + "value": "user_shell_axi_clk", + "value_src": "default" + }, + "FREQ_HZ": { + "value": "250000000" + }, + "FREQ_TOLERANCE_HZ": { + "value": "0", + "value_src": "default" + }, + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "PHASE": { + "value": "0.0", + "value_src": "default" + } + } + }, + "shell_rstn": { + "type": "rst", + "direction": "I", + "parameters": { + "INSERT_VIP": { + "value": "0", + "value_src": "default" + }, + "POLARITY": { + "value": "ACTIVE_LOW", + "value_src": "default" + } + } + } + }, + "components": { + "debug_bridge": { + "vlnv": "xilinx.com:ip:debug_bridge:3.0", + "xci_name": "user_debug_bridge_0", + "xci_path": "ip/user_debug_bridge_0/user_debug_bridge_0.xci", + "inst_hier_path": "debug_bridge", + "parameters": { + "C_DESIGN_TYPE": { + "value": "1" + } + }, + "interface_ports": { + "S_BSCAN": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:bscan:1.0", + "vlnv": "xilinx.com:interface:bscan_rtl:1.0" + } + } + }, + "dummy_ctrl_target": { + "vlnv": "xilinx.com:ip:axi_bram_ctrl:4.1", + "xci_name": "user_dummy_ctrl_target_0", + "xci_path": "ip/user_dummy_ctrl_target_0/user_dummy_ctrl_target_0.xci", + "inst_hier_path": "dummy_ctrl_target", + "parameters": { + "PROTOCOL": { + "value": "AXI4LITE" + }, + "SINGLE_PORT_BRAM": { + "value": "1" + } + } + }, + "smartconnect_ctrl": { + "vlnv": "xilinx.com:ip:smartconnect:1.0", + "xci_name": "user_smartconnect_ctrl_0", + "xci_path": "ip/user_smartconnect_ctrl_0/user_smartconnect_ctrl_0.xci", + "inst_hier_path": "smartconnect_ctrl", + "parameters": { + "NUM_SI": { + "value": "1" + } + }, + "interface_ports": { + "S00_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "parameters": { + "NUM_READ_OUTSTANDING": { + "value": "1" + }, + "NUM_WRITE_OUTSTANDING": { + "value": "1" + } + }, + "bridges": [ + "M00_AXI" + ] + }, + "M00_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "parameters": { + "MAX_BURST_LENGTH": { + "value": "1" + }, + "NUM_READ_OUTSTANDING": { + "value": "1" + }, + "NUM_READ_THREADS": { + "value": "1" + }, + "NUM_WRITE_OUTSTANDING": { + "value": "1" + }, + "NUM_WRITE_THREADS": { + "value": "1" + }, + "RUSER_BITS_PER_BYTE": { + "value": "0" + }, + "SUPPORTS_NARROW_BURST": { + "value": "0" + }, + "WUSER_BITS_PER_BYTE": { + "value": "0" + } + } + } + } + }, + "dummy_ctrl_target_bram": { + "vlnv": "xilinx.com:ip:blk_mem_gen:8.4", + "xci_name": "user_dummy_ctrl_target_bram_0", + "xci_path": "ip/user_dummy_ctrl_target_bram_0/user_dummy_ctrl_target_bram_0.xci", + "inst_hier_path": "dummy_ctrl_target_bram" + }, + "dummy_dma_target": { + "vlnv": "xilinx.com:ip:axi_bram_ctrl:4.1", + "xci_name": "user_dummy_dma_target_0", + "xci_path": "ip/user_dummy_dma_target_0/user_dummy_dma_target_0.xci", + "inst_hier_path": "dummy_dma_target", + "parameters": { + "DATA_WIDTH": { + "value": "256" + }, + "SINGLE_PORT_BRAM": { + "value": "0" + } + } + }, + "dummy_dma_target_bram": { + "vlnv": "xilinx.com:ip:blk_mem_gen:8.4", + "xci_name": "user_dummy_dma_target_bram_0", + "xci_path": "ip/user_dummy_dma_target_bram_0/user_dummy_dma_target_bram_0.xci", + "inst_hier_path": "dummy_dma_target_bram", + "parameters": { + "Memory_Type": { + "value": "True_Dual_Port_RAM" + }, + "PRIM_type_to_Implement": { + "value": "URAM" + } + } + }, + "smartconnect_dma": { + "vlnv": "xilinx.com:ip:smartconnect:1.0", + "xci_name": "user_smartconnect_0_0", + "xci_path": "ip/user_smartconnect_0_0/user_smartconnect_0_0.xci", + "inst_hier_path": "smartconnect_dma", + "parameters": { + "NUM_SI": { + "value": "1" + } + }, + "interface_ports": { + "S00_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "parameters": { + "NUM_READ_OUTSTANDING": { + "value": "32" + }, + "NUM_WRITE_OUTSTANDING": { + "value": "16" + } + }, + "bridges": [ + "M00_AXI" + ] + }, + "M00_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "parameters": { + "MAX_BURST_LENGTH": { + "value": "256" + }, + "NUM_READ_OUTSTANDING": { + "value": "32" + }, + "NUM_READ_THREADS": { + "value": "1" + }, + "NUM_WRITE_OUTSTANDING": { + "value": "16" + }, + "NUM_WRITE_THREADS": { + "value": "1" + }, + "RUSER_BITS_PER_BYTE": { + "value": "0" + }, + "SUPPORTS_NARROW_BURST": { + "value": "0" + }, + "WUSER_BITS_PER_BYTE": { + "value": "0" + } + } + } + } + } + }, + "interface_nets": { + "S_BSCAN_0_1": { + "interface_ports": [ + "bscan", + "debug_bridge/S_BSCAN" + ] + }, + "dummy_ctrl_BRAM_PORTA": { + "interface_ports": [ + "dummy_ctrl_target_bram/BRAM_PORTA", + "dummy_ctrl_target/BRAM_PORTA" + ] + }, + "dummy_dma_target_BRAM_PORTA": { + "interface_ports": [ + "dummy_dma_target_bram/BRAM_PORTA", + "dummy_dma_target/BRAM_PORTA" + ] + }, + "dummy_dma_target_BRAM_PORTB": { + "interface_ports": [ + "dummy_dma_target_bram/BRAM_PORTB", + "dummy_dma_target/BRAM_PORTB" + ] + }, + "shell_axi_dma_1": { + "interface_ports": [ + "shell_axi_dma", + "smartconnect_dma/S00_AXI" + ] + }, + "shell_axil_ctrl_1": { + "interface_ports": [ + "shell_axil_ctrl", + "smartconnect_ctrl/S00_AXI" + ] + }, + "smartconnect_ctrl_M00_AXI": { + "interface_ports": [ + "smartconnect_ctrl/M00_AXI", + "dummy_ctrl_target/S_AXI" + ] + }, + "smartconnect_dma_M00_AXI": { + "interface_ports": [ + "smartconnect_dma/M00_AXI", + "dummy_dma_target/S_AXI" + ] + } + }, + "nets": { + "shell_axi_clk_1": { + "ports": [ + "shell_axi_clk", + "debug_bridge/clk", + "dummy_ctrl_target/s_axi_aclk", + "smartconnect_ctrl/aclk", + "dummy_dma_target/s_axi_aclk", + "smartconnect_dma/aclk" + ] + }, + "shell_rstn_1": { + "ports": [ + "shell_rstn", + "dummy_ctrl_target/s_axi_aresetn", + "smartconnect_ctrl/aresetn", + "dummy_dma_target/s_axi_aresetn", + "smartconnect_dma/aresetn" + ] + } + }, + "addressing": { + "/": { + "address_spaces": { + "shell_axil_ctrl": { + "range": "4G", + "width": "32", + "segments": { + "SEG_dummy_ctrl_target_Mem0": { + "address_block": "/dummy_ctrl_target/S_AXI/Mem0", + "offset": "0x00000000", + "range": "8K" + } + } + }, + "shell_axi_dma": { + "range": "16E", + "width": "64", + "segments": { + "SEG_dummy_dma_target_Mem0": { + "address_block": "/dummy_dma_target/S_AXI/Mem0", + "offset": "0x0000000000000000", + "range": "256T" + } + } + } + } + } + } + } +} \ No newline at end of file