From 2353040f51ff31fabdefd04251ad0413fe69632b Mon Sep 17 00:00:00 2001 From: Quarky93 Date: Thu, 24 Nov 2022 12:57:37 +1100 Subject: [PATCH] Initial U55C support --- Makefile | 23 ++ hw/shells/xilinx_u55c/README.md | 1 - hw/shells/xilinx_u55c/floorplan.xdc | 0 hw/shells/xilinx_u55c/shell_bd.tcl | 0 hw/shells/xilinx_u55c/xdma_gen3x8/README.md | 1 + hw/shells/xilinx_u55c/xdma_gen3x8/build.tcl | 37 ++ hw/shells/xilinx_u55c/xdma_gen3x8/edit.tcl | 17 + .../xilinx_u55c/xdma_gen3x8/floorplan.xdc | 13 + .../xilinx_u55c/{ => xdma_gen3x8}/io.xdc | 31 +- hw/shells/xilinx_u55c/xdma_gen3x8/misc.xdc | 12 + hw/shells/xilinx_u55c/xdma_gen3x8/shell.tcl | 384 ++++++++++++++++++ hw/shells/xilinx_u55c/xdma_gen3x8/top.v | 222 ++++++++++ hw/shells/xilinx_u55c/xdma_gen3x8/user.tcl | 313 ++++++++++++++ 13 files changed, 1031 insertions(+), 23 deletions(-) delete mode 100644 hw/shells/xilinx_u55c/README.md delete mode 100644 hw/shells/xilinx_u55c/floorplan.xdc delete mode 100644 hw/shells/xilinx_u55c/shell_bd.tcl create mode 100644 hw/shells/xilinx_u55c/xdma_gen3x8/README.md create mode 100644 hw/shells/xilinx_u55c/xdma_gen3x8/build.tcl create mode 100644 hw/shells/xilinx_u55c/xdma_gen3x8/edit.tcl create mode 100644 hw/shells/xilinx_u55c/xdma_gen3x8/floorplan.xdc rename hw/shells/xilinx_u55c/{ => xdma_gen3x8}/io.xdc (75%) create mode 100644 hw/shells/xilinx_u55c/xdma_gen3x8/misc.xdc create mode 100644 hw/shells/xilinx_u55c/xdma_gen3x8/shell.tcl create mode 100644 hw/shells/xilinx_u55c/xdma_gen3x8/top.v create mode 100644 hw/shells/xilinx_u55c/xdma_gen3x8/user.tcl diff --git a/Makefile b/Makefile index cea5cac..9d8ef47 100644 --- a/Makefile +++ b/Makefile @@ -1,14 +1,37 @@ +PLATFORM=xilinx_u55n + +# -- U55C -- +xilinx_u55c_xdma_gen3x8: ./hw/shells/xilinx_u55c/xdma_gen3x8/* + mkdir -p ./build/xilinx_u55c_xdma_gen3x8/ + cd ./build/xilinx_u55c_xdma_gen3x8/; \ + vivado -mode batch -source ../../hw/shells/xilinx_u55c/xdma_gen3x8/build.tcl + +edit_xilinx_u55c_xdma_gen3x8_shell: + rm -rf ./build/edit_xilinx_u55c_xdma_gen3x8/ + mkdir -p ./build/edit_xilinx_u55c_xdma_gen3x8/ + cd ./build/edit_xilinx_u55c_xdma_gen3x8/; \ + vivado -mode batch -source ../../hw/shells/xilinx_u55c/xdma_gen3x8/edit.tcl -tclargs shell + +edit_xilinx_u55c_xdma_gen3x8_user: + rm -rf ./build/edit_xilinx_u55c_xdma_gen3x8/ + mkdir -p ./build/edit_xilinx_u55c_xdma_gen3x8/ + cd ./build/edit_xilinx_u55c_xdma_gen3x8/; \ + vivado -mode batch -source ../../hw/shells/xilinx_u55c/xdma_gen3x8/edit.tcl -tclargs user + +# -- U55N -- xilinx_u55n_xdma_gen3x8: ./hw/shells/xilinx_u55n/xdma_gen3x8/* mkdir -p ./build/xilinx_u55n_xdma_gen3x8/ cd ./build/xilinx_u55n_xdma_gen3x8/; \ vivado -mode batch -source ../../hw/shells/xilinx_u55n/xdma_gen3x8/build.tcl edit_xilinx_u55n_xdma_gen3x8_shell: + rm -rf ./build/edit_xilinx_u55n_xdma_gen3x8/ mkdir -p ./build/edit_xilinx_u55n_xdma_gen3x8/ cd ./build/edit_xilinx_u55n_xdma_gen3x8/; \ vivado -mode batch -source ../../hw/shells/xilinx_u55n/xdma_gen3x8/edit.tcl -tclargs shell edit_xilinx_u55n_xdma_gen3x8_user: + rm -rf ./build/edit_xilinx_u55n_xdma_gen3x8/ mkdir -p ./build/edit_xilinx_u55n_xdma_gen3x8/ cd ./build/edit_xilinx_u55n_xdma_gen3x8/; \ vivado -mode batch -source ../../hw/shells/xilinx_u55n/xdma_gen3x8/edit.tcl -tclargs user diff --git a/hw/shells/xilinx_u55c/README.md b/hw/shells/xilinx_u55c/README.md deleted file mode 100644 index f87f972..0000000 --- a/hw/shells/xilinx_u55c/README.md +++ /dev/null @@ -1 +0,0 @@ -# Xilinx Alveo U55C diff --git a/hw/shells/xilinx_u55c/floorplan.xdc b/hw/shells/xilinx_u55c/floorplan.xdc deleted file mode 100644 index e69de29..0000000 diff --git a/hw/shells/xilinx_u55c/shell_bd.tcl b/hw/shells/xilinx_u55c/shell_bd.tcl deleted file mode 100644 index e69de29..0000000 diff --git a/hw/shells/xilinx_u55c/xdma_gen3x8/README.md b/hw/shells/xilinx_u55c/xdma_gen3x8/README.md new file mode 100644 index 0000000..a341e93 --- /dev/null +++ b/hw/shells/xilinx_u55c/xdma_gen3x8/README.md @@ -0,0 +1 @@ +# Xilinx U55C XDMA diff --git a/hw/shells/xilinx_u55c/xdma_gen3x8/build.tcl b/hw/shells/xilinx_u55c/xdma_gen3x8/build.tcl new file mode 100644 index 0000000..74fcf65 --- /dev/null +++ b/hw/shells/xilinx_u55c/xdma_gen3x8/build.tcl @@ -0,0 +1,37 @@ +set script_path [file dirname [file normalize [info script]]] + +create_project -in_memory -part xcu55c-fsvh2892-2L-e +set_property source_mgmt_mode All [current_project] + +# -- [READ FILES] ------------------------------------------------------------- +source "${script_path}/user.tcl" +source "${script_path}/shell.tcl" +read_xdc "${script_path}/io.xdc" +read_xdc "${script_path}/misc.xdc" +read_xdc "${script_path}/floorplan.xdc" +read_verilog "${script_path}/top.v" +# ----------------------------------------------------------------------------- + +# -- [CONFIGURE USER BD] ------------------------------------------------------ +cr_bd_user {} +generate_target all [get_files user.bd] +# ----------------------------------------------------------------------------- + +# -- [CONFIGURE SHELL BD] ----------------------------------------------------- +cr_bd_shell {} +generate_target all [get_files shell.bd] +# ----------------------------------------------------------------------------- + +# -- [COMPILE] ---------------------------------------------------------------- +synth_design -top top +write_checkpoint -force ./post_synth_xilinx_u55n_xdma_gen3x8.dcp +opt_design -directive Explore +place_design -directive Auto_1 +phys_opt_design -directive ExploreWithAggressiveHoldFix +route_design -directive AggressiveExplore +phys_opt_design -directive ExploreWithAggressiveHoldFix +write_checkpoint ./post_route_xilinx_u55n_xdma_gen3x8.dcp +write_bitstream -bin_file -force ./warpshell_xilinx_u55n_xdma_gen3x8.bit +write_abstract_shell -cell user_partition -force ./abstract_warpshell_xilinx_u55n_xdma_gen3x8.dcp +write_cfgmem -force -format mcs -interface spix4 -size 128 -loadbit "up 0x01002000 warpshell_xilinx_u55n_xdma_gen3x8.bit" -file "warpshell_xilinx_u55n_xdma_gen3x8.mcs" +# ----------------------------------------------------------------------------- diff --git a/hw/shells/xilinx_u55c/xdma_gen3x8/edit.tcl b/hw/shells/xilinx_u55c/xdma_gen3x8/edit.tcl new file mode 100644 index 0000000..cb9d13a --- /dev/null +++ b/hw/shells/xilinx_u55c/xdma_gen3x8/edit.tcl @@ -0,0 +1,17 @@ +set bd [lindex $argv 0] +set script_path [file dirname [file normalize [info script]]] + +create_project -in_memory -part xcu55c-fsvh2892-2L-e +set_property source_mgmt_mode All [current_project] + +proc commit {} { + validate_bd_design + puts "Writing to: $::script_path/$::bd.tcl" + write_bd_tcl -bd_name $::bd -no_project_wrapper -make_local -force "$::script_path/$::bd.tcl" +} + +source "${script_path}/${bd}.tcl" + +start_gui + +cr_bd_${bd} {} diff --git a/hw/shells/xilinx_u55c/xdma_gen3x8/floorplan.xdc b/hw/shells/xilinx_u55c/xdma_gen3x8/floorplan.xdc new file mode 100644 index 0000000..754912e --- /dev/null +++ b/hw/shells/xilinx_u55c/xdma_gen3x8/floorplan.xdc @@ -0,0 +1,13 @@ +# create_pblock shell_partition +# resize_pblock shell_partition -add {CLOCKREGION_X7Y1:CLOCKREGION_X7Y5} +# add_cells_to_pblock shell_partition [get_cells shell_partition] +# set_property USER_SLR_ASSIGNMENT SLR0 [get_cells {shell_partition/ctrl_firewall shell_partition/dma_firewall}] + +# create_pblock user_partition +# resize_pblock user_partition -add {CLOCKREGION_X0Y4:CLOCKREGION_X6Y7} +# resize_pblock user_partition -add {CLOCKREGION_X7Y6:CLOCKREGION_X7Y7} +# resize_pblock user_partition -add {CLOCKREGION_X0Y0:CLOCKREGION_X6Y3} +# resize_pblock user_partition -add {CLOCKREGION_X7Y0:CLOCKREGION_X7Y0} +# resize_pblock user_partition -remove {IOB_X0Y103 IOB_X0Y98 IOB_X0Y84 IOB_X0Y93 IOB_X0Y94 IOB_X0Y79 IOB_X0Y78} +# add_cells_to_pblock user_partition [get_cells user_partition] +# set_property HD.RECONFIGURABLE TRUE [get_cells user_partition] diff --git a/hw/shells/xilinx_u55c/io.xdc b/hw/shells/xilinx_u55c/xdma_gen3x8/io.xdc similarity index 75% rename from hw/shells/xilinx_u55c/io.xdc rename to hw/shells/xilinx_u55c/xdma_gen3x8/io.xdc index fd299f8..2b2a7f7 100644 --- a/hw/shells/xilinx_u55c/io.xdc +++ b/hw/shells/xilinx_u55c/xdma_gen3x8/io.xdc @@ -1,20 +1,20 @@ # -- [Clocks] ------------------------------------------------------------------ -# pcie clock -create_clock -period 10.000 -name pcie_ref_clk [get_ports pcie_clk_clk_p] -# sys clock -create_clock -period 10.000 -name hbm_ref_clk [get_ports hbm_clk_clk_p] +# pcie refclock +create_clock -period 10.000 -name pcie_refclk [get_ports pcie_refclk_clk_p] +# hbm refclock +create_clock -period 10.000 -name sysclk_0 [get_ports sys_refclk_0_clk_p] # ------------------------------------------------------------------------------ # -- [Clock Pins] -------------------------------------------------------------- -set_property PACKAGE_PIN AR14 [get_ports pcie_clk_clk_n] -set_property PACKAGE_PIN AR15 [get_ports pcie_clk_clk_p] +set_property PACKAGE_PIN AR14 [get_ports pcie_refclk_clk_n] +set_property PACKAGE_PIN AR15 [get_ports pcie_refclk_clk_p] -set_property -dict {IOSTANDARD LVDS PACKAGE_PIN BK44} [get_ports hbm_clk_clk_p] -set_property -dict {IOSTANDARD LVDS PACKAGE_PIN BK43} [get_ports hbm_clk_clk_p] +set_property -dict {IOSTANDARD LVDS PACKAGE_PIN BK44} [get_ports sys_refclk_0_clk_n] +set_property -dict {IOSTANDARD LVDS PACKAGE_PIN BK43} [get_ports sys_refclk_0_clk_p] # ------------------------------------------------------------------------------ # -- [PCIE Pins] --------------------------------------------------------------- -set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN BF41} [get_ports pcie_clkreq] +set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN BF41} [get_ports pcie_rstn] set_property PACKAGE_PIN AU10 [get_ports { pcie_mgt_txn[7] }] set_property PACKAGE_PIN AU11 [get_ports { pcie_mgt_txp[7] }] @@ -58,16 +58,3 @@ set_property -dict { IOSTANDARD LVCMOS18 PACKAGE_PIN BH46 } [get_ports { satelli set_property -dict { IOSTANDARD LVCMOS18 PACKAGE_PIN BJ42 } [get_ports satellite_uart_rxd] set_property -dict { IOSTANDARD LVCMOS18 PACKAGE_PIN BH42 } [get_ports satellite_uart_txd] # ------------------------------------------------------------------------------ - -# -- [BITSTREAM] --------------------------------------------------------------- -set_property CONFIG_VOLTAGE 1.8 [current_design] -set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design] -set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] -set_property CONFIG_MODE SPIx4 [current_design] -set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] -set_property BITSTREAM.CONFIG.CONFIGRATE 63.8 [current_design] -set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design] -set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] -set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] -set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] -# ------------------------------------------------------------------------------ diff --git a/hw/shells/xilinx_u55c/xdma_gen3x8/misc.xdc b/hw/shells/xilinx_u55c/xdma_gen3x8/misc.xdc new file mode 100644 index 0000000..f995ab2 --- /dev/null +++ b/hw/shells/xilinx_u55c/xdma_gen3x8/misc.xdc @@ -0,0 +1,12 @@ +# -- [CONFIG] ----------------------------------------------------------------- +set_property CONFIG_VOLTAGE 1.8 [current_design] +set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design] +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +set_property CONFIG_MODE SPIx4 [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 63.8 [current_design] +set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design] +set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] +set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] +set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] +# ----------------------------------------------------------------------------- diff --git a/hw/shells/xilinx_u55c/xdma_gen3x8/shell.tcl b/hw/shells/xilinx_u55c/xdma_gen3x8/shell.tcl new file mode 100644 index 0000000..f5a89a4 --- /dev/null +++ b/hw/shells/xilinx_u55c/xdma_gen3x8/shell.tcl @@ -0,0 +1,384 @@ +# Proc to create BD shell +proc cr_bd_shell { parentCell } { + + # CHANGE DESIGN NAME HERE + set design_name shell + + common::send_gid_msg -ssname BD::TCL -id 2010 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + set bCheckIPsPassed 1 + ################################################################## + # CHECK IPs + ################################################################## + set bCheckIPs 1 + if { $bCheckIPs == 1 } { + set list_check_ips "\ + xilinx.com:ip:cms_subsystem:4.0\ + xilinx.com:ip:axi_firewall:1.2\ + xilinx.com:ip:debug_bridge:3.0\ + xilinx.com:ip:dfx_decoupler:1.0\ + xilinx.com:ip:axi_hbicap:1.0\ + xilinx.com:ip:util_vector_logic:2.0\ + xilinx.com:ip:clk_wiz:6.0\ + xilinx.com:ip:axi_bram_ctrl:4.1\ + xilinx.com:ip:blk_mem_gen:8.4\ + xilinx.com:ip:util_ds_buf:2.2\ + xilinx.com:ip:axi_quad_spi:3.2\ + xilinx.com:ip:proc_sys_reset:5.0\ + xilinx.com:ip:smartconnect:1.0\ + xilinx.com:ip:xdma:4.1\ + " + + set list_ips_missing "" + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + + } + + if { $bCheckIPsPassed != 1 } { + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 + } + + variable script_folder + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set pcie_mgt [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 pcie_mgt ] + + set pcie_refclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 pcie_refclk ] + + set satellite_uart [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 satellite_uart ] + + set shell_axi_dma [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 shell_axi_dma ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.HAS_QOS {1} \ + CONFIG.HAS_REGION {0} \ + CONFIG.NUM_READ_OUTSTANDING {32} \ + CONFIG.NUM_WRITE_OUTSTANDING {32} \ + CONFIG.PROTOCOL {AXI4} \ + ] $shell_axi_dma + + set shell_axil_ctrl [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 shell_axil_ctrl ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {32} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_REGION {0} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.PROTOCOL {AXI4LITE} \ + ] $shell_axil_ctrl + + set sys_refclk_0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_refclk_0 ] + + + # Create ports + set pcie_rstn [ create_bd_port -dir I -type rst pcie_rstn ] + set satellite_gpio [ create_bd_port -dir I -from 3 -to 0 -type intr satellite_gpio ] + set_property -dict [ list \ + CONFIG.PortWidth {4} \ + CONFIG.SENSITIVITY {EDGE_RISING} \ + ] $satellite_gpio + set shell_axi_clk [ create_bd_port -dir O -type clk shell_axi_clk ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {shell_axi_dma:shell_axil_ctrl} \ + CONFIG.ASSOCIATED_RESET {shell_rstn} \ + ] $shell_axi_clk + set shell_refclk_0 [ create_bd_port -dir O -from 0 -to 0 -type clk shell_refclk_0 ] + set shell_rstn [ create_bd_port -dir O -from 0 -to 0 -type rst shell_rstn ] + set user_hbm_cattrip [ create_bd_port -dir I -type intr user_hbm_cattrip ] + set user_hbm_temp_0 [ create_bd_port -dir I -from 6 -to 0 user_hbm_temp_0 ] + set user_hbm_temp_1 [ create_bd_port -dir I -from 6 -to 0 user_hbm_temp_1 ] + + # Create instance: cms, and set properties + set cms [ create_bd_cell -type ip -vlnv xilinx.com:ip:cms_subsystem:4.0 cms ] + + # Create instance: ctrl_firewall, and set properties + set ctrl_firewall [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_firewall:1.2 ctrl_firewall ] + set_property -dict [list \ + CONFIG.ADDR_WIDTH {32} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.ENABLE_PRESCALER {0} \ + CONFIG.ENABLE_PROTOCOL_CHECKS {1} \ + CONFIG.FIREWALL_MODE {MI_SIDE} \ + CONFIG.HAS_ARESETN {1} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_REGION {0} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.PROTOCOL {AXI4LITE} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.SUPPORTS_NARROW {0} \ + ] $ctrl_firewall + + + # Create instance: debug_bridge, and set properties + set debug_bridge [ create_bd_cell -type ip -vlnv xilinx.com:ip:debug_bridge:3.0 debug_bridge ] + set_property -dict [list \ + CONFIG.C_DEBUG_MODE {5} \ + CONFIG.C_DESIGN_TYPE {0} \ + ] $debug_bridge + + + # Create instance: dfx_decoupler, and set properties + set dfx_decoupler [ create_bd_cell -type ip -vlnv xilinx.com:ip:dfx_decoupler:1.0 dfx_decoupler ] + set_property -dict [list \ + CONFIG.ALL_PARAMS {HAS_AXI_LITE 1 INTF {hbm_cattrip {ID 0 VLNV xilinx.com:signal:interrupt_rtl:1.0 SIGNALS {INTERRUPT {PRESENT 1 WIDTH 1}}} hbm_temp_0 {ID 1 VLNV xilinx.com:signal:data_rtl:1.0 SIGNALS\ +{DATA {PRESENT 1 WIDTH 7}}} hbm_temp_1 {ID 2 VLNV xilinx.com:signal:data_rtl:1.0 SIGNALS {DATA {PRESENT 1 WIDTH 7}}}} HAS_SIGNAL_CONTROL 0 HAS_SIGNAL_STATUS 1 IPI_PROP_COUNT 0} \ + CONFIG.GUI_INTERFACE_NAME {hbm_cattrip} \ + CONFIG.GUI_SELECT_VLNV {xilinx.com:signal:interrupt_rtl:1.0} \ + ] $dfx_decoupler + + + # Create instance: dma_firewall, and set properties + set dma_firewall [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_firewall:1.2 dma_firewall ] + set_property -dict [list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.ENABLE_PRESCALER {0} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {1} \ + CONFIG.HAS_LOCK {1} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {1} \ + CONFIG.HAS_REGION {0} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {0} \ + CONFIG.NUM_READ_OUTSTANDING {32} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {32} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $dma_firewall + + + # Create instance: hbicap, and set properties + set hbicap [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_hbicap:1.0 hbicap ] + set_property -dict [list \ + CONFIG.C_ICAP_EXTERNAL {0} \ + CONFIG.C_INCLUDE_STARTUP {0} \ + CONFIG.C_READ_PATH {0} \ + CONFIG.C_WRITE_FIFO_DEPTH {1024} \ + ] $hbicap + + + # Create instance: inv_decouple_status, and set properties + set inv_decouple_status [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 inv_decouple_status ] + set_property -dict [list \ + CONFIG.C_OPERATION {not} \ + CONFIG.C_SIZE {1} \ + ] $inv_decouple_status + + + # Create instance: mgmt_clk_wiz, and set properties + set mgmt_clk_wiz [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 mgmt_clk_wiz ] + set_property -dict [list \ + CONFIG.AXI_DRP {false} \ + CONFIG.CLKOUT1_JITTER {102.484} \ + CONFIG.CLKOUT1_PHASE_ERROR {79.008} \ + CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {100} \ + CONFIG.CLKOUT2_JITTER {98.122} \ + CONFIG.CLKOUT2_PHASE_ERROR {79.008} \ + CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {125} \ + CONFIG.CLKOUT2_USED {true} \ + CONFIG.CLK_OUT1_PORT {spi_clk} \ + CONFIG.CLK_OUT2_PORT {icap_clk} \ + CONFIG.MMCM_CLKFBOUT_MULT_F {5.000} \ + CONFIG.MMCM_CLKOUT0_DIVIDE_F {12.500} \ + CONFIG.MMCM_CLKOUT1_DIVIDE {10} \ + CONFIG.MMCM_DIVCLK_DIVIDE {1} \ + CONFIG.NUM_OUT_CLKS {2} \ + CONFIG.PHASE_DUTY_CONFIG {false} \ + CONFIG.RESET_PORT {resetn} \ + CONFIG.RESET_TYPE {ACTIVE_LOW} \ + CONFIG.USE_DYN_RECONFIG {false} \ + ] $mgmt_clk_wiz + + + # Create instance: mgmt_ram, and set properties + set mgmt_ram [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 mgmt_ram ] + set_property -dict [list \ + CONFIG.PROTOCOL {AXI4LITE} \ + CONFIG.SINGLE_PORT_BRAM {1} \ + ] $mgmt_ram + + + # Create instance: mgmt_ram_bram, and set properties + set mgmt_ram_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 mgmt_ram_bram ] + + # Create instance: pcie_refclk_buf, and set properties + set pcie_refclk_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 pcie_refclk_buf ] + set_property CONFIG.C_BUF_TYPE {IBUFDSGTE} $pcie_refclk_buf + + + # Create instance: qspi, and set properties + set qspi [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 qspi ] + set_property -dict [list \ + CONFIG.C_FIFO_DEPTH {256} \ + CONFIG.C_SPI_MEMORY {2} \ + CONFIG.C_SPI_MODE {2} \ + CONFIG.C_USE_STARTUP {1} \ + CONFIG.C_USE_STARTUP_INT {1} \ + ] $qspi + + + # Create instance: shell_resetn, and set properties + set shell_resetn [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 shell_resetn ] + + # Create instance: smartconnect_ctrl, and set properties + set smartconnect_ctrl [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_ctrl ] + set_property -dict [list \ + CONFIG.NUM_MI {8} \ + CONFIG.NUM_SI {1} \ + ] $smartconnect_ctrl + + + # Create instance: smartconnect_dma, and set properties + set smartconnect_dma [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_dma ] + set_property -dict [list \ + CONFIG.NUM_MI {2} \ + CONFIG.NUM_SI {1} \ + ] $smartconnect_dma + + + # Create instance: sys_refclk_0_buf, and set properties + set sys_refclk_0_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 sys_refclk_0_buf ] + + # Create instance: xdma, and set properties + set xdma [ create_bd_cell -type ip -vlnv xilinx.com:ip:xdma:4.1 xdma ] + set_property -dict [list \ + CONFIG.axi_data_width {256_bit} \ + CONFIG.axilite_master_en {true} \ + CONFIG.axilite_master_size {128} \ + CONFIG.cfg_ext_if {true} \ + CONFIG.cfg_mgmt_if {false} \ + CONFIG.pcie_blk_locn {PCIE4C_X1Y1} \ + CONFIG.pf0_Use_Class_Code_Lookup_Assistant {true} \ + CONFIG.pf0_base_class_menu {Processing_accelerators} \ + CONFIG.pl_link_cap_max_link_speed {8.0_GT/s} \ + CONFIG.pl_link_cap_max_link_width {X8} \ + ] $xdma + + + # Create interface connections + connect_bd_intf_net -intf_net CLK_IN_D_0_1 [get_bd_intf_ports pcie_refclk] [get_bd_intf_pins pcie_refclk_buf/CLK_IN_D] + connect_bd_intf_net -intf_net cms_satellite_uart [get_bd_intf_ports satellite_uart] [get_bd_intf_pins cms/satellite_uart] + connect_bd_intf_net -intf_net ctrl_firewall_M_AXI [get_bd_intf_ports shell_axil_ctrl] [get_bd_intf_pins ctrl_firewall/M_AXI] + connect_bd_intf_net -intf_net dma_firewall_M_AXI [get_bd_intf_ports shell_axi_dma] [get_bd_intf_pins dma_firewall/M_AXI] + connect_bd_intf_net -intf_net mgmt_ram_BRAM_PORTA [get_bd_intf_pins mgmt_ram/BRAM_PORTA] [get_bd_intf_pins mgmt_ram_bram/BRAM_PORTA] + connect_bd_intf_net -intf_net smartconnect_ctrl_M00_AXI [get_bd_intf_pins cms/s_axi_ctrl] [get_bd_intf_pins smartconnect_ctrl/M00_AXI] + connect_bd_intf_net -intf_net smartconnect_ctrl_M01_AXI [get_bd_intf_pins qspi/AXI_LITE] [get_bd_intf_pins smartconnect_ctrl/M01_AXI] + connect_bd_intf_net -intf_net smartconnect_ctrl_M02_AXI [get_bd_intf_pins hbicap/S_AXI_CTRL] [get_bd_intf_pins smartconnect_ctrl/M02_AXI] + connect_bd_intf_net -intf_net smartconnect_ctrl_M03_AXI [get_bd_intf_pins mgmt_ram/S_AXI] [get_bd_intf_pins smartconnect_ctrl/M03_AXI] + connect_bd_intf_net -intf_net smartconnect_ctrl_M04_AXI [get_bd_intf_pins ctrl_firewall/S_AXI_CTL] [get_bd_intf_pins smartconnect_ctrl/M04_AXI] + connect_bd_intf_net -intf_net smartconnect_ctrl_M05_AXI [get_bd_intf_pins dma_firewall/S_AXI_CTL] [get_bd_intf_pins smartconnect_ctrl/M05_AXI] + connect_bd_intf_net -intf_net smartconnect_ctrl_M06_AXI [get_bd_intf_pins dfx_decoupler/s_axi_reg] [get_bd_intf_pins smartconnect_ctrl/M06_AXI] + connect_bd_intf_net -intf_net smartconnect_ctrl_M07_AXI [get_bd_intf_pins ctrl_firewall/S_AXI] [get_bd_intf_pins smartconnect_ctrl/M07_AXI] + connect_bd_intf_net -intf_net smartconnect_dma_M00_AXI [get_bd_intf_pins hbicap/S_AXI] [get_bd_intf_pins smartconnect_dma/M00_AXI] + connect_bd_intf_net -intf_net smartconnect_dma_M01_AXI [get_bd_intf_pins dma_firewall/S_AXI] [get_bd_intf_pins smartconnect_dma/M01_AXI] + connect_bd_intf_net -intf_net sys_refclk_0 [get_bd_intf_ports sys_refclk_0] [get_bd_intf_pins sys_refclk_0_buf/CLK_IN_D] + connect_bd_intf_net -intf_net xdma_M_AXI [get_bd_intf_pins smartconnect_dma/S00_AXI] [get_bd_intf_pins xdma/M_AXI] + connect_bd_intf_net -intf_net xdma_M_AXI_LITE [get_bd_intf_pins smartconnect_ctrl/S00_AXI] [get_bd_intf_pins xdma/M_AXI_LITE] + connect_bd_intf_net -intf_net xdma_pcie_cfg_ext [get_bd_intf_pins debug_bridge/pcie3_cfg_ext] [get_bd_intf_pins xdma/pcie_cfg_ext] + connect_bd_intf_net -intf_net xdma_pcie_mgt [get_bd_intf_ports pcie_mgt] [get_bd_intf_pins xdma/pcie_mgt] + + # Create port connections + connect_bd_net -net decouple_status [get_bd_pins dfx_decoupler/decouple_status] [get_bd_pins inv_decouple_status/Op1] + connect_bd_net -net eos [get_bd_pins hbicap/eos_in] [get_bd_pins qspi/eos] + connect_bd_net -net hbm_cattrip [get_bd_pins cms/interrupt_hbm_cattrip] [get_bd_pins dfx_decoupler/s_hbm_cattrip_INTERRUPT] + connect_bd_net -net hbm_temp_0 [get_bd_pins cms/hbm_temp_1] [get_bd_pins dfx_decoupler/s_hbm_temp_0_DATA] + connect_bd_net -net hbm_temp_1 [get_bd_pins cms/hbm_temp_2] [get_bd_pins dfx_decoupler/s_hbm_temp_1_DATA] + connect_bd_net -net icap_clk [get_bd_pins hbicap/icap_clk] [get_bd_pins mgmt_clk_wiz/icap_clk] + connect_bd_net -net inv_decouple_status [get_bd_pins inv_decouple_status/Res] [get_bd_pins shell_resetn/ext_reset_in] + connect_bd_net -net pcie_refclk_buf_IBUF_DS_ODIV2 [get_bd_pins pcie_refclk_buf/IBUF_DS_ODIV2] [get_bd_pins xdma/sys_clk] + connect_bd_net -net pcie_refclk_buf_IBUF_OUT [get_bd_pins pcie_refclk_buf/IBUF_OUT] [get_bd_pins xdma/sys_clk_gt] + connect_bd_net -net pcie_rstn [get_bd_ports pcie_rstn] [get_bd_pins xdma/sys_rst_n] + connect_bd_net -net satellite_gpio [get_bd_ports satellite_gpio] [get_bd_pins cms/satellite_gpio] + connect_bd_net -net shell_refclk_0 [get_bd_ports shell_refclk_0] [get_bd_pins sys_refclk_0_buf/IBUF_OUT] + connect_bd_net -net shell_resetn_peripheral_aresetn [get_bd_ports shell_rstn] [get_bd_pins shell_resetn/peripheral_aresetn] + connect_bd_net -net spi_clk [get_bd_pins mgmt_clk_wiz/spi_clk] [get_bd_pins qspi/ext_spi_clk] + connect_bd_net -net user_hbm_cattrip [get_bd_ports user_hbm_cattrip] [get_bd_pins dfx_decoupler/rp_hbm_cattrip_INTERRUPT] + connect_bd_net -net user_hbm_temp_0 [get_bd_ports user_hbm_temp_0] [get_bd_pins dfx_decoupler/rp_hbm_temp_0_DATA] + connect_bd_net -net user_hbm_temp_1 [get_bd_ports user_hbm_temp_1] [get_bd_pins dfx_decoupler/rp_hbm_temp_1_DATA] + connect_bd_net -net xdma_axi_aclk [get_bd_ports shell_axi_clk] [get_bd_pins cms/aclk_ctrl] [get_bd_pins ctrl_firewall/aclk] [get_bd_pins debug_bridge/clk] [get_bd_pins dfx_decoupler/aclk] [get_bd_pins dma_firewall/aclk] [get_bd_pins hbicap/s_axi_aclk] [get_bd_pins hbicap/s_axi_mm_aclk] [get_bd_pins mgmt_clk_wiz/clk_in1] [get_bd_pins mgmt_ram/s_axi_aclk] [get_bd_pins qspi/s_axi_aclk] [get_bd_pins shell_resetn/slowest_sync_clk] [get_bd_pins smartconnect_ctrl/aclk] [get_bd_pins smartconnect_dma/aclk] [get_bd_pins xdma/axi_aclk] + connect_bd_net -net xdma_axi_aresetn [get_bd_pins cms/aresetn_ctrl] [get_bd_pins ctrl_firewall/aresetn] [get_bd_pins dfx_decoupler/s_axi_reg_aresetn] [get_bd_pins dma_firewall/aresetn] [get_bd_pins hbicap/s_axi_aresetn] [get_bd_pins hbicap/s_axi_mm_aresetn] [get_bd_pins mgmt_clk_wiz/resetn] [get_bd_pins mgmt_ram/s_axi_aresetn] [get_bd_pins qspi/s_axi_aresetn] [get_bd_pins smartconnect_ctrl/aresetn] [get_bd_pins smartconnect_dma/aresetn] [get_bd_pins xdma/axi_aresetn] + + # Create address segments + assign_bd_address -offset 0xF000000000000000 -range 0x40000000 -target_address_space [get_bd_addr_spaces xdma/M_AXI] [get_bd_addr_segs hbicap/S_AXI/Mem0] -force + assign_bd_address -offset 0x00000000 -range 0x0001000000000000 -target_address_space [get_bd_addr_spaces xdma/M_AXI] [get_bd_addr_segs shell_axi_dma/Reg] -force + assign_bd_address -offset 0x04000000 -range 0x00040000 -target_address_space [get_bd_addr_spaces xdma/M_AXI_LITE] [get_bd_addr_segs cms/s_axi_ctrl/Mem] -force + assign_bd_address -offset 0x04070000 -range 0x00010000 -target_address_space [get_bd_addr_spaces xdma/M_AXI_LITE] [get_bd_addr_segs ctrl_firewall/S_AXI_CTL/Control] -force + assign_bd_address -offset 0x04090000 -range 0x00010000 -target_address_space [get_bd_addr_spaces xdma/M_AXI_LITE] [get_bd_addr_segs dfx_decoupler/s_axi_reg/Reg] -force + assign_bd_address -offset 0x04080000 -range 0x00010000 -target_address_space [get_bd_addr_spaces xdma/M_AXI_LITE] [get_bd_addr_segs dma_firewall/S_AXI_CTL/Control] -force + assign_bd_address -offset 0x04050000 -range 0x00010000 -target_address_space [get_bd_addr_spaces xdma/M_AXI_LITE] [get_bd_addr_segs hbicap/S_AXI_CTRL/Reg0] -force + assign_bd_address -offset 0x04060000 -range 0x00002000 -target_address_space [get_bd_addr_spaces xdma/M_AXI_LITE] [get_bd_addr_segs mgmt_ram/S_AXI/Mem0] -force + assign_bd_address -offset 0x04040000 -range 0x00010000 -target_address_space [get_bd_addr_spaces xdma/M_AXI_LITE] [get_bd_addr_segs qspi/AXI_LITE/Reg] -force + assign_bd_address -offset 0x00000000 -range 0x04000000 -target_address_space [get_bd_addr_spaces xdma/M_AXI_LITE] [get_bd_addr_segs shell_axil_ctrl/Reg] -force + + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design + close_bd_design $design_name +} +# End of cr_bd_shell() \ No newline at end of file diff --git a/hw/shells/xilinx_u55c/xdma_gen3x8/top.v b/hw/shells/xilinx_u55c/xdma_gen3x8/top.v new file mode 100644 index 0000000..d96ca6f --- /dev/null +++ b/hw/shells/xilinx_u55c/xdma_gen3x8/top.v @@ -0,0 +1,222 @@ +module top ( + // -- PCIE -------------------------------------------------------------------------------------------------------- + input pcie_refclk_clk_n, + input pcie_refclk_clk_p, + input pcie_rstn, + input [7:0] pcie_mgt_rxn, + input [7:0] pcie_mgt_rxp, + output [7:0] pcie_mgt_txn, + output [7:0] pcie_mgt_txp, + // ---------------------------------------------------------------------------------------------------------------- + // -- SATELLITE CONTROLLER ---------------------------------------------------------------------------------------- + input [3:0] satellite_gpio, + input satellite_uart_rxd, + output satellite_uart_txd, + // ---------------------------------------------------------------------------------------------------------------- + // -- REFCLKS ----------------------------------------------------------------------------------------------------- + input sys_refclk_0_clk_n, + input sys_refclk_0_clk_p + // ---------------------------------------------------------------------------------------------------------------- +); +wire shell_axi_clk; +wire [63:0]shell_axi_dma_araddr; +wire [1:0]shell_axi_dma_arburst; +wire [3:0]shell_axi_dma_arcache; +wire [7:0]shell_axi_dma_arlen; +wire [0:0]shell_axi_dma_arlock; +wire [2:0]shell_axi_dma_arprot; +wire [3:0]shell_axi_dma_arqos; +wire shell_axi_dma_arready; +wire [2:0]shell_axi_dma_arsize; +wire shell_axi_dma_arvalid; +wire [63:0]shell_axi_dma_awaddr; +wire [1:0]shell_axi_dma_awburst; +wire [3:0]shell_axi_dma_awcache; +wire [7:0]shell_axi_dma_awlen; +wire [0:0]shell_axi_dma_awlock; +wire [2:0]shell_axi_dma_awprot; +wire [3:0]shell_axi_dma_awqos; +wire shell_axi_dma_awready; +wire [2:0]shell_axi_dma_awsize; +wire shell_axi_dma_awvalid; +wire shell_axi_dma_bready; +wire [1:0]shell_axi_dma_bresp; +wire shell_axi_dma_bvalid; +wire [255:0]shell_axi_dma_rdata; +wire shell_axi_dma_rlast; +wire shell_axi_dma_rready; +wire [1:0]shell_axi_dma_rresp; +wire shell_axi_dma_rvalid; +wire [255:0]shell_axi_dma_wdata; +wire shell_axi_dma_wlast; +wire shell_axi_dma_wready; +wire [31:0]shell_axi_dma_wstrb; +wire shell_axi_dma_wvalid; +wire [31:0]shell_axil_ctrl_araddr; +wire [2:0]shell_axil_ctrl_arprot; +wire shell_axil_ctrl_arready; +wire shell_axil_ctrl_arvalid; +wire [31:0]shell_axil_ctrl_awaddr; +wire [2:0]shell_axil_ctrl_awprot; +wire shell_axil_ctrl_awready; +wire shell_axil_ctrl_awvalid; +wire shell_axil_ctrl_bready; +wire [1:0]shell_axil_ctrl_bresp; +wire shell_axil_ctrl_bvalid; +wire [31:0]shell_axil_ctrl_rdata; +wire shell_axil_ctrl_rready; +wire [1:0]shell_axil_ctrl_rresp; +wire shell_axil_ctrl_rvalid; +wire [31:0]shell_axil_ctrl_wdata; +wire shell_axil_ctrl_wready; +wire [3:0]shell_axil_ctrl_wstrb; +wire shell_axil_ctrl_wvalid; +wire [0:0]shell_rstn; +wire user_hbm_cattrip; +wire [6:0]user_hbm_temp_0; +wire [6:0]user_hbm_temp_1; + +user user_partition ( + // -- REFCLKS -- + .shell_refclk_0(sys_refclk_0), + // -- SHELL <> USER -- + .shell_axi_clk(shell_axi_clk), + .shell_rstn(shell_rstn), + .user_hbm_cattrip(user_hbm_cattrip), + .user_hbm_temp_0(user_hbm_temp_0), + .user_hbm_temp_1(user_hbm_temp_1), + // -- SHELL AXIL CTRL -- + .shell_axil_ctrl_araddr(shell_axil_ctrl_araddr), + .shell_axil_ctrl_arprot(shell_axil_ctrl_arprot), + .shell_axil_ctrl_arready(shell_axil_ctrl_arready), + .shell_axil_ctrl_arvalid(shell_axil_ctrl_arvalid), + .shell_axil_ctrl_awaddr(shell_axil_ctrl_awaddr), + .shell_axil_ctrl_awprot(shell_axil_ctrl_awprot), + .shell_axil_ctrl_awready(shell_axil_ctrl_awready), + .shell_axil_ctrl_awvalid(shell_axil_ctrl_awvalid), + .shell_axil_ctrl_bready(shell_axil_ctrl_bready), + .shell_axil_ctrl_bresp(shell_axil_ctrl_bresp), + .shell_axil_ctrl_bvalid(shell_axil_ctrl_bvalid), + .shell_axil_ctrl_rdata(shell_axil_ctrl_rdata), + .shell_axil_ctrl_rready(shell_axil_ctrl_rready), + .shell_axil_ctrl_rresp(shell_axil_ctrl_rresp), + .shell_axil_ctrl_rvalid(shell_axil_ctrl_rvalid), + .shell_axil_ctrl_wdata(shell_axil_ctrl_wdata), + .shell_axil_ctrl_wready(shell_axil_ctrl_wready), + .shell_axil_ctrl_wstrb(shell_axil_ctrl_wstrb), + .shell_axil_ctrl_wvalid(shell_axil_ctrl_wvalid), + // -- SHELL AXI DMA -- + .shell_axi_dma_araddr(shell_axi_dma_araddr), + .shell_axi_dma_arburst(shell_axi_dma_arburst), + .shell_axi_dma_arcache(shell_axi_dma_arcache), + .shell_axi_dma_arlen(shell_axi_dma_arlen), + .shell_axi_dma_arlock(shell_axi_dma_arlock), + .shell_axi_dma_arprot(shell_axi_dma_arprot), + .shell_axi_dma_arqos(shell_axi_dma_arqos), + .shell_axi_dma_arready(shell_axi_dma_arready), + .shell_axi_dma_arsize(shell_axi_dma_arsize), + .shell_axi_dma_arvalid(shell_axi_dma_arvalid), + .shell_axi_dma_awaddr(shell_axi_dma_awaddr), + .shell_axi_dma_awburst(shell_axi_dma_awburst), + .shell_axi_dma_awcache(shell_axi_dma_awcache), + .shell_axi_dma_awlen(shell_axi_dma_awlen), + .shell_axi_dma_awlock(shell_axi_dma_awlock), + .shell_axi_dma_awprot(shell_axi_dma_awprot), + .shell_axi_dma_awqos(shell_axi_dma_awqos), + .shell_axi_dma_awready(shell_axi_dma_awready), + .shell_axi_dma_awsize(shell_axi_dma_awsize), + .shell_axi_dma_awvalid(shell_axi_dma_awvalid), + .shell_axi_dma_bready(shell_axi_dma_bready), + .shell_axi_dma_bresp(shell_axi_dma_bresp), + .shell_axi_dma_bvalid(shell_axi_dma_bvalid), + .shell_axi_dma_rdata(shell_axi_dma_rdata), + .shell_axi_dma_rlast(shell_axi_dma_rlast), + .shell_axi_dma_rready(shell_axi_dma_rready), + .shell_axi_dma_rresp(shell_axi_dma_rresp), + .shell_axi_dma_rvalid(shell_axi_dma_rvalid), + .shell_axi_dma_wdata(shell_axi_dma_wdata), + .shell_axi_dma_wlast(shell_axi_dma_wlast), + .shell_axi_dma_wready(shell_axi_dma_wready), + .shell_axi_dma_wstrb(shell_axi_dma_wstrb), + .shell_axi_dma_wvalid(shell_axi_dma_wvalid) +); + +shell shell_partition ( + // -- REFCLKS -- + .sys_refclk_0_clk_n(sys_refclk_0_clk_n), + .sys_refclk_0_clk_p(sys_refclk_0_clk_p), + .shell_refclk_0(shell_refclk_0), + // -- PCIE -- + .pcie_refclk_clk_n(pcie_refclk_clk_n), + .pcie_refclk_clk_p(pcie_refclk_clk_p), + .pcie_rstn(pcie_rstn), + .pcie_mgt_rxn(pcie_mgt_rxn), + .pcie_mgt_rxp(pcie_mgt_rxp), + .pcie_mgt_txn(pcie_mgt_txn), + .pcie_mgt_txp(pcie_mgt_txp), + // -- SATELLITE CONTROLLER -- + .satellite_gpio(satellite_gpio), + .satellite_uart_rxd(satellite_uart_rxd), + .satellite_uart_txd(satellite_uart_txd), + // -- SHELL <> USER -- + .shell_axi_clk(shell_axi_clk), + .shell_rstn(shell_rstn), + .user_hbm_cattrip(user_hbm_cattrip), + .user_hbm_temp_0(user_hbm_temp_0), + .user_hbm_temp_1(user_hbm_temp_1), + // -- SHELL AXIL CTRL -- + .shell_axil_ctrl_araddr(shell_axil_ctrl_araddr), + .shell_axil_ctrl_arprot(shell_axil_ctrl_arprot), + .shell_axil_ctrl_arready(shell_axil_ctrl_arready), + .shell_axil_ctrl_arvalid(shell_axil_ctrl_arvalid), + .shell_axil_ctrl_awaddr(shell_axil_ctrl_awaddr), + .shell_axil_ctrl_awprot(shell_axil_ctrl_awprot), + .shell_axil_ctrl_awready(shell_axil_ctrl_awready), + .shell_axil_ctrl_awvalid(shell_axil_ctrl_awvalid), + .shell_axil_ctrl_bready(shell_axil_ctrl_bready), + .shell_axil_ctrl_bresp(shell_axil_ctrl_bresp), + .shell_axil_ctrl_bvalid(shell_axil_ctrl_bvalid), + .shell_axil_ctrl_rdata(shell_axil_ctrl_rdata), + .shell_axil_ctrl_rready(shell_axil_ctrl_rready), + .shell_axil_ctrl_rresp(shell_axil_ctrl_rresp), + .shell_axil_ctrl_rvalid(shell_axil_ctrl_rvalid), + .shell_axil_ctrl_wdata(shell_axil_ctrl_wdata), + .shell_axil_ctrl_wready(shell_axil_ctrl_wready), + .shell_axil_ctrl_wstrb(shell_axil_ctrl_wstrb), + .shell_axil_ctrl_wvalid(shell_axil_ctrl_wvalid), + // -- SHELL AXI DMA -- + .shell_axi_dma_araddr(shell_axi_dma_araddr), + .shell_axi_dma_arburst(shell_axi_dma_arburst), + .shell_axi_dma_arcache(shell_axi_dma_arcache), + .shell_axi_dma_arlen(shell_axi_dma_arlen), + .shell_axi_dma_arlock(shell_axi_dma_arlock), + .shell_axi_dma_arprot(shell_axi_dma_arprot), + .shell_axi_dma_arqos(shell_axi_dma_arqos), + .shell_axi_dma_arready(shell_axi_dma_arready), + .shell_axi_dma_arsize(shell_axi_dma_arsize), + .shell_axi_dma_arvalid(shell_axi_dma_arvalid), + .shell_axi_dma_awaddr(shell_axi_dma_awaddr), + .shell_axi_dma_awburst(shell_axi_dma_awburst), + .shell_axi_dma_awcache(shell_axi_dma_awcache), + .shell_axi_dma_awlen(shell_axi_dma_awlen), + .shell_axi_dma_awlock(shell_axi_dma_awlock), + .shell_axi_dma_awprot(shell_axi_dma_awprot), + .shell_axi_dma_awqos(shell_axi_dma_awqos), + .shell_axi_dma_awready(shell_axi_dma_awready), + .shell_axi_dma_awsize(shell_axi_dma_awsize), + .shell_axi_dma_awvalid(shell_axi_dma_awvalid), + .shell_axi_dma_bready(shell_axi_dma_bready), + .shell_axi_dma_bresp(shell_axi_dma_bresp), + .shell_axi_dma_bvalid(shell_axi_dma_bvalid), + .shell_axi_dma_rdata(shell_axi_dma_rdata), + .shell_axi_dma_rlast(shell_axi_dma_rlast), + .shell_axi_dma_rready(shell_axi_dma_rready), + .shell_axi_dma_rresp(shell_axi_dma_rresp), + .shell_axi_dma_rvalid(shell_axi_dma_rvalid), + .shell_axi_dma_wdata(shell_axi_dma_wdata), + .shell_axi_dma_wlast(shell_axi_dma_wlast), + .shell_axi_dma_wready(shell_axi_dma_wready), + .shell_axi_dma_wstrb(shell_axi_dma_wstrb), + .shell_axi_dma_wvalid(shell_axi_dma_wvalid) +); +endmodule diff --git a/hw/shells/xilinx_u55c/xdma_gen3x8/user.tcl b/hw/shells/xilinx_u55c/xdma_gen3x8/user.tcl new file mode 100644 index 0000000..16b2fd7 --- /dev/null +++ b/hw/shells/xilinx_u55c/xdma_gen3x8/user.tcl @@ -0,0 +1,313 @@ +# Proc to create BD user +proc cr_bd_user { parentCell } { + + # CHANGE DESIGN NAME HERE + set design_name user + + common::send_gid_msg -ssname BD::TCL -id 2010 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + set bCheckIPsPassed 1 + ################################################################## + # CHECK IPs + ################################################################## + set bCheckIPs 1 + if { $bCheckIPs == 1 } { + set list_check_ips "\ + xilinx.com:ip:axi_apb_bridge:3.0\ + xilinx.com:ip:clk_wiz:6.0\ + xilinx.com:ip:proc_sys_reset:5.0\ + xilinx.com:ip:hbm:1.0\ + xilinx.com:ip:util_vector_logic:2.0\ + xilinx.com:ip:smartconnect:1.0\ + " + + set list_ips_missing "" + common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + + } + + if { $bCheckIPsPassed != 1 } { + common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 + } + + variable script_folder + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set shell_axi_dma [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 shell_axi_dma ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {64} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {256} \ + CONFIG.FREQ_HZ {250000000} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {1} \ + CONFIG.HAS_LOCK {1} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {1} \ + CONFIG.HAS_REGION {0} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {0} \ + CONFIG.MAX_BURST_LENGTH {256} \ + CONFIG.NUM_READ_OUTSTANDING {32} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {32} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {0} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $shell_axi_dma + + set shell_axil_ctrl [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 shell_axil_ctrl ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {32} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {32} \ + CONFIG.FREQ_HZ {250000000} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {0} \ + CONFIG.HAS_CACHE {0} \ + CONFIG.HAS_LOCK {0} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {0} \ + CONFIG.HAS_REGION {0} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {0} \ + CONFIG.MAX_BURST_LENGTH {1} \ + CONFIG.NUM_READ_OUTSTANDING {1} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {1} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI4LITE} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {0} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $shell_axil_ctrl + + + # Create ports + set shell_axi_clk [ create_bd_port -dir I -type clk -freq_hz 250000000 shell_axi_clk ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {shell_axi_dma:shell_axil_ctrl} \ + CONFIG.ASSOCIATED_RESET {shell_rstn} \ + ] $shell_axi_clk + set shell_refclk_0 [ create_bd_port -dir I -type clk -freq_hz 100000000 shell_refclk_0 ] + set shell_rstn [ create_bd_port -dir I -type rst shell_rstn ] + set user_hbm_cattrip [ create_bd_port -dir O -from 0 -to 0 -type intr user_hbm_cattrip ] + set user_hbm_temp_0 [ create_bd_port -dir O -from 6 -to 0 -type data user_hbm_temp_0 ] + set user_hbm_temp_1 [ create_bd_port -dir O -from 6 -to 0 -type data user_hbm_temp_1 ] + + # Create instance: axi_apb_bridge, and set properties + set axi_apb_bridge [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_apb_bridge:3.0 axi_apb_bridge ] + set_property -dict [list \ + CONFIG.C_APB_NUM_SLAVES {2} \ + CONFIG.C_M_APB_PROTOCOL {apb4} \ + ] $axi_apb_bridge + + + # Create instance: core_clk, and set properties + set core_clk [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 core_clk ] + set_property -dict [list \ + CONFIG.CLKOUT1_JITTER {104.289} \ + CONFIG.CLKOUT1_PHASE_ERROR {153.873} \ + CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {450} \ + CONFIG.CLK_OUT1_PORT {hbm_axi_clk} \ + CONFIG.ENABLE_CDDC {false} \ + CONFIG.MMCM_CLKFBOUT_MULT_F {23.625} \ + CONFIG.MMCM_CLKOUT0_DIVIDE_F {2.625} \ + CONFIG.MMCM_DIVCLK_DIVIDE {5} \ + CONFIG.PRIM_SOURCE {No_buffer} \ + CONFIG.RESET_PORT {reset} \ + CONFIG.RESET_TYPE {ACTIVE_HIGH} \ + CONFIG.USE_LOCKED {false} \ + CONFIG.USE_RESET {false} \ + ] $core_clk + + + # Create instance: core_reset, and set properties + set core_reset [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 core_reset ] + + # Create instance: hbm, and set properties + set hbm [ create_bd_cell -type ip -vlnv xilinx.com:ip:hbm:1.0 hbm ] + set_property -dict [list \ + CONFIG.USER_HBM_DENSITY {16GB} \ + CONFIG.USER_SAXI_00 {false} \ + CONFIG.USER_SAXI_01 {false} \ + CONFIG.USER_SAXI_02 {false} \ + CONFIG.USER_SAXI_03 {false} \ + CONFIG.USER_SAXI_04 {false} \ + CONFIG.USER_SAXI_05 {false} \ + CONFIG.USER_SAXI_06 {false} \ + CONFIG.USER_SAXI_07 {false} \ + CONFIG.USER_SAXI_08 {false} \ + CONFIG.USER_SAXI_09 {false} \ + CONFIG.USER_SAXI_10 {false} \ + CONFIG.USER_SAXI_11 {false} \ + CONFIG.USER_SAXI_12 {false} \ + CONFIG.USER_SAXI_13 {false} \ + CONFIG.USER_SAXI_14 {false} \ + CONFIG.USER_SAXI_15 {false} \ + CONFIG.USER_SAXI_16 {false} \ + CONFIG.USER_SAXI_17 {false} \ + CONFIG.USER_SAXI_18 {false} \ + CONFIG.USER_SAXI_19 {false} \ + CONFIG.USER_SAXI_20 {false} \ + CONFIG.USER_SAXI_21 {false} \ + CONFIG.USER_SAXI_22 {false} \ + CONFIG.USER_SAXI_23 {false} \ + CONFIG.USER_SAXI_24 {false} \ + CONFIG.USER_SAXI_25 {false} \ + CONFIG.USER_SAXI_26 {false} \ + CONFIG.USER_SAXI_27 {false} \ + CONFIG.USER_SAXI_28 {false} \ + CONFIG.USER_SAXI_29 {false} \ + CONFIG.USER_SAXI_30 {false} \ + ] $hbm + + + # Create instance: hbm_cattrip, and set properties + set hbm_cattrip [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 hbm_cattrip ] + set_property -dict [list \ + CONFIG.C_OPERATION {or} \ + CONFIG.C_SIZE {1} \ + ] $hbm_cattrip + + + # Create instance: hbm_reset, and set properties + set hbm_reset [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 hbm_reset ] + + # Create instance: smartconnect_ctrl, and set properties + set smartconnect_ctrl [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_ctrl ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $smartconnect_ctrl + + + # Create instance: smartconnect_dma, and set properties + set smartconnect_dma [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_dma ] + set_property -dict [list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {1} \ + ] $smartconnect_dma + + + # Create interface connections + connect_bd_intf_net -intf_net axi_apb_bridge_APB_M [get_bd_intf_pins axi_apb_bridge/APB_M] [get_bd_intf_pins hbm/SAPB_0] + connect_bd_intf_net -intf_net axi_apb_bridge_APB_M2 [get_bd_intf_pins axi_apb_bridge/APB_M2] [get_bd_intf_pins hbm/SAPB_1] + connect_bd_intf_net -intf_net shell_axi_dma_1 [get_bd_intf_ports shell_axi_dma] [get_bd_intf_pins smartconnect_dma/S00_AXI] + connect_bd_intf_net -intf_net shell_axil_ctrl_1 [get_bd_intf_ports shell_axil_ctrl] [get_bd_intf_pins smartconnect_ctrl/S00_AXI] + connect_bd_intf_net -intf_net smartconnect_ctrl_M00_AXI [get_bd_intf_pins axi_apb_bridge/AXI4_LITE] [get_bd_intf_pins smartconnect_ctrl/M00_AXI] + connect_bd_intf_net -intf_net smartconnect_dma_M00_AXI [get_bd_intf_pins hbm/SAXI_31_8HI] [get_bd_intf_pins smartconnect_dma/M00_AXI] + + # Create port connections + connect_bd_net -net core_clk_hbm_axi_clk [get_bd_pins core_clk/hbm_axi_clk] [get_bd_pins core_reset/slowest_sync_clk] [get_bd_pins hbm/AXI_31_ACLK] [get_bd_pins smartconnect_dma/aclk1] + connect_bd_net -net core_reset_peripheral_aresetn [get_bd_pins core_reset/peripheral_aresetn] [get_bd_pins hbm/AXI_31_ARESET_N] + connect_bd_net -net hbm_DRAM_0_STAT_CATTRIP [get_bd_pins hbm/DRAM_0_STAT_CATTRIP] [get_bd_pins hbm_cattrip/Op1] + connect_bd_net -net hbm_DRAM_0_STAT_TEMP [get_bd_ports user_hbm_temp_0] [get_bd_pins hbm/DRAM_0_STAT_TEMP] + connect_bd_net -net hbm_DRAM_1_STAT_CATTRIP [get_bd_pins hbm/DRAM_1_STAT_CATTRIP] [get_bd_pins hbm_cattrip/Op2] + connect_bd_net -net hbm_DRAM_1_STAT_TEMP [get_bd_ports user_hbm_temp_1] [get_bd_pins hbm/DRAM_1_STAT_TEMP] + connect_bd_net -net hbm_cattrip_Res [get_bd_ports user_hbm_cattrip] [get_bd_pins hbm_cattrip/Res] + connect_bd_net -net hbm_refclk_buf_IBUF_OUT [get_bd_ports shell_refclk_0] [get_bd_pins axi_apb_bridge/s_axi_aclk] [get_bd_pins hbm/APB_0_PCLK] [get_bd_pins hbm/APB_1_PCLK] [get_bd_pins hbm/HBM_REF_CLK_0] [get_bd_pins hbm/HBM_REF_CLK_1] [get_bd_pins hbm_reset/slowest_sync_clk] [get_bd_pins smartconnect_ctrl/aclk1] + connect_bd_net -net shell_axi_clk_1 [get_bd_ports shell_axi_clk] [get_bd_pins core_clk/clk_in1] [get_bd_pins smartconnect_ctrl/aclk] [get_bd_pins smartconnect_dma/aclk] + connect_bd_net -net shell_rstn_1 [get_bd_ports shell_rstn] [get_bd_pins core_reset/ext_reset_in] [get_bd_pins hbm_reset/ext_reset_in] [get_bd_pins smartconnect_ctrl/aresetn] [get_bd_pins smartconnect_dma/aresetn] + connect_bd_net -net sys_reset_peripheral_aresetn [get_bd_pins axi_apb_bridge/s_axi_aresetn] [get_bd_pins hbm/APB_0_PRESET_N] [get_bd_pins hbm/APB_1_PRESET_N] [get_bd_pins hbm_reset/peripheral_aresetn] + + # Create address segments + assign_bd_address -offset 0x00000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces shell_axi_dma] [get_bd_addr_segs hbm/SAXI_31_8HI/HBM_MEM00] -force + assign_bd_address -offset 0x20000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces shell_axi_dma] [get_bd_addr_segs hbm/SAXI_31_8HI/HBM_MEM01] -force + assign_bd_address -offset 0x40000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces shell_axi_dma] [get_bd_addr_segs hbm/SAXI_31_8HI/HBM_MEM02] -force + assign_bd_address -offset 0x60000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces shell_axi_dma] [get_bd_addr_segs hbm/SAXI_31_8HI/HBM_MEM03] -force + assign_bd_address -offset 0x80000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces shell_axi_dma] [get_bd_addr_segs hbm/SAXI_31_8HI/HBM_MEM04] -force + assign_bd_address -offset 0xA0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces shell_axi_dma] [get_bd_addr_segs hbm/SAXI_31_8HI/HBM_MEM05] -force + assign_bd_address -offset 0xC0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces shell_axi_dma] [get_bd_addr_segs hbm/SAXI_31_8HI/HBM_MEM06] -force + assign_bd_address -offset 0xE0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces shell_axi_dma] [get_bd_addr_segs hbm/SAXI_31_8HI/HBM_MEM07] -force + assign_bd_address -offset 0x000100000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces shell_axi_dma] [get_bd_addr_segs hbm/SAXI_31_8HI/HBM_MEM08] -force + assign_bd_address -offset 0x000120000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces shell_axi_dma] [get_bd_addr_segs hbm/SAXI_31_8HI/HBM_MEM09] -force + assign_bd_address -offset 0x000140000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces shell_axi_dma] [get_bd_addr_segs hbm/SAXI_31_8HI/HBM_MEM10] -force + assign_bd_address -offset 0x000160000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces shell_axi_dma] [get_bd_addr_segs hbm/SAXI_31_8HI/HBM_MEM11] -force + assign_bd_address -offset 0x000180000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces shell_axi_dma] [get_bd_addr_segs hbm/SAXI_31_8HI/HBM_MEM12] -force + assign_bd_address -offset 0x0001A0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces shell_axi_dma] [get_bd_addr_segs hbm/SAXI_31_8HI/HBM_MEM13] -force + assign_bd_address -offset 0x0001C0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces shell_axi_dma] [get_bd_addr_segs hbm/SAXI_31_8HI/HBM_MEM14] -force + assign_bd_address -offset 0x0001E0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces shell_axi_dma] [get_bd_addr_segs hbm/SAXI_31_8HI/HBM_MEM15] -force + assign_bd_address -offset 0x000200000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces shell_axi_dma] [get_bd_addr_segs hbm/SAXI_31_8HI/HBM_MEM16] -force + assign_bd_address -offset 0x000220000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces shell_axi_dma] [get_bd_addr_segs hbm/SAXI_31_8HI/HBM_MEM17] -force + assign_bd_address -offset 0x000240000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces shell_axi_dma] [get_bd_addr_segs hbm/SAXI_31_8HI/HBM_MEM18] -force + assign_bd_address -offset 0x000260000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces shell_axi_dma] [get_bd_addr_segs hbm/SAXI_31_8HI/HBM_MEM19] -force + assign_bd_address -offset 0x000280000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces shell_axi_dma] [get_bd_addr_segs hbm/SAXI_31_8HI/HBM_MEM20] -force + assign_bd_address -offset 0x0002A0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces shell_axi_dma] [get_bd_addr_segs hbm/SAXI_31_8HI/HBM_MEM21] -force + assign_bd_address -offset 0x0002C0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces shell_axi_dma] [get_bd_addr_segs hbm/SAXI_31_8HI/HBM_MEM22] -force + assign_bd_address -offset 0x0002E0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces shell_axi_dma] [get_bd_addr_segs hbm/SAXI_31_8HI/HBM_MEM23] -force + assign_bd_address -offset 0x000300000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces shell_axi_dma] [get_bd_addr_segs hbm/SAXI_31_8HI/HBM_MEM24] -force + assign_bd_address -offset 0x000320000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces shell_axi_dma] [get_bd_addr_segs hbm/SAXI_31_8HI/HBM_MEM25] -force + assign_bd_address -offset 0x000340000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces shell_axi_dma] [get_bd_addr_segs hbm/SAXI_31_8HI/HBM_MEM26] -force + assign_bd_address -offset 0x000360000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces shell_axi_dma] [get_bd_addr_segs hbm/SAXI_31_8HI/HBM_MEM27] -force + assign_bd_address -offset 0x000380000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces shell_axi_dma] [get_bd_addr_segs hbm/SAXI_31_8HI/HBM_MEM28] -force + assign_bd_address -offset 0x0003A0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces shell_axi_dma] [get_bd_addr_segs hbm/SAXI_31_8HI/HBM_MEM29] -force + assign_bd_address -offset 0x0003C0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces shell_axi_dma] [get_bd_addr_segs hbm/SAXI_31_8HI/HBM_MEM30] -force + assign_bd_address -offset 0x0003E0000000 -range 0x20000000 -target_address_space [get_bd_addr_spaces shell_axi_dma] [get_bd_addr_segs hbm/SAXI_31_8HI/HBM_MEM31] -force + assign_bd_address -offset 0x00000000 -range 0x00400000 -target_address_space [get_bd_addr_spaces shell_axil_ctrl] [get_bd_addr_segs hbm/SAPB_0/Reg] -force + assign_bd_address -offset 0x00400000 -range 0x00400000 -target_address_space [get_bd_addr_spaces shell_axil_ctrl] [get_bd_addr_segs hbm/SAPB_1/Reg] -force + + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design + close_bd_design $design_name +} +# End of cr_bd_user() \ No newline at end of file