diff --git a/a__box_2bmi_2bmi088_8h.html b/a__box_2bmi_2bmi088_8h.html index 8d5246ca..4c5c7bfd 100644 --- a/a__box_2bmi_2bmi088_8h.html +++ b/a__box_2bmi_2bmi088_8h.html @@ -126,9 +126,9 @@   #define BMI088_GYRO_RATE_Z_LSB_ADDR   (0x04U) /* Gyro Z rate LSB address */   -#define BMI088_GYRO_RANGE_ADDR   (0x0FU) /* Gyro data range address */ +#define BMI088_GYRO_RANGE_ADDR   (0x0FU) /* Gyro data range address */   -#define BMI088_GYRO_BANDWIDTH_ADDR   (0x10U) /* Gyro data bandwidth address */ +#define BMI088_GYRO_BANDWIDTH_ADDR   (0x10U) /* Gyro data bandwidth address */   #define BMI088_GYRO_SELFTEST_ADDR   (0x3CU) /* Gyro self test address */   @@ -388,7 +388,7 @@

- +
#define BMI088_GYRO_BANDWIDTH_ADDR   (0x10U) /* Gyro data bandwidth address */#define BMI088_GYRO_BANDWIDTH_ADDR   (0x10U) /* Gyro data bandwidth address */
@@ -430,7 +430,7 @@

- +
#define BMI088_GYRO_RANGE_ADDR   (0x0FU) /* Gyro data range address */#define BMI088_GYRO_RANGE_ADDR   (0x0FU) /* Gyro data range address */

diff --git a/a__box_2can_2can__parse_8h_source.html b/a__box_2can_2can__parse_8h_source.html index 811e266e..54074566 100644 --- a/a__box_2can_2can__parse_8h_source.html +++ b/a__box_2can_2can__parse_8h_source.html @@ -501,7 +501,7 @@
386 uint64_t daq_command: 64;
387 } daq_command_A_BOX;
388 uint8_t raw_data[8];
-
389} __attribute__((packed)) CanParsedData_t;
+
389} __attribute__((packed)) CanParsedData_t;
390/* END AUTO MESSAGE STRUCTURE */
391
@@ -658,7 +658,7 @@
can_data
can_data_t can_data
Definition can_parse.c:16
initCANParse
void initCANParse(void)
Setup queue and message filtering.
Definition can_parse.c:19
send_fault
void send_fault(uint16_t id, bool latched)
-
__attribute__
struct eeprom __attribute__
Definition daq_hub.h:70
+
__attribute__
struct gs_tx_context __attribute__
Definition daq_hub.h:70
charge_enable
uint8_t charge_enable
Definition main.c:102
can.h
diff --git a/a__box_2main_8h_source.html b/a__box_2main_8h_source.html index f9cc265d..13fad4c5 100644 --- a/a__box_2main_8h_source.html +++ b/a__box_2main_8h_source.html @@ -197,7 +197,7 @@
104 // CAN I DO THIS??
105 uint16_t isense_ch1;
106 uint16_t isense_ch2;
-
107}__attribute__((packed)) ADCReadings_t;
+
107}__attribute__((packed)) ADCReadings_t;
108volatile extern ADCReadings_t adc_readings;
109
110extern bool bms_daq_override;
@@ -210,8 +210,8 @@
canTxSendToBack
void canTxSendToBack(CanMsgTypeDef_t *msg)
Definition main.c:116
bms_daq_override
bool bms_daq_override
Definition main.c:84
bms_daq_stat
bool bms_daq_stat
Definition main.c:85
-
__attribute__
struct eeprom __attribute__
Definition daq_hub.h:70
msg
char msg[100]
Definition main.c:105
+
__attribute__
struct gs_tx_context __attribute__
Definition daq_hub.h:70
can.h
CanMsgTypeDef_t
Definition can.h:31
__attribute__::isense_ch2
uint16_t isense_ch2
Definition main.h:106
diff --git a/afe_8c.html b/afe_8c.html index c6fac621..81b39e19 100644 --- a/afe_8c.html +++ b/afe_8c.html @@ -97,7 +97,7 @@ - + @@ -109,9 +109,9 @@ - + - +

Functions

int verifyPEC (uint8_t *data, uint16_t len, uint16_t PEC)
int verifyPEC (uint8_t *data, uint16_t len, uint16_t PEC)
 
void checkConn (void)
 
 
void broadcastPoll (uint16_t command)
 
void broadcastWrite (uint16_t command, uint16_t size, uint8_t *data)
void broadcastWrite (uint16_t command, uint16_t size, uint8_t *data)
 
int broadcastRead (uint16_t command, uint16_t size, uint8_t *data)
int broadcastRead (uint16_t command, uint16_t size, uint8_t *data)
 

Function Documentation

diff --git a/afe_8h.html b/afe_8h.html index ee3dcc2e..65e8b366 100644 --- a/afe_8h.html +++ b/afe_8h.html @@ -318,9 +318,9 @@   void broadcastPoll (uint16_t command)   -void broadcastWrite (uint16_t command, uint16_t size, uint8_t *data) +void broadcastWrite (uint16_t command, uint16_t size, uint8_t *data)   -int broadcastRead (uint16_t command, uint16_t size, uint8_t *data) +int broadcastRead (uint16_t command, uint16_t size, uint8_t *data)  

Macro Definition Documentation

diff --git a/afe_8h_source.html b/afe_8h_source.html index 93b92f66..795dfcd4 100644 --- a/afe_8h_source.html +++ b/afe_8h_source.html @@ -247,8 +247,8 @@
160void afeTask(void);
161void afeWakeup(void);
162void broadcastPoll(uint16_t command);
-
163void broadcastWrite(uint16_t command, uint16_t size, uint8_t* data);
-
164int broadcastRead(uint16_t command, uint16_t size, uint8_t* data);
+
163void broadcastWrite(uint16_t command, uint16_t size, uint8_t* data);
+
164int broadcastRead(uint16_t command, uint16_t size, uint8_t* data);
165
166// PEC Table
167static const uint16_t crc15Table[256] = {0x0,0xc599, 0xceab, 0xb32, 0xd8cf, 0x1d56, 0x1664, 0xd3fd, 0xf407, 0x319e,
@@ -312,6 +312,7 @@
can_parse.h
Parsing of CAN messages using auto-generated structures with bit-fields.
node_defs.h
+
data
u8 data[8]
Definition gs_usb.h:8
spi.h
diff --git a/bootloader_2can_2can__parse_8h_source.html b/bootloader_2can_2can__parse_8h_source.html index 369cd63a..5448b501 100644 --- a/bootloader_2can_2can__parse_8h_source.html +++ b/bootloader_2can_2can__parse_8h_source.html @@ -258,39 +258,39 @@
154typedef union {
155 struct {
156 uint64_t cmd: 8;
-
157 uint64_t data: 32;
+
157 uint64_t data: 32;
158 } main_module_bl_resp;
159 struct {
160 uint64_t cmd: 8;
-
161 uint64_t data: 32;
+
161 uint64_t data: 32;
162 } dashboard_bl_resp;
163 struct {
164 uint64_t cmd: 8;
-
165 uint64_t data: 32;
+
165 uint64_t data: 32;
166 } torquevector_bl_resp;
167 struct {
168 uint64_t cmd: 8;
-
169 uint64_t data: 32;
+
169 uint64_t data: 32;
170 } a_box_bl_resp;
171 struct {
172 uint64_t cmd: 8;
-
173 uint64_t data: 32;
+
173 uint64_t data: 32;
174 } pdu_bl_resp;
175 struct {
176 uint64_t cmd: 8;
-
177 uint64_t data: 32;
+
177 uint64_t data: 32;
178 } l4_testing_bl_resp;
179 struct {
180 uint64_t cmd: 8;
-
181 uint64_t data: 32;
+
181 uint64_t data: 32;
182 } f4_testing_bl_resp;
183 struct {
184 uint64_t cmd: 8;
-
185 uint64_t data: 32;
+
185 uint64_t data: 32;
186 } f7_testing_bl_resp;
187 struct {
188 uint64_t cmd: 8;
-
189 uint64_t data: 32;
+
189 uint64_t data: 32;
190 } daq_bl_resp;
191 struct {
192 uint64_t d0: 8;
@@ -304,42 +304,42 @@
200 } bitstream_data;
201 struct {
202 uint64_t cmd: 8;
-
203 uint64_t data: 32;
+
203 uint64_t data: 32;
204 } main_module_bl_cmd;
205 struct {
206 uint64_t cmd: 8;
-
207 uint64_t data: 32;
+
207 uint64_t data: 32;
208 } dashboard_bl_cmd;
209 struct {
210 uint64_t cmd: 8;
-
211 uint64_t data: 32;
+
211 uint64_t data: 32;
212 } torquevector_bl_cmd;
213 struct {
214 uint64_t cmd: 8;
-
215 uint64_t data: 32;
+
215 uint64_t data: 32;
216 } a_box_bl_cmd;
217 struct {
218 uint64_t cmd: 8;
-
219 uint64_t data: 32;
+
219 uint64_t data: 32;
220 } pdu_bl_cmd;
221 struct {
222 uint64_t cmd: 8;
-
223 uint64_t data: 32;
+
223 uint64_t data: 32;
224 } l4_testing_bl_cmd;
225 struct {
226 uint64_t cmd: 8;
-
227 uint64_t data: 32;
+
227 uint64_t data: 32;
228 } f4_testing_bl_cmd;
229 struct {
230 uint64_t cmd: 8;
-
231 uint64_t data: 32;
+
231 uint64_t data: 32;
232 } f7_testing_bl_cmd;
233 struct {
234 uint64_t cmd: 8;
-
235 uint64_t data: 32;
+
235 uint64_t data: 32;
236 } daq_bl_cmd;
237 uint8_t raw_data[8];
-
238} __attribute__((packed)) CanParsedData_t;
+
238} __attribute__((packed)) CanParsedData_t;
239/* END AUTO MESSAGE STRUCTURE */
240
241// contains most up to date received
@@ -358,39 +358,39 @@
254 } bitstream_data;
255 struct {
256 uint8_t cmd;
-
257 uint32_t data;
+
257 uint32_t data;
258 } main_module_bl_cmd;
259 struct {
260 uint8_t cmd;
-
261 uint32_t data;
+
261 uint32_t data;
262 } dashboard_bl_cmd;
263 struct {
264 uint8_t cmd;
-
265 uint32_t data;
+
265 uint32_t data;
266 } torquevector_bl_cmd;
267 struct {
268 uint8_t cmd;
-
269 uint32_t data;
+
269 uint32_t data;
270 } a_box_bl_cmd;
271 struct {
272 uint8_t cmd;
-
273 uint32_t data;
+
273 uint32_t data;
274 } pdu_bl_cmd;
275 struct {
276 uint8_t cmd;
-
277 uint32_t data;
+
277 uint32_t data;
278 } l4_testing_bl_cmd;
279 struct {
280 uint8_t cmd;
-
281 uint32_t data;
+
281 uint32_t data;
282 } f4_testing_bl_cmd;
283 struct {
284 uint8_t cmd;
-
285 uint32_t data;
+
285 uint32_t data;
286 } f7_testing_bl_cmd;
287 struct {
288 uint8_t cmd;
-
289 uint32_t data;
+
289 uint32_t data;
290 } daq_bl_cmd;
291} can_data_t;
292/* END AUTO CAN DATA STRUCTURE */
@@ -445,8 +445,9 @@
l4_testing_bl_cmd_CALLBACK
void l4_testing_bl_cmd_CALLBACK(CanParsedData_t *msg_data_a)
Definition main.c:484
canTxSendToBack
void canTxSendToBack(CanMsgTypeDef_t *msg)
Definition main.c:116
cmd
uint8_t cmd[NXT_STR_SIZE]
Definition main.c:541
-
__attribute__
struct eeprom __attribute__
Definition daq_hub.h:70
msg
char msg[100]
Definition main.c:105
+
data
u8 data[8]
Definition gs_usb.h:8
+
__attribute__
struct gs_tx_context __attribute__
Definition daq_hub.h:70
can.h
can.h
diff --git a/bootloader_8c.html b/bootloader_8c.html index 9003d45e..e381e348 100644 --- a/bootloader_8c.html +++ b/bootloader_8c.html @@ -133,11 +133,11 @@   void bitstream_data_CALLBACK (CanParsedData_t *msg_data_a)   -void BL_processCommand (BLCmd_t cmd, uint32_t data) +void BL_processCommand (BLCmd_t cmd, uint32_t data)   bool BL_flashStarted (void)   -void BL_sendStatusMessage (uint8_t cmd, uint32_t data) +void BL_sendStatusMessage (uint8_t cmd, uint32_t data)   - + - + diff --git a/bootloader_8h_source.html b/bootloader_8h_source.html index d811ae14..a97e0a5b 100644 --- a/bootloader_8h_source.html +++ b/bootloader_8h_source.html @@ -125,9 +125,9 @@
37
38void BL_checkAndBoot(void);
39
-
40void BL_processCommand(BLCmd_t cmd, uint32_t data);
+
40void BL_processCommand(BLCmd_t cmd, uint32_t data);
41
-
42void BL_sendStatusMessage(uint8_t cmd, uint32_t data);
+
42void BL_sendStatusMessage(uint8_t cmd, uint32_t data);
43
44bool BL_flashStarted(void);
45
@@ -149,6 +149,7 @@
BL_flashStarted
bool BL_flashStarted(void)
Definition bootloader.c:298
BL_checkAndBoot
void BL_checkAndBoot(void)
Definition bootloader.c:99
cmd
uint8_t cmd[NXT_STR_SIZE]
Definition main.c:541
+
data
u8 data[8]
Definition gs_usb.h:8
diff --git a/buffer_8c.html b/buffer_8c.html index 328623da..71a83cad 100644 --- a/buffer_8c.html +++ b/buffer_8c.html @@ -108,7 +108,7 @@
- + diff --git a/buffer_8h.html b/buffer_8h.html index ff4ce894..938cd8b4 100644 --- a/buffer_8h.html +++ b/buffer_8h.html @@ -119,7 +119,7 @@ - + diff --git a/buffer_8h_source.html b/buffer_8h_source.html index 5fc771af..7389fb4c 100644 --- a/buffer_8h_source.html +++ b/buffer_8h_source.html @@ -127,7 +127,7 @@
40void bConstruct(b_handle_t *b, uint32_t item_size, uint32_t buff_size);
41int8_t bGetHeadForWrite(b_handle_t *b, void** tx_loc, uint32_t *contiguous_items);
42int8_t bCommitWrite(b_handle_t *b, uint32_t items_written);
-
43int8_t bSendToBack(b_handle_t *b, const void* data);
+
43int8_t bSendToBack(b_handle_t *b, const void* data);
44int8_t bGetTailForRead(b_handle_t *b, uint8_t t_idx, void** rx_loc, uint32_t *contiguous_items);
45int8_t bCommitRead(b_handle_t *b, uint8_t t_idx, uint32_t items_read);
46uint32_t bGetItemCount(b_handle_t *b, uint8_t t_idx);
@@ -146,6 +146,7 @@
bCommitWrite
int8_t bCommitWrite(b_handle_t *b, uint32_t items_written)
Updates the head by 1 item Call after successful bGetHeadForWrite and AFTER writing your data Note: E...
Definition buffer.c:71
bGetTailForRead
int8_t bGetTailForRead(b_handle_t *b, uint8_t t_idx, void **rx_loc, uint32_t *contiguous_items)
Gets the number of contiguous items available to read at *rx_loc.
Definition buffer.c:188
bActivateTail
void bActivateTail(b_handle_t *b, uint8_t t_idx)
Definition buffer.c:165
+
data
u8 data[8]
Definition gs_usb.h:8
b_handle_t
Definition buffer.h:25
b_handle_t::underflows
uint32_t underflows
Number of times bCommitRead failed.
Definition buffer.h:36
b_handle_t::_max_items
uint32_t _max_items
Maximum number of items that can be stored (only ever max - 1)
Definition buffer.h:33
diff --git a/crc_8c.html b/crc_8c.html index 834dce41..d68609df 100644 --- a/crc_8c.html +++ b/crc_8c.html @@ -104,9 +104,9 @@ - + - +

@@ -351,9 +351,10 @@

Value:
case app_id:\
-
resp_func(cmd, data);\
+
resp_func(cmd, data);\
break;\
cmd
uint8_t cmd[NXT_STR_SIZE]
Definition main.c:541
+
data
u8 data[8]
Definition gs_usb.h:8
diff --git a/bootloader_8h.html b/bootloader_8h.html index 4c7eb459..d713da3e 100644 --- a/bootloader_8h.html +++ b/bootloader_8h.html @@ -126,9 +126,9 @@ Functions

void BL_checkAndBoot (void)
 
void BL_processCommand (BLCmd_t cmd, uint32_t data)
void BL_processCommand (BLCmd_t cmd, uint32_t data)
 
void BL_sendStatusMessage (uint8_t cmd, uint32_t data)
void BL_sendStatusMessage (uint8_t cmd, uint32_t data)
 
bool BL_flashStarted (void)
 
int8_t bCommitWrite (b_handle_t *b, uint32_t items_written)
 Updates the head by 1 item Call after successful bGetHeadForWrite and AFTER writing your data Note: Ensure these calls occur in order (i.e. not preempted by another producer)
 
int8_t bSendToBack (b_handle_t *b, const void *data)
int8_t bSendToBack (b_handle_t *b, const void *data)
 
uint32_t bGetItemCount (b_handle_t *b, uint8_t t_idx)
 Returns number of items left to read for given tail.
int8_t bCommitWrite (b_handle_t *b, uint32_t items_written)
 Updates the head by 1 item Call after successful bGetHeadForWrite and AFTER writing your data Note: Ensure these calls occur in order (i.e. not preempted by another producer)
 
int8_t bSendToBack (b_handle_t *b, const void *data)
int8_t bSendToBack (b_handle_t *b, const void *data)
 
int8_t bGetTailForRead (b_handle_t *b, uint8_t t_idx, void **rx_loc, uint32_t *contiguous_items)
 Gets the number of contiguous items available to read at *rx_loc.
 
void PHAL_CRC32_Init (void)
 
uint32_t PHAL_CRC32_Calculate (uint32_t *data, uint32_t count)
uint32_t PHAL_CRC32_Calculate (uint32_t *data, uint32_t count)
 
uint32_t PHAL_CRC32_CalculateSW (uint32_t *data, uint32_t count)
uint32_t PHAL_CRC32_CalculateSW (uint32_t *data, uint32_t count)
 

Detailed Description

diff --git a/crc_8h.html b/crc_8h.html index 267d4203..ab952a1b 100644 --- a/crc_8h.html +++ b/crc_8h.html @@ -103,9 +103,9 @@ Functions

void PHAL_CRC32_Reset (void)   -uint32_t PHAL_CRC32_Calculate (uint32_t *data, uint32_t count) +uint32_t PHAL_CRC32_Calculate (uint32_t *data, uint32_t count)   -uint32_t PHAL_CRC32_CalculateSW (uint32_t *data, uint32_t count) +uint32_t PHAL_CRC32_CalculateSW (uint32_t *data, uint32_t count)  

Detailed Description

diff --git a/crc_8h_source.html b/crc_8h_source.html index 54637e20..23817896 100644 --- a/crc_8h_source.html +++ b/crc_8h_source.html @@ -107,14 +107,15 @@
24
25void PHAL_CRC32_Reset(void);
26
-
27uint32_t PHAL_CRC32_Calculate(uint32_t *data, uint32_t count);
+
27uint32_t PHAL_CRC32_Calculate(uint32_t *data, uint32_t count);
28
-
29uint32_t PHAL_CRC32_CalculateSW(uint32_t *data, uint32_t count);
+
29uint32_t PHAL_CRC32_CalculateSW(uint32_t *data, uint32_t count);
30
31#endif // _PHAL_CRC_H
PHAL_CRC32_Calculate
uint32_t PHAL_CRC32_Calculate(uint32_t *data, uint32_t count)
Definition crc.c:34
PHAL_CRC32_CalculateSW
uint32_t PHAL_CRC32_CalculateSW(uint32_t *data, uint32_t count)
Definition crc.c:69
PHAL_CRC32_Reset
void PHAL_CRC32_Reset(void)
Definition crc.c:14
+
data
u8 data[8]
Definition gs_usb.h:8
diff --git a/daq_2can_2can__parse_8h_source.html b/daq_2can_2can__parse_8h_source.html index 60d6f1ff..3629f19b 100644 --- a/daq_2can_2can__parse_8h_source.html +++ b/daq_2can_2can__parse_8h_source.html @@ -135,10 +135,10 @@
49typedef union {
50 struct {
51 uint64_t cmd: 8;
-
52 uint64_t data: 32;
+
52 uint64_t data: 32;
53 } daq_bl_cmd;
54 uint8_t raw_data[8];
-
55} __attribute__((packed)) CanParsedData_t;
+
55} __attribute__((packed)) CanParsedData_t;
56/* END AUTO MESSAGE STRUCTURE */
57
58// contains most up to date received
@@ -147,7 +147,7 @@
61typedef struct {
62 struct {
63 uint8_t cmd;
-
64 uint32_t data;
+
64 uint32_t data;
65 } daq_bl_cmd;
66} can_data_t;
67/* END AUTO CAN DATA STRUCTURE */
@@ -184,7 +184,8 @@
send_fault
void send_fault(uint16_t id, bool latched)
daq_bl_cmd_CALLBACK
void daq_bl_cmd_CALLBACK(CanParsedData_t *msg_data_a)
cmd
uint8_t cmd[NXT_STR_SIZE]
Definition main.c:541
-
__attribute__
struct eeprom __attribute__
Definition daq_hub.h:70
+
data
u8 data[8]
Definition gs_usb.h:8
+
__attribute__
struct gs_tx_context __attribute__
Definition daq_hub.h:70
can.h
diff --git a/daq_2main_8c.html b/daq_2main_8c.html index d2e29e10..d950d105 100644 --- a/daq_2main_8c.html +++ b/daq_2main_8c.html @@ -129,8 +129,6 @@   void CAN1_RX0_IRQHandler ()   -void CAN2_RX0_IRQHandler () -  void CAN1_SCE_IRQHandler ()   void HardFault_Handler () @@ -140,9 +138,9 @@ Variables GPIOInitConfig_t gpio_config []   -dma_init_t spi_rx_dma_config = SPI2_RXDMA_CONT_CONFIG(NULL, 2) +dma_init_t spi_rx_dma_config = SPI1_RXDMA_CONT_CONFIG(NULL, 2)   -dma_init_t spi_tx_dma_config = SPI2_TXDMA_CONT_CONFIG(NULL, 1) +dma_init_t spi_tx_dma_config = SPI1_TXDMA_CONT_CONFIG(NULL, 1)   SPI_InitConfig_t eth_spi_config   @@ -160,8 +158,16 @@   volatile uint32_t tick_ms   +dma_init_t usart_tx_dma_config = USART6_TXDMA_CONT_CONFIG(NULL, 1) +  +dma_init_t usart_rx_dma_config = USART6_RXDMA_CONT_CONFIG(NULL, 2) +  +usart_init_t lte_usart_config +  q_handle_t q_tx_can2_to_can1   +q_handle_t q_rx_can_uds +  volatile timestamped_frame_t rx_buffer [RX_BUFF_ITEM_COUNT]   b_tail_t tails [RX_TAIL_COUNT] @@ -225,23 +231,6 @@

- - - -

◆ CAN2_RX0_IRQHandler()

- -
-
- - - - - - - -
void CAN2_RX0_IRQHandler ()
-
-
@@ -479,19 +468,18 @@

Initial value:
= {
-
.data_rate = 42000000 / 2,
.data_len = 8,
.nss_sw = false,
.nss_gpio_port = ETH_CS_PORT,
.nss_gpio_pin = ETH_CS_PIN,
.rx_dma_cfg = &spi_rx_dma_config,
.tx_dma_cfg = &spi_tx_dma_config,
-
.periph = SPI2
+
.periph = SPI1,
}
spi_rx_dma_config
dma_init_t spi_rx_dma_config
Definition main.c:47
spi_tx_dma_config
dma_init_t spi_tx_dma_config
Definition main.c:48
-
ETH_CS_PORT
#define ETH_CS_PORT
Definition main.h:82
-
ETH_CS_PIN
#define ETH_CS_PIN
Definition main.h:83
+
ETH_CS_PORT
#define ETH_CS_PORT
Definition main.h:75
+
ETH_CS_PIN
#define ETH_CS_PIN
Definition main.h:76
dma_init_t::periph
DMA_TypeDef * periph
Definition dma.h:45
@@ -508,6 +496,42 @@

+ + + +

◆ lte_usart_config

+ +
+
+ + + + +
usart_init_t lte_usart_config
+
+Initial value:
= {
+
.baud_rate = 115200,
+
.word_length = WORD_8,
+
.stop_bits = SB_ONE,
+
.parity = PT_NONE,
+
.hw_flow_ctl = HW_DISABLE,
+
.ovsample = OV_16,
+
.obsample = OB_DISABLE,
+
.periph = USART6,
+
.wake_addr = false,
+
.usart_active_num = USART6_ACTIVE_IDX,
+
.tx_dma_cfg = &usart_tx_dma_config,
+
.rx_dma_cfg = &usart_rx_dma_config
+
}
+
usart_tx_dma_config
dma_init_t usart_tx_dma_config
Definition main.c:123
+
usart_rx_dma_config
dma_init_t usart_rx_dma_config
Definition main.c:124
+
WORD_8
@ WORD_8
Definition usart.h:36
+
HW_DISABLE
@ HW_DISABLE
Definition usart.h:58
+
OB_DISABLE
@ OB_DISABLE
Definition usart.h:72
+
PT_NONE
@ PT_NONE
Definition usart.h:29
+
SB_ONE
@ SB_ONE
Definition usart.h:43
+
OV_16
@ OV_16
Definition usart.h:66
+
@@ -530,6 +554,20 @@

+ + + +

◆ q_rx_can_uds

+ +
+
+ + + + +
q_handle_t q_rx_can_uds
+
+
@@ -567,7 +605,7 @@

- +
dma_init_t spi_rx_dma_config = SPI2_RXDMA_CONT_CONFIG(NULL, 2)dma_init_t spi_rx_dma_config = SPI1_RXDMA_CONT_CONFIG(NULL, 2)
@@ -581,7 +619,7 @@

- +
dma_init_t spi_tx_dma_config = SPI2_TXDMA_CONT_CONFIG(NULL, 1)dma_init_t spi_tx_dma_config = SPI1_TXDMA_CONT_CONFIG(NULL, 1)

@@ -599,7 +637,7 @@

-Initial value:
=
+Initial value:
=
{
.date = {.month_bcd=RTC_MONTH_FEBRUARY,
.weekday=RTC_WEEKDAY_TUESDAY,
@@ -670,6 +708,34 @@

+

+
+ +

◆ usart_rx_dma_config

+ +
+
+ + + + +
dma_init_t usart_rx_dma_config = USART6_RXDMA_CONT_CONFIG(NULL, 2)
+
+ +
+
+ +

◆ usart_tx_dma_config

+ +
+
+ + + + +
dma_init_t usart_tx_dma_config = USART6_TXDMA_CONT_CONFIG(NULL, 1)
+
+
diff --git a/daq_2main_8h.html b/daq_2main_8h.html index 97be88a1..bb773c9b 100644 --- a/daq_2main_8h.html +++ b/daq_2main_8h.html @@ -96,57 +96,27 @@
main.h File Reference
-
#include "log.h"
-#include "common/queue/queue.h"
+
#include "common/queue/queue.h"
#include "buffer.h"
+#include "common/log/log.h"

Go to the source code of this file.

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - + - + - + - + - + @@ -160,25 +130,45 @@ - + - + - + - + - + + + + + + + + + + + + + - + + + + + + + + + - + @@ -214,146 +204,148 @@ + +

Macros

#define EN_CAN2   1
 
#define ID_LWS_STANDARD   0x2b0
 
#define RED   14
 
#define BLUE   15
 
#define GREEN   12
 
#define ORANGE   13
 
#define RED_LED_PORT   GPIOD
 
#define RED_LED_PIN   RED
 
#define BLUE_LED_PORT   GPIOD
 
#define BLUE_LED_PIN   BLUE
 
#define GREEN_LED_PORT   GPIOD
 
#define GREEN_LED_PIN   GREEN
 
#define ORANGE_LED_PORT   GPIOD
 
#define ORANGE_LED_PIN   ORANGE
 
#define USER_BTN_PORT   GPIOA
 
#define USER_BTN_PIN   0
 
#define HEARTBEAT_LED_PORT   GPIOA
#define HEARTBEAT_LED_PORT   GPIOD
 
#define HEARTBEAT_LED_PIN   0
#define HEARTBEAT_LED_PIN   13
 
#define CONNECTION_LED_PORT   GPIOA
#define CONNECTION_LED_PORT   GPIOD
 
#define CONNECTION_LED_PIN   1
#define CONNECTION_LED_PIN   14
 
#define ERROR_LED_PORT   GPIOA
#define ERROR_LED_PORT   GPIOD
 
#define ERROR_LED_PIN   4
#define ERROR_LED_PIN   15
 
#define SD_ACTIVITY_LED_PORT   GPIOA
 
 
#define SD_DETECT_LED_PIN   10
 
#define SD_CD_PORT   GPIOC
#define SD_CD_PORT   GPIOD
 
#define SD_CD_PIN   6
#define SD_CD_PIN   4
 
#define ETH_CS_PORT   GPIOB
#define ETH_CS_PORT   GPIOA
 
#define ETH_CS_PIN   12
#define ETH_CS_PIN   4
 
#define ETH_RST_PORT   GPIOB
#define ETH_SCK_PORT   GPIOA
 
#define ETH_SCK_PIN   5
 
#define ETH_MISO_PORT   GPIOA
 
#define ETH_MISO_PIN   6
 
#define ETH_MOSI_PORT   GPIOA
 
#define ETH_MOSI_PIN   7
 
#define ETH_RST_PORT   GPIOE
 
#define ETH_RST_PIN   11
#define ETH_RST_PIN   3
 
#define LTE_UART_TX_PORT   GPIOC
 
#define LTE_UART_TX_PIN   6
 
#define LTE_UART_RX_PORT   GPIOC
 
#define LTE_UART_RX_PIN   7
 
#define PWR_LOSS_PORT   GPIOE
 
#define PWR_LOSS_PIN   15
 
#define LOG_ENABLE_PORT   GPIOC
 
#define LOG_ENABLE_PIN   7
#define LOG_ENABLE_PIN   15
 
#define PER   1
 
 
q_handle_t q_tx_can2_to_can1
 
q_handle_t q_rx_can_uds
 
b_handle_t b_rx_can
 
b_handle_t b_rx_tcp
 

Macro Definition Documentation

- -

◆ BLUE

+ +

◆ CONNECTION_LED_PIN

- +
#define BLUE   15#define CONNECTION_LED_PIN   14
- -

◆ BLUE_LED_PIN

+ +

◆ CONNECTION_LED_PORT

- +
#define BLUE_LED_PIN   BLUE#define CONNECTION_LED_PORT   GPIOD
- -

◆ BLUE_LED_PORT

+ +

◆ ERROR_LED_PIN

- +
#define BLUE_LED_PORT   GPIOD#define ERROR_LED_PIN   15
- -

◆ CONNECTION_LED_PIN

+ +

◆ ERROR_LED_PORT

- +
#define CONNECTION_LED_PIN   1#define ERROR_LED_PORT   GPIOD
- -

◆ CONNECTION_LED_PORT

+ +

◆ ETH_CS_PIN

- +
#define CONNECTION_LED_PORT   GPIOA#define ETH_CS_PIN   4
- -

◆ EN_CAN2

+ +

◆ ETH_CS_PORT

- +
#define EN_CAN2   1#define ETH_CS_PORT   GPIOA
- -

◆ ERROR_LED_PIN

+ +

◆ ETH_MISO_PIN

- +
#define ERROR_LED_PIN   4#define ETH_MISO_PIN   6
- -

◆ ERROR_LED_PORT

+ +

◆ ETH_MISO_PORT

- +
#define ERROR_LED_PORT   GPIOA#define ETH_MISO_PORT   GPIOA
- -

◆ ETH_CS_PIN

+ +

◆ ETH_MOSI_PIN

- +
#define ETH_CS_PIN   12#define ETH_MOSI_PIN   7
- -

◆ ETH_CS_PORT

+ +

◆ ETH_MOSI_PORT

- +
#define ETH_CS_PORT   GPIOB#define ETH_MOSI_PORT   GPIOA
@@ -367,7 +359,7 @@

- +
#define ETH_RST_PIN   11#define ETH_RST_PIN   3

@@ -381,63 +373,49 @@

- +
#define ETH_RST_PORT   GPIOB#define ETH_RST_PORT   GPIOE

- -

◆ GREAT

+ +

◆ ETH_SCK_PIN

- +
#define GREAT   PER#define ETH_SCK_PIN   5
- -

◆ GREEN

+ +

◆ ETH_SCK_PORT

- +
#define GREEN   12#define ETH_SCK_PORT   GPIOA
- -

◆ GREEN_LED_PIN

- -
-
- - - - -
#define GREEN_LED_PIN   GREEN
-
- -
-
- -

◆ GREEN_LED_PORT

+ +

◆ GREAT

- +
#define GREEN_LED_PORT   GPIOD#define GREAT   PER
@@ -451,7 +429,7 @@

- +
#define HEARTBEAT_LED_PIN   0#define HEARTBEAT_LED_PIN   13

@@ -465,7 +443,7 @@

- +
#define HEARTBEAT_LED_PORT   GPIOA#define HEARTBEAT_LED_PORT   GPIOD

@@ -493,7 +471,7 @@

- +
#define LOG_ENABLE_PIN   7#define LOG_ENABLE_PIN   15

@@ -514,126 +492,98 @@

-

◆ ORANGE

- -
-
- - - - -
#define ORANGE   13
-
- -
-
- -

◆ ORANGE_LED_PIN

- -
-
- - - - -
#define ORANGE_LED_PIN   ORANGE
-
- -
-
- -

◆ ORANGE_LED_PORT

+ +

◆ LTE_UART_RX_PIN

- +
#define ORANGE_LED_PORT   GPIOD#define LTE_UART_RX_PIN   7
- -

◆ PER

+ +

◆ LTE_UART_RX_PORT

- +
#define PER   1#define LTE_UART_RX_PORT   GPIOC
- -

◆ PWR_LOSS_PIN

+ +

◆ LTE_UART_TX_PIN

- +
#define PWR_LOSS_PIN   15#define LTE_UART_TX_PIN   6
- -

◆ PWR_LOSS_PORT

+ +

◆ LTE_UART_TX_PORT

- +
#define PWR_LOSS_PORT   GPIOE#define LTE_UART_TX_PORT   GPIOC
- -

◆ RED

+ +

◆ PER

- +
#define RED   14#define PER   1
- -

◆ RED_LED_PIN

+ +

◆ PWR_LOSS_PIN

- +
#define RED_LED_PIN   RED#define PWR_LOSS_PIN   15
- -

◆ RED_LED_PORT

+ +

◆ PWR_LOSS_PORT

- +
#define RED_LED_PORT   GPIOD#define PWR_LOSS_PORT   GPIOE
@@ -675,7 +625,7 @@

- +
#define SD_CD_PIN   6#define SD_CD_PIN   4

@@ -689,7 +639,7 @@

- +
#define SD_CD_PORT   GPIOC#define SD_CD_PORT   GPIOD

@@ -750,34 +700,6 @@

-

-
- -

◆ USER_BTN_PIN

- -
-
- - - - -
#define USER_BTN_PIN   0
-
- -
-
- -

◆ USER_BTN_PORT

- -
-
- - - - -
#define USER_BTN_PORT   GPIOA
-
-

Enumeration Type Documentation

@@ -894,6 +816,28 @@

+

+
+ +

◆ q_rx_can_uds

+ +
+
+ + + + + +
+ + + + +
q_handle_t q_rx_can_uds
+ 		+extern
+
+
diff --git a/daq_2main_8h_source.html b/daq_2main_8h_source.html index 503bc413..45f8691c 100644 --- a/daq_2main_8h_source.html +++ b/daq_2main_8h_source.html @@ -95,7 +95,7 @@
2#define _MAIN_H_
3
4// Enable the CAN2 bus
-
5#define EN_CAN2 1
+
5//#define EN_CAN2 1
6#define ID_LWS_STANDARD 0x2b0 // hehe
7
@@ -116,89 +116,94 @@
20} tcp_rx_tail_t;
21
-
22// #define DEBUG_LOG
-
23#include "log.h"
-
24#include "common/queue/queue.h"
-
25#include "buffer.h"
-
26
-
27#ifdef DEBUG_LOG
-
28// int _write(int handle, char* data, int size);
-
29void _log_str(char* data);
-
30#endif
-
31
-
32// #define DISCO_BOARD
-
33
-
34// DISCO
-
35#define RED 14
-
36#define BLUE 15
-
37#define GREEN 12
-
38#define ORANGE 13
-
39
-
40#define RED_LED_PORT GPIOD
-
41#define RED_LED_PIN RED
-
42#define BLUE_LED_PORT GPIOD
-
43#define BLUE_LED_PIN BLUE
-
44#define GREEN_LED_PORT GPIOD
-
45#define GREEN_LED_PIN GREEN
-
46#define ORANGE_LED_PORT GPIOD
-
47#define ORANGE_LED_PIN ORANGE
-
48#define USER_BTN_PORT GPIOA
-
49#define USER_BTN_PIN 0
-
50
-
51// Status LEDs
-
52#ifdef DISCO_BOARD
-
53#define HEARTBEAT_LED_PORT BLUE_LED_PORT
-
54#define HEARTBEAT_LED_PIN BLUE_LED_PIN
-
55#define CONNECTION_LED_PORT ORANGE_LED_PORT
-
56#define CONNECTION_LED_PIN ORANGE_LED_PIN
-
57#define ERROR_LED_PORT RED_LED_PORT
-
58#define ERROR_LED_PIN RED_LED_PIN
-
59#define SD_ACTIVITY_LED_PORT GREEN_LED_PORT
-
60#define SD_ACTIVITY_LED_PIN GREEN_LED_PIN
-
61#define SD_ERROR_LED_PORT RED_LED_PORT
-
62#define SD_ERROR_LED_PIN RED_LED_PIN
-
63#else
-
64#define HEARTBEAT_LED_PORT GPIOA
-
65#define HEARTBEAT_LED_PIN 0
-
66#define CONNECTION_LED_PORT GPIOA
-
67#define CONNECTION_LED_PIN 1
-
68#define ERROR_LED_PORT GPIOA
-
69#define ERROR_LED_PIN 4
-
70#define SD_ACTIVITY_LED_PORT GPIOA
-
71#define SD_ACTIVITY_LED_PIN 9
-
72#define SD_ERROR_LED_PORT GPIOA
-
73#define SD_ERROR_LED_PIN 8
-
74#endif
-
75
-
76// TODO: SD Detect LED
-
77#define SD_DETECT_LED_PORT GPIOA
-
78#define SD_DETECT_LED_PIN 10
-
79#define SD_CD_PORT GPIOC
-
80#define SD_CD_PIN 6
-
81
-
82#define ETH_CS_PORT GPIOB
-
83#define ETH_CS_PIN 12
-
84#define ETH_RST_PORT GPIOB
-
85#define ETH_RST_PIN 11
-
86
-
87#define PWR_LOSS_PORT GPIOE
-
88#define PWR_LOSS_PIN 15
-
89
-
90
-
91#define LOG_ENABLE_PORT GPIOC
-
92#define LOG_ENABLE_PIN 7
-
93
-
94#define PER 1
-
95#define GREAT PER
-
96
-
97extern volatile uint32_t tick_ms; // Systick 1ms counter
-
98extern q_handle_t q_tx_can2_to_can1;
-
99extern b_handle_t b_rx_can;
-
100extern b_handle_t b_rx_tcp;
-
101
-
102extern void HardFault_Handler();
-
103
-
104#endif
+
22#include "common/queue/queue.h"
+
23#include "buffer.h"
+
24#include "common/log/log.h"
+
25
+
26// #define DISCO_BOARD
+
27// Status LEDs
+
28#ifdef DISCO_BOARD
+
29
+
30#define RED 14
+
31#define BLUE 15
+
32#define GREEN 12
+
33#define ORANGE 13
+
34
+
35#define RED_LED_PORT GPIOD
+
36#define RED_LED_PIN RED
+
37#define BLUE_LED_PORT GPIOD
+
38#define BLUE_LED_PIN BLUE
+
39#define GREEN_LED_PORT GPIOD
+
40#define GREEN_LED_PIN GREEN
+
41#define ORANGE_LED_PORT GPIOD
+
42#define ORANGE_LED_PIN ORANGE
+
43#define USER_BTN_PORT GPIOA
+
44#define USER_BTN_PIN 0
+
45
+
46#define HEARTBEAT_LED_PORT BLUE_LED_PORT
+
47#define HEARTBEAT_LED_PIN BLUE_LED_PIN
+
48#define CONNECTION_LED_PORT ORANGE_LED_PORT
+
49#define CONNECTION_LED_PIN ORANGE_LED_PIN
+
50#define ERROR_LED_PORT RED_LED_PORT
+
51#define ERROR_LED_PIN RED_LED_PIN
+
52#define SD_ACTIVITY_LED_PORT GREEN_LED_PORT
+
53#define SD_ACTIVITY_LED_PIN GREEN_LED_PIN
+
54#define SD_ERROR_LED_PORT RED_LED_PORT
+
55#define SD_ERROR_LED_PIN RED_LED_PIN
+
56#else
+
57#define HEARTBEAT_LED_PORT GPIOD
+
58#define HEARTBEAT_LED_PIN 13
+
59#define CONNECTION_LED_PORT GPIOD
+
60#define CONNECTION_LED_PIN 14
+
61#define ERROR_LED_PORT GPIOD
+
62#define ERROR_LED_PIN 15
+
63#define SD_ACTIVITY_LED_PORT GPIOA
+
64#define SD_ACTIVITY_LED_PIN 9
+
65#define SD_ERROR_LED_PORT GPIOA
+
66#define SD_ERROR_LED_PIN 8
+
67#endif
+
68
+
69#define SD_DETECT_LED_PORT GPIOA
+
70#define SD_DETECT_LED_PIN 10
+
71#define SD_CD_PORT GPIOD
+
72#define SD_CD_PIN 4
+
73
+
74// W5500 ETH SPI1
+
75#define ETH_CS_PORT GPIOA
+
76#define ETH_CS_PIN 4
+
77#define ETH_SCK_PORT GPIOA
+
78#define ETH_SCK_PIN 5
+
79#define ETH_MISO_PORT GPIOA
+
80#define ETH_MISO_PIN 6
+
81#define ETH_MOSI_PORT GPIOA
+
82#define ETH_MOSI_PIN 7
+
83#define ETH_RST_PORT GPIOE
+
84#define ETH_RST_PIN 3
+
85
+
86// LTE USART6
+
87#define LTE_UART_TX_PORT GPIOC
+
88#define LTE_UART_TX_PIN 6
+
89#define LTE_UART_RX_PORT GPIOC
+
90#define LTE_UART_RX_PIN 7
+
91
+
92#define PWR_LOSS_PORT GPIOE
+
93#define PWR_LOSS_PIN 15
+
94
+
95#define LOG_ENABLE_PORT GPIOC
+
96#define LOG_ENABLE_PIN 15
+
97
+
98#define PER 1
+
99#define GREAT PER
+
100
+
101extern volatile uint32_t tick_ms; // Systick 1ms counter
+
102extern q_handle_t q_tx_can2_to_can1;
+
103extern q_handle_t q_rx_can_uds;
+
104extern b_handle_t b_rx_can;
+
105extern b_handle_t b_rx_tcp;
+
106
+
107extern void HardFault_Handler();
+
108
+
109#endif
buffer.h
Buffer for one producer, multiple consumers.
HardFault_Handler
void HardFault_Handler()
Definition main.c:211
tcp_rx_tail_t
tcp_rx_tail_t
Definition main.h:16
@@ -206,9 +211,10 @@
TCP_RX_TAIL_SD
@ TCP_RX_TAIL_SD
Definition main.h:18
TCP_RX_TAIL_CAN_TX
@ TCP_RX_TAIL_CAN_TX
Definition main.h:17
b_rx_can
b_handle_t b_rx_can
Definition test_buffer.c:22
+
q_rx_can_uds
q_handle_t q_rx_can_uds
Definition main.c:151
b_rx_tcp
b_handle_t b_rx_tcp
Definition main.c:163
-
q_tx_can2_to_can1
q_handle_t q_tx_can2_to_can1
Definition main.c:151
-
tick_ms
volatile uint32_t tick_ms
Definition main.c:102
+
q_tx_can2_to_can1
q_handle_t q_tx_can2_to_can1
Definition main.c:150
+
tick_ms
volatile uint32_t tick_ms
Definition main.c:121
rx_tail_t
rx_tail_t
Definition main.h:8
RX_TAIL_USB
@ RX_TAIL_USB
USB Send.
Definition main.h:12
RX_TAIL_CAN_RX
@ RX_TAIL_CAN_RX
CAN rx message parsing.
Definition main.h:9
diff --git a/daq__hub_8c.html b/daq__hub_8c.html index 9a3e8c08..0aedde6b 100644 --- a/daq__hub_8c.html +++ b/daq__hub_8c.html @@ -90,6 +90,7 @@
Classes | +Macros | Functions | Variables
daq_hub.c File Reference
@@ -115,6 +116,21 @@ struct  eth_config_t   + + + + + + + + + + + + + +

+Macros

#define DAQ_BL_CMD_RST   0x05
 
#define DAQ_BL_CMD_NTP_DATE   0x10
 
#define DAQ_BL_CMD_NTP_TIME   0x11
 
#define DAQ_BL_CMD_NTP_GET   0x12
 
#define DAQ_BL_CMD_LOG_ENABLE   0x20
 
#define DAQ_BL_CMD_LOG_STATUS   0x21
 
@@ -146,7 +162,92 @@
Version
0.1
Date
2024-02-08
Copyright
Copyright (c) 2024
-

Function Documentation

+

Macro Definition Documentation

+ +

◆ DAQ_BL_CMD_LOG_ENABLE

+ +
+
+

Functions

void daq_init (void)
+ + + +
#define DAQ_BL_CMD_LOG_ENABLE   0x20
+
+ +
+
+ +

◆ DAQ_BL_CMD_LOG_STATUS

+ +
+
+ + + + +
#define DAQ_BL_CMD_LOG_STATUS   0x21
+
+ +
+
+ +

◆ DAQ_BL_CMD_NTP_DATE

+ +
+
+ + + + +
#define DAQ_BL_CMD_NTP_DATE   0x10
+
+ +
+
+ +

◆ DAQ_BL_CMD_NTP_GET

+ +
+
+ + + + +
#define DAQ_BL_CMD_NTP_GET   0x12
+
+ +
+
+ +

◆ DAQ_BL_CMD_NTP_TIME

+ +
+
+ + + + +
#define DAQ_BL_CMD_NTP_TIME   0x11
+
+ +
+
+ +

◆ DAQ_BL_CMD_RST

+ +
+
+ + + + +
#define DAQ_BL_CMD_RST   0x05
+
+ +
+
+

Function Documentation

◆ daq_init()

diff --git a/daq__hub_8h.html b/daq__hub_8h.html index 9a74bb05..3494dacf 100644 --- a/daq__hub_8h.html +++ b/daq__hub_8h.html @@ -123,7 +123,7 @@   #define CAN_EFF_MASK   0x1FFFFFFFU /* extended frame format (EFF) */   -#define CAN_ERR_MASK   0x1FFFFFFFU /* omit EFF, RTR, ERR flags */ +#define CAN_ERR_MASK   0x1FFFFFFFU /* omit EFF, RTR, ERR flags */   #define BUS_ID_CAN1   0   @@ -319,7 +319,7 @@

- +
#define CAN_ERR_MASK   0x1FFFFFFFU /* omit EFF, RTR, ERR flags */#define CAN_ERR_MASK   0x1FFFFFFFU /* omit EFF, RTR, ERR flags */

diff --git a/daq__hub_8h_source.html b/daq__hub_8h_source.html index d45f53d5..357d5628 100644 --- a/daq__hub_8h_source.html +++ b/daq__hub_8h_source.html @@ -138,7 +138,7 @@
56 busid_t bus_id;
57 uint8_t dlc;
58 uint8_t data[8];
-
59} timestamped_frame_t;
+
59} timestamped_frame_t;
60
@@ -271,22 +271,23 @@
175 uint32_t last_write_ms;
176 bool log_enable_sw;
177 bool log_enable_tcp;
-
178 // General
-
179 uint32_t loop_time_max_ms;
-
180 uint32_t loop_time_avg_ms;
-
181 // FTP
-
182 bool ftp_busy;
-
183} daq_hub_t;
+
178 bool log_enable_uds;
+
179 // General
+
180 uint32_t loop_time_max_ms;
+
181 uint32_t loop_time_avg_ms;
+
182 // FTP
+
183 bool ftp_busy;
+
184} daq_hub_t;
-
184extern daq_hub_t dh;
-
185
-
186void daq_init(void);
-
187void daq_loop(void);
-
188bool daq_request_sd_mount(void);
-
189
-
190#endif
-
tick_ms
volatile uint32_t tick_ms
Definition main.c:102
-
daq_init
void daq_init(void)
Definition daq_hub.c:77
+
185extern daq_hub_t dh;
+
186
+
187void daq_init(void);
+
188void daq_loop(void);
+
189bool daq_request_sd_mount(void);
+
190
+
191#endif
+
tick_ms
volatile uint32_t tick_ms
Definition main.c:121
+
daq_init
void daq_init(void)
Definition daq_hub.c:79
tcp_time_frame_t
tcp_time_frame_t
Definition daq_hub.h:88
dh
daq_hub_t dh
Definition daq_hub.c:55
sd_error_t
sd_error_t
Definition daq_hub.h:100
@@ -310,7 +311,7 @@
ETH_ERROR_UDP_SOCK
@ ETH_ERROR_UDP_SOCK
Definition daq_hub.h:130
ETH_ERROR_VERS
@ ETH_ERROR_VERS
Definition daq_hub.h:129
timestamped_frame_t
timestamped_frame_t
Definition daq_hub.h:59
-
daq_loop
void daq_loop(void)
Definition daq_hub.c:108
+
daq_loop
void daq_loop(void)
Definition daq_hub.c:111
eth_tcp_state_t
eth_tcp_state_t
Definition daq_hub.h:118
ETH_TCP_ESTABLISHED
@ ETH_TCP_ESTABLISHED
Definition daq_hub.h:121
ETH_TCP_IDLE
@ ETH_TCP_IDLE
Definition daq_hub.h:119
@@ -321,7 +322,7 @@
TCP_CMD_START_LOG
@ TCP_CMD_START_LOG
Definition daq_hub.h:64
TCP_CMD_CAN_FRAME
@ TCP_CMD_CAN_FRAME
Definition daq_hub.h:63
TCP_CMD_SYNC_TIME
@ TCP_CMD_SYNC_TIME
Definition daq_hub.h:66
-
daq_request_sd_mount
bool daq_request_sd_mount(void)
Definition daq_hub.c:238
+
daq_request_sd_mount
bool daq_request_sd_mount(void)
Definition daq_hub.c:242
tcp_can_frame_t
tcp_can_frame_t
Definition daq_hub.h:76
sd_state_t
sd_state_t
Definition daq_hub.h:91
SD_FILE_CREATED
@ SD_FILE_CREATED
Definition daq_hub.h:94
@@ -346,17 +347,18 @@
daq_hub_t::eth_enable_udp_broadcast
bool eth_enable_udp_broadcast
Definition daq_hub.h:159
daq_hub_t::eth_tcp_last_rx_ms
uint32_t eth_tcp_last_rx_ms
Definition daq_hub.h:165
daq_hub_t::eth_last_err
eth_error_t eth_last_err
Definition daq_hub.h:163
+
daq_hub_t::log_enable_uds
bool log_enable_uds
Definition daq_hub.h:178
daq_hub_t::log_enable_tcp
bool log_enable_tcp
Definition daq_hub.h:177
daq_hub_t::sd_last_err
sd_error_t sd_last_err
Definition daq_hub.h:171
-
daq_hub_t::loop_time_max_ms
uint32_t loop_time_max_ms
Definition daq_hub.h:179
+
daq_hub_t::loop_time_max_ms
uint32_t loop_time_max_ms
Definition daq_hub.h:180
daq_hub_t::fat_fs
FATFS fat_fs
Definition daq_hub.h:168
daq_hub_t::sd_error_ct
uint32_t sd_error_ct
Definition daq_hub.h:170
daq_hub_t::log_fp
FIL log_fp
Definition daq_hub.h:173
-
daq_hub_t::ftp_busy
bool ftp_busy
Definition daq_hub.h:182
+
daq_hub_t::ftp_busy
bool ftp_busy
Definition daq_hub.h:183
daq_hub_t::sd_last_err_res
FRESULT sd_last_err_res
Definition daq_hub.h:172
daq_hub_t::eth_error_ct
uint32_t eth_error_ct
Definition daq_hub.h:161
daq_hub_t::last_write_ms
uint32_t last_write_ms
Definition daq_hub.h:175
-
daq_hub_t::loop_time_avg_ms
uint32_t loop_time_avg_ms
Definition daq_hub.h:180
+
daq_hub_t::loop_time_avg_ms
uint32_t loop_time_avg_ms
Definition daq_hub.h:181
daq_hub_t::eth_tcp_state
eth_tcp_state_t eth_tcp_state
Definition daq_hub.h:164
busid_t
uint8_t busid_t
Definition test_buffer.c:7
canid_t
uint32_t canid_t
Definition test_buffer.c:6
diff --git a/dashboard_2can_2can__parse_8h_source.html b/dashboard_2can_2can__parse_8h_source.html index 363f3e27..7072592b 100644 --- a/dashboard_2can_2can__parse_8h_source.html +++ b/dashboard_2can_2can__parse_8h_source.html @@ -435,7 +435,7 @@
321 uint64_t is_charging: 1;
322 uint64_t multi_input_2: 1;
323 uint64_t multi_input_3: 1;
-
324 uint64_t reserved: 1;
+
324 uint64_t reserved: 1;
325 uint64_t multi_output_2: 1;
326 uint64_t multi_output_3: 1;
327 uint64_t multi_output_4: 1;
@@ -459,9 +459,9 @@
345 uint64_t min_cellv_low: 1;
346 uint64_t pack_overheat: 1;
347 uint64_t reserved0: 1;
-
348 uint64_t reserved1: 1;
-
349 uint64_t reserved2: 1;
-
350 uint64_t reserved3: 1;
+
348 uint64_t reserved1: 1;
+
349 uint64_t reserved2: 1;
+
350 uint64_t reserved3: 1;
351 uint64_t reserved4: 1;
352 uint64_t reserved5: 1;
353 uint64_t reserved6: 1;
@@ -521,7 +521,7 @@
407 } gearbox;
408 struct {
409 uint64_t cmd: 8;
-
410 uint64_t data: 32;
+
410 uint64_t data: 32;
411 } dashboard_bl_cmd;
412 struct {
413 uint64_t IMD: 1;
@@ -577,7 +577,7 @@
463 uint64_t daq_command: 64;
464 } daq_command_DASHBOARD;
465 uint8_t raw_data[8];
-
466} __attribute__((packed)) CanParsedData_t;
+
466} __attribute__((packed)) CanParsedData_t;
467/* END AUTO MESSAGE STRUCTURE */
468
469// contains most up to date received
@@ -608,7 +608,7 @@
494 uint8_t is_charging;
495 uint8_t multi_input_2;
496 uint8_t multi_input_3;
-
497 uint8_t reserved;
+
497 uint8_t reserved;
498 uint8_t multi_output_2;
499 uint8_t multi_output_3;
500 uint8_t multi_output_4;
@@ -636,9 +636,9 @@
522 uint8_t min_cellv_low;
523 uint8_t pack_overheat;
524 uint8_t reserved0;
-
525 uint8_t reserved1;
-
526 uint8_t reserved2;
-
527 uint8_t reserved3;
+
525 uint8_t reserved1;
+
526 uint8_t reserved2;
+
527 uint8_t reserved3;
528 uint8_t reserved4;
529 uint8_t reserved5;
530 uint8_t reserved6;
@@ -714,7 +714,7 @@
600 } gearbox;
601 struct {
602 uint8_t cmd;
-
603 uint32_t data;
+
603 uint32_t data;
604 } dashboard_bl_cmd;
605 struct {
606 uint8_t IMD;
@@ -826,7 +826,12 @@
CAR_STATE_CONSTANT_TORQUE
@ CAR_STATE_CONSTANT_TORQUE
Definition can_parse.h:240
daq_command_DASHBOARD_CALLBACK
void daq_command_DASHBOARD_CALLBACK(CanMsgTypeDef_t *msg_header_a)
Definition daq.c:44
cmd
uint8_t cmd[NXT_STR_SIZE]
Definition main.c:541
-
__attribute__
struct eeprom __attribute__
Definition daq_hub.h:70
+
data
u8 data[8]
Definition gs_usb.h:8
+
reserved2
u8 reserved2
Definition gs_usb.h:1
+
reserved3
u8 reserved3
Definition gs_usb.h:2
+
reserved1
u8 reserved1
Definition gs_usb.h:0
+
reserved
u8 reserved
Definition gs_usb.h:6
+
__attribute__
struct gs_tx_context __attribute__
Definition daq_hub.h:70
charge_enable
uint8_t charge_enable
Definition main.c:102
can.h
diff --git a/dashboard_2main_8c.html b/dashboard_2main_8c.html index fc8d549a..76a2fab7 100644 --- a/dashboard_2main_8c.html +++ b/dashboard_2main_8c.html @@ -789,11 +789,11 @@

.periph = USART1,
.wake_addr = false,
.usart_active_num = USART1_ACTIVE_IDX,
-
.tx_dma_cfg = &usart_tx_dma_config,
-
.rx_dma_cfg = &usart_rx_dma_config
+
.tx_dma_cfg = &usart_tx_dma_config,
+
.rx_dma_cfg = &usart_rx_dma_config
}
-
usart_tx_dma_config
dma_init_t usart_tx_dma_config
Definition main.c:109
-
usart_rx_dma_config
dma_init_t usart_rx_dma_config
Definition main.c:110
+
usart_tx_dma_config
dma_init_t usart_tx_dma_config
Definition main.c:123
+
usart_rx_dma_config
dma_init_t usart_rx_dma_config
Definition main.c:124
WORD_8
@ WORD_8
Definition usart.h:36
HW_DISABLE
@ HW_DISABLE
Definition usart.h:58
OB_DISABLE
@ OB_DISABLE
Definition usart.h:72
diff --git a/diskio_8c.html b/diskio_8c.html index 52b84335..644decc1 100644 --- a/diskio_8c.html +++ b/diskio_8c.html @@ -105,8 +105,6 @@ Macros

#define TM_FATFS_CUSTOM_FATTIME   0   -#define DISK_LOG(...) -  #define ATA   0   #define USB   1 @@ -160,24 +158,6 @@

- - - -

◆ DISK_LOG

- -
-
- - - - - - - -
#define DISK_LOG( ...)
-
-Value:
log_msg(__VA_ARGS__)
-
diff --git a/diskio_8h_source.html b/diskio_8h_source.html index 68aecbbb..4de4b551 100644 --- a/diskio_8h_source.html +++ b/diskio_8h_source.html @@ -172,17 +172,17 @@
77
78#endif
cmd
uint8_t cmd[NXT_STR_SIZE]
Definition main.c:541
-
disk_read
DRESULT disk_read(BYTE pdrv, BYTE *buff, DWORD sector, UINT count)
Definition diskio.c:80
-
disk_initialize
DSTATUS disk_initialize(BYTE pdrv)
Definition diskio.c:41
-
disk_write
DRESULT disk_write(BYTE pdrv, const BYTE *buff, DWORD sector, UINT count)
Definition diskio.c:159
-
disk_status
DSTATUS disk_status(BYTE pdrv)
Definition diskio.c:63
+
disk_read
DRESULT disk_read(BYTE pdrv, BYTE *buff, DWORD sector, UINT count)
Definition diskio.c:81
+
disk_initialize
DSTATUS disk_initialize(BYTE pdrv)
Definition diskio.c:42
+
disk_write
DRESULT disk_write(BYTE pdrv, const BYTE *buff, DWORD sector, UINT count)
Definition diskio.c:160
+
disk_status
DSTATUS disk_status(BYTE pdrv)
Definition diskio.c:64
DRESULT
DRESULT
Definition diskio.h:19
RES_OK
@ RES_OK
Definition diskio.h:20
RES_WRPRT
@ RES_WRPRT
Definition diskio.h:22
RES_ERROR
@ RES_ERROR
Definition diskio.h:21
RES_NOTRDY
@ RES_NOTRDY
Definition diskio.h:23
RES_PARERR
@ RES_PARERR
Definition diskio.h:24
-
disk_ioctl
DRESULT disk_ioctl(BYTE pdrv, BYTE cmd, void *buff)
Definition diskio.c:243
+
disk_ioctl
DRESULT disk_ioctl(BYTE pdrv, BYTE cmd, void *buff)
Definition diskio.c:244
DSTATUS
BYTE DSTATUS
Definition diskio.h:16
UINT
unsigned int UINT
Definition ff.h:58
BYTE
unsigned char BYTE
Definition ff.h:59
diff --git a/doxygen_crawl.html b/doxygen_crawl.html index ac33e894..ca81245c 100644 --- a/doxygen_crawl.html +++ b/doxygen_crawl.html @@ -2013,15 +2013,17 @@ + + + - @@ -2029,6 +2031,7 @@ + @@ -2038,49 +2041,43 @@ + + - - + - + + - - - + - - - - + - - - - - + + @@ -2091,15 +2088,23 @@ + + + + + + + + @@ -2572,7 +2577,6 @@ - @@ -2695,7 +2699,7 @@ - + @@ -3506,6 +3510,8 @@ + + @@ -3514,6 +3520,7 @@ + @@ -3527,10 +3534,12 @@ + + - + @@ -3542,44 +3551,67 @@ + + + + + + + + + + + + + + + + + + + + + + + @@ -3593,16 +3625,21 @@ + + + + + @@ -5039,9 +5076,11 @@ + + @@ -5050,10 +5089,12 @@ + + @@ -6651,6 +6692,7 @@ + diff --git a/eeprom_8h_source.html b/eeprom_8h_source.html index cd0d0457..a7b851be 100644 --- a/eeprom_8h_source.html +++ b/eeprom_8h_source.html @@ -182,7 +182,7 @@
89 uint16_t pg_bound[MAX_PAGES]; // Page bound offset
90 uint16_t mem_size[MAX_PAGES]; // Size of file in bytes (actual)
91 bool bcmp[MAX_PAGES]; // Backwards compatibility enabled
-
92}__attribute__((__packed__));
+
92}__attribute__((__packed__));
93
94struct eeprom {
95 struct phys_mem phys; // Physical
@@ -218,7 +218,7 @@
NAME_LEN
#define NAME_LEN
Definition eeprom_spi.h:34
MAX_PAGES
#define MAX_PAGES
Definition eeprom_spi.h:30
version
uint16_t version
Version number -> X.X.X.
Definition eeprom_spi.h:1
-
__attribute__
struct eeprom __attribute__
Definition daq_hub.h:70
+
__attribute__
struct gs_tx_context __attribute__
Definition daq_hub.h:70
gpio.h
GPIO Driver for STM32L432 Devices.
eeprom
Definition eeprom_spi.h:102
diff --git a/eeprom__spi_8h.html b/eeprom__spi_8h.html index 8b30a4ce..57dd7ee7 100644 --- a/eeprom__spi_8h.html +++ b/eeprom__spi_8h.html @@ -220,8 +220,8 @@ uint8_t bcmp [MAX_PAGES]  Backwards compatibility enabled.
  -struct eeprom __attribute__ -  +struct eeprom __attribute__ + 

Detailed Description

Author
Luke Oxley (lcoxl.nosp@m.ey@p.nosp@m.urdue.nosp@m..edu), modification of Dawson Moore's eeprom.c for SPI support
@@ -899,21 +899,17 @@

Variable Documentation

- -

◆ __attribute__

+ +

◆ __attribute__

- +
void __attribute__struct eeprom __attribute__
-

< command

-

< message id

-

< data length code

-

< message data

diff --git a/eeprom__spi_8h_source.html b/eeprom__spi_8h_source.html index a4ffd7e7..2770c1ed 100644 --- a/eeprom__spi_8h_source.html +++ b/eeprom__spi_8h_source.html @@ -184,7 +184,7 @@
97 uint16_t pg_bound[MAX_PAGES];
98 uint16_t mem_size[MAX_PAGES];
99 uint8_t bcmp[MAX_PAGES];
-
100}__attribute__((__packed__));
+
100}__attribute__((__packed__));
101
@@ -207,7 +207,7 @@
117 uint8_t* source_loc;
118 uint16_t dest_loc;
119 uint8_t update_len;
-
120};
+
120};
121
122// Prototypes
@@ -237,7 +237,7 @@
writePage
int writePage(uint16_t addr, uint8_t *page, uint8_t size)
: Writes a single micro page to chip Must wait 5ms between calls Fails if SPI busy
Definition eeprom_spi.c:420
version
uint16_t version
Version number -> X.X.X.
Definition eeprom_spi.h:1
checkVersion
int checkVersion(uint16_t version)
: Checks version to ensure app code is new enough
Definition eeprom_spi.c:131
-
__attribute__
struct eeprom __attribute__
Definition daq_hub.h:70
+
__attribute__
struct eeprom __attribute__
gpio.h
GPIO Driver for STM32L432 Devices.
spi.h
SPI_InitConfig_t
Configuration entry for SPI initilization.
Definition spi.h:26
diff --git a/f4__testing_2main_8c.html b/f4__testing_2main_8c.html index 9b2138ee..0c193e9f 100644 --- a/f4__testing_2main_8c.html +++ b/f4__testing_2main_8c.html @@ -524,11 +524,11 @@

.periph = USART2,
.wake_addr = false,
.usart_active_num = USART2_ACTIVE_IDX,
-
.tx_dma_cfg = &usart_tx_dma_config,
-
.rx_dma_cfg = &usart_rx_dma_config
+
.tx_dma_cfg = &usart_tx_dma_config,
+
.rx_dma_cfg = &usart_rx_dma_config
}
-
usart_tx_dma_config
dma_init_t usart_tx_dma_config
Definition main.c:109
-
usart_rx_dma_config
dma_init_t usart_rx_dma_config
Definition main.c:110
+
usart_tx_dma_config
dma_init_t usart_tx_dma_config
Definition main.c:123
+
usart_rx_dma_config
dma_init_t usart_rx_dma_config
Definition main.c:124
WORD_8
@ WORD_8
Definition usart.h:36
HW_DISABLE
@ HW_DISABLE
Definition usart.h:58
OB_DISABLE
@ OB_DISABLE
Definition usart.h:72
diff --git a/ff_8c.html b/ff_8c.html index c8c41018..aba495ed 100644 --- a/ff_8c.html +++ b/ff_8c.html @@ -180,7 +180,7 @@   #define BPB_SecPerClus   13 /* Cluster size [sector] (BYTE) */   -#define BPB_RsvdSecCnt   14 /* Size of reserved area [sector] (WORD) */ +#define BPB_RsvdSecCnt   14 /* Size of reserved area [sector] (WORD) */   #define BPB_NumFATs   16 /* Number of FATs (BYTE) */   @@ -218,7 +218,7 @@   #define BPB_FATSz32   36 /* FAT32: FAT size [sector] (DWORD) */   -#define BPB_ExtFlags32   40 /* FAT32: Extended flags (WORD) */ +#define BPB_ExtFlags32   40 /* FAT32: Extended flags (WORD) */   #define BPB_FSVer32   42 /* FAT32: Filesystem version (WORD) */   @@ -262,7 +262,7 @@   #define BPB_FSVerEx   104 /* exFAT: Filesystem version (WORD) */   -#define BPB_VolFlagEx   106 /* exFAT: Volume flags (WORD) */ +#define BPB_VolFlagEx   106 /* exFAT: Volume flags (WORD) */   #define BPB_BytsPerSecEx   108 /* exFAT: Log2 of sector size in unit of byte (BYTE) */   @@ -338,7 +338,7 @@   #define XDIR_AccTZ   24 /* exFAT: Last accessed timezone (BYTE) */   -#define XDIR_GenFlags   33 /* exFAT: General secondary flags (BYTE) */ +#define XDIR_GenFlags   33 /* exFAT: General secondary flags (BYTE) */   #define XDIR_NumName   35 /* exFAT: Number of file name characters (BYTE) */   @@ -346,7 +346,7 @@   #define XDIR_ValidFileSize   40 /* exFAT: Valid file size (QWORD) */   -#define XDIR_FstClus   52 /* exFAT: First cluster of the file data (DWORD) */ +#define XDIR_FstClus   52 /* exFAT: First cluster of the file data (DWORD) */   #define XDIR_FileSize   56 /* exFAT: File/Directory size (QWORD) */   @@ -402,9 +402,9 @@   #define GPTH_BakLba   32 /* GPT HDR: Another header LBA (QWORD) */   -#define GPTH_FstLba   40 /* GPT HDR: First LBA for partition data (QWORD) */ +#define GPTH_FstLba   40 /* GPT HDR: First LBA for partition data (QWORD) */   -#define GPTH_LstLba   48 /* GPT HDR: Last LBA for partition data (QWORD) */ +#define GPTH_LstLba   48 /* GPT HDR: Last LBA for partition data (QWORD) */   #define GPTH_DskGuid   56 /* GPT HDR: Disk GUID (16-byte) */   @@ -426,7 +426,7 @@   #define GPTE_LstLba   40 /* GPT PTE: Last LBA of partition (QWORD) */   -#define GPTE_Flags   48 /* GPT PTE: Partition flags (QWORD) */ +#define GPTE_Flags   48 /* GPT PTE: Partition flags (QWORD) */   #define GPTE_Name   56 /* GPT PTE: Partition name */   @@ -509,7 +509,7 @@ Functions

FRESULT f_mount (FATFS *fs, const TCHAR *path, BYTE opt)   -FRESULT f_open (FIL *fp, const TCHAR *path, BYTE mode) +FRESULT f_open (FIL *fp, const TCHAR *path, BYTE mode)   FRESULT f_read (FIL *fp, void *buff, UINT btr, UINT *br)   @@ -698,7 +698,7 @@

- +
#define BPB_ExtFlags32   40 /* FAT32: Extended flags (WORD) */#define BPB_ExtFlags32   40 /* FAT32: Extended flags (WORD) */
@@ -964,7 +964,7 @@

- +
#define BPB_RsvdSecCnt   14 /* Size of reserved area [sector] (WORD) */#define BPB_RsvdSecCnt   14 /* Size of reserved area [sector] (WORD) */

@@ -1062,7 +1062,7 @@

- +
#define BPB_VolFlagEx   106 /* exFAT: Volume flags (WORD) */#define BPB_VolFlagEx   106 /* exFAT: Volume flags (WORD) */

@@ -1795,7 +1795,7 @@

Value:
get_fattime()
-
get_fattime
DWORD get_fattime(void)
Definition diskio.c:269
+
get_fattime
DWORD get_fattime(void)
Definition diskio.c:270

@@ -1806,7 +1806,7 @@

- +
#define GPTE_Flags   48 /* GPT PTE: Partition flags (QWORD) */#define GPTE_Flags   48 /* GPT PTE: Partition flags (QWORD) */
@@ -1946,7 +1946,7 @@

- +
#define GPTH_FstLba   40 /* GPT HDR: First LBA for partition data (QWORD) */#define GPTH_FstLba   40 /* GPT HDR: First LBA for partition data (QWORD) */

@@ -1960,7 +1960,7 @@

- +
#define GPTH_LstLba   48 /* GPT HDR: Last LBA for partition data (QWORD) */#define GPTH_LstLba   48 /* GPT HDR: Last LBA for partition data (QWORD) */

@@ -3440,7 +3440,7 @@

- +
#define XDIR_FstClus   52 /* exFAT: First cluster of the file data (DWORD) */#define XDIR_FstClus   52 /* exFAT: First cluster of the file data (DWORD) */

@@ -3454,7 +3454,7 @@

- +
#define XDIR_GenFlags   33 /* exFAT: General secondary flags (BYTE) */#define XDIR_GenFlags   33 /* exFAT: General secondary flags (BYTE) */

diff --git a/ff_8h.html b/ff_8h.html index 8faaf825..56f93a08 100644 --- a/ff_8h.html +++ b/ff_8h.html @@ -239,7 +239,7 @@ - + diff --git a/ff_8h_source.html b/ff_8h_source.html index 66d6086b..e28a3d76 100644 --- a/ff_8h_source.html +++ b/ff_8h_source.html @@ -408,7 +408,7 @@
301/* FatFs Module Application Interface */
302/*--------------------------------------------------------------*/
303
-
304FRESULT f_open (FIL* fp, const TCHAR* path, BYTE mode); /* Open or create a file */
+
304FRESULT f_open (FIL* fp, const TCHAR* path, BYTE mode); /* Open or create a file */
305FRESULT f_close (FIL* fp); /* Close an open file object */
306FRESULT f_read (FIL* fp, void* buff, UINT btr, UINT* br); /* Read data from the file */
307FRESULT f_write (FIL* fp, const void* buff, UINT btw, UINT* bw); /* Write data to the file */
@@ -600,12 +600,13 @@
f_sync
FRESULT f_sync(FIL *fp)
Definition ff.c:4135
f_write
FRESULT f_write(FIL *fp, const void *buff, UINT btw, UINT *bw)
Definition ff.c:4014
f_open
FRESULT f_open(FIL *fp, const TCHAR *path, BYTE mode)
Definition ff.c:3717
-
get_fattime
DWORD get_fattime(void)
Definition diskio.c:269
+
get_fattime
DWORD get_fattime(void)
Definition diskio.c:270
FF_MAX_SS
#define FF_MAX_SS
Definition ffconf.h:197
FF_VOLUMES
#define FF_VOLUMES
Definition ffconf.h:169
FF_LFN_BUF
#define FF_LFN_BUF
Definition ffconf.h:148
FF_SFN_BUF
#define FF_SFN_BUF
Definition ffconf.h:149
+
mode
u32 mode
Definition gs_usb.h:0
DIR
Definition ff.h:226
DIR::dptr
DWORD dptr
Definition ff.h:228
DIR::dir
BYTE * dir
Definition ff.h:231
diff --git a/functions_l.html b/functions_l.html index a39aab69..55da1455 100644 --- a/functions_l.html +++ b/functions_l.html @@ -129,6 +129,7 @@

- l -

- + - + - + - + @@ -242,13 +243,13 @@ - + - + - + - + @@ -317,10 +318,79 @@ }

Functions

FRESULT f_open (FIL *fp, const TCHAR *path, BYTE mode)
FRESULT f_open (FIL *fp, const TCHAR *path, BYTE mode)
 
FRESULT f_close (FIL *fp)
 
 
#define CAN_ERR_TX_TIMEOUT   0x00000001U /* TX timeout (by netdevice driver) */
 
#define CAN_ERR_LOSTARB   0x00000002U /* lost arbitration / data[0] */
#define CAN_ERR_LOSTARB   0x00000002U /* lost arbitration / data[0] */
 
#define CAN_ERR_CRTL   0x00000004U /* controller problems / data[1] */
#define CAN_ERR_CRTL   0x00000004U /* controller problems / data[1] */
 
#define CAN_ERR_PROT   0x00000008U /* protocol violations / data[2..3] */
#define CAN_ERR_PROT   0x00000008U /* protocol violations / data[2..3] */
 
#define CAN_ERR_TRX   0x00000010U /* transceiver status / data[4] */
#define CAN_ERR_TRX   0x00000010U /* transceiver status / data[4] */
 
#define CAN_ERR_ACK   0x00000020U /* received no ACK on transmission */
 
 
#define CAN_ERR_PROT_LOC_RTR   0x0C /* RTR */
 
#define CAN_ERR_PROT_LOC_RES1   0x0D /* reserved bit 1 */
#define CAN_ERR_PROT_LOC_RES1   0x0D /* reserved bit 1 */
 
#define CAN_ERR_PROT_LOC_RES0   0x09 /* reserved bit 0 */
#define CAN_ERR_PROT_LOC_RES0   0x09 /* reserved bit 0 */
 
#define CAN_ERR_PROT_LOC_DLC   0x0B /* data length code */
#define CAN_ERR_PROT_LOC_DLC   0x0B /* data length code */
 
#define CAN_ERR_PROT_LOC_DATA   0x0A /* data section */
#define CAN_ERR_PROT_LOC_DATA   0x0A /* data section */
 
#define CAN_ERR_PROT_LOC_CRC_SEQ   0x08 /* CRC sequence */
 
 
 + + + +

+Functions

struct gs_host_config __attribute__ ((__packed__))
 
- - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Variables

struct gs_host_config __packed
 
u32 byte_order
 
u8 reserved1
 
u8 reserved2
 
u8 reserved3
 
u8 icount
 
u32 sw_version
 
u32 hw_version
 
u32 mode
 
u32 flags
 
struct gs_device_state __packed
 
u32 prop_seg
 
u32 phase_seg1
 
u32 phase_seg2
 
u32 sjw
 
u32 brp
 
u32 feature
 
u32 fclk_can
 
u32 tseg1_min
 
u32 tseg1_max
 
u32 tseg2_min
 
u32 tseg2_max
 
u32 sjw_max
 
u32 brp_min
 
u32 brp_max
 
u32 brp_inc
 
u32 echo_id
 
u32 can_id
 
u8 can_dlc
 
u8 channel
 
u8 reserved
 
u8 data [8]
 
u32 timestamp_us
 
struct gs_tx_context __attribute__
 

Macro Definition Documentation

@@ -386,7 +456,7 @@

- +
#define CAN_ERR_CRTL   0x00000004U /* controller problems / data[1] */#define CAN_ERR_CRTL   0x00000004U /* controller problems / data[1] */

@@ -540,7 +610,7 @@

- +
#define CAN_ERR_LOSTARB   0x00000002U /* lost arbitration / data[0] */#define CAN_ERR_LOSTARB   0x00000002U /* lost arbitration / data[0] */

@@ -568,7 +638,7 @@

- +
#define CAN_ERR_PROT   0x00000008U /* protocol violations / data[2..3] */#define CAN_ERR_PROT   0x00000008U /* protocol violations / data[2..3] */

@@ -708,7 +778,7 @@

- +
#define CAN_ERR_PROT_LOC_DATA   0x0A /* data section */#define CAN_ERR_PROT_LOC_DATA   0x0A /* data section */

@@ -722,7 +792,7 @@

- +
#define CAN_ERR_PROT_LOC_DLC   0x0B /* data length code */#define CAN_ERR_PROT_LOC_DLC   0x0B /* data length code */

@@ -848,7 +918,7 @@

- +
#define CAN_ERR_PROT_LOC_RES0   0x09 /* reserved bit 0 */#define CAN_ERR_PROT_LOC_RES0   0x09 /* reserved bit 0 */

@@ -862,7 +932,7 @@

- +
#define CAN_ERR_PROT_LOC_RES1   0x0D /* reserved bit 1 */#define CAN_ERR_PROT_LOC_RES1   0x0D /* reserved bit 1 */

@@ -1002,7 +1072,7 @@

- +
#define CAN_ERR_TRX   0x00000010U /* transceiver status / data[4] */#define CAN_ERR_TRX   0x00000010U /* transceiver status / data[4] */

@@ -1522,17 +1592,487 @@

GS_USB_BREQ_SET_USER_ID  +

+ +

Function Documentation

+ +

◆ __attribute__()

+ +
+
+ + + + + + + +
struct gs_host_config __attribute__ ((__packed__) )
+
+

Variable Documentation

- -

◆ __packed

+ +

◆ __attribute__

+ +
+
+ + + + +
void __attribute__
+
+

< command

+

< message id

+

< data length code

+

< message data

+ +
+
+ +

◆ __packed

+ +
+
+ + + + +
struct gs_device_state __packed
+
+ +
+
+ +

◆ brp

+ +
+
+ + + + +
u32 brp
+
+ +
+
+ +

◆ brp_inc

+ +
+
+ + + + +
u32 brp_inc
+
+ +
+
+ +

◆ brp_max

+ +
+
+ + + + +
u32 brp_max
+
+ +
+
+ +

◆ brp_min

+ +
+
+ + + + +
u32 brp_min
+
+ +
+
+ +

◆ byte_order

+ +
+
+ + + + +
u32 byte_order
+
+ +
+
+ +

◆ can_dlc

+ +
+
+ + + + +
u8 can_dlc
+
+ +
+
+ +

◆ can_id

+ +
+
+ + + + +
u32 can_id
+
+ +
+
+ +

◆ channel

+ +
+
+ + + + +
u8 channel
+
+ +
+
+ +

◆ data

+ +
+
+ + + + +
u8 data[8]
+
+ +
+
+ +

◆ echo_id

+ +
+
+ + + + +
u32 echo_id
+
+ +
+
+ +

◆ fclk_can

+ +
+
+ + + + +
u32 fclk_can
+
+ +
+
+ +

◆ feature

+ +
+
+ + + + +
u32 feature
+
+ +
+
+ +

◆ flags

+ +
+
+ + + + +
u8 flags
+
+ +
+
+ +

◆ hw_version

+ +
+
+ + + + +
u32 hw_version
+
+ +
+
+ +

◆ icount

+ +
+
+ + + + +
u8 icount
+
+ +
+
+ +

◆ mode

+ +
+
+ + + + +
u32 mode
+
+ +
+
+ +

◆ phase_seg1

+ +
+
+ + + + +
u32 phase_seg1
+
+ +
+
+ +

◆ phase_seg2

+ +
+
+ + + + +
u32 phase_seg2
+
+ +
+
+ +

◆ prop_seg

+ +
+
+ + + + +
u32 prop_seg
+
+ +
+
+ +

◆ reserved

+ +
+
+ + + + +
u8 reserved
+
+ +
+
+ +

◆ reserved1

+ +
+
+ + + + +
u8 reserved1
+
+ +
+
+ +

◆ reserved2

+ +
+
+ + + + +
u8 reserved2
+
+ +
+
+ +

◆ reserved3

+ +
+
+ + + + +
u8 reserved3
+
+ +
+
+ +

◆ sjw

+ +
+
+ + + + +
u32 sjw
+
+ +
+
+ +

◆ sjw_max

+ +
+
+ + + + +
u32 sjw_max
+
+ +
+
+ +

◆ sw_version

+ +
+
+ + + + +
u32 sw_version
+
+ +
+
+ +

◆ timestamp_us

+ +
+
+ + + + +
u32 timestamp_us
+
+ +
+
+ +

◆ tseg1_max

+ +
+
+ + + + +
u32 tseg1_max
+
+ +
+
+ +

◆ tseg1_min

+ +
+
+ + + + +
u32 tseg1_min
+
+ +
+
+ +

◆ tseg2_max

+ +
+
+ + + + +
u32 tseg2_max
+
+ +
+
+ +

◆ tseg2_min

- +
struct gs_host_frame __packedu32 tseg2_min
diff --git a/gs__usb_8h_source.html b/gs__usb_8h_source.html index e0d28059..878a9b0c 100644 --- a/gs__usb_8h_source.html +++ b/gs__usb_8h_source.html @@ -91,16 +91,17 @@
gs_usb.h
-Go to the documentation of this file.
1/*
-
2
-
3The MIT License (MIT)
-
4
-
5Copyright (c) 2016 Hubert Denkmair
-
6
-
7Permission is hereby granted, free of charge, to any person obtaining a copy
-
8of this software and associated documentation files (the "Software"), to deal
-
9in the Software without restriction, including without limitation the rights
-
10to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+Go to the documentation of this file.
+
1/*
+
2
+
3The MIT License (MIT)
+
4
+
5Copyright (c) 2016 Hubert Denkmair
+
6
+
7Permission is hereby granted, free of charge, to any person obtaining a copy
+
8of this software and associated documentation files (the "Software"), to deal
+
9in the Software without restriction, including without limitation the rights
+
10to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11copies of the Software, and to permit persons to whom the Software is
12furnished to do so, subject to the following conditions:
13
@@ -117,306 +118,310 @@
24
25*/
26
-
27#pragma once
-
28
-
29#define u32 uint32_t
-
30#define u8 uint8_t
-
31
-
32#define GSUSB_ENDPOINT_IN 0x81
-
33#define GSUSB_ENDPOINT_OUT 0x02
-
34
+
27#ifndef __GS_USB_H__
+
28#define __GS_USB_H__
+
29
+
30#define u32 uint32_t
+
31#define u8 uint8_t
+
32
+
33#define GSUSB_ENDPOINT_IN 0x81
+
34#define GSUSB_ENDPOINT_OUT 0x02
35
-
36#define GS_CAN_MODE_NORMAL 0
-
37#define GS_CAN_MODE_LISTEN_ONLY (1<<0)
-
38#define GS_CAN_MODE_LOOP_BACK (1<<1)
-
39#define GS_CAN_MODE_TRIPLE_SAMPLE (1<<2)
-
40#define GS_CAN_MODE_ONE_SHOT (1<<3)
-
41#define GS_CAN_MODE_HW_TIMESTAMP (1<<4)
-
42
-
43#define GS_CAN_MODE_PAD_PKTS_TO_MAX_PKT_SIZE (1<<7)
-
44
-
45#define GS_CAN_FEATURE_LISTEN_ONLY (1<<0)
-
46#define GS_CAN_FEATURE_LOOP_BACK (1<<1)
-
47#define GS_CAN_FEATURE_TRIPLE_SAMPLE (1<<2)
-
48#define GS_CAN_FEATURE_ONE_SHOT (1<<3)
-
49#define GS_CAN_FEATURE_HW_TIMESTAMP (1<<4)
-
50#define GS_CAN_FEATURE_IDENTIFY (1<<5)
-
51#define GS_CAN_FEATURE_USER_ID (1<<6)
-
52
-
53#define GS_CAN_FEATURE_PAD_PKTS_TO_MAX_PKT_SIZE (1<<7)
-
54
-
55#define GS_CAN_FLAG_OVERFLOW 1
-
56
-
57#define CAN_EFF_FLAG 0x80000000U /* EFF/SFF is set in the MSB */
-
58#define CAN_RTR_FLAG 0x40000000U /* remote transmission request */
-
59#define CAN_ERR_FLAG 0x20000000U /* error message frame */
-
60
-
61#define CAN_ERR_DLC 8 /* dlc for error message frames */
-
62
-
63/* error class (mask) in can_id */
-
64#define CAN_ERR_TX_TIMEOUT 0x00000001U /* TX timeout (by netdevice driver) */
-
65#define CAN_ERR_LOSTARB 0x00000002U /* lost arbitration / data[0] */
-
66#define CAN_ERR_CRTL 0x00000004U /* controller problems / data[1] */
-
67#define CAN_ERR_PROT 0x00000008U /* protocol violations / data[2..3] */
-
68#define CAN_ERR_TRX 0x00000010U /* transceiver status / data[4] */
-
69#define CAN_ERR_ACK 0x00000020U /* received no ACK on transmission */
-
70#define CAN_ERR_BUSOFF 0x00000040U /* bus off */
-
71#define CAN_ERR_BUSERROR 0x00000080U /* bus error (may flood!) */
-
72#define CAN_ERR_RESTARTED 0x00000100U /* controller restarted */
-
73
-
74/* arbitration lost in bit ... / data[0] */
-
75#define CAN_ERR_LOSTARB_UNSPEC 0x00 /* unspecified */
-
76 /* else bit number in bitstream */
-
77
-
78/* error status of CAN-controller / data[1] */
-
79#define CAN_ERR_CRTL_UNSPEC 0x00 /* unspecified */
-
80#define CAN_ERR_CRTL_RX_OVERFLOW 0x01 /* RX buffer overflow */
-
81#define CAN_ERR_CRTL_TX_OVERFLOW 0x02 /* TX buffer overflow */
-
82#define CAN_ERR_CRTL_RX_WARNING 0x04 /* reached warning level for RX errors */
-
83#define CAN_ERR_CRTL_TX_WARNING 0x08 /* reached warning level for TX errors */
-
84#define CAN_ERR_CRTL_RX_PASSIVE 0x10 /* reached error passive status RX */
-
85#define CAN_ERR_CRTL_TX_PASSIVE 0x20 /* reached error passive status TX */
-
86 /* (at least one error counter exceeds */
-
87 /* the protocol-defined level of 127) */
-
88#define CAN_ERR_CRTL_ACTIVE 0x40 /* recovered to error active state */
-
89
-
90/* error in CAN protocol (type) / data[2] */
-
91#define CAN_ERR_PROT_UNSPEC 0x00 /* unspecified */
-
92#define CAN_ERR_PROT_BIT 0x01 /* single bit error */
-
93#define CAN_ERR_PROT_FORM 0x02 /* frame format error */
-
94#define CAN_ERR_PROT_STUFF 0x04 /* bit stuffing error */
-
95#define CAN_ERR_PROT_BIT0 0x08 /* unable to send dominant bit */
-
96#define CAN_ERR_PROT_BIT1 0x10 /* unable to send recessive bit */
-
97#define CAN_ERR_PROT_OVERLOAD 0x20 /* bus overload */
-
98#define CAN_ERR_PROT_ACTIVE 0x40 /* active error announcement */
-
99#define CAN_ERR_PROT_TX 0x80 /* error occurred on transmission */
-
100
-
101/* error in CAN protocol (location) / data[3] */
-
102#define CAN_ERR_PROT_LOC_UNSPEC 0x00 /* unspecified */
-
103#define CAN_ERR_PROT_LOC_SOF 0x03 /* start of frame */
-
104#define CAN_ERR_PROT_LOC_ID28_21 0x02 /* ID bits 28 - 21 (SFF: 10 - 3) */
-
105#define CAN_ERR_PROT_LOC_ID20_18 0x06 /* ID bits 20 - 18 (SFF: 2 - 0 )*/
-
106#define CAN_ERR_PROT_LOC_SRTR 0x04 /* substitute RTR (SFF: RTR) */
-
107#define CAN_ERR_PROT_LOC_IDE 0x05 /* identifier extension */
-
108#define CAN_ERR_PROT_LOC_ID17_13 0x07 /* ID bits 17-13 */
-
109#define CAN_ERR_PROT_LOC_ID12_05 0x0F /* ID bits 12-5 */
-
110#define CAN_ERR_PROT_LOC_ID04_00 0x0E /* ID bits 4-0 */
-
111#define CAN_ERR_PROT_LOC_RTR 0x0C /* RTR */
-
112#define CAN_ERR_PROT_LOC_RES1 0x0D /* reserved bit 1 */
-
113#define CAN_ERR_PROT_LOC_RES0 0x09 /* reserved bit 0 */
-
114#define CAN_ERR_PROT_LOC_DLC 0x0B /* data length code */
-
115#define CAN_ERR_PROT_LOC_DATA 0x0A /* data section */
-
116#define CAN_ERR_PROT_LOC_CRC_SEQ 0x08 /* CRC sequence */
-
117#define CAN_ERR_PROT_LOC_CRC_DEL 0x18 /* CRC delimiter */
-
118#define CAN_ERR_PROT_LOC_ACK 0x19 /* ACK slot */
-
119#define CAN_ERR_PROT_LOC_ACK_DEL 0x1B /* ACK delimiter */
-
120#define CAN_ERR_PROT_LOC_EOF 0x1A /* end of frame */
-
121#define CAN_ERR_PROT_LOC_INTERM 0x12 /* intermission */
-
122
-
123/* error status of CAN-transceiver / data[4] */
-
124/* CANH CANL */
-
125#define CAN_ERR_TRX_UNSPEC 0x00 /* 0000 0000 */
-
126#define CAN_ERR_TRX_CANH_NO_WIRE 0x04 /* 0000 0100 */
-
127#define CAN_ERR_TRX_CANH_SHORT_TO_BAT 0x05 /* 0000 0101 */
-
128#define CAN_ERR_TRX_CANH_SHORT_TO_VCC 0x06 /* 0000 0110 */
-
129#define CAN_ERR_TRX_CANH_SHORT_TO_GND 0x07 /* 0000 0111 */
-
130#define CAN_ERR_TRX_CANL_NO_WIRE 0x40 /* 0100 0000 */
-
131#define CAN_ERR_TRX_CANL_SHORT_TO_BAT 0x50 /* 0101 0000 */
-
132#define CAN_ERR_TRX_CANL_SHORT_TO_VCC 0x60 /* 0110 0000 */
-
133#define CAN_ERR_TRX_CANL_SHORT_TO_GND 0x70 /* 0111 0000 */
-
134#define CAN_ERR_TRX_CANL_SHORT_TO_CANH 0x80 /* 1000 0000 */
-
135
+
36
+
37#define GS_CAN_MODE_NORMAL 0
+
38#define GS_CAN_MODE_LISTEN_ONLY (1<<0)
+
39#define GS_CAN_MODE_LOOP_BACK (1<<1)
+
40#define GS_CAN_MODE_TRIPLE_SAMPLE (1<<2)
+
41#define GS_CAN_MODE_ONE_SHOT (1<<3)
+
42#define GS_CAN_MODE_HW_TIMESTAMP (1<<4)
+
43
+
44#define GS_CAN_MODE_PAD_PKTS_TO_MAX_PKT_SIZE (1<<7)
+
45
+
46#define GS_CAN_FEATURE_LISTEN_ONLY (1<<0)
+
47#define GS_CAN_FEATURE_LOOP_BACK (1<<1)
+
48#define GS_CAN_FEATURE_TRIPLE_SAMPLE (1<<2)
+
49#define GS_CAN_FEATURE_ONE_SHOT (1<<3)
+
50#define GS_CAN_FEATURE_HW_TIMESTAMP (1<<4)
+
51#define GS_CAN_FEATURE_IDENTIFY (1<<5)
+
52#define GS_CAN_FEATURE_USER_ID (1<<6)
+
53
+
54#define GS_CAN_FEATURE_PAD_PKTS_TO_MAX_PKT_SIZE (1<<7)
+
55
+
56#define GS_CAN_FLAG_OVERFLOW 1
+
57
+
58#define CAN_EFF_FLAG 0x80000000U /* EFF/SFF is set in the MSB */
+
59#define CAN_RTR_FLAG 0x40000000U /* remote transmission request */
+
60#define CAN_ERR_FLAG 0x20000000U /* error message frame */
+
61
+
62#define CAN_ERR_DLC 8 /* dlc for error message frames */
+
63
+
64/* error class (mask) in can_id */
+
65#define CAN_ERR_TX_TIMEOUT 0x00000001U /* TX timeout (by netdevice driver) */
+
66#define CAN_ERR_LOSTARB 0x00000002U /* lost arbitration / data[0] */
+
67#define CAN_ERR_CRTL 0x00000004U /* controller problems / data[1] */
+
68#define CAN_ERR_PROT 0x00000008U /* protocol violations / data[2..3] */
+
69#define CAN_ERR_TRX 0x00000010U /* transceiver status / data[4] */
+
70#define CAN_ERR_ACK 0x00000020U /* received no ACK on transmission */
+
71#define CAN_ERR_BUSOFF 0x00000040U /* bus off */
+
72#define CAN_ERR_BUSERROR 0x00000080U /* bus error (may flood!) */
+
73#define CAN_ERR_RESTARTED 0x00000100U /* controller restarted */
+
74
+
75/* arbitration lost in bit ... / data[0] */
+
76#define CAN_ERR_LOSTARB_UNSPEC 0x00 /* unspecified */
+
77 /* else bit number in bitstream */
+
78
+
79/* error status of CAN-controller / data[1] */
+
80#define CAN_ERR_CRTL_UNSPEC 0x00 /* unspecified */
+
81#define CAN_ERR_CRTL_RX_OVERFLOW 0x01 /* RX buffer overflow */
+
82#define CAN_ERR_CRTL_TX_OVERFLOW 0x02 /* TX buffer overflow */
+
83#define CAN_ERR_CRTL_RX_WARNING 0x04 /* reached warning level for RX errors */
+
84#define CAN_ERR_CRTL_TX_WARNING 0x08 /* reached warning level for TX errors */
+
85#define CAN_ERR_CRTL_RX_PASSIVE 0x10 /* reached error passive status RX */
+
86#define CAN_ERR_CRTL_TX_PASSIVE 0x20 /* reached error passive status TX */
+
87 /* (at least one error counter exceeds */
+
88 /* the protocol-defined level of 127) */
+
89#define CAN_ERR_CRTL_ACTIVE 0x40 /* recovered to error active state */
+
90
+
91/* error in CAN protocol (type) / data[2] */
+
92#define CAN_ERR_PROT_UNSPEC 0x00 /* unspecified */
+
93#define CAN_ERR_PROT_BIT 0x01 /* single bit error */
+
94#define CAN_ERR_PROT_FORM 0x02 /* frame format error */
+
95#define CAN_ERR_PROT_STUFF 0x04 /* bit stuffing error */
+
96#define CAN_ERR_PROT_BIT0 0x08 /* unable to send dominant bit */
+
97#define CAN_ERR_PROT_BIT1 0x10 /* unable to send recessive bit */
+
98#define CAN_ERR_PROT_OVERLOAD 0x20 /* bus overload */
+
99#define CAN_ERR_PROT_ACTIVE 0x40 /* active error announcement */
+
100#define CAN_ERR_PROT_TX 0x80 /* error occurred on transmission */
+
101
+
102/* error in CAN protocol (location) / data[3] */
+
103#define CAN_ERR_PROT_LOC_UNSPEC 0x00 /* unspecified */
+
104#define CAN_ERR_PROT_LOC_SOF 0x03 /* start of frame */
+
105#define CAN_ERR_PROT_LOC_ID28_21 0x02 /* ID bits 28 - 21 (SFF: 10 - 3) */
+
106#define CAN_ERR_PROT_LOC_ID20_18 0x06 /* ID bits 20 - 18 (SFF: 2 - 0 )*/
+
107#define CAN_ERR_PROT_LOC_SRTR 0x04 /* substitute RTR (SFF: RTR) */
+
108#define CAN_ERR_PROT_LOC_IDE 0x05 /* identifier extension */
+
109#define CAN_ERR_PROT_LOC_ID17_13 0x07 /* ID bits 17-13 */
+
110#define CAN_ERR_PROT_LOC_ID12_05 0x0F /* ID bits 12-5 */
+
111#define CAN_ERR_PROT_LOC_ID04_00 0x0E /* ID bits 4-0 */
+
112#define CAN_ERR_PROT_LOC_RTR 0x0C /* RTR */
+
113#define CAN_ERR_PROT_LOC_RES1 0x0D /* reserved bit 1 */
+
114#define CAN_ERR_PROT_LOC_RES0 0x09 /* reserved bit 0 */
+
115#define CAN_ERR_PROT_LOC_DLC 0x0B /* data length code */
+
116#define CAN_ERR_PROT_LOC_DATA 0x0A /* data section */
+
117#define CAN_ERR_PROT_LOC_CRC_SEQ 0x08 /* CRC sequence */
+
118#define CAN_ERR_PROT_LOC_CRC_DEL 0x18 /* CRC delimiter */
+
119#define CAN_ERR_PROT_LOC_ACK 0x19 /* ACK slot */
+
120#define CAN_ERR_PROT_LOC_ACK_DEL 0x1B /* ACK delimiter */
+
121#define CAN_ERR_PROT_LOC_EOF 0x1A /* end of frame */
+
122#define CAN_ERR_PROT_LOC_INTERM 0x12 /* intermission */
+
123
+
124/* error status of CAN-transceiver / data[4] */
+
125/* CANH CANL */
+
126#define CAN_ERR_TRX_UNSPEC 0x00 /* 0000 0000 */
+
127#define CAN_ERR_TRX_CANH_NO_WIRE 0x04 /* 0000 0100 */
+
128#define CAN_ERR_TRX_CANH_SHORT_TO_BAT 0x05 /* 0000 0101 */
+
129#define CAN_ERR_TRX_CANH_SHORT_TO_VCC 0x06 /* 0000 0110 */
+
130#define CAN_ERR_TRX_CANH_SHORT_TO_GND 0x07 /* 0000 0111 */
+
131#define CAN_ERR_TRX_CANL_NO_WIRE 0x40 /* 0100 0000 */
+
132#define CAN_ERR_TRX_CANL_SHORT_TO_BAT 0x50 /* 0101 0000 */
+
133#define CAN_ERR_TRX_CANL_SHORT_TO_VCC 0x60 /* 0110 0000 */
+
134#define CAN_ERR_TRX_CANL_SHORT_TO_GND 0x70 /* 0111 0000 */
+
135#define CAN_ERR_TRX_CANL_SHORT_TO_CANH 0x80 /* 1000 0000 */
136
-
-
137enum gs_usb_breq {
-
138 GS_USB_BREQ_HOST_FORMAT = 0,
-
139 GS_USB_BREQ_BITTIMING,
-
140 GS_USB_BREQ_MODE,
-
141 GS_USB_BREQ_BERR,
-
142 GS_USB_BREQ_BT_CONST,
-
143 GS_USB_BREQ_DEVICE_CONFIG,
-
144 GS_USB_BREQ_TIMESTAMP,
-
145 GS_USB_BREQ_IDENTIFY,
-
146 GS_USB_BREQ_GET_USER_ID,
-
147 GS_USB_BREQ_SET_USER_ID,
-
148};
+
137
+ -
149
-
-
150enum gs_can_mode {
-
151 /* reset a channel. turns it off */
-
152 GS_CAN_MODE_RESET = 0,
-
153 /* starts a channel */
-
154 GS_CAN_MODE_START
-
155};
+
150
+
+
151enum gs_can_mode {
+
152 /* reset a channel. turns it off */
+
153 GS_CAN_MODE_RESET = 0,
+
154 /* starts a channel */
+
155 GS_CAN_MODE_START
+
156};
-
156
-
-
157enum gs_can_state {
-
158 GS_CAN_STATE_ERROR_ACTIVE = 0,
-
159 GS_CAN_STATE_ERROR_WARNING,
-
160 GS_CAN_STATE_ERROR_PASSIVE,
-
161 GS_CAN_STATE_BUS_OFF,
-
162 GS_CAN_STATE_STOPPED,
-
163 GS_CAN_STATE_SLEEPING
-
164};
+
157
+ -
165
-
166/* data types passed between host and device */
-
-
167struct gs_host_config {
-
168 u32 byte_order;
-
169} __packed;
+
166
+
167/* data types passed between host and device */
+
+
168struct gs_host_config {
+
169 u32 byte_order;
+
170} __attribute__((__packed__));
-
170/* All data exchanged between host and device is exchanged in host byte order,
-
171 * thanks to the struct gs_host_config byte_order member, which is sent first
-
172 * to indicate the desired byte order.
-
173 */
-
174
- -
183
-
-
184struct gs_device_mode {
-
185 u32 mode;
-
186 u32 flags;
-
187} __packed;
+
171/* All data exchanged between host and device is exchanged in host byte order,
+
172 * thanks to the struct gs_host_config byte_order member, which is sent first
+
173 * to indicate the desired byte order.
+
174 */
+
175
+ -
188
-
-
189struct gs_device_state {
-
190 u32 state;
-
191 u32 rxerr;
-
192 u32 txerr;
-
193} __packed;
+
184
+
+
185struct gs_device_mode {
+
186 u32 mode;
+
187 u32 flags;
+
188} __attribute__((__packed__));
-
194
-
-
195struct gs_device_bittiming {
-
196 u32 prop_seg;
-
197 u32 phase_seg1;
-
198 u32 phase_seg2;
-
199 u32 sjw;
-
200 u32 brp;
-
201} __packed;
+
189
+ -
202
-
-
203struct gs_device_bt_const {
-
204 u32 feature;
-
205 u32 fclk_can;
-
206 u32 tseg1_min;
-
207 u32 tseg1_max;
-
208 u32 tseg2_min;
-
209 u32 tseg2_max;
-
210 u32 sjw_max;
-
211 u32 brp_min;
-
212 u32 brp_max;
-
213 u32 brp_inc;
-
214} __packed;
+
195
+ -
215
-
-
216struct gs_host_frame {
-
217 u32 echo_id;
-
218 u32 can_id;
-
219
-
220 u8 can_dlc;
-
221 u8 channel;
-
222 u8 flags;
-
223 u8 reserved;
-
224
-
225 u8 data[8];
-
226
-
227 u32 timestamp_us;
-
228
-
229} __packed;
+
203
+ -
230
-
-
231struct gs_tx_context {
-
232 struct gs_can *dev;
-
233 unsigned int echo_id;
-
234};
+
216
+
+
217struct gs_host_frame {
+
218 u32 echo_id;
+
219 u32 can_id;
+
220
+
221 u8 can_dlc;
+
222 u8 channel;
+
223 u8 flags;
+
224 u8 reserved;
+
225
+
226 u8 data[8];
+
227
+
228 u32 timestamp_us;
+
229
+
230} __attribute__((__packed__));
-
235
-
u32
#define u32
Definition gs_usb.h:29
-
__packed
struct gs_host_config __packed
-
gs_can_state
gs_can_state
Definition gs_usb.h:157
-
GS_CAN_STATE_SLEEPING
@ GS_CAN_STATE_SLEEPING
Definition gs_usb.h:163
-
GS_CAN_STATE_ERROR_PASSIVE
@ GS_CAN_STATE_ERROR_PASSIVE
Definition gs_usb.h:160
-
GS_CAN_STATE_ERROR_ACTIVE
@ GS_CAN_STATE_ERROR_ACTIVE
Definition gs_usb.h:158
-
GS_CAN_STATE_STOPPED
@ GS_CAN_STATE_STOPPED
Definition gs_usb.h:162
-
GS_CAN_STATE_BUS_OFF
@ GS_CAN_STATE_BUS_OFF
Definition gs_usb.h:161
-
GS_CAN_STATE_ERROR_WARNING
@ GS_CAN_STATE_ERROR_WARNING
Definition gs_usb.h:159
-
gs_can_mode
gs_can_mode
Definition gs_usb.h:150
-
GS_CAN_MODE_START
@ GS_CAN_MODE_START
Definition gs_usb.h:154
-
GS_CAN_MODE_RESET
@ GS_CAN_MODE_RESET
Definition gs_usb.h:152
-
gs_usb_breq
gs_usb_breq
Definition gs_usb.h:137
-
GS_USB_BREQ_TIMESTAMP
@ GS_USB_BREQ_TIMESTAMP
Definition gs_usb.h:144
-
GS_USB_BREQ_HOST_FORMAT
@ GS_USB_BREQ_HOST_FORMAT
Definition gs_usb.h:138
-
GS_USB_BREQ_SET_USER_ID
@ GS_USB_BREQ_SET_USER_ID
Definition gs_usb.h:147
-
GS_USB_BREQ_BERR
@ GS_USB_BREQ_BERR
Definition gs_usb.h:141
-
GS_USB_BREQ_IDENTIFY
@ GS_USB_BREQ_IDENTIFY
Definition gs_usb.h:145
-
GS_USB_BREQ_GET_USER_ID
@ GS_USB_BREQ_GET_USER_ID
Definition gs_usb.h:146
-
GS_USB_BREQ_MODE
@ GS_USB_BREQ_MODE
Definition gs_usb.h:140
-
GS_USB_BREQ_BITTIMING
@ GS_USB_BREQ_BITTIMING
Definition gs_usb.h:139
-
GS_USB_BREQ_DEVICE_CONFIG
@ GS_USB_BREQ_DEVICE_CONFIG
Definition gs_usb.h:143
-
GS_USB_BREQ_BT_CONST
@ GS_USB_BREQ_BT_CONST
Definition gs_usb.h:142
-
u8
#define u8
Definition gs_usb.h:30
-
gs_device_bittiming
Definition gs_usb.h:195
-
gs_device_bittiming::brp
u32 brp
Definition gs_usb.h:200
-
gs_device_bittiming::sjw
u32 sjw
Definition gs_usb.h:199
-
gs_device_bittiming::phase_seg2
u32 phase_seg2
Definition gs_usb.h:198
-
gs_device_bittiming::phase_seg1
u32 phase_seg1
Definition gs_usb.h:197
-
gs_device_bittiming::prop_seg
u32 prop_seg
Definition gs_usb.h:196
-
gs_device_bt_const
Definition gs_usb.h:203
-
gs_device_bt_const::sjw_max
u32 sjw_max
Definition gs_usb.h:210
-
gs_device_bt_const::brp_max
u32 brp_max
Definition gs_usb.h:212
-
gs_device_bt_const::brp_min
u32 brp_min
Definition gs_usb.h:211
-
gs_device_bt_const::tseg2_min
u32 tseg2_min
Definition gs_usb.h:208
-
gs_device_bt_const::tseg2_max
u32 tseg2_max
Definition gs_usb.h:209
-
gs_device_bt_const::brp_inc
u32 brp_inc
Definition gs_usb.h:213
-
gs_device_bt_const::fclk_can
u32 fclk_can
Definition gs_usb.h:205
-
gs_device_bt_const::tseg1_max
u32 tseg1_max
Definition gs_usb.h:207
-
gs_device_bt_const::tseg1_min
u32 tseg1_min
Definition gs_usb.h:206
-
gs_device_bt_const::feature
u32 feature
Definition gs_usb.h:204
-
gs_device_config
Definition gs_usb.h:175
-
gs_device_config::reserved3
u8 reserved3
Definition gs_usb.h:178
-
gs_device_config::reserved2
u8 reserved2
Definition gs_usb.h:177
-
gs_device_config::reserved1
u8 reserved1
Definition gs_usb.h:176
-
gs_device_config::sw_version
u32 sw_version
Definition gs_usb.h:180
-
gs_device_config::hw_version
u32 hw_version
Definition gs_usb.h:181
-
gs_device_config::icount
u8 icount
Definition gs_usb.h:179
-
gs_device_mode
Definition gs_usb.h:184
-
gs_device_mode::mode
u32 mode
Definition gs_usb.h:185
-
gs_device_mode::flags
u32 flags
Definition gs_usb.h:186
-
gs_device_state
Definition gs_usb.h:189
-
gs_device_state::txerr
u32 txerr
Definition gs_usb.h:192
-
gs_device_state::state
u32 state
Definition gs_usb.h:190
-
gs_device_state::rxerr
u32 rxerr
Definition gs_usb.h:191
-
gs_host_config
Definition gs_usb.h:167
-
gs_host_config::byte_order
u32 byte_order
Definition gs_usb.h:168
-
gs_host_frame
Definition gs_usb.h:216
-
gs_host_frame::timestamp_us
u32 timestamp_us
Definition gs_usb.h:227
-
gs_host_frame::channel
u8 channel
Definition gs_usb.h:221
-
gs_host_frame::data
u8 data[8]
Definition gs_usb.h:225
-
gs_host_frame::reserved
u8 reserved
Definition gs_usb.h:223
-
gs_host_frame::can_dlc
u8 can_dlc
Definition gs_usb.h:220
-
gs_host_frame::flags
u8 flags
Definition gs_usb.h:222
-
gs_host_frame::echo_id
u32 echo_id
Definition gs_usb.h:217
-
gs_host_frame::can_id
u32 can_id
Definition gs_usb.h:218
-
gs_tx_context
Definition gs_usb.h:231
-
gs_tx_context::dev
struct gs_can * dev
Definition gs_usb.h:232
-
gs_tx_context::echo_id
unsigned int echo_id
Definition gs_usb.h:233
+
231
+
+
232struct gs_tx_context {
+
233 struct gs_can *dev;
+
234 unsigned int echo_id;
+
235};
+
+
236
+
237#endif // __GS_USB_H__
+
u32
#define u32
Definition gs_usb.h:30
+
gs_can_state
gs_can_state
Definition gs_usb.h:158
+
GS_CAN_STATE_SLEEPING
@ GS_CAN_STATE_SLEEPING
Definition gs_usb.h:164
+
GS_CAN_STATE_ERROR_PASSIVE
@ GS_CAN_STATE_ERROR_PASSIVE
Definition gs_usb.h:161
+
GS_CAN_STATE_ERROR_ACTIVE
@ GS_CAN_STATE_ERROR_ACTIVE
Definition gs_usb.h:159
+
GS_CAN_STATE_STOPPED
@ GS_CAN_STATE_STOPPED
Definition gs_usb.h:163
+
GS_CAN_STATE_BUS_OFF
@ GS_CAN_STATE_BUS_OFF
Definition gs_usb.h:162
+
GS_CAN_STATE_ERROR_WARNING
@ GS_CAN_STATE_ERROR_WARNING
Definition gs_usb.h:160
+
__packed
struct gs_device_state __packed
+
gs_can_mode
gs_can_mode
Definition gs_usb.h:151
+
GS_CAN_MODE_START
@ GS_CAN_MODE_START
Definition gs_usb.h:155
+
GS_CAN_MODE_RESET
@ GS_CAN_MODE_RESET
Definition gs_usb.h:153
+
gs_usb_breq
gs_usb_breq
Definition gs_usb.h:138
+
GS_USB_BREQ_TIMESTAMP
@ GS_USB_BREQ_TIMESTAMP
Definition gs_usb.h:145
+
GS_USB_BREQ_HOST_FORMAT
@ GS_USB_BREQ_HOST_FORMAT
Definition gs_usb.h:139
+
GS_USB_BREQ_SET_USER_ID
@ GS_USB_BREQ_SET_USER_ID
Definition gs_usb.h:148
+
GS_USB_BREQ_BERR
@ GS_USB_BREQ_BERR
Definition gs_usb.h:142
+
GS_USB_BREQ_IDENTIFY
@ GS_USB_BREQ_IDENTIFY
Definition gs_usb.h:146
+
GS_USB_BREQ_GET_USER_ID
@ GS_USB_BREQ_GET_USER_ID
Definition gs_usb.h:147
+
GS_USB_BREQ_MODE
@ GS_USB_BREQ_MODE
Definition gs_usb.h:141
+
GS_USB_BREQ_BITTIMING
@ GS_USB_BREQ_BITTIMING
Definition gs_usb.h:140
+
GS_USB_BREQ_DEVICE_CONFIG
@ GS_USB_BREQ_DEVICE_CONFIG
Definition gs_usb.h:144
+
GS_USB_BREQ_BT_CONST
@ GS_USB_BREQ_BT_CONST
Definition gs_usb.h:143
+
u8
#define u8
Definition gs_usb.h:31
+
__attribute__
struct gs_tx_context __attribute__
Definition daq_hub.h:70
+
gs_device_bittiming
Definition gs_usb.h:196
+
gs_device_bittiming::brp
u32 brp
Definition gs_usb.h:201
+
gs_device_bittiming::sjw
u32 sjw
Definition gs_usb.h:200
+
gs_device_bittiming::phase_seg2
u32 phase_seg2
Definition gs_usb.h:199
+
gs_device_bittiming::phase_seg1
u32 phase_seg1
Definition gs_usb.h:198
+
gs_device_bittiming::prop_seg
u32 prop_seg
Definition gs_usb.h:197
+
gs_device_bt_const
Definition gs_usb.h:204
+
gs_device_bt_const::sjw_max
u32 sjw_max
Definition gs_usb.h:211
+
gs_device_bt_const::brp_max
u32 brp_max
Definition gs_usb.h:213
+
gs_device_bt_const::brp_min
u32 brp_min
Definition gs_usb.h:212
+
gs_device_bt_const::tseg2_min
u32 tseg2_min
Definition gs_usb.h:209
+
gs_device_bt_const::tseg2_max
u32 tseg2_max
Definition gs_usb.h:210
+
gs_device_bt_const::brp_inc
u32 brp_inc
Definition gs_usb.h:214
+
gs_device_bt_const::fclk_can
u32 fclk_can
Definition gs_usb.h:206
+
gs_device_bt_const::tseg1_max
u32 tseg1_max
Definition gs_usb.h:208
+
gs_device_bt_const::tseg1_min
u32 tseg1_min
Definition gs_usb.h:207
+
gs_device_bt_const::feature
u32 feature
Definition gs_usb.h:205
+
gs_device_config
Definition gs_usb.h:176
+
gs_device_config::reserved3
u8 reserved3
Definition gs_usb.h:179
+
gs_device_config::reserved2
u8 reserved2
Definition gs_usb.h:178
+
gs_device_config::reserved1
u8 reserved1
Definition gs_usb.h:177
+
gs_device_config::sw_version
u32 sw_version
Definition gs_usb.h:181
+
gs_device_config::hw_version
u32 hw_version
Definition gs_usb.h:182
+
gs_device_config::icount
u8 icount
Definition gs_usb.h:180
+
gs_device_mode
Definition gs_usb.h:185
+
gs_device_mode::mode
u32 mode
Definition gs_usb.h:186
+
gs_device_mode::flags
u32 flags
Definition gs_usb.h:187
+
gs_device_state
Definition gs_usb.h:190
+
gs_device_state::txerr
u32 txerr
Definition gs_usb.h:193
+
gs_device_state::state
u32 state
Definition gs_usb.h:191
+
gs_device_state::rxerr
u32 rxerr
Definition gs_usb.h:192
+
gs_host_config
Definition gs_usb.h:168
+
gs_host_config::byte_order
u32 byte_order
Definition gs_usb.h:169
+
gs_host_frame
Definition gs_usb.h:217
+
gs_host_frame::timestamp_us
u32 timestamp_us
Definition gs_usb.h:228
+
gs_host_frame::channel
u8 channel
Definition gs_usb.h:222
+
gs_host_frame::data
u8 data[8]
Definition gs_usb.h:226
+
gs_host_frame::reserved
u8 reserved
Definition gs_usb.h:224
+
gs_host_frame::can_dlc
u8 can_dlc
Definition gs_usb.h:221
+
gs_host_frame::flags
u8 flags
Definition gs_usb.h:223
+
gs_host_frame::echo_id
u32 echo_id
Definition gs_usb.h:218
+
gs_host_frame::can_id
u32 can_id
Definition gs_usb.h:219
+
gs_tx_context
Definition gs_usb.h:232
+
gs_tx_context::dev
struct gs_can * dev
Definition gs_usb.h:233
+
gs_tx_context::echo_id
unsigned int echo_id
Definition gs_usb.h:234
diff --git a/i2c_8c.html b/i2c_8c.html index ab97f356..51db435b 100644 --- a/i2c_8c.html +++ b/i2c_8c.html @@ -103,13 +103,13 @@ bool PHAL_initI2C (I2C_TypeDef *i2c)  Enables the I2C3 peripheral by enabling the peripheral clock and configuring I2C timing.
  -bool PHAL_I2C_gen_start (I2C_TypeDef *i2c, uint8_t address, uint8_t length, I2CDirection_t mode) +bool PHAL_I2C_gen_start (I2C_TypeDef *i2c, uint8_t address, uint8_t length, I2CDirection_t mode)  Generates an I2C start command, call before reading or writing.
  -bool PHAL_I2C_write (I2C_TypeDef *i2c, uint8_t data) +bool PHAL_I2C_write (I2C_TypeDef *i2c, uint8_t data)  Sends a byte over I2C Call PHAL_I2C_gen_start before using this command.
  -bool PHAL_I2C_write_multi (I2C_TypeDef *i2c, uint8_t *data, uint8_t size) +bool PHAL_I2C_write_multi (I2C_TypeDef *i2c, uint8_t *data, uint8_t size)  Sends multiple bytes over I2C Call PHAL_I2C_gen_start before using this command.
  bool PHAL_I2C_read (I2C_TypeDef *i2c, uint8_t *data_a) diff --git a/i2c_8h.html b/i2c_8h.html index 25908ea7..c8555e20 100644 --- a/i2c_8h.html +++ b/i2c_8h.html @@ -119,13 +119,13 @@ bool PHAL_initI2C (I2C_TypeDef *i2c)  Enables the I2C3 peripheral by enabling the peripheral clock and configuring I2C timing.
  -bool PHAL_I2C_gen_start (I2C_TypeDef *i2c, uint8_t address, uint8_t length, I2CDirection_t mode) +bool PHAL_I2C_gen_start (I2C_TypeDef *i2c, uint8_t address, uint8_t length, I2CDirection_t mode)  Generates an I2C start command, call before reading or writing.
  -bool PHAL_I2C_write (I2C_TypeDef *i2c, uint8_t data) +bool PHAL_I2C_write (I2C_TypeDef *i2c, uint8_t data)  Sends a byte over I2C Call PHAL_I2C_gen_start before using this command.
  -bool PHAL_I2C_write_multi (I2C_TypeDef *i2c, uint8_t *data, uint8_t size) +bool PHAL_I2C_write_multi (I2C_TypeDef *i2c, uint8_t *data, uint8_t size)  Sends multiple bytes over I2C Call PHAL_I2C_gen_start before using this command.
  bool PHAL_I2C_read (I2C_TypeDef *i2c, uint8_t *data_a) diff --git a/i2c_8h_source.html b/i2c_8h_source.html index b8c4a933..24c40f63 100644 --- a/i2c_8h_source.html +++ b/i2c_8h_source.html @@ -110,11 +110,11 @@
24
31bool PHAL_initI2C(I2C_TypeDef *i2c);
32
-
42bool PHAL_I2C_gen_start(I2C_TypeDef *i2c, uint8_t address, uint8_t length, I2CDirection_t mode);
+
42bool PHAL_I2C_gen_start(I2C_TypeDef *i2c, uint8_t address, uint8_t length, I2CDirection_t mode);
43
-
51bool PHAL_I2C_write(I2C_TypeDef *i2c, uint8_t data);
+
51bool PHAL_I2C_write(I2C_TypeDef *i2c, uint8_t data);
52
-
61bool PHAL_I2C_write_multi(I2C_TypeDef *i2c, uint8_t* data, uint8_t size);
+
61bool PHAL_I2C_write_multi(I2C_TypeDef *i2c, uint8_t* data, uint8_t size);
62
70bool PHAL_I2C_read(I2C_TypeDef *i2c, uint8_t* data_a);
71
@@ -123,6 +123,8 @@
86bool PHAL_I2C_gen_stop(I2C_TypeDef *i2c);
87
88#endif
+
mode
u32 mode
Definition gs_usb.h:0
+
data
u8 data[8]
Definition gs_usb.h:8
PHAL_I2C_read
bool PHAL_I2C_read(I2C_TypeDef *i2c, uint8_t *data_a)
Reads a byte over I2C Call PHAL_I2C_gen_start before using this command.
Definition i2c.c:83
PHAL_I2C_gen_start
bool PHAL_I2C_gen_start(I2C_TypeDef *i2c, uint8_t address, uint8_t length, I2CDirection_t mode)
Generates an I2C start command, call before reading or writing.
Definition i2c.c:36
I2CDirection_t
I2CDirection_t
Definition i2c.h:20
diff --git a/i2c__alt_8c.html b/i2c__alt_8c.html index 9349cb95..d92ae4b1 100644 --- a/i2c__alt_8c.html +++ b/i2c__alt_8c.html @@ -100,9 +100,9 @@ Functions

int PHAL_I2C_init (I2C_TypeDef *instance, i2c_handle_t *handle, uint32_t freq, const uint32_t fck)   -int PHAL_I2C_write_a (I2C_TypeDef *instance, uint8_t addr, const uint8_t *data, uint8_t len, bool stop, bool force) +int PHAL_I2C_write_a (I2C_TypeDef *instance, uint8_t addr, const uint8_t *data, uint8_t len, bool stop, bool force)   -int PHAL_I2C_read_a (I2C_TypeDef *instance, uint8_t addr, uint8_t *data, uint8_t len, bool stop, bool force) +int PHAL_I2C_read_a (I2C_TypeDef *instance, uint8_t addr, uint8_t *data, uint8_t len, bool stop, bool force)   int PHAL_I2C_stop (I2C_TypeDef *instance)   diff --git a/i2c__alt_8h.html b/i2c__alt_8h.html index 0a7b6a00..1bca6ec0 100644 --- a/i2c__alt_8h.html +++ b/i2c__alt_8h.html @@ -145,9 +145,9 @@ Functions

int PHAL_I2C_init (I2C_TypeDef *instance, i2c_handle_t *handle, uint32_t freq, const uint32_t fck)   -int PHAL_I2C_write_a (I2C_TypeDef *instance, uint8_t addr, const uint8_t *data, uint8_t len, bool stop, bool force) +int PHAL_I2C_write_a (I2C_TypeDef *instance, uint8_t addr, const uint8_t *data, uint8_t len, bool stop, bool force)   -int PHAL_I2C_read_a (I2C_TypeDef *instance, uint8_t addr, uint8_t *data, uint8_t len, bool stop, bool force) +int PHAL_I2C_read_a (I2C_TypeDef *instance, uint8_t addr, uint8_t *data, uint8_t len, bool stop, bool force)   int PHAL_I2C_stop (I2C_TypeDef *instance)   @@ -178,8 +178,9 @@

.dir=0b0, .mem_inc=true, .periph_inc=false, .mem_to_mem=false, \
.priority=(priority_), .mem_size=0b00, .periph_size=0b00, \
.tx_isr_en=true, .dma_chan_request=0b0011, .channel_idx=7, \
-
.periph=DMA1, .channel=DMA1_Channel7, .request=DMA1_CSELR}
+
.periph=DMA1, .channel=DMA1_Channel7, .request=DMA1_CSELR}
mem_size
uint16_t mem_size[MAX_PAGES]
Size of file in bytes (actual)
Definition eeprom_spi.h:4
+
channel
u8 channel
Definition gs_usb.h:4
@@ -206,7 +207,7 @@

.dir=0b1, .mem_inc=true, .periph_inc=false, .mem_to_mem=false, \
.priority=(priority_), .mem_size=0b00, .periph_size=0b00, \
.tx_isr_en=true, .dma_chan_request=0b0011, .channel_idx=6, \
-
.periph=DMA1, .channel=DMA1_Channel6, .request=DMA1_CSELR}
+
.periph=DMA1, .channel=DMA1_Channel6, .request=DMA1_CSELR}
@@ -233,7 +234,7 @@

.dir=0b0, .mem_inc=true, .periph_inc=false, .mem_to_mem=false, \
.priority=(priority_), .mem_size=0b00, .periph_size=0b00, \
.tx_isr_en=true, .dma_chan_request=0b0011, .channel_idx=3, \
-
.periph=DMA1, .channel=DMA1_Channel3, .request=DMA1_CSELR}
+
.periph=DMA1, .channel=DMA1_Channel3, .request=DMA1_CSELR}
@@ -260,7 +261,7 @@

.dir=0b1, .mem_inc=true, .periph_inc=false, .mem_to_mem=false, \
.priority=(priority_), .mem_size=0b00, .periph_size=0b00, \
.tx_isr_en=true, .dma_chan_request=0b0011, .channel_idx=2, \
-
.periph=DMA1, .channel=DMA1_Channel2, .request=DMA1_CSELR}
+
.periph=DMA1, .channel=DMA1_Channel2, .request=DMA1_CSELR}
diff --git a/i2c__alt_8h_source.html b/i2c__alt_8h_source.html index 6fa84e62..fe5db119 100644 --- a/i2c__alt_8h_source.html +++ b/i2c__alt_8h_source.html @@ -132,8 +132,8 @@
37
38// Prototypes
39int PHAL_I2C_init(I2C_TypeDef* instance, i2c_handle_t* handle, uint32_t freq, const uint32_t fck);
-
40int PHAL_I2C_write_a(I2C_TypeDef* instance, uint8_t addr, const uint8_t* data, uint8_t len, bool stop, bool force);
-
41int PHAL_I2C_read_a(I2C_TypeDef* instance, uint8_t addr, uint8_t* data, uint8_t len, bool stop, bool force);
+
40int PHAL_I2C_write_a(I2C_TypeDef* instance, uint8_t addr, const uint8_t* data, uint8_t len, bool stop, bool force);
+
41int PHAL_I2C_read_a(I2C_TypeDef* instance, uint8_t addr, uint8_t* data, uint8_t len, bool stop, bool force);
42int PHAL_I2C_stop(I2C_TypeDef* instance);
43int PHAL_I2C_check_state(void);
44
@@ -178,6 +178,7 @@
76
77#endif
+
data
u8 data[8]
Definition gs_usb.h:8
PHAL_I2C_check_state
int PHAL_I2C_check_state(void)
Definition i2c_alt.c:160
E_BAD_BUSY
@ E_BAD_BUSY
Definition i2c_alt.h:19
E_ARLO
@ E_ARLO
Definition i2c_alt.h:20
diff --git a/l4__testing_2can_2can__parse_8h_source.html b/l4__testing_2can_2can__parse_8h_source.html index 585dbcca..427a1e3d 100644 --- a/l4__testing_2can_2can__parse_8h_source.html +++ b/l4__testing_2can_2can__parse_8h_source.html @@ -362,14 +362,14 @@
248 uint64_t test_sig5_3: 32;
249 } test_msg5_2;
250 struct {
-
251 uint64_t data: 8;
+
251 uint64_t data: 8;
252 } test_stale;
253 struct {
254 uint64_t car_state2: 8;
255 } car_state2;
256 struct {
257 uint64_t cmd: 8;
-
258 uint64_t data: 32;
+
258 uint64_t data: 32;
259 } l4_testing_bl_cmd;
260 struct {
261 uint64_t idx: 16;
@@ -402,7 +402,7 @@
288 uint64_t daq_command: 64;
289 } daq_command_TEST_NODE;
290 uint8_t raw_data[8];
-
291} __attribute__((packed)) CanParsedData_t;
+
291} __attribute__((packed)) CanParsedData_t;
292/* END AUTO MESSAGE STRUCTURE */
293
294// contains most up to date received
@@ -426,7 +426,7 @@
312 } car_state2;
313 struct {
314 uint8_t cmd;
-
315 uint32_t data;
+
315 uint32_t data;
316 } l4_testing_bl_cmd;
317 struct {
318 uint16_t idx;
@@ -494,7 +494,8 @@
l4_testing_bl_cmd_CALLBACK
void l4_testing_bl_cmd_CALLBACK(CanParsedData_t *msg_data_a)
Definition main.c:484
car_state_t
car_state_t
Definition can_parse.h:230
cmd
uint8_t cmd[NXT_STR_SIZE]
Definition main.c:541
-
__attribute__
struct eeprom __attribute__
Definition daq_hub.h:70
+
data
u8 data[8]
Definition gs_usb.h:8
+
__attribute__
struct gs_tx_context __attribute__
Definition daq_hub.h:70
car_state2_t
car_state2_t
Definition can_parse.h:189
CAR_STATE2_LIGHTSPEED
@ CAR_STATE2_LIGHTSPEED
Definition can_parse.h:193
CAR_STATE2_FLIPPED
@ CAR_STATE2_FLIPPED
Definition can_parse.h:191
diff --git a/l4__testing_2daq_2daq_8h_source.html b/l4__testing_2daq_2daq_8h_source.html index 398a0a39..3ec57f7a 100644 --- a/l4__testing_2daq_2daq_8h_source.html +++ b/l4__testing_2daq_2daq_8h_source.html @@ -128,7 +128,7 @@
44 float charge_current;
45 float charge_voltage;
46 int16_t trim;
-
47} __attribute__((packed)) config_t;
+
47} __attribute__((packed)) config_t;
48
49extern config_t config;
50
@@ -140,7 +140,7 @@
56#endif
daqPeriodic
void daqPeriodic()
Definition daq.c:50
daqInit
bool daqInit(q_handle_t *tx_a)
Definition daq.c:42
-
__attribute__
struct eeprom __attribute__
Definition daq_hub.h:70
+
__attribute__
struct gs_tx_context __attribute__
Definition daq_hub.h:70
config
config_t config
Definition daq.c:37
q_handle_t
Definition queue.h:25
__attribute__::green_on
uint8_t green_on
Definition daq.h:42
diff --git a/main__module_2can_2can__parse_8h_source.html b/main__module_2can_2can__parse_8h_source.html index 0f52008b..3c1f34f9 100644 --- a/main__module_2can_2can__parse_8h_source.html +++ b/main__module_2can_2can__parse_8h_source.html @@ -574,7 +574,7 @@
442 } LWS_Standard;
443 struct {
444 uint64_t cmd: 8;
-
445 uint64_t data: 32;
+
445 uint64_t data: 32;
446 } main_module_bl_cmd;
447 struct {
448 uint64_t pack_current: 16;
@@ -619,7 +619,7 @@
487 uint64_t daq_command: 64;
488 } daq_command_MAIN_MODULE;
489 uint8_t raw_data[8];
-
490} __attribute__((packed)) CanParsedData_t;
+
490} __attribute__((packed)) CanParsedData_t;
491/* END AUTO MESSAGE STRUCTURE */
492
493// contains most up to date received
@@ -662,7 +662,7 @@
530 } LWS_Standard;
531 struct {
532 uint8_t cmd;
-
533 uint32_t data;
+
533 uint32_t data;
534 } main_module_bl_cmd;
535 struct {
536 int16_t pack_current;
@@ -760,7 +760,8 @@
CAR_STATE_RESET
@ CAR_STATE_RESET
Definition can_parse.h:238
CAR_STATE_CONSTANT_TORQUE
@ CAR_STATE_CONSTANT_TORQUE
Definition can_parse.h:240
cmd
uint8_t cmd[NXT_STR_SIZE]
Definition main.c:541
-
__attribute__
struct eeprom __attribute__
Definition daq_hub.h:70
+
data
u8 data[8]
Definition gs_usb.h:8
+
__attribute__
struct gs_tx_context __attribute__
Definition daq_hub.h:70
rear_right_last_link_error_t
rear_right_last_link_error_t
Definition can_parse.h:315
REAR_RIGHT_LAST_LINK_ERROR_NONE
@ REAR_RIGHT_LAST_LINK_ERROR_NONE
Definition can_parse.h:316
REAR_RIGHT_LAST_LINK_ERROR_CMD_TIMEOUT
@ REAR_RIGHT_LAST_LINK_ERROR_CMD_TIMEOUT
Definition can_parse.h:318
diff --git a/main__module_2main_8h_source.html b/main__module_2main_8h_source.html index 7abbf56f..a3811b67 100644 --- a/main__module_2main_8h_source.html +++ b/main__module_2main_8h_source.html @@ -260,7 +260,7 @@
177 uint16_t load_l;
178 uint16_t load_r;
179 uint16_t therm_mcu;
-
180}__attribute__((packed)) ADCReadings_t;
+
180}__attribute__((packed)) ADCReadings_t;
181volatile extern ADCReadings_t adc_readings;
182
183void canTxSendToBack(CanMsgTypeDef_t *msg);
@@ -268,8 +268,8 @@
185#endif
adc_readings
volatile ADCReadings_t adc_readings
Definition main.c:113
canTxSendToBack
void canTxSendToBack(CanMsgTypeDef_t *msg)
Definition main.c:116
-
__attribute__
struct eeprom __attribute__
Definition daq_hub.h:70
msg
char msg[100]
Definition main.c:105
+
__attribute__
struct gs_tx_context __attribute__
Definition daq_hub.h:70
can.h
CanMsgTypeDef_t
Definition can.h:31
__attribute__::v_mc
uint16_t v_mc
Definition main.h:172
diff --git a/pdu_2can_2can__parse_8h_source.html b/pdu_2can_2can__parse_8h_source.html index 21a1229e..18d2116c 100644 --- a/pdu_2can_2can__parse_8h_source.html +++ b/pdu_2can_2can__parse_8h_source.html @@ -326,7 +326,7 @@
220 } daq_response_PDU;
221 struct {
222 uint64_t cmd: 8;
-
223 uint64_t data: 32;
+
223 uint64_t data: 32;
224 } pdu_bl_cmd;
225 struct {
226 uint64_t dt_pump: 8;
@@ -370,7 +370,7 @@
264 uint64_t daq_command: 64;
265 } daq_command_PDU;
266 uint8_t raw_data[8];
-
267} __attribute__((packed)) CanParsedData_t;
+
267} __attribute__((packed)) CanParsedData_t;
268/* END AUTO MESSAGE STRUCTURE */
269
270// contains most up to date received
@@ -379,7 +379,7 @@
273typedef struct {
274 struct {
275 uint8_t cmd;
-
276 uint32_t data;
+
276 uint32_t data;
277 } pdu_bl_cmd;
278 struct {
279 uint8_t dt_pump;
@@ -473,7 +473,8 @@
CAR_STATE_RESET
@ CAR_STATE_RESET
Definition can_parse.h:238
CAR_STATE_CONSTANT_TORQUE
@ CAR_STATE_CONSTANT_TORQUE
Definition can_parse.h:240
cmd
uint8_t cmd[NXT_STR_SIZE]
Definition main.c:541
-
__attribute__
struct eeprom __attribute__
Definition daq_hub.h:70
+
data
u8 data[8]
Definition gs_usb.h:8
+
__attribute__
struct gs_tx_context __attribute__
Definition daq_hub.h:70
daq_command_PDU_CALLBACK
void daq_command_PDU_CALLBACK(CanMsgTypeDef_t *msg_header_a)
Definition daq.c:46
cooling_driver_request_CALLBACK
void cooling_driver_request_CALLBACK(CanParsedData_t *msg_data_a)
Definition cooling.c:46
can.h
diff --git a/pdu_2main_8h_source.html b/pdu_2main_8h_source.html index 927f8eaa..2d9ae947 100644 --- a/pdu_2main_8h_source.html +++ b/pdu_2main_8h_source.html @@ -342,15 +342,15 @@
259 uint16_t lv_3v3_v_sense;
260 uint16_t external_therm;
261 uint16_t internal_therm;
-
262}__attribute__((packed)) ADCReadings_t;
+
262}__attribute__((packed)) ADCReadings_t;
263volatile extern ADCReadings_t adc_readings;
264
265void canTxSendToBack(CanMsgTypeDef_t *msg);
266#endif
adc_readings
volatile ADCReadings_t adc_readings
Definition main.c:113
canTxSendToBack
void canTxSendToBack(CanMsgTypeDef_t *msg)
Definition main.c:116
-
__attribute__
struct eeprom __attribute__
Definition daq_hub.h:70
msg
char msg[100]
Definition main.c:105
+
__attribute__
struct gs_tx_context __attribute__
Definition daq_hub.h:70
can.h
CanMsgTypeDef_t
Definition can.h:31
__attribute__::lv_24_v_sense
uint16_t lv_24_v_sense
Definition main.h:255
diff --git a/phal__F4__F7_2adc_2adc_8h_source.html b/phal__F4__F7_2adc_2adc_8h_source.html index a8c89e48..b84349d1 100644 --- a/phal__F4__F7_2adc_2adc_8h_source.html +++ b/phal__F4__F7_2adc_2adc_8h_source.html @@ -163,7 +163,7 @@
68
69typedef struct {
-
70 uint32_t channel; // not the GPIO channel, use the ADC channel
+
70 uint32_t channel; // not the GPIO channel, use the ADC channel
71 uint32_t rank; // order at which the channels will be polled, starting at 1
72 ADCChannelSampleCycles_t sampling_time;
73} ADCChannelConfig_t;
@@ -189,8 +189,8 @@
115
116
117#endif
+
channel
u8 channel
Definition gs_usb.h:4
config
config_t config
Definition daq.c:37
-
can_test.channel
channel
Definition can_test.py:5
PHAL_startADC
bool PHAL_startADC(ADC_TypeDef *adc)
Starts the ADC conversions, requires PHAL_initADC to be called prior.
Definition adc.c:136
PHAL_readADC
uint16_t PHAL_readADC(ADC_TypeDef *adc)
Reads the ADC data register.
Definition adc.c:148
ADCDMAMode_t
ADCDMAMode_t
Definition adc.h:38
diff --git a/phal__F4__F7_2flash_2flash_8c.html b/phal__F4__F7_2flash_2flash_8c.html index 34b4b77e..c408b309 100644 --- a/phal__F4__F7_2flash_2flash_8c.html +++ b/phal__F4__F7_2flash_2flash_8c.html @@ -104,7 +104,7 @@ uint8_t PHAL_flashWriteU64 (uint32_t Address, uint64_t Data)  Writes 64 bits to flash memory.
  -uint8_t PHAL_flashWriteU32_Buffered (uint32_t Address, uint32_t *data, uint32_t count) +uint8_t PHAL_flashWriteU32_Buffered (uint32_t Address, uint32_t *data, uint32_t count)   uint8_t PHAL_flashErasePage (uint8_t page)   diff --git a/phal__F4__F7_2flash_2flash_8h.html b/phal__F4__F7_2flash_2flash_8h.html index 034f56b5..e5004c33 100644 --- a/phal__F4__F7_2flash_2flash_8h.html +++ b/phal__F4__F7_2flash_2flash_8h.html @@ -122,9 +122,9 @@   uint8_t PHAL_flashWriteU32 (uint32_t address, uint32_t value)   -uint8_t PHAL_flashWriteU32_Buffered (uint32_t Address, uint32_t *data, uint32_t count) +uint8_t PHAL_flashWriteU32_Buffered (uint32_t Address, uint32_t *data, uint32_t count)   -uint8_t PHAL_flashWriteU64 (uint32_t address, uint64_t data) +uint8_t PHAL_flashWriteU64 (uint32_t address, uint64_t data)  Writes 64 bits to flash memory.
  uint8_t PHAL_flashErasePage (uint8_t page) diff --git a/phal__F4__F7_2flash_2flash_8h_source.html b/phal__F4__F7_2flash_2flash_8h_source.html index ed1a1ca5..616c930e 100644 --- a/phal__F4__F7_2flash_2flash_8h_source.html +++ b/phal__F4__F7_2flash_2flash_8h_source.html @@ -152,13 +152,14 @@
69uint32_t PHAL_flashReadU32(uint32_t addr);
70
71uint8_t PHAL_flashWriteU32(uint32_t address, uint32_t value);
-
72uint8_t PHAL_flashWriteU32_Buffered(uint32_t Address, uint32_t *data, uint32_t count);
+
72uint8_t PHAL_flashWriteU32_Buffered(uint32_t Address, uint32_t *data, uint32_t count);
73
-
74uint8_t PHAL_flashWriteU64(uint32_t address, uint64_t data);
+
74uint8_t PHAL_flashWriteU64(uint32_t address, uint64_t data);
75uint8_t PHAL_flashErasePage(uint8_t page);
76uint8_t PHAL_flashErase(uint32_t *addr, uint32_t words);
77
78#endif
+
data
u8 data[8]
Definition gs_usb.h:8
PHAL_flashWriteU32_Buffered
uint8_t PHAL_flashWriteU32_Buffered(uint32_t Address, uint32_t *data, uint32_t count)
Definition flash.c:137
PHAL_flashReadU32
uint32_t PHAL_flashReadU32(uint32_t addr)
Definition flash.c:63
PHAL_flashWriteU64
uint8_t PHAL_flashWriteU64(uint32_t address, uint64_t data)
Writes 64 bits to flash memory.
Definition flash.c:46
diff --git a/phal__F4__F7_2gpio_2gpio_8h_source.html b/phal__F4__F7_2gpio_2gpio_8h_source.html index d41db82d..62119dff 100644 --- a/phal__F4__F7_2gpio_2gpio_8h_source.html +++ b/phal__F4__F7_2gpio_2gpio_8h_source.html @@ -274,75 +274,76 @@
219
220#define GPIO_INIT_USART2TX_PD5 GPIO_INIT_AF(GPIOD, 5, 7, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_PUSH_PULL, GPIO_INPUT_OPEN_DRAIN)
221#define GPIO_INIT_USART2RX_PD6 GPIO_INIT_AF(GPIOD, 6, 7, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_OPEN_DRAIN, GPIO_INPUT_OPEN_DRAIN)
-
222#define GPIO_INIT_USART3TX_PC10 GPIO_INIT_AF(GPIOC, 10, 7, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_PUSH_PULL, GPIO_INPUT_OPEN_DRAIN)
-
223#define GPIO_INIT_USART3RX_PC11 GPIO_INIT_AF(GPIOC, 11, 7, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_OPEN_DRAIN, GPIO_INPUT_OPEN_DRAIN)
-
224#endif
-
225
-
226// SDIO
-
227#define GPIO_INIT_SDIO_CLK GPIO_INIT_AF(GPIOC, 12, 12, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_PUSH_PULL, GPIO_INPUT_PULL_UP)
-
228#define GPIO_INIT_SDIO_CMD GPIO_INIT_AF(GPIOD, 2, 12, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_PUSH_PULL, GPIO_INPUT_PULL_UP)
-
229#define GPIO_INIT_SDIO_DT0 GPIO_INIT_AF(GPIOC, 8, 12, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_PUSH_PULL, GPIO_INPUT_PULL_UP)
-
230#define GPIO_INIT_SDIO_DT1 GPIO_INIT_AF(GPIOC, 9, 12, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_PUSH_PULL, GPIO_INPUT_PULL_UP)
-
231#define GPIO_INIT_SDIO_DT2 GPIO_INIT_AF(GPIOC, 10, 12, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_PUSH_PULL, GPIO_INPUT_PULL_UP)
-
232#define GPIO_INIT_SDIO_DT3 GPIO_INIT_AF(GPIOC, 11, 12, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_PUSH_PULL, GPIO_INPUT_PULL_UP)
-
233
-
234#ifdef STM32F732xx
-
235//CAN
-
236#define GPIO_INIT_CANRX_PA11 GPIO_INIT_AF(GPIOA, 11, 9, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_OPEN_DRAIN, GPIO_INPUT_OPEN_DRAIN)
-
237#define GPIO_INIT_CANTX_PA12 GPIO_INIT_AF(GPIOA, 12, 9, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_PUSH_PULL, GPIO_INPUT_OPEN_DRAIN)
-
238
+
222
+
223#define GPIO_INIT_USART6TX_PC6 GPIO_INIT_AF(GPIOC, 6, 8, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_PUSH_PULL, GPIO_INPUT_OPEN_DRAIN)
+
224#define GPIO_INIT_USART6RX_PC7 GPIO_INIT_AF(GPIOC, 7, 8, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_OPEN_DRAIN, GPIO_INPUT_OPEN_DRAIN)
+
225#endif
+
226
+
227// SDIO
+
228#define GPIO_INIT_SDIO_CLK GPIO_INIT_AF(GPIOC, 12, 12, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_PUSH_PULL, GPIO_INPUT_PULL_UP)
+
229#define GPIO_INIT_SDIO_CMD GPIO_INIT_AF(GPIOD, 2, 12, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_PUSH_PULL, GPIO_INPUT_PULL_UP)
+
230#define GPIO_INIT_SDIO_DT0 GPIO_INIT_AF(GPIOC, 8, 12, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_PUSH_PULL, GPIO_INPUT_PULL_UP)
+
231#define GPIO_INIT_SDIO_DT1 GPIO_INIT_AF(GPIOC, 9, 12, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_PUSH_PULL, GPIO_INPUT_PULL_UP)
+
232#define GPIO_INIT_SDIO_DT2 GPIO_INIT_AF(GPIOC, 10, 12, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_PUSH_PULL, GPIO_INPUT_PULL_UP)
+
233#define GPIO_INIT_SDIO_DT3 GPIO_INIT_AF(GPIOC, 11, 12, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_PUSH_PULL, GPIO_INPUT_PULL_UP)
+
234
+
235#ifdef STM32F732xx
+
236//CAN
+
237#define GPIO_INIT_CANRX_PA11 GPIO_INIT_AF(GPIOA, 11, 9, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_OPEN_DRAIN, GPIO_INPUT_OPEN_DRAIN)
+
238#define GPIO_INIT_CANTX_PA12 GPIO_INIT_AF(GPIOA, 12, 9, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_PUSH_PULL, GPIO_INPUT_OPEN_DRAIN)
239
-
240//SPI
-
241
+
240
+
241//SPI
242
243
-
244//UART/USART
-
245#define GPIO_INIT_UART4TX_PA0 GPIO_INIT_AF(GPIOA, 0, 8, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_PUSH_PULL, GPIO_INPUT_OPEN_DRAIN)
-
246#define GPIO_INIT_UART4RX_PA1 GPIO_INIT_AF(GPIOA, 1, 8, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_OPEN_DRAIN, GPIO_INPUT_OPEN_DRAIN)
-
247#endif
-
248
-
258bool PHAL_initGPIO(GPIOInitConfig_t config[], uint8_t config_len);
-
259
-
268inline bool PHAL_readGPIO(GPIO_TypeDef *bank, uint8_t pin);
-
269
-
277inline void PHAL_writeGPIO(GPIO_TypeDef *bank, uint8_t pin, bool value);
-
278inline void PHAL_toggleGPIO(GPIO_TypeDef *bank, uint8_t pin);
-
279
-
-
280inline bool PHAL_readGPIO(GPIO_TypeDef *bank, uint8_t pin)
-
281{
-
282 return (bank->IDR >> pin) & 0b1;
-
283}
+
244
+
245//UART/USART
+
246#define GPIO_INIT_UART4TX_PA0 GPIO_INIT_AF(GPIOA, 0, 8, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_PUSH_PULL, GPIO_INPUT_OPEN_DRAIN)
+
247#define GPIO_INIT_UART4RX_PA1 GPIO_INIT_AF(GPIOA, 1, 8, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_OPEN_DRAIN, GPIO_INPUT_OPEN_DRAIN)
+
248#endif
+
249
+
259bool PHAL_initGPIO(GPIOInitConfig_t config[], uint8_t config_len);
+
260
+
269inline bool PHAL_readGPIO(GPIO_TypeDef *bank, uint8_t pin);
+
270
+
278inline void PHAL_writeGPIO(GPIO_TypeDef *bank, uint8_t pin, bool value);
+
279inline void PHAL_toggleGPIO(GPIO_TypeDef *bank, uint8_t pin);
+
280
+
+
281inline bool PHAL_readGPIO(GPIO_TypeDef *bank, uint8_t pin)
+
282{
+
283 return (bank->IDR >> pin) & 0b1;
+
284}
-
284
-
-
285inline void PHAL_writeGPIO(GPIO_TypeDef *bank, uint8_t pin, bool value)
-
286{
-
287 bank->BSRR |= 1 << (pin + (16 * (!value))); // BSRR has "set" as bottom 16 bits and "reset" as top 16
-
288}
+
285
+
+
286inline void PHAL_writeGPIO(GPIO_TypeDef *bank, uint8_t pin, bool value)
+
287{
+
288 bank->BSRR |= 1 << ((!value << 4) | pin); // BSRR has "set" as bottom 16 bits and "reset" as top 16
+
289}
-
289
-
-
290inline void PHAL_toggleGPIO(GPIO_TypeDef *bank, uint8_t pin)
-
291{
-
292 PHAL_writeGPIO(bank, pin, !PHAL_readGPIO(bank, pin));
-
293}
+
290
+
+
291inline void PHAL_toggleGPIO(GPIO_TypeDef *bank, uint8_t pin)
+
292{
+
293 PHAL_writeGPIO(bank, pin, !PHAL_readGPIO(bank, pin));
+
294}
-
294
-
295#endif
+
295
+
296#endif
config
config_t config
Definition daq.c:37
-
PHAL_readGPIO
bool PHAL_readGPIO(GPIO_TypeDef *bank, uint8_t pin)
Read the state of the input register for the specific GPIO pin.
Definition gpio.h:280
+
PHAL_readGPIO
bool PHAL_readGPIO(GPIO_TypeDef *bank, uint8_t pin)
Read the state of the input register for the specific GPIO pin.
Definition gpio.h:281
GPIOOutputPull_t
GPIOOutputPull_t
Output drive mode selection.
Definition gpio.h:79
GPIO_OUTPUT_OPEN_DRAIN
@ GPIO_OUTPUT_OPEN_DRAIN
Definition gpio.h:81
GPIO_OUTPUT_PUSH_PULL
@ GPIO_OUTPUT_PUSH_PULL
Definition gpio.h:80
-
PHAL_writeGPIO
void PHAL_writeGPIO(GPIO_TypeDef *bank, uint8_t pin, bool value)
Write a logic value to an output pin.
Definition gpio.h:285
+
PHAL_writeGPIO
void PHAL_writeGPIO(GPIO_TypeDef *bank, uint8_t pin, bool value)
Write a logic value to an output pin.
Definition gpio.h:286
GPIOPinType_t
GPIOPinType_t
Configuration type for GPIO Pin.
Definition gpio.h:57
GPIO_TYPE_AF
@ GPIO_TYPE_AF
Definition gpio.h:60
GPIO_TYPE_INPUT
@ GPIO_TYPE_INPUT
Definition gpio.h:58
GPIO_TYPE_OUTPUT
@ GPIO_TYPE_OUTPUT
Definition gpio.h:59
GPIO_TYPE_ANALOG
@ GPIO_TYPE_ANALOG
Definition gpio.h:61
PHAL_initGPIO
bool PHAL_initGPIO(GPIOInitConfig_t config[], uint8_t config_len)
Initilize the GPIO perpheral given a list of configuration fields for all of the GPIO pins....
Definition gpio.c:15
-
PHAL_toggleGPIO
void PHAL_toggleGPIO(GPIO_TypeDef *bank, uint8_t pin)
Definition gpio.h:290
+
PHAL_toggleGPIO
void PHAL_toggleGPIO(GPIO_TypeDef *bank, uint8_t pin)
Definition gpio.h:291
GPIOInputPull_t
GPIOInputPull_t
Enable internal pullup/down resistors.
Definition gpio.h:88
GPIO_INPUT_PULL_UP
@ GPIO_INPUT_PULL_UP
Definition gpio.h:90
GPIO_INPUT_OPEN_DRAIN
@ GPIO_INPUT_OPEN_DRAIN
Definition gpio.h:89
diff --git a/phal__F4__F7_2spi_2spi_8c.html b/phal__F4__F7_2spi_2spi_8c.html index 0a465646..8e8bfb1f 100644 --- a/phal__F4__F7_2spi_2spi_8c.html +++ b/phal__F4__F7_2spi_2spi_8c.html @@ -107,12 +107,16 @@ bool PHAL_SPI_transfer_noDMA (SPI_InitConfig_t *spi, const uint8_t *out_data, uint32_t txlen, uint32_t rxlen, uint8_t *in_data)  SPI handle.
  +bool PHAL_SPI_transfer_noDMA_DAQW5500Only (SPI_InitConfig_t *spi, const uint8_t *out_data, uint32_t txlen, uint32_t rxlen, uint8_t *in_data) +  bool PHAL_SPI_transfer (SPI_InitConfig_t *spi, const uint8_t *out_data, const uint32_t data_len, const uint8_t *in_data)  Transfer data_len bytes from out_data to SPI device and place MISO data in in_data This function just starts the DMA transfer,.
  bool PHAL_SPI_busy (SPI_InitConfig_t *cfg)  Check for current SPI transaction to complete.
  +void PHAL_SPI_ForceReset (SPI_InitConfig_t *spi) +  void DMA2_Stream3_IRQHandler ()   uint8_t PHAL_SPI_readByte (SPI_InitConfig_t *spi, uint8_t address, bool skipDummy) @@ -179,6 +183,23 @@

+

◆ PHAL_SPI_ForceReset()

+ +
+
+ + + + + + + +
void PHAL_SPI_ForceReset (SPI_InitConfig_t * spi)
+
+
@@ -340,6 +361,42 @@

+

◆ PHAL_SPI_transfer_noDMA_DAQW5500Only()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
bool PHAL_SPI_transfer_noDMA_DAQW5500Only (SPI_InitConfig_t * spi,
const uint8_t * out_data,
uint32_t txlen,
uint32_t rxlen,
uint8_t * in_data )
+
+
diff --git a/phal__F4__F7_2spi_2spi_8h.html b/phal__F4__F7_2spi_2spi_8h.html index 18720e80..0363dfc1 100644 --- a/phal__F4__F7_2spi_2spi_8h.html +++ b/phal__F4__F7_2spi_2spi_8h.html @@ -132,6 +132,8 @@ bool PHAL_SPI_transfer_noDMA (SPI_InitConfig_t *spi, const uint8_t *out_data, uint32_t txlen, uint32_t rxlen, uint8_t *in_data)  SPI handle.
  +bool PHAL_SPI_transfer_noDMA_DAQW5500Only (SPI_InitConfig_t *spi, const uint8_t *out_data, uint32_t txlen, uint32_t rxlen, uint8_t *in_data) +  bool PHAL_SPI_busy (SPI_InitConfig_t *cfg)  Check for current SPI transaction to complete.
  @@ -141,6 +143,8 @@ uint8_t PHAL_SPI_readByte (SPI_InitConfig_t *spi, uint8_t address, bool skipDummy)  Blocking function to read a single byte from a SPI device. Useful for Initilization functions that just need to read a single byte in a blocking function.
  +void PHAL_SPI_ForceReset (SPI_InitConfig_t *spi) + 

Detailed Description

Author
Aditya Anand (anand.nosp@m.89@p.nosp@m.urdue.nosp@m..edu)
@@ -292,6 +296,23 @@

+

◆ PHAL_SPI_ForceReset()

+ +
+
+ + + + + + + +
void PHAL_SPI_ForceReset (SPI_InitConfig_t * spi)
+
+
@@ -462,6 +483,42 @@

+

◆ PHAL_SPI_transfer_noDMA_DAQW5500Only()

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
bool PHAL_SPI_transfer_noDMA_DAQW5500Only (SPI_InitConfig_t * spi,
const uint8_t * out_data,
uint32_t txlen,
uint32_t rxlen,
uint8_t * in_data )
+
+
diff --git a/phal__F4__F7_2spi_2spi_8h_source.html b/phal__F4__F7_2spi_2spi_8h_source.html index 0ac6a880..65a85b4d 100644 --- a/phal__F4__F7_2spi_2spi_8h_source.html +++ b/phal__F4__F7_2spi_2spi_8h_source.html @@ -134,63 +134,67 @@
71
83bool PHAL_SPI_transfer_noDMA(SPI_InitConfig_t *spi, const uint8_t *out_data, uint32_t txlen, uint32_t rxlen, uint8_t *in_data);
84
-
92bool PHAL_SPI_busy(SPI_InitConfig_t *cfg);
-
93
-
102uint8_t PHAL_SPI_writeByte(SPI_InitConfig_t *spi, uint8_t address, uint8_t writeDat);
-
103
-
112uint8_t PHAL_SPI_readByte(SPI_InitConfig_t *spi, uint8_t address, bool skipDummy);
-
113
-
114// SPI Configuration macros
-
-
115#define SPI1_RXDMA_CONT_CONFIG(rx_addr_, priority_) \
-
116 { \
-
117 .periph_addr = (uint32_t) & (SPI1->DR), .mem_addr = (uint32_t)(rx_addr_), \
-
118 .tx_size = 1, .increment = false, .circular = false, \
-
119 .dir = 0b0, .mem_inc = true, .periph_inc = false, .mem_to_mem = false, \
-
120 .priority = (priority_), .mem_size = 0b00, .periph_size = 0b00, \
-
121 .tx_isr_en = false, .dma_chan_request=0b0011, .stream_idx=2, \
-
122 .periph=DMA2, .stream=DMA2_Stream2 \
-
123 }
+
85bool PHAL_SPI_transfer_noDMA_DAQW5500Only(SPI_InitConfig_t *spi, const uint8_t *out_data, uint32_t txlen, uint32_t rxlen, uint8_t *in_data);
+
86
+
94bool PHAL_SPI_busy(SPI_InitConfig_t *cfg);
+
95
+
104uint8_t PHAL_SPI_writeByte(SPI_InitConfig_t *spi, uint8_t address, uint8_t writeDat);
+
105
+
114uint8_t PHAL_SPI_readByte(SPI_InitConfig_t *spi, uint8_t address, bool skipDummy);
+
115
+
116void PHAL_SPI_ForceReset(SPI_InitConfig_t *spi);
+
117
+
118// SPI Configuration macros
+
+
119#define SPI1_RXDMA_CONT_CONFIG(rx_addr_, priority_) \
+
120 { \
+
121 .periph_addr = (uint32_t) & (SPI1->DR), .mem_addr = (uint32_t)(rx_addr_), \
+
122 .tx_size = 1, .increment = false, .circular = false, \
+
123 .dir = 0b0, .mem_inc = true, .periph_inc = false, .mem_to_mem = false, \
+
124 .priority = (priority_), .mem_size = 0b00, .periph_size = 0b00, \
+
125 .tx_isr_en = false, .dma_chan_request=0b0011, .stream_idx=2, \
+
126 .periph=DMA2, .stream=DMA2_Stream2 \
+
127 }
-
124
-
-
125#define SPI1_TXDMA_CONT_CONFIG(tx_addr_, priority_) \
-
126 { \
-
127 .periph_addr = (uint32_t) & (SPI1->DR), .mem_addr = (uint32_t)(tx_addr_), \
-
128 .tx_size = 1, .increment = false, .circular = false, \
-
129 .dir = 0b1, .mem_inc = true, .periph_inc = false, .mem_to_mem = false, \
-
130 .priority = (priority_), .mem_size = 0b00, .periph_size = 0b00, \
-
131 .tx_isr_en = true, .dma_chan_request=0b0011, .stream_idx=3, \
-
132 .periph=DMA2, .stream=DMA2_Stream3 \
-
133 }
+
128
+
+
129#define SPI1_TXDMA_CONT_CONFIG(tx_addr_, priority_) \
+
130 { \
+
131 .periph_addr = (uint32_t) & (SPI1->DR), .mem_addr = (uint32_t)(tx_addr_), \
+
132 .tx_size = 1, .increment = false, .circular = false, \
+
133 .dir = 0b1, .mem_inc = true, .periph_inc = false, .mem_to_mem = false, \
+
134 .priority = (priority_), .mem_size = 0b00, .periph_size = 0b00, \
+
135 .tx_isr_en = true, .dma_chan_request=0b0011, .stream_idx=3, \
+
136 .periph=DMA2, .stream=DMA2_Stream3 \
+
137 }
-
134
-
-
135#define SPI2_TXDMA_CONT_CONFIG(tx_addr_, priority_) \
-
136 { \
-
137 .periph_addr = (uint32_t) & (SPI2->DR), .mem_addr = (uint32_t)(tx_addr_), \
-
138 .tx_size = 1, .increment = false, .circular = false, \
-
139 .dir = 0b1, .mem_inc = true, .periph_inc = false, .mem_to_mem = false, \
-
140 .priority = (priority_), .mem_size = 0b00, .periph_size = 0b00, \
-
141 .tx_isr_en = true, .dma_chan_request=0b0000, .stream_idx=4, \
-
142 .periph=DMA1, .stream=DMA1_Stream4 \
-
143 }
+
138
+
+
139#define SPI2_TXDMA_CONT_CONFIG(tx_addr_, priority_) \
+
140 { \
+
141 .periph_addr = (uint32_t) & (SPI2->DR), .mem_addr = (uint32_t)(tx_addr_), \
+
142 .tx_size = 1, .increment = false, .circular = false, \
+
143 .dir = 0b1, .mem_inc = true, .periph_inc = false, .mem_to_mem = false, \
+
144 .priority = (priority_), .mem_size = 0b00, .periph_size = 0b00, \
+
145 .tx_isr_en = true, .dma_chan_request=0b0000, .stream_idx=4, \
+
146 .periph=DMA1, .stream=DMA1_Stream4 \
+
147 }
-
144
-
-
145#define SPI2_RXDMA_CONT_CONFIG(rx_addr_, priority_) \
-
146 { \
-
147 .periph_addr = (uint32_t) & (SPI2->DR), .mem_addr = (uint32_t)(rx_addr_), \
-
148 .tx_size = 1, .increment = false, .circular = false, \
-
149 .dir = 0b0, .mem_inc = true, .periph_inc = false, .mem_to_mem = false, \
-
150 .priority = (priority_), .mem_size = 0b00, .periph_size = 0b00, \
-
151 .tx_isr_en = false, .dma_chan_request=0b0000, .stream_idx=3, \
-
152 .periph=DMA1, .stream=DMA1_Stream3 \
-
153 }
+
148
+
+
149#define SPI2_RXDMA_CONT_CONFIG(rx_addr_, priority_) \
+
150 { \
+
151 .periph_addr = (uint32_t) & (SPI2->DR), .mem_addr = (uint32_t)(rx_addr_), \
+
152 .tx_size = 1, .increment = false, .circular = false, \
+
153 .dir = 0b0, .mem_inc = true, .periph_inc = false, .mem_to_mem = false, \
+
154 .priority = (priority_), .mem_size = 0b00, .periph_size = 0b00, \
+
155 .tx_isr_en = false, .dma_chan_request=0b0000, .stream_idx=3, \
+
156 .periph=DMA1, .stream=DMA1_Stream3 \
+
157 }
-
154
-
155
-
156#endif /* _PHAL_SPI_H */
+
158
+
159
+
160#endif /* _PHAL_SPI_H */
dma.h
gpio.h
GPIO Driver for STM32L432 Devices.
rcc.h
RCC Configuration Driver for STM32F4 Devices.
@@ -198,8 +202,10 @@
PHAL_SPI_busy
bool PHAL_SPI_busy(SPI_InitConfig_t *cfg)
Check for current SPI transaction to complete.
Definition spi.c:215
PHAL_SPI_transfer_noDMA
bool PHAL_SPI_transfer_noDMA(SPI_InitConfig_t *spi, const uint8_t *out_data, uint32_t txlen, uint32_t rxlen, uint8_t *in_data)
SPI handle.
Definition spi.c:81
PHAL_SPI_init
bool PHAL_SPI_init(SPI_InitConfig_t *handle)
Initilize SPI peripheral with the configuired structure.
Definition spi.c:20
+
PHAL_SPI_transfer_noDMA_DAQW5500Only
bool PHAL_SPI_transfer_noDMA_DAQW5500Only(SPI_InitConfig_t *spi, const uint8_t *out_data, uint32_t txlen, uint32_t rxlen, uint8_t *in_data)
Definition spi.c:169
PHAL_SPI_transfer
bool PHAL_SPI_transfer(SPI_InitConfig_t *spi, const uint8_t *out_data, const uint32_t data_len, const uint8_t *in_data)
Transfer data_len bytes from out_data to SPI device and place MISO data in in_data This function just...
Definition spi.c:144
PHAL_SPI_readByte
uint8_t PHAL_SPI_readByte(SPI_InitConfig_t *spi, uint8_t address, bool skipDummy)
Blocking function to read a single byte from a SPI device. Useful for Initilization functions that ju...
Definition spi.c:400
+
PHAL_SPI_ForceReset
void PHAL_SPI_ForceReset(SPI_InitConfig_t *spi)
Definition spi.c:321
SPI_InitConfig_t
Configuration entry for SPI initilization.
Definition spi.h:26
SPI_InitConfig_t::_direct_mode_error
volatile bool _direct_mode_error
DMA error while attempting to operate in direct mode.
Definition spi.h:44
SPI_InitConfig_t::_fifo_overrun
volatile bool _fifo_overrun
DMA FIFO has been overrun - this should never occur, as it should never be enabled.
Definition spi.h:45
diff --git a/phal__F4__F7_2usart_2usart_8c.html b/phal__F4__F7_2usart_2usart_8c.html index 5cb04071..82ccc758 100644 --- a/phal__F4__F7_2usart_2usart_8c.html +++ b/phal__F4__F7_2usart_2usart_8c.html @@ -116,13 +116,13 @@ bool PHAL_initUSART (usart_init_t *handle, const uint32_t fck)  Initialize a USART Peripheral with desired settings.
  -bool PHAL_usartTxDma (usart_init_t *handle, uint16_t *data, uint32_t len) +bool PHAL_usartTxDma (usart_init_t *handle, uint16_t *data, uint32_t len)  Starts a tx using dma, use PHAL_usartTxDmaComplete to ensure the previous transmission is complete.
  volatile bool PHAL_usartTxBusy (usart_init_t *handle)  Returns whether USART peripheral is currently transmitting data.
  -bool PHAL_usartRxDma (usart_init_t *handle, uint16_t *data, uint32_t len, bool cont) +bool PHAL_usartRxDma (usart_init_t *handle, uint16_t *data, uint32_t len, bool cont)  Starts an rx using dma of a specific length.
  bool PHAL_disableContinousRxDMA (usart_init_t *handle) diff --git a/phal__F4__F7_2usart_2usart_8h.html b/phal__F4__F7_2usart_2usart_8h.html index 44b79d8a..6f6bc519 100644 --- a/phal__F4__F7_2usart_2usart_8h.html +++ b/phal__F4__F7_2usart_2usart_8h.html @@ -154,10 +154,10 @@ bool PHAL_initUSART (usart_init_t *handle, const uint32_t fck)  Initialize a USART Peripheral with desired settings.
  -bool PHAL_usartTxDma (usart_init_t *handle, uint16_t *data, uint32_t len) +bool PHAL_usartTxDma (usart_init_t *handle, uint16_t *data, uint32_t len)  Starts a tx using dma, use PHAL_usartTxDmaComplete to ensure the previous transmission is complete.
  -bool PHAL_usartRxDma (usart_init_t *handle, uint16_t *data, uint32_t len, bool cont) +bool PHAL_usartRxDma (usart_init_t *handle, uint16_t *data, uint32_t len, bool cont)  Starts an rx using dma of a specific length.
  bool PHAL_disableContinousRxDMA (usart_init_t *handle) @@ -197,13 +197,13 @@

-Value:
{ \
+Value:
{ \
.periph_addr = (uint32_t) & (UART4->RDR), .mem_addr = (uint32_t)(rx_addr_), \
-
.tx_size = 1, .increment = false, .circular = false, \
-
.dir = 0b0, .mem_inc = true, .periph_inc = false, .mem_to_mem = false, \
-
.priority = (priority_), .mem_size = 0b00, .periph_size = 0b00, \
-
.tx_isr_en = true, .dma_chan_request=0b0100, .stream_idx=2, \
-
.periph=DMA1, .stream=DMA1_Stream2 \
+
.tx_size = 1, .increment = false, .circular = false, \
+
.dir = 0b0, .mem_inc = true, .periph_inc = false, .mem_to_mem = false, \
+
.priority = (priority_), .mem_size = 0b00, .periph_size = 0b00, \
+
.tx_isr_en = true, .dma_chan_request=0b0100, .stream_idx=2, \
+
.periph=DMA1, .stream=DMA1_Stream2 \
}
mem_size
uint16_t mem_size[MAX_PAGES]
Size of file in bytes (actual)
Definition eeprom_spi.h:4
@@ -227,13 +227,13 @@

-Value:
{ \
+Value:
{ \
.periph_addr = (uint32_t) & (UART4->TDR), .mem_addr = (uint32_t)(tx_addr_), \
-
.tx_size = 1, .increment = false, .circular = false, \
-
.dir = 0b1, .mem_inc = true, .periph_inc = false, .mem_to_mem = false, \
-
.priority = (priority_), .mem_size = 0b00, .periph_size = 0b00, \
-
.tx_isr_en = true, .dma_chan_request=0b0100, .stream_idx=4, \
-
.periph=DMA1, .stream=DMA1_Stream4 \
+
.tx_size = 1, .increment = false, .circular = false, \
+
.dir = 0b1, .mem_inc = true, .periph_inc = false, .mem_to_mem = false, \
+
.priority = (priority_), .mem_size = 0b00, .periph_size = 0b00, \
+
.tx_isr_en = true, .dma_chan_request=0b0100, .stream_idx=4, \
+
.periph=DMA1, .stream=DMA1_Stream4 \
}
diff --git a/phal__F4__F7_2usart_2usart_8h_source.html b/phal__F4__F7_2usart_2usart_8h_source.html index ca8a652b..6572f7a4 100644 --- a/phal__F4__F7_2usart_2usart_8h_source.html +++ b/phal__F4__F7_2usart_2usart_8h_source.html @@ -243,97 +243,122 @@
144
153bool PHAL_initUSART(usart_init_t* handle, const uint32_t fck);
154
-
155
-
163bool PHAL_usartTxDma(usart_init_t* handle, uint16_t* data, uint32_t len);
+
155#ifdef STM32F407xx
+
156
+
163void PHAL_usartTxBl(usart_init_t* handle, uint8_t* data, uint32_t len);
164
-
173bool PHAL_usartRxDma(usart_init_t* handle, uint16_t* data, uint32_t len, bool cont);
-
174
-
180bool PHAL_disableContinousRxDMA(usart_init_t* handle);
-
181
-
189bool PHAL_usartTxBusy(usart_init_t* handle);
-
190
-
198bool PHAL_usartRxBusy(usart_init_t *handle);
+
171void PHAL_usartRxBl(usart_init_t* handle, uint8_t* data, uint32_t len);
+
172#endif
+
173
+
181bool PHAL_usartTxDma(usart_init_t* handle, uint16_t* data, uint32_t len);
+
182
+
191bool PHAL_usartRxDma(usart_init_t* handle, uint16_t* data, uint32_t len, bool cont);
+
192
+
198bool PHAL_disableContinousRxDMA(usart_init_t* handle);
199
-
208extern void usart_recieve_complete_callback(usart_init_t *handle);
-
209
-
210#ifdef STM32F407xx
-
211
-
212 #define USART1_RXDMA_CONT_CONFIG(rx_addr_, priority_) \
-
213 { \
-
214 .periph_addr = (uint32_t) & (USART1->DR), .mem_addr = (uint32_t)(rx_addr_), \
-
215 .tx_size = 1, .increment = false, .circular = false, \
-
216 .dir = 0b0, .mem_inc = true, .periph_inc = false, .mem_to_mem = false, \
-
217 .priority = (priority_), .mem_size = 0b00, .periph_size = 0b00, \
-
218 .tx_isr_en = true, .dma_chan_request=0b0100, .stream_idx=5, \
-
219 .periph=DMA2, .stream=DMA2_Stream5 \
-
220 }
-
221
-
222 #define USART1_TXDMA_CONT_CONFIG(tx_addr_, priority_) \
-
223 { \
-
224 .periph_addr = (uint32_t) & (USART1->DR), .mem_addr = (uint32_t)(tx_addr_), \
-
225 .tx_size = 1, .increment = false, .circular = false, \
-
226 .dir = 0b1, .mem_inc = true, .periph_inc = false, .mem_to_mem = false, \
-
227 .priority = (priority_), .mem_size = 0b00, .periph_size = 0b00, \
-
228 .tx_isr_en = true, .dma_chan_request=0b0100, .stream_idx=7, \
-
229 .periph=DMA2, .stream=DMA2_Stream7 \
-
230 }
-
231
-
232 #define USART2_RXDMA_CONT_CONFIG(rx_addr_, priority_) \
-
233 { \
-
234 .periph_addr = (uint32_t) & (USART2->DR), .mem_addr = (uint32_t)(rx_addr_), \
-
235 .tx_size = 1, .increment = false, .circular = false, \
-
236 .dir = 0b0, .mem_inc = true, .periph_inc = false, .mem_to_mem = false, \
-
237 .priority = (priority_), .mem_size = 0b00, .periph_size = 0b00, \
-
238 .tx_isr_en = true, .dma_chan_request=0b0100, .stream_idx=5, \
-
239 .periph=DMA1, .stream=DMA1_Stream5 \
-
240 }
+
207bool PHAL_usartTxBusy(usart_init_t* handle);
+
208
+
216bool PHAL_usartRxBusy(usart_init_t *handle);
+
217
+
226extern void usart_recieve_complete_callback(usart_init_t *handle);
+
227
+
228#ifdef STM32F407xx
+
229 // 4,5,7,8 are UART, rest are USART
+
230 #define PHAL_USART1_RXDMA_STREAM DMA2_Stream5
+
231 #define PHAL_USART1_TXDMA_STREAM DMA2_Stream7
+
232
+
233 #define PHAL_USART2_RXDMA_STREAM DMA1_Stream5
+
234 #define PHAL_USART2_TXDMA_STREAM DMA1_Stream6
+
235
+
236 #define PHAL_USART3_RXDMA_STREAM DMA1_Stream1
+
237 #define PHAL_USART3_TXDMA_STREAM DMA1_Stream3
+
238
+
239 #define PHAL_USART4_RXDMA_STREAM DMA1_Stream2 // UART
+
240 #define PHAL_USART4_TXDMA_STREAM DMA1_Stream4
241
-
242 #define USART2_TXDMA_CONT_CONFIG(tx_addr_, priority_) \
-
243 { \
-
244 .periph_addr = (uint32_t) & (USART2->DR), .mem_addr = (uint32_t)(tx_addr_), \
-
245 .tx_size = 1, .increment = false, .circular = false, \
-
246 .dir = 0b1, .mem_inc = true, .periph_inc = false, .mem_to_mem = false, \
-
247 .priority = (priority_), .mem_size = 0b00, .periph_size = 0b00, \
-
248 .tx_isr_en = true, .dma_chan_request=0b0100, .stream_idx=6, \
-
249 .periph=DMA1, .stream=DMA1_Stream6 \
-
250 }
-
251#else
-
-
252 #define USART4_RXDMA_CONT_CONFIG(rx_addr_, priority_) \
-
253 { \
-
254 .periph_addr = (uint32_t) & (UART4->RDR), .mem_addr = (uint32_t)(rx_addr_), \
-
255 .tx_size = 1, .increment = false, .circular = false, \
-
256 .dir = 0b0, .mem_inc = true, .periph_inc = false, .mem_to_mem = false, \
-
257 .priority = (priority_), .mem_size = 0b00, .periph_size = 0b00, \
-
258 .tx_isr_en = true, .dma_chan_request=0b0100, .stream_idx=2, \
-
259 .periph=DMA1, .stream=DMA1_Stream2 \
-
260 }
+
242 #define PHAL_USART5_RXDMA_STREAM DMA1_Stream0 // UART
+
243 #define PHAL_USART5_TXDMA_STREAM DMA1_Stream7
+
244
+
245 #define PHAL_USART6_RXDMA_STREAM DMA2_Stream1
+
246 #define PHAL_USART6_TXDMA_STREAM DMA2_Stream6
+
247
+
248 #define PHAL_USART7_RXDMA_STREAM DMA1_Stream3 // UART
+
249 #define PHAL_USART7_TXDMA_STREAM DMA1_Stream1
+
250
+
251 #define PHAL_USART8_RXDMA_STREAM DMA1_Stream6 // UART
+
252 #define PHAL_USART8_TXDMA_STREAM DMA1_Stream0
+
253 // dm00031020 311
+
254 #define _DEF_USART_RXDMA_CONFIG(rx_addr_, priority_, UXART, dmanum, streamnum, channum)\
+
255 { \
+
256 .periph_addr = (uint32_t) & ((UXART)->DR), .mem_addr = (uint32_t)(rx_addr_), \
+
257 .tx_size = 1, .increment = false, .circular = false, \
+
258 .dir = 0b0, .mem_inc = true, .periph_inc = false, .mem_to_mem = false, \
+
259 .priority = (priority_), .mem_size = 0b00, .periph_size = 0b00, \
+
260 .tx_isr_en = true, .dma_chan_request = channum, .stream_idx = streamnum, \
+
261 .periph = DMA##dmanum , .stream = DMA##dmanum##_Stream##streamnum , \
+
262 }
+
263
+
264 #define _DEF_USART_TXDMA_CONFIG(tx_addr_, priority_, UXART, dmanum, streamnum, channum)\
+
265 { \
+
266 .periph_addr = (uint32_t) & ((UXART)->DR), .mem_addr = (uint32_t)(tx_addr_), \
+
267 .tx_size = 1, .increment = false, .circular = false, \
+
268 .dir = 0b1, .mem_inc = true, .periph_inc = false, .mem_to_mem = false, \
+
269 .priority = (priority_), .mem_size = 0b00, .periph_size = 0b00, \
+
270 .tx_isr_en = true, .dma_chan_request = channum, .stream_idx = streamnum, \
+
271 .periph = DMA##dmanum , .stream = DMA##dmanum##_Stream##streamnum , \
+
272 }
+
273
+
274 #define USART1_RXDMA_CONT_CONFIG(a, p) _DEF_USART_RXDMA_CONFIG(a, p, USART1, 2, 5, 4)
+
275 #define USART1_TXDMA_CONT_CONFIG(a, p) _DEF_USART_TXDMA_CONFIG(a, p, USART1, 2, 7, 4)
+
276 #define USART2_RXDMA_CONT_CONFIG(a, p) _DEF_USART_RXDMA_CONFIG(a, p, USART2, 1, 5, 4)
+
277 #define USART2_TXDMA_CONT_CONFIG(a, p) _DEF_USART_TXDMA_CONFIG(a, p, USART2, 1, 6, 4)
+
278 #define USART3_RXDMA_CONT_CONFIG(a, p) _DEF_USART_RXDMA_CONFIG(a, p, USART3, 1, 1, 4)
+
279 #define USART3_TXDMA_CONT_CONFIG(a, p) _DEF_USART_TXDMA_CONFIG(a, p, USART3, 1, 3, 4)
+
280 #define USART4_RXDMA_CONT_CONFIG(a, p) _DEF_USART_RXDMA_CONFIG(a, p, UART4, 1, 2, 4)
+
281 #define USART4_TXDMA_CONT_CONFIG(a, p) _DEF_USART_TXDMA_CONFIG(a, p, UART4, 1, 4, 4)
+
282 #define USART5_RXDMA_CONT_CONFIG(a, p) _DEF_USART_RXDMA_CONFIG(a, p, UART5, 1, 0, 4)
+
283 #define USART5_TXDMA_CONT_CONFIG(a, p) _DEF_USART_TXDMA_CONFIG(a, p, UART5, 1, 7, 4)
+
284 #define USART6_RXDMA_CONT_CONFIG(a, p) _DEF_USART_RXDMA_CONFIG(a, p, USART6, 2, 1, 5)
+
285 #define USART6_TXDMA_CONT_CONFIG(a, p) _DEF_USART_TXDMA_CONFIG(a, p, USART6, 2, 6, 5)
+
286
+
287#else
+
+
288 #define USART4_RXDMA_CONT_CONFIG(rx_addr_, priority_) \
+
289 { \
+
290 .periph_addr = (uint32_t) & (UART4->RDR), .mem_addr = (uint32_t)(rx_addr_), \
+
291 .tx_size = 1, .increment = false, .circular = false, \
+
292 .dir = 0b0, .mem_inc = true, .periph_inc = false, .mem_to_mem = false, \
+
293 .priority = (priority_), .mem_size = 0b00, .periph_size = 0b00, \
+
294 .tx_isr_en = true, .dma_chan_request=0b0100, .stream_idx=2, \
+
295 .periph=DMA1, .stream=DMA1_Stream2 \
+
296 }
-
261
-
-
262 #define USART4_TXDMA_CONT_CONFIG(tx_addr_, priority_) \
-
263 { \
-
264 .periph_addr = (uint32_t) & (UART4->TDR), .mem_addr = (uint32_t)(tx_addr_), \
-
265 .tx_size = 1, .increment = false, .circular = false, \
-
266 .dir = 0b1, .mem_inc = true, .periph_inc = false, .mem_to_mem = false, \
-
267 .priority = (priority_), .mem_size = 0b00, .periph_size = 0b00, \
-
268 .tx_isr_en = true, .dma_chan_request=0b0100, .stream_idx=4, \
-
269 .periph=DMA1, .stream=DMA1_Stream4 \
-
270 }
+
297
+
+
298 #define USART4_TXDMA_CONT_CONFIG(tx_addr_, priority_) \
+
299 { \
+
300 .periph_addr = (uint32_t) & (UART4->TDR), .mem_addr = (uint32_t)(tx_addr_), \
+
301 .tx_size = 1, .increment = false, .circular = false, \
+
302 .dir = 0b1, .mem_inc = true, .periph_inc = false, .mem_to_mem = false, \
+
303 .priority = (priority_), .mem_size = 0b00, .periph_size = 0b00, \
+
304 .tx_isr_en = true, .dma_chan_request=0b0100, .stream_idx=4, \
+
305 .periph=DMA1, .stream=DMA1_Stream4 \
+
306 }
-
271#endif
-
272#endif
+
307#endif
+
308#endif
+
data
u8 data[8]
Definition gs_usb.h:8
ptr_int
uint32_t ptr_int
Definition i2c_alt.h:11
dma.h
word_length_t
word_length_t
Definition usart.h:66
WORD_8
@ WORD_8
8-Bit word length
Definition usart.h:67
WORD_9
@ WORD_9
9-Bit word length
Definition usart.h:68
PHAL_initUSART
bool PHAL_initUSART(usart_init_t *handle, const uint32_t fck)
Initialize a USART Peripheral with desired settings.
Definition usart.c:34
-
PHAL_disableContinousRxDMA
bool PHAL_disableContinousRxDMA(usart_init_t *handle)
Disables the Continous RX that was previously used.
Definition usart.c:232
-
PHAL_usartRxBusy
bool PHAL_usartRxBusy(usart_init_t *handle)
Returns whether USART peripheral is currently receiving data.
Definition usart.c:270
-
PHAL_usartTxBusy
bool PHAL_usartTxBusy(usart_init_t *handle)
Returns whether USART peripheral is currently transmitting data.
Definition usart.c:187
+
PHAL_disableContinousRxDMA
bool PHAL_disableContinousRxDMA(usart_init_t *handle)
Disables the Continous RX that was previously used.
Definition usart.c:304
+
PHAL_usartRxBusy
bool PHAL_usartRxBusy(usart_init_t *handle)
Returns whether USART peripheral is currently receiving data.
Definition usart.c:358
+
PHAL_usartTxBusy
bool PHAL_usartTxBusy(usart_init_t *handle)
Returns whether USART peripheral is currently transmitting data.
Definition usart.c:243
usart_recieve_complete_callback
void usart_recieve_complete_callback(usart_init_t *handle)
Callback function called immediately after reception of a USART RX message Uses USART IDLE line inter...
Definition main.c:151
-
PHAL_usartRxDma
bool PHAL_usartRxDma(usart_init_t *handle, uint16_t *data, uint32_t len, bool cont)
Starts an rx using dma of a specific length.
Definition usart.c:192
+
PHAL_usartRxDma
bool PHAL_usartRxDma(usart_init_t *handle, uint16_t *data, uint32_t len, bool cont)
Starts an rx using dma of a specific length.
Definition usart.c:248
hw_flow_ctl_t
hw_flow_ctl_t
Definition usart.h:80
CTS_RTS
@ CTS_RTS
Enable both CTS and RTS.
Definition usart.h:84
HW_DISABLE
@ HW_DISABLE
Hardware flow control disable.
Definition usart.h:81
@@ -354,7 +379,9 @@
ovsample_t
ovsample_t
Definition usart.h:87
OV_16
@ OV_16
Oversample by 16.
Definition usart.h:88
OV_8
@ OV_8
Oversample by 8.
Definition usart.h:89
-
PHAL_usartTxDma
bool PHAL_usartTxDma(usart_init_t *handle, uint16_t *data, uint32_t len)
Starts a tx using dma, use PHAL_usartTxDmaComplete to ensure the previous transmission is complete.
Definition usart.c:137
+
PHAL_usartTxDma
bool PHAL_usartTxDma(usart_init_t *handle, uint16_t *data, uint32_t len)
Starts a tx using dma, use PHAL_usartTxDmaComplete to ensure the previous transmission is complete.
Definition usart.c:179
+
PHAL_usartTxBl
void PHAL_usartTxBl(USART_TypeDef *instance, const uint16_t *data, uint32_t len)
Definition usart.c:102
+
PHAL_usartRxBl
void PHAL_usartRxBl(USART_TypeDef *instance, uint16_t *data, uint32_t len)
Definition usart.c:116
word_length_t
word_length_t
Definition usart.h:35
hw_flow_ctl_t
hw_flow_ctl_t
Definition usart.h:57
obsample_t
obsample_t
Definition usart.h:71
diff --git a/phal__L4_2flash_2flash_8h.html b/phal__L4_2flash_2flash_8h.html index 177b156c..4c6d488e 100644 --- a/phal__L4_2flash_2flash_8h.html +++ b/phal__L4_2flash_2flash_8h.html @@ -129,7 +129,7 @@ - + diff --git a/phal__L4_2flash_2flash_8h_source.html b/phal__L4_2flash_2flash_8h_source.html index bec6924a..efdab6a6 100644 --- a/phal__L4_2flash_2flash_8h_source.html +++ b/phal__L4_2flash_2flash_8h_source.html @@ -116,13 +116,14 @@
33#define USER_FLASH_END_ADDRESS (FLASH_END) /* Last usable flash address */
34#define MAX_FLASH_SECTOR (((FLASH_END - FLASH_BASE + 1) / FLASH_PAGE_SIZE) - 1)
35
-
42uint8_t PHAL_flashWriteU64(uint32_t address, uint64_t data);
+
42uint8_t PHAL_flashWriteU64(uint32_t address, uint64_t data);
43
49uint8_t PHAL_flashErasePage(uint16_t page);
50
58uint8_t PHAL_flashErase(uint32_t *addr, uint32_t words);
59
60#endif
+
data
u8 data[8]
Definition gs_usb.h:8
PHAL_flashWriteU64
uint8_t PHAL_flashWriteU64(uint32_t address, uint64_t data)
Writes 64 bits to flash memory.
Definition flash.c:46
FLASH_FAIL
@ FLASH_FAIL
Definition flash.h:26
FLASH_TIMEOUT
@ FLASH_TIMEOUT
Definition flash.h:28
diff --git a/phal__L4_2gpio_2gpio_8h_source.html b/phal__L4_2gpio_2gpio_8h_source.html index ba997632..4721d928 100644 --- a/phal__L4_2gpio_2gpio_8h_source.html +++ b/phal__L4_2gpio_2gpio_8h_source.html @@ -267,18 +267,18 @@
234
235#endif
config
config_t config
Definition daq.c:37
-
PHAL_readGPIO
bool PHAL_readGPIO(GPIO_TypeDef *bank, uint8_t pin)
Read the state of the input register for the specific GPIO pin.
Definition gpio.h:280
+
PHAL_readGPIO
bool PHAL_readGPIO(GPIO_TypeDef *bank, uint8_t pin)
Read the state of the input register for the specific GPIO pin.
Definition gpio.h:281
GPIOOutputPull_t
GPIOOutputPull_t
Output drive mode selection.
Definition gpio.h:79
GPIO_OUTPUT_OPEN_DRAIN
@ GPIO_OUTPUT_OPEN_DRAIN
Definition gpio.h:81
GPIO_OUTPUT_PUSH_PULL
@ GPIO_OUTPUT_PUSH_PULL
Definition gpio.h:80
-
PHAL_writeGPIO
void PHAL_writeGPIO(GPIO_TypeDef *bank, uint8_t pin, bool value)
Write a logic value to an output pin.
Definition gpio.h:285
+
PHAL_writeGPIO
void PHAL_writeGPIO(GPIO_TypeDef *bank, uint8_t pin, bool value)
Write a logic value to an output pin.
Definition gpio.h:286
GPIOPinType_t
GPIOPinType_t
Configuration type for GPIO Pin.
Definition gpio.h:57
GPIO_TYPE_AF
@ GPIO_TYPE_AF
Definition gpio.h:60
GPIO_TYPE_INPUT
@ GPIO_TYPE_INPUT
Definition gpio.h:58
GPIO_TYPE_OUTPUT
@ GPIO_TYPE_OUTPUT
Definition gpio.h:59
GPIO_TYPE_ANALOG
@ GPIO_TYPE_ANALOG
Definition gpio.h:61
PHAL_initGPIO
bool PHAL_initGPIO(GPIOInitConfig_t config[], uint8_t config_len)
Initilize the GPIO perpheral given a list of configuration fields for all of the GPIO pins....
Definition gpio.c:15
-
PHAL_toggleGPIO
void PHAL_toggleGPIO(GPIO_TypeDef *bank, uint8_t pin)
Definition gpio.h:290
+
PHAL_toggleGPIO
void PHAL_toggleGPIO(GPIO_TypeDef *bank, uint8_t pin)
Definition gpio.h:291
GPIOInputPull_t
GPIOInputPull_t
Enable internal pullup/down resistors.
Definition gpio.h:88
GPIO_INPUT_PULL_UP
@ GPIO_INPUT_PULL_UP
Definition gpio.h:90
GPIO_INPUT_OPEN_DRAIN
@ GPIO_INPUT_OPEN_DRAIN
Definition gpio.h:89
diff --git a/phal__L4_2spi_2spi_8h.html b/phal__L4_2spi_2spi_8h.html index 6f7726d8..95b14572 100644 --- a/phal__L4_2spi_2spi_8h.html +++ b/phal__L4_2spi_2spi_8h.html @@ -173,9 +173,10 @@

.dir = 0b0, .mem_inc = true, .periph_inc = false, .mem_to_mem = false, \
.priority = (priority_), .mem_size = 0b00, .periph_size = 0b00, \
.tx_isr_en = true, .dma_chan_request = 0b0001, .channel_idx = 2, \
-
.periph = DMA1, .channel = DMA1_Channel2, .request = DMA1_CSELR \
+
.periph = DMA1, .channel = DMA1_Channel2, .request = DMA1_CSELR \
}
mem_size
uint16_t mem_size[MAX_PAGES]
Size of file in bytes (actual)
Definition eeprom_spi.h:4
+
channel
u8 channel
Definition gs_usb.h:4
@@ -203,7 +204,7 @@

.dir = 0b1, .mem_inc = true, .periph_inc = false, .mem_to_mem = false, \
.priority = (priority_), .mem_size = 0b00, .periph_size = 0b00, \
.tx_isr_en = false, .dma_chan_request = 0b0001, .channel_idx = 3, \
-
.periph = DMA1, .channel = DMA1_Channel3, .request = DMA1_CSELR \
+
.periph = DMA1, .channel = DMA1_Channel3, .request = DMA1_CSELR \
}
@@ -232,7 +233,7 @@

.dir = 0b0, .mem_inc = true, .periph_inc = false, .mem_to_mem = false, \
.priority = (priority_), .mem_size = 0b00, .periph_size = 0b00, \
.tx_isr_en = true, .dma_chan_request = 0b0001, .channel_idx = 4, \
-
.periph = DMA1, .channel = DMA1_Channel4, .request = DMA1_CSELR \
+
.periph = DMA1, .channel = DMA1_Channel4, .request = DMA1_CSELR \
}
@@ -261,7 +262,7 @@

.dir = 0b1, .mem_inc = true, .periph_inc = false, .mem_to_mem = false, \
.priority = (priority_), .mem_size = 0b00, .periph_size = 0b00, \
.tx_isr_en = false, .dma_chan_request = 0b0001, .channel_idx = 5, \
-
.periph = DMA1, .channel = DMA1_Channel5, .request = DMA1_CSELR \
+
.periph = DMA1, .channel = DMA1_Channel5, .request = DMA1_CSELR \
}
diff --git a/phal__L4_2usart_2usart_8c.html b/phal__L4_2usart_2usart_8c.html index 3855bcf2..789dbb23 100644 --- a/phal__L4_2usart_2usart_8c.html +++ b/phal__L4_2usart_2usart_8c.html @@ -99,16 +99,16 @@ Functions

- + - + - + - + diff --git a/phal__L4_2usart_2usart_8h.html b/phal__L4_2usart_2usart_8h.html index afe132b6..69108674 100644 --- a/phal__L4_2usart_2usart_8h.html +++ b/phal__L4_2usart_2usart_8h.html @@ -187,14 +187,14 @@ Functions - + - + - + - + @@ -232,9 +232,10 @@

.dir = 0b0, .mem_inc = true, .periph_inc = false, .mem_to_mem = false, \
.priority = (priority_), .mem_size = 0b00, .periph_size = 0b00, \
.tx_isr_en = true, .dma_chan_request = 0b0100, .channel_idx = 7, \
-
.periph = DMA2, .channel = DMA2_Channel7, .request = DMA2_CSELR \
+
.periph = DMA2, .channel = DMA2_Channel7, .request = DMA2_CSELR \
}
mem_size
uint16_t mem_size[MAX_PAGES]
Size of file in bytes (actual)
Definition eeprom_spi.h:4
+
channel
u8 channel
Definition gs_usb.h:4
@@ -262,7 +263,7 @@

.dir = 0b1, .mem_inc = true, .periph_inc = false, .mem_to_mem = false, \
.priority = (priority_), .mem_size = 0b00, .periph_size = 0b00, \
.tx_isr_en = true, .dma_chan_request = 0b0100, .channel_idx = 6, \
-
.periph = DMA2, .channel = DMA2_Channel6, .request = DMA2_CSELR \
+
.periph = DMA2, .channel = DMA2_Channel6, .request = DMA2_CSELR \
}
@@ -319,7 +320,7 @@

.dir = 0b0, .mem_inc = true, .periph_inc = false, .mem_to_mem = false, \
.priority = (priority_), .mem_size = 0b00, .periph_size = 0b00, \
.tx_isr_en = true, .dma_chan_request = 0b0010, .channel_idx = 5, \
-
.periph = DMA1, .channel = DMA1_Channel5, .request = DMA1_CSELR \
+
.periph = DMA1, .channel = DMA1_Channel5, .request = DMA1_CSELR \
}
@@ -348,7 +349,7 @@

.dir = 0b1, .mem_inc = true, .periph_inc = false, .mem_to_mem = false, \
.priority = (priority_), .mem_size = 0b00, .periph_size = 0b00, \
.tx_isr_en = true, .dma_chan_request = 0b0010, .channel_idx = 4, \
-
.periph = DMA1, .channel = DMA1_Channel4, .request = DMA1_CSELR \
+
.periph = DMA1, .channel = DMA1_Channel4, .request = DMA1_CSELR \
}
@@ -377,7 +378,7 @@

.dir = 0b0, .mem_inc = true, .periph_inc = false, .mem_to_mem = false, \
.priority = (priority_), .mem_size = 0b00, .periph_size = 0b00, \
.tx_isr_en = true, .dma_chan_request = 0b0010, .channel_idx = 6, \
-
.periph = DMA1, .channel = DMA1_Channel6, .request = DMA1_CSELR \
+
.periph = DMA1, .channel = DMA1_Channel6, .request = DMA1_CSELR \
}
@@ -406,7 +407,7 @@

.dir = 0b1, .mem_inc = true, .periph_inc = false, .mem_to_mem = false, \
.priority = (priority_), .mem_size = 0b00, .periph_size = 0b00, \
.tx_isr_en = true, .dma_chan_request = 0b0010, .channel_idx = 7, \
-
.periph = DMA1, .channel = DMA1_Channel7, .request = DMA1_CSELR \
+
.periph = DMA1, .channel = DMA1_Channel7, .request = DMA1_CSELR \
}
@@ -435,7 +436,7 @@

.dir = 0b0, .mem_inc = true, .periph_inc = false, .mem_to_mem = false, \
.priority = (priority_), .mem_size = 0b00, .periph_size = 0b00, \
.tx_isr_en = true, .dma_chan_request = 0b0010, .channel_idx = 3, \
-
.periph = DMA1, .channel = DMA1_Channel3, .request = DMA1_CSELR \
+
.periph = DMA1, .channel = DMA1_Channel3, .request = DMA1_CSELR \
}
@@ -464,7 +465,7 @@

.dir = 0b1, .mem_inc = true, .periph_inc = false, .mem_to_mem = false, \
.priority = (priority_), .mem_size = 0b00, .periph_size = 0b00, \
.tx_isr_en = true, .dma_chan_request = 0b0010, .channel_idx = 2, \
-
.periph = DMA1, .channel = DMA1_Channel2, .request = DMA1_CSELR \
+
.periph = DMA1, .channel = DMA1_Channel2, .request = DMA1_CSELR \
}
diff --git a/phal__L4_2usart_2usart_8h_source.html b/phal__L4_2usart_2usart_8h_source.html index 7222b012..1520f957 100644 --- a/phal__L4_2usart_2usart_8h_source.html +++ b/phal__L4_2usart_2usart_8h_source.html @@ -250,12 +250,12 @@
143
144// Function Prototypes
145bool PHAL_initUSART(USART_TypeDef *instance, usart_init_t *handle, const uint32_t fck);
-
146void PHAL_usartTxBl(USART_TypeDef *instance, const uint16_t *data, uint32_t len);
-
147void PHAL_usartRxBl(USART_TypeDef *instance, uint16_t *data, uint32_t len);
+
146void PHAL_usartTxBl(USART_TypeDef *instance, const uint16_t *data, uint32_t len);
+
147void PHAL_usartRxBl(USART_TypeDef *instance, uint16_t *data, uint32_t len);
148
-
157bool PHAL_usartTxDma(USART_TypeDef *instance, usart_init_t *handle, uint16_t *data, uint32_t len);
+
157bool PHAL_usartTxDma(USART_TypeDef *instance, usart_init_t *handle, uint16_t *data, uint32_t len);
158
-
167bool PHAL_usartRxDma(USART_TypeDef *instance, usart_init_t *handle, uint16_t *data, uint32_t len);
+
167bool PHAL_usartRxDma(USART_TypeDef *instance, usart_init_t *handle, uint16_t *data, uint32_t len);
168bool PHAL_usartTxDmaComplete(usart_init_t *handle);
169bool PHAL_usartRxDmaComplete(usart_init_t *handle);
170
@@ -355,12 +355,13 @@
249
250#endif
+
data
u8 data[8]
Definition gs_usb.h:8
ptr_int
uint32_t ptr_int
Definition i2c_alt.h:11
word_length_t
word_length_t
Definition usart.h:66
WORD_8
@ WORD_8
8-Bit word length
Definition usart.h:67
WORD_9
@ WORD_9
9-Bit word length
Definition usart.h:68
PHAL_initUSART
bool PHAL_initUSART(usart_init_t *handle, const uint32_t fck)
Initialize a USART Peripheral with desired settings.
Definition usart.c:34
-
PHAL_usartRxDma
bool PHAL_usartRxDma(usart_init_t *handle, uint16_t *data, uint32_t len, bool cont)
Starts an rx using dma of a specific length.
Definition usart.c:192
+
PHAL_usartRxDma
bool PHAL_usartRxDma(usart_init_t *handle, uint16_t *data, uint32_t len, bool cont)
Starts an rx using dma of a specific length.
Definition usart.c:248
hw_flow_ctl_t
hw_flow_ctl_t
Definition usart.h:80
CTS_RTS
@ CTS_RTS
Enable both CTS and RTS.
Definition usart.h:84
HW_DISABLE
@ HW_DISABLE
Hardware flow control disable.
Definition usart.h:81
@@ -381,9 +382,10 @@
ovsample_t
ovsample_t
Definition usart.h:87
OV_16
@ OV_16
Oversample by 16.
Definition usart.h:88
OV_8
@ OV_8
Oversample by 8.
Definition usart.h:89
-
PHAL_usartTxDma
bool PHAL_usartTxDma(usart_init_t *handle, uint16_t *data, uint32_t len)
Starts a tx using dma, use PHAL_usartTxDmaComplete to ensure the previous transmission is complete.
Definition usart.c:137
+
PHAL_usartTxDma
bool PHAL_usartTxDma(usart_init_t *handle, uint16_t *data, uint32_t len)
Starts a tx using dma, use PHAL_usartTxDmaComplete to ensure the previous transmission is complete.
Definition usart.c:179
dma.h
Basic DMA Peripheral HAL library for setting up DMA transfers.
-
PHAL_usartTxBl
void PHAL_usartTxBl(USART_TypeDef *instance, const uint16_t *data, uint32_t len)
Definition usart.c:102
+
PHAL_usartTxBl
void PHAL_usartTxBl(USART_TypeDef *instance, const uint16_t *data, uint32_t len)
Definition usart.c:102
+
PHAL_usartRxBl
void PHAL_usartRxBl(USART_TypeDef *instance, uint16_t *data, uint32_t len)
Definition usart.c:116
WORD_7
@ WORD_7
Definition usart.h:38
PHAL_usartTxDmaComplete
bool PHAL_usartTxDmaComplete(usart_init_t *handle)
Definition usart.c:141
ab_mode_t
ab_mode_t
Definition usart.h:77
@@ -395,7 +397,6 @@
MODE_TX
@ MODE_TX
Definition usart.h:52
MODE_TX_RX
@ MODE_TX_RX
Definition usart.h:51
MODE_RX
@ MODE_RX
Definition usart.h:53
-
PHAL_usartRxBl
void PHAL_usartRxBl(USART_TypeDef *instance, uint16_t *data, uint32_t len)
Definition usart.c:116
PHAL_usartRxDmaComplete
bool PHAL_usartRxDmaComplete(usart_init_t *handle)
Definition usart.c:166
tx_mode_t
tx_mode_t
Definition usart.h:85
DMA
@ DMA
Definition usart.h:88
diff --git a/quadspi_8c.html b/quadspi_8c.html index b42a0f66..5d4b3f30 100644 --- a/quadspi_8c.html +++ b/quadspi_8c.html @@ -103,9 +103,9 @@

- + - +

Functions

uint8_t PHAL_flashWriteU64 (uint32_t address, uint64_t data)
uint8_t PHAL_flashWriteU64 (uint32_t address, uint64_t data)
 Writes 64 bits to flash memory.
 
uint8_t PHAL_flashErasePage (uint16_t page)
bool PHAL_initUSART (USART_TypeDef *instance, usart_init_t *handle, const uint32_t fck)
 
void PHAL_usartTxBl (USART_TypeDef *instance, const uint16_t *data, uint32_t len)
void PHAL_usartTxBl (USART_TypeDef *instance, const uint16_t *data, uint32_t len)
 
void PHAL_usartRxBl (USART_TypeDef *instance, uint16_t *data, uint32_t len)
void PHAL_usartRxBl (USART_TypeDef *instance, uint16_t *data, uint32_t len)
 
bool PHAL_usartTxDma (USART_TypeDef *instance, usart_init_t *handle, uint16_t *data, uint32_t len)
bool PHAL_usartTxDma (USART_TypeDef *instance, usart_init_t *handle, uint16_t *data, uint32_t len)
 Starts a tx using dma, use PHAL_usartTxDmaComplete to ensure the previous transmission is complete.
 
bool PHAL_usartTxDmaComplete (usart_init_t *handle)
 
bool PHAL_usartRxDma (USART_TypeDef *instance, usart_init_t *handle, uint16_t *data, uint32_t len)
bool PHAL_usartRxDma (USART_TypeDef *instance, usart_init_t *handle, uint16_t *data, uint32_t len)
 Starts an rx using dma of a specific length Use PHAL_usartRxDmaComplete to check if the entire msg has been received.
 
bool PHAL_usartRxDmaComplete (usart_init_t *handle)
bool PHAL_initUSART (USART_TypeDef *instance, usart_init_t *handle, const uint32_t fck)
 
void PHAL_usartTxBl (USART_TypeDef *instance, const uint16_t *data, uint32_t len)
void PHAL_usartTxBl (USART_TypeDef *instance, const uint16_t *data, uint32_t len)
 
void PHAL_usartRxBl (USART_TypeDef *instance, uint16_t *data, uint32_t len)
void PHAL_usartRxBl (USART_TypeDef *instance, uint16_t *data, uint32_t len)
 
bool PHAL_usartTxDma (USART_TypeDef *instance, usart_init_t *handle, uint16_t *data, uint32_t len)
bool PHAL_usartTxDma (USART_TypeDef *instance, usart_init_t *handle, uint16_t *data, uint32_t len)
 Starts a tx using dma, use PHAL_usartTxDmaComplete to ensure the previous transmission is complete.
 
bool PHAL_usartRxDma (USART_TypeDef *instance, usart_init_t *handle, uint16_t *data, uint32_t len)
bool PHAL_usartRxDma (USART_TypeDef *instance, usart_init_t *handle, uint16_t *data, uint32_t len)
 Starts an rx using dma of a specific length Use PHAL_usartRxDmaComplete to check if the entire msg has been received.
 
bool PHAL_usartTxDmaComplete (usart_init_t *handle)
bool PHAL_qspiConfigure (QUADSPI_Config_t *config)
 Configure QUADSPI peripheral for SPI Flash transactions Will setup flash size, dummy cycles, instruction width, and data width.
 
bool PHAL_qspiTrasnfer (uint8_t instruction, uint32_t address, uint8_t *data, uint32_t length)
bool PHAL_qspiTrasnfer (uint8_t instruction, uint32_t address, uint8_t *data, uint32_t length)
 
bool PHAL_qspiTrasnfer_DMA (uint8_t instruction, uint32_t address, uint8_t *data, uint32_t length)
bool PHAL_qspiTrasnfer_DMA (uint8_t instruction, uint32_t address, uint8_t *data, uint32_t length)
 

Function Documentation

diff --git a/quadspi_8h.html b/quadspi_8h.html index d50f9312..14c861ca 100644 --- a/quadspi_8h.html +++ b/quadspi_8h.html @@ -139,7 +139,7 @@ bool PHAL_qspiConfigure (QUADSPI_Config_t *config)  Configure QUADSPI peripheral for SPI Flash transactions Will setup flash size, dummy cycles, instruction width, and data width.
  -bool PHAL_qspiTrasnfer (uint8_t instruction, uint32_t address, uint8_t *data, uint32_t length) +bool PHAL_qspiTrasnfer (uint8_t instruction, uint32_t address, uint8_t *data, uint32_t length)  

Macro Definition Documentation

diff --git a/quadspi_8h_source.html b/quadspi_8h_source.html index c99a024d..9bb17f64 100644 --- a/quadspi_8h_source.html +++ b/quadspi_8h_source.html @@ -150,9 +150,10 @@
55
63bool PHAL_qspiConfigure(QUADSPI_Config_t* config);
64
-
65bool PHAL_qspiTrasnfer(uint8_t instruction, uint32_t address, uint8_t* data, uint32_t length);
+
65bool PHAL_qspiTrasnfer(uint8_t instruction, uint32_t address, uint8_t* data, uint32_t length);
66
67#endif
+
data
u8 data[8]
Definition gs_usb.h:8
config
config_t config
Definition daq.c:37
PHAL_qspiTrasnfer
bool PHAL_qspiTrasnfer(uint8_t instruction, uint32_t address, uint8_t *data, uint32_t length)
Definition quadspi.c:74
QUADSPI_LineWidth_t
QUADSPI_LineWidth_t
Definition quadspi.h:16
diff --git a/rtc_8h.html b/rtc_8h.html index 197fdbdf..feb09e9c 100644 --- a/rtc_8h.html +++ b/rtc_8h.html @@ -146,14 +146,14 @@   enum  RTC_WEEKDAY_t {
  RTC_WEEKDAY_UNKNOWN = 0x0 -, RTC_WEEKDAY_MONDAY -, RTC_WEEKDAY_TUESDAY -, RTC_WEEKDAY_WEDNESDAY +, RTC_WEEKDAY_MONDAY = 0x1 +, RTC_WEEKDAY_TUESDAY = 0x2 +, RTC_WEEKDAY_WEDNESDAY = 0x3 ,
-  RTC_WEEKDAY_THURSDAY -, RTC_WEEKDAY_FRIDAY -, RTC_WEEKDAY_SATURDAY -, RTC_WEEKDAY_SUNDAY +  RTC_WEEKDAY_THURSDAY = 0x4 +, RTC_WEEKDAY_FRIDAY = 0x5 +, RTC_WEEKDAY_SATURDAY = 0x6 +, RTC_WEEKDAY_SUNDAY = 0x7
}   diff --git a/rtc_8h_source.html b/rtc_8h_source.html index b2ba147e..7029e4f6 100644 --- a/rtc_8h_source.html +++ b/rtc_8h_source.html @@ -111,12 +111,12 @@
28// Clock source: currently only supporting LSE
29
30/*
-
31 When both prescalers are used, it is recommended to configure the asynchronous
+
31 When both prescalers are used, it is recommended to configure the asynchronous
32 prescaler to a high value to minimize consumption. (RM0090 26.3.1)
33
34 Default Configuration STM32F4
35 =======================================================
-
36 The asynchronous prescaler division factor is set to 128, and the synchronous division factor to 256,
+
36 The asynchronous prescaler division factor is set to 128, and the synchronous division factor to 256,
37 to obtain an internal clock frequency of 1 Hz (ck_spre) with an LSE frequency of 32.768 kHz.
38*/
39
@@ -155,13 +155,13 @@
80
diff --git a/sdio_8c.html b/sdio_8c.html index 5dc704ce..a837da26 100644 --- a/sdio_8c.html +++ b/sdio_8c.html @@ -212,8 +212,7 @@

-Value:
log_msg(__VA_ARGS__)
-
+

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['pstatistic_97',['pStatistic',['../structtag__nCn326iMCNAOlldGGgUCWC.html#a7a629612173bb2d5d596bec785aa4b94',1,'tag_nCn326iMCNAOlldGGgUCWC::pStatistic'],['../structtag__A9AnQ4YrsYeUCGYxAP6xUF.html#ad48b655caf9d3eea58cc6c02819b1f28',1,'tag_A9AnQ4YrsYeUCGYxAP6xUF::pStatistic'],['../structtag__nCn326iMCNAOlldGGgUCWC.html#a788bed1d140611f2b4915b8a214fdeb3',1,'tag_nCn326iMCNAOlldGGgUCWC::pStatistic']]], diff --git a/structdaq__hub__t-members.html b/structdaq__hub__t-members.html index 5756d913..b5d8434e 100644 --- a/structdaq__hub__t-members.html +++ b/structdaq__hub__t-members.html @@ -103,15 +103,16 @@ last_write_msdaq_hub_t log_enable_swdaq_hub_t log_enable_tcpdaq_hub_t - log_fpdaq_hub_t - log_start_msdaq_hub_t - loop_time_avg_msdaq_hub_t - loop_time_max_msdaq_hub_t - my_watchdaq_hub_t - sd_error_ctdaq_hub_t - sd_last_errdaq_hub_t - sd_last_err_resdaq_hub_t - sd_statedaq_hub_t + log_enable_udsdaq_hub_t + log_fpdaq_hub_t + log_start_msdaq_hub_t + loop_time_avg_msdaq_hub_t + loop_time_max_msdaq_hub_t + my_watchdaq_hub_t + sd_error_ctdaq_hub_t + sd_last_errdaq_hub_t + sd_last_err_resdaq_hub_t + sd_statedaq_hub_t

diff --git a/structdaq__hub__t.html b/structdaq__hub__t.html index 3dc4a57a..8e81dabe 100644 --- a/structdaq__hub__t.html +++ b/structdaq__hub__t.html @@ -134,6 +134,8 @@   bool log_enable_tcp   +bool log_enable_uds +  uint32_t loop_time_max_ms   uint32_t loop_time_avg_ms @@ -324,6 +326,20 @@

+

+
+ +

◆ log_enable_uds

+ +
+
+ + + + +
bool daq_hub_t::log_enable_uds
+
+
diff --git a/torque__vector_2bmi_2bmi088_8h.html b/torque__vector_2bmi_2bmi088_8h.html index 7033abdd..c6fc4d68 100644 --- a/torque__vector_2bmi_2bmi088_8h.html +++ b/torque__vector_2bmi_2bmi088_8h.html @@ -126,9 +126,9 @@   #define BMI088_GYRO_RATE_Z_LSB_ADDR   (0x04U) /* Gyro Z rate LSB address */   -#define BMI088_GYRO_RANGE_ADDR   (0x0FU) /* Gyro data range address */ +#define BMI088_GYRO_RANGE_ADDR   (0x0FU) /* Gyro data range address */   -#define BMI088_GYRO_BANDWIDTH_ADDR   (0x10U) /* Gyro data bandwidth address */ +#define BMI088_GYRO_BANDWIDTH_ADDR   (0x10U) /* Gyro data bandwidth address */   #define BMI088_GYRO_SELFTEST_ADDR   (0x3CU) /* Gyro self test address */   @@ -393,7 +393,7 @@

- +
#define BMI088_GYRO_BANDWIDTH_ADDR   (0x10U) /* Gyro data bandwidth address */#define BMI088_GYRO_BANDWIDTH_ADDR   (0x10U) /* Gyro data bandwidth address */

@@ -435,7 +435,7 @@

- +
#define BMI088_GYRO_RANGE_ADDR   (0x0FU) /* Gyro data range address */#define BMI088_GYRO_RANGE_ADDR   (0x0FU) /* Gyro data range address */

diff --git a/torque__vector_2can_2can__parse_8h_source.html b/torque__vector_2can_2can__parse_8h_source.html index 6748be8a..e2964746 100644 --- a/torque__vector_2can_2can__parse_8h_source.html +++ b/torque__vector_2can_2can__parse_8h_source.html @@ -429,7 +429,7 @@
311 } fault_sync_torque_vector;
312 struct {
313 uint64_t cmd: 8;
-
314 uint64_t data: 32;
+
314 uint64_t data: 32;
315 } torquevector_bl_cmd;
316 struct {
317 uint64_t throttle: 12;
@@ -501,7 +501,7 @@
383 uint64_t id: 16;
384 } return_fault_control;
385 uint8_t raw_data[8];
-
386} __attribute__((packed)) CanParsedData_t;
+
386} __attribute__((packed)) CanParsedData_t;
387/* END AUTO MESSAGE STRUCTURE */
388
389// contains most up to date received
@@ -510,7 +510,7 @@
392typedef struct {
393 struct {
394 uint8_t cmd;
-
395 uint32_t data;
+
395 uint32_t data;
396 } torquevector_bl_cmd;
397 struct {
398 uint16_t throttle;
@@ -644,7 +644,8 @@
CAR_STATE_RESET
@ CAR_STATE_RESET
Definition can_parse.h:238
CAR_STATE_CONSTANT_TORQUE
@ CAR_STATE_CONSTANT_TORQUE
Definition can_parse.h:240
cmd
uint8_t cmd[NXT_STR_SIZE]
Definition main.c:541
-
__attribute__
struct eeprom __attribute__
Definition daq_hub.h:70
+
data
u8 data[8]
Definition gs_usb.h:8
+
__attribute__
struct gs_tx_context __attribute__
Definition daq_hub.h:70
can.h