diff --git a/common/daq/can_config.json b/common/daq/can_config.json index c82ad538..c01ae2cd 100644 --- a/common/daq/can_config.json +++ b/common/daq/can_config.json @@ -844,6 +844,25 @@ ], "rx": [] }, + { + "node_name": "PDU", + "node_ssa":31, + "tx": [ + { + "msg_name":"pdu_test", + "msg_desc":"periodic dashboard heartbeat", + "signals":[ + {"sig_name": "test_1", "type":"uint8_t"}, + {"sig_name": "test_2", "type":"uint8_t"}, + {"sig_name": "test_3", "type":"uint8_t"} + ], + "msg_period":15, + "msg_hlp":1, + "msg_pgn":1040 + } + ], + "rx": [ ] + }, { "node_name": "Acceleration", "can_peripheral": "CAN1", diff --git a/common/daq/per_dbc.dbc b/common/daq/per_dbc.dbc index 382bdeff..af74b16f 100644 --- a/common/daq/per_dbc.dbc +++ b/common/daq/per_dbc.dbc @@ -1,7 +1,7 @@ VERSION "" -NS_ : +NS_ : NS_DESC_ CM_ BA_DEF_ @@ -423,6 +423,15 @@ BO_ 688 LWS_Standard: 5 Steering SG_ LWS_SPEED : 16|8@1+ (4,0) [0|0] "deg/s" Vector__XXX SG_ LWS_ANGLE : 0|16@1- (0.1,0) [0|0] "deg" Vector__XXX +BO_ 2214659103 pdu_test: 3 PDU + SG_ test_3 : 16|8@1+ (1,0) [0|0] "" Vector__XXX + SG_ test_2 : 8|8@1+ (1,0) [0|0] "" Vector__XXX + SG_ test_1 : 0|8@1+ (1,0) [0|0] "" Vector__XXX + +BO_ 2148059999 fault_sync_pdu: 3 PDU + SG_ latched : 16|1@1+ (1,0) [0|0] "" Vector__XXX + SG_ idx : 0|16@1+ (1,0) [0|0] "" Vector__XXX + BO_ 372 Y_Accel: 8 Acceleration SG_ Reserved_3 : 56|8@1+ (1,0) [0|0] "" Vector__XXX SG_ Reserved_2 : 48|8@1+ (1,0) [0|0] "" Vector__XXX @@ -797,7 +806,7 @@ BO_ 2147488308 adc_values: 5 TEST_NODE BO_ 2347693088 car_state: 1 TEST_NODE SG_ car_state : 0|8@1+ (1,0) [0|0] "" Vector__XXX -BO_ 2148060031 fault_sync_test_node: 3 TEST_NODE +BO_ 2148060095 fault_sync_test_node: 3 TEST_NODE SG_ latched : 16|1@1+ (1,0) [0|0] "" Vector__XXX SG_ idx : 0|16@1+ (1,0) [0|0] "" Vector__XXX @@ -841,6 +850,7 @@ CM_ BU_ OrionBMS ""; CM_ BU_ torque_vector ""; CM_ BU_ Dashboard ""; CM_ BU_ Steering ""; +CM_ BU_ PDU ""; CM_ BU_ Acceleration ""; CM_ BU_ bootloader ""; CM_ BU_ BMS_LV ""; @@ -899,11 +909,11 @@ CM_ SG_ 2415925569 LV5_I ""; CM_ SG_ 2415925569 LV24_I ""; CM_ BO_ 2415925633 "performance metrics of MCU"; CM_ SG_ 2415925633 can_tx_fails "Number of CAN transmit failures"; -CM_ SG_ 2415925633 sched_error "PSCHED Error Flags (bit #) - 0 - N/A -1 - no free task -2 - FG Miss -3 - BG Miss +CM_ SG_ 2415925633 sched_error "PSCHED Error Flags (bit #) + 0 - N/A +1 - no free task +2 - FG Miss +3 - BG Miss 4 - Individual FG Miss"; CM_ SG_ 2415925633 background_use "Percent of the 1ms loop time used by background tasks"; CM_ SG_ 2415925633 foreground_use "Percent of the 1ms loop time used by foreground tasks"; @@ -1179,6 +1189,13 @@ CM_ SG_ 688 Cal ""; CM_ SG_ 688 Ok ""; CM_ SG_ 688 LWS_SPEED ""; CM_ SG_ 688 LWS_ANGLE ""; +CM_ BO_ 2214659103 "periodic dashboard heartbeat"; +CM_ SG_ 2214659103 test_3 ""; +CM_ SG_ 2214659103 test_2 ""; +CM_ SG_ 2214659103 test_1 ""; +CM_ BO_ 2148059999 "Fault status message"; +CM_ SG_ 2148059999 latched ""; +CM_ SG_ 2148059999 idx ""; CM_ BO_ 372 "Y Acceleration Update"; CM_ SG_ 372 Reserved_3 ""; CM_ SG_ 372 Reserved_2 ""; @@ -1472,9 +1489,9 @@ CM_ SG_ 2147488308 pot2 ""; CM_ SG_ 2147488308 pot1 ""; CM_ BO_ 2347693088 "state of the car"; CM_ SG_ 2347693088 car_state ""; -CM_ BO_ 2148060031 "Fault status message"; -CM_ SG_ 2148060031 latched ""; -CM_ SG_ 2148060031 idx ""; +CM_ BO_ 2148060095 "Fault status message"; +CM_ SG_ 2148060095 latched ""; +CM_ SG_ 2148060095 idx ""; CM_ BO_ 2550136831 "daq response from node TEST_NODE"; CM_ SG_ 2550136831 daq_response ""; CM_ BO_ 2483028093 "test_msg desc"; @@ -1520,5 +1537,3 @@ SIG_VALTYPE_ 2214593731 P_c : 1; SIG_VALTYPE_ 2348810751 left_speed : 1; SIG_VALTYPE_ 2348810751 right_speed : 1; SIG_VALTYPE_ 2483028349 test_sig5_3 : 1; - - diff --git a/common/faults/fault_config.json b/common/faults/fault_config.json index 314b3b5c..8caf16e2 100644 --- a/common/faults/fault_config.json +++ b/common/faults/fault_config.json @@ -1,6 +1,20 @@ { "$schema":"./fault_schema.json", "modules": [ + { + "node_name": "pdu", + "faults": [ + { + "fault_name": "pdu_mcu_temp_high", + "max": 50, + "min": 0, + "priority": "warning", + "time_to_latch": 1000, + "time_to_unlatch": 2000, + "lcd_message": "HIGH PDU MCU TEMP" + } + ] + }, { "node_name": "main_module", "faults": [ diff --git a/common/faults/faults.c b/common/faults/faults.c index 57d877c3..36cd04ec 100644 --- a/common/faults/faults.c +++ b/common/faults/faults.c @@ -13,24 +13,25 @@ #include "common/psched/psched.h" //BEGIN AUTO FAULT INFO ARRAY DEFS -uint16_t faultLatchTime[TOTAL_NUM_FAULTS] = { PCHG_IMPLAUS_LATCH_TIME, RTD_EXIT_LATCH_TIME, LEFT_MC_CONN_LATCH_TIME, RIGHT_MC_CONN_LATCH_TIME, MCU_TEMP_HIGH_LATCH_TIME, LV_BAT_LOW_LATCH_TIME, - LV_BAT_VERY_LOW_LATCH_TIME, LV_BAT_BMS_LATCH_TIME, DRIVE_FLOW_LATCH_TIME, MOT_FRONT_OT_LATCH_TIME, WLSPD_L_LATCH_TIME, WLSPD_R_LATCH_TIME, DRIVELINE_COMM_LATCH_TIME, - APPS_WIRING_T1_LATCH_TIME, APPS_WIRING_T2_LATCH_TIME, BSE_LATCH_TIME, BSPD_LATCH_TIME, IMPLAUS_DETECTED_LATCH_TIME, APPS_BRAKE_LATCH_TIME, DISCHARGE_LIMIT_ENFORCE_LATCH_TIME, - CHARGER_SAFETY_RELAY_LATCH_TIME, INTERNAL_HARDWARE_LATCH_TIME, HEATSINK_THERMISTOR_LATCH_TIME, SOFTWARE_LATCH_TIME, MAX_CELLV_HIGH_LATCH_TIME, MIN_CELLV_LOW_LATCH_TIME, PACK_OVERHEAT_ORION_LATCH_TIME, - INTERNAL_COMMS_LATCH_TIME, CELL_BALANCING_FOFF_LATCH_TIME, WEAK_CELL_LATCH_TIME, LOW_CELLV_LATCH_TIME, OPEN_WIRE_LATCH_TIME, CURRENT_SENSOR_LATCH_TIME, MAX_CELLV_O5V_LATCH_TIME, - CELL_ASIC_LATCH_TIME, WEAK_PACK_LATCH_TIME, FAN_MONITOR_LATCH_TIME, THERMISTOR_LATCH_TIME, EXTERNAL_COMMS_LATCH_TIME, REDUNDANT_PSU_LATCH_TIME, HV_ISOLATION_LATCH_TIME, - INPUT_PSU_LATCH_TIME, CHARGE_LIMIT_ENFORCE_LATCH_TIME, PACK_TEMP_LATCH_TIME, PACK_TEMP_EXCEEDED_LATCH_TIME, MIN_PACK_TEMP_LATCH_TIME, IMD_LATCH_TIME, TV_OFFLINE_LATCH_TIME, - TEST_FAULT_1_LATCH_TIME, TEST_FAULT_2_LATCH_TIME, TEST_FAULT_3_LATCH_TIME, TEST_FAULT_4_LATCH_TIME,}; -uint16_t faultULatchTime[TOTAL_NUM_FAULTS] = { PCHG_IMPLAUS_UNLATCH_TIME, RTD_EXIT_UNLATCH_TIME, LEFT_MC_CONN_UNLATCH_TIME, RIGHT_MC_CONN_UNLATCH_TIME, MCU_TEMP_HIGH_UNLATCH_TIME, LV_BAT_LOW_UNLATCH_TIME, - LV_BAT_VERY_LOW_UNLATCH_TIME, LV_BAT_BMS_UNLATCH_TIME, DRIVE_FLOW_UNLATCH_TIME, MOT_FRONT_OT_UNLATCH_TIME, WLSPD_L_UNLATCH_TIME, WLSPD_R_UNLATCH_TIME, DRIVELINE_COMM_UNLATCH_TIME, - APPS_WIRING_T1_UNLATCH_TIME, APPS_WIRING_T2_UNLATCH_TIME, BSE_UNLATCH_TIME, BSPD_UNLATCH_TIME, IMPLAUS_DETECTED_UNLATCH_TIME, APPS_BRAKE_UNLATCH_TIME, DISCHARGE_LIMIT_ENFORCE_UNLATCH_TIME, - CHARGER_SAFETY_RELAY_UNLATCH_TIME, INTERNAL_HARDWARE_UNLATCH_TIME, HEATSINK_THERMISTOR_UNLATCH_TIME, SOFTWARE_UNLATCH_TIME, MAX_CELLV_HIGH_UNLATCH_TIME, MIN_CELLV_LOW_UNLATCH_TIME, PACK_OVERHEAT_ORION_UNLATCH_TIME, - INTERNAL_COMMS_UNLATCH_TIME, CELL_BALANCING_FOFF_UNLATCH_TIME, WEAK_CELL_UNLATCH_TIME, LOW_CELLV_UNLATCH_TIME, OPEN_WIRE_UNLATCH_TIME, CURRENT_SENSOR_UNLATCH_TIME, MAX_CELLV_O5V_UNLATCH_TIME, - CELL_ASIC_UNLATCH_TIME, WEAK_PACK_UNLATCH_TIME, FAN_MONITOR_UNLATCH_TIME, THERMISTOR_UNLATCH_TIME, EXTERNAL_COMMS_UNLATCH_TIME, REDUNDANT_PSU_UNLATCH_TIME, HV_ISOLATION_UNLATCH_TIME, - INPUT_PSU_UNLATCH_TIME, CHARGE_LIMIT_ENFORCE_UNLATCH_TIME, PACK_TEMP_UNLATCH_TIME, PACK_TEMP_EXCEEDED_UNLATCH_TIME, MIN_PACK_TEMP_UNLATCH_TIME, IMD_UNLATCH_TIME, TV_OFFLINE_UNLATCH_TIME, - TEST_FAULT_1_UNLATCH_TIME, TEST_FAULT_2_UNLATCH_TIME, TEST_FAULT_3_UNLATCH_TIME, TEST_FAULT_4_UNLATCH_TIME,}; +uint16_t faultLatchTime[TOTAL_NUM_FAULTS] = { PDU_MCU_TEMP_HIGH_LATCH_TIME, PCHG_IMPLAUS_LATCH_TIME, RTD_EXIT_LATCH_TIME, LEFT_MC_CONN_LATCH_TIME, RIGHT_MC_CONN_LATCH_TIME, MCU_TEMP_HIGH_LATCH_TIME, + LV_BAT_LOW_LATCH_TIME, LV_BAT_VERY_LOW_LATCH_TIME, LV_BAT_BMS_LATCH_TIME, DRIVE_FLOW_LATCH_TIME, MOT_FRONT_OT_LATCH_TIME, WLSPD_L_LATCH_TIME, WLSPD_R_LATCH_TIME, + DRIVELINE_COMM_LATCH_TIME, APPS_WIRING_T1_LATCH_TIME, APPS_WIRING_T2_LATCH_TIME, BSE_LATCH_TIME, BSPD_LATCH_TIME, IMPLAUS_DETECTED_LATCH_TIME, APPS_BRAKE_LATCH_TIME, + DISCHARGE_LIMIT_ENFORCE_LATCH_TIME, CHARGER_SAFETY_RELAY_LATCH_TIME, INTERNAL_HARDWARE_LATCH_TIME, HEATSINK_THERMISTOR_LATCH_TIME, SOFTWARE_LATCH_TIME, MAX_CELLV_HIGH_LATCH_TIME, MIN_CELLV_LOW_LATCH_TIME, + PACK_OVERHEAT_ORION_LATCH_TIME, INTERNAL_COMMS_LATCH_TIME, CELL_BALANCING_FOFF_LATCH_TIME, WEAK_CELL_LATCH_TIME, LOW_CELLV_LATCH_TIME, OPEN_WIRE_LATCH_TIME, CURRENT_SENSOR_LATCH_TIME, + MAX_CELLV_O5V_LATCH_TIME, CELL_ASIC_LATCH_TIME, WEAK_PACK_LATCH_TIME, FAN_MONITOR_LATCH_TIME, THERMISTOR_LATCH_TIME, EXTERNAL_COMMS_LATCH_TIME, REDUNDANT_PSU_LATCH_TIME, + HV_ISOLATION_LATCH_TIME, INPUT_PSU_LATCH_TIME, CHARGE_LIMIT_ENFORCE_LATCH_TIME, PACK_TEMP_LATCH_TIME, PACK_TEMP_EXCEEDED_LATCH_TIME, MIN_PACK_TEMP_LATCH_TIME, IMD_LATCH_TIME, + TV_OFFLINE_LATCH_TIME, TEST_FAULT_1_LATCH_TIME, TEST_FAULT_2_LATCH_TIME, TEST_FAULT_3_LATCH_TIME, TEST_FAULT_4_LATCH_TIME,}; +uint16_t faultULatchTime[TOTAL_NUM_FAULTS] = { PDU_MCU_TEMP_HIGH_UNLATCH_TIME, PCHG_IMPLAUS_UNLATCH_TIME, RTD_EXIT_UNLATCH_TIME, LEFT_MC_CONN_UNLATCH_TIME, RIGHT_MC_CONN_UNLATCH_TIME, MCU_TEMP_HIGH_UNLATCH_TIME, + LV_BAT_LOW_UNLATCH_TIME, LV_BAT_VERY_LOW_UNLATCH_TIME, LV_BAT_BMS_UNLATCH_TIME, DRIVE_FLOW_UNLATCH_TIME, MOT_FRONT_OT_UNLATCH_TIME, WLSPD_L_UNLATCH_TIME, WLSPD_R_UNLATCH_TIME, + DRIVELINE_COMM_UNLATCH_TIME, APPS_WIRING_T1_UNLATCH_TIME, APPS_WIRING_T2_UNLATCH_TIME, BSE_UNLATCH_TIME, BSPD_UNLATCH_TIME, IMPLAUS_DETECTED_UNLATCH_TIME, APPS_BRAKE_UNLATCH_TIME, + DISCHARGE_LIMIT_ENFORCE_UNLATCH_TIME, CHARGER_SAFETY_RELAY_UNLATCH_TIME, INTERNAL_HARDWARE_UNLATCH_TIME, HEATSINK_THERMISTOR_UNLATCH_TIME, SOFTWARE_UNLATCH_TIME, MAX_CELLV_HIGH_UNLATCH_TIME, MIN_CELLV_LOW_UNLATCH_TIME, + PACK_OVERHEAT_ORION_UNLATCH_TIME, INTERNAL_COMMS_UNLATCH_TIME, CELL_BALANCING_FOFF_UNLATCH_TIME, WEAK_CELL_UNLATCH_TIME, LOW_CELLV_UNLATCH_TIME, OPEN_WIRE_UNLATCH_TIME, CURRENT_SENSOR_UNLATCH_TIME, + MAX_CELLV_O5V_UNLATCH_TIME, CELL_ASIC_UNLATCH_TIME, WEAK_PACK_UNLATCH_TIME, FAN_MONITOR_UNLATCH_TIME, THERMISTOR_UNLATCH_TIME, EXTERNAL_COMMS_UNLATCH_TIME, REDUNDANT_PSU_UNLATCH_TIME, + HV_ISOLATION_UNLATCH_TIME, INPUT_PSU_UNLATCH_TIME, CHARGE_LIMIT_ENFORCE_UNLATCH_TIME, PACK_TEMP_UNLATCH_TIME, PACK_TEMP_EXCEEDED_UNLATCH_TIME, MIN_PACK_TEMP_UNLATCH_TIME, IMD_UNLATCH_TIME, + TV_OFFLINE_UNLATCH_TIME, TEST_FAULT_1_UNLATCH_TIME, TEST_FAULT_2_UNLATCH_TIME, TEST_FAULT_3_UNLATCH_TIME, TEST_FAULT_4_UNLATCH_TIME,}; //Global arrays with all faults fault_status_t statusArray[TOTAL_NUM_FAULTS] = { + (fault_status_t){false, ID_PDU_MCU_TEMP_HIGH_FAULT}, (fault_status_t){false, ID_PCHG_IMPLAUS_FAULT}, (fault_status_t){false, ID_RTD_EXIT_FAULT}, (fault_status_t){false, ID_LEFT_MC_CONN_FAULT}, @@ -85,58 +86,59 @@ fault_status_t statusArray[TOTAL_NUM_FAULTS] = { (fault_status_t){false, ID_TEST_FAULT_4_FAULT}, }; fault_attributes_t faultArray[TOTAL_NUM_FAULTS] = { - (fault_attributes_t){false, false, PCHG_IMPLAUS_PRIORITY, 0, 0, PCHG_IMPLAUS_MAX, PCHG_IMPLAUS_MIN, &statusArray[0], 0, PCHG_IMPLAUS_MSG}, - (fault_attributes_t){false, false, RTD_EXIT_PRIORITY, 0, 0, RTD_EXIT_MAX, RTD_EXIT_MIN, &statusArray[1], 0, RTD_EXIT_MSG}, - (fault_attributes_t){false, false, LEFT_MC_CONN_PRIORITY, 0, 0, LEFT_MC_CONN_MAX, LEFT_MC_CONN_MIN, &statusArray[2], 0, LEFT_MC_CONN_MSG}, - (fault_attributes_t){false, false, RIGHT_MC_CONN_PRIORITY, 0, 0, RIGHT_MC_CONN_MAX, RIGHT_MC_CONN_MIN, &statusArray[3], 0, RIGHT_MC_CONN_MSG}, - (fault_attributes_t){false, false, MCU_TEMP_HIGH_PRIORITY, 0, 0, MCU_TEMP_HIGH_MAX, MCU_TEMP_HIGH_MIN, &statusArray[4], 0, MCU_TEMP_HIGH_MSG}, - (fault_attributes_t){false, false, LV_BAT_LOW_PRIORITY, 0, 0, LV_BAT_LOW_MAX, LV_BAT_LOW_MIN, &statusArray[5], 0, LV_BAT_LOW_MSG}, - (fault_attributes_t){false, false, LV_BAT_VERY_LOW_PRIORITY, 0, 0, LV_BAT_VERY_LOW_MAX, LV_BAT_VERY_LOW_MIN, &statusArray[6], 0, LV_BAT_VERY_LOW_MSG}, - (fault_attributes_t){false, false, LV_BAT_BMS_PRIORITY, 0, 0, LV_BAT_BMS_MAX, LV_BAT_BMS_MIN, &statusArray[7], 0, LV_BAT_BMS_MSG}, - (fault_attributes_t){false, false, DRIVE_FLOW_PRIORITY, 0, 0, DRIVE_FLOW_MAX, DRIVE_FLOW_MIN, &statusArray[8], 0, DRIVE_FLOW_MSG}, - (fault_attributes_t){false, false, MOT_FRONT_OT_PRIORITY, 0, 0, MOT_FRONT_OT_MAX, MOT_FRONT_OT_MIN, &statusArray[9], 0, MOT_FRONT_OT_MSG}, - (fault_attributes_t){false, false, WLSPD_L_PRIORITY, 0, 0, WLSPD_L_MAX, WLSPD_L_MIN, &statusArray[10], 0, WLSPD_L_MSG}, - (fault_attributes_t){false, false, WLSPD_R_PRIORITY, 0, 0, WLSPD_R_MAX, WLSPD_R_MIN, &statusArray[11], 0, WLSPD_R_MSG}, - (fault_attributes_t){false, false, DRIVELINE_COMM_PRIORITY, 0, 0, DRIVELINE_COMM_MAX, DRIVELINE_COMM_MIN, &statusArray[12], 0, DRIVELINE_COMM_MSG}, - (fault_attributes_t){false, false, APPS_WIRING_T1_PRIORITY, 0, 0, APPS_WIRING_T1_MAX, APPS_WIRING_T1_MIN, &statusArray[13], 0, APPS_WIRING_T1_MSG}, - (fault_attributes_t){false, false, APPS_WIRING_T2_PRIORITY, 0, 0, APPS_WIRING_T2_MAX, APPS_WIRING_T2_MIN, &statusArray[14], 0, APPS_WIRING_T2_MSG}, - (fault_attributes_t){false, false, BSE_PRIORITY, 0, 0, BSE_MAX, BSE_MIN, &statusArray[15], 0, BSE_MSG}, - (fault_attributes_t){false, false, BSPD_PRIORITY, 0, 0, BSPD_MAX, BSPD_MIN, &statusArray[16], 0, BSPD_MSG}, - (fault_attributes_t){false, false, IMPLAUS_DETECTED_PRIORITY, 0, 0, IMPLAUS_DETECTED_MAX, IMPLAUS_DETECTED_MIN, &statusArray[17], 0, IMPLAUS_DETECTED_MSG}, - (fault_attributes_t){false, false, APPS_BRAKE_PRIORITY, 0, 0, APPS_BRAKE_MAX, APPS_BRAKE_MIN, &statusArray[18], 0, APPS_BRAKE_MSG}, - (fault_attributes_t){false, false, DISCHARGE_LIMIT_ENFORCE_PRIORITY, 0, 0, DISCHARGE_LIMIT_ENFORCE_MAX, DISCHARGE_LIMIT_ENFORCE_MIN, &statusArray[19], 0, DISCHARGE_LIMIT_ENFORCE_MSG}, - (fault_attributes_t){false, false, CHARGER_SAFETY_RELAY_PRIORITY, 0, 0, CHARGER_SAFETY_RELAY_MAX, CHARGER_SAFETY_RELAY_MIN, &statusArray[20], 0, CHARGER_SAFETY_RELAY_MSG}, - (fault_attributes_t){false, false, INTERNAL_HARDWARE_PRIORITY, 0, 0, INTERNAL_HARDWARE_MAX, INTERNAL_HARDWARE_MIN, &statusArray[21], 0, INTERNAL_HARDWARE_MSG}, - (fault_attributes_t){false, false, HEATSINK_THERMISTOR_PRIORITY, 0, 0, HEATSINK_THERMISTOR_MAX, HEATSINK_THERMISTOR_MIN, &statusArray[22], 0, HEATSINK_THERMISTOR_MSG}, - (fault_attributes_t){false, false, SOFTWARE_PRIORITY, 0, 0, SOFTWARE_MAX, SOFTWARE_MIN, &statusArray[23], 0, SOFTWARE_MSG}, - (fault_attributes_t){false, false, MAX_CELLV_HIGH_PRIORITY, 0, 0, MAX_CELLV_HIGH_MAX, MAX_CELLV_HIGH_MIN, &statusArray[24], 0, MAX_CELLV_HIGH_MSG}, - (fault_attributes_t){false, false, MIN_CELLV_LOW_PRIORITY, 0, 0, MIN_CELLV_LOW_MAX, MIN_CELLV_LOW_MIN, &statusArray[25], 0, MIN_CELLV_LOW_MSG}, - (fault_attributes_t){false, false, PACK_OVERHEAT_ORION_PRIORITY, 0, 0, PACK_OVERHEAT_ORION_MAX, PACK_OVERHEAT_ORION_MIN, &statusArray[26], 0, PACK_OVERHEAT_ORION_MSG}, - (fault_attributes_t){false, false, INTERNAL_COMMS_PRIORITY, 0, 0, INTERNAL_COMMS_MAX, INTERNAL_COMMS_MIN, &statusArray[27], 0, INTERNAL_COMMS_MSG}, - (fault_attributes_t){false, false, CELL_BALANCING_FOFF_PRIORITY, 0, 0, CELL_BALANCING_FOFF_MAX, CELL_BALANCING_FOFF_MIN, &statusArray[28], 0, CELL_BALANCING_FOFF_MSG}, - (fault_attributes_t){false, false, WEAK_CELL_PRIORITY, 0, 0, WEAK_CELL_MAX, WEAK_CELL_MIN, &statusArray[29], 0, WEAK_CELL_MSG}, - (fault_attributes_t){false, false, LOW_CELLV_PRIORITY, 0, 0, LOW_CELLV_MAX, LOW_CELLV_MIN, &statusArray[30], 0, LOW_CELLV_MSG}, - (fault_attributes_t){false, false, OPEN_WIRE_PRIORITY, 0, 0, OPEN_WIRE_MAX, OPEN_WIRE_MIN, &statusArray[31], 0, OPEN_WIRE_MSG}, - (fault_attributes_t){false, false, CURRENT_SENSOR_PRIORITY, 0, 0, CURRENT_SENSOR_MAX, CURRENT_SENSOR_MIN, &statusArray[32], 0, CURRENT_SENSOR_MSG}, - (fault_attributes_t){false, false, MAX_CELLV_O5V_PRIORITY, 0, 0, MAX_CELLV_O5V_MAX, MAX_CELLV_O5V_MIN, &statusArray[33], 0, MAX_CELLV_O5V_MSG}, - (fault_attributes_t){false, false, CELL_ASIC_PRIORITY, 0, 0, CELL_ASIC_MAX, CELL_ASIC_MIN, &statusArray[34], 0, CELL_ASIC_MSG}, - (fault_attributes_t){false, false, WEAK_PACK_PRIORITY, 0, 0, WEAK_PACK_MAX, WEAK_PACK_MIN, &statusArray[35], 0, WEAK_PACK_MSG}, - (fault_attributes_t){false, false, FAN_MONITOR_PRIORITY, 0, 0, FAN_MONITOR_MAX, FAN_MONITOR_MIN, &statusArray[36], 0, FAN_MONITOR_MSG}, - (fault_attributes_t){false, false, THERMISTOR_PRIORITY, 0, 0, THERMISTOR_MAX, THERMISTOR_MIN, &statusArray[37], 0, THERMISTOR_MSG}, - (fault_attributes_t){false, false, EXTERNAL_COMMS_PRIORITY, 0, 0, EXTERNAL_COMMS_MAX, EXTERNAL_COMMS_MIN, &statusArray[38], 0, EXTERNAL_COMMS_MSG}, - (fault_attributes_t){false, false, REDUNDANT_PSU_PRIORITY, 0, 0, REDUNDANT_PSU_MAX, REDUNDANT_PSU_MIN, &statusArray[39], 0, REDUNDANT_PSU_MSG}, - (fault_attributes_t){false, false, HV_ISOLATION_PRIORITY, 0, 0, HV_ISOLATION_MAX, HV_ISOLATION_MIN, &statusArray[40], 0, HV_ISOLATION_MSG}, - (fault_attributes_t){false, false, INPUT_PSU_PRIORITY, 0, 0, INPUT_PSU_MAX, INPUT_PSU_MIN, &statusArray[41], 0, INPUT_PSU_MSG}, - (fault_attributes_t){false, false, CHARGE_LIMIT_ENFORCE_PRIORITY, 0, 0, CHARGE_LIMIT_ENFORCE_MAX, CHARGE_LIMIT_ENFORCE_MIN, &statusArray[42], 0, CHARGE_LIMIT_ENFORCE_MSG}, - (fault_attributes_t){false, false, PACK_TEMP_PRIORITY, 0, 0, PACK_TEMP_MAX, PACK_TEMP_MIN, &statusArray[43], 0, PACK_TEMP_MSG}, - (fault_attributes_t){false, false, PACK_TEMP_EXCEEDED_PRIORITY, 0, 0, PACK_TEMP_EXCEEDED_MAX, PACK_TEMP_EXCEEDED_MIN, &statusArray[44], 0, PACK_TEMP_EXCEEDED_MSG}, - (fault_attributes_t){false, false, MIN_PACK_TEMP_PRIORITY, 0, 0, MIN_PACK_TEMP_MAX, MIN_PACK_TEMP_MIN, &statusArray[45], 0, MIN_PACK_TEMP_MSG}, - (fault_attributes_t){false, false, IMD_PRIORITY, 0, 0, IMD_MAX, IMD_MIN, &statusArray[46], 0, IMD_MSG}, - (fault_attributes_t){false, false, TV_OFFLINE_PRIORITY, 0, 0, TV_OFFLINE_MAX, TV_OFFLINE_MIN, &statusArray[47], 0, TV_OFFLINE_MSG}, - (fault_attributes_t){false, false, TEST_FAULT_1_PRIORITY, 0, 0, TEST_FAULT_1_MAX, TEST_FAULT_1_MIN, &statusArray[48], 0, TEST_FAULT_1_MSG}, - (fault_attributes_t){false, false, TEST_FAULT_2_PRIORITY, 0, 0, TEST_FAULT_2_MAX, TEST_FAULT_2_MIN, &statusArray[49], 0, TEST_FAULT_2_MSG}, - (fault_attributes_t){false, false, TEST_FAULT_3_PRIORITY, 0, 0, TEST_FAULT_3_MAX, TEST_FAULT_3_MIN, &statusArray[50], 0, TEST_FAULT_3_MSG}, - (fault_attributes_t){false, false, TEST_FAULT_4_PRIORITY, 0, 0, TEST_FAULT_4_MAX, TEST_FAULT_4_MIN, &statusArray[51], 0, TEST_FAULT_4_MSG}, + (fault_attributes_t){false, false, PDU_MCU_TEMP_HIGH_PRIORITY, 0, 0, PDU_MCU_TEMP_HIGH_MAX, PDU_MCU_TEMP_HIGH_MIN, &statusArray[0], 0, PDU_MCU_TEMP_HIGH_MSG}, + (fault_attributes_t){false, false, PCHG_IMPLAUS_PRIORITY, 0, 0, PCHG_IMPLAUS_MAX, PCHG_IMPLAUS_MIN, &statusArray[1], 0, PCHG_IMPLAUS_MSG}, + (fault_attributes_t){false, false, RTD_EXIT_PRIORITY, 0, 0, RTD_EXIT_MAX, RTD_EXIT_MIN, &statusArray[2], 0, RTD_EXIT_MSG}, + (fault_attributes_t){false, false, LEFT_MC_CONN_PRIORITY, 0, 0, LEFT_MC_CONN_MAX, LEFT_MC_CONN_MIN, &statusArray[3], 0, LEFT_MC_CONN_MSG}, + (fault_attributes_t){false, false, RIGHT_MC_CONN_PRIORITY, 0, 0, RIGHT_MC_CONN_MAX, RIGHT_MC_CONN_MIN, &statusArray[4], 0, RIGHT_MC_CONN_MSG}, + (fault_attributes_t){false, false, MCU_TEMP_HIGH_PRIORITY, 0, 0, MCU_TEMP_HIGH_MAX, MCU_TEMP_HIGH_MIN, &statusArray[5], 0, MCU_TEMP_HIGH_MSG}, + (fault_attributes_t){false, false, LV_BAT_LOW_PRIORITY, 0, 0, LV_BAT_LOW_MAX, LV_BAT_LOW_MIN, &statusArray[6], 0, LV_BAT_LOW_MSG}, + (fault_attributes_t){false, false, LV_BAT_VERY_LOW_PRIORITY, 0, 0, LV_BAT_VERY_LOW_MAX, LV_BAT_VERY_LOW_MIN, &statusArray[7], 0, LV_BAT_VERY_LOW_MSG}, + (fault_attributes_t){false, false, LV_BAT_BMS_PRIORITY, 0, 0, LV_BAT_BMS_MAX, LV_BAT_BMS_MIN, &statusArray[8], 0, LV_BAT_BMS_MSG}, + (fault_attributes_t){false, false, DRIVE_FLOW_PRIORITY, 0, 0, DRIVE_FLOW_MAX, DRIVE_FLOW_MIN, &statusArray[9], 0, DRIVE_FLOW_MSG}, + (fault_attributes_t){false, false, MOT_FRONT_OT_PRIORITY, 0, 0, MOT_FRONT_OT_MAX, MOT_FRONT_OT_MIN, &statusArray[10], 0, MOT_FRONT_OT_MSG}, + (fault_attributes_t){false, false, WLSPD_L_PRIORITY, 0, 0, WLSPD_L_MAX, WLSPD_L_MIN, &statusArray[11], 0, WLSPD_L_MSG}, + (fault_attributes_t){false, false, WLSPD_R_PRIORITY, 0, 0, WLSPD_R_MAX, WLSPD_R_MIN, &statusArray[12], 0, WLSPD_R_MSG}, + (fault_attributes_t){false, false, DRIVELINE_COMM_PRIORITY, 0, 0, DRIVELINE_COMM_MAX, DRIVELINE_COMM_MIN, &statusArray[13], 0, DRIVELINE_COMM_MSG}, + (fault_attributes_t){false, false, APPS_WIRING_T1_PRIORITY, 0, 0, APPS_WIRING_T1_MAX, APPS_WIRING_T1_MIN, &statusArray[14], 0, APPS_WIRING_T1_MSG}, + (fault_attributes_t){false, false, APPS_WIRING_T2_PRIORITY, 0, 0, APPS_WIRING_T2_MAX, APPS_WIRING_T2_MIN, &statusArray[15], 0, APPS_WIRING_T2_MSG}, + (fault_attributes_t){false, false, BSE_PRIORITY, 0, 0, BSE_MAX, BSE_MIN, &statusArray[16], 0, BSE_MSG}, + (fault_attributes_t){false, false, BSPD_PRIORITY, 0, 0, BSPD_MAX, BSPD_MIN, &statusArray[17], 0, BSPD_MSG}, + (fault_attributes_t){false, false, IMPLAUS_DETECTED_PRIORITY, 0, 0, IMPLAUS_DETECTED_MAX, IMPLAUS_DETECTED_MIN, &statusArray[18], 0, IMPLAUS_DETECTED_MSG}, + (fault_attributes_t){false, false, APPS_BRAKE_PRIORITY, 0, 0, APPS_BRAKE_MAX, APPS_BRAKE_MIN, &statusArray[19], 0, APPS_BRAKE_MSG}, + (fault_attributes_t){false, false, DISCHARGE_LIMIT_ENFORCE_PRIORITY, 0, 0, DISCHARGE_LIMIT_ENFORCE_MAX, DISCHARGE_LIMIT_ENFORCE_MIN, &statusArray[20], 0, DISCHARGE_LIMIT_ENFORCE_MSG}, + (fault_attributes_t){false, false, CHARGER_SAFETY_RELAY_PRIORITY, 0, 0, CHARGER_SAFETY_RELAY_MAX, CHARGER_SAFETY_RELAY_MIN, &statusArray[21], 0, CHARGER_SAFETY_RELAY_MSG}, + (fault_attributes_t){false, false, INTERNAL_HARDWARE_PRIORITY, 0, 0, INTERNAL_HARDWARE_MAX, INTERNAL_HARDWARE_MIN, &statusArray[22], 0, INTERNAL_HARDWARE_MSG}, + (fault_attributes_t){false, false, HEATSINK_THERMISTOR_PRIORITY, 0, 0, HEATSINK_THERMISTOR_MAX, HEATSINK_THERMISTOR_MIN, &statusArray[23], 0, HEATSINK_THERMISTOR_MSG}, + (fault_attributes_t){false, false, SOFTWARE_PRIORITY, 0, 0, SOFTWARE_MAX, SOFTWARE_MIN, &statusArray[24], 0, SOFTWARE_MSG}, + (fault_attributes_t){false, false, MAX_CELLV_HIGH_PRIORITY, 0, 0, MAX_CELLV_HIGH_MAX, MAX_CELLV_HIGH_MIN, &statusArray[25], 0, MAX_CELLV_HIGH_MSG}, + (fault_attributes_t){false, false, MIN_CELLV_LOW_PRIORITY, 0, 0, MIN_CELLV_LOW_MAX, MIN_CELLV_LOW_MIN, &statusArray[26], 0, MIN_CELLV_LOW_MSG}, + (fault_attributes_t){false, false, PACK_OVERHEAT_ORION_PRIORITY, 0, 0, PACK_OVERHEAT_ORION_MAX, PACK_OVERHEAT_ORION_MIN, &statusArray[27], 0, PACK_OVERHEAT_ORION_MSG}, + (fault_attributes_t){false, false, INTERNAL_COMMS_PRIORITY, 0, 0, INTERNAL_COMMS_MAX, INTERNAL_COMMS_MIN, &statusArray[28], 0, INTERNAL_COMMS_MSG}, + (fault_attributes_t){false, false, CELL_BALANCING_FOFF_PRIORITY, 0, 0, CELL_BALANCING_FOFF_MAX, CELL_BALANCING_FOFF_MIN, &statusArray[29], 0, CELL_BALANCING_FOFF_MSG}, + (fault_attributes_t){false, false, WEAK_CELL_PRIORITY, 0, 0, WEAK_CELL_MAX, WEAK_CELL_MIN, &statusArray[30], 0, WEAK_CELL_MSG}, + (fault_attributes_t){false, false, LOW_CELLV_PRIORITY, 0, 0, LOW_CELLV_MAX, LOW_CELLV_MIN, &statusArray[31], 0, LOW_CELLV_MSG}, + (fault_attributes_t){false, false, OPEN_WIRE_PRIORITY, 0, 0, OPEN_WIRE_MAX, OPEN_WIRE_MIN, &statusArray[32], 0, OPEN_WIRE_MSG}, + (fault_attributes_t){false, false, CURRENT_SENSOR_PRIORITY, 0, 0, CURRENT_SENSOR_MAX, CURRENT_SENSOR_MIN, &statusArray[33], 0, CURRENT_SENSOR_MSG}, + (fault_attributes_t){false, false, MAX_CELLV_O5V_PRIORITY, 0, 0, MAX_CELLV_O5V_MAX, MAX_CELLV_O5V_MIN, &statusArray[34], 0, MAX_CELLV_O5V_MSG}, + (fault_attributes_t){false, false, CELL_ASIC_PRIORITY, 0, 0, CELL_ASIC_MAX, CELL_ASIC_MIN, &statusArray[35], 0, CELL_ASIC_MSG}, + (fault_attributes_t){false, false, WEAK_PACK_PRIORITY, 0, 0, WEAK_PACK_MAX, WEAK_PACK_MIN, &statusArray[36], 0, WEAK_PACK_MSG}, + (fault_attributes_t){false, false, FAN_MONITOR_PRIORITY, 0, 0, FAN_MONITOR_MAX, FAN_MONITOR_MIN, &statusArray[37], 0, FAN_MONITOR_MSG}, + (fault_attributes_t){false, false, THERMISTOR_PRIORITY, 0, 0, THERMISTOR_MAX, THERMISTOR_MIN, &statusArray[38], 0, THERMISTOR_MSG}, + (fault_attributes_t){false, false, EXTERNAL_COMMS_PRIORITY, 0, 0, EXTERNAL_COMMS_MAX, EXTERNAL_COMMS_MIN, &statusArray[39], 0, EXTERNAL_COMMS_MSG}, + (fault_attributes_t){false, false, REDUNDANT_PSU_PRIORITY, 0, 0, REDUNDANT_PSU_MAX, REDUNDANT_PSU_MIN, &statusArray[40], 0, REDUNDANT_PSU_MSG}, + (fault_attributes_t){false, false, HV_ISOLATION_PRIORITY, 0, 0, HV_ISOLATION_MAX, HV_ISOLATION_MIN, &statusArray[41], 0, HV_ISOLATION_MSG}, + (fault_attributes_t){false, false, INPUT_PSU_PRIORITY, 0, 0, INPUT_PSU_MAX, INPUT_PSU_MIN, &statusArray[42], 0, INPUT_PSU_MSG}, + (fault_attributes_t){false, false, CHARGE_LIMIT_ENFORCE_PRIORITY, 0, 0, CHARGE_LIMIT_ENFORCE_MAX, CHARGE_LIMIT_ENFORCE_MIN, &statusArray[43], 0, CHARGE_LIMIT_ENFORCE_MSG}, + (fault_attributes_t){false, false, PACK_TEMP_PRIORITY, 0, 0, PACK_TEMP_MAX, PACK_TEMP_MIN, &statusArray[44], 0, PACK_TEMP_MSG}, + (fault_attributes_t){false, false, PACK_TEMP_EXCEEDED_PRIORITY, 0, 0, PACK_TEMP_EXCEEDED_MAX, PACK_TEMP_EXCEEDED_MIN, &statusArray[45], 0, PACK_TEMP_EXCEEDED_MSG}, + (fault_attributes_t){false, false, MIN_PACK_TEMP_PRIORITY, 0, 0, MIN_PACK_TEMP_MAX, MIN_PACK_TEMP_MIN, &statusArray[46], 0, MIN_PACK_TEMP_MSG}, + (fault_attributes_t){false, false, IMD_PRIORITY, 0, 0, IMD_MAX, IMD_MIN, &statusArray[47], 0, IMD_MSG}, + (fault_attributes_t){false, false, TV_OFFLINE_PRIORITY, 0, 0, TV_OFFLINE_MAX, TV_OFFLINE_MIN, &statusArray[48], 0, TV_OFFLINE_MSG}, + (fault_attributes_t){false, false, TEST_FAULT_1_PRIORITY, 0, 0, TEST_FAULT_1_MAX, TEST_FAULT_1_MIN, &statusArray[49], 0, TEST_FAULT_1_MSG}, + (fault_attributes_t){false, false, TEST_FAULT_2_PRIORITY, 0, 0, TEST_FAULT_2_MAX, TEST_FAULT_2_MIN, &statusArray[50], 0, TEST_FAULT_2_MSG}, + (fault_attributes_t){false, false, TEST_FAULT_3_PRIORITY, 0, 0, TEST_FAULT_3_MAX, TEST_FAULT_3_MIN, &statusArray[51], 0, TEST_FAULT_3_MSG}, + (fault_attributes_t){false, false, TEST_FAULT_4_PRIORITY, 0, 0, TEST_FAULT_4_MAX, TEST_FAULT_4_MIN, &statusArray[52], 0, TEST_FAULT_4_MSG}, }; //END AUTO FAULT INFO ARRAY DEFS diff --git a/common/faults/faults.h b/common/faults/faults.h index 63cd9a44..2ea008b6 100644 --- a/common/faults/faults.h +++ b/common/faults/faults.h @@ -20,69 +20,71 @@ #define MAX_MSG_SIZE 75 //BEGIN AUTO TOTAL DEFS +#define TOTAL_PDU_FAULTS 1 #define TOTAL_MAIN_MODULE_FAULTS 9 #define TOTAL_DRIVELINE_FRONT_FAULTS 4 #define TOTAL_DASHBOARD_FAULTS 6 #define TOTAL_PRECHARGE_FAULTS 28 #define TOTAL_TV_OLD_FAULTS 1 #define TOTAL_TEST_FAULTS 4 -#define TOTAL_MCU_NUM 6 -#define TOTAL_NUM_FAULTS 52 +#define TOTAL_MCU_NUM 7 +#define TOTAL_NUM_FAULTS 53 //END AUTO TOTAL DEFS //BEGIN AUTO ID DEFS -#define ID_PCHG_IMPLAUS_FAULT 0x0 -#define ID_RTD_EXIT_FAULT 0x1 -#define ID_LEFT_MC_CONN_FAULT 0x2 -#define ID_RIGHT_MC_CONN_FAULT 0x3 -#define ID_MCU_TEMP_HIGH_FAULT 0x4 -#define ID_LV_BAT_LOW_FAULT 0x5 -#define ID_LV_BAT_VERY_LOW_FAULT 0x6 -#define ID_LV_BAT_BMS_FAULT 0x7 -#define ID_DRIVE_FLOW_FAULT 0x8 -#define ID_MOT_FRONT_OT_FAULT 0x1009 -#define ID_WLSPD_L_FAULT 0x100a -#define ID_WLSPD_R_FAULT 0x100b -#define ID_DRIVELINE_COMM_FAULT 0x100c -#define ID_APPS_WIRING_T1_FAULT 0x200d -#define ID_APPS_WIRING_T2_FAULT 0x200e -#define ID_BSE_FAULT 0x200f -#define ID_BSPD_FAULT 0x2010 -#define ID_IMPLAUS_DETECTED_FAULT 0x2011 -#define ID_APPS_BRAKE_FAULT 0x2012 -#define ID_DISCHARGE_LIMIT_ENFORCE_FAULT 0x3013 -#define ID_CHARGER_SAFETY_RELAY_FAULT 0x3014 -#define ID_INTERNAL_HARDWARE_FAULT 0x3015 -#define ID_HEATSINK_THERMISTOR_FAULT 0x3016 -#define ID_SOFTWARE_FAULT 0x3017 -#define ID_MAX_CELLV_HIGH_FAULT 0x3018 -#define ID_MIN_CELLV_LOW_FAULT 0x3019 -#define ID_PACK_OVERHEAT_ORION_FAULT 0x301a -#define ID_INTERNAL_COMMS_FAULT 0x301b -#define ID_CELL_BALANCING_FOFF_FAULT 0x301c -#define ID_WEAK_CELL_FAULT 0x301d -#define ID_LOW_CELLV_FAULT 0x301e -#define ID_OPEN_WIRE_FAULT 0x301f -#define ID_CURRENT_SENSOR_FAULT 0x3020 -#define ID_MAX_CELLV_O5V_FAULT 0x3021 -#define ID_CELL_ASIC_FAULT 0x3022 -#define ID_WEAK_PACK_FAULT 0x3023 -#define ID_FAN_MONITOR_FAULT 0x3024 -#define ID_THERMISTOR_FAULT 0x3025 -#define ID_EXTERNAL_COMMS_FAULT 0x3026 -#define ID_REDUNDANT_PSU_FAULT 0x3027 -#define ID_HV_ISOLATION_FAULT 0x3028 -#define ID_INPUT_PSU_FAULT 0x3029 -#define ID_CHARGE_LIMIT_ENFORCE_FAULT 0x302a -#define ID_PACK_TEMP_FAULT 0x302b -#define ID_PACK_TEMP_EXCEEDED_FAULT 0x302c -#define ID_MIN_PACK_TEMP_FAULT 0x302d -#define ID_IMD_FAULT 0x302e -#define ID_TV_OFFLINE_FAULT 0x402f -#define ID_TEST_FAULT_1_FAULT 0x5030 -#define ID_TEST_FAULT_2_FAULT 0x5031 -#define ID_TEST_FAULT_3_FAULT 0x5032 -#define ID_TEST_FAULT_4_FAULT 0x5033 +#define ID_PDU_MCU_TEMP_HIGH_FAULT 0x0 +#define ID_PCHG_IMPLAUS_FAULT 0x1001 +#define ID_RTD_EXIT_FAULT 0x1002 +#define ID_LEFT_MC_CONN_FAULT 0x1003 +#define ID_RIGHT_MC_CONN_FAULT 0x1004 +#define ID_MCU_TEMP_HIGH_FAULT 0x1005 +#define ID_LV_BAT_LOW_FAULT 0x1006 +#define ID_LV_BAT_VERY_LOW_FAULT 0x1007 +#define ID_LV_BAT_BMS_FAULT 0x1008 +#define ID_DRIVE_FLOW_FAULT 0x1009 +#define ID_MOT_FRONT_OT_FAULT 0x200a +#define ID_WLSPD_L_FAULT 0x200b +#define ID_WLSPD_R_FAULT 0x200c +#define ID_DRIVELINE_COMM_FAULT 0x200d +#define ID_APPS_WIRING_T1_FAULT 0x300e +#define ID_APPS_WIRING_T2_FAULT 0x300f +#define ID_BSE_FAULT 0x3010 +#define ID_BSPD_FAULT 0x3011 +#define ID_IMPLAUS_DETECTED_FAULT 0x3012 +#define ID_APPS_BRAKE_FAULT 0x3013 +#define ID_DISCHARGE_LIMIT_ENFORCE_FAULT 0x4014 +#define ID_CHARGER_SAFETY_RELAY_FAULT 0x4015 +#define ID_INTERNAL_HARDWARE_FAULT 0x4016 +#define ID_HEATSINK_THERMISTOR_FAULT 0x4017 +#define ID_SOFTWARE_FAULT 0x4018 +#define ID_MAX_CELLV_HIGH_FAULT 0x4019 +#define ID_MIN_CELLV_LOW_FAULT 0x401a +#define ID_PACK_OVERHEAT_ORION_FAULT 0x401b +#define ID_INTERNAL_COMMS_FAULT 0x401c +#define ID_CELL_BALANCING_FOFF_FAULT 0x401d +#define ID_WEAK_CELL_FAULT 0x401e +#define ID_LOW_CELLV_FAULT 0x401f +#define ID_OPEN_WIRE_FAULT 0x4020 +#define ID_CURRENT_SENSOR_FAULT 0x4021 +#define ID_MAX_CELLV_O5V_FAULT 0x4022 +#define ID_CELL_ASIC_FAULT 0x4023 +#define ID_WEAK_PACK_FAULT 0x4024 +#define ID_FAN_MONITOR_FAULT 0x4025 +#define ID_THERMISTOR_FAULT 0x4026 +#define ID_EXTERNAL_COMMS_FAULT 0x4027 +#define ID_REDUNDANT_PSU_FAULT 0x4028 +#define ID_HV_ISOLATION_FAULT 0x4029 +#define ID_INPUT_PSU_FAULT 0x402a +#define ID_CHARGE_LIMIT_ENFORCE_FAULT 0x402b +#define ID_PACK_TEMP_FAULT 0x402c +#define ID_PACK_TEMP_EXCEEDED_FAULT 0x402d +#define ID_MIN_PACK_TEMP_FAULT 0x402e +#define ID_IMD_FAULT 0x402f +#define ID_TV_OFFLINE_FAULT 0x5030 +#define ID_TEST_FAULT_1_FAULT 0x6031 +#define ID_TEST_FAULT_2_FAULT 0x6032 +#define ID_TEST_FAULT_3_FAULT 0x6033 +#define ID_TEST_FAULT_4_FAULT 0x6034 //END AUTO ID DEFS //Macro defs for accessing aspects of id @@ -94,6 +96,7 @@ //CRITICAL: Car exits ready2drive, but LV + HV systems still active //FATAL: The Car SDC is activated //BEGIN AUTO PRIORITY DEFS +#define PDU_MCU_TEMP_HIGH_PRIORITY 0 #define PCHG_IMPLAUS_PRIORITY 1 #define RTD_EXIT_PRIORITY 0 #define LEFT_MC_CONN_PRIORITY 1 @@ -149,6 +152,7 @@ //END AUTO PRIORITY DEFS //BEGIN AUTO MAX DEFS +#define PDU_MCU_TEMP_HIGH_MAX 50 #define PCHG_IMPLAUS_MAX 1 #define RTD_EXIT_MAX 1 #define LEFT_MC_CONN_MAX 1 @@ -204,6 +208,7 @@ //END AUTO MAX DEFS //BEGIN AUTO MIN DEFS +#define PDU_MCU_TEMP_HIGH_MIN 0 #define PCHG_IMPLAUS_MIN 0 #define RTD_EXIT_MIN 0 #define LEFT_MC_CONN_MIN 0 @@ -259,6 +264,7 @@ //END AUTO MIN DEFS //BEGIN AUTO LATCH DEFS +#define PDU_MCU_TEMP_HIGH_LATCH_TIME 1000 #define PCHG_IMPLAUS_LATCH_TIME 50 #define RTD_EXIT_LATCH_TIME 100 #define LEFT_MC_CONN_LATCH_TIME 3000 @@ -314,6 +320,7 @@ //END AUTO LATCH DEFS //BEGIN AUTO UNLATCH DEFS +#define PDU_MCU_TEMP_HIGH_UNLATCH_TIME 2000 #define PCHG_IMPLAUS_UNLATCH_TIME 1000 #define RTD_EXIT_UNLATCH_TIME 1000 #define LEFT_MC_CONN_UNLATCH_TIME 1000 @@ -369,6 +376,7 @@ //END AUTO UNLATCH DEFS //BEGIN AUTO SCREENMSG DEFS +#define PDU_MCU_TEMP_HIGH_MSG "HIGH PDU MCU TEMP\0" #define PCHG_IMPLAUS_MSG "Precharge Implausibility\0" #define RTD_EXIT_MSG "HV not detected, idling\0" #define LEFT_MC_CONN_MSG "LEFT MC CONN FAIL\0" diff --git a/common/phal_F4_F7/can/can.c b/common/phal_F4_F7/can/can.c new file mode 100644 index 00000000..1b5da33a --- /dev/null +++ b/common/phal_F4_F7/can/can.c @@ -0,0 +1,186 @@ +/** + * @file hal_can_f4.c + * @author Chris McGalliard - Port of L4 HAL by Adam Busch (busch8@purdue.edu) + * @brief Basic CAN Peripheral HAL library for setting up CAN peripheral and sending messages + * @version 0.1 + * @date 2023-09-18 + * + * @copyright Copyright (c) 2021 + * + */ +#include "common/phal_F4_F7/can/can.h" + +extern uint32_t APB1ClockRateHz; + +bool PHAL_initCAN(CAN_TypeDef* bus, bool test_mode) +{ + uint32_t timeout = 0; + + // Enable CAN Clock + if (bus == CAN1) + { + RCC->APB1ENR |= RCC_APB1ENR_CAN1EN; + } + #ifdef CAN2 + else if (bus == CAN2) + { + RCC->APB1ENR |= RCC_APB1ENR_CAN2EN; + } + #endif /* CAN2 */ + else + { + return false; + } + + // Leave SLEEP state + bus->MCR &= ~CAN_MCR_SLEEP; + // Enter INIT state + bus->MCR |= CAN_MCR_INRQ; + while((bus->MSR & CAN_MSR_SLAK) && ++timeout < PHAL_CAN_INIT_TIMEOUT) + ; + if (timeout == PHAL_CAN_INIT_TIMEOUT) + return false; + timeout = 0; + + bus->MCR |= CAN_MCR_INRQ; + while(!(bus->MSR & CAN_MSR_INAK) && ++timeout < PHAL_CAN_INIT_TIMEOUT) + ; + if (timeout == PHAL_CAN_INIT_TIMEOUT) + return false; + timeout = 0; + + // Bit timing recovered from http://www.bittiming.can-wiki.info/ + switch (APB1ClockRateHz) + { + case 16000000: + bus->BTR = PHAL_CAN_16MHz_500k; + break; + case 20000000: + bus->BTR = PHAL_CAN_20MHz_500k; + break; + case 40000000: + bus->BTR = PHAL_CAN_40MHz_500k; + break; + case 80000000: + bus->BTR = PHAL_CAN_80MHz_500k; + break; + default: + return false; + } + // Keep the bus active + bus->MCR |= CAN_MCR_ABOM; + + // Loopback mode in testing mode + if (test_mode) + { + bus->BTR |= CAN_BTR_LBKM; + } + + // Setup filters for all IDs + bus->FMR |= CAN_FMR_FINIT; // Enter init mode for filter banks + bus->FM1R &= ~(CAN_FM1R_FBM0_Msk); // Set bank 0 to mask mode + bus->FS1R &= ~(1 << CAN_FS1R_FSC0_Pos); // Set bank 0 to 16bit mode + bus->FA1R |= (1 << CAN_FA1R_FACT0_Pos); // Activate bank 0 + bus->sFilterRegister[0].FR1 = 0; // Set mask to 0 + bus->sFilterRegister[0].FR2 = 0; + bus->FMR &= ~CAN_FMR_FINIT; // Enable Filters + + // Enable FIFO0/1 RX message pending interrupt + bus->IER |= CAN_IER_FMPIE0; + bus->IER |= CAN_IER_FMPIE1; + + // Enter NORMAL mode + bus->MCR &= ~CAN_MCR_INRQ; + while((bus->MSR & CAN_MSR_INAK) && ++timeout < PHAL_CAN_INIT_TIMEOUT) + ; + + return timeout != PHAL_CAN_INIT_TIMEOUT; +} + +bool PHAL_deinitCAN(CAN_TypeDef* bus) +{ + if (bus == CAN1) + { + RCC->APB1RSTR |= RCC_APB1RSTR_CAN1RST; + } + #ifdef CAN2 + else if(bus == CAN2) + { + RCC->APB1RSTR |= RCC_APB1RSTR_CAN2RST; + } + #endif /* CAN2 */ + else return false; + return true; +} + +bool PHAL_txCANMessage(CanMsgTypeDef_t* msg) +{ + uint8_t txMbox = 0; + uint32_t timeout = 0; + uint32_t txOkay = 0; + + if (msg->Bus->TSR & CAN_TSR_TME0) + { + txMbox = 0; + txOkay = CAN_TSR_TXOK0; + } + else if (msg->Bus->TSR & CAN_TSR_TME1) + { + txMbox = 1; + txOkay = CAN_TSR_TXOK1; + } + else if (msg->Bus->TSR & CAN_TSR_TME2) + { + txMbox = 2; + txOkay = CAN_TSR_TXOK2; + } + else + return false; // Unable to find Mailbox + + if (msg->IDE == 0) + { + msg->Bus->sTxMailBox[txMbox].TIR = (msg->StdId << CAN_TI0R_STID_Pos); // Standard ID + } + else + { + msg->Bus->sTxMailBox[txMbox].TIR = (msg->ExtId << CAN_TI0R_EXID_Pos) | 4; // Extended ID + } + msg->Bus->sTxMailBox[txMbox].TDTR = (msg->DLC << CAN_TDT0R_DLC_Pos); // Data Length + msg->Bus->sTxMailBox[txMbox].TDLR = ((uint32_t) msg->Data[3] << 24) | + ((uint32_t) msg->Data[2] << 16) | + ((uint32_t) msg->Data[1] << 8) | + ((uint32_t) msg->Data[0]); + msg->Bus->sTxMailBox[txMbox].TDHR = ((uint32_t) msg->Data[7] << 24) | + ((uint32_t) msg->Data[6] << 16) | + ((uint32_t) msg->Data[5] << 8) | + ((uint32_t) msg->Data[4]); + + msg->Bus->sTxMailBox[txMbox].TIR |= (0b1 << CAN_TI0R_TXRQ_Pos); // Request TX + + while(!(msg->Bus->TSR & txOkay) && ++timeout < PHAL_CAN_TX_TIMEOUT) // Wait for message to be sent within specified timeout + ; + + return timeout != PHAL_CAN_TX_TIMEOUT; +} + +void __attribute__((weak)) CAN1_RX0_IRQHandler() +{ + // Implement for RX Mailbox 0 Handler +} + +void __attribute__((weak)) CAN1_RX1_IRQHandler() +{ + // Implement for RX Mailbox 1 Handler +} + +#ifdef STM32L496xx +void __attribute__((weak)) CAN2_RX0_IRQHandler() +{ + // Implement for RX Mailbox 0 Handler +} + +void __attribute__((weak)) CAN2_RX1_IRQHandler() +{ + // Implement for RX Mailbox 1 Handler +} +#endif \ No newline at end of file diff --git a/common/phal_F4_F7/can/can.h b/common/phal_F4_F7/can/can.h new file mode 100644 index 00000000..891ea074 --- /dev/null +++ b/common/phal_F4_F7/can/can.h @@ -0,0 +1,69 @@ +/** + * @file can.h + * @author Adam Busch (busch8@purdue.edu) + * @brief + * @version 0.1 + * @date 2021-03-20 + * + * @copyright Copyright (c) 2021 + * + */ + +#ifndef _PHAL_CAN_H +#define _PHAL_CAN_H + +#if defined(STM32F407xx) +#include "stm32f4xx.h" +#include "system_stm32f4xx.h" +#elif defined(STM32F732xx) +#include "stm32f7xx.h" +#include "system_stm32f7xx.h" +#else +#error "Please define a MCU arch" +#endif + +#include + +#define PHAL_CAN_TX_TIMEOUT (5000U) +#define PHAL_CAN_INIT_TIMEOUT (5000U) + +// Bit timing recovered from http://www.bittiming.can-wiki.info/ +#define PHAL_CAN_16MHz_500k (0x001c0001) +#define PHAL_CAN_20MHz_500k (0x00050004) +#define PHAL_CAN_40MHz_500k (0x001c0004) +#define PHAL_CAN_80MHz_500k (0x001c0009) + +typedef struct +{ + CAN_TypeDef* Bus; /*!< Specifies the bus. */ + uint16_t StdId; /*!< Specifies the standard identifier. */ + uint32_t ExtId; /*!< Specifies the extended identifier. */ + uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. */ + uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. */ + uint8_t Data[8]; /*!< Contains the data to be transmitted. */ +} CanMsgTypeDef_t; + +/** + * @brief Initilize CAN peripheral to 500k. + * + * @param test_mode Initilize CAN peripheral for self test mode + * + * @return true Peripheral sucessfully initalized + * @return false Peripheral stalled during initilization + */ +bool PHAL_initCAN(CAN_TypeDef* bus, bool test_mode); + +bool PHAL_deinitCAN(CAN_TypeDef* bus); + +/** + * @brief Find an empty TX mailbox and transmit a CAN message if one is found. + * Function will block until sucessful transmission of message until a specified timeout. + * + * @param can CAN peripheral to transmit with + * @param msgId Message ID + * @return true Sucessful TX of message. + * @return false Unable to find empty message or transmit took too long. + */ +bool PHAL_txCANMessage(CanMsgTypeDef_t* msg); + +#endif // _PHAL_CAN_H \ No newline at end of file diff --git a/common/phal_F4_F7/spi/spi.c b/common/phal_F4_F7/spi/spi.c index e301185c..834cddfd 100644 --- a/common/phal_F4_F7/spi/spi.c +++ b/common/phal_F4_F7/spi/spi.c @@ -166,7 +166,7 @@ bool PHAL_SPI_transfer(SPI_InitConfig_t *spi, const uint8_t *out_data, const uin RX Side interrupts disabled, since the same data lengths are sent to both TX and RX */ // Cannot use DMA without knowing essential configuration info - if (spi->tx_dma_cfg == 0 || spi->rx_dma_cfg == 0) + if (spi->tx_dma_cfg == 0) { return false; } @@ -198,21 +198,24 @@ bool PHAL_SPI_transfer(SPI_InitConfig_t *spi, const uint8_t *out_data, const uin //Configure DMA receive Msg - spi->periph->CR2 |= SPI_CR2_RXDMAEN; - if (!in_data) + if (spi->rx_dma_cfg) { - // No data to receive, so configure DMA to disregard any received messages - spi->rx_dma_cfg->stream->CR &= ~DMA_SxCR_MINC; - PHAL_DMA_setMemAddress(spi->rx_dma_cfg, (uint32_t)&trash_can); - } - else - { - PHAL_DMA_setMemAddress(spi->rx_dma_cfg, (uint32_t)in_data); - } - PHAL_DMA_setTxferLength(spi->rx_dma_cfg, data_len); + spi->periph->CR2 |= SPI_CR2_RXDMAEN; + if (!in_data) + { + // No data to receive, so configure DMA to disregard any received messages + spi->rx_dma_cfg->stream->CR &= ~DMA_SxCR_MINC; + PHAL_DMA_setMemAddress(spi->rx_dma_cfg, (uint32_t)&trash_can); + } + else + { + PHAL_DMA_setMemAddress(spi->rx_dma_cfg, (uint32_t)in_data); + } + PHAL_DMA_setTxferLength(spi->rx_dma_cfg, data_len); - // We must clear interrupt flags before enabling DMA - PHAL_reEnable(spi->rx_dma_cfg); + // We must clear interrupt flags before enabling DMA + PHAL_reEnable(spi->rx_dma_cfg); + } // Enable the DMA IRQ - copy + paste enabling selected SPI peripheral's TX DMA Stream ISR if (spi->periph == SPI1) diff --git a/source/dashboard/can/can_parse.c b/source/dashboard/can/can_parse.c index 286f28b0..3fd76c45 100644 --- a/source/dashboard/can/can_parse.c +++ b/source/dashboard/can/can_parse.c @@ -189,6 +189,11 @@ void canRxUpdate() can_data.dashboard_bl_cmd.data = msg_data_a->dashboard_bl_cmd.data; dashboard_bl_cmd_CALLBACK(msg_data_a); break; + case ID_FAULT_SYNC_PDU: + can_data.fault_sync_pdu.idx = msg_data_a->fault_sync_pdu.idx; + can_data.fault_sync_pdu.latched = msg_data_a->fault_sync_pdu.latched; + handleCallbacks(msg_data_a->fault_sync_main_module.idx, msg_data_a->fault_sync_main_module.latched); + break; case ID_FAULT_SYNC_MAIN_MODULE: can_data.fault_sync_main_module.idx = msg_data_a->fault_sync_main_module.idx; can_data.fault_sync_main_module.latched = msg_data_a->fault_sync_main_module.latched; @@ -316,18 +321,19 @@ bool initCANFilter() CAN1->sFilterRegister[6].FR2 = (ID_GEARBOX << 3) | 4; CAN1->FA1R |= (1 << 7); // configure bank 7 CAN1->sFilterRegister[7].FR1 = (ID_DASHBOARD_BL_CMD << 3) | 4; - CAN1->sFilterRegister[7].FR2 = (ID_FAULT_SYNC_MAIN_MODULE << 3) | 4; + CAN1->sFilterRegister[7].FR2 = (ID_FAULT_SYNC_PDU << 3) | 4; CAN1->FA1R |= (1 << 8); // configure bank 8 - CAN1->sFilterRegister[8].FR1 = (ID_FAULT_SYNC_DRIVELINE << 3) | 4; - CAN1->sFilterRegister[8].FR2 = (ID_FAULT_SYNC_PRECHARGE << 3) | 4; + CAN1->sFilterRegister[8].FR1 = (ID_FAULT_SYNC_MAIN_MODULE << 3) | 4; + CAN1->sFilterRegister[8].FR2 = (ID_FAULT_SYNC_DRIVELINE << 3) | 4; CAN1->FA1R |= (1 << 9); // configure bank 9 CAN1->sFilterRegister[9].FR1 = (ID_FAULT_SYNC_TORQUE_VECTOR_FPGA << 3) | 4; CAN1->sFilterRegister[9].FR2 = (ID_FAULT_SYNC_TEST_NODE << 3) | 4; CAN1->FA1R |= (1 << 10); // configure bank 10 - CAN1->sFilterRegister[10].FR1 = (ID_SET_FAULT << 3) | 4; - CAN1->sFilterRegister[10].FR2 = (ID_RETURN_FAULT_CONTROL << 3) | 4; + CAN1->sFilterRegister[10].FR1 = (ID_FAULT_SYNC_TEST_NODE << 3) | 4; + CAN1->sFilterRegister[10].FR2 = (ID_SET_FAULT << 3) | 4; CAN1->FA1R |= (1 << 11); // configure bank 11 - CAN1->sFilterRegister[11].FR1 = (ID_DAQ_COMMAND_DASHBOARD << 3) | 4; + CAN1->sFilterRegister[11].FR1 = (ID_RETURN_FAULT_CONTROL << 3) | 4; + CAN1->sFilterRegister[11].FR2 = (ID_DAQ_COMMAND_DASHBOARD << 3) | 4; /* END AUTO FILTER */ CAN1->FMR &= ~CAN_FMR_FINIT; // Enable Filters (exit filter init mode) diff --git a/source/dashboard/can/can_parse.h b/source/dashboard/can/can_parse.h index c263b357..6a95b948 100644 --- a/source/dashboard/can/can_parse.h +++ b/source/dashboard/can/can_parse.h @@ -43,6 +43,7 @@ #define ID_COOLANT_OUT 0x40008c1 #define ID_GEARBOX 0x10000901 #define ID_DASHBOARD_BL_CMD 0x409c47e +#define ID_FAULT_SYNC_PDU 0x8cb5f #define ID_FAULT_SYNC_MAIN_MODULE 0x8ca01 #define ID_FAULT_SYNC_DRIVELINE 0x8ca83 #define ID_FAULT_SYNC_PRECHARGE 0x8cac4 @@ -78,6 +79,7 @@ #define DLC_COOLANT_OUT 3 #define DLC_GEARBOX 2 #define DLC_DASHBOARD_BL_CMD 5 +#define DLC_FAULT_SYNC_PDU 3 #define DLC_FAULT_SYNC_MAIN_MODULE 3 #define DLC_FAULT_SYNC_DRIVELINE 3 #define DLC_FAULT_SYNC_PRECHARGE 3 @@ -192,7 +194,7 @@ typedef enum { // Message Raw Structures /* BEGIN AUTO MESSAGE STRUCTURE */ -typedef union { +typedef union { struct { uint64_t throttle: 12; uint64_t throttle_right: 12; @@ -355,6 +357,10 @@ typedef union { uint64_t cmd: 8; uint64_t data: 32; } dashboard_bl_cmd; + struct { + uint64_t idx: 16; + uint64_t latched: 1; + } fault_sync_pdu; struct { uint64_t idx: 16; uint64_t latched: 1; @@ -545,6 +551,10 @@ typedef struct { uint8_t cmd; uint32_t data; } dashboard_bl_cmd; + struct { + uint16_t idx; + uint8_t latched; + } fault_sync_pdu; struct { uint16_t idx; uint8_t latched; diff --git a/source/driveline/can/can_parse.c b/source/driveline/can/can_parse.c index 0be5487e..76def9c6 100644 --- a/source/driveline/can/can_parse.c +++ b/source/driveline/can/can_parse.c @@ -4,9 +4,9 @@ * @brief Parsing of CAN messages using auto-generated structures with bit-fields * @version 0.1 * @date 2021-09-15 - * + * * @copyright Copyright (c) 2021 - * + * */ #include "can_parse.h" @@ -104,6 +104,11 @@ void canRxUpdate() can_data.driveline_rear_bl_cmd.data = msg_data_a->driveline_rear_bl_cmd.data; driveline_rear_bl_cmd_CALLBACK(msg_data_a); break; + case ID_FAULT_SYNC_PDU: + can_data.fault_sync_pdu.idx = msg_data_a->fault_sync_pdu.idx; + can_data.fault_sync_pdu.latched = msg_data_a->fault_sync_pdu.latched; + handleCallbacks(msg_data_a->fault_sync_main_module.idx, msg_data_a->fault_sync_main_module.latched); + break; case ID_FAULT_SYNC_MAIN_MODULE: can_data.fault_sync_main_module.idx = msg_data_a->fault_sync_main_module.idx; can_data.fault_sync_main_module.latched = msg_data_a->fault_sync_main_module.latched; @@ -197,17 +202,19 @@ bool initCANFilter() CAN1->sFilterRegister[3].FR1 = (ID_DRIVELINE_FRONT_BL_CMD << 3) | 4; CAN1->sFilterRegister[3].FR2 = (ID_DRIVELINE_REAR_BL_CMD << 3) | 4; CAN1->FA1R |= (1 << 4); // configure bank 4 - CAN1->sFilterRegister[4].FR1 = (ID_FAULT_SYNC_MAIN_MODULE << 3) | 4; - CAN1->sFilterRegister[4].FR2 = (ID_FAULT_SYNC_DASHBOARD << 3) | 4; + CAN1->sFilterRegister[4].FR1 = (ID_FAULT_SYNC_PDU << 3) | 4; + CAN1->sFilterRegister[4].FR2 = (ID_FAULT_SYNC_MAIN_MODULE << 3) | 4; CAN1->FA1R |= (1 << 5); // configure bank 5 CAN1->sFilterRegister[5].FR1 = (ID_FAULT_SYNC_PRECHARGE << 3) | 4; CAN1->sFilterRegister[5].FR2 = (ID_FAULT_SYNC_TORQUE_VECTOR_FPGA << 3) | 4; CAN1->FA1R |= (1 << 6); // configure bank 6 - CAN1->sFilterRegister[6].FR1 = (ID_FAULT_SYNC_TEST_NODE << 3) | 4; - CAN1->sFilterRegister[6].FR2 = (ID_SET_FAULT << 3) | 4; + CAN1->sFilterRegister[6].FR1 = (ID_FAULT_SYNC_TORQUE_VECTOR_FPGA << 3) | 4; + CAN1->sFilterRegister[6].FR2 = (ID_FAULT_SYNC_TEST_NODE << 3) | 4; CAN1->FA1R |= (1 << 7); // configure bank 7 - CAN1->sFilterRegister[7].FR1 = (ID_RETURN_FAULT_CONTROL << 3) | 4; - CAN1->sFilterRegister[7].FR2 = (ID_DAQ_COMMAND_DRIVELINE << 3) | 4; + CAN1->sFilterRegister[7].FR1 = (ID_SET_FAULT << 3) | 4; + CAN1->sFilterRegister[7].FR2 = (ID_RETURN_FAULT_CONTROL << 3) | 4; + CAN1->FA1R |= (1 << 8); // configure bank 8 + CAN1->sFilterRegister[8].FR1 = (ID_DAQ_COMMAND_DRIVELINE << 3) | 4; /* END AUTO FILTER */ CAN1->FMR &= ~CAN_FMR_FINIT; // Enable Filters (exit filter init mode) diff --git a/source/driveline/can/can_parse.h b/source/driveline/can/can_parse.h index 8c69c161..e45237b0 100644 --- a/source/driveline/can/can_parse.h +++ b/source/driveline/can/can_parse.h @@ -4,9 +4,9 @@ * @brief Parsing of CAN messages using auto-generated structures with bit-fields * @version 0.1 * @date 2021-09-15 - * + * * @copyright Copyright (c) 2021 - * + * */ #ifndef _CAN_PARSE_H_ #define _CAN_PARSE_H_ @@ -44,6 +44,7 @@ typedef union { #define ID_ORION_CURRENTS_VOLTS 0x140006f8 #define ID_DRIVELINE_FRONT_BL_CMD 0x409c4fe #define ID_DRIVELINE_REAR_BL_CMD 0x409c53e +#define ID_FAULT_SYNC_PDU 0x8cb5f #define ID_FAULT_SYNC_MAIN_MODULE 0x8ca01 #define ID_FAULT_SYNC_DASHBOARD 0x8cb05 #define ID_FAULT_SYNC_PRECHARGE 0x8cac4 @@ -70,6 +71,7 @@ typedef union { #define DLC_ORION_CURRENTS_VOLTS 4 #define DLC_DRIVELINE_FRONT_BL_CMD 5 #define DLC_DRIVELINE_REAR_BL_CMD 5 +#define DLC_FAULT_SYNC_PDU 3 #define DLC_FAULT_SYNC_MAIN_MODULE 3 #define DLC_FAULT_SYNC_DASHBOARD 3 #define DLC_FAULT_SYNC_PRECHARGE 3 @@ -226,7 +228,7 @@ typedef enum { // Message Raw Structures /* BEGIN AUTO MESSAGE STRUCTURE */ -typedef union { +typedef union { struct { uint64_t front_left_motor: 8; uint64_t front_left_motor_link: 8; @@ -312,6 +314,10 @@ typedef union { uint64_t cmd: 8; uint64_t data: 32; } driveline_rear_bl_cmd; + struct { + uint64_t idx: 16; + uint64_t latched: 1; + } fault_sync_pdu; struct { uint64_t idx: 16; uint64_t latched: 1; @@ -417,6 +423,10 @@ typedef struct { uint8_t cmd; uint32_t data; } driveline_rear_bl_cmd; + struct { + uint16_t idx; + uint8_t latched; + } fault_sync_pdu; struct { uint16_t idx; uint8_t latched; @@ -467,7 +477,7 @@ extern void send_fault(uint16_t id, bool latched); /** * @brief Setup queue and message filtering - * + * * @param q_rx_can RX buffer of CAN messages */ void initCANParse(q_handle_t* q_rx_can_a); @@ -481,7 +491,7 @@ void canRxUpdate(); /** * @brief Process any rx message callbacks from the CAN Rx IRQ - * + * * @param rx rx data from message just recieved */ void canProcessRxIRQs(CanMsgTypeDef_t* rx); diff --git a/source/l4_testing/can/can_parse.c b/source/l4_testing/can/can_parse.c index 5c7ab4ca..a22789db 100644 --- a/source/l4_testing/can/can_parse.c +++ b/source/l4_testing/can/can_parse.c @@ -4,9 +4,9 @@ * @brief Parsing of CAN messages using auto-generated structures with bit-fields * @version 0.1 * @date 2021-09-15 - * + * * @copyright Copyright (c) 2021 - * + * */ #include "can_parse.h" @@ -63,6 +63,11 @@ void canRxUpdate(void) can_data.l4_testing_bl_cmd.data = msg_data_a->l4_testing_bl_cmd.data; l4_testing_bl_cmd_CALLBACK(msg_data_a); break; + case ID_FAULT_SYNC_PDU: + can_data.fault_sync_pdu.idx = msg_data_a->fault_sync_pdu.idx; + can_data.fault_sync_pdu.latched = msg_data_a->fault_sync_pdu.latched; + handleCallbacks(msg_data_a->fault_sync_main_module.idx, msg_data_a->fault_sync_main_module.latched); + break; case ID_FAULT_SYNC_MAIN_MODULE: can_data.fault_sync_main_module.idx = msg_data_a->fault_sync_main_module.idx; can_data.fault_sync_main_module.latched = msg_data_a->fault_sync_main_module.latched; @@ -142,18 +147,19 @@ bool initCANFilter() CAN1->sFilterRegister[1].FR2 = (ID_CAR_STATE2 << 3) | 4; CAN1->FA1R |= (1 << 2); // configure bank 2 CAN1->sFilterRegister[2].FR1 = (ID_L4_TESTING_BL_CMD << 3) | 4; - CAN1->sFilterRegister[2].FR2 = (ID_FAULT_SYNC_MAIN_MODULE << 3) | 4; + CAN1->sFilterRegister[2].FR2 = (ID_FAULT_SYNC_PDU << 3) | 4; CAN1->FA1R |= (1 << 3); // configure bank 3 - CAN1->sFilterRegister[3].FR1 = (ID_FAULT_SYNC_DRIVELINE << 3) | 4; - CAN1->sFilterRegister[3].FR2 = (ID_FAULT_SYNC_DASHBOARD << 3) | 4; + CAN1->sFilterRegister[3].FR1 = (ID_FAULT_SYNC_MAIN_MODULE << 3) | 4; + CAN1->sFilterRegister[3].FR2 = (ID_FAULT_SYNC_DRIVELINE << 3) | 4; CAN1->FA1R |= (1 << 4); // configure bank 4 CAN1->sFilterRegister[4].FR1 = (ID_FAULT_SYNC_PRECHARGE << 3) | 4; CAN1->sFilterRegister[4].FR2 = (ID_FAULT_SYNC_TORQUE_VECTOR_FPGA << 3) | 4; CAN1->FA1R |= (1 << 5); // configure bank 5 - CAN1->sFilterRegister[5].FR1 = (ID_SET_FAULT << 3) | 4; - CAN1->sFilterRegister[5].FR2 = (ID_RETURN_FAULT_CONTROL << 3) | 4; + CAN1->sFilterRegister[5].FR1 = (ID_FAULT_SYNC_TORQUE_VECTOR_FPGA << 3) | 4; + CAN1->sFilterRegister[5].FR2 = (ID_SET_FAULT << 3) | 4; CAN1->FA1R |= (1 << 6); // configure bank 6 - CAN1->sFilterRegister[6].FR1 = (ID_DAQ_COMMAND_TEST_NODE << 3) | 4; + CAN1->sFilterRegister[6].FR1 = (ID_RETURN_FAULT_CONTROL << 3) | 4; + CAN1->sFilterRegister[6].FR2 = (ID_DAQ_COMMAND_TEST_NODE << 3) | 4; /* END AUTO FILTER */ CAN1->FMR &= ~CAN_FMR_FINIT; // Enable Filters (exit filter init mode) diff --git a/source/l4_testing/can/can_parse.h b/source/l4_testing/can/can_parse.h index 7597c1fd..b4b61fbf 100644 --- a/source/l4_testing/can/can_parse.h +++ b/source/l4_testing/can/can_parse.h @@ -31,13 +31,14 @@ #define ID_WHEEL_SPEEDS 0xc0001ff #define ID_ADC_VALUES 0x1234 #define ID_CAR_STATE 0xbeef420 -#define ID_FAULT_SYNC_TEST_NODE 0x8cb7f +#define ID_FAULT_SYNC_TEST_NODE 0x8cbbf #define ID_DAQ_RESPONSE_TEST_NODE 0x17ffffff #define ID_FRONT_DRIVELINE_HB 0x4001903 #define ID_TEST_MSG5_2 0x1400017d #define ID_TEST_STALE 0x2222 #define ID_CAR_STATE2 0xbeef421 #define ID_L4_TESTING_BL_CMD 0x409c83e +#define ID_FAULT_SYNC_PDU 0x8cb5f #define ID_FAULT_SYNC_MAIN_MODULE 0x8ca01 #define ID_FAULT_SYNC_DRIVELINE 0x8ca83 #define ID_FAULT_SYNC_DASHBOARD 0x8cb05 @@ -67,6 +68,7 @@ #define DLC_TEST_STALE 1 #define DLC_CAR_STATE2 1 #define DLC_L4_TESTING_BL_CMD 5 +#define DLC_FAULT_SYNC_PDU 3 #define DLC_FAULT_SYNC_MAIN_MODULE 3 #define DLC_FAULT_SYNC_DRIVELINE 3 #define DLC_FAULT_SYNC_DASHBOARD 3 @@ -313,6 +315,10 @@ typedef union { uint64_t cmd: 8; uint64_t data: 32; } l4_testing_bl_cmd; + struct { + uint64_t idx: 16; + uint64_t latched: 1; + } fault_sync_pdu; struct { uint64_t idx: 16; uint64_t latched: 1; @@ -380,6 +386,10 @@ typedef struct { uint8_t cmd; uint32_t data; } l4_testing_bl_cmd; + struct { + uint16_t idx; + uint8_t latched; + } fault_sync_pdu; struct { uint16_t idx; uint8_t latched; diff --git a/source/main_module/can/can_parse.c b/source/main_module/can/can_parse.c index e114a0a1..fd767dec 100644 --- a/source/main_module/can/can_parse.c +++ b/source/main_module/can/can_parse.c @@ -113,6 +113,11 @@ void canRxUpdate() can_data.throttle_remapped.stale = 0; can_data.throttle_remapped.last_rx = sched.os_ticks; break; + case ID_FAULT_SYNC_PDU: + can_data.fault_sync_pdu.idx = msg_data_a->fault_sync_pdu.idx; + can_data.fault_sync_pdu.latched = msg_data_a->fault_sync_pdu.latched; + handleCallbacks(msg_data_a->fault_sync_main_module.idx, msg_data_a->fault_sync_main_module.latched); + break; case ID_FAULT_SYNC_DRIVELINE: can_data.fault_sync_driveline.idx = msg_data_a->fault_sync_driveline.idx; can_data.fault_sync_driveline.latched = msg_data_a->fault_sync_driveline.latched; @@ -211,18 +216,19 @@ bool initCANFilter() CAN1->sFilterRegister[3].FR2 = (ID_COOLING_DRIVER_REQUEST << 3) | 4; CAN1->FA1R |= (1 << 4); // configure bank 4 CAN1->sFilterRegister[4].FR1 = (ID_THROTTLE_REMAPPED << 3) | 4; - CAN1->sFilterRegister[4].FR2 = (ID_FAULT_SYNC_DRIVELINE << 3) | 4; + CAN1->sFilterRegister[4].FR2 = (ID_FAULT_SYNC_PDU << 3) | 4; CAN1->FA1R |= (1 << 5); // configure bank 5 - CAN1->sFilterRegister[5].FR1 = (ID_FAULT_SYNC_DASHBOARD << 3) | 4; - CAN1->sFilterRegister[5].FR2 = (ID_FAULT_SYNC_PRECHARGE << 3) | 4; + CAN1->sFilterRegister[5].FR1 = (ID_FAULT_SYNC_DRIVELINE << 3) | 4; + CAN1->sFilterRegister[5].FR2 = (ID_FAULT_SYNC_DASHBOARD << 3) | 4; CAN1->FA1R |= (1 << 6); // configure bank 6 CAN1->sFilterRegister[6].FR1 = (ID_FAULT_SYNC_TORQUE_VECTOR_FPGA << 3) | 4; CAN1->sFilterRegister[6].FR2 = (ID_FAULT_SYNC_TEST_NODE << 3) | 4; CAN1->FA1R |= (1 << 7); // configure bank 7 - CAN1->sFilterRegister[7].FR1 = (ID_SET_FAULT << 3) | 4; - CAN1->sFilterRegister[7].FR2 = (ID_RETURN_FAULT_CONTROL << 3) | 4; + CAN1->sFilterRegister[7].FR1 = (ID_FAULT_SYNC_TEST_NODE << 3) | 4; + CAN1->sFilterRegister[7].FR2 = (ID_SET_FAULT << 3) | 4; CAN1->FA1R |= (1 << 8); // configure bank 8 - CAN1->sFilterRegister[8].FR1 = (ID_DAQ_COMMAND_MAIN_MODULE << 3) | 4; + CAN1->sFilterRegister[8].FR1 = (ID_RETURN_FAULT_CONTROL << 3) | 4; + CAN1->sFilterRegister[8].FR2 = (ID_DAQ_COMMAND_MAIN_MODULE << 3) | 4; /* END AUTO FILTER */ CAN1->FA1R |= (1 << 6); // configure bank 6 CAN1->sFilterRegister[6].FR1 = (ID_LWS_STANDARD << 21); diff --git a/source/main_module/can/can_parse.h b/source/main_module/can/can_parse.h index 111ac499..3d1271c3 100644 --- a/source/main_module/can/can_parse.h +++ b/source/main_module/can/can_parse.h @@ -45,6 +45,7 @@ #define ID_MAIN_MODULE_BL_CMD 0x409c43e #define ID_COOLING_DRIVER_REQUEST 0xc0002c5 #define ID_THROTTLE_REMAPPED 0xc0025b7 +#define ID_FAULT_SYNC_PDU 0x8cb5f #define ID_FAULT_SYNC_DRIVELINE 0x8ca83 #define ID_FAULT_SYNC_DASHBOARD 0x8cb05 #define ID_FAULT_SYNC_PRECHARGE 0x8cac4 @@ -82,6 +83,7 @@ #define DLC_MAIN_MODULE_BL_CMD 5 #define DLC_COOLING_DRIVER_REQUEST 5 #define DLC_THROTTLE_REMAPPED 4 +#define DLC_FAULT_SYNC_PDU 3 #define DLC_FAULT_SYNC_DRIVELINE 3 #define DLC_FAULT_SYNC_DASHBOARD 3 #define DLC_FAULT_SYNC_PRECHARGE 3 @@ -314,7 +316,7 @@ typedef enum { // Message Raw Structures /* BEGIN AUTO MESSAGE STRUCTURE */ -typedef union { +typedef union { struct { uint64_t car_state: 8; uint64_t precharge_state: 1; @@ -454,6 +456,10 @@ typedef union { uint64_t remap_k_rl: 16; uint64_t remap_k_rr: 16; } throttle_remapped; + struct { + uint64_t idx: 16; + uint64_t latched: 1; + } fault_sync_pdu; struct { uint64_t idx: 16; uint64_t latched: 1; @@ -552,6 +558,10 @@ typedef struct { uint8_t stale; uint32_t last_rx; } throttle_remapped; + struct { + uint16_t idx; + uint8_t latched; + } fault_sync_pdu; struct { uint16_t idx; uint8_t latched; diff --git a/source/pdu/CMakeLists.txt b/source/pdu/CMakeLists.txt index 6b3492d9..488facd6 100644 --- a/source/pdu/CMakeLists.txt +++ b/source/pdu/CMakeLists.txt @@ -11,6 +11,6 @@ set_target_properties(${TARGET_NAME} PROPERTIES COMPONENT_NAME ${COMPONENT_NAME} COMPONENT_DIR ${CMAKE_CURRENT_LIST_DIR} LINKER_SCRIPT "STM32F407VGTx_FLASH" - COMMON_LIBS "CMSIS_F407;PSCHED_F407;PHAL_F407;" + COMMON_LIBS "CMSIS_F407;PSCHED_F407;PHAL_F407;QUEUE;FAULTS_L496" ) COMMON_FIRMWARE_COMPONENT(${TARGET_NAME}) \ No newline at end of file diff --git a/source/pdu/can/can_parse.c b/source/pdu/can/can_parse.c new file mode 100644 index 00000000..99f6a6f9 --- /dev/null +++ b/source/pdu/can/can_parse.c @@ -0,0 +1,138 @@ +/** + * @file can_parse.c + * @author Luke Oxley (lcoxley@purdue.edu) + * @brief Parsing of CAN messages using auto-generated structures with bit-fields + * @version 0.1 + * @date 2021-09-15 + * + * @copyright Copyright (c) 2021 + * + */ +#include "can_parse.h" + +// prototypes +bool initCANFilter(); + +can_data_t can_data; +q_handle_t* q_rx_can_a; +volatile uint32_t last_can_rx_time_ms = 0; + +void initCANParse(q_handle_t* rx_a) +{ + q_rx_can_a = rx_a; + initCANFilter(); +} + +void canRxUpdate() +{ + CanMsgTypeDef_t msg_header; + CanParsedData_t* msg_data_a; + + if(qReceive(q_rx_can_a, &msg_header) == SUCCESS_G) + { + last_can_rx_time_ms = sched.os_ticks; + msg_data_a = (CanParsedData_t *) &msg_header.Data; + /* BEGIN AUTO CASES */ + switch(msg_header.ExtId) + { + case ID_FAULT_SYNC_MAIN_MODULE: + can_data.fault_sync_main_module.idx = msg_data_a->fault_sync_main_module.idx; + can_data.fault_sync_main_module.latched = msg_data_a->fault_sync_main_module.latched; + handleCallbacks(msg_data_a->fault_sync_main_module.idx, msg_data_a->fault_sync_main_module.latched); + break; + case ID_FAULT_SYNC_DRIVELINE: + can_data.fault_sync_driveline.idx = msg_data_a->fault_sync_driveline.idx; + can_data.fault_sync_driveline.latched = msg_data_a->fault_sync_driveline.latched; + handleCallbacks(msg_data_a->fault_sync_main_module.idx, msg_data_a->fault_sync_main_module.latched); + break; + case ID_FAULT_SYNC_DASHBOARD: + can_data.fault_sync_dashboard.idx = msg_data_a->fault_sync_dashboard.idx; + can_data.fault_sync_dashboard.latched = msg_data_a->fault_sync_dashboard.latched; + handleCallbacks(msg_data_a->fault_sync_main_module.idx, msg_data_a->fault_sync_main_module.latched); + break; + case ID_FAULT_SYNC_PRECHARGE: + can_data.fault_sync_precharge.idx = msg_data_a->fault_sync_precharge.idx; + can_data.fault_sync_precharge.latched = msg_data_a->fault_sync_precharge.latched; + handleCallbacks(msg_data_a->fault_sync_main_module.idx, msg_data_a->fault_sync_main_module.latched); + break; + case ID_FAULT_SYNC_TORQUE_VECTOR_FPGA: + can_data.fault_sync_torque_vector_fpga.idx = msg_data_a->fault_sync_torque_vector_fpga.idx; + can_data.fault_sync_torque_vector_fpga.latched = msg_data_a->fault_sync_torque_vector_fpga.latched; + handleCallbacks(msg_data_a->fault_sync_main_module.idx, msg_data_a->fault_sync_main_module.latched); + break; + case ID_FAULT_SYNC_TEST_NODE: + can_data.fault_sync_test_node.idx = msg_data_a->fault_sync_test_node.idx; + can_data.fault_sync_test_node.latched = msg_data_a->fault_sync_test_node.latched; + handleCallbacks(msg_data_a->fault_sync_main_module.idx, msg_data_a->fault_sync_main_module.latched); + break; + case ID_SET_FAULT: + can_data.set_fault.id = msg_data_a->set_fault.id; + can_data.set_fault.value = msg_data_a->set_fault.value; + set_fault_daq(msg_data_a->set_fault.id, msg_data_a->set_fault.value); + break; + case ID_RETURN_FAULT_CONTROL: + can_data.return_fault_control.id = msg_data_a->return_fault_control.id; + return_fault_control(msg_data_a->return_fault_control.id); + break; + default: + __asm__("nop"); + } + /* END AUTO CASES */ + } + + /* BEGIN AUTO STALE CHECKS */ + /* END AUTO STALE CHECKS */ +} + +bool initCANFilter() +{ + CAN1->MCR |= CAN_MCR_INRQ; // Enter back into INIT state (required for changing scale) + uint32_t timeout = 0; + while(!(CAN1->MSR & CAN_MSR_INAK) && ++timeout < PHAL_CAN_INIT_TIMEOUT) + ; + if (timeout == PHAL_CAN_INIT_TIMEOUT) + return false; + + CAN1->FMR |= CAN_FMR_FINIT; // Enter init mode for filter banks + CAN1->FM1R |= 0x07FFFFFF; // Set banks 0-27 to id mode + CAN1->FS1R |= 0x07FFFFFF; // Set banks 0-27 to 32-bit scale + + /* BEGIN AUTO FILTER */ + CAN1->FA1R |= (1 << 0); // configure bank 0 + CAN1->sFilterRegister[0].FR1 = (ID_FAULT_SYNC_MAIN_MODULE << 3) | 4; + CAN1->sFilterRegister[0].FR2 = (ID_FAULT_SYNC_DRIVELINE << 3) | 4; + CAN1->FA1R |= (1 << 1); // configure bank 1 + CAN1->sFilterRegister[1].FR1 = (ID_FAULT_SYNC_DASHBOARD << 3) | 4; + CAN1->sFilterRegister[1].FR2 = (ID_FAULT_SYNC_PRECHARGE << 3) | 4; + CAN1->FA1R |= (1 << 2); // configure bank 2 + CAN1->sFilterRegister[2].FR1 = (ID_FAULT_SYNC_TORQUE_VECTOR_FPGA << 3) | 4; + CAN1->sFilterRegister[2].FR2 = (ID_FAULT_SYNC_TEST_NODE << 3) | 4; + CAN1->FA1R |= (1 << 3); // configure bank 3 + CAN1->sFilterRegister[3].FR1 = (ID_SET_FAULT << 3) | 4; + CAN1->sFilterRegister[3].FR2 = (ID_RETURN_FAULT_CONTROL << 3) | 4; + /* END AUTO FILTER */ + + CAN1->FMR &= ~CAN_FMR_FINIT; // Enable Filters (exit filter init mode) + + // Enter back into NORMAL mode + CAN1->MCR &= ~CAN_MCR_INRQ; + while((CAN1->MSR & CAN_MSR_INAK) && ++timeout < PHAL_CAN_INIT_TIMEOUT) + ; + + return timeout != PHAL_CAN_INIT_TIMEOUT; +} + + +void canProcessRxIRQs(CanMsgTypeDef_t* rx) +{ + CanParsedData_t* msg_data_a; + + msg_data_a = (CanParsedData_t *) rx->Data; + switch(rx->ExtId) + { + /* BEGIN AUTO RX IRQ */ + /* END AUTO RX IRQ */ + default: + __asm__("nop"); + } +} diff --git a/source/pdu/can/can_parse.h b/source/pdu/can/can_parse.h new file mode 100644 index 00000000..cd28ced5 --- /dev/null +++ b/source/pdu/can/can_parse.h @@ -0,0 +1,199 @@ +/** + * @file can_parse.h + * @author Luke Oxley (lcoxley@purdue.edu) + * @brief Parsing of CAN messages using auto-generated structures with bit-fields + * @version 0.1 + * @date 2021-09-15 + * + * @copyright Copyright (c) 2021 + * + */ +#ifndef _CAN_PARSE_H_ +#define _CAN_PARSE_H_ + +#include "common/queue/queue.h" +#include "common/psched/psched.h" +#include "common/phal_F4_F7/can/can.h" + +// Make this match the node name within the can_config.json +#define NODE_NAME "PDU" + +// Message ID definitions +/* BEGIN AUTO ID DEFS */ +#define ID_PDU_TEST 0x401041f +#define ID_FAULT_SYNC_PDU 0x8cb5f +#define ID_FAULT_SYNC_MAIN_MODULE 0x8ca01 +#define ID_FAULT_SYNC_DRIVELINE 0x8ca83 +#define ID_FAULT_SYNC_DASHBOARD 0x8cb05 +#define ID_FAULT_SYNC_PRECHARGE 0x8cac4 +#define ID_FAULT_SYNC_TORQUE_VECTOR_FPGA 0x8ca42 +#define ID_FAULT_SYNC_TEST_NODE 0x8cbbf +#define ID_SET_FAULT 0x809c83e +#define ID_RETURN_FAULT_CONTROL 0x809c87e +/* END AUTO ID DEFS */ + +// Message DLC definitions +/* BEGIN AUTO DLC DEFS */ +#define DLC_PDU_TEST 3 +#define DLC_FAULT_SYNC_PDU 3 +#define DLC_FAULT_SYNC_MAIN_MODULE 3 +#define DLC_FAULT_SYNC_DRIVELINE 3 +#define DLC_FAULT_SYNC_DASHBOARD 3 +#define DLC_FAULT_SYNC_PRECHARGE 3 +#define DLC_FAULT_SYNC_TORQUE_VECTOR_FPGA 3 +#define DLC_FAULT_SYNC_TEST_NODE 3 +#define DLC_SET_FAULT 3 +#define DLC_RETURN_FAULT_CONTROL 2 +/* END AUTO DLC DEFS */ + +// Message sending macros +/* BEGIN AUTO SEND MACROS */ +#define SEND_PDU_TEST(queue, test_1_, test_2_, test_3_) do {\ + CanMsgTypeDef_t msg = {.Bus=CAN1, .ExtId=ID_PDU_TEST, .DLC=DLC_PDU_TEST, .IDE=1};\ + CanParsedData_t* data_a = (CanParsedData_t *) &msg.Data;\ + data_a->pdu_test.test_1 = test_1_;\ + data_a->pdu_test.test_2 = test_2_;\ + data_a->pdu_test.test_3 = test_3_;\ + qSendToBack(&queue, &msg);\ + } while(0) +#define SEND_FAULT_SYNC_PDU(queue, idx_, latched_) do {\ + CanMsgTypeDef_t msg = {.Bus=CAN1, .ExtId=ID_FAULT_SYNC_PDU, .DLC=DLC_FAULT_SYNC_PDU, .IDE=1};\ + CanParsedData_t* data_a = (CanParsedData_t *) &msg.Data;\ + data_a->fault_sync_pdu.idx = idx_;\ + data_a->fault_sync_pdu.latched = latched_;\ + qSendToBack(&queue, &msg);\ + } while(0) +/* END AUTO SEND MACROS */ + +// Stale Checking +#define STALE_THRESH 3 / 2 // 3 / 2 would be 150% of period +/* BEGIN AUTO UP DEFS (Update Period)*/ +/* END AUTO UP DEFS */ + +#define CHECK_STALE(stale, curr, last, period) if(!stale && \ + (curr - last) > period * STALE_THRESH) stale = 1 + +/* BEGIN AUTO CAN ENUMERATIONS */ +/* END AUTO CAN ENUMERATIONS */ + +// Message Raw Structures +/* BEGIN AUTO MESSAGE STRUCTURE */ +typedef union { + struct { + uint64_t test_1: 8; + uint64_t test_2: 8; + uint64_t test_3: 8; + } pdu_test; + struct { + uint64_t idx: 16; + uint64_t latched: 1; + } fault_sync_pdu; + struct { + uint64_t idx: 16; + uint64_t latched: 1; + } fault_sync_main_module; + struct { + uint64_t idx: 16; + uint64_t latched: 1; + } fault_sync_driveline; + struct { + uint64_t idx: 16; + uint64_t latched: 1; + } fault_sync_dashboard; + struct { + uint64_t idx: 16; + uint64_t latched: 1; + } fault_sync_precharge; + struct { + uint64_t idx: 16; + uint64_t latched: 1; + } fault_sync_torque_vector_fpga; + struct { + uint64_t idx: 16; + uint64_t latched: 1; + } fault_sync_test_node; + struct { + uint64_t id: 16; + uint64_t value: 1; + } set_fault; + struct { + uint64_t id: 16; + } return_fault_control; + uint8_t raw_data[8]; +} __attribute__((packed)) CanParsedData_t; +/* END AUTO MESSAGE STRUCTURE */ + +// contains most up to date received +// type for each variable matches that defined in JSON +/* BEGIN AUTO CAN DATA STRUCTURE */ +typedef struct { + struct { + uint16_t idx; + uint8_t latched; + } fault_sync_main_module; + struct { + uint16_t idx; + uint8_t latched; + } fault_sync_driveline; + struct { + uint16_t idx; + uint8_t latched; + } fault_sync_dashboard; + struct { + uint16_t idx; + uint8_t latched; + } fault_sync_precharge; + struct { + uint16_t idx; + uint8_t latched; + } fault_sync_torque_vector_fpga; + struct { + uint16_t idx; + uint8_t latched; + } fault_sync_test_node; + struct { + uint16_t id; + uint8_t value; + } set_fault; + struct { + uint16_t id; + } return_fault_control; +} can_data_t; +/* END AUTO CAN DATA STRUCTURE */ + +extern can_data_t can_data; + +/* BEGIN AUTO EXTERN CALLBACK */ +extern void handleCallbacks(uint16_t id, bool latched); +extern void set_fault_daq(uint16_t id, bool value); +extern void return_fault_control(uint16_t id); +extern void send_fault(uint16_t id, bool latched); +/* END AUTO EXTERN CALLBACK */ + +/* BEGIN AUTO EXTERN RX IRQ */ +/* END AUTO EXTERN RX IRQ */ + +/** + * @brief Setup queue and message filtering + * + * @param q_rx_can RX buffer of CAN messages + */ +void initCANParse(q_handle_t* q_rx_can_a); + +/** + * @brief Pull message off of rx buffer, + * update can_data struct, + * check for stale messages + */ +void canRxUpdate(); + +/** + * @brief Process any rx message callbacks from the CAN Rx IRQ + * + * @param rx rx data from message just recieved + */ +void canProcessRxIRQs(CanMsgTypeDef_t* rx); + +extern volatile uint32_t last_can_rx_time_ms; + +#endif \ No newline at end of file diff --git a/source/pdu/main.c b/source/pdu/main.c index e63f8574..7dd07802 100644 --- a/source/pdu/main.c +++ b/source/pdu/main.c @@ -3,10 +3,14 @@ #include "common/phal_F4_F7/dma/dma.h" #include "common/phal_F4_F7/gpio/gpio.h" #include "common/phal_F4_F7/rcc/rcc.h" +#include "common/phal_F4_F7/can/can.h" +#include "common/phal_F4_F7/can/can.h" #include "common/psched/psched.h" +#include "common/faults/faults.h" /* Module Includes */ #include "main.h" +#include "can_parse.h" GPIOInitConfig_t gpio_config[] = { // Status Indicators @@ -142,10 +146,21 @@ extern uint32_t AHBClockRateHz; extern uint32_t PLLClockRateHz; void HardFault_Handler(); +void preflightAnimation(); +void preflightChecks(void); +void canTxUpdate(); void heatBeatLED(); +void sendtestmsg(); + +q_handle_t q_tx_can; +q_handle_t q_rx_can; int main() { + /* Data Struct init */ + qConstruct(&q_tx_can, sizeof(CanMsgTypeDef_t)); + qConstruct(&q_rx_can, sizeof(CanMsgTypeDef_t)); + if(0 != PHAL_configureClockRates(&clock_config)) { HardFault_Handler(); @@ -156,21 +171,138 @@ int main() } PHAL_writeGPIO(LED_CTRL_BLANK_GPIO_Port, LED_CTRL_BLANK_Pin, 1); + /* Task Creation */ schedInit(APB1ClockRateHz); + configureAnim(preflightAnimation, preflightChecks, 60, 750); + /* Schedule Periodic tasks here */ taskCreate(heatBeatLED, 500); + taskCreate(sendtestmsg, 100); + taskCreateBackground(canTxUpdate); + taskCreateBackground(canRxUpdate); schedStart(); return 0; } +void preflightChecks(void) { + static uint8_t state; + + switch (state++) + { + case 0: + if(!PHAL_initCAN(CAN1, false)) + { + HardFault_Handler(); + } + NVIC_EnableIRQ(CAN1_RX0_IRQn); + break; + case 1: + initCANParse(&q_rx_can); + break; + default: + registerPreflightComplete(1); + state = 255; // prevent wrap around + } +} + +void preflightAnimation(void) { + static uint32_t time; + + PHAL_writeGPIO(HEARTBEAT_GPIO_Port, HEARTBEAT_Pin, 0); + PHAL_writeGPIO(ERR_LED_GPIO_Port, ERR_LED_Pin, 0); + PHAL_writeGPIO(CONN_LED_GPIO_Port, CONN_LED_Pin, 0); + + switch (time++ % 6) + { + case 0: + case 5: + PHAL_writeGPIO(HEARTBEAT_GPIO_Port, HEARTBEAT_Pin, 1); + break; + case 1: + case 4: + PHAL_writeGPIO(CONN_LED_GPIO_Port, CONN_LED_Pin, 1); + break; + case 2: + case 3: + PHAL_writeGPIO(ERR_LED_GPIO_Port, ERR_LED_Pin, 1); + break; + } +} + void heatBeatLED() { PHAL_toggleGPIO(HEARTBEAT_GPIO_Port, HEARTBEAT_Pin); } +void sendtestmsg() +{ + static uint8_t test_1; + static uint8_t test_2; + static uint8_t test_3; + + if (test_3 == 0) + test_3 = 1; + + SEND_PDU_TEST(q_tx_can, test_1++, test_2, test_3); + + test_2 += 5; + test_3 *= 2; + +} + +void canTxUpdate() +{ + CanMsgTypeDef_t tx_msg; + if (qReceive(&q_tx_can, &tx_msg) == SUCCESS_G) // Check queue for items and take if there is one + { + PHAL_txCANMessage(&tx_msg); + } +} + +void CAN1_RX0_IRQHandler() +{ + if (CAN1->RF0R & CAN_RF0R_FOVR0) // FIFO Overrun + CAN1->RF0R &= !(CAN_RF0R_FOVR0); + + if (CAN1->RF0R & CAN_RF0R_FULL0) // FIFO Full + CAN1->RF0R &= !(CAN_RF0R_FULL0); + + if (CAN1->RF0R & CAN_RF0R_FMP0_Msk) // Release message pending + { + CanMsgTypeDef_t rx; + rx.Bus = CAN1; + + // Get either StdId or ExtId + if (CAN_RI0R_IDE & CAN1->sFIFOMailBox[0].RIR) + { + rx.ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & CAN1->sFIFOMailBox[0].RIR) >> CAN_RI0R_EXID_Pos; + } + else + { + rx.StdId = (CAN_RI0R_STID & CAN1->sFIFOMailBox[0].RIR) >> CAN_TI0R_STID_Pos; + } + + rx.DLC = (CAN_RDT0R_DLC & CAN1->sFIFOMailBox[0].RDTR) >> CAN_RDT0R_DLC_Pos; + + rx.Data[0] = (uint8_t) (CAN1->sFIFOMailBox[0].RDLR >> 0) & 0xFF; + rx.Data[1] = (uint8_t) (CAN1->sFIFOMailBox[0].RDLR >> 8) & 0xFF; + rx.Data[2] = (uint8_t) (CAN1->sFIFOMailBox[0].RDLR >> 16) & 0xFF; + rx.Data[3] = (uint8_t) (CAN1->sFIFOMailBox[0].RDLR >> 24) & 0xFF; + rx.Data[4] = (uint8_t) (CAN1->sFIFOMailBox[0].RDHR >> 0) & 0xFF; + rx.Data[5] = (uint8_t) (CAN1->sFIFOMailBox[0].RDHR >> 8) & 0xFF; + rx.Data[6] = (uint8_t) (CAN1->sFIFOMailBox[0].RDHR >> 16) & 0xFF; + rx.Data[7] = (uint8_t) (CAN1->sFIFOMailBox[0].RDHR >> 24) & 0xFF; + + CAN1->RF0R |= (CAN_RF0R_RFOM0); + qSendToBack(&q_rx_can, &rx); // Add to queue (qSendToBack is interrupt safe) + } +} + + void HardFault_Handler() { + PHAL_writeGPIO(ERR_LED_GPIO_Port, ERR_LED_Pin, 1); while(1) { __asm__("nop"); diff --git a/source/precharge/can/can_parse.c b/source/precharge/can/can_parse.c index 85701d0a..c970bb32 100644 --- a/source/precharge/can/can_parse.c +++ b/source/precharge/can/can_parse.c @@ -4,9 +4,9 @@ * @brief Parsing of CAN messages using auto-generated structures with bit-fields * @version 0.1 * @date 2021-09-15 - * + * * @copyright Copyright (c) 2021 - * + * */ #include "can_parse.h" @@ -222,6 +222,11 @@ void canRxUpdate() can_data.precharge_bl_cmd.data = msg_data_a->precharge_bl_cmd.data; precharge_bl_cmd_CALLBACK(msg_data_a); break; + case ID_FAULT_SYNC_PDU: + can_data.fault_sync_pdu.idx = msg_data_a->fault_sync_pdu.idx; + can_data.fault_sync_pdu.latched = msg_data_a->fault_sync_pdu.latched; + handleCallbacks(msg_data_a->fault_sync_main_module.idx, msg_data_a->fault_sync_main_module.latched); + break; case ID_FAULT_SYNC_MAIN_MODULE: can_data.fault_sync_main_module.idx = msg_data_a->fault_sync_main_module.idx; can_data.fault_sync_main_module.latched = msg_data_a->fault_sync_main_module.latched; @@ -285,7 +290,7 @@ void canRxUpdate() bool initCANFilter() { - CAN1->MCR |= CAN_MCR_INRQ; // Enter back into INIT state (required for changing scale) + CAN1->MCR |= CAN_MCR_INRQ; // Enter back into INIT state (required for changing scale) uint32_t timeout = 0; while( !(CAN1->MSR & CAN_MSR_INAK) && ++timeout < PHAL_CAN_INIT_TIMEOUT); @@ -294,15 +299,15 @@ bool initCANFilter() CAN1->FMR |= CAN_FMR_FINIT; // Enter init mode for filter banks - /** + /** * Configure the CAN2 start bank. * There are 28 total filter banks that are shared between CAN1 and CAN2. * The CAN2SB field indicates where the split between CAN1 and 2 is. * A value of 14 means that 0...13 are for CAN1 and 14...27 are for CAN2. - * + * * Make sure that all CAN filter configuration is done with the CAN1 peripheral. - * CAN2 does not have access to modify/view the filters. - */ + * CAN2 does not have access to modify/view the filters. + */ CAN1->FMR &= ~CAN_FMR_CAN2SB; CAN1->FMR |= (14 << CAN_FMR_CAN2SB_Pos); // Set 0..13 for CAN1 and 14..27 for CAN2 CAN1->FM1R |= 0x07FFFFFF; // Set banks 0-27 to id mode @@ -341,20 +346,21 @@ bool initCANFilter() CAN1->sFilterRegister[1].FR2 = (ID_ORION_ERRORS << 3) | 4; CAN1->FA1R |= (1 << 2); // configure bank 2 CAN1->sFilterRegister[2].FR1 = (ID_PRECHARGE_BL_CMD << 3) | 4; - CAN1->sFilterRegister[2].FR2 = (ID_FAULT_SYNC_MAIN_MODULE << 3) | 4; + CAN1->sFilterRegister[2].FR2 = (ID_FAULT_SYNC_PDU << 3) | 4; CAN1->FA1R |= (1 << 3); // configure bank 3 - CAN1->sFilterRegister[3].FR1 = (ID_FAULT_SYNC_DRIVELINE << 3) | 4; - CAN1->sFilterRegister[3].FR2 = (ID_FAULT_SYNC_DASHBOARD << 3) | 4; + CAN1->sFilterRegister[3].FR1 = (ID_FAULT_SYNC_MAIN_MODULE << 3) | 4; + CAN1->sFilterRegister[3].FR2 = (ID_FAULT_SYNC_DRIVELINE << 3) | 4; CAN1->FA1R |= (1 << 4); // configure bank 4 CAN1->sFilterRegister[4].FR1 = (ID_FAULT_SYNC_TORQUE_VECTOR_FPGA << 3) | 4; CAN1->sFilterRegister[4].FR2 = (ID_FAULT_SYNC_TEST_NODE << 3) | 4; CAN1->FA1R |= (1 << 5); // configure bank 5 - CAN1->sFilterRegister[5].FR1 = (ID_SET_FAULT << 3) | 4; - CAN1->sFilterRegister[5].FR2 = (ID_RETURN_FAULT_CONTROL << 3) | 4; + CAN1->sFilterRegister[5].FR1 = (ID_FAULT_SYNC_TEST_NODE << 3) | 4; + CAN1->sFilterRegister[5].FR2 = (ID_SET_FAULT << 3) | 4; CAN1->FA1R |= (1 << 6); // configure bank 6 - CAN1->sFilterRegister[6].FR1 = (ID_DAQ_COMMAND_PRECHARGE << 3) | 4; + CAN1->sFilterRegister[6].FR1 = (ID_RETURN_FAULT_CONTROL << 3) | 4; + CAN1->sFilterRegister[6].FR2 = (ID_DAQ_COMMAND_PRECHARGE << 3) | 4; /* END AUTO FILTER */ - + CAN1->FMR &= ~CAN_FMR_FINIT; // Enable Filters (exit filter init mode) CAN1->MCR &= ~CAN_MCR_INRQ; // Enter back into NORMAL mode diff --git a/source/precharge/can/can_parse.h b/source/precharge/can/can_parse.h index 979ad4de..51a9e2fb 100644 --- a/source/precharge/can/can_parse.h +++ b/source/precharge/can/can_parse.h @@ -4,9 +4,9 @@ * @brief Parsing of CAN messages using auto-generated structures with bit-fields * @version 0.1 * @date 2021-09-15 - * + * * @copyright Copyright (c) 2021 - * + * */ #ifndef _CAN_PARSE_H_ #define _CAN_PARSE_H_ @@ -58,6 +58,7 @@ #define ID_ORION_CURRENTS_VOLTS 0x140006f8 #define ID_ORION_ERRORS 0xc000738 #define ID_PRECHARGE_BL_CMD 0x409c57e +#define ID_FAULT_SYNC_PDU 0x8cb5f #define ID_FAULT_SYNC_MAIN_MODULE 0x8ca01 #define ID_FAULT_SYNC_DRIVELINE 0x8ca83 #define ID_FAULT_SYNC_DASHBOARD 0x8cb05 @@ -108,6 +109,7 @@ #define DLC_ORION_CURRENTS_VOLTS 4 #define DLC_ORION_ERRORS 4 #define DLC_PRECHARGE_BL_CMD 5 +#define DLC_FAULT_SYNC_PDU 3 #define DLC_FAULT_SYNC_MAIN_MODULE 3 #define DLC_FAULT_SYNC_DRIVELINE 3 #define DLC_FAULT_SYNC_DASHBOARD 3 @@ -271,7 +273,7 @@ // Message Raw Structures /* BEGIN AUTO MESSAGE STRUCTURE */ -typedef union { +typedef union { struct { uint64_t toggle: 1; uint64_t time: 16; @@ -521,6 +523,10 @@ typedef union { uint64_t cmd: 8; uint64_t data: 32; } precharge_bl_cmd; + struct { + uint64_t idx: 16; + uint64_t latched: 1; + } fault_sync_pdu; struct { uint64_t idx: 16; uint64_t latched: 1; @@ -735,6 +741,10 @@ typedef struct { uint8_t cmd; uint32_t data; } precharge_bl_cmd; + struct { + uint16_t idx; + uint8_t latched; + } fault_sync_pdu; struct { uint16_t idx; uint8_t latched; @@ -784,7 +794,7 @@ extern void send_fault(uint16_t id, bool latched); /** * @brief Setup queue and message filtering - * + * * @param q_rx_can RX buffer of CAN messages */ void initCANParse(q_handle_t* q_rx_can_a); @@ -798,7 +808,7 @@ void canRxUpdate(); /** * @brief Process any rx message callbacks from the CAN Rx IRQ - * + * * @param rx rx data from message just recieved */ void canProcessRxIRQs(CanMsgTypeDef_t* rx);