diff --git a/CHANGELOG.md b/CHANGELOG.md
index 7b2604db4..882ce130f 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -1,3 +1,272 @@
+## 1.0.7 (2024-09-04)
+### Feature
+- [rc_smt]: Add rc container for smart mode
+- [vepu580]: Optimization to improve VMAF
+- [vepu580]: Optimize hal processing for smart encoding
+- [vepu580]: Add qpmap and rc container interface
+- [vepu510]: Add anti-smear regs setup for H.264
+- [vepu510]: Add H.264 tuning setup
+- [vepu510]: Sync code from enc_tune branch
+- [vepu510]: Sync code from enc_tune branch
+- [vepu510]: Sync code from enc_tune branch
+- [mpp_trie]: Add trie context filling feature
+- [mpp_trie]: Add trie tag and shrink feature
+- [h264d]: support hdr meta parse
+- [h265e]: Support force mark & use ltr
+- [vpu_api]: support yuv444sp decode ouput pixel format
+
+### Fix
+- [h265d]: fix infochange loss when two sps continuous
+- [hal_h264e]: Fix CAVLC encode smartP stream err
+- [mpi_enc_test]: Remove redundant code about smart encoding
+- [h264e_sps]: fix the default value of max mv length
+- [enc_roi]: Fix cu_map init in vepu_54x_roi
+- [hal_vp9]: Optimize prob memory usage
+- [hal_h265d]: Allow reference missing for GDR
+- [osal]: Fix mpp_mem single instance issue
+- [hal_vp9d_com]: Fixed memory leak issue
+- [hal_h265d]: Avoid risk of segment fault
+- [hal_h265d]: fix error slot index marking
+- [h265d]: Adjust condition of scan type judgement
+- [mpp_hdr]: Fix buffer overflow issue
+- [mpp_buffer]: Synchronous log addition point
+- [hal_vepu]: fix split regs assignment
+- [vepu580]: poll max set to 1 on split out lowdelay mode
+- [mpp_common]: fix compile err on F_DUPFD_CLOEXEC not defined
+- [h265d]: return error on sps/pps read failure
+- [build]: The first toolchains is selected by default
+- [265e]:Fix the st refernce frame err in tsvc
+- [av1d]: when MetaData found then it is new frame
+- [m2vd]: Fix seq_head check error
+- [h265e_vepu510]: Fix a memory leak
+- [h265d]: auto output frame in dpb when ready
+- [m2vd]: Remove ref frame when info changed
+- [mpp_meta]: Missing data in the instance
+- [mpp_bitread]: Fix negative shift error
+- [osal]: fix 128 odd plus 64 bytes alignment
+- [h265d_parser]: Fix fmt configuration issue
+- [hal_av1d_vdpu383]: modify av1 segid wr/rd base config
+- [h265d_parser]: Fix fmt configuration issue
+- [hal_av1d_vdpu383]: add segid reg base config
+
+### Docs
+- Update 1.0.7 CHANGELOG.md
+- [readme]: Add more repo info
+
+### Refactor
+- [mpp_cfg]: Refactor MppTrie and string cfg
+
+### Chore
+- [mpp_mem]: Add mpp_realloc_size
+- [mpp_cfg]: Remove some unused code
+- fix compile warning
+
+## 1.0.6 (2024-06-12)
+### Feature
+- [vdpu383]: refine rcb info setup
+- [enc_265]: Support get Largest Code Unit size
+- [mpp_dec_cfg]: Add disable dpb check config
+- [vdpu383]: support 8K downscale mode
+
+### Fix
+- [drm]: Fix permission check issue on GKI kernel
+- [hal_h265e]: Amend 510 tid and sync cache
+- [hal_h265e]: Fix nalu type avoid stream warning
+- [h265e]: Fix vps/sps max temparal layers val
+- [hal_jpeg_vdpu1]: fix dec failed on RK3036 problem
+- [osal]: rv1109/rv1126 vcodec_type mismatch problem
+- [h264e_vepu2]: Adjust inter favor table
+- [h264d]: fix drop packets after reset when err stream
+- [h265d]: Allow filtering of consecutive start code
+- [hal_h264d_vdpu383]: fix spspps update issue
+- [mpp]: fix mpp frame leak when async enc
+- [enc]: Add use_lt_idx to output packet meta
+- [hal_h265e]: fix sse_sum get err
+- [mpp_enc_async]: fix mpp packet leak when thread quit
+- [enc_roi]: Support ROI cfg under CQP mode
+- [hal]: Fix the lib interdependence issue
+- [vepu_510]: fix same log type when enc feedback
+- [mpp_buffer]: fix dec/inc ref_count in multi threads
+- [mpp_enc_async]: fix debreath not work on async flow
+- [base]: fix AV1 and AVS2 string info missing problem
+- [mpp]: Add encoder input/output pts log
+- [hal_vepu580/510]: fix split out err when pass1 frame
+- [hal]: Fix target link issue
+- [hal_enc]: Fix lib dependency issue
+- [hal_h265d_vdpu383]: fix ref_err mark for special poc
+- [rc2_test]: fix pkt buffer overflow error
+- [enc_utils]: Support read odd resolution image
+- [allocator]: fix on invalid DMA heap allocator
+- [hal_h265e_vepu580]: fix reg config err for 2pass
+- [jpegd_vdpu]: Adjust file dump path
+- [mpp_common]: fix 128 odd plus 64 alignment
+- [cmake]: fix static build
+- [vdpu383]: Update vdpu383 error detection
+
+### Docs
+- Update 1.0.6 CHANGELOG.md
+
+### Refactor
+- [hal_jpegd]: init devices at hal_jpegd_api
+- [dec]: get deocder capability via common routine
+- [hal_av1d]: Migrate av1d from vpu to rkdec
+
+### Chore
+- [h265d]: Reduce malloc/free frequency of vps
+- [mpp_service]: fix typo err
+- [hal_h265d]: use INT_MAX for poc distance initiation
+- [cmake]: remove duplicate code
+
+## 1.0.5 (2024-04-19)
+### Feature
+- [vdpu383]: align hor stride to 128 odds + 64 byte
+- [vdpu383]: support 2x2 scale down
+- [mpp_buffer]: Add MppBuffer attach/detach func
+- [mpp_dev]: Add fd attach/detach operation
+- [vdpp]: Add libvdpp for hwpq
+- [vdpp]: Add capacity check function
+- [cmake]: Add building static library
+- [vdpp_test]: Add vdpp slt testcase
+- [av1d]: Add tile4x4 frame format support
+- [mpp_enc_cfg]: Add H.265 tier config
+- [jpeg]: Add VPU720 JPEG support
+- [enc]: Add config entry for output chroma format
+- [vdpu383]: Add vdpu383 av1 module
+- [vdpu383]: Add vdpu383 vp9 module
+- [vdpu383]: Add vdpu383 avs2 module
+- [vdpu383]: Add vdpu383 H.264 module
+- [vdpu383]: Add vdpu383 H.265 module
+- [vdpu383]: Add vdpu383 common module
+- [vdpp]: Add vdpp2 for rk3576
+- [vdpp]: Add vdpp module and vdpp_test
+- [vepu_510]: Add vepu510 h265e support
+- [vepu_510]: Add vepu510 h264e support
+- [mpp_frame]: Add tile format flag
+- [vepu_510] add vepu 510 common for H264 & h265
+- [mpp_soc]: support rk3576 soc
+
+### Fix
+- [avs2d_vdpu383]: Optimise dec result
+- [vdpu383]: Fix compiler warning
+- [vdpp]: Fix dmsr reg size imcompat error
+- [vdpu383]: hor stride alignment fix for vdpu383
+- [h265d_ref]: fix set fbc output fmt not effect issue
+- [vdpu383]: Fix memory out of bounds issue
+- [h264d_vdpu383]: Fix global parameter config issue
+- [avs2_parse]: add colorspace config to mpp_frame
+- [hal_h264e]:fix crash after init vepu buffer failure
+- [vpu_api]: Fix frame format and eos cfg
+- [av1d_vdpu383]: fix fbc hor_stride error
+- [av1d_parser]: fix fmt error for 10bit HDR source
+- [avs2d]: fix stuck when seq_end shows at pkt tail
+- [av1d_vdpu]: Fix forced 8bit output failure issue
+- [enc_async]: Invalidate cache for output buffer
+- [hal_av1d_vdpu383]: memleak for cdf_bufs
+- [av1d_vdpu383]: fix rcb buffer size
+- [vp9d_vdpu383]: Fix segid config issue
+- [vepu510]: Add split low delay output mode support
+- [avs2d_vdpu383]: Fix declaring shadow local variables issue
+- [av1]: Fix global config issue
+- [hal_av1d]: Delte cdf unused value
+- [av1]: Fix av1 display abnormality issue
+- [avs2d]: Remove a unnecessary log
+- [vepu510]: Adjust regs assignment
+- [hal_jpegd]: Add stream buffer flush
+- [265e_api]: Support cons_intra_pred_flag cfg
+- [mpp_enc]: Add device attach/detach on enc flow
+- [mpp_dec]: Add device attach/detach on dec flow
+- [vdpp]: Add error detection
+- [hal_265e_510]: modify srgn_max & rime_lvl val
+- [vdpu383]: spspps data not need copy all range ppsid
+- [vpu_api_legacy]: fix frame CodingType err
+- [av1]: Fix 10bit source display issue
+- [mpp_enc]: Expand the hdr_buf size
+- [av1]: Fix delta_q value read issue
+- [vdpu383]: Enable error detection
+- [ext_dma]: fix mmap permission error
+- [jpege_vpu720]: sync cache before return task
+- [mpp_buffer]: fix buffer type assigning
+- [vepu510]: Configure reg of Subjective param
+- [vepu510]: Checkout and optimize 510 reg.h
+- [mpp_dec]: Optimize HDR meta process
+- [av1d]: Fix scanlist calc issue
+- [h265e]: fix the profile tier cfg
+- [av1d]: Fix av1d ref stride error
+- [hal_h265e_vepu510]: Add cudecis reg cfg
+- [av1d]: Only rk3588 support 10bit translate to 8bit
+- [vp9d]: Fix vp9 hor stride issue
+- [rc]: Add i quality delta cfg on fixqp mode
+- [hal_h265d]: Fix filter col rcb buffer size calc
+- [av1d]: Fix compiler warning
+- [h264d]: Fix error mvc stream crash issue
+- [hal_h264e]: Fix qp err when fixqp mode
+- [h264d]: Fix H.264 error chroma_format_idc
+- [vdpu383]: Fix av1 rkfbc output error
+- [av1d]: Fix compatibility issues
+- [hal_h264d_vdpu383]: Reduce mpp_put_bits calls
+- Fix clerical error
+- [avs2d]: Fix get ref_frm slot idx error
+- [vdpu383]: Fix av1 global params bit pos issue
+- [vdpp]: fix sharp config error
+- [hal_av1d]: fix av1 dec err for rk3588
+- [vdpu383]: Fix av1 global params issue
+- [vepu510]: Fix camera record stuck issue
+- [utils]: fix read and write some YUV format
+- [mpp_bitput]: fix put bits overflow
+- [mpp_service]: fix rcb info env config
+- [vepu510]: Fix compile warning
+- [hal_vp9d]: fix colmv size calculator err
+- [avsd]: Fix the ref_frm slot idx erro in fast mode.
+
+### Docs
+- Update 1.0.5 CHANGELOG.md
+- [mpp_frame]: Add MppFrameFormat description
+
+### Refactor
+- [hal_av2sd]: refactor hal_api assign flow
+- [hal_h264d]: refactor hal_api assign flow
+- Using soc_type for compare instead of soc_name
+
+### Chore
+- [hal_h264e]: clean some unused code
+
+## 1.0.4 (2024-02-07)
+### Feature
+- [vpu_api_legacy]: Support RGB24 setup
+- [avsd]: keep codec type if not avs+
+- [mpi_enc_test]: add YUV400 fmt support
+- [mpp_enc]: Add YUV400 support for vepu580/540
+
+### Fix
+- [h265e]: fix hw stream size check error
+- [hal_vdpu]: unify colmv buffer size calculation
+- [vproc]: Fix deadlock in vproc thread
+- [h265e]: disable tmvp by default
+- [h265e]: Amend temporal_id to stream
+- [mpp_dump]: add YUV420SP_10BIT format dump
+- [hal_h265d]: Fix register length for rk3328/rk3328H
+- [hal_avsd]: Fix crash on no buffer decoded
+- [mpp_enc]: allow vp8 to cfg force idr frame
+- [m2vd]: fix unindentical of input and output pts list
+- [h265e_vepu580]: fix SIGSEGV when reencoding
+- [mpp_dmabuf]: fix align cache line size calculate err
+- [h265e_vepu580]: flush cache for the first tile
+- [dmabuf]: Disable dmabuf partial sync function
+- [iep_test]: use internal buffer group
+- [common]: Add mpp_dup function
+- [h265e]: Adapter RK3528 when encoding P frame skip
+- [h265e]: fix missing end_of_slice_segment_flag problem
+- [hal_av1d_vdpu]: change rkv_hor_align to 16 align
+- [av1d_parser]: set color info per frame
+- [jpegd]: add sof marker check when parser done
+
+### Docs
+- Update 1.0.4 CHANGELOG.md
+
+### Chore
+- [script]: add rebuild and clean for build
+- [mpp_enc_roi_utils]: change file format dos to unix
+
 ## 1.0.3 (2023-12-08)
 ### Feature
 - [dec_test]: Add buffer mode option
diff --git a/CMakeLists.txt b/CMakeLists.txt
index b75c8a68e..a38888e36 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -171,6 +171,8 @@ if(GCC)
     add_definitions(-fPIC)
     # disable exception for C++
     set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -fno-exceptions -fno-rtti")
+    # save intermediate files
+    # add_definitions(-save-temps)
 
     # for libary linking
     set(BEGIN_WHOLE_ARCHIVE -Wl,--whole-archive)
@@ -292,8 +294,7 @@ endif(MSVC)
 # ----------------------------------------------------------------------------
 # Share library option
 # ----------------------------------------------------------------------------
-option(ENABLE_STATIC "Build shared library" ON)
-option(ENABLE_SHARED "Build shared library" OFF)
+option(BUILD_SHARED_LIBS "Build shared library" ON)
 
 # ----------------------------------------------------------------------------
 # scan all LOG_TAG for log information and generate module header file
diff --git a/build/android/env_setup.sh b/build/android/env_setup.sh
index a30eb6b9f..0028c79b0 100755
--- a/build/android/env_setup.sh
+++ b/build/android/env_setup.sh
@@ -170,7 +170,8 @@ case ${NDK_COUNT} in
         echo "use ndk: ${ANDROID_NDK}"
         ;;
     *)
-        read -p "select [1-${NDK_COUNT}] ndk used for compiling: " -ra NDK_INTPUT
+        read -p "select [1-${NDK_COUNT}] ndk used for compiling, def[1]: " -ra NDK_INTPUT
+        NDK_INTPUT=${NDK_INTPUT:-1}
 
         NDK_INDEX=0
 
@@ -178,7 +179,7 @@ case ${NDK_COUNT} in
         do
             NDK_INDEX=$[${NDK_INDEX}+1]
 
-            if [ "${NDK_INDEX}" -eq "${NDK_INTPUT}" ]; then
+            if [ "${NDK_INDEX}" == "${NDK_INTPUT}" ]; then
                 echo "${NDK_INTPUT} - ${NDK_PATH} selected as ANDROID_NDK"
                 ANDROID_NDK=${NDK_PATH}
                 FOUND_NDK=1
diff --git a/debian/compat b/debian/compat
index ec635144f..f599e28b8 100644
--- a/debian/compat
+++ b/debian/compat
@@ -1 +1 @@
-9
+10
diff --git a/debian/control b/debian/control
index 4a1e30b7f..08771ae0c 100644
--- a/debian/control
+++ b/debian/control
@@ -1,7 +1,7 @@
 Source: mpp
 Priority: optional
 Maintainer: Randy Li <randy.li@rock-chips.com>
-Build-Depends: debhelper (>= 9), cmake
+Build-Depends: debhelper (>= 10), cmake, dh-exec
 Standards-Version: 3.9.5
 Section: libs
 Homepage: http://www.rock-chips.com
diff --git a/doc/Rockchip_Developer_Guide_MPP_CN.md b/doc/Rockchip_Developer_Guide_MPP_CN.md
index b3a00d1f5..df9adda92 100644
--- a/doc/Rockchip_Developer_Guide_MPP_CN.md
+++ b/doc/Rockchip_Developer_Guide_MPP_CN.md
@@ -613,12 +613,12 @@ MPP_RET mpp_enc_cfg_get_st(MppEncCfg cfg, const char *name, void *val);
 | rc:bps_target           | S32  | RK_S32                              | 表示CBR模式下的目标码率。                                    |
 | rc:bps_max              | S32  | RK_S32                              | 表示VBR/AVBR模式下的最高码率。                               |
 | rc:bps_min              | S32  | RK_S32                              | 表示VBR/AVBR模式下的最低码率。                               |
-| rc:fps_in_flex          | S32  | RK_S32                              | 表示输入帧率是否可变的标志位，默认为0。 为0表示输入帧率固定，帧率计算方式为： fps_in_num / fps_in_denorm，可以表示分数帧率。 为1表示输入帧率可变。可变帧率的情况下，帧率不固定，对应的码率计算与分配的规则变为按实际时间进行计算。 |
+| rc:fps_in_flex          | S32  | RK_S32                              | 表示输入帧率是否可变的标志位，默认为0。 为0表示输入帧率固定，帧率计算方式为： fps_in_num / fps_in_denom，可以表示分数帧率。 为1表示输入帧率可变。可变帧率的情况下，帧率不固定，对应的码率计算与分配的规则变为按实际时间进行计算。 |
 | rc:fps_in_num           | S32  | RK_S32                              | 表示输入帧率分数值的分子部分，默认值为30。                   |
-| rc:fps_in_denorm        | S32  | RK_S32                              | 表示输入帧率分数值的分母部分，默认值为1。                    |
-| rc:fps_out_flex         | S32  | RK_S32                              | 表示输出帧率是否可变的标志位，默认为0。 为0表示输出帧率固定，帧率计算方式为： fps_out_num / fps_out_denorm，可以表示分数帧率。 为1表示输出帧率可变。可变帧率的情况下，帧率不固定，对应的码流输出时间按实际时间进行计算。 |
+| rc:fps_in_denom         | S32  | RK_S32                              | 表示输入帧率分数值的分母部分，默认值为1。                    |
+| rc:fps_out_flex         | S32  | RK_S32                              | 表示输出帧率是否可变的标志位，默认为0。 为0表示输出帧率固定，帧率计算方式为： fps_out_num / fps_out_denom，可以表示分数帧率。 为1表示输出帧率可变。可变帧率的情况下，帧率不固定，对应的码流输出时间按实际时间进行计算。 |
 | rc:fps_out_num          | S32  | RK_S32                              | 表示输出帧率分数值的分子部分，默认值为30。                   |
-| rc:fps_out_denorm       | S32  | RK_S32                              | 表示输出帧率分数值的分母部分，默认值为1。                    |
+| rc:fps_out_denom        | S32  | RK_S32                              | 表示输出帧率分数值的分母部分，默认值为1。                    |
 | rc:gop                  | S32  | RK_S32                              | 表示Group Of Picture，即两个I帧之间的间隔，含义如下： 0 – 表示只有一个I帧，其他帧均为P帧。 1 – 表示全为I帧。 2 – 表示序列为I P I P I P… 3 – 表示序列为I P P I P P I P P… 一般情况下，gop应配置为输出帧率的整数倍，默认值为两倍输出帧率。 |
 | rc:max_reenc_times      | U32  | RK_U32                              | 表示一帧图像最大重编码次数，默认值为1。在低延时输出模式下，max_reenc_times只能配置为0。 |
 | rc:priority             | U32  | MppEncRcPriority                    | 表示超大帧重编优先级。 0 – 表示目标码率优先。 1 – 表示超大帧阈值优先。 此优先级只在超大帧重编时有效。 ![](media/Rockchip_Developer_Guide_MPP/MPP_MppEncRcPriority.png) |
diff --git a/doc/Rockchip_Developer_Guide_MPP_EN.md b/doc/Rockchip_Developer_Guide_MPP_EN.md
index 590bedb04..a66540eed 100644
--- a/doc/Rockchip_Developer_Guide_MPP_EN.md
+++ b/doc/Rockchip_Developer_Guide_MPP_EN.md
@@ -584,13 +584,13 @@ The character string is generally defined by \[type:parameter\]. The supported c
 |rc:bps_target|S32|RK_S32|Indicates the target code rate in CBR mode.|
 |rc:bps_max|S32|RK_S32|Indicates the highest bit rate in VBR mode.|
 |rc:bps_min|S32|RK_S32|Indicates the lowest bit rate in VBR mode.|
-|rc:fps_in_flex|S32|RK_S32|Flag bit indicating whether the input frame rate is variable. The default is 0.<br>0 means that the input frame rate is fixed, and the frame rate calculation method is fps_in_num/fps_in_denorm, which can indicate the fractional frame rate.<br>1 means that the input frame rate is variable. In the case of a variable frame rate, the frame rate is not fixed, and the corresponding code rate calculation and allocation rules become calculated according to actual time.|
-|rc:fps_in_flex|S32|RK_S32|Flag bit indicating whether the input frame rate is variable. The default is 0.<br>0 means that the input frame rate is fixed, and the frame rate calculation method is fps_in_num/fps_in_denorm, which can indicate the fractional frame rate.<br>1 means that the input frame rate is variable. In the case of a variable frame rate, the frame rate is not fixed, and the corresponding code rate calculation and allocation rules become calculated according to actual time.|
+|rc:fps_in_flex|S32|RK_S32|Flag bit indicating whether the input frame rate is variable. The default is 0.<br>0 means that the input frame rate is fixed, and the frame rate calculation method is fps_in_num/fps_in_denom, which can indicate the fractional frame rate.<br>1 means that the input frame rate is variable. In the case of a variable frame rate, the frame rate is not fixed, and the corresponding code rate calculation and allocation rules become calculated according to actual time.|
+|rc:fps_in_flex|S32|RK_S32|Flag bit indicating whether the input frame rate is variable. The default is 0.<br>0 means that the input frame rate is fixed, and the frame rate calculation method is fps_in_num/fps_in_denom, which can indicate the fractional frame rate.<br>1 means that the input frame rate is variable. In the case of a variable frame rate, the frame rate is not fixed, and the corresponding code rate calculation and allocation rules become calculated according to actual time.|
 |rc:fps_in_num|S32|RK_S32|Indicates the numerator part of the input frame rate score value, for example, 0 means the default 30fps.|
-|rc:fps_in_denorm|S32|RK_S32|Indicates the denominator part of the input frame rate fraction value. If 0 is 1|
-|rc:fps_out_flex|S32|RK_S32|Flag indicating whether the output frame rate is variable. The default is 0.<br>0 means that the output frame rate is fixed, and the frame rate calculation method is fps_out_num/fps_out_denorm, which can indicate the fractional frame rate.<br>1 means that the output frame rate is variable. In the case of variable frame rate, the frame rate is not fixed, and the corresponding code stream output time is calculated according to the actual time.|
+|rc:fps_in_denom|S32|RK_S32|Indicates the denominator part of the input frame rate fraction value. If 0 is 1|
+|rc:fps_out_flex|S32|RK_S32|Flag indicating whether the output frame rate is variable. The default is 0.<br>0 means that the output frame rate is fixed, and the frame rate calculation method is fps_out_num/fps_out_denom, which can indicate the fractional frame rate.<br>1 means that the output frame rate is variable. In the case of variable frame rate, the frame rate is not fixed, and the corresponding code stream output time is calculated according to the actual time.|
 |rc:fps_out_num|S32|RK_S32|Indicates the numerator part of the output frame rate score, such as 0 means the default 30fps.|
-|rc:fps_out_denorm|S32|RK_S32|Indicates the denominator part of the output frame rate score value. If 0 is 1|
+|rc:fps_out_denom|S32|RK_S32|Indicates the denominator part of the output frame rate score value. If 0 is 1|
 |rc:gop||RK_S32|Indicates Group Of Picture, that is, the interval between two I frames, the meaning is as follows.<br>0-indicates that there is only one I frame, other frames are P frames<br>1-means all I frames<br>2-means the sequence is I P I P I P...<br>3-means the sequence is I P P I P P I P P...<br>In general, gop is selected as an integer multiple of the input frame rate.|
 |rc:max_reenc_times|U32|RK_U32|The maximum recoding times of a frame of image.|
 |prep:width|S32|RK_S32|Indicates the number of pixels in the horizontal direction of the input image, in units of pixels.|
diff --git a/inc/mpp_buffer.h b/inc/mpp_buffer.h
index 9c5164781..bac52c08f 100644
--- a/inc/mpp_buffer.h
+++ b/inc/mpp_buffer.h
@@ -120,6 +120,10 @@ typedef enum {
  * ion      : use ion device under Android/Linux, MppBuffer will encapsulte ion file handle
  * ext_dma  : the DMABUF(DMA buffers) come from the application
  * drm      : use the drm device interface for memory management
+ *
+ * MPP default allocator select priority for kernel above 5.10:
+ * MPP_BUFFER_TYPE_DMA_HEAP > MPP_BUFFER_TYPE_DRM > MPP_BUFFER_TYPE_ION
+ * MPP_BUFFER_TYPE_EXT_DMA is only used for general external dma_buf fd import.
  */
 typedef enum {
     MPP_BUFFER_TYPE_NORMAL,
@@ -137,10 +141,10 @@ typedef enum {
  * 16 high bits of MppBufferType are used in flags
  *
  * eg:
- * DRM CMA buffer : MPP_BUFFER_TYPE_DRM | MPP_BUFFER_FLAGS_CONTIG
- *                  = 0x00010003
- * DRM SECURE buffer: MPP_BUFFER_TYPE_DRM | MPP_BUFFER_FLAGS_SECURE
- *                  = 0x00080003
+ * DMA_HEAP CMA buffer  : MPP_BUFFER_TYPE_DMA_HEAP | MPP_BUFFER_FLAGS_CONTIG
+ *                      = 0x00010004
+ * DRM SECURE buffer    : MPP_BUFFER_TYPE_DRM | MPP_BUFFER_FLAGS_SECURE
+ *                      = 0x00080003
  *
  * The dma buffer source can also be set by format: flags | type.
  * dma buffer source flags:
diff --git a/inc/mpp_frame.h b/inc/mpp_frame.h
index 42687693c..965a8e184 100644
--- a/inc/mpp_frame.h
+++ b/inc/mpp_frame.h
@@ -1,17 +1,6 @@
+/* SPDX-License-Identifier: Apache-2.0 OR MIT */
 /*
- * Copyright 2015 Rockchip Electronics Co. LTD
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *      http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * Copyright (c) 2015 Rockchip Electronics Co., Ltd.
  */
 
 #ifndef __MPP_FRAME_H__
@@ -56,6 +45,12 @@ typedef enum {
     MPP_FRAME_RANGE_NB,                 ///< Not part of ABI
 } MppFrameColorRange;
 
+typedef enum {
+    MPP_FRAME_CHROMA_DOWN_SAMPLE_MODE_NONE,
+    MPP_FRAME_CHORMA_DOWN_SAMPLE_MODE_AVERAGE,
+    MPP_FRAME_CHORMA_DOWN_SAMPLE_MODE_DISCARD,
+} MppFrameChromaDownSampleMode;
+
 typedef enum {
     MPP_FRAME_VIDEO_FMT_COMPONEMT   = 0,
     MPP_FRAME_VIDEO_FMT_PAL         = 1,
@@ -163,6 +158,33 @@ typedef enum {
     MPP_CHROMA_LOC_NB,                  ///< Not part of ABI
 } MppFrameChromaLocation;
 
+typedef enum {
+    MPP_CHROMA_UNSPECIFIED,
+    MPP_CHROMA_400,
+    MPP_CHROMA_410,
+    MPP_CHROMA_411,
+    MPP_CHROMA_420,
+    MPP_CHROMA_422,
+    MPP_CHROMA_440,
+    MPP_CHROMA_444,
+} MppFrameChromaFormat;
+
+/*
+ * MppFrameFormat bit flag:
+ *
+ *  +-----------------------------------------------+
+ *  | 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 |
+ *  +-----------------------------------------------+
+ *  bit  0 ~ 15: YUV / RGB format value
+ *  bit 16 ~ 19: YUV / RGB flag    0 - YUV; 1 - RGB;
+ *  bit 20 ~ 23: Frame Buffer Compression (FBC) flag, 0 - No FBC; 1 - FBCv1; 2 - FBCv2;
+ *  bit 24     : Big / little end flag,               0 - big end; 1 - little end;
+ *  bit 25     : Tile format flag,                    0 - No tile; 1 - tile format;
+ *  bit 26 ~ 27: High Dynamic Range (HDR) flag,       0 - Standard Dynamic Range (SDR); 1 - HDR;
+ *
+ *  NOTE: FBC format and tile format can not exist at the same time.
+ */
+
 #define MPP_FRAME_FMT_MASK          (0x000fffff)
 #define MPP_FRAME_FMT_PROP_MASK     (0x0ff00000)
 
@@ -177,6 +199,8 @@ typedef enum {
 #define MPP_FRAME_HDR_NONE          (0x00000000)
 #define MPP_FRAME_HDR               (0x04000000)
 
+#define MPP_FRAME_TILE_FLAG         (0x02000000)
+
 /*
  * AFBC_V1 is for ISP output.
  * It has default payload offset to be calculated * from width and height:
@@ -209,6 +233,8 @@ typedef enum {
 #define MPP_FRAME_FMT_IS_LE(fmt)    ((fmt & MPP_FRAME_FMT_LE_MASK) == MPP_FRAME_FMT_LE_MASK)
 #define MPP_FRAME_FMT_IS_BE(fmt)    ((fmt & MPP_FRAME_FMT_LE_MASK) == 0)
 
+#define MPP_FRAME_FMT_IS_TILE(fmt)  (fmt & MPP_FRAME_TILE_FLAG)
+
 /* mpp color format index definition */
 typedef enum {
     MPP_FMT_YUV420SP        = (MPP_FRAME_FMT_YUV + 0),  /* YYYY... UV... (NV12)     */
@@ -232,6 +258,7 @@ typedef enum {
     MPP_FMT_YUV411SP        = (MPP_FRAME_FMT_YUV + 14), /* YYYY... UV...            */
     MPP_FMT_YUV444SP        = (MPP_FRAME_FMT_YUV + 15), /* YYYY... UVUVUVUV...      */
     MPP_FMT_YUV444P         = (MPP_FRAME_FMT_YUV + 16), /* YYYY... UUUU... VVVV...  */
+    MPP_FMT_YUV444SP_10BIT  = (MPP_FRAME_FMT_YUV + 17),
     MPP_FMT_YUV_BUTT,
 
     MPP_FMT_RGB565          = (MPP_FRAME_FMT_RGB + 0),  /* 16-bit RGB               */
@@ -303,6 +330,12 @@ typedef enum MppFrameError {
     MPP_FRAME_ERR_DEC_MISS_REF     = 0x0200,
 } MppFrameError;
 
+typedef enum {
+    MPP_FRAME_THUMBNAIL_NONE,
+    MPP_FRAME_THUMBNAIL_MIXED,
+    MPP_FRAME_THUMBNAIL_ONLY,
+} MppFrameThumbnailMode;
+
 #ifdef __cplusplus
 extern "C" {
 #endif
diff --git a/inc/mpp_meta.h b/inc/mpp_meta.h
index b03355155..b66c239b8 100644
--- a/inc/mpp_meta.h
+++ b/inc/mpp_meta.h
@@ -80,6 +80,7 @@ typedef enum MppMetaKey_e {
     KEY_LONG_REF_IDX            = FOURCC_META('l', 't', 'i', 'd'),
     KEY_ENC_AVERAGE_QP          = FOURCC_META('a', 'v', 'g', 'q'),
     KEY_ENC_START_QP            = FOURCC_META('s', 't', 'r', 'q'),
+    KEY_ENC_BPS_RT              = FOURCC_META('r', 't', 'b', 'r'),   /* realtime bps */
     KEY_ROI_DATA                = FOURCC_META('r', 'o', 'i', ' '),
     KEY_OSD_DATA                = FOURCC_META('o', 's', 'd', ' '),
     KEY_OSD_DATA2               = FOURCC_META('o', 's', 'd', '2'),
@@ -98,6 +99,8 @@ typedef enum MppMetaKey_e {
     KEY_LVL4_INTRA_NUM          = FOURCC_META('l', '4', 'i', ' '),
     /* output P skip frame indicator */
     KEY_OUTPUT_PSKIP            = FOURCC_META('o', 'p', 's', 'p'),
+    /* input P skip frame request */
+    KEY_INPUT_PSKIP             = FOURCC_META('i', 'p', 's', 'p'),
     KEY_ENC_SSE                 = FOURCC_META('e', 's', 's', 'e'),
 
     /*
diff --git a/inc/mpp_rc_api.h b/inc/mpp_rc_api.h
index eedad341d..7e167a9aa 100644
--- a/inc/mpp_rc_api.h
+++ b/inc/mpp_rc_api.h
@@ -50,6 +50,7 @@ typedef enum RcMode_e {
     RC_CBR,
     RC_FIXQP,
     RC_AVBR,
+    RC_SMT,
     RC_CVBR,
     RC_QVBR,
     RC_LEARNING,
@@ -71,8 +72,8 @@ typedef enum GopMode_e {
  * fps_in_num
  * input frame rate numerator, if 0 then default 30
  *
- * fps_in_denorm
- * input frame rate denorminator, if 0 then default 1
+ * fps_in_denom
+ * input frame rate denominator, if 0 then default 1
  *
  * fps_out_flex
  * 0 - fix output frame rate
@@ -81,16 +82,16 @@ typedef enum GopMode_e {
  * fps_out_num
  * output frame rate numerator, if 0 then default 30
  *
- * fps_out_denorm
- * output frame rate denorminator, if 0 then default 1
+ * fps_out_denom
+ * output frame rate denominator, if 0 then default 1
  */
 typedef struct RcFpsCfg_t {
     RK_S32      fps_in_flex;
     RK_S32      fps_in_num;
-    RK_S32      fps_in_denorm;
+    RK_S32      fps_in_denom;
     RK_S32      fps_out_flex;
     RK_S32      fps_out_num;
-    RK_S32      fps_out_denorm;
+    RK_S32      fps_out_denom;
 } RcFpsCfg;
 
 typedef struct RcSuperframeCfg_t {
@@ -186,6 +187,8 @@ typedef struct RcCfg_s {
     RK_U32          refresh_len;
     RK_S32          scene_mode;
     RK_U32          fps_chg_prop;
+
+    RK_S32          rc_container;
 } RcCfg;
 
 /*
diff --git a/inc/mpp_rc_defs.h b/inc/mpp_rc_defs.h
index e8cb5b525..c5643f2db 100644
--- a/inc/mpp_rc_defs.h
+++ b/inc/mpp_rc_defs.h
@@ -184,6 +184,7 @@ typedef struct EncRcCommonInfo_t {
 
     /* rc to hal */
     RK_S32          bit_target;
+    RK_S32          bit_target_fix;
     RK_S32          bit_max;
     RK_S32          bit_min;
 
@@ -209,7 +210,16 @@ typedef struct EncRcCommonInfo_t {
     RK_U32          lvl8_intra_num;
     RK_U32          lvl4_intra_num;
 
-    RK_S32          reserve[5];
+    RK_U32          motion_level;
+    RK_U32          complex_level;
+    RK_S32          complex_scene;
+    RK_S32          scene_mode;
+    RK_S32          last_scene_mode;
+
+    /* rc stats info: real time bits */
+    RK_S32          rt_bits;
+
+    RK_S32          reserve[4];
 } EncRcTaskInfo;
 
 typedef struct EncRcTask_s {
diff --git a/inc/rk_hdr_meta_com.h b/inc/rk_hdr_meta_com.h
index 3f466386f..02ed8fff3 100644
--- a/inc/rk_hdr_meta_com.h
+++ b/inc/rk_hdr_meta_com.h
@@ -20,11 +20,11 @@
 #include "rk_type.h"
 
 typedef enum HdrCodecType_e {
-    HDR_AVS2 = 0,
-    HDR_HEVC = 1,
-    HDR_H264 = 2,
-    HDR_AV1  = 3,
-    HDR_CODEC_BUT,
+    HDR_CODEC_UNSPECIFIED = -1,
+    HDR_AVS2              = 0,
+    HDR_HEVC              = 1,
+    HDR_H264              = 2,
+    HDR_AV1               = 3,
 } HdrCodecType;
 
 typedef enum HdrFormat_e {
@@ -113,6 +113,14 @@ typedef struct RkMetaHdrHeader_t {
     RK_U32  payload[];
 } RkMetaHdrHeader;
 
-void fill_hdr_meta_to_frame(MppFrame frame, HdrCodecType codec_type);
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+void fill_hdr_meta_to_frame(MppFrame frame, MppCodingType in_type);
+
+#ifdef __cplusplus
+}
+#endif
 
 #endif
diff --git a/inc/rk_mpi_cmd.h b/inc/rk_mpi_cmd.h
index 391df8e59..7f7811a8d 100644
--- a/inc/rk_mpi_cmd.h
+++ b/inc/rk_mpi_cmd.h
@@ -106,6 +106,8 @@ typedef enum {
     MPP_DEC_SET_DISABLE_THREAD,         /* MPP no thread mode and use external thread to decode */
     MPP_DEC_SET_MAX_USE_BUFFER_SIZE,
     MPP_DEC_SET_ENABLE_MVC,             /* enable MVC decoding*/
+    MPP_DEC_GET_THUMBNAIL_FRAME_INFO,   /* update thumbnail frame info to user, for MPP_FRAME_THUMBNAIL_ONLY mode */
+    MPP_DEC_SET_DISABLE_DPB_CHECK,      /* disable dpb discontinuous check */
 
     MPP_DEC_CMD_QUERY                   = CMD_MODULE_CODEC | CMD_CTX_ID_DEC | CMD_DEC_QUERY,
     /* query decoder runtime information for decode stage */
diff --git a/inc/rk_venc_cmd.h b/inc/rk_venc_cmd.h
index 9f5fe2ffd..faeae3997 100644
--- a/inc/rk_venc_cmd.h
+++ b/inc/rk_venc_cmd.h
@@ -213,8 +213,8 @@ typedef enum MppEncRcCfgChange_e {
     MPP_ENC_RC_CFG_CHANGE_RC_MODE       = (1 << 0),
     MPP_ENC_RC_CFG_CHANGE_QUALITY       = (1 << 1),
     MPP_ENC_RC_CFG_CHANGE_BPS           = (1 << 2),     /* change on bps target / max / min */
-    MPP_ENC_RC_CFG_CHANGE_FPS_IN        = (1 << 5),     /* change on fps in  flex / numerator / denorminator */
-    MPP_ENC_RC_CFG_CHANGE_FPS_OUT       = (1 << 6),     /* change on fps out flex / numerator / denorminator */
+    MPP_ENC_RC_CFG_CHANGE_FPS_IN        = (1 << 5),     /* change on fps in  flex / numerator / denominator */
+    MPP_ENC_RC_CFG_CHANGE_FPS_OUT       = (1 << 6),     /* change on fps out flex / numerator / denominator */
     MPP_ENC_RC_CFG_CHANGE_GOP           = (1 << 7),
     MPP_ENC_RC_CFG_CHANGE_SKIP_CNT      = (1 << 8),
     MPP_ENC_RC_CFG_CHANGE_MAX_REENC     = (1 << 9),
@@ -239,6 +239,7 @@ typedef enum MppEncRcCfgChange_e {
     MPP_ENC_RC_CFG_CHANGE_REFRESH       = (1 << 27),
     MPP_ENC_RC_CFG_CHANGE_GOP_REF_CFG   = (1 << 28),
     MPP_ENC_RC_CFG_CHANGE_FQP           = (1 << 29),
+    MPP_ENC_RC_CFG_CHANGE_QPDD          = (1 << 30),
     MPP_ENC_RC_CFG_CHANGE_ALL           = (0xFFFFFFFF),
 } MppEncRcCfgChange;
 
@@ -312,8 +313,8 @@ typedef struct MppEncRcCfg_t {
      * fps_in_num
      * input frame rate numerator, if 0 then default 30
      *
-     * fps_in_denorm
-     * input frame rate denorminator, if 0 then default 1
+     * fps_in_denom
+     * input frame rate denominator, if 0 then default 1
      *
      * fps_out_flex
      * 0 - fix output frame rate
@@ -322,15 +323,15 @@ typedef struct MppEncRcCfg_t {
      * fps_out_num
      * output frame rate numerator, if 0 then default 30
      *
-     * fps_out_denorm
-     * output frame rate denorminator, if 0 then default 1
+     * fps_out_denom
+     * output frame rate denominator, if 0 then default 1
      */
     RK_S32  fps_in_flex;
     RK_S32  fps_in_num;
-    RK_S32  fps_in_denorm;
+    RK_S32  fps_in_denom;
     RK_S32  fps_out_flex;
     RK_S32  fps_out_num;
-    RK_S32  fps_out_denorm;
+    RK_S32  fps_out_denom;
 
     /*
      * gop - group of picture, gap between Intra frame
@@ -410,6 +411,7 @@ typedef struct MppEncRcCfg_t {
     RK_S32                  fqp_min_p;
     RK_S32                  fqp_max_i;
     RK_S32                  fqp_max_p;
+    RK_S32                  cu_qp_delta_depth;
 
     RK_S32                  hier_qp_en;
     RK_S32                  hier_qp_delta[4];
@@ -562,13 +564,19 @@ typedef struct MppEncPrepCfg_t {
     RK_S32              ver_stride;
 
     /*
-     * Mpp encoder input data format config
+     * Mpp encoder input/output color config
      */
     MppFrameFormat      format;
     MppFrameColorSpace  color;
     MppFrameColorPrimaries colorprim;
     MppFrameColorTransferCharacteristic colortrc;
     MppFrameColorRange  range;
+    MppFrameChromaFormat format_out;
+    MppFrameChromaDownSampleMode chroma_ds_mode;
+    MppFrameColorRange  range_out;
+    RK_S32              fix_chroma_en;
+    RK_S32              fix_chroma_u;
+    RK_S32              fix_chroma_v;
 
     /* suffix ext means the user set config externally */
     MppEncRotationCfg   rotation;
@@ -715,6 +723,8 @@ typedef struct MppEncH264HwCfg_t {
      * others   : changeable, default 12
      */
     RK_U32 hw_log2_max_frame_num_minus4;
+    /* default 0, only RKVENC2 support split out */
+    RK_U32 hw_split_out;
 } MppEncH264HwCfg;
 
 typedef struct MppEncH264Cfg_t {
@@ -981,6 +991,11 @@ typedef enum MppEncH265CfgChange_e {
     MPP_ENC_H265_CFG_TILE_CHANGE                = (1 << 22),
     MPP_ENC_H265_CFG_SLICE_LPFACS_CHANGE        = (1 << 23),
     MPP_ENC_H265_CFG_TILE_LPFACS_CHANGE         = (1 << 24),
+    MPP_ENC_H265_CFG_CHANGE_CONST_INTRA         = (1 << 25),
+    MPP_ENC_H265_CFG_CHANGE_LCU_SIZE            = (1 << 26),
+    MPP_ENC_H265_CFG_CHANGE_MAX_TID             = (1 << 27),
+    MPP_ENC_H265_CFG_CHANGE_MAX_LTR             = (1 << 28),
+    MPP_ENC_H265_CFG_CHANGE_BASE_LAYER_PID      = (1 << 29),
     MPP_ENC_H265_CFG_CHANGE_ALL                 = (0xFFFFFFFF),
 } MppEncH265CfgChange;
 
@@ -1086,6 +1101,11 @@ typedef struct MppEncH265Cfg_t {
     RK_S32              intra_refresh_mode;
     RK_S32              intra_refresh_arg;
 
+    /* extra mode config */
+    RK_S32              max_ltr_frames;
+    RK_S32              max_tid;
+    RK_S32              base_layer_pid;
+
     /* slice mode config */
     RK_S32              independ_slice_mode;
     RK_S32              independ_slice_arg;
@@ -1408,13 +1428,37 @@ typedef enum MppEncSceneMode_e {
 
 typedef enum MppEncFineTuneCfgChange_e {
     /* change on scene mode */
-    MPP_ENC_TUNE_CFG_CHANGE_SCENE_MODE      = (1 << 0),
+    MPP_ENC_TUNE_CFG_CHANGE_SCENE_MODE          = (1 << 0),
+    MPP_ENC_TUNE_CFG_CHANGE_DEBLUR_EN           = (1 << 1),
+    MPP_ENC_TUNE_CFG_CHANGE_DEBLUR_STR          = (1 << 2),
+    MPP_ENC_TUNE_CFG_CHANGE_ANTI_FLICKER_STR    = (1 << 3),
+    MPP_ENC_TUNE_CFG_CHANGE_LAMBDA_IDX_I        = (1 << 5),
+    MPP_ENC_TUNE_CFG_CHANGE_LAMBDA_IDX_P        = (1 << 6),
+    MPP_ENC_TUNE_CFG_CHANGE_ATR_STR_I           = (1 << 7),
+    MPP_ENC_TUNE_CFG_CHANGE_ATR_STR_P           = (1 << 8),
+    MPP_ENC_TUNE_CFG_CHANGE_ATL_STR             = (1 << 9),
+    MPP_ENC_TUNE_CFG_CHANGE_SAO_STR_I           = (1 << 10),
+    MPP_ENC_TUNE_CFG_CHANGE_SAO_STR_P           = (1 << 11),
+    MPP_ENC_TUNE_CFG_CHANGE_RC_CONTAINER        = (1 << 13),
+    MPP_ENC_TUNE_CFG_CHANGE_VMAF_OPT            = (1 << 14)
 } MppEncFineTuneCfgChange;
 
 typedef struct MppEncFineTuneCfg_t {
     RK_U32              change;
 
     MppEncSceneMode     scene_mode;
+    RK_S32              deblur_en; /* qpmap_en */
+    RK_S32              deblur_str; /* deblur strength */
+    RK_S32              anti_flicker_str;
+    RK_S32              lambda_idx_i;
+    RK_S32              lambda_idx_p;
+    RK_S32              atr_str_i; /* line_en */
+    RK_S32              atr_str_p; /* line_en */
+    RK_S32              atl_str; /* anti_stripe */
+    RK_S32              sao_str_i; /* anti blur */
+    RK_S32              sao_str_p; /* anti blur */
+    RK_S32              rc_container;
+    RK_S32              vmaf_opt;
 } MppEncFineTuneCfg;
 
 #endif /*__RK_VENC_CMD_H__*/
diff --git a/inc/rk_venc_rc.h b/inc/rk_venc_rc.h
index b03289c17..8321b0d91 100644
--- a/inc/rk_venc_rc.h
+++ b/inc/rk_venc_rc.h
@@ -28,6 +28,7 @@ typedef enum MppEncRcMode_e {
     MPP_ENC_RC_MODE_CBR,
     MPP_ENC_RC_MODE_FIXQP,
     MPP_ENC_RC_MODE_AVBR,
+    MPP_ENC_RC_MODE_SMTRC,
     MPP_ENC_RC_MODE_BUTT
 } MppEncRcMode;
 
diff --git a/inc/vpu_api.h b/inc/vpu_api.h
index 80c7a5993..c137d44ea 100644
--- a/inc/vpu_api.h
+++ b/inc/vpu_api.h
@@ -72,7 +72,8 @@ typedef enum {
     ENC_INPUT_RGB888 = 10,                    /**< 24-bit RGB           */
     ENC_INPUT_BGR888 = 11,                    /**< 24-bit RGB           */
     ENC_INPUT_RGB101010 = 12,                 /**< 30-bit RGB           */
-    ENC_INPUT_BGR101010 = 13                  /**< 30-bit RGB           */
+    ENC_INPUT_BGR101010 = 13,                 /**< 30-bit RGB           */
+    ENC_INPUT_YUV420_SEMIPLANAR_VU = 0X100    /**< YYYY... VUVUVUVU...  */
 } EncInputPictureType;
 
 typedef enum VPU_API_CMD {
@@ -105,6 +106,7 @@ typedef enum VPU_API_CMD {
     VPU_API_DEC_EN_MVC,
     VPU_API_DEC_EN_FBC_HDR_256_ODD,
     VPU_API_SET_INPUT_BLOCK,
+    VPU_API_SET_DISABLE_ERROR,
 
     /* set pkt/frm ready callback */
     VPU_API_SET_PKT_RDY_CB = 0x1100,
diff --git a/merge_static_lib.sh b/merge_static_lib.sh
new file mode 100755
index 000000000..fe252f6ff
--- /dev/null
+++ b/merge_static_lib.sh
@@ -0,0 +1,10 @@
+#!/bin/bash
+
+cd $1
+rm -rf mpp/lib'$2$'.a
+
+SCRIPT=$'CREATE mpp/lib'$2$'.a\n'
+SCRIPT=$SCRIPT$(find . -name '*.a' -exec echo 'ADDLIB {}' \;)
+SCRIPT=$SCRIPT$'\nSAVE\nEND\n'
+
+ar -M <<< $SCRIPT
\ No newline at end of file
diff --git a/mpp/CMakeLists.txt b/mpp/CMakeLists.txt
index a6df6aef3..fad59b135 100644
--- a/mpp/CMakeLists.txt
+++ b/mpp/CMakeLists.txt
@@ -50,10 +50,7 @@ set(MPP_VERSION "0")
 set(MPP_ABI_VERSION "1")
 
 add_library(${MPP_SHARED} SHARED ${MPP_SRC})
-set_target_properties(${MPP_SHARED} PROPERTIES FOLDER "mpp")
-set_target_properties(${MPP_SHARED} PROPERTIES CLEAN_DIRECT_OUTPUT 1)
-target_link_libraries(${MPP_SHARED} mpp_codec mpp_hal mpp_vproc ${ASAN_LIB}
-                      ${BEGIN_WHOLE_ARCHIVE} mpp_base ${END_WHOLE_ARCHIVE})
+target_link_libraries(${MPP_SHARED} ${ASAN_LIB})
 set_target_properties(${MPP_SHARED} PROPERTIES C_VISIBILITY_PRESET default)
 set_target_properties(${MPP_SHARED} PROPERTIES CXX_VISIBILITY_PRESET default)
 
@@ -63,7 +60,29 @@ set_target_properties(${MPP_SHARED} PROPERTIES VERSION ${MPP_VERSION})
 set_target_properties(${MPP_SHARED} PROPERTIES SOVERSION ${MPP_ABI_VERSION})
 endif()
 
+set_target_properties(${MPP_SHARED} PROPERTIES FOLDER "mpp")
+set_target_properties(${MPP_SHARED} PROPERTIES CLEAN_DIRECT_OUTPUT 1)
+target_link_libraries(${MPP_SHARED} mpp_codec mpp_hal mpp_vproc
+                      ${BEGIN_WHOLE_ARCHIVE} mpp_base ${END_WHOLE_ARCHIVE})
+
+# build static library
+add_library(${MPP_STATIC} STATIC ${MPP_SRC})
+set_target_properties(${MPP_STATIC} PROPERTIES FOLDER "mpp" OUTPUT_NAME "${MPP_SHARED}")
+set_target_properties(${MPP_STATIC} PROPERTIES CLEAN_DIRECT_OUTPUT 1)
+target_link_libraries(${MPP_STATIC} mpp_codec mpp_hal mpp_vproc
+    ${BEGIN_WHOLE_ARCHIVE} mpp_base ${END_WHOLE_ARCHIVE})
+
+add_custom_command(TARGET ${MPP_STATIC} POST_BUILD
+    COMMAND ${CMAKE_AR} x $<TARGET_FILE:${MPP_STATIC}>
+    COMMAND ${CMAKE_AR} x $<TARGET_FILE:osal>
+    COMMAND ${CMAKE_AR} x $<TARGET_FILE:mpp_base>
+    COMMAND ${CMAKE_AR} rcs lib${MPP_SHARED}.a *.o
+    COMMAND ${CMAKE_STRIP} --strip-debug lib${MPP_SHARED}.a
+    COMMAND pwd
+    COMMAND rm *.o
+    )
 
 add_subdirectory(legacy)
 
 install(TARGETS ${MPP_SHARED} LIBRARY DESTINATION "${CMAKE_INSTALL_LIBDIR}")
+install(TARGETS ${MPP_STATIC} ARCHIVE DESTINATION "${CMAKE_INSTALL_LIBDIR}")
diff --git a/mpp/base/inc/mpp_buffer_impl.h b/mpp/base/inc/mpp_buffer_impl.h
index 98fdf8158..aa8e806eb 100644
--- a/mpp/base/inc/mpp_buffer_impl.h
+++ b/mpp/base/inc/mpp_buffer_impl.h
@@ -21,6 +21,7 @@
 #include "mpp_hash.h"
 #include "mpp_common.h"
 #include "mpp_allocator.h"
+#include "mpp_device.h"
 
 #define MPP_BUF_DBG_FUNCTION            (0x00000001)
 #define MPP_BUF_DBG_OPS_RUNTIME         (0x00000002)
@@ -111,6 +112,11 @@ struct MppBufferImpl_t {
     RK_U32              used;
     RK_S32              ref_count;
     struct list_head    list_status;
+
+    /*
+     * mpp_device map for attach / detach operation
+     */
+    struct list_head    list_maps;
 };
 
 struct MppBufferGroupImpl_t {
@@ -201,6 +207,13 @@ MPP_RET mpp_buffer_ref_inc(MppBufferImpl *buffer, const char* caller);
 MPP_RET mpp_buffer_ref_dec(MppBufferImpl *buffer, const char* caller);
 MppBufferImpl *mpp_buffer_get_unused(MppBufferGroupImpl *p, size_t size, const char* caller);
 RK_U32  mpp_buffer_to_addr(MppBuffer buffer, size_t offset);
+MPP_RET mpp_buffer_attach_dev_f(const char *caller, MppBuffer buffer, MppDev dev);
+MPP_RET mpp_buffer_detach_dev_f(const char *caller, MppBuffer buffer, MppDev dev);
+RK_U32  mpp_buffer_get_iova_f(const char *caller, MppBuffer buffer, MppDev dev);
+
+#define mpp_buffer_attach_dev(buf, dev) mpp_buffer_attach_dev_f(__FUNCTION__, buf, dev)
+#define mpp_buffer_detach_dev(buf, dev) mpp_buffer_detach_dev_f(__FUNCTION__, buf, dev)
+#define mpp_buffer_get_iova(buf, dev)   mpp_buffer_get_iova_f(__FUNCTION__, buf, dev)
 
 MPP_RET mpp_buffer_group_init(MppBufferGroupImpl **group, const char *tag, const char *caller, MppBufferMode mode, MppBufferType type);
 MPP_RET mpp_buffer_group_deinit(MppBufferGroupImpl *p);
diff --git a/mpp/base/inc/mpp_enc_ref.h b/mpp/base/inc/mpp_enc_ref.h
index 6c0b3978c..89e0e5367 100644
--- a/mpp/base/inc/mpp_enc_ref.h
+++ b/mpp/base/inc/mpp_enc_ref.h
@@ -45,6 +45,7 @@ typedef struct MppEncRefCfgImpl_t {
     RK_S32              max_st_cfg;
     RK_S32              lt_cfg_cnt;
     RK_S32              st_cfg_cnt;
+    RK_S32              max_tlayers;
     MppEncRefLtFrmCfg   *lt_cfg;
     MppEncRefStFrmCfg   *st_cfg;
 
diff --git a/mpp/base/inc/mpp_trie.h b/mpp/base/inc/mpp_trie.h
index 63b2a09b4..90b8cc3ff 100644
--- a/mpp/base/inc/mpp_trie.h
+++ b/mpp/base/inc/mpp_trie.h
@@ -22,29 +22,56 @@
 
 typedef void* MppTrie;
 
-/* spatial optimized tire tree */
-typedef struct MppAcNode_t {
-    RK_S16          next[16];
-    /* idx - tire node index in ascending order */
-    RK_S32          idx;
-    /* id  - tire node carried payload data */
-    RK_S32          id;
-} MppTrieNode;
+#define MPP_TRIE_KEY_LEN                (4)
+#define MPP_TRIE_KEY_MAX                (1 << (MPP_TRIE_KEY_LEN))
+
+/*
+ * MppTrie node buffer layout
+ * +---------------+
+ * |  MppTrieImpl  |
+ * +---------------+
+ * |  MppTrieNodes |
+ * +---------------+
+ * |  MppTrieInfos |
+ * +---------------+
+ *
+ * MppTrieInfo element layout
+ * +---------------+
+ * |  MppTrieInfo  |
+ * +---------------+
+ * |  User context |
+ * +---------------+
+ * |  name string  |
+ * +---------------+
+ */
+typedef struct MppTrieInfo_t {
+    const char  *name;
+    void        *ctx;
+    RK_S16      index;
+    RK_S16      str_len;
+} MppTrieInfo;
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-MPP_RET mpp_trie_init(MppTrie *trie, RK_S32 node_count, RK_S32 info_count);
+MPP_RET mpp_trie_init(MppTrie *trie, RK_S32 info_size);
 MPP_RET mpp_trie_deinit(MppTrie trie);
 
-MPP_RET mpp_trie_add_info(MppTrie trie, const char **info);
+/* Add NULL info to mark the last trie entry */
+MPP_RET mpp_trie_add_info(MppTrie trie, const char *name, void *ctx);
+
 RK_S32 mpp_trie_get_node_count(MppTrie trie);
 RK_S32 mpp_trie_get_info_count(MppTrie trie);
+RK_S32 mpp_trie_get_buf_size(MppTrie trie);
+
+/* trie lookup function */
+MppTrieInfo *mpp_trie_get_info(MppTrie trie, const char *name);
+MppTrieInfo *mpp_trie_get_info_first(MppTrie trie);
+MppTrieInfo *mpp_trie_get_info_next(MppTrie trie, MppTrieInfo *info);
 
-MppTrieNode *mpp_trie_get_node(MppTrieNode *root, const char *name);
-const char **mpp_trie_get_info(MppTrie trie, const char *name);
-MppTrieNode *mpp_trie_node_root(MppTrie trie);
+void mpp_trie_dump(MppTrie trie, const char *func);
+#define mpp_trie_dump_f(trie)   mpp_trie_dump(trie, __FUNCTION__)
 
 #ifdef __cplusplus
 }
diff --git a/mpp/base/mpp_2str.c b/mpp/base/mpp_2str.c
index 635411b26..08df849c6 100644
--- a/mpp/base/mpp_2str.c
+++ b/mpp/base/mpp_2str.c
@@ -53,11 +53,13 @@ const char *strof_coding_type(MppCodingType coding)
         "h265",
         "avs+",
         "avs",
+        "avs2",
+        "av1",
     };
 
     if (coding >= MPP_VIDEO_CodingUnused && coding <= MPP_VIDEO_CodingVP9)
         return coding_type_str0[coding];
-    else if (coding >= MPP_VIDEO_CodingVC1 && coding <= MPP_VIDEO_CodingAVS)
+    else if (coding >= MPP_VIDEO_CodingVC1 && coding <= MPP_VIDEO_CodingAV1)
         return coding_type_str1[coding - MPP_VIDEO_CodingVC1];
 
     return NULL;
@@ -70,6 +72,7 @@ const char *strof_rc_mode(MppEncRcMode rc_mode)
         "cbr",
         "fixqp",
         "avbr",
+        "smtrc"
     };
 
     if (rc_mode >= MPP_ENC_RC_MODE_VBR && rc_mode < MPP_ENC_RC_MODE_BUTT)
diff --git a/mpp/base/mpp_bitput.c b/mpp/base/mpp_bitput.c
index 37896ceae..33a9539cb 100644
--- a/mpp/base/mpp_bitput.c
+++ b/mpp/base/mpp_bitput.c
@@ -46,6 +46,10 @@ void mpp_put_bits(BitputCtx_t *bp, RK_U64 invalue, RK_S32 lbits)
         bp->bvalue = invalue >> (64 - bp->bitpos);  // low bits value
         bp->index++;
     }
+
+    if (bp->index >= bp->buflen)
+        return;
+
     bp->pbuf[bp->index] = bp->bvalue;
     bp->bitpos = (bp->bitpos + lbits) & 63;
     // mpp_log("bp->index = %d bp->bitpos = %d lbits = %d invalue 0x%x bp->hvalue 0x%x  bp->lvalue 0x%x",bp->index,bp->bitpos,lbits, (RK_U32)invalue,(RK_U32)(bp->bvalue >> 32),(RK_U32)bp->bvalue);
diff --git a/mpp/base/mpp_bitread.c b/mpp/base/mpp_bitread.c
index e5ec1f8e0..1a4ccb343 100644
--- a/mpp/base/mpp_bitread.c
+++ b/mpp/base/mpp_bitread.c
@@ -311,8 +311,11 @@ RK_U32 mpp_has_more_rbsp_data(BitReadCtx_t *bitctx)
     // Last byte, look for stop bit;
     // We have more RBSP data if the last non-zero bit we find is not the
     // first available bit.
-    return (bitctx->curr_byte_ &
-            ((1 << (bitctx->num_remaining_bits_in_curr_byte_ - 1)) - 1)) != 0;
+    if (bitctx->num_remaining_bits_in_curr_byte_)
+        return (bitctx->curr_byte_ &
+                ((1 << (bitctx->num_remaining_bits_in_curr_byte_ - 1)) - 1)) != 0;
+    else
+        return 0;
 }
 /*!
 ***********************************************************************
diff --git a/mpp/base/mpp_buf_slot.cpp b/mpp/base/mpp_buf_slot.cpp
index f5e4eb0ee..4a48b880a 100644
--- a/mpp/base/mpp_buf_slot.cpp
+++ b/mpp/base/mpp_buf_slot.cpp
@@ -336,6 +336,9 @@ static void generate_info_set(MppBufSlotsImpl *impl, MppFrame frame, RK_U32 forc
         case MPP_FMT_YUV422SP : {
             size = get_afbc_min_size(hor_stride_pixel, hal_ver_stride, 16);
         } break;
+        case MPP_FMT_YUV444SP : {
+            size = get_afbc_min_size(hor_stride_pixel, hal_hor_stride, 24);
+        } break;
         default : {
             size = hal_hor_stride * hal_ver_stride * 3 / 2;
             mpp_err("dec out fmt is no support");
@@ -360,12 +363,37 @@ static void generate_info_set(MppBufSlotsImpl *impl, MppFrame frame, RK_U32 forc
     mpp_frame_set_ver_stride(frame, hal_ver_stride);
     mpp_frame_set_hor_stride_pixel(frame, hor_stride_pixel);
     impl->buf_size = size;
-    if (mpp_frame_get_thumbnail_en(frame)) {
+    if (mpp_frame_get_thumbnail_en(frame) == MPP_FRAME_THUMBNAIL_MIXED) {
         /*
          * The decode hw only support 1/2 scaling in width and height,
-         * so, an extra 1/4 buffer is expanded to store scaling data.
+         * downscale output image only support raster mode with 8bit depth.
          */
-        impl->buf_size += size / 4;
+        RK_U32 down_scale_ver = MPP_ALIGN(mpp_frame_get_height(frame) >> 1, 16);
+        RK_U32 down_scale_hor = MPP_ALIGN(mpp_frame_get_width(frame) >> 1, 16);
+        RK_U32 downscale_buf_size;
+        RK_U32 down_scale_y_virstride = down_scale_ver * down_scale_hor;
+
+        switch ((fmt & MPP_FRAME_FMT_MASK)) {
+        case MPP_FMT_YUV400 : {
+            downscale_buf_size = down_scale_y_virstride;
+        } break;
+        case MPP_FMT_YUV420SP_10BIT :
+        case MPP_FMT_YUV420SP : {
+            downscale_buf_size = down_scale_y_virstride * 3 / 2;
+        } break;
+        case MPP_FMT_YUV422SP_10BIT :
+        case MPP_FMT_YUV422SP : {
+            downscale_buf_size = down_scale_y_virstride * 2;
+        } break;
+        case MPP_FMT_YUV444SP : {
+            downscale_buf_size = down_scale_y_virstride * 3;
+        } break;
+        default : {
+            downscale_buf_size = down_scale_y_virstride * 3 / 2;
+        } break;
+        }
+        downscale_buf_size = MPP_ALIGN(downscale_buf_size, 16);
+        impl->buf_size += downscale_buf_size;
         mpp_frame_set_buf_size(impl->info_set, impl->buf_size);
         mpp_frame_set_buf_size(frame, impl->buf_size);
     }
diff --git a/mpp/base/mpp_buffer_impl.cpp b/mpp/base/mpp_buffer_impl.cpp
index a36e52e22..1fcab51a4 100644
--- a/mpp/base/mpp_buffer_impl.cpp
+++ b/mpp/base/mpp_buffer_impl.cpp
@@ -124,6 +124,7 @@ static const char *ops2str[BUF_OPS_BUTT] = {
 
 static MppMemPool mpp_buffer_pool = mpp_mem_pool_init_f(MODULE_TAG, sizeof(MppBufferImpl));
 static MppMemPool mpp_buf_grp_pool = mpp_mem_pool_init_f("mpp_buf_grp", sizeof(MppBufferGroupImpl));
+static MppMemPool mpp_buf_map_node_pool = mpp_mem_pool_init_f("mpp_buf_map_node", sizeof(MppDevBufMapNode));
 
 RK_U32 mpp_buffer_debug = 0;
 
@@ -232,15 +233,34 @@ static void buf_grp_add_log(MppBufferGroupImpl *group, MppBufOps ops, const char
         buf_logs_write(group->logs, group->group_id, -1, ops, 0, caller);
 }
 
+static void clear_buffer_info(MppBufferInfo *info)
+{
+    info->fd = -1;
+    info->ptr = NULL;
+    info->hnd = NULL;
+    info->size = 0;
+    info->index = -1;
+    info->type = MPP_BUFFER_TYPE_BUTT;
+}
+
 static MPP_RET put_buffer(MppBufferGroupImpl *group, MppBufferImpl *buffer,
                           RK_U32 reuse, const char *caller)
 {
+    struct list_head list_maps;
+    MppDevBufMapNode *pos, *n;
+    MppBufferInfo info;
+
     mpp_assert(group);
 
     pthread_mutex_lock(&buffer->lock);
 
-    if (!MppBufferService::get_instance()->is_finalizing())
+    if (!MppBufferService::get_instance()->is_finalizing()) {
         mpp_assert(buffer->ref_count == 0);
+        if (buffer->ref_count > 0) {
+            pthread_mutex_unlock(&buffer->lock);
+            return MPP_OK;
+        }
+    }
 
     list_del_init(&buffer->list_status);
 
@@ -259,13 +279,15 @@ static MPP_RET put_buffer(MppBufferGroupImpl *group, MppBufferImpl *buffer,
         return MPP_OK;
     }
 
-    /* release buffer here */
-    BufferOp func = (buffer->mode == MPP_BUFFER_INTERNAL) ?
-                    (buffer->alloc_api->free) :
-                    (buffer->alloc_api->release);
-
-    func(buffer->allocator, &buffer->info);
-
+    /* remove all map from buffer */
+    INIT_LIST_HEAD(&list_maps);
+    list_for_each_entry_safe(pos, n, &buffer->list_maps, MppDevBufMapNode, list_buf) {
+        list_move_tail(&pos->list_buf, &list_maps);
+        pos->iova = (RK_U32)(-1);
+    }
+    mpp_assert(list_empty(&buffer->list_maps));
+    info = buffer->info;
+    clear_buffer_info(&buffer->info);
     if (group) {
         RK_U32 destroy = 0;
 
@@ -290,8 +312,27 @@ static MPP_RET put_buffer(MppBufferGroupImpl *group, MppBufferImpl *buffer,
     } else {
         mpp_assert(MppBufferService::get_instance()->is_finalizing());
     }
+
     pthread_mutex_unlock(&buffer->lock);
 
+    list_for_each_entry_safe(pos, n, &list_maps, MppDevBufMapNode, list_buf) {
+        MppDev dev = pos->dev;
+
+        mpp_assert(dev);
+        mpp_dev_ioctl(dev, MPP_DEV_LOCK_MAP, NULL);
+        /* remove buffer from group */
+        mpp_dev_ioctl(dev, MPP_DEV_DETACH_FD, pos);
+        mpp_dev_ioctl(dev, MPP_DEV_UNLOCK_MAP, NULL);
+        mpp_mem_pool_put_f(caller, mpp_buf_map_node_pool, pos);
+    }
+
+    /* release buffer here */
+    BufferOp func = (buffer->mode == MPP_BUFFER_INTERNAL) ?
+                    (buffer->alloc_api->free) :
+                    (buffer->alloc_api->release);
+
+    func(buffer->allocator, &info);
+
     mpp_mem_pool_put_f(caller, mpp_buffer_pool, buffer);
 
     return MPP_OK;
@@ -407,6 +448,7 @@ MPP_RET mpp_buffer_create(const char *tag, const char *caller,
     pthread_mutex_lock(&group->buf_lock);
     p->buffer_id = group->buffer_id++;
     INIT_LIST_HEAD(&p->list_status);
+    INIT_LIST_HEAD(&p->list_maps);
 
     if (buffer) {
         p->ref_count++;
@@ -470,9 +512,8 @@ MPP_RET mpp_buffer_ref_dec(MppBufferImpl *buffer, const char* caller)
 
     pthread_mutex_lock(&buffer->lock);
 
-    buf_add_log(buffer, BUF_REF_DEC, caller);
-
     if (buffer->ref_count <= 0) {
+        buf_add_log(buffer, BUF_REF_DEC, caller);
         mpp_err_f("found non-positive ref_count %d caller %s\n",
                   buffer->ref_count, buffer->caller);
         mpp_abort();
@@ -484,6 +525,7 @@ MPP_RET mpp_buffer_ref_dec(MppBufferImpl *buffer, const char* caller)
     buffer->ref_count--;
     if (buffer->ref_count == 0)
         release = 1;
+    buf_add_log(buffer, BUF_REF_DEC, caller);
 
     pthread_mutex_unlock(&buffer->lock);
 
@@ -557,9 +599,9 @@ MppBufferImpl *mpp_buffer_get_unused(MppBufferGroupImpl *p, size_t size, const c
             if (pos->info.size >= size) {
                 buffer = pos;
                 pthread_mutex_lock(&buffer->lock);
-                buf_add_log(buffer, BUF_REF_INC, caller);
                 buffer->ref_count++;
                 buffer->used = 1;
+                buf_add_log(buffer, BUF_REF_INC, caller);
                 list_del_init(&buffer->list_status);
                 list_add_tail(&buffer->list_status, &p->list_used);
                 p->count_used++;
@@ -610,6 +652,93 @@ RK_U32 mpp_buffer_to_addr(MppBuffer buffer, size_t offset)
     return addr;
 }
 
+static MppDevBufMapNode *mpp_buffer_attach_dev_lock(const char *caller, MppBuffer buffer, MppDev dev)
+{
+    MppBufferImpl *impl = (MppBufferImpl *)buffer;
+    MppDevBufMapNode *pos, *n;
+    MppDevBufMapNode *node = NULL;
+    MPP_RET ret = MPP_OK;
+
+    mpp_dev_ioctl(dev, MPP_DEV_LOCK_MAP, NULL);
+    pthread_mutex_lock(&impl->lock);
+
+    list_for_each_entry_safe(pos, n, &impl->list_maps, MppDevBufMapNode, list_buf) {
+        if (pos->dev == dev) {
+            node = pos;
+            goto DONE;
+        }
+    }
+
+    node = (MppDevBufMapNode *)mpp_mem_pool_get_f(caller, mpp_buf_map_node_pool);
+    if (!node) {
+        mpp_err("mpp_buffer_attach_dev failed to allocate map node\n");
+        ret = MPP_NOK;
+        goto DONE;
+    }
+
+    INIT_LIST_HEAD(&node->list_buf);
+    INIT_LIST_HEAD(&node->list_dev);
+    node->lock_buf = &impl->lock;
+    node->buffer = impl;
+    node->dev = dev;
+    node->pool = mpp_buf_map_node_pool;
+    node->buf_fd = impl->info.fd;
+
+    ret = mpp_dev_ioctl(dev, MPP_DEV_ATTACH_FD, node);
+    if (ret) {
+        mpp_mem_pool_put_f(caller, mpp_buf_map_node_pool, node);
+        node = NULL;
+        goto DONE;
+    }
+    list_add_tail(&node->list_buf, &impl->list_maps);
+
+DONE:
+    pthread_mutex_unlock(&impl->lock);
+    mpp_dev_ioctl(dev, MPP_DEV_UNLOCK_MAP, NULL);
+
+    return node;
+}
+
+MPP_RET mpp_buffer_attach_dev_f(const char *caller, MppBuffer buffer, MppDev dev)
+{
+    MppDevBufMapNode *node;
+
+    node = mpp_buffer_attach_dev_lock(caller, buffer, dev);
+
+    return node ? MPP_OK : MPP_NOK;
+}
+
+MPP_RET mpp_buffer_detach_dev_f(const char *caller, MppBuffer buffer, MppDev dev)
+{
+    MppBufferImpl *impl = (MppBufferImpl *)buffer;
+    MppDevBufMapNode *pos, *n;
+    MPP_RET ret = MPP_OK;
+
+    mpp_dev_ioctl(dev, MPP_DEV_LOCK_MAP, NULL);
+    pthread_mutex_lock(&impl->lock);
+    list_for_each_entry_safe(pos, n, &impl->list_maps, MppDevBufMapNode, list_buf) {
+        if (pos->dev == dev) {
+            list_del_init(&pos->list_buf);
+            ret = mpp_dev_ioctl(dev, MPP_DEV_DETACH_FD, pos);
+            mpp_mem_pool_put_f(caller, mpp_buf_map_node_pool, pos);
+            break;
+        }
+    }
+    pthread_mutex_unlock(&impl->lock);
+    mpp_dev_ioctl(dev, MPP_DEV_UNLOCK_MAP, NULL);
+
+    return ret;
+}
+
+RK_U32 mpp_buffer_get_iova_f(const char *caller, MppBuffer buffer, MppDev dev)
+{
+    MppDevBufMapNode *node;
+
+    node = mpp_buffer_attach_dev_lock(caller, buffer, dev);
+
+    return node ? node->iova : (RK_U32)(-1);
+}
+
 MPP_RET mpp_buffer_group_init(MppBufferGroupImpl **group, const char *tag, const char *caller,
                               MppBufferMode mode, MppBufferType type)
 {
@@ -727,13 +856,14 @@ MppBufferGroupImpl *mpp_buffer_get_misc_group(MppBufferMode mode, MppBufferType
 {
     MppBufferGroupImpl *misc;
     RK_U32 id;
+    MppBufferType buf_type;
 
-    type = (MppBufferType)(type & MPP_BUFFER_TYPE_MASK);
-    if (type == MPP_BUFFER_TYPE_NORMAL)
+    buf_type = (MppBufferType)(type & MPP_BUFFER_TYPE_MASK);
+    if (buf_type == MPP_BUFFER_TYPE_NORMAL)
         return NULL;
 
     mpp_assert(mode < MPP_BUFFER_MODE_BUTT);
-    mpp_assert(type < MPP_BUFFER_TYPE_BUTT);
+    mpp_assert(buf_type < MPP_BUFFER_TYPE_BUTT);
 
     AutoMutex auto_lock(MppBufferService::get_lock());
 
@@ -744,8 +874,8 @@ MppBufferGroupImpl *mpp_buffer_get_misc_group(MppBufferMode mode, MppBufferType
 
         offset += snprintf(tag + offset, sizeof(tag) - offset, "misc");
         offset += snprintf(tag + offset, sizeof(tag) - offset, "_%s",
-                           type == MPP_BUFFER_TYPE_ION ? "ion" :
-                           type == MPP_BUFFER_TYPE_DRM ? "drm" : "na");
+                           buf_type == MPP_BUFFER_TYPE_ION ? "ion" :
+                           buf_type == MPP_BUFFER_TYPE_DRM ? "drm" : "na");
         offset += snprintf(tag + offset, sizeof(tag) - offset, "_%s",
                            mode == MPP_BUFFER_INTERNAL ? "int" : "ext");
 
diff --git a/mpp/base/mpp_cfg.cpp b/mpp/base/mpp_cfg.cpp
index 1fe87b3e3..e89bf66ae 100644
--- a/mpp/base/mpp_cfg.cpp
+++ b/mpp/base/mpp_cfg.cpp
@@ -31,184 +31,98 @@
 #define mpp_cfg_dbg_get(fmt, ...)   mpp_cfg_dbg(MPP_CFG_DBG_GET, fmt, ## __VA_ARGS__)
 
 #define CFG_TO_PTR(info, cfg)       ((char *)cfg + info->data_offset)
-#define CFG_TO_S32_PTR(info, cfg)   ((RK_S32 *)CFG_TO_PTR(info, cfg))
-#define CFG_TO_U32_PTR(info, cfg)   ((RK_U32 *)CFG_TO_PTR(info, cfg))
-#define CFG_TO_S64_PTR(info, cfg)   ((RK_S64 *)CFG_TO_PTR(info, cfg))
-#define CFG_TO_U64_PTR(info, cfg)   ((RK_U64 *)CFG_TO_PTR(info, cfg))
-#define CFG_TO_PTR_PTR(info, cfg)   ((void **)CFG_TO_PTR(info, cfg))
+#define CFG_TO_s32_PTR(info, cfg)   ((RK_S32 *)CFG_TO_PTR(info, cfg))
+#define CFG_TO_u32_PTR(info, cfg)   ((RK_U32 *)CFG_TO_PTR(info, cfg))
+#define CFG_TO_s64_PTR(info, cfg)   ((RK_S64 *)CFG_TO_PTR(info, cfg))
+#define CFG_TO_u64_PTR(info, cfg)   ((RK_U64 *)CFG_TO_PTR(info, cfg))
+#define CFG_TO_ptr_PTR(info, cfg)   ((void **)CFG_TO_PTR(info, cfg))
 
 #define CFG_TO_FLAG_PTR(info, cfg)  ((RK_U32 *)((char *)cfg + info->flag_offset))
 
-const char *cfg_type_names[] = {
-    "RK_S32",
-    "RK_U32",
-    "RK_S64",
-    "RK_U64",
-    "void *",
-    "struct",
-};
-
 static RK_U32 mpp_cfg_debug = 0;
 
-static void show_cfg_info_err(MppCfgInfoNode *node, CfgType type, const char *func)
-{
-    mpp_err("%s cfg %s expect %s input NOT %s\n", func, node->name,
-            cfg_type_names[node->data_type],
-            cfg_type_names[type]);
-}
-
-static MPP_RET mpp_cfg_set(MppCfgInfoNode *info, void *cfg, void *val)
-{
-    if (memcmp((char *)cfg + info->data_offset, val, info->data_size)) {
-        memcpy((char *)cfg + info->data_offset, val, info->data_size);
-        *((RK_U32 *)((char *)cfg + info->flag_offset)) |= info->flag_value;
-    }
-    return MPP_OK;
-}
-
-static MPP_RET mpp_cfg_get(MppCfgInfoNode *info, void *cfg, void *val)
-{
-    memcpy(val, (char *)cfg + info->data_offset, info->data_size);
-    return MPP_OK;
-}
-
-static MPP_RET mpp_cfg_set_s32(MppCfgInfoNode *info, void *cfg, RK_S32 val)
+const char *strof_cfg_type(CfgType type)
 {
-    RK_S32 *dst = CFG_TO_S32_PTR(info, cfg);
-
-    if (dst[0] != val) {
-        mpp_cfg_dbg_set("set s32 %-25s update %d -> %d\n", info->name, dst[0], val);
-        dst[0] = val;
-        CFG_TO_FLAG_PTR(info, cfg)[0] |= info->flag_value;
-    } else {
-        mpp_cfg_dbg_set("set s32 %-25s keep   %d\n", info->name, dst[0]);
-    }
+    static const char *cfg_type_names[] = {
+        "RK_S32",
+        "RK_U32",
+        "RK_S64",
+        "RK_U64",
+        "struct",
+        "void *",
+    };
 
-    return MPP_OK;
+    return cfg_type_names[type];
 }
 
-static MPP_RET mpp_cfg_get_s32(MppCfgInfoNode *info, void *cfg, RK_S32 *val)
+static void show_cfg_info_err(MppCfgInfo *node, CfgType type, const char *func, const char *name)
 {
-    return mpp_cfg_get(info, cfg, val);
+    mpp_err("%s cfg %s expect %s input NOT %s\n", func, name,
+            strof_cfg_type(node->data_type), strof_cfg_type(type));
 }
 
-static MPP_RET mpp_cfg_set_u32(MppCfgInfoNode *info, void *cfg, RK_U32 val)
+static MPP_RET mpp_cfg_set(MppCfgInfo *info, void *cfg, void *val)
 {
-    RK_U32 *dst = CFG_TO_U32_PTR(info, cfg);
-
-    if (dst[0] != val) {
-        mpp_cfg_dbg_set("set u32 %-25s update %u -> %u\n", info->name, dst[0], val);
-        dst[0] = val;
-        CFG_TO_FLAG_PTR(info, cfg)[0] |= info->flag_value;
-    } else {
-        mpp_cfg_dbg_set("set u32 %-25s keep   %u\n", info->name, dst[0]);
+    if (memcmp((char *)cfg + info->data_offset, val, info->data_size)) {
+        memcpy((char *)cfg + info->data_offset, val, info->data_size);
+        *((RK_U32 *)((char *)cfg + info->flag_offset)) |= info->flag_value;
     }
-
     return MPP_OK;
 }
 
-static MPP_RET mpp_cfg_get_u32(MppCfgInfoNode *info, void *cfg, RK_U32 *val)
-{
-    return mpp_cfg_get(info, cfg, val);
-}
-
-static MPP_RET mpp_cfg_set_s64(MppCfgInfoNode *info, void *cfg, RK_S64 val)
+static MPP_RET mpp_cfg_get(MppCfgInfo *info, void *cfg, void *val)
 {
-    RK_S64 *dst = CFG_TO_S64_PTR(info, cfg);
-
-    if (dst[0] != val) {
-        mpp_cfg_dbg_set("set s64 %-25s update %lld -> %lld\n", info->name, dst[0], val);
-        dst[0] = val;
-        CFG_TO_FLAG_PTR(info, cfg)[0] |= info->flag_value;
-    } else {
-        mpp_cfg_dbg_set("set s64 %-25s keep   %lld\n", info->name, dst[0]);
-    }
-
+    memcpy(val, (char *)cfg + info->data_offset, info->data_size);
     return MPP_OK;
 }
 
-static MPP_RET mpp_cfg_get_s64(MppCfgInfoNode *info, void *cfg, RK_S64 *val)
-{
-    return mpp_cfg_get(info, cfg, val);
-}
-
-static MPP_RET mpp_cfg_set_u64(MppCfgInfoNode *info, void *cfg, RK_U64 val)
-{
-    RK_U64 *dst = CFG_TO_U64_PTR(info, cfg);
-
-    if (dst[0] != val) {
-        mpp_cfg_dbg_set("set u64 %-25s update %llu -> %llu\n", info->name, dst[0], val);
-        dst[0] = val;
-        CFG_TO_FLAG_PTR(info, cfg)[0] |= info->flag_value;
-    } else {
-        mpp_cfg_dbg_set("set u64 %-25s keep   %llu\n", info->name, dst[0]);
+#define MPP_CFG_ACCESS(type, base_type) \
+    MPP_RET mpp_cfg_set_##type(MppCfgInfo *info, void *cfg, base_type val) \
+    { \
+        base_type *dst = CFG_TO_##type##_PTR(info, cfg); \
+        base_type old = dst[0]; \
+        dst[0] = val; \
+        if (!info->flag_type) { \
+            mpp_cfg_dbg_set("%p + %d set " #type " change %d -> %d\n", cfg, info->data_offset, old, val); \
+        } else { \
+            if (old != val) { \
+                mpp_cfg_dbg_set("%p + %d set " #type " update %d -> %d flag %d|%x\n", \
+                                cfg, info->data_offset, old, val, info->flag_offset, info->flag_value); \
+                CFG_TO_FLAG_PTR(info, cfg)[0] |= info->flag_value; \
+            } else { \
+                mpp_cfg_dbg_set("%p + %d set " #type " keep   %d\n", cfg, info->data_offset, old); \
+            } \
+        } \
+        return MPP_OK; \
+    } \
+    MPP_RET mpp_cfg_get_##type(MppCfgInfo *info, void *cfg, base_type *val) \
+    { \
+        if (info && info->data_size) { \
+            base_type *src = CFG_TO_##type##_PTR(info, cfg); \
+            mpp_cfg_dbg_set("%p + %d get " #type " value  %d\n", cfg, info->data_offset, src[0]); \
+            val[0] = src[0]; \
+            return MPP_OK; \
+        } \
+        return MPP_NOK; \
     }
 
-    return MPP_OK;
-}
-
-static MPP_RET mpp_cfg_get_u64(MppCfgInfoNode *info, void *cfg, RK_U64 *val)
-{
-    return mpp_cfg_get(info, cfg, val);
-}
+MPP_CFG_ACCESS(s32, RK_S32)
+MPP_CFG_ACCESS(u32, RK_U32)
+MPP_CFG_ACCESS(s64, RK_S64)
+MPP_CFG_ACCESS(u64, RK_U64)
+MPP_CFG_ACCESS(ptr, void *)
 
-static MPP_RET mpp_cfg_set_st(MppCfgInfoNode *info, void *cfg, void *val)
+MPP_RET mpp_cfg_set_st(MppCfgInfo *info, void *cfg, void *val)
 {
     return mpp_cfg_set(info, cfg, val);
 }
 
-static MPP_RET mpp_cfg_get_st(MppCfgInfoNode *info, void *cfg, void *val)
-{
-    return mpp_cfg_get(info, cfg, val);
-}
-
-static MPP_RET mpp_cfg_set_ptr(MppCfgInfoNode *info, void *cfg, void *val)
-{
-    void **dst = CFG_TO_PTR_PTR(info, cfg);
-
-    mpp_cfg_dbg_set("set ptr %-25s update %p -> %p\n", info->name, dst[0], val);
-    dst[0] = val;
-    CFG_TO_FLAG_PTR(info, cfg)[0] |= info->flag_value;
-
-    return MPP_OK;
-}
-
-static MPP_RET mpp_cfg_get_ptr(MppCfgInfoNode *info, void *cfg, void **val)
+MPP_RET mpp_cfg_get_st(MppCfgInfo *info, void *cfg, void *val)
 {
     return mpp_cfg_get(info, cfg, val);
 }
 
-MppCfgOps mpp_cfg_ops = {
-    mpp_cfg_set_s32,
-    mpp_cfg_get_s32,
-    mpp_cfg_set_u32,
-    mpp_cfg_get_u32,
-    mpp_cfg_set_s64,
-    mpp_cfg_get_s64,
-    mpp_cfg_set_u64,
-    mpp_cfg_get_u64,
-    mpp_cfg_set_st,
-    mpp_cfg_get_st,
-    mpp_cfg_set_ptr,
-    mpp_cfg_get_ptr,
-};
-
-#define MPP_CFG_SET_OPS(type)   ((long)(((void **)&mpp_cfg_ops)[type * 2 + 0]))
-#define MPP_CFG_GET_OPS(type)   ((long)(((void **)&mpp_cfg_ops)[type * 2 + 1]))
-
-MPP_RET mpp_cfg_node_fixup_func(MppCfgInfoNode *node)
-{
-    RK_S32 data_type = node->data_type;
-
-    mpp_env_get_u32("mpp_cfg_debug", &mpp_cfg_debug, 0);
-
-    mpp_assert(data_type < CFG_FUNC_TYPE_BUTT);
-    node->set_func = MPP_CFG_SET_OPS(data_type);
-    node->get_func = MPP_CFG_GET_OPS(data_type);
-    return MPP_OK;
-}
-
-MPP_RET check_cfg_info(MppCfgInfoNode *node, const char *name, CfgType type,
+MPP_RET check_cfg_info(MppCfgInfo *node, const char *name, CfgType type,
                        const char *func)
 {
     if (NULL == node) {
@@ -223,36 +137,36 @@ MPP_RET check_cfg_info(MppCfgInfoNode *node, const char *name, CfgType type,
     switch (type) {
     case CFG_FUNC_TYPE_St : {
         if (cfg_type != type) {
-            show_cfg_info_err(node, type, func);
+            show_cfg_info_err(node, type, func, name);
             ret = MPP_NOK;
         }
         if (cfg_size <= 0) {
-            mpp_err("%s: cfg %s found invalid size %d\n", func, node->name, cfg_size);
+            mpp_err("%s: cfg %s found invalid size %d\n", func, name, cfg_size);
             ret = MPP_NOK;
         }
     } break;
     case CFG_FUNC_TYPE_Ptr : {
         if (cfg_type != type) {
-            show_cfg_info_err(node, type, func);
+            show_cfg_info_err(node, type, func, name);
             ret = MPP_NOK;
         }
     } break;
     case CFG_FUNC_TYPE_S32 :
     case CFG_FUNC_TYPE_U32 : {
         if (cfg_size != sizeof(RK_S32)) {
-            show_cfg_info_err(node, type, func);
+            show_cfg_info_err(node, type, func, name);
             ret = MPP_NOK;
         }
     } break;
     case CFG_FUNC_TYPE_S64 :
     case CFG_FUNC_TYPE_U64 : {
         if (cfg_size != sizeof(RK_S64)) {
-            show_cfg_info_err(node, type, func);
+            show_cfg_info_err(node, type, func, name);
             ret = MPP_NOK;
         }
     } break;
     default : {
-        mpp_err("%s: cfg %s found invalid cfg type %d\n", func, node->name, type);
+        mpp_err("%s: cfg %s found invalid cfg type %d\n", func, name, type);
         ret = MPP_NOK;
     } break;
     }
diff --git a/mpp/base/mpp_dec_cfg.cpp b/mpp/base/mpp_dec_cfg.cpp
index 818cb0269..3f480cecd 100644
--- a/mpp/base/mpp_dec_cfg.cpp
+++ b/mpp/base/mpp_dec_cfg.cpp
@@ -43,26 +43,6 @@
 
 RK_U32 mpp_dec_cfg_debug = 0;
 
-typedef struct MppDecCfgInfo_t {
-    MppCfgInfoHead      head;
-    MppTrieNode         trie_node[];
-    /* MppCfgInfoNode is following trie_node */
-} MppDecCfgInfo;
-
-static MppCfgInfoNode *mpp_dec_cfg_find(MppDecCfgInfo *info, const char *name)
-{
-    MppTrieNode *node;
-
-    if (NULL == info || NULL == name)
-        return NULL;
-
-    node = mpp_trie_get_node(info->trie_node, name);
-    if (NULL == node)
-        return NULL;
-
-    return (MppCfgInfoNode *)(((char *)info->trie_node) + node->id);
-}
-
 class MppDecCfgService
 {
 private:
@@ -71,7 +51,8 @@ class MppDecCfgService
     MppDecCfgService(const MppDecCfgService &);
     MppDecCfgService &operator=(const MppDecCfgService &);
 
-    MppDecCfgInfo *mInfo;
+    MppCfgInfoHead mHead;
+    MppTrie mTrie;
     RK_S32 mCfgSize;
 
 public:
@@ -83,180 +64,103 @@ class MppDecCfgService
         return &instance;
     }
 
-    MppCfgInfoNode *get_info(const char *name) { return mpp_dec_cfg_find(mInfo, name); };
-    MppCfgInfoNode *get_info_root();
+    MppTrieInfo *get_info(const char *name);
+    MppTrieInfo *get_info_first();
+    MppTrieInfo *get_info_next(MppTrieInfo *info);
 
-    RK_S32 get_node_count() { return mInfo ? mInfo->head.node_count : 0; };
-    RK_S32 get_info_count() { return mInfo ? mInfo->head.info_count : 0; };
-    RK_S32 get_info_size() { return mInfo ? mInfo->head.info_size : 0; };
+    RK_S32 get_node_count() { return mHead.node_count; };
+    RK_S32 get_info_count() { return mHead.info_count; };
+    RK_S32 get_info_size() { return mHead.info_size; };
     RK_S32 get_cfg_size() { return mCfgSize; };
 };
 
-#define EXPAND_AS_API(base, name, cfg_type, in_type, flag, field_change, field_data) \
-    MppCfgApi api_##base##_##name = \
-    { \
-        #base":"#name, \
-        CFG_FUNC_TYPE_##cfg_type, \
-        (RK_U32)((long)&(((MppDecCfgSet *)0)->field_change.change)), \
-        flag, \
-        (RK_U32)((long)&(((MppDecCfgSet *)0)->field_change.field_data)), \
-        sizeof((((MppDecCfgSet *)0)->field_change.field_data)), \
-    };
-
-#define EXPAND_AS_ARRAY(base, name, cfg_type, in_type, flag, field_change, field_data) \
-    &api_##base##_##name,
+#define EXPAND_AS_TRIE(base, name, cfg_type, flag, field_change, field_data) \
+    do { \
+        MppCfgInfo tmp = { \
+            CFG_FUNC_TYPE_##cfg_type, \
+            (RK_U32)((flag) ? 1 : 0), \
+            (RK_U32)((long)&(((MppDecCfgSet *)0)->field_change.change)), \
+            flag, \
+            (RK_U32)((long)&(((MppDecCfgSet *)0)->field_change.field_data)), \
+            sizeof((((MppDecCfgSet *)0)->field_change.field_data)), \
+        }; \
+        mpp_trie_add_info(mTrie, #base":"#name, &tmp); \
+    } while (0);
 
 #define ENTRY_TABLE(ENTRY)  \
     /* rc config */ \
-    ENTRY(base, type,           U32, MppCtxType,        MPP_DEC_CFG_CHANGE_TYPE,            base, type) \
-    ENTRY(base, coding,         U32, MppCodingType,     MPP_DEC_CFG_CHANGE_CODING,          base, coding) \
-    ENTRY(base, hw_type,        U32, MppCodingType,     MPP_DEC_CFG_CHANGE_HW_TYPE,         base, hw_type) \
-    ENTRY(base, batch_mode,     U32, RK_U32,            MPP_DEC_CFG_CHANGE_BATCH_MODE,      base, batch_mode) \
-    ENTRY(base, out_fmt,        U32, MppFrameFormat,    MPP_DEC_CFG_CHANGE_OUTPUT_FORMAT,   base, out_fmt) \
-    ENTRY(base, fast_out,       U32, RK_U32,            MPP_DEC_CFG_CHANGE_FAST_OUT,        base, fast_out) \
-    ENTRY(base, fast_parse,     U32, RK_U32,            MPP_DEC_CFG_CHANGE_FAST_PARSE,      base, fast_parse) \
-    ENTRY(base, split_parse,    U32, RK_U32,            MPP_DEC_CFG_CHANGE_SPLIT_PARSE,     base, split_parse) \
-    ENTRY(base, internal_pts,   U32, RK_U32,            MPP_DEC_CFG_CHANGE_INTERNAL_PTS,    base, internal_pts) \
-    ENTRY(base, sort_pts,       U32, RK_U32,            MPP_DEC_CFG_CHANGE_SORT_PTS,        base, sort_pts) \
-    ENTRY(base, disable_error,  U32, RK_U32,            MPP_DEC_CFG_CHANGE_DISABLE_ERROR,   base, disable_error) \
-    ENTRY(base, enable_vproc,   U32, RK_U32,            MPP_DEC_CFG_CHANGE_ENABLE_VPROC,    base, enable_vproc) \
-    ENTRY(base, enable_fast_play, U32, RK_U32,          MPP_DEC_CFG_CHANGE_ENABLE_FAST_PLAY, base, enable_fast_play) \
-    ENTRY(base, enable_hdr_meta, U32, RK_U32,           MPP_DEC_CFG_CHANGE_ENABLE_HDR_META, base, enable_hdr_meta) \
-    ENTRY(base, enable_thumbnail, U32, RK_U32,          MPP_DEC_CFG_CHANGE_ENABLE_THUMBNAIL, base, enable_thumbnail) \
-    ENTRY(base, enable_mvc,     U32, RK_U32,            MPP_DEC_CFG_CHANGE_ENABLE_MVC,      base, enable_mvc) \
-    ENTRY(base, disable_thread, U32, RK_U32,            MPP_DEC_CFG_CHANGE_DISABLE_THREAD,  base, disable_thread) \
-    ENTRY(cb, pkt_rdy_cb,       Ptr, MppExtCbFunc,      MPP_DEC_CB_CFG_CHANGE_PKT_RDY,      cb, pkt_rdy_cb) \
-    ENTRY(cb, pkt_rdy_ctx,      Ptr, MppExtCbCtx,       MPP_DEC_CB_CFG_CHANGE_PKT_RDY,      cb, pkt_rdy_ctx) \
-    ENTRY(cb, pkt_rdy_cmd,      S32, RK_S32,            MPP_DEC_CB_CFG_CHANGE_PKT_RDY,      cb, pkt_rdy_cmd) \
-    ENTRY(cb, frm_rdy_cb,       Ptr, MppExtCbFunc,      MPP_DEC_CB_CFG_CHANGE_FRM_RDY,      cb, frm_rdy_cb) \
-    ENTRY(cb, frm_rdy_ctx,      Ptr, MppExtCbCtx,       MPP_DEC_CB_CFG_CHANGE_FRM_RDY,      cb, frm_rdy_ctx) \
-    ENTRY(cb, frm_rdy_cmd,      S32, RK_S32,            MPP_DEC_CB_CFG_CHANGE_FRM_RDY,      cb, frm_rdy_cmd)
-
-static MppDecCfgInfo *mpp_dec_cfg_flaten(MppTrie trie, MppCfgApi **cfgs)
+    ENTRY(base, type,               U32,    MPP_DEC_CFG_CHANGE_TYPE,                base, type) \
+    ENTRY(base, coding,             U32,    MPP_DEC_CFG_CHANGE_CODING,              base, coding) \
+    ENTRY(base, hw_type,            U32,    MPP_DEC_CFG_CHANGE_HW_TYPE,             base, hw_type) \
+    ENTRY(base, batch_mode,         U32,    MPP_DEC_CFG_CHANGE_BATCH_MODE,          base, batch_mode) \
+    ENTRY(base, out_fmt,            U32,    MPP_DEC_CFG_CHANGE_OUTPUT_FORMAT,       base, out_fmt) \
+    ENTRY(base, fast_out,           U32,    MPP_DEC_CFG_CHANGE_FAST_OUT,            base, fast_out) \
+    ENTRY(base, fast_parse,         U32,    MPP_DEC_CFG_CHANGE_FAST_PARSE,          base, fast_parse) \
+    ENTRY(base, split_parse,        U32,    MPP_DEC_CFG_CHANGE_SPLIT_PARSE,         base, split_parse) \
+    ENTRY(base, internal_pts,       U32,    MPP_DEC_CFG_CHANGE_INTERNAL_PTS,        base, internal_pts) \
+    ENTRY(base, sort_pts,           U32,    MPP_DEC_CFG_CHANGE_SORT_PTS,            base, sort_pts) \
+    ENTRY(base, disable_error,      U32,    MPP_DEC_CFG_CHANGE_DISABLE_ERROR,       base, disable_error) \
+    ENTRY(base, enable_vproc,       U32,    MPP_DEC_CFG_CHANGE_ENABLE_VPROC,        base, enable_vproc) \
+    ENTRY(base, enable_fast_play,   U32,    MPP_DEC_CFG_CHANGE_ENABLE_FAST_PLAY,    base, enable_fast_play) \
+    ENTRY(base, enable_hdr_meta,    U32,    MPP_DEC_CFG_CHANGE_ENABLE_HDR_META,     base, enable_hdr_meta) \
+    ENTRY(base, enable_thumbnail,   U32,    MPP_DEC_CFG_CHANGE_ENABLE_THUMBNAIL,    base, enable_thumbnail) \
+    ENTRY(base, enable_mvc,         U32,    MPP_DEC_CFG_CHANGE_ENABLE_MVC,          base, enable_mvc) \
+    ENTRY(base, disable_dpb_chk,    U32,    MPP_DEC_CFG_CHANGE_DISABLE_DPB_CHECK,   base, disable_dpb_chk) \
+    ENTRY(base, disable_thread,     U32,    MPP_DEC_CFG_CHANGE_DISABLE_THREAD,      base, disable_thread) \
+    ENTRY(cb, pkt_rdy_cb,           Ptr,    MPP_DEC_CB_CFG_CHANGE_PKT_RDY,          cb, pkt_rdy_cb) \
+    ENTRY(cb, pkt_rdy_ctx,          Ptr,    MPP_DEC_CB_CFG_CHANGE_PKT_RDY,          cb, pkt_rdy_ctx) \
+    ENTRY(cb, pkt_rdy_cmd,          S32,    MPP_DEC_CB_CFG_CHANGE_PKT_RDY,          cb, pkt_rdy_cmd) \
+    ENTRY(cb, frm_rdy_cb,           Ptr,    MPP_DEC_CB_CFG_CHANGE_FRM_RDY,          cb, frm_rdy_cb) \
+    ENTRY(cb, frm_rdy_ctx,          Ptr,    MPP_DEC_CB_CFG_CHANGE_FRM_RDY,          cb, frm_rdy_ctx) \
+    ENTRY(cb, frm_rdy_cmd,          S32,    MPP_DEC_CB_CFG_CHANGE_FRM_RDY,          cb, frm_rdy_cmd)
+
+MppDecCfgService::MppDecCfgService() :
+    mTrie(NULL)
 {
-    MppDecCfgInfo *info = NULL;
-    MppTrieNode *node_root = mpp_trie_node_root(trie);
-    RK_S32 node_count = mpp_trie_get_node_count(trie);
-    RK_S32 info_count = mpp_trie_get_info_count(trie);
-    MppTrieNode *node_trie;
-    char *buf = NULL;
-    RK_S32 pos = 0;
-    RK_S32 len = 0;
-    RK_S32 i;
-
-    pos += node_count * sizeof(*node_root);
-
-    mpp_dec_cfg_dbg_info("info node offset %d\n", pos);
-
-    /* update info size and string name size */
-    for (i = 0; i < info_count; i++) {
-        const char *name = cfgs[i]->name;
-        const char **info_trie = mpp_trie_get_info(trie, name);
-
-        mpp_assert(*info_trie == name);
-        len = strlen(name);
-        pos += sizeof(MppCfgInfoNode) + MPP_ALIGN(len + 1, sizeof(RK_U64));
+    MPP_RET ret = mpp_trie_init(&mTrie, sizeof(MppCfgInfo));
+    if (ret) {
+        mpp_err_f("failed to init dec cfg set trie\n");
+        return ;
     }
 
-    len = pos + sizeof(*info);
-    mpp_dec_cfg_dbg_info("tire + info size %d total %d\n", pos, len);
-
-    info = mpp_malloc_size(MppDecCfgInfo, len);
-    if (NULL == info)
-        return NULL;
-
-    memcpy(info->trie_node, node_root, sizeof(*node_root) * node_count);
-
-    node_root = info->trie_node;
-    pos = node_count * sizeof(*node_root);
-    buf = (char *)node_root + pos;
-
-    for (i = 0; i < info_count; i++) {
-        MppCfgInfoNode *node_info = (MppCfgInfoNode *)buf;
-        MppCfgApi *api = cfgs[i];
-        const char *name = api->name;
-        RK_S32 node_size;
-
-        node_trie = mpp_trie_get_node(node_root, name);
-        node_trie->id = pos;
-
-        node_info->name_len     = MPP_ALIGN(strlen(name) + 1, sizeof(RK_U64));
-        node_info->data_type    = api->data_type;
-        node_info->flag_offset  = api->flag_offset;
-        node_info->flag_value   = api->flag_value;
-        node_info->data_offset  = api->data_offset;
-        node_info->data_size    = api->data_size;
-        node_info->node_next    = 0;
+    ENTRY_TABLE(EXPAND_AS_TRIE)
 
-        node_size = node_info->name_len + sizeof(*node_info);
-        node_info->node_size    = node_size;
+    mpp_trie_add_info(mTrie, NULL, NULL);
 
-        mpp_cfg_node_fixup_func(node_info);
+    mHead.node_count = mpp_trie_get_node_count(mTrie);
+    mHead.info_count = mpp_trie_get_info_count(mTrie);
+    mHead.info_size = mpp_trie_get_buf_size(mTrie);
 
-        strcpy(node_info->name, name);
-
-        mpp_dec_cfg_dbg_info("cfg %s offset %d size %d update %d flag %x\n",
-                             node_info->name,
-                             node_info->data_offset, node_info->data_size,
-                             node_info->flag_offset, node_info->flag_value);
-
-        pos += node_size;
-        buf += node_size;
-    }
-
-    mpp_dec_cfg_dbg_info("total size %d +H %d\n", pos, pos + sizeof(info->head));
-
-    info->head.info_size  = pos;
-    info->head.info_count = info_count;
-    info->head.node_count = node_count;
-    info->head.cfg_size   = sizeof(MppDecCfgSet);
-
-    return info;
+    mpp_dec_cfg_dbg_func("node cnt: %d\n", mHead.node_count);
 }
 
-MppDecCfgService::MppDecCfgService() :
-    mInfo(NULL),
-    mCfgSize(0)
+MppDecCfgService::~MppDecCfgService()
 {
-    ENTRY_TABLE(EXPAND_AS_API);
-
-    MppCfgApi *cfgs[] = {
-        ENTRY_TABLE(EXPAND_AS_ARRAY)
-    };
-
-    RK_S32 cfg_cnt = MPP_ARRAY_ELEMS(cfgs);
-    MppTrie trie;
-    MPP_RET ret;
-    RK_S32 i;
-    /*
-     * NOTE: The dec_node_len is not the real node count should be allocated
-     * The max node count should be stream lengthg * 2 if each word is different.
-     */
-    ret = mpp_trie_init(&trie, 334, cfg_cnt);
-    if (ret) {
-        mpp_err_f("failed to init dec cfg set trie\n");
-        return ;
+    if (mTrie) {
+        mpp_trie_deinit(mTrie);
+        mTrie = NULL;
     }
-    for (i = 0; i < cfg_cnt; i++)
-        mpp_trie_add_info(trie, &cfgs[i]->name);
-
-    mInfo = mpp_dec_cfg_flaten(trie, cfgs);
-    mCfgSize = mInfo->head.cfg_size;
+}
 
-    mpp_trie_deinit(trie);
+MppTrieInfo *MppDecCfgService::get_info(const char *name)
+{
+    return mpp_trie_get_info(mTrie, name);
 }
 
-MppDecCfgService::~MppDecCfgService()
+MppTrieInfo *MppDecCfgService::get_info_first()
 {
-    MPP_FREE(mInfo);
+    if (NULL == mTrie)
+        return NULL;
+
+    return mpp_trie_get_info_first(mTrie);
 }
 
-MppCfgInfoNode *MppDecCfgService::get_info_root()
+MppTrieInfo *MppDecCfgService::get_info_next(MppTrieInfo *node)
 {
-    if (NULL == mInfo)
+    if (NULL == mTrie)
         return NULL;
 
-    return (MppCfgInfoNode *)(mInfo->trie_node + mInfo->head.node_count);
+    return mpp_trie_get_info_next(mTrie, node);
 }
 
 void mpp_dec_cfg_set_default(MppDecCfgSet *cfg)
@@ -275,14 +179,14 @@ void mpp_dec_cfg_set_default(MppDecCfgSet *cfg)
 MPP_RET mpp_dec_cfg_init(MppDecCfg *cfg)
 {
     MppDecCfgImpl *p = NULL;
-    RK_S32 cfg_size;
 
     if (NULL == cfg) {
         mpp_err_f("invalid NULL input config\n");
         return MPP_ERR_NULL_PTR;
     }
 
-    cfg_size = MppDecCfgService::get()->get_cfg_size();
+    mpp_env_get_u32("mpp_dec_cfg_debug", &mpp_dec_cfg_debug, 0);
+
     p = mpp_calloc(MppDecCfgImpl, 1);
     if (NULL == p) {
         mpp_err_f("create decoder config failed %p\n", p);
@@ -290,12 +194,9 @@ MPP_RET mpp_dec_cfg_init(MppDecCfg *cfg)
         return MPP_ERR_NOMEM;
     }
 
-    mpp_assert(cfg_size == sizeof(p->cfg));
-    p->size = cfg_size;
+    p->size = sizeof(p->cfg);
     mpp_dec_cfg_set_default(&p->cfg);
 
-    mpp_env_get_u32("mpp_dec_cfg_debug", &mpp_dec_cfg_debug, 0);
-
     *cfg = p;
 
     return MPP_OK;
@@ -313,7 +214,7 @@ MPP_RET mpp_dec_cfg_deinit(MppDecCfg cfg)
     return MPP_OK;
 }
 
-#define ENC_CFG_SET_ACCESS(func_name, in_type, cfg_type) \
+#define DEC_CFG_SET_ACCESS(func_name, in_type, cfg_type) \
     MPP_RET func_name(MppDecCfg cfg, const char *name, in_type val) \
     { \
         if (NULL == cfg || NULL == name) { \
@@ -321,23 +222,24 @@ MPP_RET mpp_dec_cfg_deinit(MppDecCfg cfg)
             return MPP_ERR_NULL_PTR; \
         } \
         MppDecCfgImpl *p = (MppDecCfgImpl *)cfg; \
-        MppCfgInfoNode *info = MppDecCfgService::get()->get_info(name); \
+        MppTrieInfo *node = MppDecCfgService::get()->get_info(name); \
+        MppCfgInfo *info = (MppCfgInfo *)(node ? node->ctx : NULL); \
         if (CHECK_CFG_INFO(info, name, CFG_FUNC_TYPE_##cfg_type)) { \
             return MPP_NOK; \
         } \
-        mpp_dec_cfg_dbg_set("name %s type %s\n", info->name, cfg_type_names[info->data_type]); \
+        mpp_dec_cfg_dbg_set("name %s type %s\n", node->name, strof_cfg_type(info->data_type)); \
         MPP_RET ret = MPP_CFG_SET_##cfg_type(info, &p->cfg, val); \
         return ret; \
     }
 
-ENC_CFG_SET_ACCESS(mpp_dec_cfg_set_s32, RK_S32, S32);
-ENC_CFG_SET_ACCESS(mpp_dec_cfg_set_u32, RK_U32, U32);
-ENC_CFG_SET_ACCESS(mpp_dec_cfg_set_s64, RK_S64, S64);
-ENC_CFG_SET_ACCESS(mpp_dec_cfg_set_u64, RK_U64, U64);
-ENC_CFG_SET_ACCESS(mpp_dec_cfg_set_ptr, void *, Ptr);
-ENC_CFG_SET_ACCESS(mpp_dec_cfg_set_st,  void *, St);
+DEC_CFG_SET_ACCESS(mpp_dec_cfg_set_s32, RK_S32, S32);
+DEC_CFG_SET_ACCESS(mpp_dec_cfg_set_u32, RK_U32, U32);
+DEC_CFG_SET_ACCESS(mpp_dec_cfg_set_s64, RK_S64, S64);
+DEC_CFG_SET_ACCESS(mpp_dec_cfg_set_u64, RK_U64, U64);
+DEC_CFG_SET_ACCESS(mpp_dec_cfg_set_ptr, void *, Ptr);
+DEC_CFG_SET_ACCESS(mpp_dec_cfg_set_st,  void *, St);
 
-#define ENC_CFG_GET_ACCESS(func_name, in_type, cfg_type) \
+#define DEC_CFG_GET_ACCESS(func_name, in_type, cfg_type) \
     MPP_RET func_name(MppDecCfg cfg, const char *name, in_type *val) \
     { \
         if (NULL == cfg || NULL == name) { \
@@ -345,46 +247,45 @@ ENC_CFG_SET_ACCESS(mpp_dec_cfg_set_st,  void *, St);
             return MPP_ERR_NULL_PTR; \
         } \
         MppDecCfgImpl *p = (MppDecCfgImpl *)cfg; \
-        MppCfgInfoNode *info = MppDecCfgService::get()->get_info(name); \
+        MppTrieInfo *node = MppDecCfgService::get()->get_info(name); \
+        MppCfgInfo *info = (MppCfgInfo *)(node ? node->ctx : NULL); \
         if (CHECK_CFG_INFO(info, name, CFG_FUNC_TYPE_##cfg_type)) { \
             return MPP_NOK; \
         } \
-        mpp_dec_cfg_dbg_set("name %s type %s\n", info->name, cfg_type_names[info->data_type]); \
+        mpp_dec_cfg_dbg_set("name %s type %s\n", node->name, strof_cfg_type(info->data_type)); \
         MPP_RET ret = MPP_CFG_GET_##cfg_type(info, &p->cfg, val); \
         return ret; \
     }
 
-ENC_CFG_GET_ACCESS(mpp_dec_cfg_get_s32, RK_S32, S32);
-ENC_CFG_GET_ACCESS(mpp_dec_cfg_get_u32, RK_U32, U32);
-ENC_CFG_GET_ACCESS(mpp_dec_cfg_get_s64, RK_S64, S64);
-ENC_CFG_GET_ACCESS(mpp_dec_cfg_get_u64, RK_U64, U64);
-ENC_CFG_GET_ACCESS(mpp_dec_cfg_get_ptr, void *, Ptr);
-ENC_CFG_GET_ACCESS(mpp_dec_cfg_get_st,  void  , St);
+DEC_CFG_GET_ACCESS(mpp_dec_cfg_get_s32, RK_S32, S32);
+DEC_CFG_GET_ACCESS(mpp_dec_cfg_get_u32, RK_U32, U32);
+DEC_CFG_GET_ACCESS(mpp_dec_cfg_get_s64, RK_S64, S64);
+DEC_CFG_GET_ACCESS(mpp_dec_cfg_get_u64, RK_U64, U64);
+DEC_CFG_GET_ACCESS(mpp_dec_cfg_get_ptr, void *, Ptr);
+DEC_CFG_GET_ACCESS(mpp_dec_cfg_get_st,  void  , St);
 
 void mpp_dec_cfg_show(void)
 {
-    RK_S32 node_count = MppDecCfgService::get()->get_node_count();
-    RK_S32 info_count = MppDecCfgService::get()->get_info_count();
-    MppCfgInfoNode *info = MppDecCfgService::get()->get_info_root();
+    MppDecCfgService *srv = MppDecCfgService::get();
+    MppTrieInfo *root = srv->get_info_first();
 
     mpp_log("dumping valid configure string start\n");
 
-    if (info) {
-        char *p = (char *)info;
-        RK_S32 i;
+    if (root) {
+        MppTrieInfo *node = root;
 
-        for (i = 0; i < info_count; i++) {
-            info = (MppCfgInfoNode *)p;
+        do {
+            MppCfgInfo *info = (MppCfgInfo *)node->ctx;
 
-            mpp_log("%-25s type %s\n", info->name,
-                    cfg_type_names[info->data_type]);
+            mpp_log("%-25s type %s\n", node->name, strof_cfg_type(info->data_type));
 
-            p += info->node_size;
-        }
+            node = srv->get_info_next(node);
+            if (!node)
+                break;
+        } while (1);
     }
     mpp_log("dumping valid configure string done\n");
 
     mpp_log("total cfg count %d with %d node size %d\n",
-            info_count, node_count,
-            MppDecCfgService::get()->get_info_size());
-}
+            srv->get_info_count(), srv->get_node_count(), srv->get_info_size());
+}
\ No newline at end of file
diff --git a/mpp/base/mpp_dec_hdr_meta.c b/mpp/base/mpp_dec_hdr_meta.c
index 4da575cf8..b7946a838 100644
--- a/mpp/base/mpp_dec_hdr_meta.c
+++ b/mpp/base/mpp_dec_hdr_meta.c
@@ -28,7 +28,7 @@ static RK_U32 hdr_get_offset_from_frame(MppFrame frame)
     return mpp_frame_get_buf_size(frame);
 }
 
-void fill_hdr_meta_to_frame(MppFrame frame, HdrCodecType codec_type)
+void fill_hdr_meta_to_frame(MppFrame frame, MppCodingType in_type)
 {
     RK_U32 off = hdr_get_offset_from_frame(frame);
     MppBuffer buf = mpp_frame_get_buffer(frame);
@@ -43,12 +43,20 @@ void fill_hdr_meta_to_frame(MppFrame frame, HdrCodecType codec_type)
     MppMeta meta = NULL;
     RK_U32 max_size = mpp_buffer_get_size(buf);
     RK_U32 static_size, dynamic_size = 0, total_size = 0;
+    HdrCodecType codec_type = HDR_CODEC_UNSPECIFIED;
 
     if (!ptr || !buf) {
         mpp_err_f("buf is null!\n");
         return;
     }
 
+    if (mpp_frame_get_thumbnail_en(frame) == MPP_FRAME_THUMBNAIL_ONLY) {
+        // only for 8K thumbnail downscale to 4K 8bit mode
+        RK_U32 downscale_width = mpp_frame_get_width(frame) / 2;
+        RK_U32 downscale_height = mpp_frame_get_height(frame) / 2;
+
+        off = downscale_width * downscale_height * 3 / 2;
+    }
     off = MPP_ALIGN(off, SZ_4K);
 
     static_size = sizeof(RkMetaHdrHeader) + sizeof(HdrStaticMeta);
@@ -71,6 +79,22 @@ void fill_hdr_meta_to_frame(MppFrame frame, HdrCodecType codec_type)
     hdr_static_meta_header->size = static_size;
     hdr_static_meta_header->message_index = msg_idx++;
 
+    switch (in_type) {
+    case MPP_VIDEO_CodingAVS2 : {
+        codec_type = HDR_AVS2;
+    } break;
+    case MPP_VIDEO_CodingHEVC : {
+        codec_type = HDR_HEVC;
+    } break;
+    case MPP_VIDEO_CodingAVC : {
+        codec_type = HDR_H264;
+    } break;
+    case MPP_VIDEO_CodingAV1 : {
+        codec_type = HDR_AV1;
+    } break;
+    default : break;
+    }
+
     /* For payload identification */
     hdr_static_meta_header->hdr_payload_type = STATIC;
     hdr_static_meta_header->video_format = codec_type;
@@ -97,15 +121,26 @@ void fill_hdr_meta_to_frame(MppFrame frame, HdrCodecType codec_type)
          *  hevc trc = 18
          *  avs trc = 14
          * hdr10:
-         *  hevc trc = 16
+         *  hevc/h264 trc = 16
          *  avs trc = 12
          */
-        if ((codec_type == HDR_HEVC && static_meta->color_trc == MPP_FRAME_TRC_ARIB_STD_B67) ||
-            (codec_type == HDR_AVS2 && static_meta->color_trc == MPP_FRAME_TRC_BT2020_10))
-            hdr_format = HLG;
-        if ((codec_type == HDR_HEVC && static_meta->color_trc == MPP_FRAME_TRC_SMPTEST2084) ||
-            (codec_type == HDR_AVS2 && static_meta->color_trc == MPP_FRAME_TRC_BT1361_ECG))
-            hdr_format = HDR10;
+        switch (codec_type) {
+        case HDR_HEVC :
+        case HDR_H264 : {
+            if (static_meta->color_trc == MPP_FRAME_TRC_ARIB_STD_B67)
+                hdr_format = HLG;
+            else if (static_meta->color_trc == MPP_FRAME_TRC_SMPTEST2084)
+                hdr_format = HDR10;
+        } break;
+        case HDR_AVS2 : {
+            if (static_meta->color_trc == MPP_FRAME_TRC_BT2020_10)
+                hdr_format = HLG;
+            else if (static_meta->color_trc == MPP_FRAME_TRC_BT1361_ECG)
+                hdr_format = HDR10;
+        } break;
+        default : {
+        } break;
+        }
     }
     off += hdr_static_meta_header->size;
 
diff --git a/mpp/base/mpp_enc_cfg.cpp b/mpp/base/mpp_enc_cfg.cpp
index c5ad1b39c..fc2ab5ce5 100644
--- a/mpp/base/mpp_enc_cfg.cpp
+++ b/mpp/base/mpp_enc_cfg.cpp
@@ -44,41 +44,6 @@
 
 RK_U32 mpp_enc_cfg_debug = 0;
 
-/*
- * MppEncCfgInfo data struct
- *
- *   +----------+
- *   |   head   |
- *   +----------+
- *   |   trie   |
- *   |   node   |
- *   |   ....   |
- *   +----------+
- *   |   info   |
- *   |   node   |
- *   |   ....   |
- *   +----------+
- */
-typedef struct MppEncCfgInfo_t {
-    MppCfgInfoHead      head;
-    MppTrieNode         trie_node[];
-    /* MppCfgInfoNode is following trie_node */
-} MppEncCfgInfo;
-
-static MppCfgInfoNode *mpp_enc_cfg_find(MppEncCfgInfo *info, const char *name)
-{
-    MppTrieNode *node;
-
-    if (NULL == info || NULL == name)
-        return NULL;
-
-    node = mpp_trie_get_node(info->trie_node, name);
-    if (NULL == node)
-        return NULL;
-
-    return (MppCfgInfoNode *)(((char *)info->trie_node) + node->id);
-}
-
 class MppEncCfgService
 {
 private:
@@ -87,7 +52,8 @@ class MppEncCfgService
     MppEncCfgService(const MppEncCfgService &);
     MppEncCfgService &operator=(const MppEncCfgService &);
 
-    MppEncCfgInfo *mInfo;
+    MppCfgInfoHead mHead;
+    MppTrie mTrie;
     RK_S32 mCfgSize;
 
 public:
@@ -99,308 +65,261 @@ class MppEncCfgService
         return &instance;
     }
 
-    MppCfgInfoNode *get_info(const char *name) { return mpp_enc_cfg_find(mInfo, name); };
-    MppCfgInfoNode *get_info_root();
+    MppTrieInfo *get_info(const char *name);
+    MppTrieInfo *get_info_first();
+    MppTrieInfo *get_info_next(MppTrieInfo *node);
 
-    RK_S32 get_node_count() { return mInfo ? mInfo->head.node_count : 0; };
-    RK_S32 get_info_count() { return mInfo ? mInfo->head.info_count : 0; };
-    RK_S32 get_info_size() { return mInfo ? mInfo->head.info_size : 0; };
+    RK_S32 get_node_count() { return mHead.node_count; };
+    RK_S32 get_info_count() { return mHead.info_count; };
+    RK_S32 get_info_size() { return mHead.info_size; };
     RK_S32 get_cfg_size() { return mCfgSize; };
 };
 
-#define EXPAND_AS_API(base, name, cfg_type, in_type, flag, field_change, field_data) \
-    MppCfgApi api_##base##_##name = \
-    { \
-        #base":"#name, \
-        CFG_FUNC_TYPE_##cfg_type, \
-        (RK_U32)((long)&(((MppEncCfgSet *)0)->field_change.change)), \
-        flag, \
-        (RK_U32)((long)&(((MppEncCfgSet *)0)->field_change.field_data)), \
-        sizeof((((MppEncCfgSet *)0)->field_change.field_data)), \
-    };
-
-#define EXPAND_AS_ARRAY(base, name, cfg_type, in_type, flag, field_change, field_data) \
-    &api_##base##_##name,
+#define EXPAND_AS_TRIE(base, name, cfg_type, flag, field_change, field_data) \
+    do { \
+        MppCfgInfo tmp = { \
+            CFG_FUNC_TYPE_##cfg_type, \
+            (RK_U32)((flag) ? 1 : 0), \
+            (RK_U32)((long)&(((MppEncCfgSet *)0)->field_change.change)), \
+            flag, \
+            (RK_U32)((long)&(((MppEncCfgSet *)0)->field_change.field_data)), \
+            sizeof((((MppEncCfgSet *)0)->field_change.field_data)), \
+        }; \
+        mpp_trie_add_info(mTrie, #base":"#name, &tmp); \
+    } while (0);
 
 #define ENTRY_TABLE(ENTRY)  \
     /* base config */ \
-    ENTRY(base, low_delay,      S32, RK_S32,            MPP_ENC_BASE_CFG_CHANGE_LOW_DELAY,      base, low_delay) \
+    ENTRY(base, low_delay,      S32,        MPP_ENC_BASE_CFG_CHANGE_LOW_DELAY,      base, low_delay) \
     /* rc config */ \
-    ENTRY(rc,   mode,           S32, MppEncRcMode,      MPP_ENC_RC_CFG_CHANGE_RC_MODE,          rc, rc_mode) \
-    ENTRY(rc,   bps_target,     S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_BPS,              rc, bps_target) \
-    ENTRY(rc,   bps_max,        S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_BPS,              rc, bps_max) \
-    ENTRY(rc,   bps_min,        S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_BPS,              rc, bps_min) \
-    ENTRY(rc,   fps_in_flex,    S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_FPS_IN,           rc, fps_in_flex) \
-    ENTRY(rc,   fps_in_num,     S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_FPS_IN,           rc, fps_in_num) \
-    ENTRY(rc,   fps_in_denorm,  S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_FPS_IN,           rc, fps_in_denorm) \
-    ENTRY(rc,   fps_out_flex,   S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_FPS_OUT,          rc, fps_out_flex) \
-    ENTRY(rc,   fps_out_num,    S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_FPS_OUT,          rc, fps_out_num) \
-    ENTRY(rc,   fps_out_denorm, S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_FPS_OUT,          rc, fps_out_denorm) \
-    ENTRY(rc,   gop,            S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_GOP,              rc, gop) \
-    ENTRY(rc,   ref_cfg,        Ptr, void *,            MPP_ENC_RC_CFG_CHANGE_GOP_REF_CFG,      rc, ref_cfg) \
-    ENTRY(rc,   max_reenc_times,U32, RK_U32,            MPP_ENC_RC_CFG_CHANGE_MAX_REENC,        rc, max_reenc_times) \
-    ENTRY(rc,   priority,       U32, MppEncRcPriority,  MPP_ENC_RC_CFG_CHANGE_PRIORITY,         rc, rc_priority) \
-    ENTRY(rc,   drop_mode,      U32, MppEncRcDropFrmMode, MPP_ENC_RC_CFG_CHANGE_DROP_FRM,       rc, drop_mode) \
-    ENTRY(rc,   drop_thd,       U32, RK_U32,            MPP_ENC_RC_CFG_CHANGE_DROP_FRM,         rc, drop_threshold) \
-    ENTRY(rc,   drop_gap,       U32, RK_U32,            MPP_ENC_RC_CFG_CHANGE_DROP_FRM,         rc, drop_gap) \
-    ENTRY(rc,   max_i_prop,     S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_MAX_I_PROP,       rc, max_i_prop) \
-    ENTRY(rc,   min_i_prop,     S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_MIN_I_PROP,       rc, min_i_prop) \
-    ENTRY(rc,   init_ip_ratio,  S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_INIT_IP_RATIO,    rc, init_ip_ratio) \
-    ENTRY(rc,   super_mode,     U32, MppEncRcSuperFrameMode, MPP_ENC_RC_CFG_CHANGE_SUPER_FRM,   rc, super_mode) \
-    ENTRY(rc,   super_i_thd,    U32, RK_U32,            MPP_ENC_RC_CFG_CHANGE_SUPER_FRM,        rc, super_i_thd) \
-    ENTRY(rc,   super_p_thd,    U32, RK_U32,            MPP_ENC_RC_CFG_CHANGE_SUPER_FRM,        rc, super_p_thd) \
-    ENTRY(rc,   debreath_en,    U32, RK_U32,            MPP_ENC_RC_CFG_CHANGE_DEBREATH,         rc, debreath_en) \
-    ENTRY(rc,   debreath_strength,  U32, RK_U32,        MPP_ENC_RC_CFG_CHANGE_DEBREATH,         rc, debre_strength) \
-    ENTRY(rc,   qp_init,        S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_QP_INIT,          rc, qp_init) \
-    ENTRY(rc,   qp_min,         S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_QP_RANGE,         rc, qp_min) \
-    ENTRY(rc,   qp_max,         S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_QP_RANGE,         rc, qp_max) \
-    ENTRY(rc,   qp_min_i,       S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_QP_RANGE_I,       rc, qp_min_i) \
-    ENTRY(rc,   qp_max_i,       S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_QP_RANGE_I,       rc, qp_max_i) \
-    ENTRY(rc,   qp_step,        S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_QP_MAX_STEP,      rc, qp_max_step) \
-    ENTRY(rc,   qp_ip,          S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_QP_IP,            rc, qp_delta_ip) \
-    ENTRY(rc,   qp_vi,          S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_QP_VI,            rc, qp_delta_vi) \
-    ENTRY(rc,   hier_qp_en,     S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_HIER_QP,          rc, hier_qp_en) \
-    ENTRY(rc,   hier_qp_delta,  St,  RK_S32 *,          MPP_ENC_RC_CFG_CHANGE_HIER_QP,          rc, hier_qp_delta) \
-    ENTRY(rc,   hier_frame_num, St,  RK_S32 *,          MPP_ENC_RC_CFG_CHANGE_HIER_QP,          rc, hier_frame_num) \
-    ENTRY(rc,   stats_time,     S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_ST_TIME,          rc, stats_time) \
-    ENTRY(rc,   refresh_en,     U32, RK_U32,            MPP_ENC_RC_CFG_CHANGE_REFRESH,          rc, refresh_en) \
-    ENTRY(rc,   refresh_mode,   U32, MppEncRcRefreshMode, MPP_ENC_RC_CFG_CHANGE_REFRESH,        rc, refresh_mode) \
-    ENTRY(rc,   refresh_num,    U32, RK_U32,            MPP_ENC_RC_CFG_CHANGE_REFRESH,          rc, refresh_num) \
-    ENTRY(rc,   fqp_min_i,      S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_FQP,              rc, fqp_min_i) \
-    ENTRY(rc,   fqp_min_p,      S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_FQP,              rc, fqp_min_p) \
-    ENTRY(rc,   fqp_max_i,      S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_FQP,              rc, fqp_max_i) \
-    ENTRY(rc,   fqp_max_p,      S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_FQP,              rc, fqp_max_p) \
+    ENTRY(rc,   mode,           S32,        MPP_ENC_RC_CFG_CHANGE_RC_MODE,          rc, rc_mode) \
+    ENTRY(rc,   bps_target,     S32,        MPP_ENC_RC_CFG_CHANGE_BPS,              rc, bps_target) \
+    ENTRY(rc,   bps_max,        S32,        MPP_ENC_RC_CFG_CHANGE_BPS,              rc, bps_max) \
+    ENTRY(rc,   bps_min,        S32,        MPP_ENC_RC_CFG_CHANGE_BPS,              rc, bps_min) \
+    ENTRY(rc,   fps_in_flex,    S32,        MPP_ENC_RC_CFG_CHANGE_FPS_IN,           rc, fps_in_flex) \
+    ENTRY(rc,   fps_in_num,     S32,        MPP_ENC_RC_CFG_CHANGE_FPS_IN,           rc, fps_in_num) \
+    ENTRY(rc,   fps_in_denom,   S32,        MPP_ENC_RC_CFG_CHANGE_FPS_IN,           rc, fps_in_denom) \
+    ENTRY(rc,   fps_in_denorm,  S32,        MPP_ENC_RC_CFG_CHANGE_FPS_IN,           rc, fps_in_denom) \
+    ENTRY(rc,   fps_out_flex,   S32,        MPP_ENC_RC_CFG_CHANGE_FPS_OUT,          rc, fps_out_flex) \
+    ENTRY(rc,   fps_out_num,    S32,        MPP_ENC_RC_CFG_CHANGE_FPS_OUT,          rc, fps_out_num) \
+    ENTRY(rc,   fps_out_denom,  S32,        MPP_ENC_RC_CFG_CHANGE_FPS_OUT,          rc, fps_out_denom) \
+    ENTRY(rc,   fps_out_denorm, S32,        MPP_ENC_RC_CFG_CHANGE_FPS_OUT,          rc, fps_out_denom) \
+    ENTRY(rc,   gop,            S32,        MPP_ENC_RC_CFG_CHANGE_GOP,              rc, gop) \
+    ENTRY(rc,   ref_cfg,        Ptr,        MPP_ENC_RC_CFG_CHANGE_GOP_REF_CFG,      rc, ref_cfg) \
+    ENTRY(rc,   max_reenc_times,U32,        MPP_ENC_RC_CFG_CHANGE_MAX_REENC,        rc, max_reenc_times) \
+    ENTRY(rc,   priority,       U32,        MPP_ENC_RC_CFG_CHANGE_PRIORITY,         rc, rc_priority) \
+    ENTRY(rc,   drop_mode,      U32,        MPP_ENC_RC_CFG_CHANGE_DROP_FRM,         rc, drop_mode) \
+    ENTRY(rc,   drop_thd,       U32,        MPP_ENC_RC_CFG_CHANGE_DROP_FRM,         rc, drop_threshold) \
+    ENTRY(rc,   drop_gap,       U32,        MPP_ENC_RC_CFG_CHANGE_DROP_FRM,         rc, drop_gap) \
+    ENTRY(rc,   max_i_prop,     S32,        MPP_ENC_RC_CFG_CHANGE_MAX_I_PROP,       rc, max_i_prop) \
+    ENTRY(rc,   min_i_prop,     S32,        MPP_ENC_RC_CFG_CHANGE_MIN_I_PROP,       rc, min_i_prop) \
+    ENTRY(rc,   init_ip_ratio,  S32,        MPP_ENC_RC_CFG_CHANGE_INIT_IP_RATIO,    rc, init_ip_ratio) \
+    ENTRY(rc,   super_mode,     U32,        MPP_ENC_RC_CFG_CHANGE_SUPER_FRM,        rc, super_mode) \
+    ENTRY(rc,   super_i_thd,    U32,        MPP_ENC_RC_CFG_CHANGE_SUPER_FRM,        rc, super_i_thd) \
+    ENTRY(rc,   super_p_thd,    U32,        MPP_ENC_RC_CFG_CHANGE_SUPER_FRM,        rc, super_p_thd) \
+    ENTRY(rc,   debreath_en,    U32,        MPP_ENC_RC_CFG_CHANGE_DEBREATH,         rc, debreath_en) \
+    ENTRY(rc,   debreath_strength,  U32,    MPP_ENC_RC_CFG_CHANGE_DEBREATH,         rc, debre_strength) \
+    ENTRY(rc,   qp_init,        S32,        MPP_ENC_RC_CFG_CHANGE_QP_INIT,          rc, qp_init) \
+    ENTRY(rc,   qp_min,         S32,        MPP_ENC_RC_CFG_CHANGE_QP_RANGE,         rc, qp_min) \
+    ENTRY(rc,   qp_max,         S32,        MPP_ENC_RC_CFG_CHANGE_QP_RANGE,         rc, qp_max) \
+    ENTRY(rc,   qp_min_i,       S32,        MPP_ENC_RC_CFG_CHANGE_QP_RANGE_I,       rc, qp_min_i) \
+    ENTRY(rc,   qp_max_i,       S32,        MPP_ENC_RC_CFG_CHANGE_QP_RANGE_I,       rc, qp_max_i) \
+    ENTRY(rc,   qp_step,        S32,        MPP_ENC_RC_CFG_CHANGE_QP_MAX_STEP,      rc, qp_max_step) \
+    ENTRY(rc,   qp_ip,          S32,        MPP_ENC_RC_CFG_CHANGE_QP_IP,            rc, qp_delta_ip) \
+    ENTRY(rc,   qp_vi,          S32,        MPP_ENC_RC_CFG_CHANGE_QP_VI,            rc, qp_delta_vi) \
+    ENTRY(rc,   hier_qp_en,     S32,        MPP_ENC_RC_CFG_CHANGE_HIER_QP,          rc, hier_qp_en) \
+    ENTRY(rc,   hier_qp_delta,  St,         MPP_ENC_RC_CFG_CHANGE_HIER_QP,          rc, hier_qp_delta) \
+    ENTRY(rc,   hier_frame_num, St,         MPP_ENC_RC_CFG_CHANGE_HIER_QP,          rc, hier_frame_num) \
+    ENTRY(rc,   stats_time,     S32,        MPP_ENC_RC_CFG_CHANGE_ST_TIME,          rc, stats_time) \
+    ENTRY(rc,   refresh_en,     U32,        MPP_ENC_RC_CFG_CHANGE_REFRESH,          rc, refresh_en) \
+    ENTRY(rc,   refresh_mode,   U32,        MPP_ENC_RC_CFG_CHANGE_REFRESH,          rc, refresh_mode) \
+    ENTRY(rc,   refresh_num,    U32,        MPP_ENC_RC_CFG_CHANGE_REFRESH,          rc, refresh_num) \
+    ENTRY(rc,   fqp_min_i,      S32,        MPP_ENC_RC_CFG_CHANGE_FQP,              rc, fqp_min_i) \
+    ENTRY(rc,   fqp_min_p,      S32,        MPP_ENC_RC_CFG_CHANGE_FQP,              rc, fqp_min_p) \
+    ENTRY(rc,   fqp_max_i,      S32,        MPP_ENC_RC_CFG_CHANGE_FQP,              rc, fqp_max_i) \
+    ENTRY(rc,   fqp_max_p,      S32,        MPP_ENC_RC_CFG_CHANGE_FQP,              rc, fqp_max_p) \
+    ENTRY(rc,   cu_qp_delta_depth, S32,     MPP_ENC_RC_CFG_CHANGE_QPDD,             rc, cu_qp_delta_depth) \
     /* prep config */ \
-    ENTRY(prep, width,          S32, RK_S32,            MPP_ENC_PREP_CFG_CHANGE_INPUT,          prep, width) \
-    ENTRY(prep, height,         S32, RK_S32,            MPP_ENC_PREP_CFG_CHANGE_INPUT,          prep, height) \
-    ENTRY(prep, hor_stride,     S32, RK_S32,            MPP_ENC_PREP_CFG_CHANGE_INPUT,          prep, hor_stride) \
-    ENTRY(prep, ver_stride,     S32, RK_S32,            MPP_ENC_PREP_CFG_CHANGE_INPUT,          prep, ver_stride) \
-    ENTRY(prep, format,         S32, MppFrameFormat,    MPP_ENC_PREP_CFG_CHANGE_FORMAT,         prep, format) \
-    ENTRY(prep, colorspace,     S32, MppFrameColorSpace,MPP_ENC_PREP_CFG_CHANGE_COLOR_SPACE,    prep, color) \
-    ENTRY(prep, colorprim,      S32, MppFrameColorPrimaries, MPP_ENC_PREP_CFG_CHANGE_COLOR_PRIME, prep, colorprim) \
-    ENTRY(prep, colortrc,       S32, MppFrameColorTransferCharacteristic, MPP_ENC_PREP_CFG_CHANGE_COLOR_TRC, prep, colortrc) \
-    ENTRY(prep, colorrange,     S32, MppFrameColorRange,MPP_ENC_PREP_CFG_CHANGE_COLOR_RANGE,    prep, range) \
-    ENTRY(prep, range,          S32, MppFrameColorRange,MPP_ENC_PREP_CFG_CHANGE_COLOR_RANGE,    prep, range) \
-    ENTRY(prep, rotation,       S32, MppEncRotationCfg, MPP_ENC_PREP_CFG_CHANGE_ROTATION,       prep, rotation_ext) \
-    ENTRY(prep, mirroring,      S32, RK_S32,            MPP_ENC_PREP_CFG_CHANGE_MIRRORING,      prep, mirroring_ext) \
-    ENTRY(prep, flip,           S32, RK_S32,            MPP_ENC_PREP_CFG_CHANGE_FLIP,           prep, flip) \
+    ENTRY(prep, width,          S32,        MPP_ENC_PREP_CFG_CHANGE_INPUT,          prep, width) \
+    ENTRY(prep, height,         S32,        MPP_ENC_PREP_CFG_CHANGE_INPUT,          prep, height) \
+    ENTRY(prep, hor_stride,     S32,        MPP_ENC_PREP_CFG_CHANGE_INPUT,          prep, hor_stride) \
+    ENTRY(prep, ver_stride,     S32,        MPP_ENC_PREP_CFG_CHANGE_INPUT,          prep, ver_stride) \
+    ENTRY(prep, format,         S32,        MPP_ENC_PREP_CFG_CHANGE_FORMAT,         prep, format) \
+    ENTRY(prep, format_out,     S32,        MPP_ENC_PREP_CFG_CHANGE_FORMAT,         prep, format_out) \
+    ENTRY(prep, chroma_ds_mode, S32,        MPP_ENC_PREP_CFG_CHANGE_FORMAT,         prep, chroma_ds_mode) \
+    ENTRY(prep, fix_chroma_en,  S32,        MPP_ENC_PREP_CFG_CHANGE_FORMAT,         prep, fix_chroma_en) \
+    ENTRY(prep, fix_chroma_u,   S32,        MPP_ENC_PREP_CFG_CHANGE_FORMAT,         prep, fix_chroma_u) \
+    ENTRY(prep, fix_chroma_v,   S32,        MPP_ENC_PREP_CFG_CHANGE_FORMAT,         prep, fix_chroma_v) \
+    ENTRY(prep, colorspace,     S32,        MPP_ENC_PREP_CFG_CHANGE_COLOR_SPACE,    prep, color) \
+    ENTRY(prep, colorprim,      S32,        MPP_ENC_PREP_CFG_CHANGE_COLOR_PRIME,    prep, colorprim) \
+    ENTRY(prep, colortrc,       S32,        MPP_ENC_PREP_CFG_CHANGE_COLOR_TRC,      prep, colortrc) \
+    ENTRY(prep, colorrange,     S32,        MPP_ENC_PREP_CFG_CHANGE_COLOR_RANGE,    prep, range) \
+    ENTRY(prep, range,          S32,        MPP_ENC_PREP_CFG_CHANGE_COLOR_RANGE,    prep, range) \
+    ENTRY(prep, range_out,      S32,        MPP_ENC_PREP_CFG_CHANGE_COLOR_RANGE,    prep, range_out) \
+    ENTRY(prep, rotation,       S32,        MPP_ENC_PREP_CFG_CHANGE_ROTATION,       prep, rotation_ext) \
+    ENTRY(prep, mirroring,      S32,        MPP_ENC_PREP_CFG_CHANGE_MIRRORING,      prep, mirroring_ext) \
+    ENTRY(prep, flip,           S32,        MPP_ENC_PREP_CFG_CHANGE_FLIP,           prep, flip) \
     /* codec coding config */ \
-    ENTRY(codec, type,          S32, MppCodingType,     0,                                      codec, coding) \
+    ENTRY(codec, type,          S32,        0,                                      codec, coding) \
     /* h264 config */ \
-    ENTRY(h264, stream_type,    S32, RK_S32,            MPP_ENC_H264_CFG_STREAM_TYPE,           codec.h264, stream_type) \
-    ENTRY(h264, profile,        S32, RK_S32,            MPP_ENC_H264_CFG_CHANGE_PROFILE,        codec.h264, profile) \
-    ENTRY(h264, level,          S32, RK_S32,            MPP_ENC_H264_CFG_CHANGE_PROFILE,        codec.h264, level) \
-    ENTRY(h264, poc_type,       U32, RK_U32,            MPP_ENC_H264_CFG_CHANGE_POC_TYPE,       codec.h264, poc_type) \
-    ENTRY(h264, log2_max_poc_lsb,   U32, RK_U32,        MPP_ENC_H264_CFG_CHANGE_MAX_POC_LSB,    codec.h264, log2_max_poc_lsb) \
-    ENTRY(h264, log2_max_frm_num,   U32, RK_U32,        MPP_ENC_H264_CFG_CHANGE_MAX_FRM_NUM,    codec.h264, log2_max_frame_num) \
-    ENTRY(h264, gaps_not_allowed,   U32, RK_U32,        MPP_ENC_H264_CFG_CHANGE_GAPS_IN_FRM_NUM, codec.h264, gaps_not_allowed) \
-    ENTRY(h264, cabac_en,       S32, RK_S32,            MPP_ENC_H264_CFG_CHANGE_ENTROPY,        codec.h264, entropy_coding_mode_ex) \
-    ENTRY(h264, cabac_idc,      S32, RK_S32,            MPP_ENC_H264_CFG_CHANGE_ENTROPY,        codec.h264, cabac_init_idc_ex) \
-    ENTRY(h264, trans8x8,       S32, RK_S32,            MPP_ENC_H264_CFG_CHANGE_TRANS_8x8,      codec.h264, transform8x8_mode_ex) \
-    ENTRY(h264, const_intra,    S32, RK_S32,            MPP_ENC_H264_CFG_CHANGE_CONST_INTRA,    codec.h264, constrained_intra_pred_mode) \
-    ENTRY(h264, scaling_list,   S32, RK_S32,            MPP_ENC_H264_CFG_CHANGE_SCALING_LIST,   codec.h264, scaling_list_mode) \
-    ENTRY(h264, cb_qp_offset,   S32, RK_S32,            MPP_ENC_H264_CFG_CHANGE_CHROMA_QP,      codec.h264, chroma_cb_qp_offset) \
-    ENTRY(h264, cr_qp_offset,   S32, RK_S32,            MPP_ENC_H264_CFG_CHANGE_CHROMA_QP,      codec.h264, chroma_cr_qp_offset) \
-    ENTRY(h264, dblk_disable,   S32, RK_S32,            MPP_ENC_H264_CFG_CHANGE_DEBLOCKING,     codec.h264, deblock_disable) \
-    ENTRY(h264, dblk_alpha,     S32, RK_S32,            MPP_ENC_H264_CFG_CHANGE_DEBLOCKING,     codec.h264, deblock_offset_alpha) \
-    ENTRY(h264, dblk_beta,      S32, RK_S32,            MPP_ENC_H264_CFG_CHANGE_DEBLOCKING,     codec.h264, deblock_offset_beta) \
-    ENTRY(h264, qp_init,        S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_QP_INIT,          rc, qp_init) \
-    ENTRY(h264, qp_min,         S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_QP_RANGE,         rc, qp_min) \
-    ENTRY(h264, qp_max,         S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_QP_RANGE,         rc, qp_max) \
-    ENTRY(h264, qp_min_i,       S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_QP_RANGE_I,       rc, qp_min_i) \
-    ENTRY(h264, qp_max_i,       S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_QP_RANGE_I,       rc, qp_max_i) \
-    ENTRY(h264, qp_step,        S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_QP_MAX_STEP,      rc, qp_max_step) \
-    ENTRY(h264, qp_delta_ip,    S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_QP_IP,            rc, qp_delta_ip) \
-    ENTRY(h264, max_tid,        S32, RK_S32,            MPP_ENC_H264_CFG_CHANGE_MAX_TID,        codec.h264, max_tid) \
-    ENTRY(h264, max_ltr,        S32, RK_S32,            MPP_ENC_H264_CFG_CHANGE_MAX_LTR,        codec.h264, max_ltr_frames) \
-    ENTRY(h264, prefix_mode,    S32, RK_S32,            MPP_ENC_H264_CFG_CHANGE_ADD_PREFIX,     codec.h264, prefix_mode) \
-    ENTRY(h264, base_layer_pid, S32, RK_S32,            MPP_ENC_H264_CFG_CHANGE_BASE_LAYER_PID, codec.h264, base_layer_pid) \
-    ENTRY(h264, constraint_set, U32, RK_U32,            MPP_ENC_H264_CFG_CHANGE_CONSTRAINT_SET, codec.h264, constraint_set) \
+    ENTRY(h264, stream_type,    S32,        MPP_ENC_H264_CFG_STREAM_TYPE,           codec.h264, stream_type) \
+    ENTRY(h264, profile,        S32,        MPP_ENC_H264_CFG_CHANGE_PROFILE,        codec.h264, profile) \
+    ENTRY(h264, level,          S32,        MPP_ENC_H264_CFG_CHANGE_PROFILE,        codec.h264, level) \
+    ENTRY(h264, poc_type,       U32,        MPP_ENC_H264_CFG_CHANGE_POC_TYPE,       codec.h264, poc_type) \
+    ENTRY(h264, log2_max_poc_lsb,   U32,    MPP_ENC_H264_CFG_CHANGE_MAX_POC_LSB,    codec.h264, log2_max_poc_lsb) \
+    ENTRY(h264, log2_max_frm_num,   U32,    MPP_ENC_H264_CFG_CHANGE_MAX_FRM_NUM,    codec.h264, log2_max_frame_num) \
+    ENTRY(h264, gaps_not_allowed,   U32,    MPP_ENC_H264_CFG_CHANGE_GAPS_IN_FRM_NUM, codec.h264, gaps_not_allowed) \
+    ENTRY(h264, cabac_en,       S32,        MPP_ENC_H264_CFG_CHANGE_ENTROPY,        codec.h264, entropy_coding_mode_ex) \
+    ENTRY(h264, cabac_idc,      S32,        MPP_ENC_H264_CFG_CHANGE_ENTROPY,        codec.h264, cabac_init_idc_ex) \
+    ENTRY(h264, trans8x8,       S32,        MPP_ENC_H264_CFG_CHANGE_TRANS_8x8,      codec.h264, transform8x8_mode_ex) \
+    ENTRY(h264, const_intra,    S32,        MPP_ENC_H264_CFG_CHANGE_CONST_INTRA,    codec.h264, constrained_intra_pred_mode) \
+    ENTRY(h264, scaling_list,   S32,        MPP_ENC_H264_CFG_CHANGE_SCALING_LIST,   codec.h264, scaling_list_mode) \
+    ENTRY(h264, cb_qp_offset,   S32,        MPP_ENC_H264_CFG_CHANGE_CHROMA_QP,      codec.h264, chroma_cb_qp_offset) \
+    ENTRY(h264, cr_qp_offset,   S32,        MPP_ENC_H264_CFG_CHANGE_CHROMA_QP,      codec.h264, chroma_cr_qp_offset) \
+    ENTRY(h264, dblk_disable,   S32,        MPP_ENC_H264_CFG_CHANGE_DEBLOCKING,     codec.h264, deblock_disable) \
+    ENTRY(h264, dblk_alpha,     S32,        MPP_ENC_H264_CFG_CHANGE_DEBLOCKING,     codec.h264, deblock_offset_alpha) \
+    ENTRY(h264, dblk_beta,      S32,        MPP_ENC_H264_CFG_CHANGE_DEBLOCKING,     codec.h264, deblock_offset_beta) \
+    ENTRY(h264, qp_init,        S32,        MPP_ENC_RC_CFG_CHANGE_QP_INIT,          rc, qp_init) \
+    ENTRY(h264, qp_min,         S32,        MPP_ENC_RC_CFG_CHANGE_QP_RANGE,         rc, qp_min) \
+    ENTRY(h264, qp_max,         S32,        MPP_ENC_RC_CFG_CHANGE_QP_RANGE,         rc, qp_max) \
+    ENTRY(h264, qp_min_i,       S32,        MPP_ENC_RC_CFG_CHANGE_QP_RANGE_I,       rc, qp_min_i) \
+    ENTRY(h264, qp_max_i,       S32,        MPP_ENC_RC_CFG_CHANGE_QP_RANGE_I,       rc, qp_max_i) \
+    ENTRY(h264, qp_step,        S32,        MPP_ENC_RC_CFG_CHANGE_QP_MAX_STEP,      rc, qp_max_step) \
+    ENTRY(h264, qp_delta_ip,    S32,        MPP_ENC_RC_CFG_CHANGE_QP_IP,            rc, qp_delta_ip) \
+    ENTRY(h264, max_tid,        S32,        MPP_ENC_H264_CFG_CHANGE_MAX_TID,        codec.h264, max_tid) \
+    ENTRY(h264, max_ltr,        S32,        MPP_ENC_H264_CFG_CHANGE_MAX_LTR,        codec.h264, max_ltr_frames) \
+    ENTRY(h264, prefix_mode,    S32,        MPP_ENC_H264_CFG_CHANGE_ADD_PREFIX,     codec.h264, prefix_mode) \
+    ENTRY(h264, base_layer_pid, S32,        MPP_ENC_H264_CFG_CHANGE_BASE_LAYER_PID, codec.h264, base_layer_pid) \
+    ENTRY(h264, constraint_set, U32,        MPP_ENC_H264_CFG_CHANGE_CONSTRAINT_SET, codec.h264, constraint_set) \
     /* h265 config*/ \
-    ENTRY(h265, profile,        S32, RK_S32,            MPP_ENC_H265_CFG_PROFILE_LEVEL_TILER_CHANGE,    codec.h265, profile) \
-    ENTRY(h265, level,          S32, RK_S32,            MPP_ENC_H265_CFG_PROFILE_LEVEL_TILER_CHANGE,    codec.h265, level) \
-    ENTRY(h265, scaling_list,   U32, RK_U32,            MPP_ENC_H265_CFG_TRANS_CHANGE,                  codec.h265, trans_cfg.defalut_ScalingList_enable) \
-    ENTRY(h265, cb_qp_offset,   S32, RK_S32,            MPP_ENC_H265_CFG_TRANS_CHANGE,                  codec.h265, trans_cfg.cb_qp_offset) \
-    ENTRY(h265, cr_qp_offset,   S32, RK_S32,            MPP_ENC_H265_CFG_TRANS_CHANGE,                  codec.h265, trans_cfg.cr_qp_offset) \
-    ENTRY(h265, dblk_disable,   U32, RK_U32,            MPP_ENC_H265_CFG_DBLK_CHANGE,                   codec.h265, dblk_cfg.slice_deblocking_filter_disabled_flag) \
-    ENTRY(h265, dblk_alpha,     S32, RK_S32,            MPP_ENC_H265_CFG_DBLK_CHANGE,                   codec.h265, dblk_cfg.slice_beta_offset_div2) \
-    ENTRY(h265, dblk_beta,      S32, RK_S32,            MPP_ENC_H265_CFG_DBLK_CHANGE,                   codec.h265, dblk_cfg.slice_tc_offset_div2) \
-    ENTRY(h265, qp_init,        S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_QP_INIT,          rc, qp_init) \
-    ENTRY(h265, qp_min,         S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_QP_RANGE,         rc, qp_min) \
-    ENTRY(h265, qp_max,         S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_QP_RANGE,         rc, qp_max) \
-    ENTRY(h265, qp_min_i,       S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_QP_RANGE_I,       rc, qp_min_i) \
-    ENTRY(h265, qp_max_i,       S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_QP_RANGE_I,       rc, qp_max_i) \
-    ENTRY(h265, qp_step,        S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_QP_MAX_STEP,      rc, qp_max_step) \
-    ENTRY(h265, qp_delta_ip,    S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_QP_IP,            rc, qp_delta_ip) \
-    ENTRY(h265, sao_luma_disable,   S32, RK_S32,        MPP_ENC_H265_CFG_SAO_CHANGE,            codec.h265, sao_cfg.slice_sao_luma_disable) \
-    ENTRY(h265, sao_chroma_disable, S32, RK_S32,        MPP_ENC_H265_CFG_SAO_CHANGE,            codec.h265, sao_cfg.slice_sao_chroma_disable) \
-    ENTRY(h265, lpf_acs_sli_en, U32, RK_U32,            MPP_ENC_H265_CFG_SLICE_LPFACS_CHANGE,   codec.h265, lpf_acs_sli_en) \
-    ENTRY(h265, lpf_acs_tile_disable, U32, RK_U32,      MPP_ENC_H265_CFG_TILE_LPFACS_CHANGE,    codec.h265, lpf_acs_tile_disable) \
-    ENTRY(h265, auto_tile,      S32, RK_S32,            MPP_ENC_H265_CFG_TILE_CHANGE,           codec.h265, auto_tile) \
+    ENTRY(h265, profile,        S32,        MPP_ENC_H265_CFG_PROFILE_LEVEL_TILER_CHANGE,    codec.h265, profile) \
+    ENTRY(h265, tier   ,        S32,        MPP_ENC_H265_CFG_PROFILE_LEVEL_TILER_CHANGE,    codec.h265, tier) \
+    ENTRY(h265, level,          S32,        MPP_ENC_H265_CFG_PROFILE_LEVEL_TILER_CHANGE,    codec.h265, level) \
+    ENTRY(h265, scaling_list,   U32,        MPP_ENC_H265_CFG_TRANS_CHANGE,                  codec.h265, trans_cfg.defalut_ScalingList_enable) \
+    ENTRY(h265, cb_qp_offset,   S32,        MPP_ENC_H265_CFG_TRANS_CHANGE,                  codec.h265, trans_cfg.cb_qp_offset) \
+    ENTRY(h265, cr_qp_offset,   S32,        MPP_ENC_H265_CFG_TRANS_CHANGE,                  codec.h265, trans_cfg.cr_qp_offset) \
+    ENTRY(h265, dblk_disable,   U32,        MPP_ENC_H265_CFG_DBLK_CHANGE,                   codec.h265, dblk_cfg.slice_deblocking_filter_disabled_flag) \
+    ENTRY(h265, dblk_alpha,     S32,        MPP_ENC_H265_CFG_DBLK_CHANGE,                   codec.h265, dblk_cfg.slice_beta_offset_div2) \
+    ENTRY(h265, dblk_beta,      S32,        MPP_ENC_H265_CFG_DBLK_CHANGE,                   codec.h265, dblk_cfg.slice_tc_offset_div2) \
+    ENTRY(h265, qp_init,        S32,        MPP_ENC_RC_CFG_CHANGE_QP_INIT,          rc, qp_init) \
+    ENTRY(h265, qp_min,         S32,        MPP_ENC_RC_CFG_CHANGE_QP_RANGE,         rc, qp_min) \
+    ENTRY(h265, qp_max,         S32,        MPP_ENC_RC_CFG_CHANGE_QP_RANGE,         rc, qp_max) \
+    ENTRY(h265, qp_min_i,       S32,        MPP_ENC_RC_CFG_CHANGE_QP_RANGE_I,       rc, qp_min_i) \
+    ENTRY(h265, qp_max_i,       S32,        MPP_ENC_RC_CFG_CHANGE_QP_RANGE_I,       rc, qp_max_i) \
+    ENTRY(h265, qp_step,        S32,        MPP_ENC_RC_CFG_CHANGE_QP_MAX_STEP,      rc, qp_max_step) \
+    ENTRY(h265, qp_delta_ip,    S32,        MPP_ENC_RC_CFG_CHANGE_QP_IP,            rc, qp_delta_ip) \
+    ENTRY(h265, sao_luma_disable,   S32,    MPP_ENC_H265_CFG_SAO_CHANGE,            codec.h265, sao_cfg.slice_sao_luma_disable) \
+    ENTRY(h265, sao_chroma_disable, S32,    MPP_ENC_H265_CFG_SAO_CHANGE,            codec.h265, sao_cfg.slice_sao_chroma_disable) \
+    ENTRY(h265, lpf_acs_sli_en, U32,        MPP_ENC_H265_CFG_SLICE_LPFACS_CHANGE,   codec.h265, lpf_acs_sli_en) \
+    ENTRY(h265, lpf_acs_tile_disable, U32,  MPP_ENC_H265_CFG_TILE_LPFACS_CHANGE,    codec.h265, lpf_acs_tile_disable) \
+    ENTRY(h265, auto_tile,      S32,        MPP_ENC_H265_CFG_TILE_CHANGE,           codec.h265, auto_tile) \
+    ENTRY(h265, max_tid,        S32,        MPP_ENC_H265_CFG_CHANGE_MAX_TID,        codec.h265, max_tid) \
+    ENTRY(h265, max_ltr,        S32,        MPP_ENC_H265_CFG_CHANGE_MAX_LTR,        codec.h265, max_ltr_frames) \
+    ENTRY(h265, base_layer_pid, S32,        MPP_ENC_H265_CFG_CHANGE_BASE_LAYER_PID, codec.h265, base_layer_pid) \
+    ENTRY(h265, const_intra,    S32,        MPP_ENC_H265_CFG_CHANGE_CONST_INTRA,    codec.h265, const_intra_pred) \
+    ENTRY(h265, lcu_size,       S32,        MPP_ENC_H265_CFG_CHANGE_LCU_SIZE,       codec.h265, max_cu_size) \
     /* vp8 config */ \
-    ENTRY(vp8,  qp_init,        S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_QP_INIT,          rc, qp_init) \
-    ENTRY(vp8,  qp_min,         S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_QP_RANGE,         rc, qp_min) \
-    ENTRY(vp8,  qp_max,         S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_QP_RANGE,         rc, qp_max) \
-    ENTRY(vp8,  qp_min_i,       S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_QP_RANGE_I,       rc, qp_min_i) \
-    ENTRY(vp8,  qp_max_i,       S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_QP_RANGE_I,       rc, qp_max_i) \
-    ENTRY(vp8,  qp_step,        S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_QP_MAX_STEP,      rc, qp_max_step) \
-    ENTRY(vp8,  qp_delta_ip,    S32, RK_S32,            MPP_ENC_RC_CFG_CHANGE_QP_IP,            rc, qp_delta_ip) \
-    ENTRY(vp8,  disable_ivf,    S32, RK_S32,            MPP_ENC_VP8_CFG_CHANGE_DIS_IVF,         codec.vp8, disable_ivf) \
+    ENTRY(vp8,  qp_init,        S32,        MPP_ENC_RC_CFG_CHANGE_QP_INIT,          rc, qp_init) \
+    ENTRY(vp8,  qp_min,         S32,        MPP_ENC_RC_CFG_CHANGE_QP_RANGE,         rc, qp_min) \
+    ENTRY(vp8,  qp_max,         S32,        MPP_ENC_RC_CFG_CHANGE_QP_RANGE,         rc, qp_max) \
+    ENTRY(vp8,  qp_min_i,       S32,        MPP_ENC_RC_CFG_CHANGE_QP_RANGE_I,       rc, qp_min_i) \
+    ENTRY(vp8,  qp_max_i,       S32,        MPP_ENC_RC_CFG_CHANGE_QP_RANGE_I,       rc, qp_max_i) \
+    ENTRY(vp8,  qp_step,        S32,        MPP_ENC_RC_CFG_CHANGE_QP_MAX_STEP,      rc, qp_max_step) \
+    ENTRY(vp8,  qp_delta_ip,    S32,        MPP_ENC_RC_CFG_CHANGE_QP_IP,            rc, qp_delta_ip) \
+    ENTRY(vp8,  disable_ivf,    S32,        MPP_ENC_VP8_CFG_CHANGE_DIS_IVF,         codec.vp8, disable_ivf) \
     /* jpeg config */ \
-    ENTRY(jpeg, quant,          S32, RK_S32,            MPP_ENC_JPEG_CFG_CHANGE_QP,             codec.jpeg, quant) \
-    ENTRY(jpeg, qtable_y,       Ptr, RK_U8*,            MPP_ENC_JPEG_CFG_CHANGE_QTABLE,         codec.jpeg, qtable_y) \
-    ENTRY(jpeg, qtable_u,       Ptr, RK_U8*,            MPP_ENC_JPEG_CFG_CHANGE_QTABLE,         codec.jpeg, qtable_u) \
-    ENTRY(jpeg, qtable_v,       Ptr, RK_U8*,            MPP_ENC_JPEG_CFG_CHANGE_QTABLE,         codec.jpeg, qtable_v) \
-    ENTRY(jpeg, q_factor,       S32, RK_S32,            MPP_ENC_JPEG_CFG_CHANGE_QFACTOR,        codec.jpeg, q_factor) \
-    ENTRY(jpeg, qf_max,         S32, RK_S32,            MPP_ENC_JPEG_CFG_CHANGE_QFACTOR,        codec.jpeg, qf_max) \
-    ENTRY(jpeg, qf_min,         S32, RK_S32,            MPP_ENC_JPEG_CFG_CHANGE_QFACTOR,        codec.jpeg, qf_min) \
+    ENTRY(jpeg, quant,          S32,        MPP_ENC_JPEG_CFG_CHANGE_QP,             codec.jpeg, quant) \
+    ENTRY(jpeg, qtable_y,       Ptr,        MPP_ENC_JPEG_CFG_CHANGE_QTABLE,         codec.jpeg, qtable_y) \
+    ENTRY(jpeg, qtable_u,       Ptr,        MPP_ENC_JPEG_CFG_CHANGE_QTABLE,         codec.jpeg, qtable_u) \
+    ENTRY(jpeg, qtable_v,       Ptr,        MPP_ENC_JPEG_CFG_CHANGE_QTABLE,         codec.jpeg, qtable_v) \
+    ENTRY(jpeg, q_factor,       S32,        MPP_ENC_JPEG_CFG_CHANGE_QFACTOR,        codec.jpeg, q_factor) \
+    ENTRY(jpeg, qf_max,         S32,        MPP_ENC_JPEG_CFG_CHANGE_QFACTOR,        codec.jpeg, qf_max) \
+    ENTRY(jpeg, qf_min,         S32,        MPP_ENC_JPEG_CFG_CHANGE_QFACTOR,        codec.jpeg, qf_min) \
     /* split config */ \
-    ENTRY(split, mode,          U32, RK_U32,            MPP_ENC_SPLIT_CFG_CHANGE_MODE,          split, split_mode) \
-    ENTRY(split, arg,           U32, RK_U32,            MPP_ENC_SPLIT_CFG_CHANGE_ARG,           split, split_arg) \
-    ENTRY(split, out,           U32, RK_U32,            MPP_ENC_SPLIT_CFG_CHANGE_OUTPUT,        split, split_out) \
+    ENTRY(split, mode,          U32,        MPP_ENC_SPLIT_CFG_CHANGE_MODE,          split, split_mode) \
+    ENTRY(split, arg,           U32,        MPP_ENC_SPLIT_CFG_CHANGE_ARG,           split, split_arg) \
+    ENTRY(split, out,           U32,        MPP_ENC_SPLIT_CFG_CHANGE_OUTPUT,        split, split_out) \
     /* hardware detail config */ \
-    ENTRY(hw,   qp_row,         S32, RK_S32,            MPP_ENC_HW_CFG_CHANGE_QP_ROW,           hw, qp_delta_row) \
-    ENTRY(hw,   qp_row_i,       S32, RK_S32,            MPP_ENC_HW_CFG_CHANGE_QP_ROW_I,         hw, qp_delta_row_i) \
-    ENTRY(hw,   aq_thrd_i,      St,  RK_S32 *,          MPP_ENC_HW_CFG_CHANGE_AQ_THRD_I,        hw, aq_thrd_i) \
-    ENTRY(hw,   aq_thrd_p,      St,  RK_S32 *,          MPP_ENC_HW_CFG_CHANGE_AQ_THRD_P,        hw, aq_thrd_p) \
-    ENTRY(hw,   aq_step_i,      St,  RK_S32 *,          MPP_ENC_HW_CFG_CHANGE_AQ_STEP_I,        hw, aq_step_i) \
-    ENTRY(hw,   aq_step_p,      St,  RK_S32 *,          MPP_ENC_HW_CFG_CHANGE_AQ_STEP_P,        hw, aq_step_p) \
-    ENTRY(hw,   mb_rc_disable,  S32, RK_S32,            MPP_ENC_HW_CFG_CHANGE_MB_RC,            hw, mb_rc_disable) \
-    ENTRY(hw,   mode_bias,      St,  RK_S32 *,          MPP_ENC_HW_CFG_CHANGE_CU_MODE_BIAS,     hw, mode_bias) \
-    ENTRY(hw,   skip_bias_en,   S32, RK_S32,            MPP_ENC_HW_CFG_CHANGE_CU_SKIP_BIAS,     hw, skip_bias_en) \
-    ENTRY(hw,   skip_sad,       S32, RK_S32,            MPP_ENC_HW_CFG_CHANGE_CU_SKIP_BIAS,     hw, skip_sad) \
-    ENTRY(hw,   skip_bias,      S32, RK_S32,            MPP_ENC_HW_CFG_CHANGE_CU_SKIP_BIAS,     hw, skip_bias) \
-    ENTRY(hw,   qbias_i,        S32, RK_S32,            MPP_ENC_HW_CFG_CHANGE_QBIAS_I,          hw, qbias_i) \
-    ENTRY(hw,   qbias_p,        S32, RK_S32,            MPP_ENC_HW_CFG_CHANGE_QBIAS_P,          hw, qbias_p) \
-    ENTRY(hw,   qbias_en,       S32, RK_S32,            MPP_ENC_HW_CFG_CHANGE_QBIAS_EN,         hw, qbias_en) \
+    ENTRY(hw,   qp_row,         S32,        MPP_ENC_HW_CFG_CHANGE_QP_ROW,           hw, qp_delta_row) \
+    ENTRY(hw,   qp_row_i,       S32,        MPP_ENC_HW_CFG_CHANGE_QP_ROW_I,         hw, qp_delta_row_i) \
+    ENTRY(hw,   aq_thrd_i,      St,         MPP_ENC_HW_CFG_CHANGE_AQ_THRD_I,        hw, aq_thrd_i) \
+    ENTRY(hw,   aq_thrd_p,      St,         MPP_ENC_HW_CFG_CHANGE_AQ_THRD_P,        hw, aq_thrd_p) \
+    ENTRY(hw,   aq_step_i,      St,         MPP_ENC_HW_CFG_CHANGE_AQ_STEP_I,        hw, aq_step_i) \
+    ENTRY(hw,   aq_step_p,      St,         MPP_ENC_HW_CFG_CHANGE_AQ_STEP_P,        hw, aq_step_p) \
+    ENTRY(hw,   mb_rc_disable,  S32,        MPP_ENC_HW_CFG_CHANGE_MB_RC,            hw, mb_rc_disable) \
+    ENTRY(hw,   mode_bias,      St,         MPP_ENC_HW_CFG_CHANGE_CU_MODE_BIAS,     hw, mode_bias) \
+    ENTRY(hw,   skip_bias_en,   S32,        MPP_ENC_HW_CFG_CHANGE_CU_SKIP_BIAS,     hw, skip_bias_en) \
+    ENTRY(hw,   skip_sad,       S32,        MPP_ENC_HW_CFG_CHANGE_CU_SKIP_BIAS,     hw, skip_sad) \
+    ENTRY(hw,   skip_bias,      S32,        MPP_ENC_HW_CFG_CHANGE_CU_SKIP_BIAS,     hw, skip_bias) \
+    ENTRY(hw,   qbias_i,        S32,        MPP_ENC_HW_CFG_CHANGE_QBIAS_I,          hw, qbias_i) \
+    ENTRY(hw,   qbias_p,        S32,        MPP_ENC_HW_CFG_CHANGE_QBIAS_P,          hw, qbias_p) \
+    ENTRY(hw,   qbias_en,       S32,        MPP_ENC_HW_CFG_CHANGE_QBIAS_EN,         hw, qbias_en) \
     /* quality fine tuning config */ \
-    ENTRY(tune, scene_mode,     S32, MppEncSceneMode,   MPP_ENC_TUNE_CFG_CHANGE_SCENE_MODE,     tune, scene_mode)
-
-static MppEncCfgInfo *mpp_enc_cfg_flaten(MppTrie trie, MppCfgApi **cfgs)
-{
-    MppEncCfgInfo *info = NULL;
-    MppTrieNode *node_root = mpp_trie_node_root(trie);
-    RK_S32 node_count = mpp_trie_get_node_count(trie);
-    RK_S32 info_count = mpp_trie_get_info_count(trie);
-    MppTrieNode *node_trie;
-    char *buf = NULL;
-    RK_S32 pos = 0;
-    RK_S32 len = 0;
-    RK_S32 i;
-
-    pos += node_count * sizeof(*node_root);
-
-    mpp_enc_cfg_dbg_info("info node offset %d\n", pos);
-
-    /* update info size and string name size */
-    for (i = 0; i < info_count; i++) {
-        const char *name = cfgs[i]->name;
-        const char **info_trie = mpp_trie_get_info(trie, name);
-
-        mpp_assert(*info_trie == name);
-        len = strlen(name);
-        pos += sizeof(MppCfgInfoNode) + MPP_ALIGN(len + 1, sizeof(RK_U64));
-    }
-
-    len = pos + sizeof(*info);
-    mpp_enc_cfg_dbg_info("tire + info size %d total %d\n", pos, len);
-
-    info = mpp_malloc_size(MppEncCfgInfo, len);
-    if (NULL == info)
-        return NULL;
-
-    memcpy(info->trie_node, node_root, sizeof(*node_root) * node_count);
-
-    node_root = info->trie_node;
-    pos = node_count * sizeof(*node_root);
-    buf = (char *)node_root + pos;
-
-    for (i = 0; i < info_count; i++) {
-        MppCfgInfoNode *node_info = (MppCfgInfoNode *)buf;
-        MppCfgApi *api = cfgs[i];
-        const char *name = api->name;
-        RK_S32 node_size;
-
-        node_trie = mpp_trie_get_node(node_root, name);
-        node_trie->id = pos;
-
-        node_info->name_len     = MPP_ALIGN(strlen(name) + 1, sizeof(RK_U64));
-        node_info->data_type    = api->data_type;
-        node_info->flag_offset  = api->flag_offset;
-        node_info->flag_value   = api->flag_value;
-        node_info->data_offset  = api->data_offset;
-        node_info->data_size    = api->data_size;
-        node_info->node_next    = 0;
-
-        node_size = node_info->name_len + sizeof(*node_info);
-        node_info->node_size    = node_size;
-
-        mpp_cfg_node_fixup_func(node_info);
-
-        strcpy(node_info->name, name);
-
-        mpp_enc_cfg_dbg_info("cfg %s offset %d size %d update %d flag %x\n",
-                             node_info->name,
-                             node_info->data_offset, node_info->data_size,
-                             node_info->flag_offset, node_info->flag_value);
-
-        pos += node_size;
-        buf += node_size;
-    }
-
-    mpp_enc_cfg_dbg_info("total size %d +H %d\n", pos, pos + sizeof(info->head));
-
-    info->head.info_size  = pos;
-    info->head.info_count = info_count;
-    info->head.node_count = node_count;
-    info->head.cfg_size   = sizeof(MppEncCfgSet);
-
-    return info;
-}
+    ENTRY(tune, scene_mode,     S32,        MPP_ENC_TUNE_CFG_CHANGE_SCENE_MODE,     tune, scene_mode) \
+    ENTRY(tune, deblur_en,      S32,        MPP_ENC_TUNE_CFG_CHANGE_DEBLUR_EN,      tune, deblur_en) \
+    ENTRY(tune, deblur_str,     S32,        MPP_ENC_TUNE_CFG_CHANGE_DEBLUR_STR,     tune, deblur_str) \
+    ENTRY(tune, anti_flicker_str,S32,       MPP_ENC_TUNE_CFG_CHANGE_ANTI_FLICKER_STR,tune, anti_flicker_str) \
+    ENTRY(tune, lambda_idx_i,   S32,        MPP_ENC_TUNE_CFG_CHANGE_LAMBDA_IDX_I,   tune, lambda_idx_i) \
+    ENTRY(tune, lambda_idx_p,   S32,        MPP_ENC_TUNE_CFG_CHANGE_LAMBDA_IDX_P,   tune, lambda_idx_p) \
+    ENTRY(tune, atr_str_i,      S32,        MPP_ENC_TUNE_CFG_CHANGE_ATR_STR_I,   tune, atr_str_i) \
+    ENTRY(tune, atr_str_p,      S32,        MPP_ENC_TUNE_CFG_CHANGE_ATR_STR_P,   tune, atr_str_p) \
+    ENTRY(tune, atl_str,        S32,        MPP_ENC_TUNE_CFG_CHANGE_ATL_STR,     tune, atl_str) \
+    ENTRY(tune, sao_str_i,      S32,        MPP_ENC_TUNE_CFG_CHANGE_SAO_STR_I,   tune, sao_str_i) \
+    ENTRY(tune, sao_str_p,      S32,        MPP_ENC_TUNE_CFG_CHANGE_SAO_STR_P,   tune, sao_str_p) \
+    ENTRY(tune, rc_container,   S32,        MPP_ENC_TUNE_CFG_CHANGE_RC_CONTAINER,   tune, rc_container) \
+    ENTRY(tune, vmaf_opt,       S32,        MPP_ENC_TUNE_CFG_CHANGE_VMAF_OPT,       tune, vmaf_opt)
 
 MppEncCfgService::MppEncCfgService() :
-    mInfo(NULL),
-    mCfgSize(0)
+    mTrie(NULL)
 {
-    ENTRY_TABLE(EXPAND_AS_API);
-
-    MppCfgApi *cfgs[] = {
-        ENTRY_TABLE(EXPAND_AS_ARRAY)
-    };
-
-    RK_S32 cfg_cnt = MPP_ARRAY_ELEMS(cfgs);
-    MppTrie trie;
     MPP_RET ret;
-    RK_S32 i;
 
-    ret = mpp_trie_init(&trie, 1732, cfg_cnt);
+    mpp_env_get_u32("mpp_enc_cfg_debug", &mpp_enc_cfg_debug, 0);
+
+    ret = mpp_trie_init(&mTrie, sizeof(MppCfgInfo));
     if (ret) {
-        mpp_err_f("failed to init enc cfg set trie\n");
+        mpp_err_f("failed to init enc cfg set trie ret %d\n", ret);
         return ;
     }
 
-    for (i = 0; i < cfg_cnt; i++)
-        mpp_trie_add_info(trie, &cfgs[i]->name);
+    ENTRY_TABLE(EXPAND_AS_TRIE)
 
-    mInfo = mpp_enc_cfg_flaten(trie, cfgs);
-    mCfgSize = mInfo->head.cfg_size;
+    mpp_trie_add_info(mTrie, NULL, NULL);
 
-    mpp_enc_cfg_dbg_func("node cnt: %d\n", get_node_count());
+    mHead.node_count = mpp_trie_get_node_count(mTrie);
+    mHead.info_count = mpp_trie_get_info_count(mTrie);
+    mHead.info_size = mpp_trie_get_buf_size(mTrie);
 
-    mpp_trie_deinit(trie);
+    mpp_enc_cfg_dbg_func("node cnt: %d\n", mHead.node_count);
 }
 
 MppEncCfgService::~MppEncCfgService()
 {
-    MPP_FREE(mInfo);
+    if (mTrie) {
+        mpp_trie_deinit(mTrie);
+        mTrie = NULL;
+    }
+}
+
+MppTrieInfo *MppEncCfgService::get_info(const char *name)
+{
+    return mpp_trie_get_info(mTrie, name);
+}
+
+MppTrieInfo *MppEncCfgService::get_info_first()
+{
+    if (NULL == mTrie)
+        return NULL;
+
+    return mpp_trie_get_info_first(mTrie);
 }
 
-MppCfgInfoNode *MppEncCfgService::get_info_root()
+MppTrieInfo *MppEncCfgService::get_info_next(MppTrieInfo *node)
 {
-    if (NULL == mInfo)
+    if (NULL == mTrie)
         return NULL;
 
-    return (MppCfgInfoNode *)(mInfo->trie_node + mInfo->head.node_count);
+    return mpp_trie_get_info_next(mTrie, node);
 }
 
 static void mpp_enc_cfg_set_default(MppEncCfgSet *cfg)
@@ -412,6 +331,10 @@ static void mpp_enc_cfg_set_default(MppEncCfgSet *cfg)
     cfg->prep.color = MPP_FRAME_SPC_UNSPECIFIED;
     cfg->prep.colorprim = MPP_FRAME_PRI_UNSPECIFIED;
     cfg->prep.colortrc = MPP_FRAME_TRC_UNSPECIFIED;
+    cfg->prep.format_out = MPP_CHROMA_UNSPECIFIED;
+    cfg->prep.chroma_ds_mode = MPP_FRAME_CHROMA_DOWN_SAMPLE_MODE_NONE;
+    cfg->prep.fix_chroma_en = 0;
+    cfg->prep.range_out = MPP_FRAME_RANGE_UNSPECIFIED;
 
     for (i = 0; i < MPP_ARRAY_ELEMS(cfg->hw.mode_bias); i++)
         cfg->hw.mode_bias[i] = 8;
@@ -423,7 +346,6 @@ static void mpp_enc_cfg_set_default(MppEncCfgSet *cfg)
 MPP_RET mpp_enc_cfg_init(MppEncCfg *cfg)
 {
     MppEncCfgImpl *p = NULL;
-    RK_S32 cfg_size;
 
     if (NULL == cfg) {
         mpp_err_f("invalid NULL input config\n");
@@ -432,7 +354,6 @@ MPP_RET mpp_enc_cfg_init(MppEncCfg *cfg)
 
     mpp_env_get_u32("mpp_enc_cfg_debug", &mpp_enc_cfg_debug, 0);
 
-    cfg_size = MppEncCfgService::get()->get_cfg_size();
     p = mpp_calloc(MppEncCfgImpl, 1);
     if (NULL == p) {
         mpp_err_f("create encoder config failed %p\n", p);
@@ -440,8 +361,7 @@ MPP_RET mpp_enc_cfg_init(MppEncCfg *cfg)
         return MPP_ERR_NOMEM;
     }
 
-    mpp_assert(cfg_size == sizeof(p->cfg));
-    p->size = cfg_size;
+    p->size = sizeof(p->cfg);
     mpp_enc_cfg_set_default(&p->cfg);
 
     *cfg = p;
@@ -469,11 +389,12 @@ MPP_RET mpp_enc_cfg_deinit(MppEncCfg cfg)
             return MPP_ERR_NULL_PTR; \
         } \
         MppEncCfgImpl *p = (MppEncCfgImpl *)cfg; \
-        MppCfgInfoNode *info = MppEncCfgService::get()->get_info(name); \
+        MppTrieInfo *node = MppEncCfgService::get()->get_info(name); \
+        MppCfgInfo *info = (MppCfgInfo *)(node ? node->ctx : NULL); \
         if (CHECK_CFG_INFO(info, name, CFG_FUNC_TYPE_##cfg_type)) { \
             return MPP_NOK; \
         } \
-        mpp_enc_cfg_dbg_set("name %s type %s\n", info->name, cfg_type_names[info->data_type]); \
+        mpp_enc_cfg_dbg_set("name %s type %s\n", node->name, strof_cfg_type(info->data_type)); \
         MPP_RET ret = MPP_CFG_SET_##cfg_type(info, &p->cfg, val); \
         return ret; \
     }
@@ -493,11 +414,12 @@ ENC_CFG_SET_ACCESS(mpp_enc_cfg_set_st,  void *, St);
             return MPP_ERR_NULL_PTR; \
         } \
         MppEncCfgImpl *p = (MppEncCfgImpl *)cfg; \
-        MppCfgInfoNode *info = MppEncCfgService::get()->get_info(name); \
+        MppTrieInfo *node = MppEncCfgService::get()->get_info(name); \
+        MppCfgInfo *info = (MppCfgInfo *)(node ? node->ctx : NULL); \
         if (CHECK_CFG_INFO(info, name, CFG_FUNC_TYPE_##cfg_type)) { \
             return MPP_NOK; \
         } \
-        mpp_enc_cfg_dbg_set("name %s type %s\n", info->name, cfg_type_names[info->data_type]); \
+        mpp_enc_cfg_dbg_set("name %s type %s\n", node->name, strof_cfg_type(info->data_type)); \
         MPP_RET ret = MPP_CFG_GET_##cfg_type(info, &p->cfg, val); \
         return ret; \
     }
@@ -511,28 +433,26 @@ ENC_CFG_GET_ACCESS(mpp_enc_cfg_get_st,  void  , St);
 
 void mpp_enc_cfg_show(void)
 {
-    RK_S32 node_count = MppEncCfgService::get()->get_node_count();
-    RK_S32 info_count = MppEncCfgService::get()->get_info_count();
-    MppCfgInfoNode *info = MppEncCfgService::get()->get_info_root();
+    MppEncCfgService *srv = MppEncCfgService::get();
+    MppTrieInfo *root = srv->get_info_first();
 
     mpp_log("dumping valid configure string start\n");
 
-    if (info) {
-        char *p = (char *)info;
-        RK_S32 i;
+    if (root) {
+        MppTrieInfo *node = root;
 
-        for (i = 0; i < info_count; i++) {
-            info = (MppCfgInfoNode *)p;
+        do {
+            MppCfgInfo *info = (MppCfgInfo *)node->ctx;
 
-            mpp_log("%-25s type %s\n", info->name,
-                    cfg_type_names[info->data_type]);
+            mpp_log("%-25s type %s\n", node->name, strof_cfg_type(info->data_type));
 
-            p += info->node_size;
-        }
+            node = srv->get_info_next(node);
+            if (!node)
+                break;
+        } while (1);
     }
     mpp_log("dumping valid configure string done\n");
 
     mpp_log("total cfg count %d with %d node size %d\n",
-            info_count, node_count,
-            MppEncCfgService::get()->get_info_size());
+            srv->get_info_count(), srv->get_node_count(), srv->get_info_size());
 }
diff --git a/mpp/base/mpp_enc_ref.cpp b/mpp/base/mpp_enc_ref.cpp
index 46d0f9893..55a4b4a7d 100644
--- a/mpp/base/mpp_enc_ref.cpp
+++ b/mpp/base/mpp_enc_ref.cpp
@@ -434,6 +434,7 @@ static const MppEncRefCfgImpl default_ref_cfg = {
     .max_st_cfg         = 1,
     .lt_cfg_cnt         = 0,
     .st_cfg_cnt         = 1,
+    .max_tlayers        = 1,
     .lt_cfg             = NULL,
     .st_cfg             = &default_st_ref_cfg,
     .cpb_info           = { 1, 0, 1, 0, 0, 0, 0 },
diff --git a/mpp/base/mpp_enc_refs.cpp b/mpp/base/mpp_enc_refs.cpp
index 6a96be725..ddf25274f 100644
--- a/mpp/base/mpp_enc_refs.cpp
+++ b/mpp/base/mpp_enc_refs.cpp
@@ -599,6 +599,7 @@ MPP_RET mpp_enc_refs_dryrun(MppEncRefs refs)
 
     cleanup_cpb_refs(cpb);
 
+    cfg->max_tlayers = cpb->info.max_st_tid + 1;
     enc_refs_dbg_flow("dryrun start: lt_cfg %d st_cfg %d\n",
                       lt_cfg_cnt, st_cfg_cnt);
 
@@ -892,7 +893,7 @@ MPP_RET mpp_enc_refs_get_cpb(MppEncRefs refs, EncCpbStatus *status)
     }
 
     if (usr_cfg->force_flag & ENC_FORCE_PSKIP) {
-        frm->is_non_ref = 1;
+        frm->force_pskip = 1;
 
         usr_cfg->force_flag &= ~ENC_FORCE_PSKIP;
     }
diff --git a/mpp/base/mpp_meta.cpp b/mpp/base/mpp_meta.cpp
index 5ff6da417..1d379d012 100644
--- a/mpp/base/mpp_meta.cpp
+++ b/mpp/base/mpp_meta.cpp
@@ -49,12 +49,14 @@ static MppMetaDef meta_defs[] = {
     {   KEY_OUTPUT_INTRA,       TYPE_S32,       },
     {   KEY_INPUT_BLOCK,        TYPE_S32,       },
     {   KEY_OUTPUT_BLOCK,       TYPE_S32,       },
+    {   KEY_INPUT_IDR_REQ,      TYPE_S32,       },
 
     /* extra information for tsvc */
     {   KEY_TEMPORAL_ID,        TYPE_S32,       },
     {   KEY_LONG_REF_IDX,       TYPE_S32,       },
     {   KEY_ENC_AVERAGE_QP,     TYPE_S32,       },
     {   KEY_ENC_START_QP,       TYPE_S32,       },
+    {   KEY_ENC_BPS_RT,         TYPE_S32,       },
 
     {   KEY_ROI_DATA,           TYPE_PTR,       },
     {   KEY_ROI_DATA2,          TYPE_PTR,       },
@@ -73,6 +75,7 @@ static MppMetaDef meta_defs[] = {
     {   KEY_LVL16_INTRA_NUM,    TYPE_S32,       },
     {   KEY_LVL8_INTRA_NUM,     TYPE_S32,       },
     {   KEY_LVL4_INTRA_NUM,     TYPE_S32,       },
+    {   KEY_INPUT_PSKIP,        TYPE_S32,       },
     {   KEY_OUTPUT_PSKIP,       TYPE_S32,       },
     {   KEY_ENC_SSE,            TYPE_S64,       },
 
diff --git a/mpp/base/mpp_trie.cpp b/mpp/base/mpp_trie.cpp
index 79d2fb578..24aac3cf9 100644
--- a/mpp/base/mpp_trie.cpp
+++ b/mpp/base/mpp_trie.cpp
@@ -30,36 +30,89 @@
 #define MPP_TRIE_DBG_SET                (0x00000002)
 #define MPP_TRIE_DBG_GET                (0x00000004)
 #define MPP_TRIE_DBG_CNT                (0x00000008)
+#define MPP_TRIE_DBG_WALK               (0x00000010)
+#define MPP_TRIE_DBG_LAST               (0x00000020)
+#define MPP_TRIE_DBG_LAST_STEP          (0x00000040)
+#define MPP_TRIE_DBG_LAST_CHECK         (0x00000080)
 
 #define trie_dbg(flag, fmt, ...)        _mpp_dbg_f(mpp_trie_debug, flag, fmt, ## __VA_ARGS__)
 #define trie_dbg_func(fmt, ...)         trie_dbg(MPP_TRIE_DBG_FUNC, fmt, ## __VA_ARGS__)
 #define trie_dbg_set(fmt, ...)          trie_dbg(MPP_TRIE_DBG_SET, fmt, ## __VA_ARGS__)
 #define trie_dbg_get(fmt, ...)          trie_dbg(MPP_TRIE_DBG_GET, fmt, ## __VA_ARGS__)
 #define trie_dbg_cnt(fmt, ...)          trie_dbg(MPP_TRIE_DBG_CNT, fmt, ## __VA_ARGS__)
+#define trie_dbg_walk(fmt, ...)         trie_dbg(MPP_TRIE_DBG_WALK, fmt, ## __VA_ARGS__)
+#define trie_dbg_last(fmt, ...)         trie_dbg(MPP_TRIE_DBG_LAST, fmt, ## __VA_ARGS__)
 
 #define DEFAULT_NODE_COUNT              900
 #define DEFAULT_INFO_COUNT              80
 #define INVALID_NODE_ID                 (-1)
+#define MPP_TRIE_TAG_LEN_MAX            ((sizeof(RK_U64) * 8) / MPP_TRIE_KEY_LEN)
+
+/* spatial optimized trie tree */
+typedef struct MppTrieNode_t {
+    /* next         - next trie node index */
+    RK_S16          next[MPP_TRIE_KEY_MAX];
+    /* id           - payload data offset of current trie node */
+    RK_S32          id;
+    /* idx          - trie node index in ascending order */
+    RK_S16          idx;
+    /* prev         - previous trie node index */
+    RK_S16          prev;
+
+    /* tag_val      - prefix tag */
+    RK_U64          tag_val;
+    /* key          - current key value in previous node as next */
+    RK_U16          key;
+    /*
+     * tag len      - prefix tag length
+     * zero         - normal node with 16 next node
+     * positive     - tag node with 64bit prefix tag
+     */
+    RK_S16          tag_len;
+
+    /* next_cnt     - valid next node count */
+    RK_U16          next_cnt;
+} MppTrieNode;
+
+typedef struct MppTrieInfoInt_t {
+    RK_S32          ctx_offset;
+    RK_S32          name_offset;
+    RK_S32          index;
+    RK_S32          str_len;
+} MppTrieInfoInt;
+
+typedef struct MppTrieImpl_t {
+    RK_S32          ctx_size;
+    RK_S32          buf_size;
+
+    RK_S32          nodes_size;
+    RK_S32          infos_size;
 
-typedef struct MppAcImpl_t {
     RK_S32          info_count;
     RK_S32          info_used;
-    const char      ***info;
+    MppTrieInfoInt  *info;
     RK_S32          node_count;
     RK_S32          node_used;
     MppTrieNode     *nodes;
+
+    /* info and name record buffer */
+    void            *info_buf;
+    void            *name_buf;
+    RK_S32          info_buf_size;
+    RK_S32          name_buf_size;
+    RK_S32          name_buf_pos;
 } MppTrieImpl;
 
 RK_U32 mpp_trie_debug = 0;
 
-static RK_S32 trie_get_node(MppTrieImpl *trie)
+static RK_S32 trie_get_node(MppTrieImpl *trie, RK_S32 prev, RK_U64 key)
 {
     if (trie->node_used >= trie->node_count) {
         RK_S32 old_count = trie->node_count;
         RK_S32 new_count = old_count * 2;
         MppTrieNode *new_nodes = mpp_realloc(trie->nodes, MppTrieNode, new_count);
 
-        if (NULL == new_nodes) {
+        if (!new_nodes) {
             mpp_err_f("failed to realloc new nodes %d\n", new_count);
             return -1;
         }
@@ -78,16 +131,21 @@ static RK_S32 trie_get_node(MppTrieImpl *trie)
     MppTrieNode *n = &trie->nodes[idx];
 
     n->idx = idx;
+    n->prev = (prev > 0) ? prev : 0;
+    n->key = key;
     n->id = INVALID_NODE_ID;
 
+    if (prev >= 0)
+        trie->nodes[prev].next_cnt++;
+
     trie_dbg_cnt("get node %d\n", idx);
 
     return idx;
 }
 
-MPP_RET mpp_trie_init(MppTrie *trie, RK_S32 node_count, RK_S32 info_count)
+MPP_RET mpp_trie_init(MppTrie *trie, RK_S32 info_size)
 {
-    if (NULL == trie) {
+    if (!trie) {
         mpp_err_f("invalid NULL input trie automation\n");
         return MPP_ERR_NULL_PTR;
     }
@@ -96,34 +154,49 @@ MPP_RET mpp_trie_init(MppTrie *trie, RK_S32 node_count, RK_S32 info_count)
 
     MPP_RET ret = MPP_ERR_NOMEM;
     MppTrieImpl *p = mpp_calloc(MppTrieImpl, 1);
-    if (NULL == p) {
+    if (!p) {
         mpp_err_f("create trie impl failed\n");
         goto DONE;
     }
 
-    p->node_count = node_count ? node_count : DEFAULT_NODE_COUNT;
-    if (p->node_count) {
-        p->nodes = mpp_calloc(MppTrieNode, p->node_count);
-        if (NULL == p->nodes) {
-            mpp_err_f("create %d nodes failed\n", p->node_count);
-            goto DONE;
-        }
+    p->node_count = DEFAULT_NODE_COUNT;
+    p->nodes = mpp_calloc(MppTrieNode, p->node_count);
+    if (!p->nodes) {
+        mpp_err_f("create %d nodes failed\n", p->node_count);
+        goto DONE;
+    }
+
+    p->info_count = DEFAULT_INFO_COUNT;
+    p->info = mpp_calloc(MppTrieInfoInt, p->info_count);
+    if (!p->info) {
+        mpp_err_f("failed to alloc %d info\n", p->info_count);
+        goto DONE;
+    }
+
+    p->ctx_size = info_size;
+    p->info_buf_size = p->ctx_size * p->info_count;
+    p->info_buf = mpp_calloc_size(void, p->info_buf_size);
+    if (!p->info_buf) {
+        mpp_err_f("failed to alloc %d info buffer\n", p->info_buf_size);
+        goto DONE;
     }
 
-    p->info_count = info_count ? info_count : DEFAULT_INFO_COUNT;
-    p->info = mpp_calloc(const char **, p->info_count);
-    if (NULL == p->info) {
-        mpp_err_f("failed to alloc %d storage\n", p->info_count);
+    p->name_buf_size = SZ_4K;
+    p->name_buf = mpp_calloc_size(void, p->name_buf_size);
+    if (!p->name_buf) {
+        mpp_err_f("failed to alloc %d name buffer\n", p->info_buf_size);
         goto DONE;
     }
 
     /* get node 0 as root node*/
-    trie_get_node(p);
+    trie_get_node(p, -1, 0);
     ret = MPP_OK;
 
 DONE:
     if (ret && p) {
         MPP_FREE(p->info);
+        MPP_FREE(p->info_buf);
+        MPP_FREE(p->name_buf);
         MPP_FREE(p->nodes);
         MPP_FREE(p);
     }
@@ -134,8 +207,8 @@ MPP_RET mpp_trie_init(MppTrie *trie, RK_S32 node_count, RK_S32 info_count)
 
 MPP_RET mpp_trie_deinit(MppTrie trie)
 {
-    if (NULL == trie) {
-        mpp_err_f("invalid NULL input trie automation\n");
+    if (!trie) {
+        mpp_err_f("invalid NULL input trie\n");
         return MPP_ERR_NULL_PTR;
     }
 
@@ -143,42 +216,359 @@ MPP_RET mpp_trie_deinit(MppTrie trie)
 
     MPP_FREE(p->nodes);
     MPP_FREE(p->info);
+    MPP_FREE(p->info_buf);
+    MPP_FREE(p->name_buf);
     MPP_FREE(p);
 
     return MPP_OK;
 }
 
-MPP_RET mpp_trie_add_info(MppTrie trie, const char **info)
+static RK_S32 mpp_trie_walk(MppTrieNode *node, RK_U64 *tag_val, RK_S32 *tag_len, RK_U32 key)
 {
-    if (NULL == trie || NULL == info) {
-        mpp_err_f("invalid trie %p info %p\n", trie, info);
-        return MPP_ERR_NULL_PTR;
+    RK_U64 val = *tag_val;
+    RK_S32 len = *tag_len;
+
+    if (node->tag_len > len) {
+        *tag_val = (val << 4) | key;
+        *tag_len = len + 1;
+
+        trie_dbg_walk("node %d:%d tag len %d - %d val %016llx - %016llx -> key %x -> tag fill\n",
+                      node->idx, node->id, node->tag_len, *tag_len, node->tag_val, *tag_val, key);
+
+        return node->idx;
+    }
+
+    /* normal next switch node */
+    if (!node->tag_len) {
+        trie_dbg_walk("node %d:%d -> key %x -> next %d\n",
+                      node->idx, node->id, key, node->next[key]);
+
+        return node->next[key];
+    }
+
+    *tag_val = 0;
+    *tag_len = 0;
+
+    if (node->tag_val != val) {
+        trie_dbg_walk("node %d:%d tag len %d - %d val %016llx - %016llx -> tag mismatch\n",
+                      node->idx, node->id, node->tag_len, len, node->tag_val, val);
+        return INVALID_NODE_ID;
+    }
+
+    trie_dbg_walk("node %d:%d tag len %d - %d val %016llx - %016llx -> tag match -> key %d next %d\n",
+                  node->idx, node->id, node->tag_len, len, node->tag_val, val, key, node->next[key]);
+
+    return node->next[key];
+}
+
+static MppTrieNode *mpp_trie_get_node(MppTrieNode *root, const char *name)
+{
+    MppTrieNode *ret = NULL;
+    const char *s = name;
+    RK_U64 tag_val = 0;
+    RK_S32 tag_len = 0;
+    RK_S32 idx = 0;
+
+    if (!root || !name) {
+        mpp_err_f("invalid root %p name %p\n", root, name);
+        return NULL;
+    }
+
+    trie_dbg_get("root %p search %s start\n", root, name);
+
+    do {
+        RK_U8 key = *s++;
+        RK_U32 key0 = (key >> 4) & 0xf;
+        RK_U32 key1 = key & 0xf;
+        RK_S32 end = (s[0] == '\0');
+
+        idx = mpp_trie_walk(&root[idx], &tag_val, &tag_len, key0);
+        if (idx < 0)
+            break;
+
+        idx = mpp_trie_walk(&root[idx], &tag_val, &tag_len, key1);
+        if (idx < 0 || end)
+            break;
+    } while (1);
+
+    ret = (idx >= 0) ? &root[idx] : NULL;
+
+    trie_dbg_get("get node %d:%d\n", idx, ret ? ret->id : INVALID_NODE_ID);
+
+    return ret;
+}
+
+static RK_S32 mpp_trie_check(MppTrie trie, const char *log)
+{
+    MppTrieImpl *p = (MppTrieImpl *)trie;
+    char *buf = (char *)p->name_buf;
+    RK_S32 i;
+
+    for (i = 0; i < p->info_used; i++) {
+        const char *name = buf + p->info[i].name_offset;
+        MppTrieNode *node = mpp_trie_get_node(p->nodes, name);
+
+        if (node && node->id >= 0 && node->id == i)
+            continue;
+
+        mpp_loge("trie check on %s found mismatch info %s %d - %d\n",
+                 log, name, i, node ? node->id : -1);
+        return MPP_NOK;
     }
 
+    return MPP_OK;
+}
+
+MPP_RET mpp_trie_last_info(MppTrie trie)
+{
     MppTrieImpl *p = (MppTrieImpl *)trie;
+    MppTrieNode *root;
+    MppTrieNode *node;
+    char *buf;
+    RK_S32 node_count;
+    RK_S32 node_valid;
+    RK_S32 nodes_size;
+    RK_S32 len = 0;
+    RK_S32 pos = 0;
+    RK_S32 i;
+    RK_S32 j;
+
+    if (!trie) {
+        mpp_err_f("invalid NULL trie\n");
+        return MPP_ERR_NULL_PTR;
+    }
+
+    root = p->nodes;
+    node_count = p->node_used;
+    node_valid = node_count;
+
+    trie_dbg_last("shrink trie node start node %d info %d\n", node_count, p->info_used);
+
+    if (mpp_trie_debug & MPP_TRIE_DBG_LAST_STEP)
+        mpp_trie_dump_f(trie);
+
+    for (i = node_count - 1; i > 0; i--) {
+        MppTrieNode *prev;
+        RK_S32 prev_idx;
+
+        node = &root[i];
+        prev_idx = node->prev;
+        prev = &root[prev_idx];
+
+        if (prev->next_cnt > 1) {
+            trie_dbg_last("node %d:%d prev %d next count %d stop shrinking for multi next\n",
+                          i, node->id, prev_idx, prev->next_cnt);
+            continue;
+        }
+
+        if (node->tag_len >= (RK_S16)MPP_TRIE_TAG_LEN_MAX) {
+            trie_dbg_last("node %d:%d tag %d - %016llx stop shrinking for max tag len\n",
+                          i, node->id, node->tag_len, node->tag_val);
+            continue;
+        }
+
+        if (prev->id >= 0) {
+            trie_dbg_last("node %d:%d tag %d - %016llx stop shrinking for valid info node\n",
+                          i, node->id, node->tag_len, node->tag_val);
+            continue;
+        }
+
+        prev->id = node->id;
+        /* NOTE: do NOT increase tag length on root node */
+        prev->tag_len = node->tag_len + 1;
+        prev->tag_val = ((RK_U64)node->key << (node->tag_len * 4)) | node->tag_val;
+        prev->next_cnt = node->next_cnt;
+        memcpy(prev->next, node->next, sizeof(node->next));
+
+        trie_dbg_last("node %d:%d shrink prev %d key %x tag %016llx -> %016llx\n",
+                      i, node->id, prev->idx, prev->key, node->tag_val, prev->tag_val);
+
+        for (j = 0; j < MPP_TRIE_KEY_MAX; j++) {
+            if (!prev->next[j])
+                continue;
+
+            root[prev->next[j]].prev = prev_idx;
+        }
+
+        memset(node, 0, sizeof(*node));
+        node->id = INVALID_NODE_ID;
+        node_valid--;
+    }
+
+    trie_dbg_last("shrink trie node finish count %d -> %d\n", node_count, node_valid);
+
+    if (mpp_trie_debug & MPP_TRIE_DBG_LAST_STEP)
+        mpp_trie_dump_f(trie);
+
+    if (mpp_trie_debug & MPP_TRIE_DBG_LAST_CHECK)
+        mpp_trie_check(trie, "shrink merge tag stage");
+
+    trie_dbg_last("move trie node start to reduce memory %d -> %d\n", node_count, node_valid);
+
+    for (i = 1; i < node_valid; i++) {
+        node = &root[i];
+
+        /* skip valid node */
+        if (node->idx)
+            continue;
+
+        for (j = i; j < node_count; j++) {
+            MppTrieNode *tmp = &root[j];
+            MppTrieNode *prev;
+            RK_S32 k;
+
+            /* skip empty node */
+            if (!tmp->idx)
+                continue;
+
+            trie_dbg_last("move node %d to %d prev %d\n", j, i, tmp->prev);
+
+            prev = &root[tmp->prev];
+
+            /* relink previous node */
+            for (k = 0; k < MPP_TRIE_KEY_MAX; k++) {
+                if (prev->next[k] != tmp->idx)
+                    continue;
+
+                prev->next[k] = i;
+                break;
+            }
+
+            memcpy(node, tmp, sizeof(*node));
+            node->idx = i;
+            memset(tmp, 0, sizeof(*tmp));
+
+            /* relink next node */
+            for (k = 0; k < MPP_TRIE_KEY_MAX; k++) {
+                if (!node->next[k])
+                    continue;
+
+                root[node->next[k]].prev = i;
+            }
+
+            break;
+        }
+    }
+
+    p->node_used = node_valid;
+
+    trie_dbg_last("move trie node finish used %d\n", p->node_used);
+
+    if (mpp_trie_debug & MPP_TRIE_DBG_LAST_STEP)
+        mpp_trie_dump_f(trie);
+
+    if (mpp_trie_debug & MPP_TRIE_DBG_LAST_CHECK)
+        mpp_trie_check(trie, "shrink move node stage");
+
+    trie_dbg_last("create user buffer start\n");
+
+    nodes_size = sizeof(MppTrieNode) * p->node_used;
+    p->nodes_size = nodes_size;
+    p->infos_size = (sizeof(MppTrieInfo) + p->ctx_size) * p->info_used;
+
+    pos += nodes_size;
+    /* update info size and string name size */
+    for (i = 0; i < p->info_used; i++) {
+        len = p->info[i].str_len;
+        pos += sizeof(MppTrieInfo) + p->ctx_size + len;
+    }
+
+    len = pos;
+    buf = mpp_calloc_size(char, len);
+    if (!buf) {
+        mpp_loge("failed to alloc trie buffer size %d\n", len);
+        return MPP_NOK;
+    }
+
+    p->nodes = (MppTrieNode *)buf;
+    p->buf_size = len;
+    memcpy(p->nodes, root, nodes_size);
+    pos = nodes_size;
+
+    for (i = 0; i < p->info_used; i++) {
+        MppTrieInfo *info;
+        const char *name = (char *)p->name_buf + p->info[i].name_offset;
+
+        node = mpp_trie_get_node(p->nodes, name);
+        node->id = pos;
+
+        /* reserve node info */
+        info = (MppTrieInfo *)(buf + pos);
+        info->index = p->info[i].index;
+        info->str_len = p->info[i].str_len;
+        pos += sizeof(MppTrieInfo);
+
+        /* reserve user context space */
+        info->ctx = (void *)(buf + pos);
+        memcpy(buf + pos, (char *)p->info_buf + p->info[i].ctx_offset, p->ctx_size);
+        pos += p->ctx_size;
+
+        /* copy info name */
+        info->name = (char *)(buf + pos);
+        strncpy(buf + pos, name, info->str_len);
+        pos += info->str_len;
+    }
+
+    MPP_FREE(root);
+    MPP_FREE(p->info);
+    MPP_FREE(p->info_buf);
+    MPP_FREE(p->name_buf);
+
+    return MPP_OK;
+}
+
+MPP_RET mpp_trie_add_info(MppTrie trie, const char *name, void *ctx)
+{
+    MppTrieImpl *p;
+    MppTrieInfoInt *info;
+    MppTrieNode *node;
+    const char *s;
+    RK_S32 act_id;
+    RK_S32 next;
+    RK_S32 len;
+    RK_S32 idx;
+    RK_S32 i;
+
+    if (!trie) {
+        mpp_err_f("invalid trie %p name %s ctx %p\n", trie, name, ctx);
+        return MPP_ERR_NULL_PTR;
+    }
+
+    if (!name)
+        return mpp_trie_last_info(trie);
+
+    p = (MppTrieImpl *)trie;
 
     /* create */
     if (p->info_used >= p->info_count) {
         RK_S32 new_count = p->info_count * 2;
-        const char ***ptr = mpp_realloc(p->info, const char **, new_count);
-        if (NULL == ptr) {
-            mpp_err_f("failed to realloc new action %d\n", new_count);
+        void *ptr = mpp_realloc_size(p->info, void, sizeof(MppTrieInfoInt) * new_count);
+
+        if (!ptr) {
+            mpp_err_f("failed to realloc new info %d\n", new_count);
             return MPP_ERR_MALLOC;
         }
-
+        p->info = (MppTrieInfoInt *)ptr;
         trie_dbg_cnt("trie %p enlarge info %p:%d -> %p:%d\n",
                      trie, p->info, p->info_count, ptr, new_count);
 
-        p->info = ptr;
+        ptr = mpp_realloc_size(p->info_buf, void, p->ctx_size * new_count);
+        if (!ptr) {
+            mpp_err_f("failed to realloc new info buffer %d\n", new_count);
+            return MPP_ERR_MALLOC;
+        }
+        p->info_buf = ptr;
+        trie_dbg_cnt("trie %p enlarge info_buf %p:%d -> %p:%d\n",
+                     trie, p->info_buf, p->info_count, ptr, new_count);
+
         p->info_count = new_count;
     }
 
-    MppTrieNode *node = NULL;
-    const char *s = *info;
-    RK_S32 len = strnlen(s, SZ_1K);
-    RK_S32 next = 0;
-    RK_S32 idx = 0;
-    RK_S32 i;
+    node = NULL;
+    s = name;
+    len = strnlen(s, SZ_1K);
+    next = 0;
+    idx = 0;
 
     trie_dbg_set("trie %p add info %s len %d\n", trie, s, len);
 
@@ -194,7 +584,7 @@ MPP_RET mpp_trie_add_info(MppTrie trie, const char **info)
                      trie, s, i, key, key, key0, key1, idx, next);
 
         if (!next) {
-            next = trie_get_node(p);
+            next = trie_get_node(p, idx, key0);
             /* realloc may cause memory address change */
             node = p->nodes + idx;
             node->next[key0] = next;
@@ -211,7 +601,7 @@ MPP_RET mpp_trie_add_info(MppTrie trie, const char **info)
                      trie, s, i, key, key, key0, key1, idx, next);
 
         if (!next) {
-            next = trie_get_node(p);
+            next = trie_get_node(p, idx, key1);
             /* realloc may cause memory address change */
             node = p->nodes + idx;
             node->next[key1] = next;
@@ -226,99 +616,150 @@ MPP_RET mpp_trie_add_info(MppTrie trie, const char **info)
                      trie, s, i, key, key, key0, key1, idx, next);
     }
 
-    RK_S32 act_id = p->info_used++;
+    act_id = p->info_used++;
     p->nodes[idx].id = act_id;
-    p->info[act_id] = info;
+
+    info = &p->info[act_id];
+    info->index = act_id;
+    info->str_len = MPP_ALIGN(len + 1, sizeof(RK_U64));
+    info->ctx_offset = act_id * p->ctx_size;
+    info->name_offset = p->name_buf_pos;
+
+    memcpy((RK_U8 *)p->info_buf + info->ctx_offset, ctx, p->ctx_size);
+
+    if (p->name_buf_pos + len + 1 >= p->name_buf_size) {
+        RK_S32 new_size = p->name_buf_size * 2;
+        void *ptr = mpp_realloc(p->name_buf, RK_U8, new_size);
+
+        if (!ptr) {
+            mpp_err_f("failed to realloc new name buffer %d\n", new_size);
+            return MPP_ERR_MALLOC;
+        }
+
+        trie_dbg_cnt("trie %p enlarge name %p:%d -> %p:%d\n",
+                     trie, p->name_buf, p->name_buf_size, ptr, new_size);
+
+        p->name_buf = ptr;
+        p->name_buf_size = new_size;
+    }
+
+    snprintf((char *)p->name_buf + p->name_buf_pos, p->name_buf_size - p->name_buf_pos - 1, "%s", name);
+    p->name_buf_pos += info->str_len;
 
     trie_dbg_set("trie %p add %d info %s at node %d pos %d action %p done\n",
-                 trie, i, s, idx, act_id, info);
+                 trie, i, s, idx, act_id, ctx);
 
     return MPP_OK;
 }
 
 RK_S32 mpp_trie_get_node_count(MppTrie trie)
 {
-    if (NULL == trie) {
-        mpp_err_f("invalid NULL trie\n");
-        return 0;
-    }
-
     MppTrieImpl *p = (MppTrieImpl *)trie;
-    return p->node_used;
+
+    return (p) ? p->node_used : 0;
 }
 
 RK_S32 mpp_trie_get_info_count(MppTrie trie)
 {
-    if (NULL == trie) {
-        mpp_err_f("invalid NULL trie\n");
-        return 0;
-    }
+    MppTrieImpl *p = (MppTrieImpl *)trie;
+
+    return (p) ? p->info_used : 0;
+}
 
+RK_S32 mpp_trie_get_buf_size(MppTrie trie)
+{
     MppTrieImpl *p = (MppTrieImpl *)trie;
-    return p->info_used;
+
+    return (p) ? p->buf_size : 0;
 }
 
-MppTrieNode *mpp_trie_get_node(MppTrieNode *root, const char *name)
+MppTrieInfo *mpp_trie_get_info(MppTrie trie, const char *name)
 {
-    MppTrieNode *node = root;
-    const char *s = name;
-    RK_S32 len = 0;
-    RK_S16 idx = 0;
-    RK_S32 i;
+    MppTrieImpl *p = (MppTrieImpl *)trie;
+    MppTrieNode *node;
 
-    if (NULL == root || NULL == name) {
-        mpp_err_f("invalid root %p name %p\n", root, name);
+    if (!trie || !name) {
+        mpp_err_f("invalid trie %p name %p\n", trie, name);
         return NULL;
     }
 
-    len = strlen(name);
-
-    trie_dbg_get("root %p search %s len %2d start\n", root, name, len);
-
-    for (i = 0; i < len; i++, s++) {
-        idx = node->next[(s[0] >> 4) & 0xf];
-        if (!idx)
-            break;
-
-        node = &root[idx];
-
-        idx = node->next[(s[0] >> 0) & 0xf];
-        if (!idx)
-            break;
-
-        node = &root[idx];
-    }
+    node = mpp_trie_get_node(p->nodes, name);
+    if (!node || node->id < 0)
+        return NULL;
 
-    trie_dbg_get("idx %d node %p id %d\n", idx, node, node->id);
+    return (MppTrieInfo *)(((RK_U8 *)p->nodes) + node->id);
+}
 
-    if (!idx || node->id == INVALID_NODE_ID)
-        node = NULL;
+MppTrieInfo *mpp_trie_get_info_first(MppTrie trie)
+{
+    MppTrieImpl *p = (MppTrieImpl *)trie;
 
-    return node;
+    return (p) ? (MppTrieInfo *)(((RK_U8 *)p->nodes) + p->node_used * sizeof(MppTrieNode)) : NULL;
 }
 
-MppTrieNode *mpp_trie_node_root(MppTrie trie)
+MppTrieInfo *mpp_trie_get_info_next(MppTrie trie, MppTrieInfo *info)
 {
-    if (NULL == trie) {
-        mpp_err_f("invalid NULL trie\n");
+    MppTrieImpl *p = (MppTrieImpl *)trie;
+
+    if (!p || !info || info->index >= p->info_used - 1)
         return NULL;
-    }
 
-    MppTrieImpl *p = (MppTrieImpl *)trie;
-    return p->nodes;
+    return (MppTrieInfo *)(info->name + info->str_len);
 }
 
-const char **mpp_trie_get_info(MppTrie trie, const char *name)
+void mpp_trie_dump(MppTrie trie, const char *func)
 {
     MppTrieImpl *p = (MppTrieImpl *)trie;
-    MppTrieNode *node;
+    RK_S32 i;
+    RK_S32 next_cnt[17];
+    RK_S32 tag_len[17];
+
+    memset(next_cnt, 0, sizeof(next_cnt));
+    memset(tag_len, 0, sizeof(tag_len));
+
+    mpp_logi("%s dumping node count %d used %d\n", func, p->node_count, p->node_used);
+
+    for (i = 0; i < p->node_used; i++) {
+        MppTrieNode *node = &p->nodes[i];
+        RK_S32 valid_count = 0;
+        RK_S32 j;
+
+        if (i && !node->idx)
+            continue;
+
+        if (node->id >= 0) {
+            /* check before and after last info */
+            if (node->id < (RK_S32)(p->node_used * sizeof(MppTrieNode)))
+                mpp_logi("node %d key %x info %d - %s\n", node->idx, node->key, node->id,
+                         (char *)p->name_buf + p->info[node->id].name_offset);
+            else
+                mpp_logi("node %d key %x info %d - %s\n", node->idx, node->key, node->id,
+                         ((MppTrieInfo *)((char *)p->nodes + node->id))->name);
+        } else
+            mpp_logi("node %d key %x\n", node->idx, node->key);
+
+        if (node->tag_len)
+            mpp_logi("    prev %d count %d tag %d - %llx\n", node->prev, node->next_cnt, node->tag_len, node->tag_val);
+        else
+            mpp_logi("    prev %d count %d\n", node->prev, node->next_cnt);
+
+        for (j = 0; j < MPP_TRIE_KEY_MAX; j++) {
+            if (node->next[j] > 0) {
+                mpp_logi("    next %d:%d -> %d\n", valid_count, j, node->next[j]);
+                valid_count++;
+            }
+        }
 
-    if (NULL == trie || NULL == name) {
-        mpp_err_f("invalid trie %p name %p\n", trie, name);
-        return NULL;
+        next_cnt[valid_count]++;
+        tag_len[node->tag_len]++;
     }
 
-    node = mpp_trie_get_node(p->nodes, name);
+    mpp_logi("node | next |  tag | used %d\n", p->node_used);
 
-    return (node && node->id >= 0) ? p->info[node->id] : NULL;
-}
+    for (i = 0; i < 17; i++) {
+        if (next_cnt[i] || tag_len[i])
+            mpp_logi("%2d   | %4d | %4d |\n", i, next_cnt[i], tag_len[i]);
+    }
+
+    mpp_logi("%s dumping node end\n", func, p->node_used);
+}
\ No newline at end of file
diff --git a/mpp/base/test/mpp_trie_test.c b/mpp/base/test/mpp_trie_test.c
index 8721a5031..ee2de293b 100644
--- a/mpp/base/test/mpp_trie_test.c
+++ b/mpp/base/test/mpp_trie_test.c
@@ -25,7 +25,7 @@
 
 #include "mpp_trie.h"
 
-typedef void *(*TestProc)(void *);
+typedef void *(*TestProc)(void *, RK_S64 time);
 
 typedef struct TestAction_t {
     const char          *name;
@@ -33,12 +33,17 @@ typedef struct TestAction_t {
     TestProc            proc;
 } TestAction;
 
-void *print_opt(void *ctx)
+typedef struct TestCase_t {
+    const char          *name;
+    MPP_RET             ret;
+} TestCase;
+
+void *print_opt(void *ctx, RK_S64 time)
 {
     RK_U8 **str = (RK_U8 **)ctx;
 
     if (str && *str)
-        mpp_log("get option %s\n", *str);
+        mpp_log("get option %-16s time %lld us\n", *str, time);
 
     return NULL;
 }
@@ -48,49 +53,69 @@ TestAction test_info[] = {
     { "rc:bps_target",  &test_info[1],  print_opt},
     { "rc:bps_max",     &test_info[2],  print_opt},
     { "rc:bps_min",     &test_info[3],  print_opt},
+    /* test valid info end in the middle */
+    { "rc:bps",         &test_info[4],  print_opt},
 };
 
-const char *test_str[] = {
-    "rc:mode",
-    "rc:bps_target",
-    "rc:bps_max",
+TestCase test_case[] = {
+    { "rc:mode",                    MPP_OK, },
+    { "rc:bps_target",              MPP_OK, },
+    { "rc:bps_max",                 MPP_OK, },
+    { "rc:bps",                     MPP_OK, },
+    { "this is an error string",    MPP_NOK, },
+    { "",                           MPP_NOK, },
 };
 
 int main()
 {
     MppTrie trie = NULL;
-    void *info = NULL;
-    RK_U32 i;
+    RK_S32 i;
     RK_S64 end = 0;
     RK_S64 start = 0;
     RK_S32 info_cnt = MPP_ARRAY_ELEMS(test_info);
-    RK_S32 node_cnt = 100;
+    RK_S32 ret = MPP_OK;
+
+    mpp_log("mpp_trie_test start\n");
 
-    mpp_trie_init(&trie, node_cnt, info_cnt);
+    mpp_trie_init(&trie, sizeof(TestAction));
 
     start = mpp_time();
-    mpp_trie_add_info(trie, &test_info[0].name);
-    mpp_trie_add_info(trie, &test_info[1].name);
-    mpp_trie_add_info(trie, &test_info[2].name);
-    mpp_trie_add_info(trie, &test_info[3].name);
+    for (i = 0; i < info_cnt; i++)
+        mpp_trie_add_info(trie, test_info[i].name, &test_info[i]);
     end = mpp_time();
     mpp_log("add act time %lld us\n", end - start);
 
-    for (i = 0; i < MPP_ARRAY_ELEMS(test_str); i++) {
+    ret = mpp_trie_add_info(trie, NULL, NULL);
+    if (ret) {
+        mpp_loge("mpp_trie_add_info last failed\n");
+        goto DONE;
+    }
+
+    for (i = 0; i < (RK_S32)MPP_ARRAY_ELEMS(test_case); i++) {
+        MppTrieInfo *info = NULL;
+        TestAction *act = NULL;
+        const char *name = test_case[i].name;
+
         start = mpp_time();
-        info = mpp_trie_get_info(trie, test_str[i]);
+        info = mpp_trie_get_info(trie, name);
         end = mpp_time();
-        if (info) {
-            TestAction *act = (TestAction *)info;
-
-            if (act && act->proc) {
-                act->proc(act->ctx);
-                mpp_log("search time %lld us\n", end - start);
-            }
-        }
+
+        if (info && info->ctx)
+            act = (TestAction *)info->ctx;
+
+        if (act && act->proc)
+            act->proc(act->ctx, end - start);
+        else
+            mpp_loge("search %s failed time %lld us\n", name, end - start);
+
+        ret |= ((info && !test_case[i].ret) ||
+                (!info && test_case[i].ret)) ? MPP_OK : MPP_NOK;
     }
 
     mpp_trie_deinit(trie);
 
-    return 0;
+DONE:
+    mpp_log("mpp_trie_test ret %s\n", ret ? "failed" : "success");
+
+    return ret;
 }
diff --git a/mpp/codec/dec/av1/av1d_cbs.c b/mpp/codec/dec/av1/av1d_cbs.c
index d0446797d..51f486f9c 100644
--- a/mpp/codec/dec/av1/av1d_cbs.c
+++ b/mpp/codec/dec/av1/av1d_cbs.c
@@ -201,8 +201,8 @@ RK_S32 mpp_av1_read_unsigned(BitReadCtx_t *gbc,
 static RK_S32 sign_extend(RK_S32 val, RK_U8 bits)
 {
     RK_U8 shift = 8 * sizeof(RK_S32) - bits;
-    union { RK_U8 u; RK_S32 s; } v = { (RK_U8) val << shift };
-    return v.s >> shift;
+    RK_S32 v = { (RK_U8) val << shift };
+    return v >> shift;
 }
 
 RK_S32 mpp_av1_read_signed(BitReadCtx_t *gbc,
@@ -1226,6 +1226,18 @@ static RK_S32 mpp_av1_segmentation_params(AV1Context *ctx, BitReadCtx_t *gb,
         }
     }
 
+    infer(segmentation_id_last_active, 0);
+    infer(segmentation_id_preskip, 0);
+    for (i = 0; i < AV1_MAX_SEGMENTS; i++) {
+        for (j = 0; j < AV1_SEG_LVL_MAX; j++) {
+            if (current->feature_enabled[i][j]) {
+                infer(segmentation_id_last_active, i);
+                if ( j > AV1_SEG_LVL_REF_FRAME)
+                    infer(segmentation_id_preskip, 1);
+            }
+        }
+    }
+
     return 0;
 __BITREAD_ERR:
     return MPP_ERR_STREAM;
@@ -1441,7 +1453,7 @@ static RK_S32 mpp_av1_read_tx_mode(AV1Context *ctx, BitReadCtx_t *gb,
         infer(tx_mode, 0);
     else {
         flag(tx_mode);
-        current->tx_mode = current->tx_mode ? 4 : 3;
+        current->tx_mode = current->tx_mode ? TX_MODE_SELECT : TX_MODE_LARGEST;
     }
 
     return 0;
@@ -1468,6 +1480,9 @@ static RK_S32 mpp_av1_skip_mode_params(AV1Context *ctx, BitReadCtx_t *gb,
     RK_S32 skip_mode_allowed;
     RK_S32 err;
 
+    ctx->skip_ref0 = 0;
+    ctx->skip_ref1 = 0;
+
     if (current->frame_type == AV1_FRAME_KEY ||
         current->frame_type == AV1_FRAME_INTRA_ONLY ||
         !current->reference_select || !seq->enable_order_hint) {
@@ -1800,8 +1815,7 @@ static RK_S32 mpp_av1_uncompressed_header(AV1Context *ctx, BitReadCtx_t *gb,
             infer(render_width_minus_1,  ref->render_width - 1);
             infer(render_height_minus_1, ref->render_height - 1);
 
-            // Section 7.20
-            goto update_refs;
+            return 0;
         }
 
         fb(2, frame_type);
@@ -1940,6 +1954,7 @@ static RK_S32 mpp_av1_uncompressed_header(AV1Context *ctx, BitReadCtx_t *gb,
         }
     }
 
+    current->ref_frame_valued = 1;
     if (current->frame_type == AV1_FRAME_KEY ||
         current->frame_type == AV1_FRAME_INTRA_ONLY) {
         CHECK(mpp_av1_frame_size(ctx, gb, current));
@@ -1951,6 +1966,7 @@ static RK_S32 mpp_av1_uncompressed_header(AV1Context *ctx, BitReadCtx_t *gb,
         else
             infer(allow_intrabc, 0);
 
+        current->ref_frame_valued = 0;
     } else {
         if (!seq->enable_order_hint) {
             infer(frame_refs_short_signaling, 0);
@@ -2112,34 +2128,6 @@ static RK_S32 mpp_av1_uncompressed_header(AV1Context *ctx, BitReadCtx_t *gb,
              seq->color_config.subsampling_y + 1, ctx->bit_depth,
              ctx->tile_rows, ctx->tile_cols);
 
-update_refs:
-    for (i = 0; i < AV1_NUM_REF_FRAMES; i++) {
-        if (current->refresh_frame_flags & (1 << i)) {
-            ctx->ref_s[i] = (AV1ReferenceFrameState) {
-                .valid          = 1,
-                 .frame_id       = current->current_frame_id,
-                  .upscaled_width = ctx->upscaled_width,
-                   .frame_width    = ctx->frame_width,
-                    .frame_height   = ctx->frame_height,
-                     .render_width   = ctx->render_width,
-                      .render_height  = ctx->render_height,
-                       .frame_type     = current->frame_type,
-                        .subsampling_x  = seq->color_config.subsampling_x,
-                         .subsampling_y  = seq->color_config.subsampling_y,
-                          .bit_depth      = ctx->bit_depth,
-                           .order_hint     = ctx->order_hint,
-            };
-            memcpy(ctx->ref_s[i].loop_filter_ref_deltas, current->loop_filter_ref_deltas,
-                   sizeof(current->loop_filter_ref_deltas));
-            memcpy(ctx->ref_s[i].loop_filter_mode_deltas, current->loop_filter_mode_deltas,
-                   sizeof(current->loop_filter_mode_deltas));
-            memcpy(ctx->ref_s[i].feature_enabled, current->feature_enabled,
-                   sizeof(current->feature_enabled));
-            memcpy(ctx->ref_s[i].feature_value, current->feature_value,
-                   sizeof(current->feature_value));
-        }
-    }
-
     return 0;
 }
 
diff --git a/mpp/codec/dec/av1/av1d_cbs.h b/mpp/codec/dec/av1/av1d_cbs.h
index a1f9304ed..42ace2ff4 100644
--- a/mpp/codec/dec/av1/av1d_cbs.h
+++ b/mpp/codec/dec/av1/av1d_cbs.h
@@ -194,6 +194,7 @@ typedef struct AV1RawFrameHeader {
     RK_U8 frame_refs_short_signaling;
     RK_U8 last_frame_idx;
     RK_U8 golden_frame_idx;
+    RK_U8 ref_frame_valued;
     RK_S8  ref_frame_idx[AV1_REFS_PER_FRAME];
     RK_U32 delta_frame_id_minus1[AV1_REFS_PER_FRAME];
 
@@ -236,6 +237,8 @@ typedef struct AV1RawFrameHeader {
     RK_U8 segmentation_update_data;
     RK_U8 feature_enabled[AV1_MAX_SEGMENTS][AV1_SEG_LVL_MAX];
     RK_S16 feature_value[AV1_MAX_SEGMENTS][AV1_SEG_LVL_MAX];
+    RK_U8 segmentation_id_last_active;
+    RK_U8 segmentation_id_preskip;
 
     RK_U8 delta_q_present;
     RK_U8 delta_q_res;
diff --git a/mpp/codec/dec/av1/av1d_common.h b/mpp/codec/dec/av1/av1d_common.h
index e4cdaea75..e41bbae5c 100644
--- a/mpp/codec/dec/av1/av1d_common.h
+++ b/mpp/codec/dec/av1/av1d_common.h
@@ -409,12 +409,9 @@ enum CompPredModeType {
 
 enum TxfmMode {
     ONLY_4X4 = 0,
-    ALLOW_8X8 = 1,
-    ALLOW_16X16 = 2,
-    ALLOW_32X32 = 3,
-    TX_MODE_LARGEST = ALLOW_32X32,  // AV1
-    TX_MODE_SELECT = 4,
-    NB_TXFM_MODES = 5,
+    TX_MODE_LARGEST,
+    TX_MODE_SELECT,
+    NB_TXFM_MODES,
 };
 
 enum SegLevelFeatures {
diff --git a/mpp/codec/dec/av1/av1d_parser.c b/mpp/codec/dec/av1/av1d_parser.c
index f64e8c220..868629b9e 100644
--- a/mpp/codec/dec/av1/av1d_parser.c
+++ b/mpp/codec/dec/av1/av1d_parser.c
@@ -121,7 +121,8 @@ static MPP_RET get_pixel_format(Av1CodecContext *ctx)
             else if (bit_depth == 10) {
                 pix_fmt = MPP_FMT_YUV420SP_10BIT;
                 /* rk3588, allow user config 8bit for 10bit source. */
-                if ((ctx->usr_set_fmt & MPP_FRAME_FMT_MASK) == MPP_FMT_YUV420SP &&
+                if ((mpp_get_soc_type() == ROCKCHIP_SOC_RK3588) &&
+                    (ctx->usr_set_fmt & MPP_FRAME_FMT_MASK) == MPP_FMT_YUV420SP &&
                     (s->cfg->base.out_fmt & MPP_FRAME_FMT_MASK) == MPP_FMT_YUV420SP)
                     pix_fmt = MPP_FMT_YUV420SP;
             } else {
@@ -206,9 +207,11 @@ static void read_global_param(AV1Context *s, RK_S32 type, RK_S32 ref, RK_S32 idx
     mx = 1 << abs_bits;
     r = (prev_gm_param >> prec_diff) - sub;
 
+    s->cur_frame.gm_params[ref].wmmat_val[idx] =
+        decode_signed_subexp_with_ref(s->raw_frame_header->gm_params[ref][idx],
+                                      -mx, mx + 1, r);
     s->cur_frame.gm_params[ref].wmmat[idx] =
-        (decode_signed_subexp_with_ref(s->raw_frame_header->gm_params[ref][idx],
-                                       -mx, mx + 1, r) << prec_diff) + round;
+        (s->cur_frame.gm_params[ref].wmmat_val[idx] << prec_diff) + round;
 }
 
 static RK_U16 round_two(RK_U64 x, RK_U16 n)
@@ -614,7 +617,7 @@ static MPP_RET set_output_frame(Av1CodecContext *ctx)
         mpp_frame_set_hdr_dynamic_meta(frame, s->hdr_dynamic_meta);
         s->hdr_dynamic = 0;
         if (s->raw_frame_header->show_existing_frame)
-            fill_hdr_meta_to_frame(frame, HDR_AV1);
+            fill_hdr_meta_to_frame(frame, MPP_VIDEO_CodingAV1);
     }
     mpp_frame_set_pts(frame, s->pts);
     mpp_buf_slot_set_flag(s->slots, s->cur_frame.slot_index, SLOT_QUEUE_USE);
@@ -673,6 +676,33 @@ static MPP_RET update_reference_list(Av1CodecContext *ctx)
     RK_S32 bwd_buf_idx;
     RK_S32 alt2_buf_idx;
 
+    for (i = 0; i < AV1_NUM_REF_FRAMES; i++) {
+        if (header->refresh_frame_flags & (1 << i)) {
+            s->ref_s[i] = (AV1ReferenceFrameState) {
+                .valid = 1,
+                 .frame_id = header->current_frame_id,
+                  .upscaled_width = s->upscaled_width,
+                   .frame_width = s->frame_width,
+                    .frame_height = s->frame_height,
+                     .render_width = s->render_width,
+                      .render_height = s->render_height,
+                       .frame_type = header->frame_type,
+                        .subsampling_x = s->sequence_header->color_config.subsampling_x,
+                         .subsampling_y = s->sequence_header->color_config.subsampling_y,
+                          .bit_depth = s->bit_depth,
+                           .order_hint = s->order_hint,
+            };
+            memcpy(s->ref_s[i].loop_filter_ref_deltas, header->loop_filter_ref_deltas,
+                   sizeof(header->loop_filter_ref_deltas));
+            memcpy(s->ref_s[i].loop_filter_mode_deltas, header->loop_filter_mode_deltas,
+                   sizeof(header->loop_filter_mode_deltas));
+            memcpy(s->ref_s[i].feature_enabled, header->feature_enabled,
+                   sizeof(header->feature_enabled));
+            memcpy(s->ref_s[i].feature_value, header->feature_value,
+                   sizeof(header->feature_value));
+        }
+    }
+
     if (!header->show_existing_frame) {
         lst2_buf_idx = s->raw_frame_header->ref_frame_idx[AV1_REF_FRAME_LAST2 - AV1_REF_FRAME_LAST];
         lst3_buf_idx = s->raw_frame_header->ref_frame_idx[AV1_REF_FRAME_LAST3 - AV1_REF_FRAME_LAST];
@@ -743,9 +773,6 @@ static MPP_RET get_current_frame(Av1CodecContext *ctx)
     mpp_frame_set_discard(frame->f, 0);
     mpp_frame_set_pts(frame->f, s->pts);
 
-    if (s->is_hdr)
-        ctx->pix_fmt |= MPP_FRAME_HDR;
-
     mpp_frame_set_color_trc(frame->f, ctx->color_trc);
     mpp_frame_set_color_primaries(frame->f, ctx->color_primaries);
     mpp_frame_set_colorspace(frame->f, ctx->colorspace);
@@ -757,18 +784,31 @@ static MPP_RET get_current_frame(Av1CodecContext *ctx)
     if (MPP_FRAME_FMT_IS_FBC(s->cfg->base.out_fmt)) {
         mpp_slots_set_prop(s->slots, SLOTS_HOR_ALIGN, hor_align_16);
         if (s->bit_depth == 10) {
-            if (ctx->pix_fmt == MPP_FMT_YUV420SP || ctx->pix_fmt == MPP_FMT_YUV420SP_10BIT)
+            if ((ctx->pix_fmt & MPP_FRAME_FMT_MASK) == MPP_FMT_YUV420SP ||
+                (ctx->pix_fmt & MPP_FRAME_FMT_MASK) == MPP_FMT_YUV420SP_10BIT)
                 ctx->pix_fmt = MPP_FMT_YUV420SP_10BIT;
             else
                 mpp_err("422p 10bit no support");
         }
 
-        mpp_frame_set_fmt(frame->f, ctx->pix_fmt | ((s->cfg->base.out_fmt & (MPP_FRAME_FBC_MASK))));
+        ctx->pix_fmt |= s->cfg->base.out_fmt & (MPP_FRAME_FBC_MASK);
         mpp_frame_set_offset_x(frame->f, 0);
         mpp_frame_set_offset_y(frame->f, 0);
-        mpp_frame_set_ver_stride(frame->f, MPP_ALIGN(ctx->height, 8) + 28);
-    } else
-        mpp_frame_set_fmt(frame->f, ctx->pix_fmt);
+        if (mpp_get_soc_type() == ROCKCHIP_SOC_RK3588)
+            mpp_frame_set_ver_stride(frame->f, MPP_ALIGN(ctx->height, 8) + 28);
+    } else if (MPP_FRAME_FMT_IS_TILE(s->cfg->base.out_fmt)) {
+        ctx->pix_fmt |= s->cfg->base.out_fmt & (MPP_FRAME_TILE_FLAG);
+    }
+
+    if (s->is_hdr)
+        ctx->pix_fmt |= MPP_FRAME_HDR;
+
+    mpp_frame_set_fmt(frame->f, ctx->pix_fmt);
+
+    if (s->cfg->base.enable_thumbnail && s->hw_info && s->hw_info->cap_down_scale)
+        mpp_frame_set_thumbnail_en(frame->f, s->cfg->base.enable_thumbnail);
+    else
+        mpp_frame_set_thumbnail_en(frame->f, 0);
 
     value = 4;
     mpp_slots_set_prop(s->slots, SLOTS_NUMERATOR, &value);
@@ -826,6 +866,7 @@ MPP_RET av1d_parser_init(Av1CodecContext *ctx, ParserCfg *init)
     s->packet_slots = init->packet_slots;
     s->slots = init->frame_slots;
     s->cfg = init->cfg;
+    s->hw_info = init->hw_info;
     mpp_buf_slot_setup(s->slots, 25);
 
     mpp_env_get_u32("av1d_debug", &av1d_debug, 0);
@@ -938,13 +979,11 @@ MPP_RET av1d_parser_frame(Av1CodecContext *ctx, HalDecTask *task)
 
             s->operating_point_idc = s->sequence_header->operating_point_idc[s->operating_point];
 
-            if (ctx->pix_fmt == MPP_FMT_BUTT) {
-                ret = get_pixel_format(ctx);
-                if (ret < 0) {
-                    mpp_err_f("Failed to get pixel format.\n");
-                    s->sequence_header = NULL;
-                    goto end;
-                }
+            ret = get_pixel_format(ctx);
+            if (ret < 0) {
+                mpp_err_f("Failed to get pixel format.\n");
+                s->sequence_header = NULL;
+                goto end;
             }
             break;
         case AV1_OBU_REDUNDANT_FRAME_HEADER:
@@ -1253,7 +1292,7 @@ RK_S32 av1d_split_frame(Av1CodecContext *ctx,
         if (len < 0)
             break;
         if (obu.type == AV1_OBU_FRAME_HEADER || obu.type == AV1_OBU_FRAME ||
-            ((obu.type == AV1_OBU_TEMPORAL_DELIMITER ||
+            ((obu.type == AV1_OBU_TEMPORAL_DELIMITER || obu.type == AV1_OBU_METADATA ||
               obu.type == AV1_OBU_SEQUENCE_HEADER) && ctx->frame_header))
             ctx->frame_header ++;
         if (ctx->frame_header == 2) {
diff --git a/mpp/codec/dec/av1/av1d_parser.h b/mpp/codec/dec/av1/av1d_parser.h
index 806506bd9..f42b21abc 100644
--- a/mpp/codec/dec/av1/av1d_parser.h
+++ b/mpp/codec/dec/av1/av1d_parser.h
@@ -61,6 +61,7 @@ typedef struct RefInfo {
 typedef struct GlobalMtionParams {
     RK_U32 wmtype;
     RK_S32 wmmat[6];
+    RK_S32 wmmat_val[6];
     RK_S32 alpha, beta, gamma, delta;
 } GlobalMtionParams;
 
@@ -149,6 +150,7 @@ typedef struct AV1Context_t {
     HalDecTask *task;
     RK_S32 eos;       ///< current packet contains an EOS/EOB NAL
     RK_S64 pts;
+    const MppDecHwCap *hw_info;
 } AV1Context;
 
 #ifdef  __cplusplus
diff --git a/mpp/codec/dec/av1/av1d_parser2_syntax.c b/mpp/codec/dec/av1/av1d_parser2_syntax.c
index b1ee5053d..1730e5636 100644
--- a/mpp/codec/dec/av1/av1d_parser2_syntax.c
+++ b/mpp/codec/dec/av1/av1d_parser2_syntax.c
@@ -1,17 +1,6 @@
+/* SPDX-License-Identifier: Apache-2.0 OR MIT */
 /*
- * Copyright 2021 Rockchip Electronics Co. LTD
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *      http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
  */
 
 #define MODULE_TAG "av1d_parser2syntax"
@@ -23,7 +12,8 @@
 
 static int av1d_fill_picparams(Av1CodecContext *ctx, DXVA_PicParams_AV1 *pp)
 {
-    int i, j, uses_lr;
+    int i, j, loop_cnt, uses_lr;
+    RK_U8 is_rk3588;
     AV1Context *h = ctx->priv_data;
     const AV1RawSequenceHeader *seq = h->sequence_header;
     const AV1RawFrameHeader *frame_header = h->raw_frame_header;
@@ -41,38 +31,32 @@ static int av1d_fill_picparams(Av1CodecContext *ctx, DXVA_PicParams_AV1 *pp)
     pp->max_width  = seq->max_frame_width_minus_1 + 1;
     pp->max_height = seq->max_frame_height_minus_1 + 1;
 
+    pp->CurrPic.Index7Bits  = h->cur_frame.slot_index;
     pp->CurrPicTextureIndex = h->cur_frame.slot_index;
     pp->superres_denom      = frame_header->use_superres ? frame_header->coded_denom : AV1_SUPERRES_NUM;
     pp->bitdepth            = h->bit_depth;
     pp->seq_profile         = seq->seq_profile;
+    pp->frame_header_size   = h->frame_header_size;
 
     /* Tiling info */
     pp->tiles.cols = frame_header->tile_cols;
     pp->tiles.rows = frame_header->tile_rows;
     pp->tiles.context_update_id = frame_header->context_update_tile_id;
 
-    {
-        RK_U8 val = 0;
-        for (i = 0; i < pp->tiles.cols; i++) {
-            pp->tiles.widths[i] = val;
-            val += frame_header->width_in_sbs_minus_1[i] + 1;
-        }
-        pp->tiles.widths[i] = val;
+    for (i = 0; i < pp->tiles.cols; i++)
+        pp->tiles.widths[i] = frame_header->width_in_sbs_minus_1[i] + 1;
 
-        val = 0;
-        for (i = 0; i < pp->tiles.rows; i++) {
-            pp->tiles.heights[i] = val;
-            val += frame_header->height_in_sbs_minus_1[i] + 1;
-        }
-        pp->tiles.heights[i] = val;
-    }
+    for (i = 0; i < pp->tiles.rows; i++)
+        pp->tiles.heights[i] = frame_header->height_in_sbs_minus_1[i] + 1;
 
     for (i = 0; i < AV1_MAX_TILES; i++) {
         pp->tiles.tile_offset_start[i] = h->tile_offset_start[i];
         pp->tiles.tile_offset_end[i] = h->tile_offset_end[i];
     }
+
     pp->tiles.tile_sz_mag = h->raw_frame_header->tile_size_bytes_minus1;
     /* Coding tools */
+    pp->coding.current_operating_point      = seq->operating_point_idc[h->operating_point_idc];
     pp->coding.use_128x128_superblock       = seq->use_128x128_superblock;
     pp->coding.intra_edge_filter            = seq->enable_intra_edge_filter;
     pp->coding.interintra_compound          = seq->enable_interintra_compound;
@@ -109,17 +93,31 @@ static int av1d_fill_picparams(Av1CodecContext *ctx, DXVA_PicParams_AV1 *pp)
     pp->format.subsampling_x  = seq->color_config.subsampling_x;
     pp->format.subsampling_y  = seq->color_config.subsampling_y;
     pp->format.mono_chrome    = seq->color_config.mono_chrome;
-    pp->coded_lossless = h->cur_frame.coded_lossless;
+    pp->coded_lossless        = h->cur_frame.coded_lossless;
+    pp->all_lossless          = h->all_lossless;
     /* References */
     pp->primary_ref_frame = frame_header->primary_ref_frame;
+    pp->enable_order_hint = seq->enable_order_hint;
     pp->order_hint        = frame_header->order_hint;
     pp->order_hint_bits   = seq->enable_order_hint ? seq->order_hint_bits_minus_1 + 1 : 0;
 
+    pp->ref_frame_valued = frame_header->ref_frame_valued;
+    for (i = 0; i < AV1_REFS_PER_FRAME; i++)
+        pp->ref_frame_idx[i] = frame_header->ref_frame_idx[i];
+
     memset(pp->RefFrameMapTextureIndex, 0xFF, sizeof(pp->RefFrameMapTextureIndex));
-    for (i = 0; i < AV1_REFS_PER_FRAME; i++) {
+    is_rk3588 = mpp_get_soc_type() == ROCKCHIP_SOC_RK3588;
+    loop_cnt = is_rk3588 ? AV1_REFS_PER_FRAME : AV1_NUM_REF_FRAMES;
+    for (i = 0; i < loop_cnt; i++) {
         int8_t ref_idx = frame_header->ref_frame_idx[i];
-        AV1Frame *ref_frame = &h->ref[ref_idx];
-        RefInfo *ref_i = ref_frame->ref;
+        AV1Frame *ref_frame;
+        RefInfo *ref_i;
+
+        if (is_rk3588)
+            ref_frame = &h->ref[ref_idx];
+        else
+            ref_frame = &h->ref[i];
+        ref_i = ref_frame->ref;
 
         if (ref_frame->f) {
             pp->frame_refs[i].width  = mpp_frame_get_width(ref_frame->f);
@@ -143,6 +141,7 @@ static int av1d_fill_picparams(Av1CodecContext *ctx, DXVA_PicParams_AV1 *pp)
         pp->frame_refs[i].wmtype    = h->cur_frame.gm_params[AV1_REF_FRAME_LAST + i].wmtype;
         for (j = 0; j < 6; ++j) {
             pp->frame_refs[i].wmmat[j] = h->cur_frame.gm_params[AV1_REF_FRAME_LAST + i].wmmat[j];
+            pp->frame_refs[i].wmmat_val[j] = h->cur_frame.gm_params[AV1_REF_FRAME_LAST + i].wmmat_val[j];
         }
         pp->frame_refs[i].alpha = h->cur_frame.gm_params[AV1_REF_FRAME_LAST + i].alpha;
         pp->frame_refs[i].beta = h->cur_frame.gm_params[AV1_REF_FRAME_LAST + i].beta;
@@ -151,6 +150,22 @@ static int av1d_fill_picparams(Av1CodecContext *ctx, DXVA_PicParams_AV1 *pp)
     }
     for (i = 0; i < AV1_NUM_REF_FRAMES; i++) {
         AV1Frame *ref_frame = &h->ref[i];
+
+        pp->frame_ref_state[i].valid           = h->ref_s[i].valid         ;
+        pp->frame_ref_state[i].frame_id        = h->ref_s[i].frame_id      ;
+        pp->frame_ref_state[i].upscaled_width  = h->ref_s[i].upscaled_width;
+        pp->frame_ref_state[i].frame_width     = h->ref_s[i].frame_width   ;
+        pp->frame_ref_state[i].frame_height    = h->ref_s[i].frame_height  ;
+        pp->frame_ref_state[i].render_width    = h->ref_s[i].render_width  ;
+        pp->frame_ref_state[i].render_height   = h->ref_s[i].render_height ;
+        pp->frame_ref_state[i].frame_type      = h->ref_s[i].frame_type    ;
+        pp->frame_ref_state[i].subsampling_x   = h->ref_s[i].subsampling_x ;
+        pp->frame_ref_state[i].subsampling_y   = h->ref_s[i].subsampling_y ;
+        pp->frame_ref_state[i].bit_depth       = h->ref_s[i].bit_depth     ;
+        pp->frame_ref_state[i].order_hint      = h->ref_s[i].order_hint    ;
+
+        pp->ref_order_hint[i] = frame_header->ref_order_hint[i];
+
         if (ref_frame->slot_index < 0x7f)
             pp->RefFrameMapTextureIndex[i] = ref_frame->slot_index;
         else
@@ -192,6 +207,7 @@ static int av1d_fill_picparams(Av1CodecContext *ctx, DXVA_PicParams_AV1 *pp)
     pp->quantization.v_dc_delta_q    = frame_header->delta_q_v_dc;
     pp->quantization.u_ac_delta_q    = frame_header->delta_q_u_ac;
     pp->quantization.v_ac_delta_q    = frame_header->delta_q_v_ac;
+    pp->quantization.using_qmatrix   = frame_header->using_qmatrix;
     pp->quantization.qm_y            = frame_header->using_qmatrix ? frame_header->qm_y : 0xFF;
     pp->quantization.qm_u            = frame_header->using_qmatrix ? frame_header->qm_u : 0xFF;
     pp->quantization.qm_v            = frame_header->using_qmatrix ? frame_header->qm_v : 0xFF;
@@ -220,8 +236,11 @@ static int av1d_fill_picparams(Av1CodecContext *ctx, DXVA_PicParams_AV1 *pp)
             pp->segmentation.feature_data[i][j]    = frame_header->feature_value[i][j];
         }
     }
+    pp->segmentation.last_active     = frame_header->segmentation_id_last_active;
+    pp->segmentation.preskip         = frame_header->segmentation_id_preskip;
 
     /* Film grain */
+    pp->film_grain.matrix_coefficients      = seq->color_config.matrix_coefficients;
     if (apply_grain) {
         pp->film_grain.apply_grain              = 1;
         pp->film_grain.scaling_shift_minus8     = film_grain->grain_scaling_minus_8;
@@ -234,6 +253,7 @@ static int av1d_fill_picparams(Av1CodecContext *ctx, DXVA_PicParams_AV1 *pp)
         pp->film_grain.matrix_coeff_is_identity = (seq->color_config.matrix_coefficients == MPP_FRAME_SPC_RGB);
 
         pp->film_grain.grain_seed               = film_grain->grain_seed;
+        pp->film_grain.update_grain             = film_grain->update_grain;
         pp->film_grain.num_y_points             = film_grain->num_y_points;
         for (i = 0; i < film_grain->num_y_points; i++) {
             pp->film_grain.scaling_points_y[i][0] = film_grain->point_y_value[i];
@@ -266,6 +286,7 @@ static int av1d_fill_picparams(Av1CodecContext *ctx, DXVA_PicParams_AV1 *pp)
     }
     pp->upscaled_width = h->upscaled_width;
     pp->frame_to_show_map_idx = frame_header->frame_to_show_map_idx;
+    pp->show_existing_frame = frame_header->show_existing_frame;
     pp->frame_tag_size = h->frame_tag_size;
     pp->skip_ref0      = h->skip_ref0;
     pp->skip_ref1      = h->skip_ref1;
@@ -274,6 +295,7 @@ static int av1d_fill_picparams(Av1CodecContext *ctx, DXVA_PicParams_AV1 *pp)
     pp->cdfs = h->cdfs;
     pp->cdfs_ndvc = h->cdfs_ndvc;
     pp->tile_cols_log2 = frame_header->tile_cols_log2;
+    pp->tile_rows_log2 = frame_header->tile_rows_log2;
     // XXX: Setting the StatusReportFeedbackNumber breaks decoding on some drivers (tested on NVIDIA 457.09)
     // Status Reporting is not used by FFmpeg, hence not providing a number does not cause any issues
     //pp->StatusReportFeedbackNumber = 1 + DXVA_CONTEXT_REPORT_ID(avctx, ctx)++;
diff --git a/mpp/codec/dec/avs/avsd_parse.c b/mpp/codec/dec/avs/avsd_parse.c
index edac429fe..dab84bf40 100644
--- a/mpp/codec/dec/avs/avsd_parse.c
+++ b/mpp/codec/dec/avs/avsd_parse.c
@@ -262,11 +262,9 @@ static MPP_RET get_i_picture_header(BitReadCtx_t *bitctx, AvsdSeqHeader_t *vsh,
     READ_ONEBIT(bitctx, &ph->repeat_first_field);
     READ_ONEBIT(bitctx, &ph->fixed_picture_qp);
     READ_BITS(bitctx, 6, &ph->picture_qp);
-
     ph->skip_mode_flag = 0;
     if (!ph->progressive_frame && !ph->picture_structure)
         READ_ONEBIT(bitctx, &ph->skip_mode_flag);
-
     READ_BITS(bitctx, 4, &val_temp); //!< reserve 4 bits
     if (val_temp) {
         AVSD_DBG(AVSD_DBG_WARNNING, "reserve bits not equal to zeros.\n");
diff --git a/mpp/codec/dec/avs2/avs2d_api.c b/mpp/codec/dec/avs2/avs2d_api.c
index 17c7e081b..40b516829 100644
--- a/mpp/codec/dec/avs2/avs2d_api.c
+++ b/mpp/codec/dec/avs2/avs2d_api.c
@@ -261,7 +261,6 @@ MPP_RET avs2d_callback(void *decoder, void *info)
 {
     MPP_RET ret = MPP_ERR_UNKNOW;
     Avs2dCtx_t *p_dec = (Avs2dCtx_t *)decoder;
-    Avs2dFrameMgr_t *mgr = &p_dec->frm_mgr;
     DecCbHalDone *ctx = (DecCbHalDone *)info;
     HalDecTask *task_dec = (HalDecTask *)ctx->task;
     MppFrame mframe = NULL;
@@ -269,6 +268,7 @@ MPP_RET avs2d_callback(void *decoder, void *info)
     RK_U32 i = 0;
     RK_U32 error = 0;
     RK_U32 discard = 0;
+    RK_U32 ref_used = task_dec->flags.ref_info_valid ? task_dec->flags.ref_used : 0xff;
     RK_U32 ref_used_flag = 0;
 
     AVS2D_PARSE_TRACE("In.");
@@ -287,22 +287,22 @@ MPP_RET avs2d_callback(void *decoder, void *info)
             discard = 1;
         }
     } else {
-        if (task_dec->flags.ref_miss & task_dec->flags.ref_used) {
+        if (task_dec->flags.ref_miss & ref_used) {
             discard = 1;
             AVS2D_DBG(AVS2D_DBG_CALLBACK, "[CALLBACK]: fake ref used, miss 0x%x used 0x%x\n",
-                      task_dec->flags.ref_miss, task_dec->flags.ref_used);
+                      task_dec->flags.ref_miss, ref_used);
         }
     }
 
     for (i = 0; i < AVS2_MAX_REFS; i++) {
-        if (!mgr->refs[i] || !mgr->refs[i]->frame || mgr->refs[i]->slot_idx < 0)
+        if (task_dec->refer[i] < 0)
             continue;
 
-        mpp_buf_slot_get_prop(p_dec->frame_slots, mgr->refs[i]->slot_idx, SLOT_FRAME_PTR, &ref_frm);
+        mpp_buf_slot_get_prop(p_dec->frame_slots, task_dec->refer[i], SLOT_FRAME_PTR, &ref_frm);
         if (!ref_frm)
             continue;
 
-        ref_used_flag = (task_dec->flags.ref_used >> i) & 1;
+        ref_used_flag = (ref_used >> i) & 1;
         //TODO: In fast mode, ref list isn't kept sync with task flag.ref_used
         AVS2D_DBG(AVS2D_DBG_CALLBACK, "[CALLBACK]: ref_frm poc %d, err %d, dis %d, ref_used %d\n",
                   mpp_frame_get_poc(ref_frm), mpp_frame_get_errinfo(ref_frm),
diff --git a/mpp/codec/dec/avs2/avs2d_dpb.c b/mpp/codec/dec/avs2/avs2d_dpb.c
index 5d307ecc5..31e61e6b7 100644
--- a/mpp/codec/dec/avs2/avs2d_dpb.c
+++ b/mpp/codec/dec/avs2/avs2d_dpb.c
@@ -513,13 +513,14 @@ static Avs2dFrame_t *dpb_alloc_frame(Avs2dCtx_t *p_dec, HalDecTask *task)
         // fbc output frame update
         mpp_frame_set_offset_y(mframe, 8);
         ver_stride += 16;
-    }
+    } else if (MPP_FRAME_FMT_IS_TILE(p_dec->init.cfg->base.out_fmt))
+        mpp_frame_set_fmt(mframe, mpp_frame_get_fmt(mframe) | (p_dec->init.cfg->base.out_fmt & (MPP_FRAME_TILE_FLAG)));
 
     if (p_dec->is_hdr)
         mpp_frame_set_fmt(mframe, mpp_frame_get_fmt(mframe) | MPP_FRAME_HDR);
 
     if (p_dec->init.cfg->base.enable_thumbnail && p_dec->init.hw_info->cap_down_scale)
-        mpp_frame_set_thumbnail_en(mframe, 1);
+        mpp_frame_set_thumbnail_en(mframe, p_dec->init.cfg->base.enable_thumbnail);
     else
         mpp_frame_set_thumbnail_en(mframe, 0);
 
@@ -535,6 +536,7 @@ static Avs2dFrame_t *dpb_alloc_frame(Avs2dCtx_t *p_dec, HalDecTask *task)
     if (p_dec->got_exh) {
         mpp_frame_set_color_primaries(mframe, exh->color_primaries);
         mpp_frame_set_color_trc(mframe, exh->transfer_characteristics);
+        mpp_frame_set_colorspace(mframe, exh->matrix_coefficients);
     }
     mpp_frame_set_content_light(mframe, p_dec->content_light);
     mpp_frame_set_mastering_display(mframe, p_dec->display_meta);
@@ -853,6 +855,6 @@ MPP_RET avs2d_dpb_flush(Avs2dCtx_t *p_dec)
     //!< reset dpb management
     dpb_init_management(mgr);
 
-    AVS2D_PARSE_TRACE("In.");
+    AVS2D_PARSE_TRACE("Out.");
     return ret;
 }
diff --git a/mpp/codec/dec/avs2/avs2d_global.h b/mpp/codec/dec/avs2/avs2d_global.h
index 9fd6ba8e6..887cd21c8 100644
--- a/mpp/codec/dec/avs2/avs2d_global.h
+++ b/mpp/codec/dec/avs2/avs2d_global.h
@@ -401,7 +401,6 @@ typedef struct avs2_dec_ctx_t {
     RK_U32                  got_vsh;
     RK_U32                  got_exh;
     RK_U32                  got_keyframe;
-    RK_U32                  vec_flag; //!< video_edit_code_flag
     RK_U8                   enable_wq;//!< seq&pic weight quant enable
     RK_U32                  prev_start_code;
     RK_U32                  new_seq_flag;
diff --git a/mpp/codec/dec/avs2/avs2d_parse.c b/mpp/codec/dec/avs2/avs2d_parse.c
index 6c7e4878b..e6cc6a5b8 100644
--- a/mpp/codec/dec/avs2/avs2d_parse.c
+++ b/mpp/codec/dec/avs2/avs2d_parse.c
@@ -304,6 +304,9 @@ static MPP_RET parse_extension_header(Avs2dCtx_t *p_dec, BitReadCtx_t *bitctx)
     case AVS2_SEQUENCE_DISPLAY_EXT_ID:
         FUN_CHECK(ret = parse_seq_dispay_ext_header(bitctx, &p_dec->exh));
         p_dec->got_exh = 1;
+        if (p_dec->exh.transfer_characteristics == MPP_FRAME_TRC_BT2020_10 ||
+            p_dec->exh.transfer_characteristics == MPP_FRAME_TRC_BT1361_ECG)
+            p_dec->is_hdr = 1;
         break;
     case AVS2_MASTERING_DISPLAY_AND_CONTENT_METADATA_EXT_ID:
         FUN_CHECK(ret = parse_mastering_display_and_content_meta(bitctx,
@@ -331,7 +334,6 @@ MPP_RET avs2d_reset_parser(Avs2dCtx_t *p_dec)
     p_dec->got_vsh      = 0;
     p_dec->got_exh      = 0;
     p_dec->got_keyframe = 0;
-    p_dec->vec_flag     = 0;
     p_dec->enable_wq    = 0;
     p_dec->new_frame_flag = 0;
     p_dec->new_seq_flag = 0;
@@ -398,6 +400,9 @@ MPP_RET avs2d_fill_parameters(Avs2dCtx_t *p_dec, Avs2dSyntax_t *syntax)
     pp->alpha_c_offset              = ph->alpha_c_offset;
     pp->beta_offset                 = ph->beta_offset;
 
+    //!< current poc
+    pp->cur_poc = ph->poi;
+
     //!< picture reference params
     refp->ref_pic_num = mgr->num_of_ref;
     memset(refp->ref_poc_list, -1, sizeof(refp->ref_poc_list));
@@ -409,7 +414,7 @@ MPP_RET avs2d_fill_parameters(Avs2dCtx_t *p_dec, Avs2dSyntax_t *syntax)
     alfp->enable_pic_alf_y  = ph->enable_pic_alf_y;
     alfp->enable_pic_alf_cb = ph->enable_pic_alf_cb;
     alfp->enable_pic_alf_cr = ph->enable_pic_alf_cr;
-    alfp->alf_filter_num_minus1 = ph->alf_filter_num - 1;
+    alfp->alf_filter_num_minus1 = (ph->alf_filter_num > 0) ? (ph->alf_filter_num - 1) : 0;
     memcpy(alfp->alf_coeff_idx_tab, ph->alf_coeff_idx_tab, sizeof(ph->alf_coeff_idx_tab));
     memcpy(alfp->alf_coeff_y, ph->alf_coeff_y, sizeof(ph->alf_coeff_y));
     memcpy(alfp->alf_coeff_cb, ph->alf_coeff_cb, sizeof(ph->alf_coeff_cb));
@@ -546,7 +551,7 @@ MPP_RET avs2d_parse_prepare_split(Avs2dCtx_t *p_dec, MppPacket *pkt, HalDecTask
             p_curdata = p_end - remain + 1;
         }
 
-        if (p_dec->new_frame_flag || (p_dec->p_nals[p_dec->nal_cnt - 1].eof == 1)) {
+        if (p_dec->new_frame_flag || (p_dec->nal_cnt > 1 && p_dec->p_nals[p_dec->nal_cnt - 1].eof == 1)) {
             task->valid = 1;
             break;
         }
@@ -609,7 +614,9 @@ MPP_RET avs2d_parse_prepare_fast(Avs2dCtx_t *p_dec, MppPacket *pkt, HalDecTask *
         }
     }
 
-    mpp_packet_set_pos(pkt, p_curdata);
+    // sequence_end_code and video_edit_code at the end of a packet will be ignored.
+    mpp_packet_set_pos(pkt, p_end + 1);
+    AVS2D_PARSE_TRACE("after split, remain %d, task->valid %d\n", remain, task->valid);
 
     AVS2D_PARSE_TRACE("Out.");
     return ret;
@@ -624,7 +631,7 @@ MPP_RET avs2d_parse_stream(Avs2dCtx_t *p_dec, HalDecTask *task)
     for (i = 0 ; i < p_dec->nal_cnt; i++) {
         RK_U32 startcode = p_nalu->header;
 
-        AVS2D_PARSE_TRACE("start code 0x%08x\n", startcode);
+        AVS2D_PARSE_TRACE("start code[%d] 0x%08x\n", i, startcode);
         if (!AVS2_IS_SLICE_START_CODE(startcode)) {
             RK_U8 *data_ptr = p_dec->p_header->pbuf + p_nalu->data_pos;
             memset(&p_dec->bitctx, 0, sizeof(BitReadCtx_t));
@@ -653,14 +660,8 @@ MPP_RET avs2d_parse_stream(Avs2dCtx_t *p_dec, HalDecTask *task)
             ret = parse_extension_header(p_dec, &p_dec->bitctx);
             break;
         case AVS2_USER_DATA_START_CODE:
-            break;
         case AVS2_VIDEO_SEQUENCE_END_CODE:
-            p_dec->new_seq_flag = 0;
-            avs2d_dpb_flush(p_dec);
-            break;
         case AVS2_VIDEO_EDIT_CODE:
-            p_dec->vec_flag = 0;
-            avs2d_dpb_flush(p_dec);
             break;
         default:
             if (AVS2_IS_SLICE_START_CODE(startcode)) {
diff --git a/mpp/codec/dec/avs2/avs2d_ps.c b/mpp/codec/dec/avs2/avs2d_ps.c
index 3d99f7b84..fda298410 100644
--- a/mpp/codec/dec/avs2/avs2d_ps.c
+++ b/mpp/codec/dec/avs2/avs2d_ps.c
@@ -304,7 +304,6 @@ MPP_RET avs2d_parse_sequence_header(Avs2dCtx_t *p_dec)
     READ_ONEBIT(bitctx, &vsh->field_coded_sequence);
     READ_BITS(bitctx, 14, &vsh->horizontal_size);
     READ_BITS(bitctx, 14, &vsh->vertical_size);
-    mpp_err_f("video resolution %dx%d\n", vsh->horizontal_size, vsh->vertical_size);
     if (vsh->horizontal_size < 16 || vsh->vertical_size < 16) {
         ret = MPP_NOK;
         mpp_err_f("invalid sequence width(%d), height(%d).\n",
diff --git a/mpp/codec/dec/h264/h264d_api.c b/mpp/codec/dec/h264/h264d_api.c
index 2edfab298..df2250fba 100644
--- a/mpp/codec/dec/h264/h264d_api.c
+++ b/mpp/codec/dec/h264/h264d_api.c
@@ -89,6 +89,7 @@ static MPP_RET free_cur_ctx(H264dCurCtx_t *p_Cur)
 
         MPP_FREE(p_Cur->subsps);
         MPP_FREE(p_Cur->sei);
+        MPP_FREE(p_Cur->hdr_dynamic_meta);
     }
 
 __RETURN:
@@ -396,13 +397,13 @@ MPP_RET h264d_reset(void *decoder)
 
     INP_CHECK(ret, !decoder);
 
-    FUN_CHECK(ret = flush_dpb(p_Dec->p_Vid->p_Dpb_layer[0], 1));
-    FUN_CHECK(ret = init_dpb(p_Dec->p_Vid, p_Dec->p_Vid->p_Dpb_layer[0], 1));
+    flush_dpb(p_Dec->p_Vid->p_Dpb_layer[0], 1);
+    init_dpb(p_Dec->p_Vid, p_Dec->p_Vid->p_Dpb_layer[0], 1);
     if (p_Dec->mvc_valid) {
         // layer_id == 1
-        FUN_CHECK(ret = flush_dpb(p_Dec->p_Vid->p_Dpb_layer[1], 1));
-        FUN_CHECK(ret = init_dpb(p_Dec->p_Vid, p_Dec->p_Vid->p_Dpb_layer[1], 2));
-        FUN_CHECK(ret = check_mvc_dpb(p_Dec->p_Vid, p_Dec->p_Vid->p_Dpb_layer[0], p_Dec->p_Vid->p_Dpb_layer[1]));
+        flush_dpb(p_Dec->p_Vid->p_Dpb_layer[1], 1);
+        init_dpb(p_Dec->p_Vid, p_Dec->p_Vid->p_Dpb_layer[1], 2);
+        check_mvc_dpb(p_Dec->p_Vid, p_Dec->p_Vid->p_Dpb_layer[0], p_Dec->p_Vid->p_Dpb_layer[1]);
     }
     flush_dpb_buf_slot(p_Dec);
     //!< reset input parameter
@@ -451,8 +452,6 @@ MPP_RET h264d_reset(void *decoder)
 
 __RETURN:
     return ret = MPP_OK;
-__FAILED:
-    return ret = MPP_NOK;
 }
 
 /*!
@@ -522,7 +521,7 @@ MPP_RET h264d_prepare(void *decoder, MppPacket pkt, HalDecTask *task)
     INP_CHECK(ret, !decoder && !pkt && !task);
 
     p_Inp = p_Dec->p_Inp;
-    if (p_Inp->has_get_eos || p_Dec->errctx.un_spt_flag) {
+    if (p_Inp->has_get_eos) {
         mpp_packet_set_length(pkt, 0);
         task->flags.eos = mpp_packet_get_eos(pkt);
         goto __RETURN;
diff --git a/mpp/codec/dec/h264/h264d_fill.c b/mpp/codec/dec/h264/h264d_fill.c
index 68353b6d7..6d3f05c96 100644
--- a/mpp/codec/dec/h264/h264d_fill.c
+++ b/mpp/codec/dec/h264/h264d_fill.c
@@ -273,6 +273,15 @@ void fill_picparams(H264dVideoCtx_t *p_Vid, DXVA_PicParams_H264_MVC *pp)
     }
 
     p_Vid->spspps_update = 0;
+
+    //!< for fpga test
+    pp->seq_parameter_set_id        = p_Vid->active_sps->seq_parameter_set_id;
+    pp->pps_seq_parameter_set_id    = p_Vid->active_pps->seq_parameter_set_id;
+    pp->pps_pic_parameter_set_id    = p_Vid->active_pps->pic_parameter_set_id;
+    pp->profile_idc                 = p_Vid->active_sps->profile_idc;
+    pp->constraint_set3_flag        = p_Vid->active_sps->constrained_set3_flag;
+    pp->qpprime_y_zero_transform_bypass_flag = p_Vid->active_sps->qpprime_y_zero_transform_bypass_flag;;
+    pp->mvc_extension_enable        = p_Vid->active_subsps ? 1 : 0;
 }
 
 /*!
diff --git a/mpp/codec/dec/h264/h264d_global.h b/mpp/codec/dec/h264/h264d_global.h
index e3d7f16ad..8126d9834 100644
--- a/mpp/codec/dec/h264/h264d_global.h
+++ b/mpp/codec/dec/h264/h264d_global.h
@@ -971,6 +971,8 @@ typedef struct h264d_cur_ctx_t {
     RK_S32                    abs_diff_view_idx_minus1[2][MAX_REORDER_TIMES];
 
     struct h264_drpm_t        *dec_ref_pic_marking_buffer[MAX_MARKING_TIMES];
+    MppFrameHdrDynamicMeta    *hdr_dynamic_meta;
+    RK_U32                    hdr_dynamic;
 } H264dCurCtx_t;
 
 //!< parameters for video decoder
diff --git a/mpp/codec/dec/h264/h264d_init.c b/mpp/codec/dec/h264/h264d_init.c
index fc2348dc1..655644c74 100644
--- a/mpp/codec/dec/h264/h264d_init.c
+++ b/mpp/codec/dec/h264/h264d_init.c
@@ -454,6 +454,10 @@ static MPP_RET dpb_mark_malloc(H264dVideoCtx_t *p_Vid, H264_StorePic_t *dec_pic)
                     fmt |= (out_fmt & MPP_FRAME_FBC_MASK);
                 } while (0);
 
+                p_Dec->cfg->base.out_fmt = fmt;
+                out_fmt = fmt;
+            } else if (MPP_FRAME_FMT_IS_TILE(out_fmt)) {
+                fmt |= (out_fmt & MPP_FRAME_TILE_FLAG);
                 p_Dec->cfg->base.out_fmt = fmt;
                 out_fmt = fmt;
             }
@@ -525,7 +529,7 @@ static MPP_RET dpb_mark_malloc(H264dVideoCtx_t *p_Vid, H264_StorePic_t *dec_pic)
             }
 
             if (p_Dec->cfg->base.enable_thumbnail && p_Dec->hw_info->cap_down_scale)
-                mpp_frame_set_thumbnail_en(p_Dec->curframe, 1);
+                mpp_frame_set_thumbnail_en(p_Dec->curframe, p_Dec->cfg->base.enable_thumbnail);
             else
                 mpp_frame_set_thumbnail_en(p_Dec->curframe, 0);
 
@@ -542,6 +546,8 @@ static MPP_RET dpb_mark_malloc(H264dVideoCtx_t *p_Vid, H264_StorePic_t *dec_pic)
                     impl->color_primaries = p->colour_primaries;
                     impl->color_trc = p->transfer_characteristics;
                     impl->colorspace = p->matrix_coefficients;
+                    if (impl->color_trc == MPP_FRAME_TRC_SMPTEST2084)
+                        impl->fmt |= MPP_FRAME_HDR;
                 } else {
                     impl->color_primaries = MPP_FRAME_PRI_UNSPECIFIED;
                     impl->color_trc = MPP_FRAME_TRC_UNSPECIFIED;
@@ -549,6 +555,12 @@ static MPP_RET dpb_mark_malloc(H264dVideoCtx_t *p_Vid, H264_StorePic_t *dec_pic)
                 }
             }
 
+            if (p_Vid->p_Cur->hdr_dynamic && p_Vid->p_Cur->hdr_dynamic_meta) {
+                impl->hdr_dynamic_meta = p_Vid->p_Cur->hdr_dynamic_meta;
+                p_Vid->p_Cur->hdr_dynamic = 0;
+                impl->fmt |= MPP_FRAME_HDR;
+            }
+
             impl->poc = dec_pic->poc;
             impl->viewid = dec_pic->layer_id;
             impl->status.is_intra = dec_pic->slice_type == H264_I_SLICE;
@@ -632,6 +644,7 @@ static MPP_RET alloc_decpic(H264_SLICE_t *currSlice)
     H264dVideoCtx_t *p_Vid = currSlice->p_Vid;
     H264_SPS_t *active_sps = p_Vid->active_sps;
     H264_DpbBuf_t *p_Dpb = currSlice->p_Dpb;
+    H264_DecCtx_t *p_Dec = p_Vid->p_Dec;
 
     dec_pic = alloc_storable_picture(p_Vid, currSlice->structure);
     MEM_CHECK(ret, dec_pic);
@@ -714,7 +727,9 @@ static MPP_RET alloc_decpic(H264_SLICE_t *currSlice)
     dec_pic->combine_flag = get_field_dpb_combine_flag(p_Dpb->last_picture, dec_pic);
     /* malloc dpb_memory */
     FUN_CHECK(ret = dpb_mark_malloc(p_Vid, dec_pic));
-    FUN_CHECK(ret = check_dpb_discontinuous(p_Vid->last_pic, dec_pic, currSlice));
+    if (!p_Dec->cfg->base.disable_dpb_chk) {
+        FUN_CHECK(ret = check_dpb_discontinuous(p_Vid->last_pic, dec_pic, currSlice));
+    }
     dec_pic->mem_malloc_type = Mem_Malloc;
     dec_pic->colmv_no_used_flag = 0;
     p_Vid->dec_pic = dec_pic;
@@ -1130,7 +1145,7 @@ static MPP_RET init_lists_p_slice_mvc(H264_SLICE_t *currSlice)
     }
 
     currSlice->listXsizeP[1] = 0;
-    if (currSlice->mvcExt.valid && currSlice->svc_extension_flag == 0) {
+    if (currSlice->mvcExt.valid && p_Vid->active_mvc_sps_flag && currSlice->svc_extension_flag == 0) {
         RK_S32 curr_layer_id = currSlice->layer_id;
         currSlice->fs_listinterview0 = mpp_calloc(H264_FrameStore_t*, p_Dpb->size);
         MEM_CHECK(ret, currSlice->fs_listinterview0);
@@ -1297,7 +1312,7 @@ static MPP_RET init_lists_b_slice_mvc(H264_SLICE_t *currSlice)
             currSlice->listB[1][1] = tmp_s;
         }
     }
-    if (currSlice->mvcExt.valid && currSlice->svc_extension_flag == 0) {
+    if (currSlice->mvcExt.valid && p_Vid->active_mvc_sps_flag && currSlice->svc_extension_flag == 0) {
         RK_S32 curr_layer_id = currSlice->layer_id;
         // B-Slice
         currSlice->fs_listinterview0 = mpp_calloc(H264_FrameStore_t*, p_Dpb->size);
@@ -1542,12 +1557,6 @@ static void check_refer_picture_lists(H264_SLICE_t *currSlice)
             H264D_DBG(H264D_DBG_DPB_REF_ERR, "list1 dpb: cur_err_flag=%d, pps_refs=%d, over_flag=%d, num_ref_l1=%d\n",
                       p_err->cur_err_flag, pps_refs, over_flag, active_l1);
         }
-        //!< B_SLICE only has one refer
-        if ((currSlice->active_sps->vui_seq_parameters.num_reorder_frames > 1)
-            && (currSlice->p_Dpb->ref_frames_in_buffer < 2)) {
-            p_err->cur_err_flag |= 1;
-            H264D_DBG(H264D_DBG_DPB_REF_ERR, "[DPB_REF_ERR] error, B frame only has one refer");
-        }
     }
 
 #endif
diff --git a/mpp/codec/dec/h264/h264d_parse.c b/mpp/codec/dec/h264/h264d_parse.c
index 3cd7ad029..f920a30fe 100644
--- a/mpp/codec/dec/h264/h264d_parse.c
+++ b/mpp/codec/dec/h264/h264d_parse.c
@@ -32,6 +32,7 @@
 #include "h264d_sei.h"
 #include "h264d_init.h"
 #include "h264d_fill.h"
+#include "rk_hdr_meta_com.h"
 
 #define  HEAD_SYNTAX_MAX_SIZE        (12800)
 #define NALU_TYPE_NORMAL_LENGTH      (1)
@@ -232,6 +233,12 @@ static MPP_RET parser_one_nalu(H264_SLICE_t *currSlice)
         currSlice->p_Dec->nalu_ret = NaluNotSupport;
         return MPP_OK;
     }
+    //!< check whether supprot mvc
+    if (currSlice->mvcExt.view_id && currSlice->mvcExt.valid &&
+        !currSlice->p_Dec->cfg->base.enable_mvc) {
+        currSlice->p_Dec->nalu_ret = MvcDisAble;
+        return MPP_OK;
+    }
 
     //!< nalu_parse
     switch (currSlice->p_Cur->nalu.nalu_type) {
@@ -240,8 +247,6 @@ static MPP_RET parser_one_nalu(H264_SLICE_t *currSlice)
         H264D_DBG(H264D_DBG_PARSE_NALU, "nalu_type=SLICE.");
         FUN_CHECK(ret = process_slice(currSlice));
         currSlice->p_Dec->nalu_ret = StartOfPicture;
-        if (currSlice->layer_id && !currSlice->p_Dec->cfg->base.enable_mvc)
-            currSlice->p_Dec->nalu_ret = MvcDisAble;
         break;
     case H264_NALU_TYPE_SPS:
         H264D_DBG(H264D_DBG_PARSE_NALU, "nalu_type=SPS");
@@ -333,6 +338,41 @@ static MPP_RET add_empty_nalu(H264dCurStream_t *p_strm)
     return ret;
 }
 
+void mpp_h264d_fill_dynamic_meta(H264dCurCtx_t *p_Cur, const RK_U8 *data, RK_U32 size, RK_U32 hdr_fmt)
+{
+    MppFrameHdrDynamicMeta *hdr_dynamic_meta = p_Cur->hdr_dynamic_meta;
+
+    if (hdr_fmt == DOLBY)
+        size += 4;
+
+    if (hdr_dynamic_meta && (hdr_dynamic_meta->size < size)) {
+        mpp_free(hdr_dynamic_meta);
+        hdr_dynamic_meta = NULL;
+    }
+
+    if (!hdr_dynamic_meta) {
+        hdr_dynamic_meta = mpp_calloc_size(MppFrameHdrDynamicMeta,
+                                           sizeof(MppFrameHdrDynamicMeta) + size);
+        if (!hdr_dynamic_meta) {
+            mpp_err_f("malloc hdr dynamic data failed!\n");
+            return;
+        }
+    }
+    if (size && data) {
+        if (hdr_fmt == DOLBY) {
+            RK_U8 start_code[4] = {0, 0, 0, 1};
+
+            memcpy((RK_U8*)hdr_dynamic_meta->data, start_code, 4);
+            memcpy((RK_U8*)hdr_dynamic_meta->data + 4, (RK_U8*)data, size - 4);
+        } else
+            memcpy((RK_U8*)hdr_dynamic_meta->data, (RK_U8*)data, size);
+        hdr_dynamic_meta->size = size;
+        hdr_dynamic_meta->hdr_fmt = hdr_fmt;
+    }
+    p_Cur->hdr_dynamic_meta = hdr_dynamic_meta;
+    p_Cur->hdr_dynamic = 1;
+}
+
 static MPP_RET store_cur_nalu(H264dCurCtx_t *p_Cur, H264dCurStream_t *p_strm, H264dDxvaCtx_t *dxva_ctx)
 {
     MPP_RET ret = MPP_ERR_UNKNOW;
@@ -402,6 +442,11 @@ static MPP_RET store_cur_nalu(H264dCurCtx_t *p_Cur, H264dCurStream_t *p_strm, H2
         memcpy(p_des + sizeof(g_start_precode), p_strm->nalu_buf, p_strm->nalu_len);
         dxva_ctx->strm_offset += add_size;
     }
+
+    /* Dolby Vision RPUs masquerade as unregistered NALs of type 28. */
+    if (p_strm->nalu_type == H264_NALU_TYPE_UNSPECIFIED28)
+        mpp_h264d_fill_dynamic_meta(p_Cur, p_strm->nalu_buf + 2, p_strm->nalu_len - 2, DOLBY);
+
     if (h264d_debug & H264D_DBG_WRITE_ES_EN) {
         H264dInputCtx_t *p_Inp = p_Cur->p_Inp;
         if ((p_strm->nalu_type == H264_NALU_TYPE_SPS)
@@ -791,7 +836,6 @@ MPP_RET parse_prepare_avcC_header(H264dInputCtx_t *p_Inp, H264dCurCtx_t *p_Cur)
 
     H264dCurStream_t *p_strm = &p_Cur->strm;
     RK_U8 *pdata = p_Inp->in_buf;
-    RK_U64 extrasize = p_Inp->in_length;
     MppPacketImpl *pkt_impl  = (MppPacketImpl *)p_Inp->in_pkt;
 
     //!< free nalu_buffer
@@ -809,30 +853,24 @@ MPP_RET parse_prepare_avcC_header(H264dInputCtx_t *p_Inp, H264dCurCtx_t *p_Cur)
     p_Inp->sps_num = pdata[5] & 31;
 
     pdata += 6;
-    extrasize -= 6;
     for (i = 0; i < p_Inp->sps_num; ++i) {
         p_strm->nalu_len = U16_AT(pdata);
         pdata += 2;
-        extrasize -= 2;
         p_strm->nalu_type = H264_NALU_TYPE_SPS;
         p_strm->nalu_buf = pdata;
         FUN_CHECK(ret = store_cur_nalu(p_Cur, p_strm, p_Cur->p_Dec->dxva_ctx));
         pdata += p_strm->nalu_len;
-        extrasize -= p_strm->nalu_len;
     }
     p_strm->nalu_buf = NULL;
     p_Inp->pps_num = *pdata;
     ++pdata;
-    --extrasize;
     for (i = 0; i < p_Inp->pps_num; ++i) {
         p_strm->nalu_len = U16_AT(pdata);
         pdata += 2;
-        extrasize -= 2;
         p_strm->nalu_type = H264_NALU_TYPE_PPS;
         p_strm->nalu_buf = pdata;
         FUN_CHECK(ret = store_cur_nalu(p_Cur, p_strm, p_Cur->p_Dec->dxva_ctx));
         pdata += p_strm->nalu_len;
-        extrasize -= p_strm->nalu_len;
     }
     pkt_impl->length = 0;
     p_strm->nalu_buf = NULL;
diff --git a/mpp/codec/dec/h264/h264d_sei.c b/mpp/codec/dec/h264/h264d_sei.c
index be4217b56..2ae3b7192 100644
--- a/mpp/codec/dec/h264/h264d_sei.c
+++ b/mpp/codec/dec/h264/h264d_sei.c
@@ -17,6 +17,7 @@
 
 #define MODULE_TAG  "h264d_sei"
 
+#include <limits.h>
 #include <stdio.h>
 #include <string.h>
 
@@ -249,6 +250,12 @@ MPP_RET process_sei(H264_SLICE_t *currSlice)
         tmp_byte = 0xFF;
         sei_msg->type = 0;
         while (tmp_byte == 0xFF) {
+            if (p_bitctx->bytes_left_ < 2 || sei_msg->type > INT_MAX - 255) {
+                mpp_err("parse payload_type error: byte_left %d payload_type %d\n",
+                        p_bitctx->bytes_left_, sei_msg->type);
+                return MPP_ERR_STREAM;
+            }
+
             READ_BITS(p_bitctx, 8, &tmp_byte);
             sei_msg->type += tmp_byte;
         }
@@ -256,10 +263,22 @@ MPP_RET process_sei(H264_SLICE_t *currSlice)
         tmp_byte = 0xFF;
         sei_msg->payload_size = 0;
         while (tmp_byte == 0xFF) {
+            if ((RK_S32)p_bitctx->bytes_left_ < sei_msg->payload_size + 1) {
+                mpp_err("parse payload_size error: byte_left %d payload_size %d\n",
+                        p_bitctx->bytes_left_, sei_msg->payload_size + 1);
+                return MPP_ERR_STREAM;
+            }
+
             READ_BITS(p_bitctx, 8, &tmp_byte);
             sei_msg->payload_size += tmp_byte;
         }
 
+        if ((RK_S32)p_bitctx->bytes_left_ < sei_msg->payload_size) {
+            mpp_err("parse payload_size error: byte_left %d payload_size %d\n",
+                    p_bitctx->bytes_left_, sei_msg->payload_size);
+            return MPP_ERR_STREAM;
+        }
+
         H264D_DBG(H264D_DBG_SEI, "SEI type %d, payload size: %d\n", sei_msg->type, sei_msg->payload_size);
 
         memset(&payload_bitctx, 0, sizeof(payload_bitctx));
diff --git a/mpp/codec/dec/h264/h264d_slice.c b/mpp/codec/dec/h264/h264d_slice.c
index b3a7b306b..691a2ebb8 100644
--- a/mpp/codec/dec/h264/h264d_slice.c
+++ b/mpp/codec/dec/h264/h264d_slice.c
@@ -275,7 +275,7 @@ static MPP_RET check_sps_pps(H264_SPS_t *sps, H264_subSPS_t *subset_sps,
 
     ret |= (sps->seq_parameter_set_id > 31);
     ret |= (sps->separate_colour_plane_flag == 1);
-    ret |= (sps->chroma_format_idc == 3);
+    ret |= (sps->chroma_format_idc >= 3);
     ret |= (sps->bit_depth_luma_minus8 > 2);
     ret |= (sps->bit_depth_chroma_minus8 > 2);
     ret |= (sps->log2_max_frame_num_minus4 > 12);
diff --git a/mpp/codec/dec/h264/h264d_sps.c b/mpp/codec/dec/h264/h264d_sps.c
index 6b553e650..dfdf351e9 100644
--- a/mpp/codec/dec/h264/h264d_sps.c
+++ b/mpp/codec/dec/h264/h264d_sps.c
@@ -213,8 +213,11 @@ static MPP_RET parser_sps(BitReadCtx_t *p_bitctx, H264_SPS_t *cur_sps, H264_DecC
         || cur_sps->profile_idc == 86  || cur_sps->profile_idc == 118
         || cur_sps->profile_idc == 128 || cur_sps->profile_idc == 138) {
         READ_UE(p_bitctx, &cur_sps->chroma_format_idc);
-        if (cur_sps->chroma_format_idc > 2) {
-            H264D_ERR("ERROR: Not support chroma_format_idc=%d.", cur_sps->chroma_format_idc);
+        /* check invalid chroma format idc */
+        VAL_CHECK (ret, (cur_sps->chroma_format_idc <= H264_CHROMA_444));
+        /* TODO: check unsupport chroma format by hardware capacity */
+        if (cur_sps->chroma_format_idc > H264_CHROMA_422) {
+            H264D_ERR("ERROR: Not support chroma_format_idc %d", cur_sps->chroma_format_idc);
             p_Dec->errctx.un_spt_flag = MPP_FRAME_ERR_UNSUPPORT;
             goto __FAILED;
         }
diff --git a/mpp/codec/dec/h265/h265d_parser.c b/mpp/codec/dec/h265/h265d_parser.c
index 5f33565a3..28bef264b 100644
--- a/mpp/codec/dec/h265/h265d_parser.c
+++ b/mpp/codec/dec/h265/h265d_parser.c
@@ -750,11 +750,12 @@ static RK_S32 hls_slice_header(HEVCContext *s)
     }
     s->pps = (HEVCPPS*)s->pps_list[sh->pps_id];
 
-    if (s->sps != (HEVCSPS*)s->sps_list[s->pps->sps_id]) {
+    if (s->sps_need_upate || s->sps != (HEVCSPS*)s->sps_list[s->pps->sps_id]) {
         s->sps = (HEVCSPS*)s->sps_list[s->pps->sps_id];
         mpp_hevc_clear_refs(s);
 
         s->ps_need_upate = 1;
+        s->sps_need_upate = 0;
         ret = set_sps(s, s->sps);
         if (ret < 0)
             return ret;
@@ -1156,6 +1157,7 @@ static RK_S32 mpp_hevc_output_frame(void *ctx, int flush)
     H265dContext_t *h265dctx = (H265dContext_t *)ctx;
     HEVCContext *s = (HEVCContext *)h265dctx->priv_data;
     MppDecCfgSet *cfg = h265dctx->cfg;
+    RK_U32 find_next_ready = 0;
 
     if (cfg->base.fast_out)
         return mpp_hevc_out_dec_order(ctx);
@@ -1201,6 +1203,30 @@ static RK_S32 mpp_hevc_output_frame(void *ctx, int flush)
             h265d_dbg(H265D_DBG_REF,
                       "Output frame with POC %d frame->slot_index = %d\n", frame->poc, frame->slot_index);
 
+            do {
+                find_next_ready = 0;
+                for (i = 0; i < MPP_ARRAY_ELEMS(s->DPB); i++) {
+                    HEVCFrame *frame_next_ready = &s->DPB[i];
+                    if ((frame_next_ready->flags & HEVC_FRAME_FLAG_OUTPUT) &&
+                        frame_next_ready->sequence == s->seq_output) {
+                        if (frame_next_ready->poc == frame->poc + 1) {
+                            find_next_ready = 1;
+                            s->output_frame_idx = i;
+                            frame_next_ready->flags &= ~(HEVC_FRAME_FLAG_OUTPUT);
+                            frame = frame_next_ready;
+                            mpp_buf_slot_set_flag(s->slots, frame->slot_index, SLOT_QUEUE_USE);
+                            mpp_buf_slot_enqueue(s->slots, frame->slot_index, QUEUE_DISPLAY);
+                            h265d_dbg(H265D_DBG_REF,
+                                      "Output frame with POC %d frm_next_ready->slot_index = %d\n",
+                                      frame_next_ready->poc, frame_next_ready->slot_index);
+                            /* release any frames that are now unused */
+                            for (i = 0; i < MPP_ARRAY_ELEMS(s->DPB); i++) {
+                                mpp_hevc_unref_frame(s, &s->DPB[i], 0);
+                            }
+                        }
+                    }
+                }
+            } while (find_next_ready);
 
             return 1;
         }
@@ -1645,7 +1671,7 @@ static RK_S32 split_nal_units(HEVCContext *s, RK_U8 *buf, RK_U32 length)
 
         consumed = mpp_hevc_extract_rbsp(s, buf, extract_length, nal);
 
-        if (consumed <= 0) {
+        if (consumed < 0) {
             ret = MPP_ERR_STREAM;
             goto fail;
         }
@@ -2004,6 +2030,7 @@ MPP_RET h265d_parse(void *ctx, HalDecTask *task)
         s->task->syntax.data = s->hal_pic_private;
         s->task->syntax.number = 1;
         s->task->valid = 1;
+        s->ps_need_upate = 0;
     }
     if (s->eos) {
         h265d_flush(ctx);
@@ -2031,8 +2058,10 @@ MPP_RET h265d_deinit(void *ctx)
         mpp_frame_deinit(&s->DPB[i].frame);
     }
 
-    for (i = 0; i < MAX_VPS_COUNT; i++)
-        mpp_free(s->vps_list[i]);
+    for (i = 0; i < MAX_VPS_COUNT; i++) {
+        if (s->vps_list[i])
+            mpp_mem_pool_put(s->vps_pool, s->vps_list[i]);
+    }
     for (i = 0; i < MAX_SPS_COUNT; i++) {
         if (s->sps_list[i])
             mpp_mem_pool_put(s->sps_pool, s->sps_list[i]);
@@ -2067,6 +2096,8 @@ MPP_RET h265d_deinit(void *ctx)
         mpp_packet_deinit(&s->input_packet);
     }
 
+    if (s->vps_pool)
+        mpp_mem_pool_deinit(s->vps_pool);
     if (s->sps_pool)
         mpp_mem_pool_deinit(s->sps_pool);
 
@@ -2200,6 +2231,7 @@ MPP_RET h265d_init(void *ctx, ParserCfg *parser_cfg)
 
     s->pre_pps_id = -1;
 
+    s->vps_pool = mpp_mem_pool_init(sizeof(HEVCVPS));
     s->sps_pool = mpp_mem_pool_init(sizeof(HEVCSPS));
 
 #ifdef dump
diff --git a/mpp/codec/dec/h265/h265d_parser.h b/mpp/codec/dec/h265/h265d_parser.h
index 561d36f59..342af849c 100644
--- a/mpp/codec/dec/h265/h265d_parser.h
+++ b/mpp/codec/dec/h265/h265d_parser.h
@@ -134,16 +134,24 @@ typedef struct VUI {
     RK_S32 log2_max_mv_length_vertical;
 } VUI;
 
+/* ProfileTierLevel */
 typedef struct PTLCommon {
     RK_U8 profile_space;
     RK_U8 tier_flag;
     RK_U8 profile_idc;
     RK_U8 profile_compatibility_flag[32];
     RK_U8 level_idc;
+
     RK_U8 progressive_source_flag;
     RK_U8 interlaced_source_flag;
     RK_U8 non_packed_constraint_flag;
     RK_U8 frame_only_constraint_flag;
+
+    RK_S32 bit_depth_constraint;
+    H265ChromaFmt chroma_format_constraint;
+    RK_U8 intra_constraint_flag;
+    RK_U8 one_picture_only_constraint_flag;
+    RK_U8 lower_bitrate_constraint_flag;
 } PTLCommon;
 
 typedef struct PTL {
@@ -254,6 +262,19 @@ typedef struct HEVCSPS {
     RK_S32 max_transform_hierarchy_depth_inter;
     RK_S32 max_transform_hierarchy_depth_intra;
 
+    // SPS extension
+    RK_S32 sps_extension_flag;
+    RK_S32 sps_range_extension_flag;
+    RK_S32 transform_skip_rotation_enabled_flag;
+    RK_S32 transform_skip_context_enabled_flag;
+    RK_S32 implicit_rdpcm_enabled_flag;
+    RK_S32 explicit_rdpcm_enabled_flag;
+    RK_S32 extended_precision_processing_flag;
+    RK_S32 intra_smoothing_disabled_flag;
+    RK_S32 high_precision_offsets_enabled_flag;
+    RK_S32 persistent_rice_adaptation_enabled_flag;
+    RK_S32 cabac_bypass_alignment_enabled_flag;
+
     ///< coded frame dimension in various units
     RK_S32 width;
     RK_S32 height;
@@ -338,9 +359,18 @@ typedef struct HEVCPPS {
     RK_S32 num_extra_slice_header_bits;
     RK_U8 slice_header_extension_present_flag;
 
+    // PPS extension
     RK_U8 pps_extension_flag;
     RK_U8 pps_range_extensions_flag;
-    RK_U8 pps_extension_data_flag;
+    RK_U8 log2_max_transform_skip_block_size;
+    RK_U8 cross_component_prediction_enabled_flag;
+    RK_U8 chroma_qp_offset_list_enabled_flag;
+    RK_U8 diff_cu_chroma_qp_offset_depth;
+    RK_U8 chroma_qp_offset_list_len_minus1;
+    RK_S8 cb_qp_offset_list[6];
+    RK_S8 cr_qp_offset_list[6];
+    RK_U8 log2_sao_offset_scale_luma;
+    RK_U8 log2_sao_offset_scale_chroma;
 
     // Inferred parameters
     HevcPpsBufInfo bufs;
@@ -504,6 +534,7 @@ typedef struct HEVCContext {
     RK_U8 *sps_list[MAX_SPS_COUNT];
     RK_U8 *pps_list[MAX_PPS_COUNT];
 
+    MppMemPool vps_pool;
     MppMemPool sps_pool;
 
     SliceHeader sh;
@@ -614,6 +645,7 @@ typedef struct HEVCContext {
     RK_U8  miss_ref_flag;
     RK_U8  pre_pps_id;
     RK_U8  ps_need_upate;
+    RK_U8  sps_need_upate;
 
     /*temporary storage for slice_cut_param*/
     RK_U32  start_bit;
diff --git a/mpp/codec/dec/h265/h265d_parser2_syntax.c b/mpp/codec/dec/h265/h265d_parser2_syntax.c
index c58e56756..444973391 100644
--- a/mpp/codec/dec/h265/h265d_parser2_syntax.c
+++ b/mpp/codec/dec/h265/h265d_parser2_syntax.c
@@ -252,6 +252,31 @@ static void fill_picture_parameters(const HEVCContext *h,
     DO_REF_LIST(ST_CURR_AFT, RefPicSetStCurrAfter);
     DO_REF_LIST(LT_CURR, RefPicSetLtCurr);
 
+    // sps exension flags
+    pp->sps_extension_flag                          = sps->sps_extension_flag;;
+    pp->sps_range_extension_flag                    = sps->sps_range_extension_flag;;
+    pp->transform_skip_rotation_enabled_flag        = sps->transform_skip_rotation_enabled_flag;;
+    pp->transform_skip_context_enabled_flag         = sps->transform_skip_context_enabled_flag;;
+    pp->implicit_rdpcm_enabled_flag                 = sps->implicit_rdpcm_enabled_flag;;
+    pp->explicit_rdpcm_enabled_flag                 = sps->explicit_rdpcm_enabled_flag;;
+    pp->extended_precision_processing_flag          = sps->extended_precision_processing_flag;;
+    pp->intra_smoothing_disabled_flag               = sps->intra_smoothing_disabled_flag;;
+    pp->high_precision_offsets_enabled_flag         = sps->high_precision_offsets_enabled_flag;;
+    pp->persistent_rice_adaptation_enabled_flag     = sps->persistent_rice_adaptation_enabled_flag;;
+    pp->cabac_bypass_alignment_enabled_flag         = sps->cabac_bypass_alignment_enabled_flag;;
+
+    // pps exension flags
+    pp->cross_component_prediction_enabled_flag     = pps->cross_component_prediction_enabled_flag;
+    pp->chroma_qp_offset_list_enabled_flag          = pps->chroma_qp_offset_list_enabled_flag;
+
+    // PPS extension
+    pp->log2_max_transform_skip_block_size          = pps->log2_max_transform_skip_block_size;
+    pp->diff_cu_chroma_qp_offset_depth              = pps->diff_cu_chroma_qp_offset_depth;
+    pp->chroma_qp_offset_list_len_minus1            = pps->chroma_qp_offset_list_len_minus1;
+    for (i = 0; i < 6; i++) {
+        pp->cb_qp_offset_list[i] = pps->cb_qp_offset_list[i];
+        pp->cr_qp_offset_list[i] = pps->cr_qp_offset_list[i];
+    }
 }
 extern RK_U8 mpp_hevc_diag_scan4x4_x[16];
 extern RK_U8 mpp_hevc_diag_scan4x4_y[16];
diff --git a/mpp/codec/dec/h265/h265d_ps.c b/mpp/codec/dec/h265/h265d_ps.c
index a6aa88215..29fe5a70b 100644
--- a/mpp/codec/dec/h265/h265d_ps.c
+++ b/mpp/codec/dec/h265/h265d_ps.c
@@ -125,6 +125,16 @@ const RK_U8 mpp_hevc_diag_scan8x8_y[64] = {
     5, 7, 6, 7,
 };
 
+static RK_U32 rkv_len_align_422(RK_U32 val)
+{
+    return (2 * MPP_ALIGN(val, 16));
+}
+
+static RK_U32 rkv_len_align_444(RK_U32 val)
+{
+    return (3 * MPP_ALIGN(val, 16));
+}
+
 int mpp_hevc_decode_short_term_rps(HEVCContext *s, ShortTermRPS *rps,
                                    const HEVCSPS *sps, RK_S32 is_slice_header)
 {
@@ -132,7 +142,6 @@ int mpp_hevc_decode_short_term_rps(HEVCContext *s, ShortTermRPS *rps,
     RK_U8 rps_predict = 0;
     RK_S32 delta_poc;
     RK_S32 k0 = 0;
-    RK_S32 k1 = 0;
     RK_S32 k  = 0;
     RK_S32 i;
 
@@ -185,8 +194,6 @@ int mpp_hevc_decode_short_term_rps(HEVCContext *s, ShortTermRPS *rps,
                 rps->delta_poc[k] = delta_poc;
                 if (delta_poc < 0)
                     k0++;
-                else
-                    k1++;
                 k++;
             }
         }
@@ -289,6 +296,11 @@ static RK_S32 decode_profile_tier_level(HEVCContext *s, PTLCommon *ptl)
     READ_ONEBIT(gb, &ptl->non_packed_constraint_flag);
     READ_ONEBIT(gb, &ptl->frame_only_constraint_flag);
 
+    ptl->bit_depth_constraint = (ptl->profile_idc == MPP_PROFILE_HEVC_MAIN_10) ? 10 : 8;
+    ptl->chroma_format_constraint = H265_CHROMA_420;
+    ptl->intra_constraint_flag = 0;
+    ptl->lower_bitrate_constraint_flag = 1;
+
     SKIP_BITS(gb, 16); // XXX_reserved_zero_44bits[0..15]
     SKIP_BITS(gb, 16); // XXX_reserved_zero_44bits[16..31]
     SKIP_BITS(gb, 12); // XXX_reserved_zero_44bits[32..43]
@@ -302,6 +314,7 @@ static RK_S32 parse_ptl(HEVCContext *s, PTL *ptl, int max_num_sub_layers)
     RK_S32 i;
     HEVCLocalContext *lc = s->HEVClc;
     BitReadCtx_t *gb = &lc->gb;
+
     decode_profile_tier_level(s, &ptl->general_ptl);
     READ_BITS(gb, 8, &ptl->general_ptl.level_idc);
 
@@ -1027,7 +1040,7 @@ int mpp_hevc_decode_nal_vps(HEVCContext *s)
     BitReadCtx_t *gb = &s->HEVClc->gb;
     RK_U32 vps_id = 0;
     HEVCVPS *vps = NULL;
-    RK_U8 *vps_buf = mpp_calloc(RK_U8, sizeof(HEVCVPS));
+    RK_U8 *vps_buf = mpp_mem_pool_get(s->vps_pool);
     RK_S32 value = 0;
 
     if (!vps_buf)
@@ -1143,10 +1156,10 @@ int mpp_hevc_decode_nal_vps(HEVCContext *s)
 
     if (s->vps_list[vps_id] &&
         !memcmp(s->vps_list[vps_id], vps_buf, sizeof(HEVCVPS))) {
-        mpp_free(vps_buf);
+        mpp_mem_pool_put(s->vps_pool, vps_buf);
     } else {
         if (s->vps_list[vps_id] != NULL) {
-            mpp_free(s->vps_list[vps_id]);
+            mpp_mem_pool_put(s->vps_pool, s->vps_list[vps_id]);
         }
         s->vps_list[vps_id] = vps_buf;
         s->ps_need_upate = 1;
@@ -1155,7 +1168,7 @@ int mpp_hevc_decode_nal_vps(HEVCContext *s)
     return 0;
 __BITREAD_ERR:
 err:
-    mpp_free(vps_buf);
+    mpp_mem_pool_put(s->vps_pool, vps_buf);
     return  MPP_ERR_STREAM;
 }
 
@@ -1225,18 +1238,21 @@ static RK_S32 decode_vui(HEVCContext *s, HEVCSPS *sps)
 
     READ_ONEBIT(gb, &vui->default_display_window_flag);
     if (vui->default_display_window_flag) {
-        //TODO: * 2 is only valid for 420
         READ_UE(gb, &vui->def_disp_win.left_offset);
-        vui->def_disp_win.left_offset  =  vui->def_disp_win.left_offset * 2;
-
-        READ_UE(gb, &vui->def_disp_win.right_offset);
-        vui->def_disp_win.right_offset  =  vui->def_disp_win.right_offset * 2;
-
-        READ_UE(gb, &vui->def_disp_win.right_offset);
-        vui->def_disp_win.top_offset = vui->def_disp_win.top_offset * 2;
-
         READ_UE(gb, &vui->def_disp_win.right_offset);
-        vui->def_disp_win.bottom_offset = vui->def_disp_win.bottom_offset * 2;
+        READ_UE(gb, &vui->def_disp_win.top_offset);
+        READ_UE(gb, &vui->def_disp_win.bottom_offset);
+        if (sps) {
+            if (sps->chroma_format_idc == H265_CHROMA_420) {
+                vui->def_disp_win.left_offset   *= 2;
+                vui->def_disp_win.right_offset  *= 2;
+                vui->def_disp_win.top_offset    *= 2;
+                vui->def_disp_win.bottom_offset *= 2;
+            } else if (sps->chroma_format_idc == H265_CHROMA_422) {
+                vui->def_disp_win.left_offset   *= 2;
+                vui->def_disp_win.right_offset  *= 2;
+            }
+        }
 
 #if 0
         if (s->apply_defdispwin &&
@@ -1374,7 +1390,7 @@ static int scaling_list_data(HEVCContext *s, ScalingList *sl, HEVCSPS *sps)
                 }
             }
         }
-    if (sps->chroma_format_idc == 3) {
+    if (sps->chroma_format_idc == H265_CHROMA_444) {
         for (i = 0; i < 64; i++) {
             sl->sl[3][1][i] = sl->sl[2][1][i];
             sl->sl[3][2][i] = sl->sl[2][2][i];
@@ -1448,13 +1464,8 @@ RK_S32 mpp_hevc_decode_nal_sps(HEVCContext *s)
     }
 
     READ_UE(gb, &sps->chroma_format_idc);
-    if (sps->chroma_format_idc != 1) {
-        mpp_err("chroma_format_idc != 1\n");
-        ret =  MPP_ERR_PROTOL;
-        goto err;
-    }
 
-    if (sps->chroma_format_idc == 3)
+    if (sps->chroma_format_idc == H265_CHROMA_444)
         READ_ONEBIT(gb, &sps->separate_colour_plane_flag);
 
     READ_UE(gb, &sps->width);
@@ -1463,32 +1474,19 @@ RK_S32 mpp_hevc_decode_nal_sps(HEVCContext *s)
     READ_ONEBIT(gb, &value);
 
     if (value) { // pic_conformance_flag
-        //TODO: * 2 is only valid for 420
         READ_UE(gb, &sps->pic_conf_win.left_offset);
-        sps->pic_conf_win.left_offset   = sps->pic_conf_win.left_offset * 2;
         READ_UE(gb, &sps->pic_conf_win.right_offset);
-        sps->pic_conf_win.right_offset  = sps->pic_conf_win.right_offset * 2;
         READ_UE(gb, &sps->pic_conf_win.top_offset);
-        sps->pic_conf_win.top_offset    =  sps->pic_conf_win.top_offset * 2;
         READ_UE(gb, &sps->pic_conf_win.bottom_offset);
-        sps->pic_conf_win.bottom_offset = sps->pic_conf_win.bottom_offset * 2;
-#if 0
-        if (s->h265dctx->flags2 & CODEC_FLAG2_IGNORE_CROP) {
-            h265d_dbg(H265D_DBG_SPS,
-                      "discarding sps conformance window, "
-                      "original values are l:%u r:%u t:%u b:%u\n",
-                      sps->pic_conf_win.left_offset,
-                      sps->pic_conf_win.right_offset,
-                      sps->pic_conf_win.top_offset,
-                      sps->pic_conf_win.bottom_offset);
-
-            sps->pic_conf_win.left_offset   =
-                sps->pic_conf_win.right_offset  =
-                    sps->pic_conf_win.top_offset    =
-                        sps->pic_conf_win.bottom_offset = 0;
+        if (sps->chroma_format_idc == H265_CHROMA_420) {
+            sps->pic_conf_win.left_offset   *= 2;
+            sps->pic_conf_win.right_offset  *= 2;
+            sps->pic_conf_win.top_offset    *= 2;
+            sps->pic_conf_win.bottom_offset *= 2;
+        } else if (sps->chroma_format_idc == H265_CHROMA_422) {
+            sps->pic_conf_win.left_offset   *= 2;
+            sps->pic_conf_win.right_offset  *= 2;
         }
-
-#endif
         sps->output_window = sps->pic_conf_win;
     }
 
@@ -1507,7 +1505,11 @@ RK_S32 mpp_hevc_decode_nal_sps(HEVCContext *s)
         goto err;
     }
 
-    if (sps->chroma_format_idc == 1) {
+    switch (sps->chroma_format_idc) {
+    case H265_CHROMA_400 : {
+        sps->pix_fmt = MPP_FMT_YUV400;
+    } break;
+    case H265_CHROMA_420 : {
         switch (sps->bit_depth) {
         case 8:  sps->pix_fmt = MPP_FMT_YUV420SP;   break;
         case 10: sps->pix_fmt = MPP_FMT_YUV420SP_10BIT; break;
@@ -1517,21 +1519,25 @@ RK_S32 mpp_hevc_decode_nal_sps(HEVCContext *s)
             ret =  MPP_ERR_PROTOL;
             goto err;
         }
-    } else {
-        mpp_err(
-            "non-4:2:0 support is currently unspecified.\n");
-        return  MPP_ERR_PROTOL;
-    }
-#if 0
-    desc = av_pix_fmt_desc_get(sps->pix_fmt);
-    if (!desc) {
-        goto err;
+    } break;
+    case H265_CHROMA_422 : {
+        switch (sps->bit_depth) {
+        case 8:  sps->pix_fmt = MPP_FMT_YUV422SP;   break;
+        case 10: sps->pix_fmt = MPP_FMT_YUV422SP_10BIT; break;
+        default:
+            mpp_err( "Unsupported bit depth: %d\n",
+                     sps->bit_depth);
+            ret =  MPP_ERR_PROTOL;
+            goto err;
+        }
+        mpp_slots_set_prop(s->slots, SLOTS_LEN_ALIGN, rkv_len_align_422);
+    } break;
+    case H265_CHROMA_444 : {
+        sps->pix_fmt = MPP_FMT_YUV444SP;
+        mpp_slots_set_prop(s->slots, SLOTS_LEN_ALIGN, rkv_len_align_444);
+    } break;
     }
 
-    sps->hshift[0] = sps->vshift[0] = 0;
-    sps->hshift[2] = sps->hshift[1] = desc->log2_chroma_w;
-    sps->vshift[2] = sps->vshift[1] = desc->log2_chroma_h;
-#endif
     sps->pixel_shift = sps->bit_depth > 8;
 
     READ_UE(gb, &sps->log2_max_poc_lsb);
@@ -1577,8 +1583,16 @@ RK_S32 mpp_hevc_decode_nal_sps(HEVCContext *s)
         }
     }
 
-    if ((s->picture_struct == MPP_PICTURE_STRUCTURE_TOP_FIELD) ||
-        (s->picture_struct == MPP_PICTURE_STRUCTURE_BOTTOM_FIELD)) {
+    /* According to T-REC-H.265 Chapter 7.4.4:
+     * If general_progressive_source_flag is equal to 0 and general_interlaced_source_flag is equal to 1, the
+     * source scan type of the pictures in the CVS should be interpreted as interlaced only.
+     * But the actual scan type is depending on encoder's behavior and out of this specification.
+     */
+    h265d_dbg(H265D_DBG_SPS, "sps progressive: %d, interlaced: %d\n",
+              sps->ptl.general_ptl.progressive_source_flag,
+              sps->ptl.general_ptl.interlaced_source_flag);
+    if (!sps->ptl.general_ptl.progressive_source_flag &&
+        sps->ptl.general_ptl.interlaced_source_flag) {
         for (i = 0; i < sps->max_sub_layers; i++) {
             sps->temporal_layer[i].num_reorder_pics += 2;
         }
@@ -1726,7 +1740,32 @@ RK_S32 mpp_hevc_decode_nal_sps(HEVCContext *s)
     }
 #endif
 
-    //  SKIP_BITS(gb, 1); // sps_extension_flag
+    READ_ONEBIT(gb, &sps->sps_extension_flag);
+    if (sps->sps_extension_flag) { // sps_extension_flag
+        READ_ONEBIT(gb, &sps->sps_range_extension_flag);
+        SKIP_BITS(gb, 7); //sps_extension_7bits = get_bits(gb, 7);
+        if (sps->sps_range_extension_flag) {
+            READ_ONEBIT(gb, &sps->transform_skip_rotation_enabled_flag);
+            READ_ONEBIT(gb, &sps->transform_skip_context_enabled_flag);
+            READ_ONEBIT(gb, &sps->implicit_rdpcm_enabled_flag);
+            READ_ONEBIT(gb, &sps->explicit_rdpcm_enabled_flag);
+
+            READ_ONEBIT(gb, &sps->extended_precision_processing_flag);
+            if (sps->extended_precision_processing_flag)
+                mpp_log("extended_precision_processing_flag not yet implemented\n");
+
+            READ_ONEBIT(gb, &sps->intra_smoothing_disabled_flag);
+            READ_ONEBIT(gb, &sps->high_precision_offsets_enabled_flag);
+            if (sps->high_precision_offsets_enabled_flag)
+                mpp_log("high_precision_offsets_enabled_flag not yet implemented\n");
+
+            READ_ONEBIT(gb, &sps->persistent_rice_adaptation_enabled_flag);
+
+            READ_ONEBIT(gb, &sps->cabac_bypass_alignment_enabled_flag);
+            if (sps->cabac_bypass_alignment_enabled_flag)
+                mpp_log("cabac_bypass_alignment_enabled_flag not yet implemented\n");
+        }
+    }
 
     if (s->apply_defdispwin) {
         sps->output_window.left_offset   += sps->vui.def_disp_win.left_offset;
@@ -1830,20 +1869,11 @@ RK_S32 mpp_hevc_decode_nal_sps(HEVCContext *s)
         }
         mpp_log("compare sps ok");
     }
-#if 0
-    if (s->h265dctx->debug & FF_DEBUG_BITSTREAM) {
-        h265d_dbg(H265D_DBG_SPS,
-                  "Parsed SPS: id %d; coded wxh: %dx%d; "
-                  "cropped wxh: %dx%d; pix_fmt: %s.\n",
-                  sps_id, sps->width, sps->height,
-                  sps->output_width, sps->output_height,
-                  av_get_pix_fmt_name(sps->pix_fmt));
-    }
-#endif
+
     /* check if this is a repeat of an already parsed SPS, then keep the
      * original one.
-     * otherwise drop all PPSes that depend on it */
-
+     * otherwise drop all PPSes that depend on it
+     */
     if (s->sps_list[sps_id] &&
         !memcmp(s->sps_list[sps_id], sps_buf, sizeof(HEVCSPS))) {
         mpp_mem_pool_put(s->sps_pool, sps_buf);
@@ -1857,7 +1887,7 @@ RK_S32 mpp_hevc_decode_nal_sps(HEVCContext *s)
         if (s->sps_list[sps_id] != NULL)
             mpp_mem_pool_put(s->sps_pool, s->sps_list[sps_id]);
         s->sps_list[sps_id] = sps_buf;
-        s->ps_need_upate = 1;
+        s->sps_need_upate = 1;
     }
 
     if (s->sps_list[sps_id])
@@ -1865,6 +1895,7 @@ RK_S32 mpp_hevc_decode_nal_sps(HEVCContext *s)
 
     return 0;
 __BITREAD_ERR:
+    ret = MPP_ERR_STREAM;
 err:
     mpp_mem_pool_put(s->sps_pool, sps_buf);
     return ret;
@@ -2193,6 +2224,7 @@ int mpp_hevc_decode_nal_pps(HEVCContext *s)
 
     return 0;
 __BITREAD_ERR:
+    ret = MPP_ERR_STREAM;
 err:
     if (pps)
         mpp_hevc_pps_free((RK_U8 *)pps);
diff --git a/mpp/codec/dec/h265/h265d_refs.c b/mpp/codec/dec/h265/h265d_refs.c
index e78e9e451..394911f83 100644
--- a/mpp/codec/dec/h265/h265d_refs.c
+++ b/mpp/codec/dec/h265/h265d_refs.c
@@ -83,6 +83,8 @@ static HEVCFrame *alloc_frame(HEVCContext *s)
 {
     RK_U32  i;
     MPP_RET ret = MPP_OK;
+    MppFrameFormat fmt = s->h265dctx->cfg->base.out_fmt & (~MPP_FRAME_FMT_MASK);
+
     for (i = 0; i < MPP_ARRAY_ELEMS(s->DPB); i++) {
         HEVCFrame *frame = &s->DPB[i];
         if (frame->slot_index != 0xff) {
@@ -95,9 +97,11 @@ static HEVCFrame *alloc_frame(HEVCContext *s)
         mpp_frame_set_hor_stride(frame->frame,
                                  (MPP_ALIGN(s->h265dctx->coded_width, 64) * s->h265dctx->nBitDepth) >> 3);
         mpp_frame_set_ver_stride(frame->frame, s->h265dctx->coded_height);
+        s->h265dctx->pix_fmt &= MPP_FRAME_FMT_MASK;
         if (s->is_hdr) {
             s->h265dctx->pix_fmt |= MPP_FRAME_HDR;
         }
+        s->h265dctx->pix_fmt |= fmt;
         mpp_frame_set_fmt(frame->frame, s->h265dctx->pix_fmt);
 
         if (MPP_FRAME_FMT_IS_FBC(s->h265dctx->pix_fmt)) {
@@ -114,6 +118,8 @@ static HEVCFrame *alloc_frame(HEVCContext *s)
                 fbc_hdr_stride = MPP_ALIGN(s->h265dctx->width, 256) | 256;
 
             mpp_frame_set_fbc_hdr_stride(frame->frame, fbc_hdr_stride);
+        } else if (MPP_FRAME_FMT_IS_TILE(s->h265dctx->pix_fmt)) {
+            /* nothing todo */
         } else {
             if ((s->h265dctx->cfg->base.enable_vproc & MPP_VPROC_MODE_DETECTION) &&
                 s->h265dctx->width <= 1920 &&  s->h265dctx->height <= 1088)
@@ -121,7 +127,7 @@ static HEVCFrame *alloc_frame(HEVCContext *s)
         }
 
         if (s->h265dctx->cfg->base.enable_thumbnail && s->h265dctx->hw_info->cap_down_scale)
-            mpp_frame_set_thumbnail_en(frame->frame, 1);
+            mpp_frame_set_thumbnail_en(frame->frame, s->h265dctx->cfg->base.enable_thumbnail);
         else
             mpp_frame_set_thumbnail_en(frame->frame, 0);
 
diff --git a/mpp/codec/dec/h265/h265d_sei.c b/mpp/codec/dec/h265/h265d_sei.c
index d7009ca71..45a9a1c43 100644
--- a/mpp/codec/dec/h265/h265d_sei.c
+++ b/mpp/codec/dec/h265/h265d_sei.c
@@ -422,15 +422,33 @@ MPP_RET mpp_hevc_decode_nal_sei(HEVCContext *s)
         payload_size = 0;
         byte = 0xFF;
         while (byte == 0xFF) {
+            if (gb->bytes_left_ < 2 || payload_type > INT_MAX - 255) {
+                mpp_err("parse payload_type error: byte_left %d payload_type %d\n",
+                        gb->bytes_left_, payload_type);
+                return MPP_ERR_STREAM;
+            }
+
             READ_BITS(gb, 8, &byte);
             payload_type += byte;
         }
         byte = 0xFF;
         while (byte == 0xFF) {
+            if ((RK_S32)gb->bytes_left_ < payload_size + 1) {
+                mpp_err("parse payload_size error: byte_left %d payload_size %d\n",
+                        gb->bytes_left_, payload_size + 1);
+                return MPP_ERR_STREAM;
+            }
+
             READ_BITS(gb, 8, &byte);
             payload_size += byte;
         }
 
+        if ((RK_S32)gb->bytes_left_ < payload_size) {
+            mpp_err("parse payload_size error: byte_left %d payload_size %d\n",
+                    gb->bytes_left_, payload_size);
+            return MPP_ERR_STREAM;
+        }
+
         memset(&payload_bitctx, 0, sizeof(payload_bitctx));
         mpp_set_bitread_ctx(&payload_bitctx, s->HEVClc->gb.data_, payload_size);
         mpp_set_bitread_pseudo_code_type(&payload_bitctx, PSEUDO_CODE_H264_H265_SEI);
diff --git a/mpp/codec/dec/jpeg/jpegd_parser.c b/mpp/codec/dec/jpeg/jpegd_parser.c
index 68d3bd31b..5461d8a9d 100644
--- a/mpp/codec/dec/jpeg/jpegd_parser.c
+++ b/mpp/codec/dec/jpeg/jpegd_parser.c
@@ -150,11 +150,6 @@ static MPP_RET jpeg_judge_yuv_mode(JpegdCtx *ctx)
         if (s->h_count[0] == s->v_count[0] && s->h_count[0] != 0) {
             s->yuv_mode = JPEGDEC_YUV400;
             s->output_fmt = MPP_FMT_YUV400;
-            if (s->output_fmt != ctx->output_fmt) {
-                mpp_err_f("unsupported upsampling(%d*%d)\n", s->output_fmt,
-                          ctx->output_fmt);
-                ret = MPP_ERR_STREAM;
-            }
             /* check if fill needed */
             if ((s->width & 0xf) && ((s->width & 0xf) <= 8)) {
                 s->fill_right = 1;
@@ -1179,7 +1174,6 @@ static MPP_RET jpegd_deinit(void *ctx)
         JpegCtx->syntax = NULL;
     }
 
-    JpegCtx->output_fmt = MPP_FMT_YUV420SP;
     JpegCtx->pts = 0;
     JpegCtx->eos = 0;
     JpegCtx->input_jpeg_count = 0;
@@ -1255,7 +1249,6 @@ static MPP_RET jpegd_init(void *ctx, ParserCfg *parser_cfg)
     }
     memset(JpegCtx->syntax, 0, sizeof(JpegdSyntax));
 
-    JpegCtx->output_fmt = MPP_FMT_YUV420SP;
     JpegCtx->pts = 0;
     JpegCtx->eos = 0;
     JpegCtx->input_jpeg_count = 0;
@@ -1288,20 +1281,9 @@ static MPP_RET jpegd_control(void *ctx, MpiCmd cmd, void *param)
 {
     jpegd_dbg_func("enter\n");
     MPP_RET ret = MPP_OK;
-    JpegdCtx *JpegCtx = (JpegdCtx *)ctx;
-    if (NULL == JpegCtx) {
-        mpp_err_f("NULL pointer");
-        return MPP_ERR_NULL_PTR;
-    }
-
-    switch (cmd) {
-    case MPP_DEC_SET_OUTPUT_FORMAT: {
-        JpegCtx->output_fmt = *((RK_U32 *)param);
-        jpegd_dbg_parser("output_format:%d\n", JpegCtx->output_fmt);
-    } break;
-    default :
-        ret = MPP_NOK;
-    }
+    (void) ctx;
+    (void) cmd;
+    (void) param;
     jpegd_dbg_func("exit\n");
     return ret;
 }
diff --git a/mpp/codec/dec/jpeg/jpegd_parser.h b/mpp/codec/dec/jpeg/jpegd_parser.h
index 72f20f593..72c20f8c7 100644
--- a/mpp/codec/dec/jpeg/jpegd_parser.h
+++ b/mpp/codec/dec/jpeg/jpegd_parser.h
@@ -125,7 +125,6 @@ typedef struct JpegdCtx {
 
     /* input stream buffer size */
     RK_U32                   bufferSize;
-    MppFrameFormat           output_fmt;
 
     MppPacket                input_packet;
     MppFrame                 output_frame;
diff --git a/mpp/codec/dec/m2v/m2vd_parser.c b/mpp/codec/dec/m2v/m2vd_parser.c
index 95b3cdbbb..c11e28f5d 100644
--- a/mpp/codec/dec/m2v/m2vd_parser.c
+++ b/mpp/codec/dec/m2v/m2vd_parser.c
@@ -155,6 +155,7 @@ static MPP_RET m2vd_parser_init_ctx(M2VDParserContext *ctx, ParserCfg *cfg)
     mpp_buf_slot_setup(ctx->frame_slots, 16);
 
     ctx->initFlag = 0;
+    ctx->info_changed = 0;
 
     /* copy from mpeg2decoder::mpeg2decoder */
     memset(&ctx->Framehead, 0, 3 * sizeof(M2VDFrameHead));
@@ -954,10 +955,23 @@ static int m2vd_decode_seq_header(M2VDParserContext *ctx)
     RK_U32 i;
     RK_S32 pre_frame_rate_code = ctx->seq_head.frame_rate_code;
     BitReadCtx_t *bx = ctx->bitread_ctx;
-    ctx->seq_head.decode_width = m2vd_read_bits(bx, 12);
-    ctx->seq_head.decode_height = m2vd_read_bits(bx, 12);
-    ctx->display_width = ctx->seq_head.decode_width;
-    ctx->display_height = ctx->seq_head.decode_height;
+    RK_U32 width = m2vd_read_bits(bx, 12);
+    RK_U32 height = m2vd_read_bits(bx, 12);
+
+    ctx->display_width = width;
+    ctx->display_height = height;
+
+    height = MPP_ALIGN(height, 16);
+    width = MPP_ALIGN(width, 16);
+
+    if (ctx->seq_head.decode_width && ctx->seq_head.decode_height) {
+        if (width != ctx->seq_head.decode_width ||
+            height != ctx->seq_head.decode_height)
+            ctx->info_changed = 1;
+    }
+
+    ctx->seq_head.decode_width = width;
+    ctx->seq_head.decode_height = height;
     ctx->seq_head.aspect_ratio_information = m2vd_read_bits(bx, 4);
     ctx->seq_head.frame_rate_code = m2vd_read_bits(bx, 4);
     if (!ctx->frame_period || pre_frame_rate_code != ctx->seq_head.frame_rate_code)
@@ -1098,7 +1112,14 @@ static MPP_RET m2v_update_ref_frame(M2VDParserContext *p, RK_S32 force)
                     mpp_buf_slot_enqueue(p->frame_slots, p->frame_ref0->slot_index, QUEUE_DISPLAY);
                     p->frame_ref0->flags = 0;
                 }
+
+                if (p->info_changed) {
+                    mpp_buf_slot_clr_flag(p->frame_slots, p->frame_ref0->slot_index, SLOT_CODEC_USE);
+                    p->frame_ref0->slot_index = -1;
+                    p->info_changed = 0;
+                }
             }
+
             if (p->frame_ref1->slot_index >= 0) {
                 mpp_buf_slot_clr_flag(p->frame_slots, p->frame_ref1->slot_index, SLOT_CODEC_USE);
                 p->frame_ref1->slot_index = -1;
@@ -1213,7 +1234,7 @@ static MPP_RET m2vd_alloc_frame(M2VDParserContext *ctx)
             }
 
             ctx->group_start_time_27M = pts_27M - pic_head->temporal_reference * ctx->frame_period;
-            if (ctx->group_start_time_27M < 0)
+            if (ctx->group_start_time_27M <= -ctx->frame_period)
                 ctx->group_start_time_27M = 0;
             ctx->pre_pts_27M = pts_27M;
             ctx->prechange_temporal_ref = pic_head->temporal_reference;
@@ -1259,8 +1280,6 @@ static MPP_RET m2vd_alloc_frame(M2VDParserContext *ctx)
         pic_head->pre_temporal_reference = pic_head->temporal_reference;
         pic_head->pre_picture_coding_type = pic_head->picture_coding_type;
         ctx->frame_cur->picCodingType = pic_head->picture_coding_type;
-        ctx->seq_head.decode_height = (ctx->seq_head.decode_height + 15) & (~15);
-        ctx->seq_head.decode_width = (ctx->seq_head.decode_width + 15) & (~15);
 
         mpp_frame_set_width(ctx->frame_cur->f, ctx->display_width);
         mpp_frame_set_height(ctx->frame_cur->f, ctx->display_height);
diff --git a/mpp/codec/dec/m2v/m2vd_parser.h b/mpp/codec/dec/m2v/m2vd_parser.h
index 08be2d061..9b983e87e 100644
--- a/mpp/codec/dec/m2v/m2vd_parser.h
+++ b/mpp/codec/dec/m2v/m2vd_parser.h
@@ -244,6 +244,7 @@ typedef struct M2VDParserContext_t {
     RK_U32          mb_height;
     RK_U32          MPEG2_Flag;
 
+    RK_U32          info_changed;
     M2VDHeadSeq         seq_head;
     M2VDHeadSeqExt      seq_ext_head;
     M2VDHeadGop         gop_head;
diff --git a/mpp/codec/dec/vp9/vp9d_parser.c b/mpp/codec/dec/vp9/vp9d_parser.c
index 3254a4b1c..baa8a8955 100644
--- a/mpp/codec/dec/vp9/vp9d_parser.c
+++ b/mpp/codec/dec/vp9/vp9d_parser.c
@@ -43,7 +43,6 @@ static   RK_U32 av_clip_uintp2(RK_S32 a, RK_S32 p)
     else                   return  a;
 }
 
-
 RK_U32 vp9d_debug = 0;
 
 #define VP9_SYNCCODE 0x498342
@@ -408,13 +407,19 @@ static RK_S32 vp9_alloc_frame(Vp9CodecContext *ctx, VP9Frame *frame)
 
         mpp_frame_set_fbc_hdr_stride(frame->f, fbc_hdr_stride);
     } else {
-        mpp_slots_set_prop(s->slots, SLOTS_HOR_ALIGN, mpp_align_256_odd);
+        if (mpp_get_soc_type() == ROCKCHIP_SOC_RK3576)
+            mpp_slots_set_prop(s->slots, SLOTS_HOR_ALIGN, mpp_align_128_odd_plus_64);
+        else
+            mpp_slots_set_prop(s->slots, SLOTS_HOR_ALIGN, mpp_align_256_odd);
         mpp_slots_set_prop(s->slots, SLOTS_VER_ALIGN, mpp_align_64);
-        mpp_frame_set_fmt(frame->f, ctx->pix_fmt);
+        if (MPP_FRAME_FMT_IS_TILE(s->cfg->base.out_fmt))
+            mpp_frame_set_fmt(frame->f, ctx->pix_fmt | ((s->cfg->base.out_fmt & (MPP_FRAME_TILE_FLAG))));
+        else
+            mpp_frame_set_fmt(frame->f, ctx->pix_fmt);
     }
 
     if (s->cfg->base.enable_thumbnail && s->hw_info->cap_down_scale)
-        mpp_frame_set_thumbnail_en(frame->f, 1);
+        mpp_frame_set_thumbnail_en(frame->f, s->cfg->base.enable_thumbnail);
     else
         mpp_frame_set_thumbnail_en(frame->f, 0);
 
@@ -630,6 +635,7 @@ static RK_S32 decode_parser_header(Vp9CodecContext *ctx,
     RK_S32 fmt = ctx->pix_fmt;
     RK_S32 last_invisible;
     const RK_U8 *data2;
+
 #ifdef dump
     char filename[20] = "data/acoef";
     if (vp9_p_fp2 != NULL) {
@@ -646,21 +652,26 @@ static RK_S32 decode_parser_header(Vp9CodecContext *ctx,
         mpp_err("Invalid frame marker\n");
         return MPP_ERR_STREAM;
     }
+
     ctx->profile  = mpp_get_bit1(&s->gb);
     ctx->profile |= mpp_get_bit1(&s->gb) << 1;
+
     if (ctx->profile == 3) ctx->profile += mpp_get_bit1(&s->gb);
     if (ctx->profile > 3) {
         mpp_err("Profile %d is not yet supported\n", ctx->profile);
         return MPP_ERR_STREAM;
     }
+
     vp9d_dbg(VP9D_DBG_HEADER, "profile %d", ctx->profile);
     s->show_existing_frame = mpp_get_bit1(&s->gb);
     vp9d_dbg(VP9D_DBG_HEADER, "show_existing_frame %d", s->show_existing_frame);
+
     if (s->show_existing_frame) {
         *refo = mpp_get_bits(&s->gb, 3);
         vp9d_dbg(VP9D_DBG_HEADER, "frame_to_show %d", *refo);
         return 0;
     }
+
     s->last_keyframe  = s->keyframe;
     s->keyframe       = !mpp_get_bit1(&s->gb);
     vp9d_dbg(VP9D_DBG_HEADER, "frame_type %d", s->keyframe);
@@ -673,10 +684,18 @@ static RK_S32 decode_parser_header(Vp9CodecContext *ctx,
     s->got_keyframes += s->keyframe ? 1 : 0;
     vp9d_dbg(VP9D_DBG_HEADER, "keyframe=%d, intraonly=%d, got_keyframes=%d\n",
              s->keyframe, s->intraonly, s->got_keyframes);
+
     if (!s->got_keyframes) {
         mpp_err_f("have not got keyframe.\n");
         return MPP_ERR_STREAM;
     }
+
+    /* set mvscale=16 default */
+    for (i = 0; i < 3; i++) {
+        s->mvscale[i][0] = 16;
+        s->mvscale[i][1] = 16;
+    }
+
     if (s->keyframe) {
         if (mpp_get_bits(&s->gb, 24) != VP9_SYNCCODE) { // synccode
             mpp_err("Invalid sync code\n");
@@ -1072,8 +1091,10 @@ static RK_S32 decode_parser_header(Vp9CodecContext *ctx,
     // next 16 bits is size of the rest of the header (arith-coded)
     size2 = mpp_get_bits(&s->gb, 16);
     vp9d_dbg(VP9D_DBG_HEADER, "first_partition_size %d", size2);
+    s->first_partition_size = size2;
     data2 = mpp_align_get_bits(&s->gb);
     vp9d_dbg(VP9D_DBG_HEADER, "offset %d", data2 - data);
+    s->uncompress_head_size_in_byte = data2 - data;
     if (size2 > size - (data2 - data)) {
         mpp_err("Invalid compressed header size\n");
         return MPP_ERR_STREAM;
diff --git a/mpp/codec/dec/vp9/vp9d_parser.h b/mpp/codec/dec/vp9/vp9d_parser.h
index 945227b02..18080e193 100644
--- a/mpp/codec/dec/vp9/vp9d_parser.h
+++ b/mpp/codec/dec/vp9/vp9d_parser.h
@@ -251,6 +251,7 @@ typedef struct VP9Context {
     RK_U16 mvscale[3][2];
     RK_U8 mvstep[3][2];
 
+    RK_U32 uncompress_head_size_in_byte;
     RK_S32 first_partition_size;
     MppBufSlots slots;
     MppBufSlots packet_slots;
diff --git a/mpp/codec/dec/vp9/vp9d_parser2_syntax.c b/mpp/codec/dec/vp9/vp9d_parser2_syntax.c
index 7028d0c8b..aababc619 100644
--- a/mpp/codec/dec/vp9/vp9d_parser2_syntax.c
+++ b/mpp/codec/dec/vp9/vp9d_parser2_syntax.c
@@ -131,6 +131,7 @@ static int vp9d_fill_picparams(Vp9CodecContext *ctx, DXVA_PicParams_VP9 *pic)
     pic->log2_tile_cols = s->tiling.log2_tile_cols;
     pic->log2_tile_rows = s->tiling.log2_tile_rows;
     pic->first_partition_size = s->first_partition_size;
+    pic->uncompressed_header_size_byte_aligned = s->uncompress_head_size_in_byte;
     memcpy(pic->mvscale, s->mvscale, sizeof(s->mvscale));
     memcpy(&pic->prob, &s->prob, sizeof(pic->prob));
     memcpy(&pic->prob_flag_delta, &s->prob_flag_delta, sizeof(pic->prob_flag_delta));
diff --git a/mpp/codec/enc/h264/h264e_api_v2.c b/mpp/codec/enc/h264/h264e_api_v2.c
index 84a07ec53..107b87bf5 100644
--- a/mpp/codec/enc/h264/h264e_api_v2.c
+++ b/mpp/codec/enc/h264/h264e_api_v2.c
@@ -48,6 +48,7 @@ typedef struct {
     MppEncCfgSet        *cfg;
     MppEncRefs          refs;
     RK_U32              idr_request;
+    RK_U32              pre_ref_idx;
 
     /* H.264 high level syntax */
     H264eSps            sps;
@@ -101,6 +102,9 @@ static void init_h264e_cfg_set(MppEncCfgSet *cfg, MppClientType type)
     memset(h264, 0, sizeof(*h264));
     h264->profile = H264_PROFILE_BASELINE;
     h264->level = H264_LEVEL_3_1;
+    cfg->tune.scene_mode = MPP_ENC_SCENE_MODE_DEFAULT;
+    cfg->tune.deblur_en = 0;
+    cfg->tune.vmaf_opt = 0;
 
     switch (type) {
     case VPU_CLIENT_VEPU1 :
@@ -110,6 +114,7 @@ static void init_h264e_cfg_set(MppEncCfgSet *cfg, MppClientType type)
         h264->log2_max_frame_num = 12;
         h264->hw_cfg.hw_poc_type = 2;
         h264->hw_cfg.hw_log2_max_frame_num_minus4 = 12;
+        h264->hw_cfg.hw_split_out = 0;
     } break;
     case VPU_CLIENT_RKVENC : {
         h264->poc_type = 0;
@@ -119,6 +124,7 @@ static void init_h264e_cfg_set(MppEncCfgSet *cfg, MppClientType type)
         h264->chroma_cr_qp_offset = -6;
         h264->hw_cfg.hw_poc_type = 0;
         h264->hw_cfg.hw_log2_max_frame_num_minus4 = 12;
+        h264->hw_cfg.hw_split_out = 0;
     } break;
     default : {
         h264->poc_type = 0;
@@ -126,6 +132,7 @@ static void init_h264e_cfg_set(MppEncCfgSet *cfg, MppClientType type)
         h264->log2_max_frame_num = 12;
         h264->hw_cfg.hw_poc_type = 0;
         h264->hw_cfg.hw_log2_max_frame_num_minus4 = 12;
+        h264->hw_cfg.hw_split_out = 0;
     } break;
     }
 
@@ -165,10 +172,10 @@ static void init_h264e_cfg_set(MppEncCfgSet *cfg, MppClientType type)
     rc_cfg->bps_min = rc_cfg->bps_target * 3 / 4;
     rc_cfg->fps_in_flex = 0;
     rc_cfg->fps_in_num = 30;
-    rc_cfg->fps_in_denorm = 1;
+    rc_cfg->fps_in_denom = 1;
     rc_cfg->fps_out_flex = 0;
     rc_cfg->fps_out_num = 30;
-    rc_cfg->fps_out_denorm = 1;
+    rc_cfg->fps_out_denom = 1;
     rc_cfg->gop = 60;
     rc_cfg->max_reenc_times = 1;
     rc_cfg->max_i_prop = 30;
@@ -185,6 +192,14 @@ static void init_h264e_cfg_set(MppEncCfgSet *cfg, MppClientType type)
     rc_cfg->fqp_min_p = INT_MAX;
     rc_cfg->fqp_max_i = INT_MAX;
     rc_cfg->fqp_max_p = INT_MAX;
+
+    cfg->tune.lambda_idx_i = 6;
+    cfg->tune.lambda_idx_p = 6;
+    cfg->tune.atl_str = 1;
+    cfg->tune.atr_str_i = 1;
+    cfg->tune.atr_str_p = 1;
+    cfg->tune.anti_flicker_str = 1;
+    cfg->tune.deblur_str = 3;
 }
 
 static void h264e_add_syntax(H264eCtx *ctx, H264eSyntaxType type, void *p)
@@ -340,7 +355,7 @@ static MPP_RET h264e_proc_prep_cfg(MppEncPrepCfg *dst, MppEncPrepCfg *src)
 
         if (MPP_FRAME_FMT_IS_FBC(dst->format) && (dst->mirroring || dst->rotation || dst->flip)) {
             // rk3588 rkvenc support fbc with rotation
-            if (!strstr(mpp_get_soc_name(), "rk3588")) {
+            if (mpp_get_soc_type() != ROCKCHIP_SOC_RK3588) {
                 mpp_err("invalid cfg fbc data no support mirror %d, rotation %d, or flip %d",
                         dst->mirroring, dst->rotation, dst->flip);
                 ret = MPP_ERR_VALUE;
@@ -759,7 +774,15 @@ static MPP_RET h264e_proc_dpb(void *ctx, HalEncTask *task)
     // update frame usage
     frms->seq_idx = curr->seq_idx;
     frms->curr_idx = curr->slot_idx;
-    frms->refr_idx = (refr) ? refr->slot_idx : curr->slot_idx;
+
+    if (refr) {
+        if (refr->status.force_pskip)
+            frms->refr_idx = p->pre_ref_idx;
+        else
+            frms->refr_idx = refr->slot_idx;
+    } else {
+        frms->refr_idx = curr->slot_idx;
+    }
 
     for (i = 0; i < (RK_S32)MPP_ARRAY_ELEMS(frms->usage); i++)
         frms->usage[i] = dpb->frames[i].on_used;
@@ -873,6 +896,7 @@ static MPP_RET h264e_sw_enc(void *ctx, HalEncTask *task)
 
     rc_info->bit_real = task->length;
     rc_info->quality_real = rc_info->quality_target;
+    p->pre_ref_idx = p->frms.refr_idx;
     mpp_packet_add_segment_info(packet, H264_NALU_TYPE_SLICE, length, final_len);
 
     return MPP_OK;
diff --git a/mpp/codec/enc/h264/h264e_pps.c b/mpp/codec/enc/h264/h264e_pps.c
index 492e08f55..cc9be5d50 100644
--- a/mpp/codec/enc/h264/h264e_pps.c
+++ b/mpp/codec/enc/h264/h264e_pps.c
@@ -22,25 +22,34 @@
 #include "h264e_debug.h"
 #include "h264e_pps.h"
 
-static void write_scaling_list(MppWriteCtx *bit, RK_S32 mode)
-{
-    switch (mode) {
-    case 0 : {
-        // flat scaling matrix
-        /* scaling_list_present_flag */
-        mpp_writer_put_bits(bit, 0, 1);
-    } break;
-    case 1 : {
-        /* scaling_list_present_flag */
-        mpp_writer_put_bits(bit, 1, 1);
-        /* delta_scale */
-        mpp_writer_put_se(bit, -8);
-    } break;
-    default : {
-        mpp_err_f("unsupport scaling list mode %d\n", mode);
-    } break;
-    }
-}
+static const uint8_t zigzag[64] = {
+    0,  8,  1,  2,  9, 16, 24, 17, 10,  3,  4, 11, 18, 25, 32, 40,
+    33, 26, 19, 12,  5,  6, 13, 20, 27, 34, 41, 48, 56, 49, 42, 35,
+    28, 21, 14,  7, 15, 22, 29, 36, 43, 50, 57, 58, 51, 44, 37, 30,
+    23, 31, 38, 45, 52, 59, 60, 53, 46, 39, 47, 54, 61, 62, 55, 63
+};
+
+static const uint8_t intra_scl[64] = {
+    10, 11, 14, 16, 17, 19, 21, 23,
+    11, 12, 16, 17, 19, 21, 23, 25,
+    14, 16, 17, 19, 21, 23, 25, 27,
+    16, 17, 19, 21, 23, 25, 27, 28,
+    17, 19, 21, 23, 25, 27, 28, 29,
+    19, 21, 23, 25, 27, 28, 29, 30,
+    21, 23, 25, 27, 28, 29, 30, 31,
+    23, 25, 27, 28, 29, 30, 31, 32,
+};
+
+static const uint8_t inter_scl[64] = {
+    12, 13, 15, 16, 17, 19, 20, 21,
+    13, 14, 16, 17, 19, 20, 21, 22,
+    15, 16, 17, 19, 20, 21, 22, 23,
+    16, 17, 19, 20, 21, 22, 23, 25,
+    17, 19, 20, 21, 22, 23, 25, 27,
+    19, 20, 21, 22, 23, 25, 27, 28,
+    20, 21, 22, 23, 25, 27, 28, 29,
+    21, 22, 23, 25, 27, 28, 29, 30,
+};
 
 MPP_RET h264e_pps_update(H264ePps *pps, MppEncCfgSet *cfg)
 {
@@ -91,6 +100,11 @@ MPP_RET h264e_pps_update(H264ePps *pps, MppEncCfgSet *cfg)
             mpp_log_f("warning: for profile %d transform_8x8_mode should be 0\n",
                       codec->profile);
         }
+        if (pps->pic_scaling_matrix_present) {
+            pps->pic_scaling_matrix_present = 0;
+            mpp_log_f("warning: for profile %d pic_scaling_matrix_present should be 0\n",
+                      codec->profile);
+        }
     } else {
         pps->second_chroma_qp_index_offset_present = 1;
         pps->second_chroma_qp_index_offset = codec->chroma_cr_qp_offset;
@@ -165,16 +179,39 @@ RK_S32 h264e_pps_to_packet(H264ePps *pps, MppPacket packet, RK_S32 *offset, RK_S
         /* transform_8x8_mode_flag */
         mpp_writer_put_bits(bit, pps->transform_8x8_mode, 1);
 
-        /* pic_scaling_matrix_present_flag */
-        mpp_writer_put_bits(bit, pps->pic_scaling_matrix_present, 1);
-        if (pps->pic_scaling_matrix_present) {
-            /* Only support default scaling list */
-            /* pic_scaling_list_present_flag[i] */
-            RK_S32 count = pps->transform_8x8_mode ? 8 : 6;
-            RK_S32 i;
-
-            for (i = 0; i < count; i++)
-                write_scaling_list(bit, pps->use_default_scaling_matrix[i]);
+        /* TODO: scaling_list_mode */
+        mpp_writer_put_bits(bit, pps->pic_scaling_matrix_present != 0, 1);
+        if (pps->pic_scaling_matrix_present)
+            mpp_writer_put_bits(bit, 0, 6);
+
+        if (1 == pps->pic_scaling_matrix_present)
+            mpp_writer_put_bits(bit, 0, 2); /* default scaling list */
+        else if (2 == pps->pic_scaling_matrix_present) {
+            /* user defined scaling list */
+            if (pps->transform_8x8_mode) {
+                RK_S32 run = 0;
+                RK_S32 len2 = 64;
+                RK_S32 j = 0;
+
+                mpp_writer_put_bits(bit, 1, 1);
+                for (run = len2; run > 1; run --)
+                    if (intra_scl[zigzag[run - 1]] != intra_scl[zigzag[run - 2]])
+                        break;
+                for (j = 0; j < run; j ++)
+                    mpp_writer_put_se(bit, (int8_t)(intra_scl[zigzag[j]] - (j > 0 ? intra_scl[zigzag[j - 1]] : 8)));
+                if (run < len2)
+                    mpp_writer_put_se(bit, (int8_t) - intra_scl[zigzag[run]]);
+
+                mpp_writer_put_bits(bit, 1, 1);
+                for (run = len2; run > 1; run --)
+                    if (inter_scl[zigzag[run - 1]] != inter_scl[zigzag[run - 2]])
+                        break;
+                for (j = 0; j < run; j ++)
+                    mpp_writer_put_se(bit, (int8_t)(inter_scl[zigzag[j]] - (j > 0 ? inter_scl[zigzag[j - 1]] : 8)));
+                if (run < len2)
+                    mpp_writer_put_se(bit, (int8_t) - inter_scl[zigzag[run]]);
+            } else
+                mpp_writer_put_bits(bit, 0, 2);
         }
 
         /* second_chroma_qp_index_offset */
diff --git a/mpp/codec/enc/h264/h264e_pps.h b/mpp/codec/enc/h264/h264e_pps.h
index c9e3fd52c..04b208979 100644
--- a/mpp/codec/enc/h264/h264e_pps.h
+++ b/mpp/codec/enc/h264/h264e_pps.h
@@ -52,7 +52,7 @@ typedef struct H264ePps_t {
     RK_S32      transform_8x8_mode;
 
     // Only support flat and default scaling list
-    RK_S32      pic_scaling_matrix_present;
+    RK_S32      pic_scaling_matrix_present; //TODO: replaced with scaling_list_mode
     RK_S32      use_default_scaling_matrix[H264_SCALING_MATRIX_TYPE_BUTT];
 } H264ePps;
 
diff --git a/mpp/codec/enc/h264/h264e_sps.c b/mpp/codec/enc/h264/h264e_sps.c
index ca68f85b4..f82bcf3e8 100644
--- a/mpp/codec/enc/h264/h264e_sps.c
+++ b/mpp/codec/enc/h264/h264e_sps.c
@@ -218,7 +218,7 @@ MPP_RET h264e_sps_update(H264eSps *sps, MppEncCfgSet *cfg)
     vui->vui_present = 1;
     vui->timing_info_present = 1;
     vui->time_scale = rc->fps_out_num * 2;
-    vui->num_units_in_tick = rc->fps_out_denorm;
+    vui->num_units_in_tick = rc->fps_out_denom;
     vui->fixed_frame_rate = !rc->fps_out_flex;
     vui->vidformat = MPP_FRAME_VIDEO_FMT_UNSPECIFIED;
 
@@ -242,8 +242,9 @@ MPP_RET h264e_sps_update(H264eSps *sps, MppEncCfgSet *cfg)
 
     vui->bitstream_restriction = 1;
     vui->motion_vectors_over_pic_boundaries = 1;
-    vui->log2_max_mv_length_horizontal = 16;
-    vui->log2_max_mv_length_vertical = 16;
+    /* the max and default value has been changed to 15 since the 2016 standard */
+    vui->log2_max_mv_length_horizontal = 15;
+    vui->log2_max_mv_length_vertical = 15;
     vui->max_dec_frame_buffering = info->dpb_size;
 
     return MPP_OK;
diff --git a/mpp/codec/enc/h265/h265e_api.c b/mpp/codec/enc/h265/h265e_api.c
index bf5d7954c..ce4096d2a 100644
--- a/mpp/codec/enc/h265/h265e_api.c
+++ b/mpp/codec/enc/h265/h265e_api.c
@@ -43,6 +43,7 @@ static MPP_RET h265e_init(void *ctx, EncImplCfg *ctrlCfg)
     MppEncRcCfg *rc_cfg = &ctrlCfg->cfg->rc;
     MppEncPrepCfg *prep = &ctrlCfg->cfg->prep;
     MppEncH265Cfg *h265 = NULL;
+    RockchipSocType soc_type;
 
     if (ctx == NULL) {
         mpp_err_f("invalid NULL ctx\n");
@@ -87,16 +88,13 @@ static MPP_RET h265e_init(void *ctx, EncImplCfg *ctrlCfg)
     h265->level = 120;
     h265->const_intra_pred = 0;           /* constraint intra prediction flag */
 
-    if (mpp_get_soc_type() == ROCKCHIP_SOC_RK3528) {
-        h265->ctu_size = 32;
+    soc_type = mpp_get_soc_type();
+    if (soc_type == ROCKCHIP_SOC_RK3528 || soc_type == ROCKCHIP_SOC_RK3576)
         h265->max_cu_size = 32;
-        h265->tmvp_enable = 0;
-    } else {
-        h265->ctu_size = 64;
+    else
         h265->max_cu_size = 64;
-        h265->tmvp_enable = 1;
-    }
 
+    h265->tmvp_enable = 0;
     h265->amp_enable = 0;
     h265->sao_enable = 1;
 
@@ -112,6 +110,18 @@ static MPP_RET h265e_init(void *ctx, EncImplCfg *ctrlCfg)
     h265->merge_cfg.merge_left_flag = 1;
     h265->merge_cfg.merge_up_flag = 1;
     p->cfg->tune.scene_mode = MPP_ENC_SCENE_MODE_DEFAULT;
+    p->cfg->tune.lambda_idx_i = 2;
+    p->cfg->tune.lambda_idx_p = 4;
+    p->cfg->tune.anti_flicker_str = 2;
+    p->cfg->tune.atr_str_i = 3;
+    p->cfg->tune.atr_str_p = 0;
+    p->cfg->tune.atl_str = 1;
+    p->cfg->tune.sao_str_i = 0;
+    p->cfg->tune.sao_str_p = 1;
+    p->cfg->tune.deblur_str = 3;
+    p->cfg->tune.deblur_en = 0;
+    p->cfg->tune.rc_container = 0;
+    p->cfg->tune.vmaf_opt = 0;
 
     /*
      * default prep:
@@ -149,10 +159,10 @@ static MPP_RET h265e_init(void *ctx, EncImplCfg *ctrlCfg)
     rc_cfg->bps_min = rc_cfg->bps_target * 3 / 4;
     rc_cfg->fps_in_flex = 0;
     rc_cfg->fps_in_num = 30;
-    rc_cfg->fps_in_denorm = 1;
+    rc_cfg->fps_in_denom = 1;
     rc_cfg->fps_out_flex = 0;
     rc_cfg->fps_out_num = 30;
-    rc_cfg->fps_out_denorm = 1;
+    rc_cfg->fps_out_denom = 1;
     rc_cfg->gop = 60;
     rc_cfg->max_reenc_times = 1;
     rc_cfg->max_i_prop = 30;
@@ -169,7 +179,7 @@ static MPP_RET h265e_init(void *ctx, EncImplCfg *ctrlCfg)
     rc_cfg->fqp_min_p = INT_MAX;
     rc_cfg->fqp_max_i = INT_MAX;
     rc_cfg->fqp_max_p = INT_MAX;
-
+    rc_cfg->cu_qp_delta_depth = 0;
     INIT_LIST_HEAD(&p->rc_list);
 
     h265e_dbg_func("leave ctx %p\n", ctx);
@@ -226,10 +236,49 @@ static MPP_RET h265e_gen_hdr(void *ctx, MppPacket pkt)
 
 static MPP_RET h265e_start(void *ctx, HalEncTask *task)
 {
-    H265eCtx *p = (H265eCtx *)ctx;
-    (void) p;
     h265e_dbg_func("enter\n");
 
+    if (mpp_frame_has_meta(task->frame)) {
+        MppEncRefFrmUsrCfg *frm_cfg = task->frm_cfg;
+        EncRcForceCfg *rc_force = &task->rc_task->force;
+        MppMeta meta = mpp_frame_get_meta(task->frame);
+        RK_S32 force_lt_idx = -1;
+        RK_S32 force_use_lt_idx = -1;
+        RK_S32 force_frame_qp = -1;
+        RK_S32 base_layer_pid = -1;
+
+        mpp_meta_get_s32(meta, KEY_ENC_MARK_LTR, &force_lt_idx);
+        mpp_meta_get_s32(meta, KEY_ENC_USE_LTR, &force_use_lt_idx);
+        mpp_meta_get_s32(meta, KEY_ENC_FRAME_QP, &force_frame_qp);
+        mpp_meta_get_s32(meta, KEY_ENC_BASE_LAYER_PID, &base_layer_pid);
+
+        if (force_lt_idx >= 0) {
+            frm_cfg->force_flag |= ENC_FORCE_LT_REF_IDX;
+            frm_cfg->force_lt_idx = force_lt_idx;
+        }
+
+        if (force_use_lt_idx >= 0) {
+            frm_cfg->force_flag |= ENC_FORCE_REF_MODE;
+            frm_cfg->force_ref_mode = REF_TO_LT_REF_IDX;
+            frm_cfg->force_ref_arg = force_use_lt_idx;
+        }
+
+        if (force_frame_qp >= 0) {
+            rc_force->force_flag = ENC_RC_FORCE_QP;
+            rc_force->force_qp = force_frame_qp;
+        } else {
+            rc_force->force_flag &= (~ENC_RC_FORCE_QP);
+            rc_force->force_qp = -1;
+        }
+
+        if (base_layer_pid >= 0) {
+            H265eCtx *p = (H265eCtx *)ctx;
+            MppEncH265Cfg *h265 = &p->cfg->codec.h265;
+
+            h265->base_layer_pid = base_layer_pid;
+        }
+    }
+
     /*
      * Step 2: Fps conversion
      *
@@ -269,16 +318,36 @@ static MPP_RET h265e_proc_dpb(void *ctx, HalEncTask *task)
 static MPP_RET h265e_proc_hal(void *ctx, HalEncTask *task)
 {
     H265eCtx *p = (H265eCtx *)ctx;
-    EncFrmStatus *frm = &task->rc_task->frm;
-    MppPacket packet = task->packet;
-    MppMeta meta = mpp_packet_get_meta(packet);
+    MppEncH265Cfg *h265 = &p->cfg->codec.h265;
 
     if (ctx == NULL) {
         mpp_err_f("invalid NULL ctx\n");
         return MPP_ERR_NULL_PTR;
     }
 
-    mpp_meta_set_s32(meta, KEY_TEMPORAL_ID, frm->temporal_id);
+    /* check max temporal layer id */
+    {
+        MppEncCpbInfo *cpb_info = mpp_enc_ref_cfg_get_cpb_info(p->cfg->ref_cfg);
+        RK_S32 cpb_max_tid = cpb_info->max_st_tid;
+        RK_S32 cfg_max_tid = h265->max_tid;
+
+        if (cpb_max_tid != cfg_max_tid) {
+            mpp_log("max tid is update to match cpb %d -> %d\n",
+                    cfg_max_tid, cpb_max_tid);
+            h265->max_tid = cpb_max_tid;
+        }
+    }
+
+    if (h265->max_tid) {
+        EncFrmStatus *frm = &task->rc_task->frm;
+        MppPacket packet = task->packet;
+        MppMeta meta = mpp_packet_get_meta(packet);
+
+        mpp_meta_set_s32(meta, KEY_TEMPORAL_ID, frm->temporal_id);
+        if (!frm->is_non_ref && frm->is_lt_ref)
+            mpp_meta_set_s32(meta, KEY_LONG_REF_IDX, frm->lt_idx);
+    }
+
     h265e_dbg_func("enter ctx %p \n", ctx);
 
     h265e_syntax_fill(ctx);
@@ -295,6 +364,7 @@ static MPP_RET h265e_proc_enc_skip(void *ctx, HalEncTask *task)
 {
     H265eCtx *p = (H265eCtx *)ctx;
     MppPacket pkt = task->packet;
+    H265eSyntax_new *syntax = &p->syntax;
     RK_U8 *ptr = mpp_packet_get_pos(pkt);
     RK_U32 offset = mpp_packet_get_length(pkt);
     RK_U32 len    = mpp_packet_get_size(pkt) - offset;
@@ -306,6 +376,7 @@ static MPP_RET h265e_proc_enc_skip(void *ctx, HalEncTask *task)
     new_length = h265e_code_slice_skip_frame(ctx, p->slice, ptr, len);
     task->length = new_length;
     task->rc_task->info.bit_real = 8 * new_length;
+    syntax->pre_ref_idx = syntax->sp.recon_pic.slot_idx;
     mpp_packet_add_segment_info(pkt, NAL_TRAIL_R, offset, new_length);
 
     h265e_dbg_func("leave\n");
@@ -432,7 +503,7 @@ static MPP_RET h265e_proc_prep_cfg(MppEncPrepCfg *dst, MppEncPrepCfg *src)
 
     if (MPP_FRAME_FMT_IS_FBC(dst->format) && (dst->mirroring || dst->rotation || dst->flip)) {
         // rk3588 rkvenc support fbc with rotation
-        if (!strstr(mpp_get_soc_name(), "rk3588")) {
+        if (mpp_get_soc_type() != ROCKCHIP_SOC_RK3588) {
             mpp_err("invalid cfg fbc data no support mirror %d, rotation %d, or flip %d",
                     dst->mirroring, dst->rotation, dst->flip);
             ret = MPP_ERR_VALUE;
@@ -478,6 +549,7 @@ static MPP_RET h265e_proc_h265_cfg(MppEncH265Cfg *dst, MppEncH265Cfg *src)
         }
 
         dst->level = src->level;
+        dst->tier = (src->level >= 120) ? src->tier : 0;
     }
 
     if (change & MPP_ENC_H265_CFG_CU_CHANGE) {
@@ -527,6 +599,38 @@ static MPP_RET h265e_proc_h265_cfg(MppEncH265Cfg *dst, MppEncH265Cfg *src)
     if (change & MPP_ENC_H265_CFG_TILE_LPFACS_CHANGE)
         dst->lpf_acs_tile_disable = src->lpf_acs_tile_disable;
 
+    if ((change & MPP_ENC_H265_CFG_CHANGE_CONST_INTRA) &&
+        (dst->const_intra_pred != src->const_intra_pred)) {
+        RockchipSocType soc_type = mpp_get_soc_type();
+
+        if (soc_type != ROCKCHIP_SOC_RK3576 && src->const_intra_pred == 1) {
+            dst->const_intra_pred = 0;
+
+            mpp_log("warning: Only rk3576's HEVC encoder support constraint intra prediction flag = 1.");
+        } else
+            dst->const_intra_pred = src->const_intra_pred;
+
+        dst->change |= MPP_ENC_H265_CFG_CHANGE_CONST_INTRA;
+    }
+
+    if ((change & MPP_ENC_H265_CFG_CHANGE_MAX_LTR) &&
+        (dst->max_ltr_frames != src->max_ltr_frames)) {
+        dst->max_ltr_frames = src->max_ltr_frames;
+        dst->change |= MPP_ENC_H265_CFG_CHANGE_MAX_LTR;
+    }
+
+    if ((change & MPP_ENC_H265_CFG_CHANGE_MAX_TID) &&
+        (dst->max_tid != src->max_tid)) {
+        dst->max_tid = src->max_tid;
+        dst->change |= MPP_ENC_H265_CFG_CHANGE_MAX_TID;
+    }
+
+    if ((change & MPP_ENC_H265_CFG_CHANGE_BASE_LAYER_PID) &&
+        (dst->base_layer_pid != src->base_layer_pid)) {
+        dst->base_layer_pid = src->base_layer_pid;
+        dst->change |= MPP_ENC_H265_CFG_CHANGE_BASE_LAYER_PID;
+    }
+
     /*
      * NOTE: use OR here for avoiding overwrite on multiple config
      * When next encoding is trigger the change flag will be clear
diff --git a/mpp/codec/enc/h265/h265e_dpb.c b/mpp/codec/enc/h265/h265e_dpb.c
index 8e76285c0..5ab3abd66 100644
--- a/mpp/codec/enc/h265/h265e_dpb.c
+++ b/mpp/codec/enc/h265/h265e_dpb.c
@@ -24,6 +24,7 @@
 
 #include "h265e_codec.h"
 #include "h265e_dpb.h"
+#include "h265e_slice.h"
 
 void h265e_dpb_dump_frm(H265eDpb *dpb, const char *fmt)
 {
@@ -42,10 +43,42 @@ void h265e_dpb_dump_frm(H265eDpb *dpb, const char *fmt)
     mpp_log("%20s %s", fmt, buf);
 }
 
-void h265e_dpb_set_ref_list(H265eRpsList *RpsList, H265eReferencePictureSet *m_pRps, RK_S32 delta_poc)
+MPP_RET calc_ref_pic_set_idxl0(H265eDpb *dpb, H265eSlice *slice, RK_S32 ref_idx)
+{
+    H265eReferencePictureSet * rps = (H265eReferencePictureSet*)&slice->m_localRPS;
+    H265eDpbFrm *frame_list = dpb->frame_list;
+    H265eRpsList *RpsList = &dpb->RpsList;
+    RK_S32 poc_idx = rps->m_RealPoc[ref_idx];
+    H265eDpbFrm* refPicSetLtCurr[MAX_REFS];
+    H265eDpbFrm* refPic = NULL;
+    RK_S32 numPocLtCurr = 0;
+    RK_S32 i = 0;
+
+    for (i = rps->num_negative_pic + rps->num_positive_pic + rps->num_long_term_pic - 1;
+         i > rps->num_negative_pic + rps->num_positive_pic - 1; i--) {
+        if (rps->m_used[i]) {
+            refPic = get_lt_ref_pic(frame_list, slice, rps->m_RealPoc[i], rps->check_lt_msb[i]);
+            refPicSetLtCurr[numPocLtCurr] = refPic;
+            numPocLtCurr++;
+        }
+    }
+
+    RpsList->m_RefPicListModification->m_RefPicSetIdxL0[0] = ref_idx;
+    for (i = 0; i < numPocLtCurr; i++) {
+        if (poc_idx == refPicSetLtCurr[i]->poc)
+            RpsList->m_RefPicListModification->m_RefPicSetIdxL0[0] = rps->m_numberOfPictures - rps->num_long_term_pic + i;
+    }
+
+    return MPP_OK;
+}
+
+void h265e_dpb_set_ref_list(H265eDpb *dpb, H265eSlice *slice, RK_S32 delta_poc)
 {
     RK_S32 i;
     RK_S32 ref_idx = -1;
+    RK_S32 lt_cnt = 0, st_cnt = 0;
+    H265eRpsList *RpsList = &dpb->RpsList;
+    H265eReferencePictureSet * m_pRps = (H265eReferencePictureSet*)&slice->m_localRPS;
     H265eRefPicListModification* refPicListModification = RpsList->m_RefPicListModification;
 
     h265e_dbg_func("enter\n");
@@ -64,21 +97,19 @@ void h265e_dpb_set_ref_list(H265eRpsList *RpsList, H265eReferencePictureSet *m_p
             h265e_dbg_dpb("m_pRps->delta_poc[%d] = %d", i, m_pRps->delta_poc[i]);
             if (m_pRps->delta_poc[i] == delta_poc) {
                 ref_idx = i;
-                h265e_dbg_dpb("get ref ref_idx %d", ref_idx);
-                break;
+                if (i > m_pRps->m_numberOfPictures - m_pRps->num_long_term_pic - 1)
+                    lt_cnt++;
+                else
+                    st_cnt++;
+                h265e_dbg_dpb("get %s ref ref_idx %d delta_poc %d", st_cnt ? "st" : "lt", ref_idx, delta_poc);
             }
         }
-        if (-1 == ref_idx) {
-            mpp_err("Did not find the right reference picture");
+        if (lt_cnt != 1 && st_cnt == 0) {
+            mpp_err("Warning: Did not find the right long term reference picture or more than one.");
             return;
         } else if (ref_idx != 0) {
             refPicListModification->m_refPicListModificationFlagL0 = 1;
-            refPicListModification->m_RefPicSetIdxL0[0] = ref_idx;
-            for ( i = 1; i < m_pRps->m_numberOfPictures - 1; i++) {
-                if (i != ref_idx)
-                    refPicListModification->m_RefPicSetIdxL0[i] = i;
-            }
-            refPicListModification->m_RefPicSetIdxL0[ref_idx] = 0;
+            calc_ref_pic_set_idxl0(dpb, slice, ref_idx);
         }
     }
     refPicListModification->m_refPicListModificationFlagL1 = 0;
@@ -650,9 +681,12 @@ void h265e_dpb_cpb2rps(H265eDpb *dpb, RK_S32 curPoc, H265eSlice *slice, EncCpbSt
             rps->poc[i + st_size] = nLongTermRefPicPoc[i];
             rps->m_RealPoc[i + st_size] = nLongTermRefPicRealPoc[i];
             rps->m_used[i + st_size] = 1;
-            rps->m_ref[i + st_size] = p->is_long_term;
             rps->delta_poc[i + st_size] = nLongTermDealtPoc[i];
             rps->check_lt_msb[i + st_size] = isMsbValid[i];
+            if (cpb->refr.seq_idx == rps->poc[i + st_size])
+                rps->m_ref[i + st_size] = 1;
+            else
+                rps->m_ref[i + st_size] = 0;
         }
     }
 
@@ -663,7 +697,7 @@ void h265e_dpb_cpb2rps(H265eDpb *dpb, RK_S32 curPoc, H265eSlice *slice, EncCpbSt
     slice->m_rps = rps;
     h265e_dpb_apply_rps(dpb, slice->m_rps, curPoc);
     h265e_dpb_arrange_lt_rps(dpb, slice);
-    h265e_dpb_set_ref_list(RpsList, rps, ref_dealt_poc);
+    h265e_dpb_set_ref_list(dpb, slice, ref_dealt_poc);
     memcpy(&slice->m_RefPicListModification, RpsList->m_RefPicListModification,
            sizeof(H265eRefPicListModification));
     h265e_dbg_func("leave\n");
diff --git a/mpp/codec/enc/h265/h265e_header_gen.c b/mpp/codec/enc/h265/h265e_header_gen.c
index 41b71b402..9d05f248c 100644
--- a/mpp/codec/enc/h265/h265e_header_gen.c
+++ b/mpp/codec/enc/h265/h265e_header_gen.c
@@ -73,7 +73,7 @@ static void h265e_nal_encode(RK_U8 *dst, H265eNal *nal)
     mpp_writer_put_bits(&s, 0, 1); //forbidden_zero_bit
     mpp_writer_put_bits(&s, nal->i_type, 6);//nal_unit_type
     mpp_writer_put_bits(&s, 0, 6); //nuh_reserved_zero_6bits
-    mpp_writer_put_bits(&s, 1, 3); //nuh_temporal_id_plus1
+    mpp_writer_put_bits(&s, nal->temporal_id + 1, 3); //nuh_temporal_id_plus1
     dst += 2;
     dst = h265e_nal_escape_c(dst, src, end);
     size = (RK_S32)((dst - orig_dst) - 4);
@@ -494,12 +494,11 @@ static MPP_RET h265e_sps_write(H265eSps *sps, H265eStream *s)
     h265e_stream_write_ue_with_log(s, sps->m_quadtreeTUMaxDepthInter - 1,   "max_transform_hierarchy_depth_inter");
     h265e_stream_write_ue_with_log(s, sps->m_quadtreeTUMaxDepthIntra - 1,   "max_transform_hierarchy_depth_intra");
     h265e_stream_write1_with_log(s, sps->m_scalingListEnabledFlag ? 1 : 0,       "scaling_list_enabled_flag");
-    if (sps->m_scalingListEnabledFlag) {
-        h265e_stream_write1_with_log(s, sps->m_scalingListPresentFlag ? 1 : 0, "sps_scaling_list_data_present_flag");
-        if (sps->m_scalingListPresentFlag) {
-            mpp_log("to do m_scalingListPresentFlag");
-            ;//codeScalingList(m_slice->getScalingList()); //todo only support default
-        }
+    if (sps->m_scalingListEnabledFlag == 1)
+        h265e_stream_write1_with_log(s, 0, "sps_scaling_list_data_present_flag");
+    else if (sps->m_scalingListEnabledFlag == 2) {
+        //TODO:
+        mpp_err_f("m_scalingListEnabledFlag == 2 not supported yet\n");
     }
     h265e_stream_write1_with_log(s, sps->m_useAMP ? 1 : 0, "amp_enabled_flag");
     h265e_stream_write1_with_log(s, sps->m_bUseSAO ? 1 : 0, "sample_adaptive_offset_enabled_flag");
@@ -651,6 +650,8 @@ void h265e_nal_start(H265eExtraInfo *out, RK_S32 i_type,
     /* NOTE: consistent with stream_init */
     nal->p_payload = &s->buf[s->enc_stream.byte_cnt];
     nal->i_padding = 0;
+
+    nal->temporal_id = out->temporal_id;
 }
 
 void h265e_nal_end(H265eExtraInfo *out)
@@ -711,9 +712,9 @@ MPP_RET h265e_set_extra_info(H265eCtx *ctx)
 
     h265e_dbg_func("enter\n");
     info->nal_num = 0;
+    info->temporal_id = 0;
     h265e_stream_reset(&info->stream);
 
-
     h265e_nal_start(info, NAL_VPS, H265_NAL_PRIORITY_HIGHEST);
     h265e_set_vps(ctx, vps);
     h265e_vps_write(vps, &info->stream);
diff --git a/mpp/codec/enc/h265/h265e_header_gen.h b/mpp/codec/enc/h265/h265e_header_gen.h
index 57d779776..04431366b 100644
--- a/mpp/codec/enc/h265/h265e_header_gen.h
+++ b/mpp/codec/enc/h265/h265e_header_gen.h
@@ -72,6 +72,7 @@ typedef struct  H265eNal_t {
     /* Size of padding in bytes. */
     RK_S32 i_padding;
     RK_S32 sh_head_len;
+    RK_S32 temporal_id;
 } H265eNal;
 
 typedef struct H265eExtraInfo_t {
@@ -82,6 +83,7 @@ typedef struct H265eExtraInfo_t {
     RK_U32          sei_change_flg;
     H265eStream     stream;
 //    H265eSei        sei;
+    RK_S32          temporal_id;
 } H265eExtraInfo;
 
 #ifdef __cplusplus
diff --git a/mpp/codec/enc/h265/h265e_ps.c b/mpp/codec/enc/h265/h265e_ps.c
index 0e76e8d1a..aaec00733 100644
--- a/mpp/codec/enc/h265/h265e_ps.c
+++ b/mpp/codec/enc/h265/h265e_ps.c
@@ -23,6 +23,7 @@
 #include "mpp_common.h"
 
 #include "h265e_ps.h"
+#include "mpp_enc_ref.h"
 
 #define MAX_UINT        0xFFFFFFFFU
 
@@ -116,12 +117,14 @@ MPP_RET h265e_set_vps(H265eCtx *ctx, H265eVps *vps)
     MppEncH265Cfg *codec = &ctx->cfg->codec.h265;
     ProfileTierLevel *profileTierLevel = &vps->m_ptl.m_generalPTL;
     MppEncPrepCfg *prep = &ctx->cfg->prep;
+    MppEncRefCfg ref_cfg = ctx->cfg->ref_cfg;
     RK_U32 maxlumas = prep->width * prep->height;
     RK_S32 level_idc = H265_LEVEL_NONE;
+    MppEncRefCfgImpl *refs = (MppEncRefCfgImpl *)ref_cfg;
 
     vps->m_VPSId = 0;
-    vps->m_maxTLayers = 1;
-    vps->m_maxLayers = 1;
+    vps->m_maxTLayers = refs->max_tlayers ? refs->max_tlayers : 1;
+    vps->m_maxLayers = vps->m_maxTLayers;
     vps->m_bTemporalIdNestingFlag = 1;
     vps->m_numHrdParameters = 0;
     vps->m_maxNuhReservedZeroLayerId = 0;
@@ -183,7 +186,7 @@ MPP_RET h265e_set_sps(H265eCtx *ctx, H265eSps *sps, H265eVps *vps)
     MppEncRefCfg ref_cfg = ctx->cfg->ref_cfg;
     MppEncH265VuiCfg *vui = &codec->vui;
     MppFrameFormat fmt = prep->format;
-    RK_S32 i_timebase_num = rc->fps_out_denorm;
+    RK_S32 i_timebase_num = rc->fps_out_denom;
     RK_S32 i_timebase_den = rc->fps_out_num;
     RK_U8  convertToBit[MAX_CU_SIZE + 1];
     RK_U32 maxCUDepth, minCUDepth, addCUDepth;
@@ -205,6 +208,9 @@ MPP_RET h265e_set_sps(H265eCtx *ctx, H265eSps *sps, H265eVps *vps)
     minCUDepth = (codec->max_cu_size >> (maxCUDepth - 1));
 
     tuQTMaxLog2Size = convertToBit[codec->max_cu_size] + 2 - 1;
+    if (mpp_get_soc_type() == ROCKCHIP_SOC_RK3576) {
+        tuQTMaxLog2Size = tuQTMaxLog2Size + 1;
+    }
 
     addCUDepth = 0;
     while ((RK_U32)(codec->max_cu_size >> maxCUDepth) > (1u << (tuQTMinLog2Size + addCUDepth))) {
@@ -245,7 +251,7 @@ MPP_RET h265e_set_sps(H265eCtx *ctx, H265eSps *sps, H265eVps *vps)
     sps->m_SPSId = 0;
     sps->m_VPSId = 0;
     sps->m_chromaFormatIdc = (fmt == MPP_FMT_YUV400) ? H265_CHROMA_400 : H265_CHROMA_420;
-    sps->m_maxTLayers = 1;
+    sps->m_maxTLayers = vps->m_maxLayers;
     sps->m_picWidthInLumaSamples = prep->width + pad[0];
     sps->m_picHeightInLumaSamples = prep->height + pad[1];
     sps->m_log2MinCodingBlockSize = 0;
@@ -291,9 +297,6 @@ MPP_RET h265e_set_sps(H265eCtx *ctx, H265eSps *sps, H265eVps *vps)
     sps->m_qpBDOffsetC = 0;
 
     sps->m_bUseSAO = codec->sao_enable;
-
-    sps->m_maxTLayers = 1;
-
     sps->m_bTemporalIdNestingFlag = 1;
 
     for (i = 0; i < sps->m_maxTLayers; i++) {
@@ -321,6 +324,14 @@ MPP_RET h265e_set_sps(H265eCtx *ctx, H265eSps *sps, H265eVps *vps)
     } else if (cpb_info->max_st_tid) {
         sps->m_TMVPFlagsPresent = 0;
     }
+
+    if (rc->drop_mode == MPP_ENC_RC_DROP_FRM_PSKIP) {
+        codec->tmvp_enable = 0;
+        sps->m_TMVPFlagsPresent = 0;
+        codec->sao_enable = 0;
+        sps->m_bUseSAO = 0;
+    }
+
     sps->m_ptl = &vps->m_ptl;
     sps->m_vuiParametersPresentFlag = 1;
     if (sps->m_vuiParametersPresentFlag) {
@@ -390,16 +401,14 @@ MPP_RET h265e_set_pps(H265eCtx  *ctx, H265ePps *pps, H265eSps *sps)
 {
     MppEncH265Cfg *codec = &ctx->cfg->codec.h265;
     MppEncRcCfg *rc = &ctx->cfg->rc;
-    pps->m_bConstrainedIntraPred = 0;
+
+    pps->m_bConstrainedIntraPred = codec->const_intra_pred;
     pps->m_PPSId = 0;
     pps->m_SPSId = 0;
     pps->m_picInitQPMinus26 = 0;
-    pps->m_useDQP = 0;
-    if (rc->rc_mode != MPP_ENC_RC_MODE_FIXQP) {
-        pps->m_useDQP = 1;
-        pps->m_maxCuDQPDepth = 0;
-        pps->m_minCuDQPSize = (sps->m_maxCUSize >> pps->m_maxCuDQPDepth);
-    }
+    pps->m_useDQP = 1;
+    pps->m_maxCuDQPDepth = rc->cu_qp_delta_depth;
+    pps->m_minCuDQPSize = (sps->m_maxCUSize >> pps->m_maxCuDQPDepth);
 
     pps->m_sps = sps;
     pps->m_bSliceChromaQpFlag = 0;
@@ -424,7 +433,7 @@ MPP_RET h265e_set_pps(H265eCtx  *ctx, H265ePps *pps, H265eSps *sps)
         }
     } else {
         pps->m_deblockingFilterOverrideEnabledFlag = 0;
-        pps->m_picDisableDeblockingFilterFlag = 0;
+        pps->m_picDisableDeblockingFilterFlag = 1;
         pps->m_deblockingFilterBetaOffsetDiv2 = 0;
         pps->m_deblockingFilterTcOffsetDiv2 = 0;
     }
@@ -448,11 +457,16 @@ MPP_RET h265e_set_pps(H265eCtx  *ctx, H265ePps *pps, H265eSps *sps)
     pps->m_nNumTileColumnsMinus1 = 0;
     pps->m_loopFilterAcrossTilesEnabledFlag = !codec->lpf_acs_tile_disable;
     {
-        const char *soc_name = mpp_get_soc_name();
+        RockchipSocType soc_type = mpp_get_soc_type();
+        RK_S32 index;
+        RK_S32 mb_w = (sps->m_picWidthInLumaSamples + sps->m_maxCUSize - 1) / sps->m_maxCUSize;
+        RK_S32 mb_h = (sps->m_picHeightInLumaSamples + sps->m_maxCUSize - 1) / sps->m_maxCUSize;
+        RK_S32 tile_width;
+
         /* check tile support on rk3566 and rk3568 */
-        if (strstr(soc_name, "rk3566") || strstr(soc_name, "rk3568")) {
+        if (soc_type == ROCKCHIP_SOC_RK3566 || soc_type == ROCKCHIP_SOC_RK3568) {
             pps->m_nNumTileColumnsMinus1 = (sps->m_picWidthInLumaSamples - 1) / 1920 ;
-        } else if (strstr(soc_name, "rk3588")) {
+        } else if (soc_type == ROCKCHIP_SOC_RK3588) {
             if (sps->m_picWidthInLumaSamples > 8192) {
                 /* 4 tile for over 8k encoding */
                 pps->m_nNumTileColumnsMinus1 = 3;
@@ -467,7 +481,18 @@ MPP_RET h265e_set_pps(H265eCtx  *ctx, H265ePps *pps, H265eSps *sps)
         if (pps->m_nNumTileColumnsMinus1) {
             pps->m_tiles_enabled_flag = 1;
             pps->m_bTileUniformSpacing = 1;
-            pps->m_loopFilterAcrossTilesEnabledFlag = !codec->lpf_acs_tile_disable;;
+            pps->m_loopFilterAcrossTilesEnabledFlag = !codec->lpf_acs_tile_disable;
+
+            /* calc width per tile */
+            for (index = 0; index < pps->m_nNumTileColumnsMinus1; index++) {
+                tile_width = (index + 1) * mb_w / (pps->m_nNumTileColumnsMinus1 + 1) -
+                             index * mb_w / (pps->m_nNumTileColumnsMinus1 + 1);
+                pps->m_nTileColumnWidthArray[index] = tile_width;
+                pps->m_nTileRowHeightArray[index] = mb_h;
+            }
+            tile_width = mb_w - index * mb_w / (pps->m_nNumTileColumnsMinus1 + 1);
+            pps->m_nTileColumnWidthArray[index] = tile_width;
+            pps->m_nTileRowHeightArray[index] = mb_h;
         }
     }
 
diff --git a/mpp/codec/enc/h265/h265e_slice.c b/mpp/codec/enc/h265/h265e_slice.c
index acd3f1209..903be9a54 100644
--- a/mpp/codec/enc/h265/h265e_slice.c
+++ b/mpp/codec/enc/h265/h265e_slice.c
@@ -270,6 +270,7 @@ void h265e_slice_init(void *ctx, EncFrmStatus curr)
 
     slice->poc = p->dpb->curr->seq_idx;
     slice->gop_idx = p->dpb->gop_idx;
+    slice->temporal_id = p->dpb->curr->status.temporal_id;
     p->dpb->curr->gop_idx =  p->dpb->gop_idx++;
     p->dpb->curr->poc = slice->poc;
     if (curr.is_lt_ref)
@@ -350,11 +351,29 @@ RK_S32 get_num_rps_cur_templist(H265eReferencePictureSet* rps)
 }
 
 
-void h265e_code_slice_header(H265eSlice *slice, MppWriteCtx *bitIf)
+void h265e_code_slice_header(H265eSlice *slice, MppWriteCtx *bitIf,
+                             RK_U32 slice_segment_addr)
 {
     RK_U32 i = 0;
-    mpp_writer_put_bits(bitIf, 1, 1); //first_slice_segment_in_pic_flag
+    RK_U32 slice_address_addr_bits = 0;
+    H265eSps *sps = slice->m_sps;
+    RK_U32 pic_width_in_ctb = (sps->m_picWidthInLumaSamples + sps->m_maxCUSize - 1) /
+                              sps->m_maxCUSize;
+    RK_U32 pic_height_in_ctb = (sps->m_picHeightInLumaSamples + sps->m_maxCUSize - 1) /
+                               sps->m_maxCUSize;
+    RK_U32 max_ctu_num = pic_width_in_ctb * pic_height_in_ctb;
+
+    mpp_writer_put_bits(bitIf, (slice_segment_addr == 0), 1); //first_slice_segment_in_pic_flag
     mpp_writer_put_ue(bitIf, slice->m_ppsId);
+
+    if (slice_segment_addr != 0) {
+        while (max_ctu_num > (1 << slice_address_addr_bits)) {
+            slice_address_addr_bits++;
+        }
+        //slice_segment_address
+        mpp_writer_put_bits(bitIf, slice_segment_addr, slice_address_addr_bits);
+    }
+
     H265eReferencePictureSet* rps = slice->m_rps;
     slice->m_enableTMVPFlag = 0;
     if (!slice->m_dependentSliceSegmentFlag) {
@@ -402,7 +421,7 @@ void h265e_code_slice_header(H265eSlice *slice, MppWriteCtx *bitIf)
                     }
                 }
 
-                numLtrpInSH -= numLtrpInSPS;
+                numLtrpInSH -= rps->m_numberOfPictures - rps->num_long_term_pic;
 
                 RK_S32 bitsForLtrpInSPS = 0;
                 while (slice->m_sps->m_numLongTermRefPicSPS > (RK_U32)(1 << bitsForLtrpInSPS)) {
@@ -521,6 +540,9 @@ void h265e_code_slice_header(H265eSlice *slice, MppWriteCtx *bitIf)
             }
         }
     }
+    if (slice->m_pps->m_tiles_enabled_flag) {
+        mpp_writer_put_ue(bitIf, 0);    // num_entry_point_offsets
+    }
     if (slice->m_pps->m_sliceHeaderExtensionPresentFlag) {
         mpp_writer_put_ue(bitIf, slice->slice_header_extension_length);
         for (i = 0; i < slice->slice_header_extension_length; i++) {
@@ -543,7 +565,7 @@ void code_skip_flag(H265eSlice *slice, RK_U32 abs_part_idx, DataCu *cu)
     h265e_dbg_skip("tpelx = %d", tpelx);
     if (cu->cur_addr == 0 ) {
         ctxSkip = 0;
-    } else if ((tpely == 0) || (tpelx == 0)) {
+    } else if ((tpely == 0) || (tpelx == cu->tile_start_x)) {
         ctxSkip = 1;
     } else {
         ctxSkip = 2;
@@ -585,7 +607,7 @@ static void encode_cu(H265eSlice *slice, RK_U32 abs_part_idx, RK_U32 depth, Data
 
     h265e_dbg_skip("EncodeCU depth %d, abs_part_idx %d", depth, abs_part_idx);
 
-    if ((rpelx < sps->m_picWidthInLumaSamples) && (bpely < sps->m_picHeightInLumaSamples)) {
+    if ((rpelx <= cu->tile_end_x) && (bpely <= cu->tile_end_y)) {
         h265e_dbg_skip("code_split_flag in depth %d", depth);
         code_split_flag(slice, abs_part_idx, depth, cu);
     } else {
@@ -604,7 +626,7 @@ static void encode_cu(H265eSlice *slice, RK_U32 abs_part_idx, RK_U32 depth, Data
             h265e_dbg_skip("depth %d partUnitIdx = %d, qNumParts %d, abs_part_idx %d", depth, partUnitIdx, qNumParts, abs_part_idx);
             lpelx = cu->pixelX + sps->raster2pelx[sps->zscan2raster[abs_part_idx]];
             tpely = cu->pixelY + sps->raster2pely[sps->zscan2raster[abs_part_idx]];
-            if ((lpelx < sps->m_picWidthInLumaSamples) && (tpely < sps->m_picHeightInLumaSamples)) {
+            if ((lpelx <= cu->tile_end_x) && (tpely <= cu->tile_end_y)) {
                 encode_cu(slice, abs_part_idx, depth + 1, cu);
             }
         }
@@ -625,21 +647,21 @@ static void proc_cu8(DataCu *cu, RK_S32 nSubPart, RK_S32 cuDepth, RK_S32 puIdx)
     memset(cu->m_cuDepth + puIdx * nSubPart, cuDepth, nSubPart);
 }
 
-static void proc_cu16(H265eSlice *slice, DataCu *cu, RK_U32 pos_x, RK_U32 pos_y, RK_S32 nSubPart, RK_S32 cuDepth, RK_S32 puIdx)
+static void proc_cu16(DataCu *cu, RK_U32 pos_x, RK_U32 pos_y,
+                      RK_S32 nSubPart, RK_S32 cuDepth, RK_S32 puIdx)
 {
     RK_U32 m;
-    H265eSps *sps = slice->m_sps;
     RK_S32 newPuIdx;
 
     h265e_dbg_skip("cu 16 pos_x %d pos_y %d", pos_x, pos_y);
 
-    if ((cu->pixelX + pos_x + 15 < sps->m_picWidthInLumaSamples) &&
-        (cu->pixelY + pos_y + 15 < sps->m_picHeightInLumaSamples)) {
+    if ((cu->pixelX + pos_x + 15 <= cu->tile_end_x) &&
+        (cu->pixelY + pos_y + 15 <= cu->tile_end_y)) {
         h265e_dbg_skip("16 ctu puIdx %d no need split", puIdx);
         memset(cu->m_cuDepth + puIdx * nSubPart, cuDepth, nSubPart);
         return;
-    } else if ((cu->pixelX + pos_x >=  sps->m_picWidthInLumaSamples) ||
-               (cu->pixelY + pos_y  >= sps->m_picHeightInLumaSamples)) {
+    } else if ((cu->pixelX + pos_x > cu->tile_end_x) ||
+               (cu->pixelY + pos_y > cu->tile_end_y)) {
         h265e_dbg_skip("16 ctu puIdx %d out of pic", puIdx);
         memset(cu->m_cuDepth + puIdx * nSubPart, cuDepth, nSubPart);
         return;
@@ -651,24 +673,23 @@ static void proc_cu16(H265eSlice *slice, DataCu *cu, RK_U32 pos_x, RK_U32 pos_y,
     }
 }
 
-
-static void proc_cu32(H265eSlice *slice, DataCu *cu, RK_U32 pos_x, RK_U32 pos_y, RK_S32 nSubPart, RK_S32 cuDepth, RK_S32 puIdx)
+static void proc_cu32(DataCu *cu, RK_U32 pos_x, RK_U32 pos_y,
+                      RK_S32 nSubPart, RK_S32 cuDepth, RK_S32 puIdx)
 {
     RK_U32 m;
-    H265eSps *sps = slice->m_sps;
     RK_S32 nSize = 32;
     RK_U32 cu_x_1, cu_y_1;
     RK_S32 newPuIdx;
 
     h265e_dbg_skip("cu 32 pos_x %d pos_y %d", pos_x, pos_y);
 
-    if ((cu->pixelX + pos_x + 31 < sps->m_picWidthInLumaSamples) &&
-        (cu->pixelY + pos_y + 31 < sps->m_picHeightInLumaSamples)) {
+    if ((cu->pixelX + pos_x + 31 <= cu->tile_end_x) &&
+        (cu->pixelY + pos_y + 31 <= cu->tile_end_y)) {
         h265e_dbg_skip("32 ctu puIdx %d no need split", puIdx);
         memset(cu->m_cuDepth + puIdx * nSubPart, cuDepth, nSubPart);
         return;
-    } else if ((cu->pixelX + pos_x >=  sps->m_picWidthInLumaSamples) ||
-               (cu->pixelY + pos_y  >= sps->m_picHeightInLumaSamples)) {
+    } else if ((cu->pixelX + pos_x > cu->tile_end_x) ||
+               (cu->pixelY + pos_y > cu->tile_end_y)) {
         h265e_dbg_skip("32 ctu puIdx %d out of pic", puIdx);
         memset(cu->m_cuDepth + puIdx * nSubPart, cuDepth, nSubPart);
         return;
@@ -678,7 +699,7 @@ static void proc_cu32(H265eSlice *slice, DataCu *cu, RK_U32 pos_x, RK_U32 pos_y,
         cu_x_1 = pos_x + (m & 1) * (nSize >> 1);
         cu_y_1 = pos_y + (m >> 1) * (nSize >> 1);
         newPuIdx = puIdx * 4 + m;
-        proc_cu16(slice, cu, cu_x_1, cu_y_1, nSubPart / 4, cuDepth + 1, newPuIdx);
+        proc_cu16(cu, cu_x_1, cu_y_1, nSubPart / 4, cuDepth + 1, newPuIdx);
     }
 }
 
@@ -699,13 +720,13 @@ static void proc_ctu64(H265eSlice *slice, DataCu *cu)
         cu->m_cuDepth[k] = 0;
         cu->m_cuSize[k] = m_nCtuSize;
     }
-    if ((rpelx < sps->m_picWidthInLumaSamples) && (bpely < sps->m_picHeightInLumaSamples))
+    if ((rpelx <= cu->tile_end_x) && (bpely <= cu->tile_end_y))
         return;
 
     for (m = 0; m < 4; m ++) {
         cu_x_1 = (m & 1) * (m_nCtuSize >> 1);
         cu_y_1 = (m >> 1) * (m_nCtuSize >> 1);
-        proc_cu32(slice, cu, cu_x_1, cu_y_1, numPartions / 4, cuDepth + 1, m);
+        proc_cu32(cu, cu_x_1, cu_y_1, numPartions / 4, cuDepth + 1, m);
     }
 
     for (k = 0; k < numPartions; k++) {
@@ -718,16 +739,16 @@ static void proc_ctu64(H265eSlice *slice, DataCu *cu)
     }
 }
 
-static void h265e_write_nal(MppWriteCtx *bitIf)
+static void h265e_write_nal(MppWriteCtx *bitIf, RK_S32 temporal_id)
 {
     h265e_dbg_func("enter\n");
 
     mpp_writer_put_raw_bits(bitIf, 0x0, 24);
     mpp_writer_put_raw_bits(bitIf, 0x01, 8);
-    mpp_writer_put_bits(bitIf, 0, 1);   // forbidden_zero_bit
-    mpp_writer_put_bits(bitIf, 1, 6);   // nal_unit_type
-    mpp_writer_put_bits(bitIf, 0, 6);   // nuh_reserved_zero_6bits
-    mpp_writer_put_bits(bitIf, 1, 3);   // nuh_temporal_id_plus1
+    mpp_writer_put_bits(bitIf, 0, 1);   //forbidden_zero_bit
+    mpp_writer_put_bits(bitIf, 1, 6);   //nal_unit_type
+    mpp_writer_put_bits(bitIf, 0, 6);   //nuh_reserved_zero_6bits
+    mpp_writer_put_bits(bitIf, temporal_id + 1, 3); //nuh_temporal_id_plus1
 
     h265e_dbg_func("leave\n");
 }
@@ -757,13 +778,13 @@ static void proc_ctu32(H265eSlice *slice, DataCu *cu)
         cu->m_cuDepth[k] = 0;
         cu->m_cuSize[k] = m_nCtuSize;
     }
-    if ((rpelx < sps->m_picWidthInLumaSamples) && (bpely < sps->m_picHeightInLumaSamples))
+    if ((rpelx <= cu->tile_end_x) && (bpely <= cu->tile_end_y))
         return;
 
     for (m = 0; m < 4; m ++) {
         cu_x_1 = (m & 1) * (m_nCtuSize >> 1);
         cu_y_1 = (m >> 1) * (m_nCtuSize >> 1);
-        proc_cu16(slice, cu, cu_x_1, cu_y_1, numPartions / 4, cuDepth + 1, m);
+        proc_cu16(cu, cu_x_1, cu_y_1, numPartions / 4, cuDepth + 1, m);
     }
 
     for (k = 0; k < numPartions; k++) {
@@ -775,25 +796,16 @@ static void proc_ctu32(H265eSlice *slice, DataCu *cu)
     }
 }
 
-RK_S32 h265e_code_slice_skip_frame(void *ctx, H265eSlice *slice, RK_U8 *buf, RK_S32 len)
+static void h265e_code_skip_tile(void *ctx, H265eSlice *slice, MppWriteCtx *bitIf, TileInfo *tile)
 {
+    DataCu cu;
     void (*proc_ctu)(H265eSlice *, DataCu *);
-    MppWriteCtx bitIf;
     H265eCtx *p = (H265eCtx *)ctx;
     H265eSps *sps = &p->sps;
     H265eCabacCtx *cabac_ctx = &slice->m_cabac;
-    h265e_dbg_func("enter\n");
-    RK_U32 mb_wd = (sps->m_picWidthInLumaSamples + sps->m_maxCUSize - 1) / sps->m_maxCUSize;
-    RK_U32 mb_h = (sps->m_picHeightInLumaSamples + sps->m_maxCUSize - 1) / sps->m_maxCUSize;
     RK_U32 cu_cnt;
-    RK_U32 offset_x = 0;
-    RK_U32 offset_y = 0;
-    RK_U32 mb_total = mb_wd * mb_h;
-
-    if (!buf || !len) {
-        mpp_err("buf or size no set");
-        return MPP_NOK;
-    }
+    RK_U32 offset_x = tile->tile_start_x;
+    RK_U32 offset_y = tile->tile_start_y;
 
     if (sps->m_maxCUSize == 32)
         /* rk3528 maxCUSize[32] depth[3], other chips maxCUSize[64] depth[4],
@@ -802,17 +814,17 @@ RK_S32 h265e_code_slice_skip_frame(void *ctx, H265eSlice *slice, RK_U8 *buf, RK_
     else
         proc_ctu = proc_ctu64;
 
-    mpp_writer_init(&bitIf, buf, len);
-    h265e_write_nal(&bitIf);
-    h265e_code_slice_header(slice, &bitIf);
-    h265e_write_algin(&bitIf);
+    h265e_write_nal(bitIf, slice->temporal_id);
+    h265e_code_slice_header(slice, bitIf, tile->ctu_addr);
+    h265e_write_algin(bitIf);
     h265e_reset_enctropy((void*)slice);
-    h265e_cabac_init(cabac_ctx, &bitIf);
-    DataCu cu;
-    cu.mb_w = mb_wd;
-    cu.mb_h = mb_h;
+    h265e_cabac_init(cabac_ctx, bitIf);
+
     slice->is_referenced = 0;
-    for (cu_cnt = 0; cu_cnt < mb_total - 1; cu_cnt++) {
+    cu.tile_start_x = tile->tile_start_x;
+    cu.tile_end_x = tile->tile_end_x;
+    cu.tile_end_y = tile->tile_end_y;
+    for (cu_cnt = 0; cu_cnt < tile->mb_total - 1; cu_cnt++) {
         cu.pixelX = offset_x;
         cu.pixelY = offset_y;
         cu.cur_addr = cu_cnt;
@@ -820,8 +832,8 @@ RK_S32 h265e_code_slice_skip_frame(void *ctx, H265eSlice *slice, RK_U8 *buf, RK_
         encode_cu(slice, 0, 0, &cu);
         h265e_cabac_encodeBinTrm(cabac_ctx, 0);
         offset_x += sps->m_maxCUSize;
-        if (offset_x >= sps->m_picWidthInLumaSamples) {
-            offset_x = 0;
+        if (offset_x > tile->tile_end_x) {
+            offset_x = tile->tile_start_x;
             offset_y += sps->m_maxCUSize;
         }
     }
@@ -833,7 +845,53 @@ RK_S32 h265e_code_slice_skip_frame(void *ctx, H265eSlice *slice, RK_U8 *buf, RK_
     encode_cu(slice, 0, 0, &cu);
     h265e_cabac_encodeBinTrm(cabac_ctx, 1);
     h265e_cabac_finish(cabac_ctx);
-    h265e_write_algin(&bitIf);
+    h265e_write_algin(bitIf);
+}
+
+RK_S32 h265e_code_slice_skip_frame(void *ctx, H265eSlice *slice, RK_U8 *buf, RK_S32 len)
+{
+    H265eCtx *p = (H265eCtx *)ctx;
+    H265eSps *sps = &p->sps;
+    H265ePps *pps = &p->pps;
+    TileInfo tile;
+    MppWriteCtx bitIf;
+    RK_U32 mb_wd;
+    RK_U32 mb_h;
+    RK_S32 i;
+
+    h265e_dbg_func("enter\n");
+    if (!buf || !len) {
+        mpp_err("buf or size no set");
+        return MPP_NOK;
+    }
+
+    mpp_writer_init(&bitIf, buf, len);
+    tile.ctu_addr = 0;
+    tile.tile_start_y = 0;
+    tile.tile_end_y = sps->m_picHeightInLumaSamples - 1;
+
+    if (pps->m_nNumTileColumnsMinus1) {
+        tile.tile_start_x = 0;
+        for (i = 0; i <= pps->m_nNumTileColumnsMinus1; i++) {
+            tile.mb_total = pps->m_nTileColumnWidthArray[i] * pps->m_nTileRowHeightArray[i];
+            if (i != pps->m_nNumTileColumnsMinus1)
+                tile.tile_end_x = tile.tile_start_x +
+                                  (pps->m_nTileColumnWidthArray[i] * sps->m_maxCUSize) - 1;
+            else
+                tile.tile_end_x = sps->m_picWidthInLumaSamples - 1;
+            h265e_code_skip_tile(ctx, slice, &bitIf, &tile);
+            tile.tile_start_x += (pps->m_nTileColumnWidthArray[i] * sps->m_maxCUSize);
+            tile.ctu_addr += pps->m_nTileColumnWidthArray[i];
+        }
+    } else {
+        mb_wd = (sps->m_picWidthInLumaSamples + sps->m_maxCUSize - 1) / sps->m_maxCUSize;
+        mb_h = (sps->m_picHeightInLumaSamples + sps->m_maxCUSize - 1) / sps->m_maxCUSize;
+        tile.mb_total = mb_wd * mb_h;
+        tile.tile_start_x = 0;
+        tile.tile_end_x = sps->m_picWidthInLumaSamples - 1;
+        h265e_code_skip_tile(ctx, slice, &bitIf, &tile);
+    }
+
     h265e_dbg_func("leave\n");
     return mpp_writer_bytes(&bitIf);
 }
diff --git a/mpp/codec/enc/h265/h265e_slice.h b/mpp/codec/enc/h265/h265e_slice.h
index 47b4d9544..9a7ee17dd 100644
--- a/mpp/codec/enc/h265/h265e_slice.h
+++ b/mpp/codec/enc/h265/h265e_slice.h
@@ -41,11 +41,21 @@ typedef struct DataCu_t {
     RK_U8   m_cuDepth[256];
     RK_U32  pixelX;
     RK_U32  pixelY;
-    RK_U32  mb_w;
-    RK_U32  mb_h;
     RK_U32  cur_addr;
+    RK_U32  tile_start_x;
+    RK_U32  tile_end_x;
+    RK_U32  tile_end_y;
 } DataCu;
 
+typedef struct TileInfo_t {
+    RK_U32 tile_start_x;
+    RK_U32 tile_end_x;
+    RK_U32 tile_start_y;
+    RK_U32 tile_end_y;
+    RK_U32 mb_total;
+    RK_U32 ctu_addr;
+} TileInfo;
+
 typedef struct H265eReferencePictureSet_e {
     RK_S32  m_deltaRIdxMinus1;
     RK_S32  m_deltaRPS;
@@ -275,7 +285,7 @@ typedef struct H265eSps_e {
 
     RK_U32          m_bTemporalIdNestingFlag; // temporal_id_nesting_flag
 
-    RK_U32          m_scalingListEnabledFlag;
+    RK_U32          m_scalingListEnabledFlag; //TODO: replaced with scaling_list_mode
     RK_U32          m_scalingListPresentFlag;
     RK_U32          m_maxDecPicBuffering[MAX_SUB_LAYERS];
 
@@ -367,6 +377,8 @@ typedef struct H265eSlice_e {
 
     enum NALUnitType m_nalUnitType;       ///< Nal unit type for the slice
     SliceType        m_sliceType;
+
+    RK_S32           temporal_id;
     RK_U32           m_IsGenB;
     RK_S32           m_sliceQp;
     RK_U32           m_dependentSliceSegmentFlag;
@@ -435,6 +447,7 @@ void h265e_slice_set_ref_list(H265eDpbFrm *frame_list, H265eSlice *slice);
 void h265e_slice_set_ref_poc_list(H265eSlice *slice);
 void h265e_slice_init(void *ctx, EncFrmStatus curr);
 RK_S32 h265e_code_slice_skip_frame(void *ctx, H265eSlice *slice, RK_U8 *buf, RK_S32 len);
+H265eDpbFrm* get_lt_ref_pic(H265eDpbFrm *frame_list, H265eSlice *slice, RK_S32 poc, RK_U32 pocHasMsb);
 
 #ifdef __cplusplus
 }
diff --git a/mpp/codec/enc/h265/h265e_syntax.c b/mpp/codec/enc/h265/h265e_syntax.c
index f31b1e47b..a27136e41 100644
--- a/mpp/codec/enc/h265/h265e_syntax.c
+++ b/mpp/codec/enc/h265/h265e_syntax.c
@@ -120,11 +120,11 @@ static void fill_picture_parameters(const H265eCtx *h,
         pp->num_tile_columns_minus1 = pps->m_nNumTileColumnsMinus1;
         pp->num_tile_rows_minus1 = pps->m_nNumTileRowsMinus1;
 
-        for (i = 0; i < pp->num_tile_columns_minus1; i++)
-            pp->column_width_minus1[i] = pps->m_nTileColumnWidthArray[i];
+        for (i = 0; i <= pp->num_tile_columns_minus1; i++)
+            pp->column_width_minus1[i] = pps->m_nTileColumnWidthArray[i] - 1;
 
-        for (i = 0; i < pp->num_tile_rows_minus1; i++)
-            pp->row_height_minus1[i] = pps->m_nTileRowHeightArray[i];
+        for (i = 0; i <= pp->num_tile_rows_minus1; i++)
+            pp->row_height_minus1[i] = pps->m_nTileRowHeightArray[i] - 1;
     }
 }
 
@@ -147,8 +147,6 @@ static void fill_slice_parameters( const H265eCtx *h,
         sp->sli_flsh = 1;
     }
 
-
-
     sp->cbc_init_flg        = slice->m_cabacInitFlag;
     sp->mvd_l1_zero_flg     = slice->m_bLMvdL1Zero;
     sp->merge_up_flag       = codec->merge_cfg.merge_up_flag;
@@ -181,6 +179,7 @@ static void fill_slice_parameters( const H265eCtx *h,
     sp->sli_cb_qp_ofst = slice->m_sliceQpDeltaCb;
     sp->sli_qp = slice->m_sliceQp;
     sp->max_mrg_cnd = slice->m_maxNumMergeCand;
+    sp->temporal_id = slice->temporal_id;
     sp->non_reference_flag = slice->m_temporalLayerNonReferenceFlag;
     sp->col_ref_idx = 0;
     sp->col_frm_l0_flg = slice->m_colFromL0Flag;
@@ -193,6 +192,7 @@ RK_S32 fill_ref_parameters(const H265eCtx *h, H265eSlicParams *sp)
 {
     H265eSlice  *slice = h->slice;
     H265eReferencePictureSet* rps = slice->m_rps;
+    H265eSyntax_new *syn = (H265eSyntax_new*)&h->syntax;
     RK_U32 numRpsCurrTempList = 0;
     RK_S32 ref_num = 0;
     H265eDpbFrm *ref_frame;
@@ -232,7 +232,6 @@ RK_S32 fill_ref_parameters(const H265eCtx *h, H265eSlicParams *sp)
     if (slice->m_sps->m_bLongTermRefsPresent) {
         RK_S32 numLtrpInSH = rps->num_long_term_pic;
         RK_S32 numLtrpInSPS = 0;
-        RK_S32 counter = 0;
         RK_U32 poc_lsb_lt[3] = { 0, 0, 0 };
         RK_U32 used_by_lt_flg[3] = { 0, 0, 0 };
         RK_U32 dlt_poc_msb_prsnt[3] = { 0, 0, 0 };
@@ -251,11 +250,8 @@ RK_S32 fill_ref_parameters(const H265eCtx *h, H265eSlicParams *sp)
                 }
             }
 
-            if (find_flag) {
+            if (find_flag)
                 numLtrpInSPS++;
-            } else {
-                counter++;
-            }
         }
 
         numLtrpInSH -= numLtrpInSPS;
@@ -344,11 +340,15 @@ RK_S32 fill_ref_parameters(const H265eCtx *h, H265eSlicParams *sp)
 
     sp->recon_pic.slot_idx = h->dpb->curr->slot_idx;
     ref_frame = slice->m_refPicList[0][0];
-    if (ref_frame != NULL) {
+
+    if (ref_frame) {
+        if (ref_frame->status.force_pskip)
+            ref_frame->slot_idx = syn->pre_ref_idx;
         sp->ref_pic.slot_idx = ref_frame->slot_idx;
     } else {
         sp->ref_pic.slot_idx = h->dpb->curr->slot_idx;
     }
+
     return  0;
 }
 
diff --git a/mpp/codec/enc/jpeg/jpege_api_v2.c b/mpp/codec/enc/jpeg/jpege_api_v2.c
index 96039579c..a69acd52f 100644
--- a/mpp/codec/enc/jpeg/jpege_api_v2.c
+++ b/mpp/codec/enc/jpeg/jpege_api_v2.c
@@ -23,12 +23,12 @@
 #include "mpp_mem.h"
 #include "mpp_common.h"
 #include "mpp_2str.h"
+#include "mpp_enc_cfg_impl.h"
+#include "mpp_bitwrite.h"
 
 #include "jpege_debug.h"
 #include "jpege_api_v2.h"
 #include "jpege_syntax.h"
-#include "mpp_enc_cfg_impl.h"
-#include "mpp_bitwrite.h"
 
 typedef struct {
     MppEncCfgSet    *cfg;
@@ -82,10 +82,10 @@ static MPP_RET jpege_init_v2(void *ctx, EncImplCfg *cfg)
 
         rc->fps_in_flex = 0;
         rc->fps_in_num = 30;
-        rc->fps_in_denorm = 1;
+        rc->fps_in_denom = 1;
         rc->fps_out_flex = 0;
         rc->fps_out_num = 30;
-        rc->fps_out_denorm = 1;
+        rc->fps_out_denom = 1;
         rc->rc_mode = MPP_ENC_RC_MODE_VBR;
         /* init default quant */
         jpeg_cfg->quant = 10;
@@ -121,8 +121,19 @@ static MPP_RET jpege_proc_prep_cfg(MppEncPrepCfg *dst, MppEncPrepCfg *src)
         RK_S32 mirroring;
         RK_S32 rotation;
 
-        if (change & MPP_ENC_PREP_CFG_CHANGE_FORMAT)
+        if (change & MPP_ENC_PREP_CFG_CHANGE_FORMAT) {
             dst->format = src->format;
+            dst->format_out = src->format_out;
+            dst->fix_chroma_en = src->fix_chroma_en;
+            dst->fix_chroma_u = src->fix_chroma_u;
+            dst->fix_chroma_v = src->fix_chroma_v;
+            dst->chroma_ds_mode = src->chroma_ds_mode;
+        }
+
+        if (change & MPP_ENC_PREP_CFG_CHANGE_COLOR_RANGE) {
+            dst->range = src->range;
+            dst->range_out = src->range_out;
+        }
 
         if (change & MPP_ENC_PREP_CFG_CHANGE_ROTATION)
             dst->rotation_ext = src->rotation_ext;
@@ -241,6 +252,7 @@ static MPP_RET jpege_gen_qt_by_qfactor(MppEncJpegCfg *cfg, RK_S32 *factor)
         qtable_y[i] = MPP_CLIP3(1, 255, lq);
         qtable_c[i] = MPP_CLIP3(1, 255, cq);
     }
+
     return ret;
 }
 
@@ -468,6 +480,58 @@ static MPP_RET jpege_start(void *ctx, HalEncTask *task)
     return MPP_OK;
 }
 
+static MPP_RET init_jpeg_component_info(JpegeSyntax *syntax)
+{
+    MPP_RET ret = MPP_OK;
+    JPEGCompInfo *comp_info = (JPEGCompInfo *)syntax->comp_info;
+
+    jpege_dbg_input("Chroma format %d\n", syntax->format_out);
+
+    if (syntax->format_out == MPP_CHROMA_UNSPECIFIED)
+        syntax->format_out = MPP_CHROMA_420;
+
+    memset(comp_info, 0, sizeof(JPEGCompInfo) * MAX_NUMBER_OF_COMPONENTS);
+
+    switch (syntax->format_out) {
+    case MPP_CHROMA_400:
+        syntax->nb_components = 1;
+        comp_info[0].val = 1 | 1 << 8 | 1 << 16;
+        break;
+    case MPP_CHROMA_420:
+        syntax->nb_components = 3;
+        comp_info[0].val = 1 | 2 << 8 | 2 << 16;
+        comp_info[1].val = 2 | 1 << 8 | 1 << 16 | 1 << 24;
+        comp_info[2].val = 3 | 1 << 8 | 1 << 16 | 1 << 24;
+        break;
+    case MPP_CHROMA_422:
+        syntax->nb_components = 3;
+        comp_info[0].val = 1 | 2 << 8 | 1 << 16;
+        comp_info[1].val = 2 | 1 << 8 | 1 << 16 | 1 << 24;
+        comp_info[2].val = 3 | 1 << 8 | 1 << 16 | 1 << 24;
+        break;
+    case MPP_CHROMA_444:
+        syntax->nb_components = 3;
+        comp_info[0].val = 1 | 1 << 8 | 1 << 16;
+        comp_info[1].val = 2 | 1 << 8 | 1 << 16 | 1 << 24;
+        comp_info[2].val = 3 | 1 << 8 | 1 << 16 | 1 << 24;
+        break;
+    default:
+        syntax->nb_components = 1;
+        comp_info[0].val = 1 | 1 << 8 | 1 << 16;
+        mpp_err("Unsupported chroma format %d\n", syntax->format_out);
+        ret = MPP_ERR_VALUE;
+        break;
+    }
+
+    syntax->mcu_width = comp_info[0].h_sample_factor * DCT_SIZE;
+    syntax->mcu_height = comp_info[0].v_sample_factor * DCT_SIZE;
+    syntax->mcu_hor_cnt = (syntax->width + syntax->mcu_width - 1) / syntax->mcu_width;
+    syntax->mcu_ver_cnt = (syntax->height + syntax->mcu_height - 1) / syntax->mcu_height;
+    syntax->mcu_cnt = syntax->mcu_hor_cnt * syntax->mcu_ver_cnt;
+
+    return ret;
+}
+
 static MPP_RET jpege_proc_hal(void *ctx, HalEncTask *task)
 {
     JpegeCtx *p = (JpegeCtx *)ctx;
@@ -484,9 +548,8 @@ static MPP_RET jpege_proc_hal(void *ctx, HalEncTask *task)
     syntax->height      = prep->height;
     syntax->hor_stride  = prep->hor_stride;
     syntax->ver_stride  = prep->ver_stride;
-    syntax->mcu_w       = MPP_ALIGN(prep->width, 16) / 16;
-    syntax->mcu_h       = MPP_ALIGN(prep->height, 16) / 16;
     syntax->format      = prep->format;
+    syntax->format_out  = prep->format_out;
     syntax->color       = prep->color;
     syntax->rotation    = prep->rotation;
     syntax->mirroring   = prep->mirroring;
@@ -502,22 +565,23 @@ static MPP_RET jpege_proc_hal(void *ctx, HalEncTask *task)
     syntax->restart_ri  = 0;
     syntax->low_delay   = 0;
 
+    init_jpeg_component_info(syntax);
+
     if (split->split_mode) {
-        RK_U32 mb_h = MPP_ALIGN(prep->height, 16) / 16;
+        RK_U32 mb_w = syntax->mcu_hor_cnt;
+        RK_U32 mb_h = syntax->mcu_ver_cnt;
         RK_U32 part_rows = 0;
 
         if (split->split_mode == MPP_ENC_SPLIT_BY_CTU) {
             RK_U32 part_mbs = split->split_arg;
-            RK_U32 mb_w = MPP_ALIGN(prep->width, 16) / 16;
-            RK_U32 mb_all = mb_w * mb_h;
 
-            if (part_mbs > 0 && part_mbs <= mb_all) {
+            if (part_mbs > 0 && part_mbs <= syntax->mcu_cnt) {
                 part_rows = (part_mbs + mb_w - 1) / mb_w;
                 if (part_rows >= mb_h)
                     part_rows = 0;
             } else {
                 mpp_err_f("warning: invalid split arg %d > max %d\n",
-                          part_mbs, mb_all);
+                          part_mbs, syntax->mcu_cnt);
             }
         } else {
             mpp_err_f("warning: only mcu split is supported\n");
@@ -525,7 +589,10 @@ static MPP_RET jpege_proc_hal(void *ctx, HalEncTask *task)
 
         if (part_rows) {
             syntax->part_rows   = part_rows;
-            syntax->restart_ri  = syntax->mcu_w * part_rows;
+            if (mpp_get_soc_type() == ROCKCHIP_SOC_RK3576 && split->split_arg <= syntax->mcu_cnt)
+                syntax->restart_ri = split->split_arg;
+            else
+                syntax->restart_ri  = syntax->mcu_hor_cnt * part_rows;
             syntax->low_delay   = cfg->base.low_delay && part_rows;
             jpege_dbg_func("Split by CTU, part_rows %d, restart_ri %d",
                            syntax->part_rows, syntax->restart_ri);
diff --git a/mpp/codec/enc/vp8/vp8e_api_v2.c b/mpp/codec/enc/vp8/vp8e_api_v2.c
index 00be169c1..17add9bff 100644
--- a/mpp/codec/enc/vp8/vp8e_api_v2.c
+++ b/mpp/codec/enc/vp8/vp8e_api_v2.c
@@ -97,10 +97,10 @@ static MPP_RET vp8e_init(void *ctx, EncImplCfg *ctrl_cfg)
     rc_cfg->bps_min = rc_cfg->bps_target * 3 / 4;
     rc_cfg->fps_in_flex = 0;
     rc_cfg->fps_in_num = 30;
-    rc_cfg->fps_in_denorm = 1;
+    rc_cfg->fps_in_denom = 1;
     rc_cfg->fps_out_flex = 0;
     rc_cfg->fps_out_num = 30;
-    rc_cfg->fps_out_denorm = 1;
+    rc_cfg->fps_out_denom = 1;
     rc_cfg->gop = 60;
     rc_cfg->max_reenc_times = 1;
     rc_cfg->fqp_min_i = INT_MAX;
diff --git a/mpp/codec/enc/vp8/vp8e_rc.c b/mpp/codec/enc/vp8/vp8e_rc.c
index 669b1b2c4..135325f39 100644
--- a/mpp/codec/enc/vp8/vp8e_rc.c
+++ b/mpp/codec/enc/vp8/vp8e_rc.c
@@ -406,18 +406,18 @@ MPP_RET vp8e_update_rc_cfg(Vp8eRc *rc, MppEncRcCfg *cfg)
     }
 
     if (change & MPP_ENC_RC_CFG_CHANGE_FPS_OUT) {
-        vp8e_rc_dbg_cfg("fps: %d / %d\n", cfg->fps_out_num, cfg->fps_out_denorm);
+        vp8e_rc_dbg_cfg("fps: %d / %d\n", cfg->fps_out_num, cfg->fps_out_denom);
         rc->fps_out_num = cfg->fps_out_num;
-        rc->fps_out_denorm = cfg->fps_out_denorm;
-        if (rc->fps_out_denorm == 0) {
-            mpp_err("denorm can not be 0, change to default 1");
-            rc->fps_out_denorm = 1;
+        rc->fps_out_denom = cfg->fps_out_denom;
+        if (rc->fps_out_denom == 0) {
+            mpp_err("denom can not be 0, change to default 1");
+            rc->fps_out_denom = 1;
         }
-        rc->fps_out = rc->fps_out_num / rc->fps_out_denorm;
+        rc->fps_out = rc->fps_out_num / rc->fps_out_denom;
         if (rc->fps_out == 0) {
             rc->fps_out = 30;
             rc->fps_out_num = 30;
-            rc->fps_out_denorm = 1;
+            rc->fps_out_denom = 1;
             mpp_err("fps out can not be 0, change to default 30");
         }
     }
@@ -427,7 +427,7 @@ MPP_RET vp8e_update_rc_cfg(Vp8eRc *rc, MppEncRcCfg *cfg)
         rc->gop_len = cfg->gop;
         vp8e_rc_dbg_cfg("gop: %d\n", cfg->gop);
     }
-    vb->bit_per_pic = axb_div_c(vb->bit_rate, rc->fps_out_denorm, rc->fps_out_num);
+    vb->bit_per_pic = axb_div_c(vb->bit_rate, rc->fps_out_denom, rc->fps_out_num);
 
     cfg->change = 0;
 
@@ -452,7 +452,7 @@ MPP_RET vp8e_init_rc(Vp8eRc *rc, MppEncCfgSet *cfg)
     rc->golden_picture_rate = 0;
     rc->altref_picture_rate = 0;
     rc->virbuf.bit_rate = cfg->rc.bps_target;
-    rc->fps_out_denorm = cfg->rc.fps_out_denorm;
+    rc->fps_out_denom = cfg->rc.fps_out_denom;
     rc->fps_out_num = cfg->rc.fps_out_num;
     rc->mb_per_pic = ((cfg->prep.width + 15) / 16) * ((cfg->prep.height + 15) / 16);
 
@@ -464,12 +464,12 @@ MPP_RET vp8e_init_rc(Vp8eRc *rc, MppEncCfgSet *cfg)
 
     max_bps = rc->mb_per_pic * 16 * 16 * 6;
     max_bps = axb_div_c(max_bps, rc->fps_out_num,
-                        rc->fps_out_denorm);
+                        rc->fps_out_denom);
 
     if (max_bps < 0)
         max_bps = I32_MPP_MAX;
     vb->bit_rate = MPP_MIN(vb->bit_rate, max_bps);
-    vb->bit_per_pic = axb_div_c(vb->bit_rate, rc->fps_out_denorm,
+    vb->bit_per_pic = axb_div_c(vb->bit_rate, rc->fps_out_denom,
                                 rc->fps_out_num);
 
     if (rc->qp_hdr == -1)
diff --git a/mpp/codec/inc/mpp_rc.h b/mpp/codec/inc/mpp_rc.h
index 94e4f52d3..bbe6e71ce 100644
--- a/mpp/codec/inc/mpp_rc.h
+++ b/mpp/codec/inc/mpp_rc.h
@@ -124,11 +124,11 @@ extern "C" {
 MPP_RET mpp_data_init(MppData **p, RK_S32 len);
 void mpp_data_deinit(MppData *p);
 void mpp_data_update(MppData *p, RK_S32 val);
-RK_S32 mpp_data_avg(MppData *p, RK_S32 len, RK_S32 num, RK_S32 denorm);
+RK_S32 mpp_data_avg(MppData *p, RK_S32 len, RK_S32 num, RK_S32 denom);
 
 void mpp_pid_reset(MppPIDCtx *p);
 void mpp_pid_set_param(MppPIDCtx *p, RK_S32 coef_p, RK_S32 coef_i, RK_S32 coef_d, RK_S32 div, RK_S32 len);
-void mpp_pid_update(MppPIDCtx *p, RK_S32 val);
+void mpp_pid_update(MppPIDCtx *p, RK_S32 val, RK_S32 is_reset);
 RK_S32 mpp_pid_calc(MppPIDCtx *ctx);
 
 #ifdef __cplusplus
diff --git a/mpp/codec/mpp_dec.cpp b/mpp/codec/mpp_dec.cpp
index ffc7016ee..71ffec6bb 100644
--- a/mpp/codec/mpp_dec.cpp
+++ b/mpp/codec/mpp_dec.cpp
@@ -142,7 +142,8 @@ MPP_RET mpp_dec_proc_cfg(MppDecImpl *dec, MpiCmd cmd, void *param)
     case MPP_DEC_SET_DISABLE_ERROR :
     case MPP_DEC_SET_ENABLE_DEINTERLACE :
     case MPP_DEC_SET_ENABLE_FAST_PLAY :
-    case MPP_DEC_SET_ENABLE_MVC : {
+    case MPP_DEC_SET_ENABLE_MVC :
+    case MPP_DEC_SET_DISABLE_DPB_CHECK: {
         ret = mpp_dec_set_cfg_by_cmd(&dec->cfg, cmd, param);
         mpp_dec_update_cfg(dec);
         dec->cfg.base.change = 0;
@@ -534,6 +535,9 @@ MPP_RET mpp_dec_set_cfg(MppDecCfgSet *dst, MppDecCfgSet *src)
         if (change & MPP_DEC_CFG_CHANGE_ENABLE_MVC)
             dst_base->enable_mvc = src_base->enable_mvc;
 
+        if (change & MPP_DEC_CFG_CHANGE_DISABLE_DPB_CHECK)
+            dst_base->disable_dpb_chk = src_base->disable_dpb_chk;
+
         if (change & MPP_DEC_CFG_CHANGE_DISABLE_THREAD)
             dst_base->disable_thread = src_base->disable_thread;
 
@@ -1058,6 +1062,11 @@ MPP_RET mpp_dec_set_cfg_by_cmd(MppDecCfgSet *set, MpiCmd cmd, void *param)
         cfg->change |= MPP_DEC_CFG_CHANGE_ENABLE_MVC;
         dec_dbg_func("enable MVC decoder %d\n", cfg->enable_mvc);
     } break;
+    case MPP_DEC_SET_DISABLE_DPB_CHECK : {
+        cfg->disable_dpb_chk = (param) ? (*((RK_U32 *)param)) : (0);
+        cfg->change |= MPP_DEC_CFG_CHANGE_DISABLE_DPB_CHECK;
+        dec_dbg_func("disable dpb discontinuous check %d\n", cfg->disable_dpb_chk);
+    } break;
     default : {
         mpp_err_f("unsupported cfg update cmd %x\n", cmd);
         ret = MPP_NOK;
diff --git a/mpp/codec/mpp_dec_no_thread.cpp b/mpp/codec/mpp_dec_no_thread.cpp
index cc50c87e6..69e96989f 100644
--- a/mpp/codec/mpp_dec_no_thread.cpp
+++ b/mpp/codec/mpp_dec_no_thread.cpp
@@ -23,6 +23,7 @@
 #include "mpp_dec_debug.h"
 #include "mpp_dec_vproc.h"
 #include "mpp_dec_no_thread.h"
+#include "rk_hdr_meta_com.h"
 
 MPP_RET mpp_dec_decode(MppDec ctx, MppPacket packet)
 {
@@ -118,6 +119,7 @@ MPP_RET mpp_dec_decode(MppDec ctx, MppPacket packet)
             mpp_buffer_get(mpp->mPacketGroup, &hal_buf_in, stream_size);
             if (hal_buf_in) {
                 mpp_buf_slot_set_prop(packet_slots, slot_pkt, SLOT_BUFFER, hal_buf_in);
+                mpp_buffer_attach_dev(hal_buf_in, dec->dev);
                 mpp_buffer_put(hal_buf_in);
             }
         } else {
@@ -271,6 +273,17 @@ MPP_RET mpp_dec_decode(MppDec ctx, MppPacket packet)
         task->hal_frm_buf_out = hal_buf_out;
     }
 
+    {
+        MppFrame mframe = NULL;
+
+        mpp_buf_slot_get_prop(frame_slots, task_dec->output, SLOT_FRAME_PTR, &mframe);
+
+        if (MPP_FRAME_FMT_IS_HDR(mpp_frame_get_fmt(mframe)) &&
+            dec->cfg.base.enable_hdr_meta) {
+            fill_hdr_meta_to_frame(mframe, dec->coding);
+        }
+    }
+
     task->wait.dec_pic_match = (NULL == task->hal_frm_buf_out);
     if (task->wait.dec_pic_match)
         return MPP_NOK;
diff --git a/mpp/codec/mpp_dec_normal.cpp b/mpp/codec/mpp_dec_normal.cpp
index da8b65aa3..986056d4d 100644
--- a/mpp/codec/mpp_dec_normal.cpp
+++ b/mpp/codec/mpp_dec_normal.cpp
@@ -23,6 +23,7 @@
 #include "mpp_dec_debug.h"
 #include "mpp_dec_vproc.h"
 #include "mpp_dec_normal.h"
+#include "rk_hdr_meta_com.h"
 
 static RK_S32 ts_cmp(void *priv, const struct list_head *a, const struct list_head *b)
 {
@@ -425,6 +426,7 @@ static MPP_RET try_proc_dec_task(Mpp *mpp, DecTask *task)
         mpp_buffer_get(mpp->mPacketGroup, &hal_buf_in, stream_size);
         if (hal_buf_in) {
             mpp_buf_slot_set_prop(packet_slots, task_dec->input, SLOT_BUFFER, hal_buf_in);
+            mpp_buffer_attach_dev(hal_buf_in, dec->dev);
             mpp_buffer_put(hal_buf_in);
         }
     } else {
@@ -600,7 +602,18 @@ static MPP_RET try_proc_dec_task(Mpp *mpp, DecTask *task)
     output = task_dec->output;
     mpp_buf_slot_get_prop(frame_slots, output, SLOT_BUFFER, &hal_buf_out);
     if (NULL == hal_buf_out) {
+        MppFrame mframe = NULL;
+        mpp_buf_slot_get_prop(frame_slots, output,
+                              SLOT_FRAME_PTR, &mframe);
         size_t size = mpp_buf_slot_get_size(frame_slots);
+
+        if (mframe && mpp_frame_get_thumbnail_en(mframe) == MPP_FRAME_THUMBNAIL_ONLY) {
+            // only for 8K thumbnail downscale to 4K 8bit mode
+            RK_U32 downscale_width = mpp_frame_get_width(mframe) / 2;
+            RK_U32 downscale_height = mpp_frame_get_height(mframe) / 2;
+
+            size = downscale_width * downscale_height * 3 / 2;
+        }
         mpp_buffer_get(mpp->mFrameGroup, &hal_buf_out, size);
         if (hal_buf_out)
             mpp_buf_slot_set_prop(frame_slots, output, SLOT_BUFFER,
@@ -609,6 +622,17 @@ static MPP_RET try_proc_dec_task(Mpp *mpp, DecTask *task)
 
     dec_dbg_detail("detail: %p check output buffer %p\n", dec, hal_buf_out);
 
+    {
+        MppFrame mframe = NULL;
+
+        mpp_buf_slot_get_prop(frame_slots, output, SLOT_FRAME_PTR, &mframe);
+
+        if (MPP_FRAME_FMT_IS_HDR(mpp_frame_get_fmt(mframe)) &&
+            dec->cfg.base.enable_hdr_meta) {
+            fill_hdr_meta_to_frame(mframe, dec->coding);
+        }
+    }
+
     // update codec info
     if (!dec->info_updated && dec->dev) {
         MppFrame frame = NULL;
diff --git a/mpp/codec/mpp_enc_impl.cpp b/mpp/codec/mpp_enc_impl.cpp
index 063623b92..55f1f1449 100644
--- a/mpp/codec/mpp_enc_impl.cpp
+++ b/mpp/codec/mpp_enc_impl.cpp
@@ -21,8 +21,11 @@
 #include <limits.h>
 
 #include "mpp_time.h"
+#include "mpp_mem.h"
 #include "mpp_common.h"
+#include "mpp_buffer_impl.h"
 
+#include "mpp_enc_refs.h"
 #include "mpp_frame_impl.h"
 #include "mpp_packet_impl.h"
 
@@ -82,6 +85,7 @@ RK_U8 uuid_refresh_cfg[16] = {
     0x5f, 0x70, 0x6f, 0x69, 0x6e, 0x74, 0x00, 0x00
 };
 
+static MPP_RET enc_async_wait_task(MppEncImpl *enc, EncAsyncTaskInfo *info);
 static void reset_hal_enc_task(HalEncTask *task)
 {
     memset(task, 0, sizeof(*task));
@@ -262,8 +266,7 @@ static RK_S32 check_resend_hdr(MpiCmd cmd, void *param, MppEncCfgSet *cfg)
         "set cfg change codec",
     };
 
-    if (cfg->codec.coding == MPP_VIDEO_CodingMJPEG ||
-        cfg->codec.coding == MPP_VIDEO_CodingVP8)
+    if (cfg->codec.coding == MPP_VIDEO_CodingMJPEG)
         return 0;
 
     do {
@@ -561,13 +564,13 @@ MPP_RET mpp_enc_proc_rc_cfg(MppCodingType coding, MppEncRcCfg *dst, MppEncRcCfg
         if (change & MPP_ENC_RC_CFG_CHANGE_FPS_IN) {
             dst->fps_in_flex = src->fps_in_flex;
             dst->fps_in_num = src->fps_in_num;
-            dst->fps_in_denorm = src->fps_in_denorm;
+            dst->fps_in_denom = src->fps_in_denom;
         }
 
         if (change & MPP_ENC_RC_CFG_CHANGE_FPS_OUT) {
             dst->fps_out_flex = src->fps_out_flex;
             dst->fps_out_num = src->fps_out_num;
-            dst->fps_out_denorm = src->fps_out_denorm;
+            dst->fps_out_denom = src->fps_out_denom;
         }
 
         if (change & MPP_ENC_RC_CFG_CHANGE_GOP) {
@@ -680,6 +683,9 @@ MPP_RET mpp_enc_proc_rc_cfg(MppCodingType coding, MppEncRcCfg *dst, MppEncRcCfg
             dst->refresh_num = src->refresh_num;
         }
 
+        if (change & MPP_ENC_RC_CFG_CHANGE_QPDD)
+            dst->cu_qp_delta_depth = src->cu_qp_delta_depth;
+
         // parameter checking
         if (dst->rc_mode >= MPP_ENC_RC_MODE_BUTT) {
             mpp_err("invalid rc mode %d should be RC_MODE_VBR or RC_MODE_CBR\n",
@@ -714,11 +720,11 @@ MPP_RET mpp_enc_proc_rc_cfg(MppCodingType coding, MppEncRcCfg *dst, MppEncRcCfg
             }
         }
 
-        if (dst->fps_in_num < 0 || dst->fps_in_denorm < 0 ||
-            dst->fps_out_num < 0 || dst->fps_out_denorm < 0) {
-            mpp_err("invalid fps cfg [number:denorm:flex]: in [%d:%d:%d] out [%d:%d:%d]\n",
-                    dst->fps_in_num, dst->fps_in_denorm, dst->fps_in_flex,
-                    dst->fps_out_num, dst->fps_out_denorm, dst->fps_out_flex);
+        if (dst->fps_in_num < 0 || dst->fps_in_denom < 0 ||
+            dst->fps_out_num < 0 || dst->fps_out_denom < 0) {
+            mpp_err("invalid fps cfg [number:denom:flex]: in [%d:%d:%d] out [%d:%d:%d]\n",
+                    dst->fps_in_num, dst->fps_in_denom, dst->fps_in_flex,
+                    dst->fps_out_num, dst->fps_out_denom, dst->fps_out_flex);
             ret = MPP_ERR_VALUE;
         }
 
@@ -858,11 +864,102 @@ MPP_RET mpp_enc_proc_tune_cfg(MppEncFineTuneCfg *dst, MppEncFineTuneCfg *src)
 
         if (dst->scene_mode < MPP_ENC_SCENE_MODE_DEFAULT ||
             dst->scene_mode >= MPP_ENC_SCENE_MODE_BUTT) {
-            mpp_err("invalid scene mode %d not in range [%d:%d]\n", dst->scene_mode,
+            mpp_err("invalid scene mode %d not in range [%d, %d]\n", dst->scene_mode,
                     MPP_ENC_SCENE_MODE_DEFAULT, MPP_ENC_SCENE_MODE_BUTT - 1);
             ret = MPP_ERR_VALUE;
         }
 
+        if (change & MPP_ENC_TUNE_CFG_CHANGE_DEBLUR_EN)
+            dst->deblur_en = src->deblur_en;
+
+        if (change & MPP_ENC_TUNE_CFG_CHANGE_DEBLUR_STR)
+            dst->deblur_str = src->deblur_str;
+
+        if (dst->deblur_str < 0 || dst->deblur_str > 7) {
+            mpp_err("invalid deblur strength not in range [0, 7]\n");
+            ret = MPP_ERR_VALUE;
+        }
+
+        if (change & MPP_ENC_TUNE_CFG_CHANGE_ANTI_FLICKER_STR)
+            dst->anti_flicker_str = src->anti_flicker_str;
+
+        if (dst->anti_flicker_str < 0 || dst->anti_flicker_str > 3) {
+            mpp_err("invalid anti_flicker_str not in range [0 : 3]\n");
+            ret = MPP_ERR_VALUE;
+        }
+
+        if (change & MPP_ENC_TUNE_CFG_CHANGE_ATR_STR_I)
+            dst->atr_str_i = src->atr_str_i;
+
+        if (dst->atr_str_i < 0 || dst->atr_str_i > 3) {
+            mpp_err("invalid atr_str not in range [0 : 3]\n");
+            ret = MPP_ERR_VALUE;
+        }
+
+        if (change & MPP_ENC_TUNE_CFG_CHANGE_ATR_STR_P)
+            dst->atr_str_p = src->atr_str_p;
+
+        if (dst->atr_str_p < 0 || dst->atr_str_p > 3) {
+            mpp_err("invalid atr_str not in range [0 : 3]\n");
+            ret = MPP_ERR_VALUE;
+        }
+
+        if (change & MPP_ENC_TUNE_CFG_CHANGE_ATL_STR)
+            dst->atl_str = src->atl_str;
+
+        if (dst->atl_str < 0 || dst->atl_str > 3) {
+            mpp_err("invalid atr_str not in range [0 : 3]\n");
+            ret = MPP_ERR_VALUE;
+        }
+
+        if (change & MPP_ENC_TUNE_CFG_CHANGE_SAO_STR_I)
+            dst->sao_str_i = src->sao_str_i;
+
+        if (dst->sao_str_i < 0 || dst->sao_str_i > 3) {
+            mpp_err("invalid atr_str not in range [0 : 3]\n");
+            ret = MPP_ERR_VALUE;
+        }
+
+        if (change & MPP_ENC_TUNE_CFG_CHANGE_SAO_STR_P)
+            dst->sao_str_p = src->sao_str_p;
+
+        if (dst->sao_str_p < 0 || dst->sao_str_p > 3) {
+            mpp_err("invalid atr_str not in range [0 : 3]\n");
+            ret = MPP_ERR_VALUE;
+        }
+
+        if (change & MPP_ENC_TUNE_CFG_CHANGE_LAMBDA_IDX_I)
+            dst->lambda_idx_i = src->lambda_idx_i;
+
+        if (dst->lambda_idx_i < 0 || dst->lambda_idx_i > 8) {
+            mpp_err("invalid lambda idx i not in range [0, 8]\n");
+            ret = MPP_ERR_VALUE;
+        }
+
+        if (change & MPP_ENC_TUNE_CFG_CHANGE_LAMBDA_IDX_P)
+            dst->lambda_idx_p = src->lambda_idx_p;
+
+        if (dst->lambda_idx_p < 0 || dst->lambda_idx_p > 8) {
+            mpp_err("invalid lambda idx i not in range [0, 8]\n");
+            ret = MPP_ERR_VALUE;
+        }
+
+        if (change & MPP_ENC_TUNE_CFG_CHANGE_RC_CONTAINER)
+            dst->rc_container = src->rc_container;
+
+        if (dst->rc_container < 0 || dst->rc_container > 2) {
+            mpp_err("invalid rc_container %d not in range [0, 2]\n", dst->rc_container);
+            ret = MPP_ERR_VALUE;
+        }
+
+        if (change & MPP_ENC_TUNE_CFG_CHANGE_VMAF_OPT)
+            dst->vmaf_opt = src->vmaf_opt;
+
+        if (dst->vmaf_opt < 0 || dst->vmaf_opt > 1) {
+            mpp_err("invalid vmaf_opt %d not in range [0, 1]\n", dst->vmaf_opt);
+            ret = MPP_ERR_VALUE;
+        }
+
         dst->change |= change;
 
         if (ret) {
@@ -1132,6 +1229,7 @@ static const char *name_of_rc_mode[] = {
     "cbr",
     "fixqp",
     "avbr",
+    "smtrc"
 };
 
 static void update_rc_cfg_log(MppEncImpl *impl, const char* fmt, ...)
@@ -1217,6 +1315,9 @@ static void set_rc_cfg(RcCfg *cfg, MppEncCfgSet *cfg_set)
     case MPP_ENC_RC_MODE_FIXQP: {
         cfg->mode = RC_FIXQP;
     } break;
+    case MPP_ENC_RC_MODE_SMTRC: {
+        cfg->mode = RC_SMT;
+    } break;
     default : {
         cfg->mode = RC_AVBR;
     } break;
@@ -1224,10 +1325,10 @@ static void set_rc_cfg(RcCfg *cfg, MppEncCfgSet *cfg_set)
 
     cfg->fps.fps_in_flex    = rc->fps_in_flex;
     cfg->fps.fps_in_num     = rc->fps_in_num;
-    cfg->fps.fps_in_denorm  = rc->fps_in_denorm;
+    cfg->fps.fps_in_denom  = rc->fps_in_denom;
     cfg->fps.fps_out_flex   = rc->fps_out_flex;
     cfg->fps.fps_out_num    = rc->fps_out_num;
-    cfg->fps.fps_out_denorm = rc->fps_out_denorm;
+    cfg->fps.fps_out_denom = rc->fps_out_denom;
     cfg->igop               = rc->gop;
     cfg->max_i_bit_prop     = rc->max_i_prop;
     cfg->min_i_bit_prop     = rc->min_i_prop;
@@ -1237,6 +1338,7 @@ static void set_rc_cfg(RcCfg *cfg, MppEncCfgSet *cfg_set)
     cfg->bps_max    = rc->bps_max;
     cfg->bps_min    = rc->bps_min;
     cfg->scene_mode = cfg_set->tune.scene_mode;
+    cfg->rc_container = cfg_set->tune.rc_container;
 
     cfg->hier_qp_cfg.hier_qp_en = rc->hier_qp_en;
     memcpy(cfg->hier_qp_cfg.hier_frame_num, rc->hier_frame_num, sizeof(rc->hier_frame_num));
@@ -1303,7 +1405,7 @@ static void set_rc_cfg(RcCfg *cfg, MppEncCfgSet *cfg_set)
 
     if (info->st_gop) {
         cfg->vgop = info->st_gop;
-        if (cfg->vgop >= rc->fps_out_num / rc->fps_out_denorm &&
+        if (cfg->vgop >= rc->fps_out_num / rc->fps_out_denom &&
             cfg->vgop < cfg->igop ) {
             cfg->gop_mode = SMART_P;
             if (!cfg->vi_quality_delta)
@@ -1317,9 +1419,9 @@ static void set_rc_cfg(RcCfg *cfg, MppEncCfgSet *cfg_set)
                 name_of_rc_mode[cfg->mode],
                 rc->bps_min, rc->bps_target, rc->bps_max,
                 cfg->fps.fps_in_flex ? "flex" : "fix",
-                cfg->fps.fps_in_num, cfg->fps.fps_in_denorm,
+                cfg->fps.fps_in_num, cfg->fps.fps_in_denom,
                 cfg->fps.fps_out_flex ? "flex" : "fix",
-                cfg->fps.fps_out_num, cfg->fps.fps_out_denorm,
+                cfg->fps.fps_out_num, cfg->fps.fps_out_denom,
                 cfg->igop, cfg->vgop);
     }
 }
@@ -1437,6 +1539,7 @@ static MPP_RET mpp_enc_check_pkt_buf(MppEncImpl *enc)
 
         mpp_assert(size);
         mpp_buffer_get(mpp->mPacketGroup, &buffer, size);
+        mpp_buffer_attach_dev(buffer, enc->dev);
         mpp_assert(buffer);
         enc->pkt_buf = buffer;
         pkt->data   = mpp_buffer_get_ptr(buffer);
@@ -1526,6 +1629,86 @@ static void mpp_enc_rc_info_backup(MppEncImpl *enc, EncAsyncTaskInfo *task)
     enc->rc_info_prev = task->rc.info;
 }
 
+static MPP_RET mpp_enc_force_pskip_check(Mpp *mpp, EncAsyncTaskInfo *task)
+{
+    MppEncImpl *enc = (MppEncImpl *)mpp->mEnc;
+    EncRcTask *rc_task = &task->rc;
+    EncCpbStatus *cpb = &rc_task->cpb;
+    EncFrmStatus *frm = &rc_task->frm;
+    MppEncCpbInfo cpb_info;
+    RK_U32 max_tid = 0;
+    MPP_RET ret = MPP_OK;
+
+    mpp_enc_refs_get_cpb_info(enc->refs, &cpb_info);
+    max_tid = cpb_info.max_st_tid;
+
+    if (frm->is_idr) {
+        enc_dbg_detail("task %d, IDR frames should not be set as pskip frames", frm->seq_idx);
+        ret = MPP_NOK;
+    }
+    if (frm->is_lt_ref) {
+        enc_dbg_detail("task %d, LTR frames should not be set as pskip frames", frm->seq_idx);
+        ret = MPP_NOK;
+    }
+    if (cpb->curr.temporal_id != max_tid) {
+        enc_dbg_detail("task %d, Only top-layer frames can be set as pskip frames in TSVC mode", frm->seq_idx);
+        ret = MPP_NOK;
+    }
+    if (cpb->curr.ref_mode != REF_TO_PREV_REF_FRM) {
+        enc_dbg_detail("task %d, Only frames with reference mode set to prev_ref can be set as pskip frames", frm->seq_idx);
+        ret = MPP_NOK;
+    }
+
+    return ret;
+}
+
+static MPP_RET mpp_enc_force_pskip(Mpp *mpp, EncAsyncTaskInfo *task)
+{
+    MppEncImpl *enc = (MppEncImpl *)mpp->mEnc;
+    EncImpl impl = enc->impl;
+    MppEncRefFrmUsrCfg *frm_cfg = &task->usr;
+    EncRcTask *rc_task = &task->rc;
+    EncCpbStatus *cpb = &rc_task->cpb;
+    EncFrmStatus *frm = &rc_task->frm;
+    HalEncTask *hal_task = &task->task;
+    MPP_RET ret = MPP_OK;
+
+    enc_dbg_func("enter\n");
+
+    frm_cfg->force_pskip++;
+    frm_cfg->force_flag |= ENC_FORCE_PSKIP;
+
+    /* NOTE: in some condition the pskip should not happen */
+    mpp_enc_refs_set_usr_cfg(enc->refs, frm_cfg);
+
+    enc_dbg_detail("task %d enc proc dpb\n", frm->seq_idx);
+    mpp_enc_refs_get_cpb(enc->refs, cpb);
+
+    enc_dbg_frm_status("frm %d start ***********************************\n", cpb->curr.seq_idx);
+    ENC_RUN_FUNC2(enc_impl_proc_dpb, impl, hal_task, mpp, ret);
+
+    ret = mpp_enc_force_pskip_check(mpp, task);
+    if (ret) {
+        mpp_enc_refs_rollback(enc->refs);
+        frm_cfg->force_pskip--;
+        frm_cfg->force_flag &= ~ENC_FORCE_PSKIP;
+        return MPP_NOK;
+    }
+
+    enc_dbg_detail("task %d rc frame start\n", frm->seq_idx);
+    ENC_RUN_FUNC2(rc_frm_start, enc->rc_ctx, rc_task, mpp, ret);
+
+    enc_dbg_detail("task %d enc sw enc start\n", frm->seq_idx);
+    ENC_RUN_FUNC2(enc_impl_sw_enc, impl, hal_task, mpp, ret);
+
+    enc_dbg_detail("task %d rc frame end\n", frm->seq_idx);
+    ENC_RUN_FUNC2(rc_frm_end, enc->rc_ctx, rc_task, mpp, ret);
+
+TASK_DONE:
+    enc_dbg_func("leave\n");
+    return ret;
+}
+
 static void mpp_enc_add_sw_header(MppEncImpl *enc, HalEncTask *hal_task)
 {
     EncImpl impl = enc->impl;
@@ -1610,6 +1793,7 @@ static MPP_RET mpp_enc_normal(Mpp *mpp, EncAsyncTaskInfo *task)
     EncFrmStatus *frm = &rc_task->frm;
     HalEncTask *hal_task = &task->task;
     MPP_RET ret = MPP_OK;
+    EncAsyncStatus *status = &task->status;
 
     if (enc->support_hw_deflicker && enc->cfg.rc.debreath_en) {
         ret = mpp_enc_proc_two_pass(mpp, task);
@@ -1617,6 +1801,27 @@ static MPP_RET mpp_enc_normal(Mpp *mpp, EncAsyncTaskInfo *task)
             return ret;
     }
 
+    enc_dbg_detail("task %d check force pskip start\n", frm->seq_idx);
+    if (!status->check_frm_pskip) {
+        RK_S32 force_pskip = 0;
+        status->check_frm_pskip = 1;
+
+        if (mpp_frame_has_meta(enc->frame)) {
+            MppMeta frm_meta = mpp_frame_get_meta(enc->frame);
+            if (frm_meta)
+                mpp_meta_get_s32(frm_meta, KEY_INPUT_PSKIP, &force_pskip);
+        }
+
+        if (force_pskip == 1) {
+            frm->force_pskip = 1;
+            ret = mpp_enc_force_pskip((Mpp*)enc->mpp, task);
+            if (ret)
+                enc_dbg_detail("task %d set force pskip failed.", frm->seq_idx);
+            else
+                goto TASK_DONE;
+        }
+    }
+
     enc_dbg_detail("task %d enc proc dpb\n", frm->seq_idx);
     mpp_enc_refs_get_cpb(enc->refs, cpb);
 
@@ -2031,6 +2236,27 @@ static MPP_RET try_proc_low_deley_task(Mpp *mpp, EncAsyncTaskInfo *task, EncAsyn
     if (status->low_delay_again)
         goto GET_OUTPUT_TASK;
 
+    enc_dbg_detail("task %d check force pskip start\n", frm->seq_idx);
+    if (!status->check_frm_pskip) {
+        RK_S32 force_pskip = 0;
+        status->check_frm_pskip = 1;
+
+        if (mpp_frame_has_meta(enc->frame)) {
+            MppMeta frm_meta = mpp_frame_get_meta(enc->frame);
+            if (frm_meta)
+                mpp_meta_get_s32(frm_meta, KEY_INPUT_PSKIP, &force_pskip);
+        }
+
+        if (force_pskip == 1) {
+            frm->force_pskip = 1;
+            ret = mpp_enc_force_pskip((Mpp*)enc->mpp, task);
+            if (ret)
+                enc_dbg_detail("task %d set force pskip failed.", frm->seq_idx);
+            else
+                goto TASK_DONE;
+        }
+    }
+
     enc_dbg_detail("task %d enc proc dpb\n", frm->seq_idx);
     mpp_enc_refs_get_cpb(enc->refs, cpb);
 
@@ -2232,6 +2458,10 @@ static MPP_RET set_enc_info_to_packet(MppEncImpl *enc, HalEncTask *hal_task)
         /* frame type */
         mpp_meta_set_s32(meta, KEY_OUTPUT_INTRA,    frm->is_intra);
         mpp_meta_set_s32(meta, KEY_OUTPUT_PSKIP,    frm->force_pskip || is_pskip);
+        mpp_meta_set_s32(meta, KEY_ENC_BPS_RT, rc_task->info.rt_bits);
+
+        if (rc_task->info.frame_type == INTER_VI_FRAME)
+            mpp_meta_set_s32(meta, KEY_ENC_USE_LTR, rc_task->cpb.refr.lt_idx);
     }
     /* start qp and average qp */
     mpp_meta_set_s32(meta, KEY_ENC_START_QP,    rc_task->info.quality_target);
@@ -2598,6 +2828,7 @@ static MPP_RET check_async_pkt_buf(MppEncImpl *enc, EncAsyncTaskInfo *async)
 
         mpp_assert(size);
         mpp_buffer_get(mpp->mPacketGroup, &buffer, size);
+        mpp_buffer_attach_dev(buffer, enc->dev);
         mpp_assert(buffer);
         enc->pkt_buf = buffer;
         pkt->data   = mpp_buffer_get_ptr(buffer);
@@ -2835,7 +3066,28 @@ static MPP_RET try_get_async_task(MppEncImpl *enc, EncAsyncWait *wait)
     return ret;
 }
 
-static MPP_RET proc_async_task(MppEncImpl *enc)
+static MPP_RET try_proc_processing_task(MppEncImpl *enc, EncAsyncWait *wait)
+{
+    HalTaskHnd hnd = NULL;
+    EncAsyncTaskInfo *info = NULL;
+    MPP_RET ret = MPP_NOK;
+
+    ret = hal_task_get_hnd(enc->tasks, TASK_PROCESSING, &hnd);
+    if (ret)
+        return ret;
+
+    info = (EncAsyncTaskInfo *)hal_task_hnd_get_data(hnd);
+
+    mpp_assert(!info->status.enc_done);
+
+    enc_async_wait_task(enc, info);
+    hal_task_hnd_set_status(hnd, TASK_IDLE);
+    wait->task_hnd = 0;
+
+    return MPP_OK;
+}
+
+static MPP_RET proc_async_task(MppEncImpl *enc, EncAsyncWait *wait)
 {
     Mpp *mpp = (Mpp*)enc->mpp;
     EncImpl impl = enc->impl;
@@ -2854,6 +3106,40 @@ static MPP_RET proc_async_task(MppEncImpl *enc)
     if (hal_task->flags.drop_by_fps)
         goto SEND_TASK_INFO;
 
+    if (!status->check_frm_pskip) {
+        RK_S32 force_pskip = 0;
+        status->check_frm_pskip = 1;
+
+        if (mpp_frame_has_meta(hal_task->frame)) {
+            MppMeta frm_meta = mpp_frame_get_meta(hal_task->frame);
+            if (frm_meta)
+                mpp_meta_get_s32(frm_meta, KEY_INPUT_PSKIP, &force_pskip);
+        }
+
+        if (force_pskip == 1) {
+            frm->force_pskip = 1;
+            ret = mpp_enc_force_pskip((Mpp*)enc->mpp, async);
+
+            if (ret)
+                enc_dbg_detail("task %d set force pskip failed.", frm->seq_idx);
+            else
+                goto SEND_TASK_INFO;
+        }
+    }
+
+    if (enc->support_hw_deflicker && enc->cfg.rc.debreath_en) {
+        bool two_pass_en = mpp_enc_refs_next_frm_is_intra(enc->refs);
+
+        if (two_pass_en) {
+            /* wait all tasks done */
+            while (MPP_OK == try_proc_processing_task(enc, wait));
+
+            ret = mpp_enc_proc_two_pass(mpp, async);
+            if (ret)
+                return ret;
+        }
+    }
+
     enc_dbg_detail("task %d enc proc dpb\n", seq_idx);
     mpp_enc_refs_get_cpb(enc->refs, cpb);
 
@@ -2949,7 +3235,7 @@ static MPP_RET enc_async_wait_task(MppEncImpl *enc, EncAsyncTaskInfo *info)
     MppPacket pkt = hal_task->packet;
     MPP_RET ret = MPP_OK;
 
-    if (hal_task->flags.drop_by_fps)
+    if (hal_task->flags.drop_by_fps || hal_task->frm_cfg->force_pskip)
         goto TASK_DONE;
 
     enc_dbg_detail("task %d hal wait\n", frm->seq_idx);
@@ -3040,8 +3326,6 @@ void *mpp_enc_async_thread(void *data)
         // 1. process user control and reset flag
         if (enc->cmd_send != enc->cmd_recv || enc->reset_flag) {
             mpp_list *frm_in = mpp->mFrmIn;
-            HalTaskHnd hnd = NULL;
-            EncAsyncTaskInfo *info = NULL;
 
             /* when process cmd or reset hold frame input */
             frm_in->lock();
@@ -3049,15 +3333,7 @@ void *mpp_enc_async_thread(void *data)
             enc_dbg_detail("ctrl proc %d cmd %08x\n", enc->cmd_recv, enc->cmd);
 
             // wait all tasks done
-            while (MPP_OK == hal_task_get_hnd(enc->tasks, TASK_PROCESSING, &hnd)) {
-                info = (EncAsyncTaskInfo *)hal_task_hnd_get_data(hnd);
-
-                mpp_assert(!info->status.enc_done);
-
-                enc_async_wait_task(enc, info);
-                hal_task_hnd_set_status(hnd, TASK_IDLE);
-                wait.task_hnd = 0;
-            }
+            while (MPP_OK == try_proc_processing_task(enc, &wait));
 
             if (enc->cmd_send != enc->cmd_recv) {
                 sem_wait(&enc->cmd_start);
@@ -3111,28 +3387,17 @@ void *mpp_enc_async_thread(void *data)
         ret = try_get_async_task(enc, &wait);
         enc_dbg_detail("try_get_async_task ret %d\n", ret);
         if (ret) {
-            HalTaskHnd hnd = NULL;
-            EncAsyncTaskInfo *info = NULL;
-
-            hal_task_get_hnd(enc->tasks, TASK_PROCESSING, &hnd);
-            if (hnd) {
-                info = (EncAsyncTaskInfo *)hal_task_hnd_get_data(hnd);
-
-                mpp_assert(!info->status.enc_done);
-
-                enc_async_wait_task(enc, info);
-                hal_task_hnd_set_status(hnd, TASK_IDLE);
-                wait.task_hnd = 0;
-            }
-
+            try_proc_processing_task(enc, &wait);
             continue;
         }
 
         mpp_assert(enc->async);
         mpp_assert(enc->async->task.valid);
 
-        proc_async_task(enc);
+        proc_async_task(enc, &wait);
     }
+    /* wait all task done */
+    while (MPP_OK == try_proc_processing_task(enc, &wait));
 
     enc_dbg_func("thread finish\n");
 
diff --git a/mpp/codec/mpp_enc_v2.cpp b/mpp/codec/mpp_enc_v2.cpp
index 1f93448b1..eb6e9437b 100644
--- a/mpp/codec/mpp_enc_v2.cpp
+++ b/mpp/codec/mpp_enc_v2.cpp
@@ -119,7 +119,7 @@ MPP_RET mpp_enc_init_v2(MppEnc *enc, MppEncInitCfg *cfg)
 
     {
         // create header packet storage
-        size_t size = SZ_1K;
+        size_t size = SZ_4K;
         p->hdr_buf = mpp_calloc_size(void, size);
 
         mpp_packet_init(&p->hdr_pkt, p->hdr_buf, size);
diff --git a/mpp/codec/mpp_rc.cpp b/mpp/codec/mpp_rc.cpp
index 39d796290..4305e2282 100644
--- a/mpp/codec/mpp_rc.cpp
+++ b/mpp/codec/mpp_rc.cpp
@@ -88,7 +88,7 @@ void mpp_data_update(MppData *p, RK_S32 val)
         p->len++;
 }
 
-RK_S32 mpp_data_avg(MppData *p, RK_S32 len, RK_S32 num, RK_S32 denorm)
+RK_S32 mpp_data_avg(MppData *p, RK_S32 len, RK_S32 num, RK_S32 denom)
 {
     mpp_assert(p);
 
@@ -102,7 +102,7 @@ RK_S32 mpp_data_avg(MppData *p, RK_S32 len, RK_S32 num, RK_S32 denorm)
     if (len < 0 || len > p->len)
         len = p->len;
 
-    if (num == denorm) {
+    if (num == denom) {
         i = len;
         while (i--) {
             if (pos)
@@ -114,9 +114,9 @@ RK_S32 mpp_data_avg(MppData *p, RK_S32 len, RK_S32 num, RK_S32 denorm)
         }
     } else {
         /* This case is not used so far, but may be useful in the future */
-        mpp_assert(num > denorm);
+        mpp_assert(num > denom);
         RK_S32 acc_num = num;
-        RK_S32 acc_denorm = denorm;
+        RK_S32 acc_denom = denom;
 
         i = len - 1;
         sum = p->val[--pos];
@@ -126,9 +126,9 @@ RK_S32 mpp_data_avg(MppData *p, RK_S32 len, RK_S32 num, RK_S32 denorm)
             else
                 pos = p->len - 1;
 
-            sum += p->val[pos] * acc_num / acc_denorm;
+            sum += p->val[pos] * acc_num / acc_denom;
             acc_num *= num;
-            acc_denorm *= denorm;
+            acc_denom *= denom;
         }
     }
     return DIV(sum, len);
@@ -155,7 +155,7 @@ void mpp_pid_set_param(MppPIDCtx *ctx, RK_S32 coef_p, RK_S32 coef_i, RK_S32 coef
                   ctx, coef_p, coef_i, coef_d, div, len);
 }
 
-void mpp_pid_update(MppPIDCtx *ctx, RK_S32 val)
+void mpp_pid_update(MppPIDCtx *ctx, RK_S32 val, RK_S32 is_reset)
 {
     mpp_rc_dbg_rc("RC: pid ctx %p update val %d\n", ctx, val);
     mpp_rc_dbg_rc("RC: pid ctx %p before update P %d I %d D %d\n", ctx, ctx->p, ctx->i, ctx->d);
@@ -169,7 +169,7 @@ void mpp_pid_update(MppPIDCtx *ctx, RK_S32 val)
     /*
      * pid control is a short time control, it needs periodically reset
      */
-    if (ctx->count >= ctx->len)
+    if (is_reset && ctx->count >= ctx->len)
         mpp_pid_reset(ctx);
 }
 
diff --git a/mpp/codec/rc/rc.cpp b/mpp/codec/rc/rc.cpp
index faf691cd9..780fc1553 100644
--- a/mpp/codec/rc/rc.cpp
+++ b/mpp/codec/rc/rc.cpp
@@ -145,12 +145,12 @@ MPP_RET rc_frm_check_drop(RcCtx ctx, EncRcTask *task)
     } else {
         RcFpsCfg *cfg = &p->fps;
         RK_S32 frm_cnt  = p->frm_cnt;
-        RK_S32 rate_in  = cfg->fps_in_num * cfg->fps_out_denorm;
-        RK_S32 rate_out = cfg->fps_out_num * cfg->fps_in_denorm;
+        RK_S32 rate_in  = cfg->fps_in_num * cfg->fps_out_denom;
+        RK_S32 rate_out = cfg->fps_out_num * cfg->fps_in_denom;
         RK_S32 drop = 0;
 
-        mpp_assert(cfg->fps_in_denorm >= 1);
-        mpp_assert(cfg->fps_out_denorm >= 1);
+        mpp_assert(cfg->fps_in_denom >= 1);
+        mpp_assert(cfg->fps_out_denom >= 1);
         mpp_assert(rate_in >= rate_out);
 
         // frame counter is inited to (rate_in - rate_out)  to encode first frame
diff --git a/mpp/codec/rc/rc_base.cpp b/mpp/codec/rc/rc_base.cpp
index 300a02fc0..49b871abf 100644
--- a/mpp/codec/rc/rc_base.cpp
+++ b/mpp/codec/rc/rc_base.cpp
@@ -165,7 +165,7 @@ RK_S32 mpp_data_mean_v2(MppDataV2 *p)
     return mean;
 }
 
-RK_S32 mpp_data_sum_with_ratio_v2(MppDataV2 *p, RK_S32 len, RK_S32 num, RK_S32 denorm)
+RK_S32 mpp_data_sum_with_ratio_v2(MppDataV2 *p, RK_S32 len, RK_S32 num, RK_S32 denom)
 {
     mpp_assert(p);
 
@@ -175,18 +175,18 @@ RK_S32 mpp_data_sum_with_ratio_v2(MppDataV2 *p, RK_S32 len, RK_S32 num, RK_S32 d
 
     mpp_assert(len <= p->size);
 
-    if (num == denorm) {
+    if (num == denom) {
         for (i = 0; i < len; i++)
             sum += *data++;
     } else {
         // NOTE: use 64bit to avoid 0 in 32bit
         RK_S64 acc_num = 1;
-        RK_S64 acc_denorm = 1;
+        RK_S64 acc_denom = 1;
 
         for (i = 0; i < len; i++) {
-            sum += p->val[i] * acc_num / acc_denorm;
+            sum += p->val[i] * acc_num / acc_denom;
             acc_num *= num;
-            acc_denorm *= denorm;
+            acc_denom *= denom;
         }
     }
 
diff --git a/mpp/codec/rc/rc_base.h b/mpp/codec/rc/rc_base.h
index 931ff42bb..06dcbaf74 100644
--- a/mpp/codec/rc/rc_base.h
+++ b/mpp/codec/rc/rc_base.h
@@ -60,7 +60,7 @@ void mpp_data_update_v2(MppDataV2 *p, RK_S32 val);
 RK_S32 mpp_data_sum_v2(MppDataV2 *p);
 RK_S32 mpp_data_mean_v2(MppDataV2 *p);
 RK_S32 mpp_data_get_pre_val_v2(MppDataV2 *p, RK_S32 idx);
-RK_S32 mpp_data_sum_with_ratio_v2(MppDataV2 *p, RK_S32 len, RK_S32 num, RK_S32 denorm);
+RK_S32 mpp_data_sum_with_ratio_v2(MppDataV2 *p, RK_S32 len, RK_S32 num, RK_S32 denom);
 
 #ifdef __cplusplus
 }
diff --git a/mpp/codec/rc/rc_ctx.h b/mpp/codec/rc/rc_ctx.h
index 6a8d4033e..0fc1ffc4b 100644
--- a/mpp/codec/rc/rc_ctx.h
+++ b/mpp/codec/rc/rc_ctx.h
@@ -52,9 +52,14 @@ typedef struct RcModelV2Ctx_t {
     MppDataV2       *pre_i_mean_qp;
     MppDataV2       *madi;
     MppDataV2       *madp;
+    MppDataV2       *motion_level;
+    MppDataV2       *complex_level;
 
     RK_S32          target_bps;
     RK_S32          pre_target_bits;
+    RK_S32          pre_target_bits_fix;
+    RK_S64          pre_target_bits_fix_count;
+    RK_S64          pre_real_bits_count;
     RK_S32          pre_real_bits;
     RK_S32          frm_bits_thr;
     RK_S32          ins_bps;
diff --git a/mpp/codec/rc/rc_model_v2.c b/mpp/codec/rc/rc_model_v2.c
index f4205f0e7..370a66672 100644
--- a/mpp/codec/rc/rc_model_v2.c
+++ b/mpp/codec/rc/rc_model_v2.c
@@ -30,6 +30,7 @@
 #define I_WINDOW_LEN 2
 #define P_WINDOW1_LEN 5
 #define P_WINDOW2_LEN 8
+#define MAX_BIT_COUNT_VALUE 1000000000000000
 
 static const RK_S32 max_i_delta_qp[51] = {
     640, 640, 640, 640, 640, 640, 640, 640, 640, 640, 640, 640, 640, 640,
@@ -129,6 +130,14 @@ MPP_RET bits_model_param_deinit(RcModelV2Ctx *ctx)
         mpp_data_deinit_v2(ctx->gop_bits);
         ctx->gop_bits = NULL;
     }
+    if (ctx->motion_level != NULL) {
+        mpp_data_deinit_v2(ctx->motion_level);
+        ctx->motion_level = NULL;
+    }
+    if (ctx->complex_level != NULL) {
+        mpp_data_deinit_v2(ctx->complex_level);
+        ctx->complex_level = NULL;
+    }
     rc_dbg_func("leave %p\n", ctx);
     return MPP_OK;
 }
@@ -137,7 +146,8 @@ MPP_RET bits_model_param_init(RcModelV2Ctx *ctx)
 {
     RK_S32 gop_len = ctx->usr_cfg.igop;
     RcFpsCfg *fps = &ctx->usr_cfg.fps;
-    RK_U32 stat_len = fps->fps_out_num * ctx->usr_cfg.stats_time / fps->fps_out_denorm;
+    RK_S32 mad_len = 10;
+    RK_U32 stat_len = fps->fps_out_num * ctx->usr_cfg.stats_time / fps->fps_out_denom;
     stat_len = stat_len ? stat_len : 1;
 
     bits_model_param_deinit(ctx);
@@ -210,6 +220,19 @@ MPP_RET bits_model_param_init(RcModelV2Ctx *ctx)
             return MPP_ERR_MALLOC;
         }
     }
+
+    mpp_data_init_v2(&ctx->motion_level, mad_len, 0);
+    if (ctx->motion_level == NULL) {
+        mpp_err("motion_level init fail mad_len %d\n", mad_len);
+        return MPP_ERR_MALLOC;
+    }
+
+    mpp_data_init_v2(&ctx->complex_level, mad_len, 0);
+    if (ctx->complex_level == NULL) {
+        mpp_err("complex_level init fail mad_len %d\n", mad_len);
+        return MPP_ERR_MALLOC;
+    }
+
     return MPP_OK;
 }
 
@@ -431,6 +454,7 @@ MPP_RET bits_model_alloc(RcModelV2Ctx *ctx, EncRcTaskInfo *cfg, RK_S64 total_bit
     RK_S32 vi_scale = ctx->vi_scale;
     RK_S32 alloc_bits = 0;
     RK_S32 super_bit_thr = 0x7fffffff;
+    RK_S64 total_bits_fix = total_bits;
 
     ctx->i_scale = 80 * ctx->i_sumbits / (2 * ctx->p_sumbits);
     i_scale = ctx->i_scale;
@@ -519,6 +543,10 @@ MPP_RET bits_model_alloc(RcModelV2Ctx *ctx, EncRcTaskInfo *cfg, RK_S64 total_bit
 
     ctx->cur_super_thd = super_bit_thr;
     cfg->bit_target = alloc_bits;
+    if (cfg->frame_type == INTRA_FRAME)
+        cfg->bit_target_fix = total_bits_fix * 240 / (240 + 16 * (gop_len - 1));
+    else
+        cfg->bit_target_fix = total_bits_fix * 16 / (240 + 16 * (gop_len - 1));
 
     mpp_assert(alloc_bits);
 
@@ -613,6 +641,13 @@ MPP_RET calc_cbr_ratio(void *ctx, EncRcTaskInfo *cfg)
 
     mpp_assert(target_bps > 0);
 
+    p->pre_real_bits_count = p->pre_real_bits_count + pre_real_bits;
+    p->pre_target_bits_fix_count = p->pre_target_bits_fix_count + p->pre_target_bits_fix;
+    if (p->pre_real_bits_count > MAX_BIT_COUNT_VALUE || p->pre_target_bits_fix_count > MAX_BIT_COUNT_VALUE) {
+        p->pre_real_bits_count = 0;
+        p->pre_target_bits_fix_count = 0;
+    }
+
     if (pre_target_bits > pre_real_bits)
         bit_diff_ratio = 52 * (pre_real_bits - pre_target_bits) / pre_target_bits;
     else
@@ -1134,16 +1169,16 @@ MPP_RET bits_model_init(RcModelV2Ctx *ctx)
     ctx->target_bps = ctx->usr_cfg.bps_target;
 
     if (gop_len >= 1)
-        gop_bits = (RK_S64)gop_len * target_bps * fps->fps_out_denorm;
+        gop_bits = (RK_S64)gop_len * target_bps * fps->fps_out_denom;
     else
-        gop_bits = (RK_S64)fps->fps_out_num * target_bps * fps->fps_out_denorm;
+        gop_bits = (RK_S64)fps->fps_out_num * target_bps * fps->fps_out_denom;
 
     ctx->gop_total_bits = gop_bits / fps->fps_out_num;
-    ctx->bit_per_frame = target_bps * fps->fps_out_denorm / fps->fps_out_num;
+    ctx->bit_per_frame = target_bps * fps->fps_out_denom / fps->fps_out_num;
     ctx->watl_thrd = 3 * target_bps;
     ctx->stat_watl = ctx->watl_thrd  >> 3;
     ctx->watl_base = ctx->stat_watl;
-    ctx->last_fps = fps->fps_out_num / fps->fps_out_denorm;
+    ctx->last_fps = fps->fps_out_num / fps->fps_out_denom;
 
     rc_dbg_rc("gop %d total bit %lld per_frame %d statistics time %d second\n",
               ctx->usr_cfg.igop, ctx->gop_total_bits, ctx->bit_per_frame,
@@ -1324,6 +1359,9 @@ MPP_RET rc_model_v2_init(void *ctx, RcCfg *cfg)
     rc_dbg_func("enter %p\n", ctx);
 
     memcpy(&p->usr_cfg, cfg, sizeof(RcCfg));
+    rc_dbg_rc("init rc param: fqp %d:%d:%d:%d\n", cfg->fqp_min_i, cfg->fqp_max_i,
+              cfg->fqp_min_p, cfg->fqp_max_p);
+
     bits_model_init(p);
 
     rc_dbg_func("leave %p\n", ctx);
@@ -1472,6 +1510,50 @@ static RK_S32 cal_first_i_start_qp(RK_S32 target_bit, RK_U32 total_mb)
     return qscale2qp[index];
 }
 
+static RK_S32 derive_min_qp_from_complexity(RcModelV2Ctx *ctx, EncRcTaskInfo *info, RK_U32 is_intra)
+{
+    RcCfg *usr_cfg = &ctx->usr_cfg;
+    RcMode rc_mode = usr_cfg->mode;
+    RK_S32 qp_min = info->quality_min;
+    RK_S32 fqp_min_i = usr_cfg->fqp_min_i;
+    RK_S32 fqp_min_p = usr_cfg->fqp_min_p;
+    RK_S32 cplx = mpp_data_sum_v2(ctx->complex_level);
+    RK_S32 md = mpp_data_sum_v2(ctx->motion_level);
+    RK_S32 md3 = mpp_data_get_pre_val_v2(ctx->motion_level, 0) +
+                 mpp_data_get_pre_val_v2(ctx->motion_level, 1) +
+                 mpp_data_get_pre_val_v2(ctx->motion_level, 2);
+
+    if (RC_AVBR == rc_mode || RC_VBR == rc_mode || RC_CBR == rc_mode) {
+        if (md >= 700) {
+            qp_min = is_intra ? fqp_min_i : fqp_min_p;
+            if (md >= 1400)
+                qp_min += md3 > 300 ? 3 : 2;
+            else
+                qp_min += md3 > 300 ? 2 : 1;
+
+            if (cplx >= 15)
+                qp_min++;
+        } else if (RC_CBR != rc_mode) {
+            if (md > 100) {
+                if (cplx >= 16)
+                    qp_min = (is_intra ? fqp_min_i : fqp_min_p) + 1;
+                else if (cplx >= 10)
+                    qp_min = (is_intra ? fqp_min_i : fqp_min_p) + 0;
+            } else {
+                qp_min = (is_intra ? fqp_min_i : fqp_min_p);
+                qp_min += (cplx >= 15) ? 3 : (cplx >= 10) ? 2 : (cplx >= 5) ? 1 : 0;
+            }
+        }
+
+        qp_min = mpp_clip(qp_min, info->quality_min, info->quality_max);
+
+        rc_dbg_rc("frame %d complex_level %d motion_level %d md3 %d qp_min %d\n",
+                  ctx->frm_num, cplx, md, md3, qp_min);
+    }
+
+    return qp_min;
+}
+
 MPP_RET rc_model_v2_hal_start(void *ctx, EncRcTask *task)
 {
     RcModelV2Ctx *p = (RcModelV2Ctx *)ctx;
@@ -1489,7 +1571,6 @@ MPP_RET rc_model_v2_hal_start(void *ctx, EncRcTask *task)
     RK_S32 quality_target = info->quality_target;
 
     rc_dbg_func("enter p %p task %p\n", p, task);
-
     rc_dbg_rc("seq_idx %d intra %d\n", frm->seq_idx, frm->is_intra);
 
     if (force->force_flag & ENC_RC_FORCE_QP) {
@@ -1500,12 +1581,24 @@ MPP_RET rc_model_v2_hal_start(void *ctx, EncRcTask *task)
         return MPP_OK;
     }
 
-    if (usr_cfg->mode == RC_FIXQP)
+    if (usr_cfg->mode == RC_FIXQP) {
+        RK_S32 i_quality_delta = usr_cfg->i_quality_delta;
+
+        if (frm->is_intra && i_quality_delta)
+            p->start_qp = quality_target - i_quality_delta;
+        else
+            p->start_qp = quality_target;
+
+        info->quality_target = p->start_qp;
+
         return MPP_OK;
+    }
 
     /* setup quality parameters */
     if (p->first_frm_flg && frm->is_intra) {
         RK_S32 i_quality_delta = usr_cfg->i_quality_delta;
+        p->pre_target_bits_fix_count = 0;
+        p->pre_real_bits_count = 0;
 
         if (info->quality_target < 0) {
             if (info->bit_target) {
@@ -1531,12 +1624,18 @@ MPP_RET rc_model_v2_hal_start(void *ctx, EncRcTask *task)
     } else {
         RK_S32 qp_scale = p->cur_scale_qp + p->next_ratio;
         RK_S32 start_qp = 0;
+        RK_S32 qpmin = derive_min_qp_from_complexity(p, info, frm->is_intra);
 
         if (frm->is_intra && !frm->is_i_refresh) {
             RK_S32 i_quality_delta = usr_cfg->i_quality_delta;
+            RK_S32 qp_scale_t = qp_scale =
+                                    mpp_clip(qp_scale, (info->quality_min << 6), (info->quality_max << 6));
 
-            qp_scale = mpp_clip(qp_scale, (info->quality_min << 6), (info->quality_max << 6));
-            start_qp = ((p->pre_i_qp + ((qp_scale + p->next_i_ratio) >> 6)) >> 1);
+            qp_scale_t = (qp_scale + p->next_i_ratio) >> 6;
+            if (qp_scale_t >= 35 && p->pre_i_qp <= 33)
+                start_qp = (p->pre_i_qp * 307 + qp_scale_t * 717) >> 10;
+            else
+                start_qp = (p->pre_i_qp + qp_scale_t) >> 1;
 
             if (i_quality_delta) {
                 RK_U32 index = mpp_clip(mpp_data_mean_v2(p->madi) / 4, 0, 7);
@@ -1550,11 +1649,12 @@ MPP_RET rc_model_v2_hal_start(void *ctx, EncRcTask *task)
                           usr_cfg->i_quality_delta, max_ip_delta,
                           start_qp - i_quality_delta, p->reenc_cnt);
 
-                if (!p->reenc_cnt) {
-                    start_qp -= i_quality_delta;
-                }
+                //if (!p->reenc_cnt) {
+                start_qp -= i_quality_delta;
+                //}
             }
 
+            start_qp = mpp_clip(start_qp, qpmin, usr_cfg->fqp_max_i);
             start_qp = mpp_clip(start_qp, info->quality_min, info->quality_max);
             p->start_qp = start_qp;
 
@@ -1563,13 +1663,12 @@ MPP_RET rc_model_v2_hal_start(void *ctx, EncRcTask *task)
                 if (p->usr_cfg.debreath_cfg.enable) {
                     calc_debreath_qp(ctx);
                 }
-            } else {
-                p->cur_scale_qp = qp_scale;
             }
 
             p->gop_frm_cnt = 0;
             p->gop_qp_sum = 0;
         } else {
+            qp_scale = mpp_clip(qp_scale, (qpmin << 6), (info->quality_max << 6));
             qp_scale = mpp_clip(qp_scale, (info->quality_min << 6), (info->quality_max << 6));
             p->cur_scale_qp = qp_scale;
             rc_dbg_rc("qp %d -> %d\n", p->start_qp, qp_scale >> 6);
@@ -1578,7 +1677,16 @@ MPP_RET rc_model_v2_hal_start(void *ctx, EncRcTask *task)
                 rc_dbg_rc("qp %d -> %d (vi)\n", p->start_qp, p->start_qp - usr_cfg->vi_quality_delta);
                 p->start_qp -= usr_cfg->vi_quality_delta;
             }
+            p->start_qp = mpp_clip(p->start_qp, qpmin, usr_cfg->fqp_max_p);
+        }
+        if (p->pre_target_bits_fix_count * 90 / 100 > p->pre_real_bits_count) {
+            p->start_qp = mpp_clip(p->start_qp, info->quality_min, 35);
+        } else if (p->pre_target_bits_fix_count * 100 / 100 > p->pre_real_bits_count) {
+            p->start_qp = mpp_clip(p->start_qp, info->quality_min, 37);
+        } else if (p->pre_target_bits_fix_count * 107 / 100 > p->pre_real_bits_count) {
+            p->start_qp = mpp_clip(p->start_qp, info->quality_min, 39);
         }
+        p->start_qp = mpp_clip(p->start_qp, qpmin, 51);
     }
 
     if (usr_cfg->hier_qp_cfg.hier_qp_en && !p->reenc_cnt) {
@@ -1695,6 +1803,10 @@ MPP_RET rc_model_v2_end(void *ctx, EncRcTask *task)
     if (usr_cfg->mode == RC_FIXQP)
         goto DONE;
 
+    rc_dbg_rc("motion_level %u, complex_level %u\n", cfg->motion_level, cfg->complex_level);
+    mpp_data_update_v2(p->motion_level, cfg->motion_level);
+    mpp_data_update_v2(p->complex_level, cfg->complex_level);
+    cfg->rt_bits = p->ins_bps;
     p->last_inst_bps = p->ins_bps;
     p->first_frm_flg = 0;
 
@@ -1712,6 +1824,7 @@ MPP_RET rc_model_v2_end(void *ctx, EncRcTask *task)
     p->scale_qp = p->cur_scale_qp;
     p->prev_md_prop = 0;
     p->pre_target_bits = cfg->bit_target;
+    p->pre_target_bits_fix = cfg->bit_target_fix;
     p->pre_real_bits = cfg->bit_real;
 
     p->on_drop = 0;
diff --git a/mpp/codec/rc/rc_model_v2_smt.c b/mpp/codec/rc/rc_model_v2_smt.c
index 9ac4fb232..8ded2e14f 100644
--- a/mpp/codec/rc/rc_model_v2_smt.c
+++ b/mpp/codec/rc/rc_model_v2_smt.c
@@ -28,151 +28,69 @@
 #include "rc_model_v2_smt.h"
 #include "mpp_rc.h"
 
-#define MAD_THDI 20
-#define LIMIT_QP_MORE_MOVE 30
-#define ENOUGH_QP 33
 #define LOW_QP 34
-#define LOW_QP_level0 34
-#define LOW_QP_level1 34
-#define LOW_LOW_QP 38
-#define LOW_PRE_DIFF_BIT_USE   -20000
-
-extern RK_S32 tab_lnx[64];
+#define LOW_LOW_QP 35
 
 typedef struct RcModelV2SmtCtx_t {
-    RcCfg        usr_cfg;
-    EncRcTaskInfo     hal_cfg;
-    RK_U32       frame_type;
-    RK_U32       last_frame_type;
-    RK_S64       gop_total_bits;
-    RK_U32       bit_per_frame;
-    MppDataV2    *i_bit;
-    RK_U32       i_sumbits;
-    RK_U32       i_scale;
-    MppDataV2    *idr_bit;
-    RK_U32       idr_sumbits;
-    RK_U32       idr_scale;
-    MppDataV2    *p_bit;
-    RK_U32       p_sumbits;
-    RK_U32       p_scale;
-    MppDataV2    *pre_p_bit;
-    RK_S32       target_bps;
-    RK_S32       pre_target_bits;
-    RK_S32       pre_real_bits;
-    RK_S32       frm_bits_thr;
-    RK_S32       ins_bps;
-    RK_S32       last_inst_bps;
-    RK_U32       water_level_thr;
-    MppDataV2    *stat_bits;
-    MppDataV2    *stat_rate;
-    RK_S32       stat_watl_thrd;
-    RK_S32       stat_watl;
-    RK_S32       stat_last_watl;
-    RK_S32       next_i_ratio;      // scale 64
-    RK_S32       next_ratio;        // scale 64
-    RK_S32       pre_i_qp;
-    RK_S32       pre_p_qp;
-    RK_S32       scale_qp;          // scale 64
-    MppDataV2    *means_qp;
-    RK_S64       frm_num;
-    RK_S32       reenc_cnt;
-    RK_S32 codec_type;              // 264:   0  ; 265:   1
-    RK_S32 qp_min;
-    RK_S32 qp_max;
-    RK_S32 qp_step;
-    MppEncGopMode gop_mode;
-    RK_S32 window_len;
-    RK_S32 intra_to_inter_rate;
-    RK_S32 acc_intra_bits_in_fps;
-    RK_S32 acc_inter_bits_in_fps;
-    RK_S32 acc_total_bits;
-    RK_S64 acc_total_count;
-    RK_S64 acc_intra_count;
-    RK_S64 acc_inter_count;
-    RK_S32 last_fps_bits;
-    RK_S32 pre_gop_left_bit;
-    MppData     *qp_p;
-    MppData     *sse_p;
-    MppData *intra;
-    MppData *inter;
-    MppData *gop_bits;
-    MppData *intra_percent;
-    MppPIDCtx pid_fps;
-    RK_S32 bps_target_low_rate;
-    RK_S32 bps_target_high_rate;
-    RK_S32 bits_target_low_rate;
-    RK_S32 bits_target_high_rate;
-    RK_S32 bits_per_pic_low_rate;
-    RK_S32 bits_per_intra_low_rate;
-    RK_S32 bits_per_inter_low_rate;
-    RK_S32 bits_per_pic_high_rate;
-    RK_S32 bits_per_intra_high_rate;
-    RK_S32 bits_per_inter_high_rate;
-    RK_S32 pre_diff_bit_low_rate;
-    RK_S32 pre_diff_bit_high_rate;
-    RK_S32 gop_min;
-    MppPIDCtx pid_intra_low_rate;
-    MppPIDCtx pid_intra_high_rate;
-    MppPIDCtx pid_inter_low_rate;
-    MppPIDCtx pid_inter_high_rate;
-    RK_S32 bits_one_gop[1000];
-    RK_S32 bits_one_gop_use_flag;
-    RK_S32 bits_one_gop_sum;
-    RK_S32 delta_bits_per_frame;
-    RK_S32 frame_cnt_in_gop;
-    RK_S32 bits_target_use;
-    RK_S32 qp_out;
-    RK_S32 qp_prev_out;
-    RK_S32 qp_preavg;
-    RK_S32 intra_prerealbit;
-    RK_S32 intra_preqp;
-    RK_S32 intra_presse;
-    RK_S32 intra_premadi;
-    RK_U32 st_madi;
+    RcCfg           usr_cfg;
+    RK_U32          frame_type;
+    RK_U32          last_frame_type;
+    RK_U32          first_frm_flg;
+    RK_S64          frm_num;
+    RK_S32          qp_min;
+    RK_S32          qp_max;
+    MppEncGopMode   gop_mode;
+    RK_S64          acc_intra_count;
+    RK_S64          acc_inter_count;
+    RK_S32          last_fps_bits;
+    RK_S32          pre_gop_left_bit;
+    MppData         *qp_p;
+    MppDataV2       *motion_level;
+    MppDataV2       *complex_level;
+    MppDataV2       *stat_bits;
+    MppDataV2       *rt_bits; /* real time bits */
+    MppPIDCtx       pid_fps;
+    RK_S64          count_real_bit;
+    RK_S64          count_pred_bit;
+    RK_S64          count_frame;
+    RK_S64          fixed_i_pred_bit;
+    RK_S64          fixed_p_pred_bit;
+    RK_S32          change_bit_flag;
+
+    RK_S32          bits_tgt_lower; /* bits target lower limit */
+    RK_S32          bits_tgt_upper; /* bits target upper limit */
+    RK_S32          bits_per_lower_i; /* bits per intra frame in low rate */
+    RK_S32          bits_per_upper_i; /* bits per intra frame in high rate */
+    RK_S32          bits_per_lower_p; /* bits per P frame in low rate */
+    RK_S32          bits_per_upper_p; /* bits per P frame in high rate */
+
+    RK_S32          pre_diff_bit_lower;
+    RK_S32          pre_diff_bit_upper;
+    RK_S32          igop;
+    MppPIDCtx       pid_lower_i;
+    MppPIDCtx       pid_upper_i;
+    MppPIDCtx       pid_lower_all;
+    MppPIDCtx       pid_upper_all;
+    MppDataV2       *pid_lower_p;
+    MppDataV2       *pid_upper_p;
+    RK_S32          qp_out;
+    RK_S32          qp_prev_out;
+    RK_S32          pre_real_bit_i; /* real bit of last intra frame */
+    RK_S32          pre_qp_i; /* qp of last intra frame */
+    RK_S32          gop_qp_sum;
+    RK_S32          gop_frm_cnt;
+    RK_S32          pre_iblk4_prop;
+    RK_S32          reenc_cnt;
+    RK_U32          drop_cnt;
+    RK_S32          on_drop;
+    RK_S32          on_pskip;
 } RcModelV2SmtCtx;
 
-typedef struct InfoList_t {
-    RK_U16 flag;            // 1 - valid   0 - unvaild
-    RK_U16 up_left[2];      // 0 - y idx   1 - x idx
-    RK_U16 down_right[2];   // 0 - y idx   1 - x idx
-} InfoList;
-
-typedef struct RoiInfo_t {
-    RK_U16 flag;            // 1 - valid        0 - unvaild
-    RK_U16 is_move;         // 1 - is motion    0 - is motionless
-    RK_U16 up_left[2];      // 0 - y idx        1 - x idx
-    RK_U16 down_right[2];   // 0 - y idx        1 - x idx
-} RoiInfo;
-
-static RK_U32 cal_mv_info(InfoList* info)
-{
-    RK_S32 k, i, j;
-    RK_S32 mb_sta_x, mb_sta_y;
-    RK_S32 mb_end_x, mb_end_y;
-    RK_U32 move_num = 0;
-
-    if (info == NULL)
-        return 0;
-
-    for (k = 0; k < 4096; k++) {
-        if (info[k].flag == 0)
-            break;
-
-        mb_sta_y = info[k].up_left[0] / 16;
-        mb_sta_x = info[k].up_left[1] / 16;
-        mb_end_y = info[k].down_right[0] / 16;
-        mb_end_x = info[k].down_right[1] / 16;
-
-        for (j = mb_sta_y; j <= mb_end_y; j++) {
-            for (i = mb_sta_x; i <= mb_end_x; i++) {
-
-                move_num++;
-            }
-        }
-    }
-
-    return move_num;
-}
+// rc_container_bitrate_thd2
+static RK_S32 rc_ctnr_qp_thd1[6] = { 51, 42, 42, 51, 38, 38 };
+static RK_S32 rc_ctnr_qp_thd2[6] = { 51, 44, 44, 51, 40, 40 };
+static RK_S32 rc_ctnr_br_thd1[6] = { 100, 110, 110, 100, 110, 110 };
+static RK_S32 rc_ctnr_br_thd2[6] = { 100, 120, 120, 100, 125, 125 };
 
 MPP_RET bits_model_smt_deinit(RcModelV2SmtCtx *ctx)
 {
@@ -183,55 +101,34 @@ MPP_RET bits_model_smt_deinit(RcModelV2SmtCtx *ctx)
         ctx->qp_p = NULL;
     }
 
-    if (ctx->sse_p) {
-        mpp_data_deinit(ctx->sse_p);
-        ctx->sse_p = NULL;
-    }
-
-    if (ctx->intra) {
-        mpp_data_deinit(ctx->intra);
-        ctx->intra = NULL;
-    }
-
-    if (ctx->inter) {
-        mpp_data_deinit(ctx->inter);
-        ctx->inter = NULL;
+    if (ctx->motion_level != NULL) {
+        mpp_data_deinit_v2(ctx->motion_level);
+        ctx->motion_level = NULL;
     }
 
-    if (ctx->gop_bits) {
-        mpp_data_deinit(ctx->gop_bits);
-        ctx->gop_bits = NULL;
+    if (ctx->complex_level != NULL) {
+        mpp_data_deinit_v2(ctx->complex_level);
+        ctx->complex_level = NULL;
     }
 
-    if (ctx->intra_percent) {
-        mpp_data_deinit(ctx->intra_percent);
-        ctx->intra_percent = NULL;
-    }
-
-
-    if (ctx->i_bit != NULL) {
-        mpp_data_deinit_v2(ctx->i_bit);
-        ctx->i_bit = NULL;
-    }
-
-    if (ctx->p_bit != NULL) {
-        mpp_data_deinit_v2(ctx->p_bit);
-        ctx->p_bit = NULL;
+    if (ctx->stat_bits != NULL) {
+        mpp_data_deinit_v2(ctx->stat_bits);
+        ctx->stat_bits = NULL;
     }
 
-    if (ctx->pre_p_bit != NULL) {
-        mpp_data_deinit_v2(ctx->pre_p_bit);
-        ctx->pre_p_bit = NULL;
+    if (ctx->rt_bits != NULL) {
+        mpp_data_deinit_v2(ctx->rt_bits);
+        ctx->rt_bits = NULL;
     }
 
-    if (ctx->stat_rate != NULL) {
-        mpp_data_deinit_v2(ctx->stat_rate);
-        ctx->stat_rate = NULL;
+    if (ctx->pid_lower_p != NULL) {
+        mpp_data_deinit_v2(ctx->pid_lower_p);
+        ctx->pid_lower_p = NULL;
     }
 
-    if (ctx->stat_bits != NULL) {
-        mpp_data_deinit_v2(ctx->stat_bits);
-        ctx->stat_bits = NULL;
+    if (ctx->pid_upper_p != NULL) {
+        mpp_data_deinit_v2(ctx->pid_upper_p);
+        ctx->pid_upper_p = NULL;
     }
 
     rc_dbg_func("leave %p\n", ctx);
@@ -242,106 +139,113 @@ MPP_RET bits_model_smt_init(RcModelV2SmtCtx *ctx)
 {
     RK_S32 gop_len = ctx->usr_cfg.igop;
     RcFpsCfg *fps = &ctx->usr_cfg.fps;
+    RK_S32 mad_len = 10;
+    RK_S32 ave_bits_lower = 0, ave_bits_uppper = 0;
+    RK_S32 bits_lower_i, bits_upper_i;
+    RK_S32 bits_lower_p, bits_upper_p;
+    RK_S32 bit_ratio[5] = { 7, 8, 9, 10, 11 };
+    RK_S32 nfps = fps->fps_out_num / fps->fps_out_denom;
+    RK_S32 win_len = mpp_clip(MPP_MAX3(gop_len, nfps, 10), 1, nfps);
+    RK_S32 rt_stat_len = fps->fps_out_num / fps->fps_out_denom; /* real time stat len */
+    RK_S32 stat_len = fps->fps_out_num * ctx->usr_cfg.stats_time / fps->fps_out_denom;
+    stat_len = stat_len ? stat_len : (fps->fps_out_num * 8 / fps->fps_out_denom);
 
     rc_dbg_func("enter %p\n", ctx);
     ctx->frm_num = 0;
+    ctx->first_frm_flg = 1;
+    ctx->gop_frm_cnt = 0;
+    ctx->gop_qp_sum = 0;
 
     // smt
-    ctx->frame_cnt_in_gop = 0;
-    ctx->bits_one_gop_use_flag = 0;
-    ctx->gop_min = gop_len;
-
-    ctx->qp_min = 18;
+    ctx->igop = gop_len;
+    ctx->qp_min = 10;
     ctx->qp_max = 51;
-    ctx->qp_step = 4;
 
-    if (gop_len < fps->fps_out_num)
-        ctx->window_len = fps->fps_out_num;
-    else
-        ctx->window_len = gop_len;
+    if (ctx->motion_level)
+        mpp_data_deinit_v2(ctx->motion_level);
+    mpp_data_init_v2(&ctx->motion_level, mad_len, 0);
 
-    if (ctx->window_len < 10)
-        ctx->window_len = 10;
+    if (ctx->complex_level)
+        mpp_data_deinit_v2(ctx->complex_level);
+    mpp_data_init_v2(&ctx->complex_level, mad_len, 0);
 
-    if (ctx->window_len > fps->fps_out_num)
-        ctx->window_len = fps->fps_out_num;
+    if (ctx->pid_lower_p)
+        mpp_data_deinit_v2(ctx->pid_lower_p);
+    mpp_data_init_v2(&ctx->pid_lower_p, stat_len, 0);
 
-    if (ctx->intra)
-        mpp_data_deinit(ctx->intra);
-    mpp_data_init(&ctx->intra, gop_len);
+    if (ctx->pid_upper_p)
+        mpp_data_deinit_v2(ctx->pid_upper_p);
+    mpp_data_init_v2(&ctx->pid_upper_p, stat_len, 0);
 
-    if (ctx->inter)
-        mpp_data_deinit(ctx->inter);
-    mpp_data_init(&ctx->inter, fps->fps_out_num); /* need test */
+    mpp_pid_reset(&ctx->pid_fps);
+    mpp_pid_reset(&ctx->pid_lower_i);
+    mpp_pid_reset(&ctx->pid_upper_i);
+    mpp_pid_reset(&ctx->pid_lower_all);
+    mpp_pid_reset(&ctx->pid_upper_all);
 
-    if (ctx->gop_bits)
-        mpp_data_deinit(ctx->gop_bits);
-    mpp_data_init(&ctx->gop_bits, gop_len);
+    mpp_pid_set_param(&ctx->pid_fps, 4, 6, 0, 90, win_len);
+    mpp_pid_set_param(&ctx->pid_lower_i, 4, 6, 0, 100, win_len);
+    mpp_pid_set_param(&ctx->pid_upper_i, 4, 6, 0, 100, win_len);
+    mpp_pid_set_param(&ctx->pid_lower_all, 4, 6, 0, 100, gop_len);
+    mpp_pid_set_param(&ctx->pid_upper_all, 4, 6, 0, 100, gop_len);
 
-    if (ctx->intra_percent)
-        mpp_data_deinit(ctx->intra_percent);
-    mpp_data_init(&ctx->intra_percent, gop_len);
+    ave_bits_lower = axb_div_c(ctx->usr_cfg.bps_min, fps->fps_out_denom, fps->fps_out_num);
+    ave_bits_uppper = axb_div_c(ctx->usr_cfg.bps_max, fps->fps_out_denom, fps->fps_out_num);
 
-    mpp_pid_reset(&ctx->pid_fps);
-    mpp_pid_reset(&ctx->pid_intra_low_rate);
-    mpp_pid_reset(&ctx->pid_intra_high_rate);
-    mpp_pid_reset(&ctx->pid_inter_low_rate);
-    mpp_pid_reset(&ctx->pid_inter_high_rate);
-
-    mpp_pid_set_param(&ctx->pid_fps, 4, 6, 0, 100, ctx->window_len);
-    mpp_pid_set_param(&ctx->pid_intra_low_rate, 4, 6, 0, 100, ctx->window_len);
-    mpp_pid_set_param(&ctx->pid_intra_high_rate, 4, 6, 0, 100, ctx->window_len);
-    mpp_pid_set_param(&ctx->pid_inter_low_rate, 4, 6, 0, 100, ctx->window_len);
-    mpp_pid_set_param(&ctx->pid_inter_high_rate, 4, 6, 0, 100, ctx->window_len);
-
-    ctx->bps_target_low_rate = ctx->usr_cfg.bps_min;
-    ctx->bps_target_high_rate = ctx->usr_cfg.bps_max;
-    ctx->bits_per_pic_low_rate = axb_div_c(ctx->bps_target_low_rate, fps->fps_out_denorm, fps->fps_out_num);
-    ctx->bits_per_pic_high_rate = axb_div_c(ctx->bps_target_high_rate, fps->fps_out_denorm, fps->fps_out_num);
-
-    ctx->acc_intra_bits_in_fps = 0;
-    ctx->acc_inter_bits_in_fps = 0;
-    ctx->acc_total_bits = 0;
     ctx->acc_intra_count = 0;
     ctx->acc_inter_count = 0;
     ctx->last_fps_bits = 0;
 
-    RK_S32 avg_low_rate = ctx->bits_per_pic_low_rate;
-    RK_S32 avg_high_rate = ctx->bits_per_pic_high_rate;
-
     if (gop_len == 0) {
         ctx->gop_mode = MPP_GOP_ALL_INTER;
-        ctx->bits_per_inter_low_rate = avg_low_rate;
-        ctx->bits_per_intra_low_rate = avg_low_rate * 10;
-        ctx->bits_per_inter_high_rate = avg_high_rate;
-        ctx->bits_per_intra_high_rate = avg_high_rate * 10;
+        bits_lower_p = ave_bits_lower;
+        bits_lower_i = ave_bits_lower * 10;
+        bits_upper_p = ave_bits_uppper;
+        bits_upper_i = ave_bits_uppper * 10;
     } else if (gop_len == 1) {
         ctx->gop_mode = MPP_GOP_ALL_INTRA;
-        ctx->bits_per_inter_low_rate = 0;
-        ctx->bits_per_intra_low_rate = avg_low_rate;
-        ctx->bits_per_inter_high_rate = 0;
-        ctx->bits_per_intra_high_rate = avg_high_rate;
-        ctx->intra_to_inter_rate = 0;
-    } else if (gop_len < ctx->window_len) {
+        bits_lower_p = 0;
+        bits_lower_i = ave_bits_lower;
+        bits_upper_p = 0;
+        bits_upper_i = ave_bits_uppper;
+        /* disable debreath on all intra case */
+        if (ctx->usr_cfg.debreath_cfg.enable)
+            ctx->usr_cfg.debreath_cfg.enable = 0;
+    } else if (gop_len < win_len) {
         ctx->gop_mode = MPP_GOP_SMALL;
-        ctx->intra_to_inter_rate = gop_len + 1;
-
-        ctx->bits_per_inter_low_rate = avg_low_rate / 2;
-        ctx->bits_per_intra_low_rate = ctx->bits_per_inter_low_rate * ctx->intra_to_inter_rate;
-        ctx->bits_per_inter_high_rate = avg_high_rate / 2;
-        ctx->bits_per_intra_high_rate = ctx->bits_per_inter_high_rate * ctx->intra_to_inter_rate;
+        bits_lower_p = ave_bits_lower >> 1;
+        bits_lower_i = bits_lower_p * (gop_len + 1);
+        bits_upper_p = ave_bits_uppper >> 1;
+        bits_upper_i = bits_upper_p * (gop_len + 1);
     } else {
+        RK_S32 g = gop_len;
+        RK_S32 idx = g <= 50 ? 0 : (g <= 100 ? 1 : (g <= 200 ? 2 : (g <= 300 ? 3 : 4)));
+
         ctx->gop_mode = MPP_GOP_LARGE;
-        ctx->intra_to_inter_rate = gop_len + 1;
+        bits_lower_i = ave_bits_lower * bit_ratio[idx] / 2;
+        bits_upper_i = ave_bits_uppper * bit_ratio[idx] / 2;
+        bits_lower_p = ave_bits_lower - bits_lower_i / (nfps - 1);
+        bits_upper_p = ave_bits_uppper - bits_upper_i / (nfps - 1);
+        ctx->fixed_i_pred_bit = (ctx->usr_cfg.bps_max / nfps * 8) / 8;
+        ctx->fixed_p_pred_bit = ((ctx->usr_cfg.bps_max * g / nfps - ctx->fixed_i_pred_bit) / (g - 1)) / 8;
+    }
 
-        ctx->bits_per_intra_low_rate = ctx->bits_per_pic_low_rate * (2.0 * log((float)gop_len));
-        ctx->bits_per_inter_low_rate = ctx->bits_per_pic_low_rate;
-        ctx->bits_per_inter_low_rate -= ctx->bits_per_intra_low_rate / (fps->fps_out_num - 1);
+    ctx->bits_per_lower_i = bits_lower_i;
+    ctx->bits_per_upper_i = bits_upper_i;
+    ctx->bits_per_lower_p = bits_lower_p;
+    ctx->bits_per_upper_p = bits_upper_p;
 
-        ctx->bits_per_intra_high_rate = ctx->bits_per_pic_high_rate * (2.0 * log((float)gop_len));
-        ctx->bits_per_inter_high_rate = ctx->bits_per_pic_high_rate;
-        ctx->bits_per_inter_high_rate -= ctx->bits_per_intra_high_rate / (fps->fps_out_num - 1);
-    }
+    rc_dbg_rc("bits_per_lower_i %d, bits_per_upper_i %d, "
+              "bits_per_lower_p %d, bits_per_upper_p %d\n",
+              bits_lower_i, bits_upper_i, bits_lower_p, bits_upper_p);
+
+    if (ctx->stat_bits)
+        mpp_data_deinit_v2(ctx->stat_bits);
+    mpp_data_init_v2(&ctx->stat_bits, stat_len, bits_upper_p);
+
+    if (ctx->rt_bits)
+        mpp_data_deinit_v2(ctx->rt_bits);
+    mpp_data_init_v2(&ctx->rt_bits, rt_stat_len, bits_upper_p);
 
     rc_dbg_func("leave %p\n", ctx);
     return MPP_OK;
@@ -350,59 +254,56 @@ MPP_RET bits_model_smt_init(RcModelV2SmtCtx *ctx)
 MPP_RET bits_model_update_smt(RcModelV2SmtCtx *ctx, RK_S32 real_bit)
 {
     rc_dbg_func("enter %p\n", ctx);
-    // smt
-    RK_S32 gop_len = ctx->usr_cfg.igop;
     RcFpsCfg *fps = &ctx->usr_cfg.fps;
+    RK_S32 bps_target_tmp = 0;
+    RK_S32 mod = 0;
 
-    ctx->pre_diff_bit_low_rate = ctx->bits_target_low_rate - real_bit;
-    ctx->pre_diff_bit_high_rate = ctx->bits_target_high_rate - real_bit;
-    ctx->bits_one_gop[ctx->frame_cnt_in_gop % 1000] = real_bit;
-    ctx->frame_cnt_in_gop++;
-
-    if (ctx->frame_cnt_in_gop == gop_len) {
-        ctx->frame_cnt_in_gop = 0;
-        ctx->bits_one_gop_use_flag = 1;
-        ctx->bits_one_gop_sum = 0;
-        RK_S32 i = 0;
-        RK_S32 gop_len_save = gop_len;
-        if (gop_len > 1000) {
-            gop_len_save = 1000;
-        }
-        for (i = 0; i < gop_len_save; i++)
-            ctx->bits_one_gop_sum += ctx->bits_one_gop[i];
+    rc_dbg_func("enter %p\n", ctx);
 
-        ctx->delta_bits_per_frame = ctx->bps_target_high_rate / (fps->fps_out_num) - ctx->bits_one_gop_sum / gop_len_save;
+    mpp_data_update_v2(ctx->stat_bits, real_bit);
+    ctx->pre_diff_bit_lower = ctx->bits_tgt_lower - real_bit;
+    ctx->pre_diff_bit_upper = ctx->bits_tgt_upper - real_bit;
+
+    ctx->count_real_bit = ctx->count_real_bit + real_bit / 8;
+    if (ctx->frame_type == INTRA_FRAME) {
+        ctx->count_pred_bit = ctx->count_pred_bit + ctx->fixed_i_pred_bit;
+    } else {
+        ctx->count_pred_bit = ctx->count_pred_bit + ctx->fixed_p_pred_bit;
+    }
+    ctx->count_frame ++;
+    if (ctx->count_real_bit > 72057594037927935 || ctx->count_pred_bit > 72057594037927935) {
+        ctx->count_real_bit = 0;
+        ctx->count_pred_bit = 0;
+    }
+
+    if (ctx->change_bit_flag == 1) {
+        real_bit = real_bit * 8 / 10;
     }
 
     if (ctx->frame_type == INTRA_FRAME) {
         ctx->acc_intra_count++;
-        ctx->acc_intra_bits_in_fps += real_bit;
-        mpp_data_update(ctx->intra, real_bit);
-        mpp_data_update(ctx->gop_bits, real_bit);
-        mpp_pid_update(&ctx->pid_intra_low_rate, real_bit - ctx->bits_target_low_rate);
-        mpp_pid_update(&ctx->pid_intra_high_rate, real_bit - ctx->bits_target_high_rate);
+        mpp_pid_update(&ctx->pid_lower_i, real_bit - ctx->bits_tgt_lower, 1);
+        mpp_pid_update(&ctx->pid_upper_i, real_bit - ctx->bits_tgt_upper, 1);
     } else {
         ctx->acc_inter_count++;
-        ctx->acc_inter_bits_in_fps += real_bit;
-        mpp_data_update(ctx->inter, real_bit);
-        mpp_data_update(ctx->gop_bits, real_bit);
-        mpp_pid_update(&ctx->pid_inter_low_rate, real_bit - ctx->bits_target_low_rate);
-        mpp_pid_update(&ctx->pid_inter_high_rate, real_bit - ctx->bits_target_high_rate);
+        mpp_data_update_v2(ctx->pid_lower_p, real_bit - ctx->bits_tgt_lower);
+        mpp_data_update_v2(ctx->pid_upper_p, real_bit - ctx->bits_tgt_upper);
     }
+    mpp_pid_update(&ctx->pid_lower_all, real_bit - ctx->bits_tgt_lower, 1);
+    mpp_pid_update(&ctx->pid_upper_all, real_bit - ctx->bits_tgt_upper, 1);
 
-    ctx->acc_total_count++;
     ctx->last_fps_bits += real_bit;
     /* new fps start */
-    if ((ctx->acc_intra_count + ctx->acc_inter_count) % fps->fps_out_num == 0) {
-        RK_S32 bps_target_temp = (ctx->bps_target_low_rate + ctx->bps_target_high_rate) / 2;
-        if (bps_target_temp > (ctx->last_fps_bits * 2 / 3))
-            mpp_pid_update(&ctx->pid_fps, bps_target_temp - ctx->last_fps_bits);
+    mod = ctx->acc_intra_count + ctx->acc_inter_count;
+    mod = mod % fps->fps_out_num;
+    if (0 == mod) {
+        bps_target_tmp = (ctx->usr_cfg.bps_min + ctx->usr_cfg.bps_max) >> 1;
+        if (bps_target_tmp * 3 > (ctx->last_fps_bits * 2))
+            mpp_pid_update(&ctx->pid_fps, bps_target_tmp - ctx->last_fps_bits, 0);
         else {
-            bps_target_temp = ctx->bps_target_low_rate * 0.4 + ctx->bps_target_high_rate * 0.6;
-            mpp_pid_update(&ctx->pid_fps, bps_target_temp - ctx->last_fps_bits);
+            bps_target_tmp = ctx->usr_cfg.bps_min * 4 / 10 + ctx->usr_cfg.bps_max * 6 / 10;
+            mpp_pid_update(&ctx->pid_fps, bps_target_tmp - ctx->last_fps_bits, 0);
         }
-        ctx->acc_intra_bits_in_fps = 0;
-        ctx->acc_inter_bits_in_fps = 0;
         ctx->last_fps_bits = 0;
     }
 
@@ -414,578 +315,711 @@ MPP_RET bits_model_update_smt(RcModelV2SmtCtx *ctx, RK_S32 real_bit)
     return MPP_OK;
 }
 
-MPP_RET reenc_calc_cbr_ratio_smt(RcModelV2SmtCtx *ctx, EncRcTaskInfo *cfg)
+MPP_RET rc_model_v2_smt_h265_init(void *ctx, RcCfg *cfg)
 {
-    RK_S32 stat_time = ctx->usr_cfg.stats_time;
-    RK_S32 last_ins_bps = mpp_data_sum_v2(ctx->stat_bits) / stat_time;
-    RK_S32 ins_bps = (last_ins_bps * stat_time - mpp_data_get_pre_val_v2(ctx->stat_bits, -1) + cfg->bit_real) / stat_time;
-    RK_S32 real_bit = cfg->bit_real;
-    RK_S32 target_bit = cfg->bit_target;
-    RK_S32 target_bps = ctx->target_bps;
-    RK_S32 water_level = 0;
-    RK_S32 idx1, idx2;
-    RK_S32 i_flag = 0;
-    RK_S32 bit_diff_ratio, ins_ratio, bps_ratio, wl_ratio;
+    RcModelV2SmtCtx *p = (RcModelV2SmtCtx*)ctx;
 
     rc_dbg_func("enter %p\n", ctx);
 
-    i_flag = (ctx->frame_type == INTRA_FRAME);
-
-    if (real_bit + ctx->stat_watl > ctx->stat_watl_thrd)
-        water_level = ctx->stat_watl_thrd - ctx->bit_per_frame;
-    else
-        water_level = real_bit + ctx->stat_watl_thrd - ctx->bit_per_frame;
-
-    if (water_level < ctx->stat_last_watl) {
-        water_level = ctx->stat_last_watl;
-    }
-
-    if (target_bit > real_bit)
-        bit_diff_ratio = 32 * (real_bit - target_bit) / target_bit;
-    else
-        bit_diff_ratio = 32 * (real_bit - target_bit) / real_bit;
-
-    idx1 = ins_bps / (target_bps >> 5);
-    idx2 = last_ins_bps / (target_bps >> 5);
-
-    idx1 = mpp_clip(idx1, 0, 63);
-    idx2 = mpp_clip(idx2, 0, 63);
-    ins_ratio = tab_lnx[idx1] - tab_lnx[idx2];
-
-    bps_ratio = 96 * (ins_bps - target_bps) / target_bps;
-    wl_ratio = 32 * (water_level - (ctx->water_level_thr >> 3)) / (ctx->water_level_thr >> 3);
-    if (last_ins_bps < ins_bps && target_bps != last_ins_bps) {
-        ins_ratio = 6 * ins_ratio;
-        ins_ratio = mpp_clip(ins_ratio, -192, 256);
-    } else {
-        if (i_flag) {
-            ins_ratio = 3 * ins_ratio;
-            ins_ratio = mpp_clip(ins_ratio, -192, 256);
-        } else {
-            ins_ratio = 0;
-        }
-    }
-    if (bit_diff_ratio >= 256)
-        bit_diff_ratio = 256;
-
-    if (bps_ratio >= 32)
-        bps_ratio = 32;
-
-    if (wl_ratio >= 32)
-        wl_ratio = 32;
-
-    if (bit_diff_ratio < -128)
-        ins_ratio = ins_ratio - 128;
-    else
-        ins_ratio = ins_ratio + bit_diff_ratio;
-
-    if (bps_ratio < -32)
-        ins_ratio = ins_ratio - 32;
-    else
-        ins_ratio = ins_ratio + bps_ratio;
-
-    if (wl_ratio < -32)
-        wl_ratio = ins_ratio - 32;
-    else
-        wl_ratio = ins_ratio + wl_ratio;
-
-    ctx->next_ratio = wl_ratio;
+    memcpy(&p->usr_cfg, cfg, sizeof(RcCfg));
+    bits_model_smt_init(p);
 
     rc_dbg_func("leave %p\n", ctx);
     return MPP_OK;
 }
 
-MPP_RET reenc_calc_vbr_ratio_smt(RcModelV2SmtCtx *ctx, EncRcTaskInfo *cfg)
+MPP_RET rc_model_v2_smt_h264_init(void *ctx, RcCfg *cfg)
 {
-    RK_S32 stat_time = ctx->usr_cfg.stats_time;
-    RK_S32 last_ins_bps = mpp_data_sum_v2(ctx->stat_bits) / stat_time;
-    RK_S32 ins_bps = (last_ins_bps * stat_time - mpp_data_get_pre_val_v2(ctx->stat_bits, -1)
-                      + cfg->bit_real) / stat_time;
-    RK_S32 bps_change = ctx->target_bps;
-    RK_S32 max_bps_target = ctx->usr_cfg.bps_max;
-    RK_S32 real_bit = cfg->bit_real;
-    RK_S32 target_bit = cfg->bit_target;
-    RK_S32 idx1, idx2;
-    RK_S32 bit_diff_ratio, ins_ratio, bps_ratio;
+    RcModelV2SmtCtx *p = (RcModelV2SmtCtx*)ctx;
 
     rc_dbg_func("enter %p\n", ctx);
 
-    if (target_bit <= real_bit)
-        bit_diff_ratio = 32 * (real_bit - target_bit) / target_bit;
-    else
-        bit_diff_ratio = 32 * (real_bit - target_bit) / real_bit;
-
-    idx1 = ins_bps / (max_bps_target >> 5);
-    idx2 =  last_ins_bps / (max_bps_target >> 5);
-    idx1 = mpp_clip(idx1, 0, 63);
-    idx2 = mpp_clip(idx2, 0, 63);
-    if (last_ins_bps < ins_bps && bps_change < ins_bps) {
-        ins_ratio = 6 * (tab_lnx[idx1] - tab_lnx[idx2]);
-        ins_ratio = mpp_clip(ins_ratio, -192, 256);
-    } else {
-        ins_ratio = 0;
-    }
-
-    bps_ratio = 96 * (ins_bps - bps_change) / bps_change;
-
-    if (bit_diff_ratio >= 256)
-        bit_diff_ratio = 256;
-    if (bps_ratio >= 32)
-        bps_ratio = 32;
-
-    if (bit_diff_ratio < -128)
-        ins_ratio = ins_ratio - 128;
-    else
-        ins_ratio = bit_diff_ratio + ins_ratio;
-
-    if (bps_ratio < -32)
-        ins_ratio = ins_ratio - 32;
-    else
-        ins_ratio = ins_ratio + bps_ratio;
+    memcpy(&p->usr_cfg, cfg, sizeof(RcCfg));
+    bits_model_smt_init(p);
 
-    ctx->next_ratio = ins_ratio;
     rc_dbg_func("leave %p\n", ctx);
     return MPP_OK;
 }
 
-MPP_RET check_re_enc_smt(RcModelV2SmtCtx *ctx, EncRcTaskInfo *cfg)
-{
-    return MPP_OK;
-
-    RK_S32 frame_type = ctx->frame_type;
-    RK_S32 i_flag = 0;
-    RK_S32 big_flag = 0;
-    RK_S32 stat_time = ctx->usr_cfg.stats_time;
-    RK_S32 last_ins_bps = mpp_data_sum_v2(ctx->stat_bits) / stat_time;
-    RK_S32 ins_bps = (last_ins_bps * stat_time -  mpp_data_get_pre_val_v2(ctx->stat_bits, -1)
-                      + cfg->bit_real) / stat_time;
-    RK_S32 target_bps;
-    RK_S32 flag1 = 0;
-    RK_S32 flag2 = 0;
 
+MPP_RET rc_model_v2_smt_deinit(void *ctx)
+{
+    RcModelV2SmtCtx *p = (RcModelV2SmtCtx *)ctx;
     rc_dbg_func("enter %p\n", ctx);
+    bits_model_smt_deinit(p);
+    rc_dbg_func("leave %p\n", ctx);
+    return MPP_OK;
+}
 
-    if (ctx->usr_cfg.mode == RC_CBR)
-        target_bps = ctx->usr_cfg.bps_target;
-    else
-        target_bps = ctx->usr_cfg.bps_max;
+static void set_coef(void *ctx, RK_S32 *coef, RK_S32 val)
+{
+    RcModelV2SmtCtx *p = (RcModelV2SmtCtx*)ctx;
+    RK_S32 cplx_lvl_0 = mpp_data_get_pre_val_v2(p->complex_level, 0);
+    RK_S32 cplx_lvl_1 = mpp_data_get_pre_val_v2(p->complex_level, 1);
+    RK_S32 cplx_lvl_sum = mpp_data_sum_v2(p->complex_level);
+
+    if (cplx_lvl_sum == 0)
+        *coef = val + 0;
+    else if (cplx_lvl_sum == 1) {
+        if (cplx_lvl_0 == 0)
+            *coef = val + 10;
+        else
+            *coef = val + 25;
+    } else if (cplx_lvl_sum == 2) {
+        if (cplx_lvl_0 == 0)
+            *coef = val + 25;
+        else
+            *coef = val + 35;
+    } else if (cplx_lvl_sum == 3) {
+        if (cplx_lvl_0 == 0)
+            *coef = val + 35;
+        else
+            *coef = val + 51;
+    } else if (cplx_lvl_sum >= 4 && cplx_lvl_sum <= 6) {
+        if (cplx_lvl_0 == 0) {
+            if (cplx_lvl_1 == 0)
+                *coef = val + 35;
+            else
+                *coef = val + 51;
+        } else
+            *coef = val + 64;
+    } else if (cplx_lvl_sum >= 7 && cplx_lvl_sum <= 9) {
+        if (cplx_lvl_0 == 0) {
+            if (cplx_lvl_1 == 0)
+                *coef = val + 64;
+            else
+                *coef = val + 72;
+        } else
+            *coef = val + 72;
+    } else
+        *coef = val + 80;
+}
 
-    if (ctx->reenc_cnt >= ctx->usr_cfg.max_reencode_times) {
-        return MPP_OK;
-    }
+static RK_U32 mb_num[9] = {
+    0, 200, 700, 1200, 2000, 4000, 8000, 16000, 20000
+};
 
-    i_flag = (frame_type == INTRA_FRAME);
-    if (!i_flag && cfg->bit_real > 3 * cfg->bit_target) {
-        big_flag = 1;
-    }
+static RK_U32 tab_bit[9] = {
+    3780, 3570, 3150, 2940, 2730, 3780, 2100, 1680, 2100
+};
 
-    if (i_flag && cfg->bit_real > 3 * cfg->bit_target / 2) {
-        big_flag = 1;
-    }
+static RK_U8 qscale2qp[96] = {
+    15,  15,  15,  15,  15,  16, 18, 20, 21, 22, 23,
+    24,  25,  25,  26,  27,  28, 28, 29, 29, 30, 30,
+    30,  31,  31,  32,  32,  33, 33, 33, 34, 34, 34,
+    34,  35,  35,  35,  36,  36, 36, 36, 36, 37, 37,
+    37,  37,  38,  38,  38,  38, 38, 39, 39, 39, 39,
+    39,  39,  40,  40,  40,  40, 41, 41, 41, 41, 41,
+    41,  41,  42,  42,  42,  42, 42, 42, 42, 42, 43,
+    43,  43,  43,  43,  43,  43, 43, 44, 44, 44, 44,
+    44,  44,  44,  44,  45,  45, 45, 45,
+};
 
-    if (ctx->usr_cfg.mode == RC_CBR) {
-        flag1 = target_bps / 20 < ins_bps - last_ins_bps;
-        if (target_bps + target_bps / 10 < ins_bps ||
-            target_bps - target_bps / 10 > ins_bps) {
-            flag2 = 1;
-        }
-    } else {
-        flag1 = target_bps - (target_bps >> 3) < ins_bps;
-        flag2 = target_bps / 20  < ins_bps - last_ins_bps;
-    }
+static RK_U8 inter_pqp0[52] = {
+    1,  1,  1,  1,  1,  2,  3,  4,
+    5,  6,  7,  8,  9,  10, 11, 12,
+    13, 14, 15, 17, 18, 19, 20, 21,
+    21, 21, 22, 23, 24, 25, 26, 26,
+    27, 28, 28, 29, 29, 29, 30, 31,
+    31, 32, 32, 33, 33, 34, 35, 35,
+    35, 36, 36, 36
+};
 
-    if (!(big_flag && flag1 && flag2)) {
-        return MPP_OK;
-    }
+static RK_U8 inter_pqp1[52] = {
+    1,  1,  2,  3,  4,  5,  6,  7,
+    8,  9,  10, 11, 12, 13, 14, 15,
+    16, 17, 18, 19, 20, 20, 21, 22,
+    23, 24, 25, 26, 26, 27, 28, 29,
+    29, 30, 31, 31, 32, 33, 34, 35,
+    36, 37, 38, 39, 40, 41, 42, 42,
+    42, 43, 43, 44
+};
 
-    rc_dbg_func("leave %p\n", ctx);
-    return MPP_OK;
-}
+static RK_U8 intra_pqp0[3][52] = {
+    {
+        1,  1,  1,  2,  3,  4,  5,  6,
+        7,  8,  9,  10, 11, 12, 13, 14,
+        15, 16, 17, 18, 19, 20, 21, 22,
+        23, 23, 24, 25, 26, 27, 27, 28,
+        28, 29, 30, 31, 32, 32, 33, 34,
+        34, 34, 35, 35, 36, 36, 36, 36,
+        37, 37, 37, 38
+    },
+
+    {
+        1,  1,  1,  2,  3,  4,  5,  6,
+        7,  8,  9,  10, 11, 12, 13, 14,
+        15, 16, 17, 17, 18, 18, 19, 19,
+        20, 21, 22, 23, 24, 25, 26, 27,
+        28, 29, 30, 31, 32, 32, 33, 34,
+        34, 34, 35, 35, 36, 36, 36, 36,
+        37, 37, 37, 38
+    },
+
+    {
+        1,  1,  1,  2,  3,  4,  5,  6,
+        7,  8,  9,  10, 11, 12, 13, 14,
+        14, 15, 15, 16, 16, 17, 17, 18,
+        16, 16, 16, 17, 18, 19, 20, 21,
+        23, 24, 26, 28, 30, 31, 32, 33,
+        34, 34, 35, 35, 36, 36, 36, 36,
+        37, 37, 37, 38
+    },
+};
 
+static RK_U8 intra_pqp1[52] = {
+    2,  3,  4,  5,  6,  7,  8,  9,
+    10, 11, 12, 13, 14, 15, 16, 17,
+    18, 19, 20, 22, 23, 24, 25, 26,
+    27, 28, 29, 30, 31, 32, 33, 34,
+    35, 36, 37, 38, 39, 40, 41, 42,
+    43, 44, 45, 46, 47, 48, 49, 50,
+    51, 51, 51, 51
+};
 
-MPP_RET rc_model_v2_smt_h265_init(void *ctx, RcCfg *cfg)
+static RK_S32 cal_smt_first_i_start_qp(RK_S32 target_bit, RK_U32 total_mb)
 {
-    RcModelV2SmtCtx *p = (RcModelV2SmtCtx*)ctx;
+    RK_S32 cnt = 0;
+    RK_S32 index;
+    RK_S32 i;
 
-    rc_dbg_func("enter %p\n", ctx);
+    for (i = 0; i < 8; i++) {
+        if (mb_num[i] > total_mb)
+            break;
+        cnt++;
+    }
 
-    p->codec_type = 1;
-    memcpy(&p->usr_cfg, cfg, sizeof(RcCfg));
-    bits_model_smt_init(p);
+    index = (total_mb * tab_bit[cnt] - 350) / target_bit; // qscale
+    index = mpp_clip(index, 4, 95);
 
-    rc_dbg_func("leave %p\n", ctx);
-    return MPP_OK;
+    return qscale2qp[index];
 }
 
-MPP_RET rc_model_v2_smt_h264_init(void *ctx, RcCfg *cfg)
+static MPP_RET calc_smt_debreath_qp(RcModelV2SmtCtx * ctx)
 {
-    RcModelV2SmtCtx *p = (RcModelV2SmtCtx*)ctx;
+    RK_S32 fm_qp_sum = 0;
+    RK_S32 new_fm_qp = 0;
+    RcDebreathCfg *debreath_cfg = &ctx->usr_cfg.debreath_cfg;
+    RK_S32 dealt_qp = 0;
+    RK_S32 gop_qp_sum = ctx->gop_qp_sum;
+    RK_S32 gop_frm_cnt = ctx->gop_frm_cnt;
+    static RK_S8 intra_qp_map[8] = {
+        0, 0, 1, 1, 2, 2, 2, 2,
+    };
+    RK_U8 idx2 = MPP_MIN(ctx->pre_iblk4_prop >> 5, (RK_S32)sizeof(intra_qp_map) - 1);
+
+    static RK_S8 strength_map[36] = {
+        0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4,
+        5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8,
+        9, 9, 9, 10, 10, 10, 11, 11, 11, 12, 12, 12
+    };
 
     rc_dbg_func("enter %p\n", ctx);
 
-    p->codec_type = 0;
-    memcpy(&p->usr_cfg, cfg, sizeof(RcCfg));
-    bits_model_smt_init(p);
+    fm_qp_sum = MPP_MIN(gop_qp_sum / gop_frm_cnt, (RK_S32)sizeof(strength_map) - 1);
 
-    rc_dbg_func("leave %p\n", ctx);
-    return MPP_OK;
-}
+    rc_dbg_qp("i qp_out %d, qp_start_sum = %d, intra_lv4_prop %d",
+              ctx->qp_out, fm_qp_sum, ctx->pre_iblk4_prop);
 
+    dealt_qp = strength_map[debreath_cfg->strength] - intra_qp_map[idx2];
+    if (fm_qp_sum > dealt_qp)
+        new_fm_qp = fm_qp_sum - dealt_qp;
+    else
+        new_fm_qp = fm_qp_sum;
 
-MPP_RET rc_model_v2_smt_deinit(void *ctx)
-{
-    RcModelV2SmtCtx *p = (RcModelV2SmtCtx *)ctx;
-    rc_dbg_func("enter %p\n", ctx);
-    bits_model_smt_deinit(p);
+    ctx->qp_out = mpp_clip(new_fm_qp, ctx->usr_cfg.min_i_quality, ctx->usr_cfg.max_i_quality);
+    ctx->gop_frm_cnt = 0;
+    ctx->gop_qp_sum = 0;
     rc_dbg_func("leave %p\n", ctx);
     return MPP_OK;
 }
 
-MPP_RET rc_model_v2_smt_start(void *ctx, EncRcTask *task)
+static MPP_RET smt_start_prepare(void *ctx, EncRcTask *task)
 {
-    RcModelV2SmtCtx *p = (RcModelV2SmtCtx*)ctx;
     EncFrmStatus *frm = &task->frm;
+    RcModelV2SmtCtx *p = (RcModelV2SmtCtx *) ctx;
     EncRcTaskInfo *info = &task->info;
     RcFpsCfg *fps = &p->usr_cfg.fps;
-    RK_U32 md_ctu_cnt = 0;
-    void *ptr = NULL;
+    RK_S32 fps_out = fps->fps_out_num / fps->fps_out_denom;
+    RK_S32 b_min = p->usr_cfg.bps_min;
+    RK_S32 b_max = p->usr_cfg.bps_max;
+    RK_S32 bits_lower, bits_upper;
 
-    if (frm->reencode)
-        return MPP_OK;
-
-    if (mpp_frame_has_meta(task->frame)) {
-        MppMeta meta = mpp_frame_get_meta(task->frame);
-
-        mpp_meta_get_ptr(meta, KEY_MV_LIST, &ptr);
-    }
-
-    md_ctu_cnt = cal_mv_info(ptr);
-
-    if (frm->is_intra) {
-        p->frame_type = INTRA_FRAME;
-        p->acc_total_count = 0;
-        p->acc_intra_bits_in_fps = 0;
-    } else {
-        p->frame_type = INTER_P_FRAME;
-    }
+    p->frame_type = frm->is_intra ? INTRA_FRAME : INTER_P_FRAME;
+    if (frm->ref_mode == REF_TO_PREV_INTRA)
+        p->frame_type = info->frame_type = INTER_VI_FRAME;
 
     switch (p->gop_mode) {
-    case MPP_GOP_ALL_INTER : {
+    case MPP_GOP_ALL_INTER: {
         if (p->frame_type == INTRA_FRAME) {
-            p->bits_target_low_rate = p->bits_per_intra_low_rate;
-            p->bits_target_high_rate = p->bits_per_intra_high_rate;
+            bits_lower = p->bits_per_lower_i;
+            bits_upper = p->bits_per_upper_i;
         } else {
-            p->bits_target_low_rate = p->bits_per_inter_low_rate
-                                      - mpp_pid_calc(&p->pid_inter_low_rate);
-            p->bits_target_high_rate = p->bits_per_inter_high_rate
-                                       - mpp_pid_calc(&p->pid_inter_high_rate);
+            bits_lower = p->bits_per_lower_p - mpp_data_mean_v2(p->pid_lower_p);
+            bits_upper = p->bits_per_upper_p - mpp_data_mean_v2(p->pid_upper_p);
         }
     } break;
-    case MPP_GOP_ALL_INTRA : {
-        p->bits_target_low_rate = p->bits_per_intra_low_rate
-                                  - mpp_pid_calc(&p->pid_intra_low_rate);
-        p->bits_target_high_rate = p->bits_per_intra_high_rate
-                                   - mpp_pid_calc(&p->pid_intra_high_rate);
+    case MPP_GOP_ALL_INTRA: {
+        bits_lower = p->bits_per_lower_i - mpp_pid_calc(&p->pid_lower_i);
+        bits_upper = p->bits_per_upper_i - mpp_pid_calc(&p->pid_upper_i);
     } break;
-    default : {
+    default: {
         if (p->frame_type == INTRA_FRAME) {
-            //float intra_percent = 0.0;
             RK_S32 diff_bit = mpp_pid_calc(&p->pid_fps);
-            /* only affected by last gop */
-            p->pre_gop_left_bit = p->pid_fps.i - diff_bit;
 
+            p->pre_gop_left_bit = p->pid_fps.i - diff_bit;
             mpp_pid_reset(&p->pid_fps);
-
             if (p->acc_intra_count) {
-                p->bits_target_low_rate = (p->bits_per_intra_low_rate + diff_bit);
-                p->bits_target_high_rate = (p->bits_per_intra_high_rate + diff_bit);
+                bits_lower = (p->bits_per_lower_i + diff_bit);
+                bits_upper = (p->bits_per_upper_i + diff_bit);
             } else {
-                p->bits_target_low_rate = p->bits_per_intra_low_rate
-                                          - mpp_pid_calc(&p->pid_intra_low_rate);
-                p->bits_target_high_rate = p->bits_per_intra_high_rate
-                                           - mpp_pid_calc(&p->pid_intra_high_rate);
+                bits_lower = p->bits_per_lower_i - mpp_pid_calc(&p->pid_lower_i);
+                bits_upper = p->bits_per_upper_i - mpp_pid_calc(&p->pid_upper_i);
             }
         } else {
             if (p->last_frame_type == INTRA_FRAME) {
-                RK_S32 diff_bit = mpp_pid_calc(&p->pid_fps);
-                /*
-                * case - inter frame after intra frame
-                * update inter target bits with compensation of previous intra frame
-                */
-                RK_S32 bits_prev_intra = mpp_data_avg(p->intra, 1, 1, 1);
-
-                p->bits_per_inter_low_rate =  (p->bps_target_low_rate *
-                                               (p->gop_min * 1.0 / fps->fps_out_num) -
-                                               bits_prev_intra + diff_bit + p->pre_gop_left_bit) /
-                                              (p->gop_min - 1);
-                p->bits_target_low_rate = p->bits_per_inter_low_rate;
-                p->bits_per_inter_high_rate =  (p->bps_target_high_rate *
-                                                (p->gop_min * 1.0 / fps->fps_out_num) -
-                                                bits_prev_intra + diff_bit + p->pre_gop_left_bit) /
-                                               (p->gop_min - 1);
-                p->bits_target_high_rate = p->bits_per_inter_high_rate;
-            } else {
-                RK_S32 diff_bit_low_rate = mpp_pid_calc(&p->pid_inter_low_rate);
-                p->bits_target_low_rate = p->bits_per_inter_low_rate - diff_bit_low_rate;
-                if (p->bits_target_low_rate > p->bits_per_pic_low_rate * 2) {
-                    p->bits_target_low_rate = 2 * p->bits_per_pic_low_rate;
-                    p->pid_inter_low_rate.i = p->pid_inter_low_rate.i / 2;
-                }
-                RK_S32 diff_bit_high_rate = mpp_pid_calc(&p->pid_inter_high_rate);
-                p->bits_target_high_rate = p->bits_per_inter_high_rate - diff_bit_high_rate;
+                RK_S32 bits_prev_i = p->pre_real_bit_i;
 
-                if (p->bits_target_high_rate > p->bits_per_pic_high_rate * 2) {
-                    p->bits_target_high_rate = 2 * p->bits_per_pic_high_rate;
-                    p->pid_inter_high_rate.i = p->pid_inter_high_rate.i / 2;
-                }
+                bits_lower = p->bits_per_lower_p
+                             = ((RK_S64)b_min * p->igop / fps_out - bits_prev_i +
+                                p->pre_gop_left_bit) / (p->igop - 1);
+
+                bits_upper = p->bits_per_upper_p
+                             = ((RK_S64)b_max * p->igop / fps_out - bits_prev_i +
+                                p->pre_gop_left_bit) / (p->igop - 1);
+
+            } else {
+                RK_S32 diff_bit_lr = mpp_data_mean_v2(p->pid_lower_p);
+                RK_S32 diff_bit_hr = mpp_data_mean_v2(p->pid_upper_p);
+                RK_S32 lr = axb_div_c(b_min, fps->fps_out_denom, fps->fps_out_num);
+                RK_S32 hr = axb_div_c(b_max, fps->fps_out_denom, fps->fps_out_num);
+
+                bits_lower = p->bits_per_lower_p - diff_bit_lr;
+                if (bits_lower > 2 * lr)
+                    bits_lower = 2 * lr;
+
+                bits_upper = p->bits_per_upper_p - diff_bit_hr;
+                if (bits_upper > 2 * hr)
+                    bits_upper = 2 * hr;
             }
 
         }
     } break;
+    }
+
+    p->bits_tgt_lower = bits_lower;
+    p->bits_tgt_upper = bits_upper;
+    info->bit_max = (bits_lower + bits_upper) / 2;
+    if (info->bit_max < 100)
+        info->bit_max = 100;
 
+    if (NULL == p->qp_p) {
+        RK_S32 nfps = fps_out < 15 ? 4 * fps_out : (fps_out < 25 ? 3 * fps_out : 2 * fps_out);
+        mpp_data_init(&p->qp_p, mpp_clip(MPP_MAX(p->igop, nfps), 20, 50));
     }
 
-    if (NULL == p->qp_p)
-        mpp_data_init(&p->qp_p, MPP_MIN(p->gop_min, 15));
-    if (NULL == p->sse_p)
-        mpp_data_init(&p->sse_p, MPP_MIN(p->gop_min, 15));
+    rc_dbg_rc("bits_tgt_lower %d, bits_tgt_upper %d, bit_max %d, qp_out %d",
+              p->bits_tgt_lower, p->bits_tgt_upper, info->bit_max, p->qp_out);
+
+    return MPP_OK;
+}
+
+static RK_S32 smt_calc_coef(void *ctx)
+{
+    RcModelV2SmtCtx *p = (RcModelV2SmtCtx *) ctx;
+    RK_S32 coef = 1024;
+    RK_S32 coef2 = 512;
+    RK_S32 md_lvl_sum = mpp_data_sum_v2(p->motion_level);
+    RK_S32 md_lvl_0 = mpp_data_get_pre_val_v2(p->motion_level, 0);
+    RK_S32 md_lvl_1 = mpp_data_get_pre_val_v2(p->motion_level, 1);
+
+    if (md_lvl_sum < 100)
+        set_coef(ctx, &coef, 0);
+    else if (md_lvl_sum < 200) {
+        if (md_lvl_0 < 100)
+            set_coef(ctx, &coef, 102);
+        else
+            set_coef(ctx, &coef, 154);
+    } else if (md_lvl_sum < 300) {
+        if (md_lvl_0 < 100)
+            set_coef(ctx, &coef, 154);
+        else if (md_lvl_0 == 100) {
+            if (md_lvl_1  < 100)
+                set_coef(ctx, &coef, 205);
+            else if (md_lvl_1 == 100)
+                set_coef(ctx, &coef, 256);
+            else
+                set_coef(ctx, &coef, 307);
+        } else
+            set_coef(ctx, &coef, 307);
+    } else if (md_lvl_sum < 600) {
+        if (md_lvl_0 < 100) {
+            if (md_lvl_1  < 100)
+                set_coef(ctx, &coef, 307);
+            else if (md_lvl_1 == 100)
+                set_coef(ctx, &coef, 358);
+            else
+                set_coef(ctx, &coef, 410);
+        } else if (md_lvl_0 == 100) {
+            if (md_lvl_1  < 100)
+                set_coef(ctx, &coef, 358);
+            else if (md_lvl_1 == 100)
+                set_coef(ctx, &coef, 410);
+            else
+                set_coef(ctx, &coef, 461);
+        } else
+            set_coef(ctx, &coef, 461);
+    } else if (md_lvl_sum < 900) {
+        if (md_lvl_0 < 100) {
+            if (md_lvl_1 < 100)
+                set_coef(ctx, &coef, 410);
+            else if (md_lvl_1 == 100)
+                set_coef(ctx, &coef, 461);
+            else
+                set_coef(ctx, &coef, 512);
+        } else if (md_lvl_0 == 100) {
+            if (md_lvl_1 < 100)
+                set_coef(ctx, &coef, 512);
+            else if (md_lvl_1 == 100)
+                set_coef(ctx, &coef, 563);
+            else
+                set_coef(ctx, &coef, 614);
+        } else
+            set_coef(ctx, &coef, 614);
+    } else if (md_lvl_sum < 1500)
+        set_coef(ctx, &coef, 666);
+    else if (md_lvl_sum < 1900)
+        set_coef(ctx, &coef, 768);
+    else
+        set_coef(ctx, &coef, 900);
+
+    if (coef > 1024)
+        coef = 1024;
 
-    RK_S32 madi = p->hal_cfg.madi;
+    if (coef >= 900)
+        coef2 = 1024;
+    else if (coef >= 307)    // 0.7~0.3 --> 1.0~0.5
+        coef2 = 512 + (coef - 307) * (1024 - 512) / (717 - 307);
+    else    // 0.3~0.0 --> 0.5~0.0
+        coef2 = 0 + coef * (512 - 0) / (307 - 0);
+    if (coef2 >= 1024)
+        coef2 = 1024;
+
+    return coef2;
+}
+
+MPP_RET rc_model_v2_smt_start(void *ctx, EncRcTask * task)
+{
+    RcModelV2SmtCtx *p = (RcModelV2SmtCtx *) ctx;
+    EncFrmStatus *frm = &task->frm;
+    EncRcTaskInfo *info = &task->info;
+    RcFpsCfg *fps = &p->usr_cfg.fps;
+    RK_S32 qp_add = 0, qp_add_p = 0, qp_minus = 0;
+    RK_S32 bit_target_use = 0;
+    RK_S32 avg_bps = (p->usr_cfg.bps_min + p->usr_cfg.bps_max) / 2;
+    RK_S32 fps_out = fps->fps_out_num / fps->fps_out_denom;
+    RK_S32 avg_pqp = 0;
+    RK_S32 prev_pqp = p->qp_prev_out;
+    RK_S32 fm_min_iqp = p->usr_cfg.fqp_min_i;
+    RK_S32 fm_min_pqp = p->usr_cfg.fqp_min_p;
+    RK_S32 fm_max_iqp = p->usr_cfg.fqp_max_i;
+    RK_S32 fm_max_pqp = p->usr_cfg.fqp_max_p;
+    RK_S32 md_lvl_sum = mpp_data_sum_v2(p->motion_level);
+    RK_S32 md_lvl_0 = mpp_data_get_pre_val_v2(p->motion_level, 0);
+    RK_S32 cplx_lvl_sum = mpp_data_sum_v2(p->complex_level);
+
+    if (frm->reencode)
+        return MPP_OK;
+
+    smt_start_prepare(ctx, task);
+    bit_target_use = info->bit_max;
+    avg_pqp = mpp_data_avg(p->qp_p, -1, 1, 1);
 
     if (p->frm_num == 0) {
-        RK_S32 bits_target_use = 0;
-        bits_target_use = (p->bits_target_high_rate - p->bits_target_low_rate) * 1 * 0.5
-                          + p->bits_target_low_rate;
-        p->bits_target_use = bits_target_use;
-        bits_target_use = bits_target_use * ((1920 * 1080 * 1000)
-                                             / (p->usr_cfg.width * p->usr_cfg.height)) / 1000;
-        p->qp_out = 95 - 10.0 * log((float)(bits_target_use / 1000));
-
-        if (p->qp_out < 27) {
-            p->qp_out = 27;
-        }
-        p->qp_out = mpp_clip(p->qp_out, p->qp_min, p->qp_max);
-        p->qp_preavg = 0;
+        RK_S32 mb_w = MPP_ALIGN(p->usr_cfg.width, 16) / 16;
+        RK_S32 mb_h = MPP_ALIGN(p->usr_cfg.height, 16) / 16;
+        RK_S32 ratio = mpp_clip(fps_out  / 10 + 1, 1, 3);
+        RK_S32 qp_out_f0 = 0;
+        if (p->usr_cfg.init_quality < 0) {
+            qp_out_f0 = cal_smt_first_i_start_qp(p->bits_tgt_upper * ratio, mb_w * mb_h);
+            qp_out_f0 = (fm_min_iqp > 31) ? mpp_clip(qp_out_f0, fm_min_iqp, p->qp_max) :
+                        mpp_clip(qp_out_f0, 31, p->qp_max);
+        } else
+            qp_out_f0 = p->usr_cfg.init_quality;
+
+        p->qp_out = qp_out_f0;
+        p->count_real_bit = 0;
+        p->count_pred_bit = 0;
+        p->count_frame = 0;
+        rc_dbg_rc("first frame init_quality %d bits_tgt_upper %d "
+                  "mb_w %d mb_h %d ratio %d qp_out %d\n",
+                  p->usr_cfg.init_quality, p->bits_tgt_upper,
+                  mb_w, mb_h, ratio, p->qp_out);
     }
 
+    p->change_bit_flag = 0;
     if (p->frame_type == INTRA_FRAME) {
         if (p->frm_num > 0) {
-            p->qp_out = mpp_data_avg(p->qp_p, -1, 1, 1) - 3;
-            RK_S32 sse = mpp_data_avg(p->sse_p, 1, 1, 1) + 1;
-            RK_S32 bit_target_use = (p->bits_target_low_rate + p->bits_target_high_rate) / 2;
-            RK_S32 qp_add = 0;
-
-            if (bit_target_use < 100)
-                bit_target_use = 100;
-
-            if (sse < p->intra_presse) {
-                if (bit_target_use <= p->intra_prerealbit) {
-                    p->qp_out = p->intra_preqp;
-                } else {
-                    if (madi >= MAD_THDI) {
-                        p->qp_out = p->intra_preqp - 1;
-                    } else {
-                        if (p->intra_preqp - p->qp_out >= 4) {
-                            p->qp_out = p->intra_preqp - (madi <= 12 ? 4 : 3);
-                        }
-                    }
-                }
-            } else if (sse > p->intra_presse && p->qp_out < p->intra_preqp) {
-                if (p->intra_preqp - p->qp_out >= 3)
-                    p->qp_out = p->intra_preqp - 2;
+            RK_S32 avg_qp = mpp_clip(avg_pqp, p->qp_min, p->qp_max);
+            RK_S32 prev_iqp = p->pre_qp_i;
+            RK_S32 pre_bits_i = p->pre_real_bit_i;
+            RK_S32 qp_out_i = 0;
+
+            if (bit_target_use <= pre_bits_i) {
+                qp_out_i = (bit_target_use * 5 < pre_bits_i) ? prev_iqp + 3 :
+                           (bit_target_use * 2 < pre_bits_i) ? prev_iqp + 2 :
+                           (bit_target_use * 3 < pre_bits_i * 2) ? prev_iqp + 1 : prev_iqp;
             } else {
-                RK_S32 ratio = (RK_S32)((float)sse / (float)p->intra_presse + 0.5);
-                if (ratio <= 2) {
-                    p->qp_out = p->intra_preqp;
-                } else if (ratio <= 4) {
-                    p->qp_out = mpp_clip(p->qp_out, p->intra_preqp - 1, p->intra_preqp + 1);
-                } else {
-                    p->qp_out = mpp_clip(p->qp_out, p->intra_preqp - 2, p->intra_preqp + 2);
-                }
-            }
-            if (p->qp_prev_out < 25) {
-                qp_add = 4;
-            } else if (p->qp_prev_out < 27) {
-                qp_add = 2;
-            } else if (p->qp_prev_out < 29) {
-                qp_add = 1;
+                qp_out_i = (pre_bits_i * 3 < bit_target_use) ? prev_iqp - 3 :
+                           (pre_bits_i * 2 < bit_target_use) ? prev_iqp - 2 :
+                           (pre_bits_i * 3 < bit_target_use * 2) ? prev_iqp - 1 : prev_iqp;
             }
-            p->qp_out = mpp_clip(p->qp_out, p->qp_prev_out - 4, p->qp_prev_out + qp_add);
 
-            p->bits_target_use = (p->bits_target_low_rate + p->bits_target_high_rate) / 2;
-            if (p->bits_target_use < 100)
-                p->bits_target_use = 100;
+            if (!p->reenc_cnt && p->usr_cfg.debreath_cfg.enable)
+                calc_smt_debreath_qp(p);
+
+            qp_out_i = mpp_clip(qp_out_i, inter_pqp0[avg_qp], inter_pqp1[avg_qp]);
+            qp_out_i = mpp_clip(qp_out_i, inter_pqp0[prev_pqp], inter_pqp1[prev_pqp]);
+            if (qp_out_i > 27)
+                p->qp_out = mpp_clip(qp_out_i, intra_pqp0[0][prev_iqp], intra_pqp1[prev_iqp]);
+            else if (qp_out_i > 22)
+                p->qp_out = mpp_clip(qp_out_i, intra_pqp0[1][prev_iqp], intra_pqp1[prev_iqp]);
+            else
+                p->qp_out = mpp_clip(qp_out_i, intra_pqp0[2][prev_iqp], intra_pqp1[prev_iqp]);
+
+            if (p->pre_gop_left_bit < 0) {
+                if (abs(p->pre_gop_left_bit) * 5 > avg_bps * (p->igop / fps_out))
+                    p->qp_out = mpp_clip(p->qp_out, 20, 51);
+                else if (abs(p->pre_gop_left_bit) * 20 > avg_bps * (p->igop / fps_out))
+                    p->qp_out = mpp_clip(p->qp_out, 15, 51);
+            }
         }
     } else {
-        p->bits_target_use = (p->bits_target_low_rate + p->bits_target_high_rate) / 2;
-        p->qp_out = p->qp_preavg;
-
-        if (p->last_frame_type == INTRA_FRAME) {
-            RK_S32 qp_add = 0;
-            if (p->qp_prev_out < 25) {
-                qp_add = 2;
-            } else if (p->qp_prev_out < 29) {
-                qp_add = 1;
-            }
-            p->qp_out = mpp_clip(p->qp_out, p->qp_prev_out + qp_add, p->qp_prev_out + 4 + qp_add);
-            p->bits_target_use = (p->bits_target_low_rate + p->bits_target_high_rate) / 2;
-            if (p->bits_target_use < 100)
-                p->bits_target_use = 100;
-        } else {
-            MppFrame frame = task->frame;
-            RK_S32 width = mpp_frame_get_width(frame);
-            RK_S32 height = mpp_frame_get_height(frame);
-            float coef = (float)md_ctu_cnt / (MPP_ALIGN(width, 16) / 16 * MPP_ALIGN(height, 16) / 16);
-            float coef2 = 0.5;
-
-            if (coef >= 0.7)
-                coef2 = 1.0;
-            else if (coef >= 0.3) // 0.7~0.3 --> 1.0~0.5
-                coef2 = 0.5 + (coef - 0.3) * (1.0 - 0.5) / (0.7 - 0.3);
-            else  // 0.3~0.0 --> 0.5~0.0
-                coef2 = 0.0 + coef * (0.5 - 0.0) / (0.3 - 0.0);
-
-            RK_S32 bits_target_use = p->bits_target_low_rate; // bits_target_high_rate
-            RK_S32 pre_diff_bit_use = p->pre_diff_bit_low_rate; // pre_diff_bit_high_rate
-
-            bits_target_use = (p->bits_target_high_rate - p->bits_target_low_rate) * 1 * coef2
-                              + p->bits_target_low_rate;
-            pre_diff_bit_use = (p->pre_diff_bit_high_rate - p->pre_diff_bit_low_rate) * 1 * coef2
-                               + p->pre_diff_bit_low_rate;
-
-            if (bits_target_use < 100)
-                bits_target_use = 100;
-
-            p->bits_target_use = bits_target_use;
-            if (abs(pre_diff_bit_use) <= bits_target_use * 3 / 100) {
-                p->qp_out = p->qp_prev_out - 1;
-            } else if (pre_diff_bit_use > bits_target_use * 3 / 100) {
-                if (pre_diff_bit_use >= bits_target_use) {
-                    p->qp_out = (p->qp_out >= 30 && madi < MAD_THDI) ? p->qp_prev_out - 4 : p->qp_prev_out - 3;
-                } else if (pre_diff_bit_use >= bits_target_use * 1 / 4) {
-                    p->qp_out = (p->qp_out >= 30 && madi < MAD_THDI) ? p->qp_prev_out - 3 : p->qp_prev_out - 2;
-                } else if (pre_diff_bit_use > bits_target_use * 1 / 10) {
-                    p->qp_out = (madi < MAD_THDI) ? p->qp_prev_out - 2 : p->qp_prev_out - 1;
-                } else {
-                    p->qp_out = p->qp_prev_out - 1;
-                }
+        if (p->last_frame_type == INTRA_FRAME)
+            p->qp_out = prev_pqp + (prev_pqp < 33 ? 3 : (prev_pqp < 35 ? 2 : 1));
+        else {
+            RK_S32 bits_tgt_use = 0;
+            RK_S32 pre_diff_bit_use = 0;
+            RK_S32 coef = smt_calc_coef(ctx);
+            RK_S32 m_tbr = p->bits_tgt_upper - p->bits_tgt_lower;
+            RK_S32 m_dbr = p->pre_diff_bit_upper - p->pre_diff_bit_lower;
+            RK_S32 diff_bit = (p->pid_lower_all.i + p->pid_upper_all.i) >> 1;
+            RK_S32 qp_out = p->qp_out;
+
+            bits_tgt_use = (m_tbr * coef + p->bits_tgt_lower * 1024) >> 10;
+            pre_diff_bit_use = (m_dbr * coef + p->pre_diff_bit_lower * 1024) >> 10;
+            if (bits_tgt_use < 100)
+                bits_tgt_use = 100;
+
+            if (abs(pre_diff_bit_use) * 100 <= bits_tgt_use * 3)
+                qp_out = prev_pqp - 1;
+            else if (pre_diff_bit_use * 100 > bits_tgt_use * 3) {
+                if (pre_diff_bit_use >= bits_tgt_use)
+                    qp_out = qp_out >= 30 ? prev_pqp - 4 : prev_pqp - 3;
+                else if (pre_diff_bit_use * 4 >= bits_tgt_use * 1)
+                    qp_out = qp_out >= 30 ? prev_pqp - 3 : prev_pqp - 2;
+                else if (pre_diff_bit_use * 10 > bits_tgt_use * 1)
+                    qp_out = prev_pqp - 2;
+                else
+                    qp_out = prev_pqp - 1;
             } else {
+                RK_S32 qp_add_tmp = 1;
+                if (prev_pqp >= 36)
+                    qp_add_tmp = 0;
                 pre_diff_bit_use = abs(pre_diff_bit_use);
-                RK_S32 weight = (madi < MAD_THDI ? 1 : 3);
-                if (pre_diff_bit_use >= 2 * weight * bits_target_use) {
-                    p->qp_out =  p->qp_prev_out + 3 ;
-                } else if (pre_diff_bit_use >= bits_target_use * 2 * weight / 3) {
-                    p->qp_out =  p->qp_prev_out + 2 ;
-                } else if (pre_diff_bit_use > bits_target_use * weight / 5) {
-                    p->qp_out = p->qp_prev_out + 1;
-                } else {
-                    p->qp_out = p->qp_prev_out;
-                }
+                qp_out = (pre_diff_bit_use >= 2 * bits_tgt_use)     ? prev_pqp + 2 + qp_add_tmp :
+                         (pre_diff_bit_use * 3 >= bits_tgt_use * 2) ? prev_pqp + 1 + qp_add_tmp :
+                         (pre_diff_bit_use * 5 >  bits_tgt_use)     ? prev_pqp + 1 : prev_pqp;
             }
 
-            p->qp_out =  mpp_clip(p->qp_out, p->qp_min, p->qp_max);
-
-            pre_diff_bit_use = (p->pre_diff_bit_high_rate - p->pre_diff_bit_low_rate) * 1 * coef2 + p->pre_diff_bit_low_rate;
-            RK_S32 low_pre_diff_bit_use = LOW_PRE_DIFF_BIT_USE;
-            low_pre_diff_bit_use = (p->bps_target_low_rate + p->bps_target_high_rate) / 2 / fps->fps_out_num;
-            low_pre_diff_bit_use = -low_pre_diff_bit_use / 5;
-
-            RK_S32 frame_low_qp;
-
-            if (p->codec_type == 1) {
-                if (madi >= MAD_THDI)
-                    frame_low_qp = LOW_QP_level1;
-                else
-                    frame_low_qp = LOW_QP_level0;
-            } else {
-                frame_low_qp = LOW_QP;
+            qp_out = mpp_clip(qp_out, p->qp_min, p->qp_max);
+            pre_diff_bit_use = (m_dbr * coef + p->pre_diff_bit_lower * 1024) >> 10;
+            bits_tgt_use = avg_bps / fps_out;
+            bits_tgt_use = -bits_tgt_use / 5;
+            if (qp_out > LOW_QP) {
+                coef += pre_diff_bit_use <= 2 * bits_tgt_use ? 205 :
+                        ((pre_diff_bit_use <= bits_tgt_use) ? 102 : 51);
+                if (coef >= 1024 || qp_out > LOW_LOW_QP)
+                    coef = 1024;
+                pre_diff_bit_use = (m_dbr * coef + p->pre_diff_bit_lower * 1024) >> 10;
+                bits_tgt_use = (m_tbr * coef + p->bits_tgt_lower * 1024) >> 10;
+                if (bits_tgt_use < 100)
+                    bits_tgt_use = 100;
+
+                if (abs(pre_diff_bit_use) * 100 <= bits_tgt_use * 3)
+                    qp_out = prev_pqp;
+                else if (pre_diff_bit_use * 100 > bits_tgt_use * 3) {
+                    if (pre_diff_bit_use >= bits_tgt_use)
+                        qp_out = qp_out >= 30 ?  prev_pqp - 3 : prev_pqp - 2;
+                    else if (pre_diff_bit_use * 4 >= bits_tgt_use * 1)
+                        qp_out = qp_out >= 30 ? prev_pqp - 2 : prev_pqp - 1;
+                    else if (pre_diff_bit_use * 10 > bits_tgt_use * 1)
+                        qp_out = prev_pqp - 1;
+                    else
+                        qp_out = prev_pqp;
+                } else {
+                    pre_diff_bit_use = abs(pre_diff_bit_use);
+                    qp_out = prev_pqp + (pre_diff_bit_use * 3 >= bits_tgt_use * 2 ? 1 : 0);
+                }
             }
-
-            if (p->qp_out >  frame_low_qp) {
-                if (pre_diff_bit_use <= 2 * low_pre_diff_bit_use)
-                    coef2 += 0.5;
-                else if (pre_diff_bit_use <= low_pre_diff_bit_use)
-                    coef2 += 0.2;
-                else
-                    coef2 += 0.1;
-
-                if (coef2 >= 1.0)
-                    coef2 = 1.0;
-
-                if (p->qp_out > LOW_LOW_QP)
-                    coef2 = 1.0;
-
-                if (coef2 == 1.0 && p->qp_prev_out > frame_low_qp) {
-                    float delta_coef = 0;
-                    if (p->bits_one_gop_use_flag == 1 && p->delta_bits_per_frame > 0) {
-                        delta_coef = ((float)p->delta_bits_per_frame) / ((float)p->bits_per_inter_high_rate - p->bits_per_inter_low_rate);
-
-                        if (delta_coef >= 0.5)
-                            delta_coef = 0.5;
-                        else if (delta_coef >= 0.3)
-                            delta_coef = 0.3;
-
-                        if (p->qp_prev_out > (frame_low_qp + 1))
-                            delta_coef += 0.1;
-
-                        coef2 += delta_coef;
+            qp_out = mpp_clip(qp_out, p->qp_min, p->qp_max);
+
+            //Add rc_container
+            if (p->usr_cfg.rc_container) {
+                RK_S32 cnt = p->usr_cfg.scene_mode * 3 + p->usr_cfg.rc_container;
+                if (p->count_real_bit < p->count_pred_bit * rc_ctnr_br_thd1[cnt] / 100) {
+                    if (qp_out > rc_ctnr_qp_thd1[cnt]) {
+                        p->change_bit_flag = 1;
                     }
-                }
 
-                bits_target_use = (p->bits_target_high_rate - p->bits_target_low_rate) * 1 * coef2 + p->bits_target_low_rate;
-                pre_diff_bit_use = (p->pre_diff_bit_high_rate - p->pre_diff_bit_low_rate) * 1 * coef2 + p->pre_diff_bit_low_rate;
-                if (bits_target_use < 100)
-                    bits_target_use = 100;
-
-                p->bits_target_use = bits_target_use;
-                if (abs(pre_diff_bit_use) <= bits_target_use * 3 / 100) {
-                    p->qp_out = p->qp_prev_out ;
-                } else if (pre_diff_bit_use > bits_target_use * 3 / 100) {
-                    if (pre_diff_bit_use >= bits_target_use) {
-                        p->qp_out = (p->qp_out >= 30 && madi < MAD_THDI) ? p->qp_prev_out - 3 : p->qp_prev_out - 2;
-                    } else if (pre_diff_bit_use >= bits_target_use * 1 / 4) {
-                        p->qp_out = (p->qp_out >= 30 && madi < MAD_THDI) ? p->qp_prev_out - 2 : p->qp_prev_out - 1;
-                    } else if (pre_diff_bit_use > bits_target_use * 1 / 10) {
-                        p->qp_out = (madi < MAD_THDI) ? p->qp_prev_out - 1 : p->qp_prev_out;
-                    } else {
-                        p->qp_out = p->qp_prev_out;
-                    }
-                } else {
-                    pre_diff_bit_use = abs(pre_diff_bit_use);
-                    RK_S32 weight = (madi < MAD_THDI ? 0 : 2);
-                    if (pre_diff_bit_use >= 2 * weight * bits_target_use) {
-                        p->qp_out =  p->qp_prev_out + 1 ;
-                    } else if (pre_diff_bit_use >= bits_target_use * 2 * weight / 3) {
-                        p->qp_out =  p->qp_prev_out + 1 ;
-                    } else if (pre_diff_bit_use > bits_target_use * weight / 5) {
-                        p->qp_out = p->qp_prev_out;
-                    } else {
-                        p->qp_out = p->qp_prev_out;
+                    qp_out = mpp_clip(qp_out, 10, rc_ctnr_qp_thd1[cnt]);
+                } else if (p->count_real_bit < p->count_pred_bit * rc_ctnr_br_thd2[cnt] / 100) {
+                    if (qp_out > rc_ctnr_qp_thd2[cnt]) {
+                        p->change_bit_flag = 1;
                     }
+                    qp_out = mpp_clip(qp_out, 10, rc_ctnr_qp_thd2[cnt]);
                 }
-
-                p->qp_out =  mpp_clip(p->qp_out, p->qp_min, p->qp_max);
             }
 
-            if (p->qp_out < LIMIT_QP_MORE_MOVE && coef >= 0.2)
-                p->qp_out = LIMIT_QP_MORE_MOVE;
+            qp_add = qp_out > 36 ? 1 : (qp_out > 33 ? 2 : (qp_out > 30 ? 3 : 4));
+            qp_minus = qp_out > 40 ? 4 : (qp_out > 36 ? 3 : (qp_out > 33 ? 2 : 1));
+            p->qp_out = mpp_clip(qp_out, prev_pqp - qp_minus, prev_pqp + qp_add);
+            if (diff_bit > 0) {
+                if (avg_bps * 5 > avg_bps)
+                    p->qp_out = mpp_clip(p->qp_out, 25, 51);
+                else if (avg_bps * 20 > avg_bps)
+                    p->qp_out = mpp_clip(p->qp_out, 21, 51);
+            }
         }
     }
 
-    if (p->frm_num >= 1) {
-        p->qp_out = mpp_clip(p->qp_out, p->qp_prev_out - 3, p->qp_prev_out + p->qp_step);
+    qp_add = 4;
+    qp_add_p = 4;
+    if (md_lvl_sum >= 700 || md_lvl_0 == 200) {
+        qp_add = 6;
+        qp_add_p = 6;
+    } else if (md_lvl_sum >= 400 || md_lvl_0 == 100) {
+        qp_add = 5;
+        qp_add_p = 5;
+    }
+    if (cplx_lvl_sum >= 12) {
+        qp_add++;
+        qp_add_p++;
     }
 
-    info->bit_target = p->bits_target_use;
+    if (p->frame_type == INTRA_FRAME)
+        p->qp_out = mpp_clip(p->qp_out, fm_min_iqp + qp_add, fm_max_iqp);
+    else if (p->frame_type == INTER_VI_FRAME) {
+        RK_S32 vi_max_qp = (fm_max_pqp > 42) ? (fm_max_pqp - 5) :
+                           (fm_max_pqp > 39) ? (fm_max_pqp - 3) :
+                           (fm_max_pqp > 35) ? (fm_max_pqp - 2) : fm_max_pqp;
+        p->qp_out -= 1;
+        p->qp_out = mpp_clip(p->qp_out, fm_min_pqp + qp_add - 1, fm_max_pqp);
+        p->qp_out = mpp_clip(p->qp_out, p->qp_out, vi_max_qp);
+    } else
+        p->qp_out = mpp_clip(p->qp_out, fm_min_pqp + qp_add_p, fm_max_pqp);
+
+    p->qp_out = mpp_clip(p->qp_out, p->qp_min, p->qp_max);
     info->quality_target = p->qp_out;
+
+    info->complex_scene = 0;
+    if (p->frame_type == INTER_P_FRAME && avg_pqp >= fm_max_pqp - 1 &&
+        p->qp_out == fm_max_pqp && p->qp_prev_out == fm_max_pqp)
+        info->complex_scene = 1;
+
     info->quality_max = p->usr_cfg.max_quality;
     info->quality_min = p->usr_cfg.min_quality;
+
+    rc_dbg_rc("frame %lld quality [%d : %d : %d] complex_scene %d\n",
+              p->frm_num, info->quality_min, info->quality_target,
+              info->quality_max, info->complex_scene);
+
     p->frm_num++;
     p->reenc_cnt = 0;
     rc_dbg_func("leave %p\n", ctx);
     return MPP_OK;
 }
 
+MPP_RET check_super_frame_smt(RcModelV2SmtCtx *ctx, EncRcTaskInfo *cfg)
+{
+    MPP_RET ret = MPP_OK;
+    RK_S32 frame_type = ctx->frame_type;
+    RK_U32 bits_thr = 0;
+    RcCfg *usr_cfg = &ctx->usr_cfg;
+
+    rc_dbg_func("enter %p\n", ctx);
+    if (usr_cfg->super_cfg.super_mode) {
+        bits_thr = usr_cfg->super_cfg.super_p_thd;
+        if (frame_type == INTRA_FRAME)
+            bits_thr = usr_cfg->super_cfg.super_i_thd;
+
+        if ((RK_U32)cfg->bit_real >= bits_thr) {
+            if (usr_cfg->super_cfg.super_mode == MPP_ENC_RC_SUPER_FRM_DROP) {
+                rc_dbg_rc("super frame drop current frame");
+                usr_cfg->drop_mode = MPP_ENC_RC_DROP_FRM_NORMAL;
+                usr_cfg->drop_gap  = 0;
+            }
+            ret = MPP_NOK;
+        }
+    }
+    rc_dbg_func("leave %p\n", ctx);
+    return ret;
+}
+
+MPP_RET check_re_enc_smt(RcModelV2SmtCtx *ctx, EncRcTaskInfo *cfg)
+{
+    RcCfg *usr_cfg = &ctx->usr_cfg;
+    RK_S32 frame_type = ctx->frame_type;
+    RK_S32 bit_thr = 0;
+    RK_S32 stat_time = usr_cfg->stats_time;
+    RK_S32 last_ins_bps = mpp_data_sum_v2(ctx->stat_bits) / stat_time;
+    RK_S32 ins_bps = (last_ins_bps * stat_time - mpp_data_get_pre_val_v2(ctx->stat_bits, -1)
+                      + cfg->bit_real) / stat_time;
+    RK_S32 bps;
+    RK_S32 ret = MPP_OK;
+
+    rc_dbg_func("enter %p\n", ctx);
+    rc_dbg_rc("reenc check target_bps %d last_ins_bps %d ins_bps %d",
+              usr_cfg->bps_target, last_ins_bps, ins_bps);
+
+    if (ctx->reenc_cnt >= usr_cfg->max_reencode_times)
+        return MPP_OK;
+
+    if (check_super_frame_smt(ctx, cfg))
+        return MPP_NOK;
+
+    if (usr_cfg->debreath_cfg.enable && !ctx->first_frm_flg)
+        return MPP_OK;
+
+    rc_dbg_drop("drop mode %d frame_type %d\n", usr_cfg->drop_mode, frame_type);
+    if (usr_cfg->drop_mode && frame_type == INTER_P_FRAME) {
+        bit_thr = (RK_S32)(usr_cfg->bps_max * (100 + usr_cfg->drop_thd) / (float)100);
+        rc_dbg_drop("drop mode %d check max_bps %d bit_thr %d ins_bps %d",
+                    usr_cfg->drop_mode, usr_cfg->bps_target, bit_thr, ins_bps);
+        return (ins_bps > bit_thr) ? MPP_NOK : MPP_OK;
+    }
+
+    switch (frame_type) {
+    case INTRA_FRAME:
+        bit_thr = 3 * cfg->bit_max / 2;
+        break;
+    case INTER_P_FRAME:
+        bit_thr = 3 * cfg->bit_max;
+        break;
+    default:
+        break;
+    }
+
+    if (cfg->bit_real > bit_thr) {
+        bps = usr_cfg->bps_max;
+        if ((bps - (bps >> 3) < ins_bps) && (bps / 20  < ins_bps - last_ins_bps))
+            ret =  MPP_NOK;
+    }
+
+    rc_dbg_func("leave %p ret %d\n", ctx, ret);
+    return ret;
+}
+
 MPP_RET rc_model_v2_smt_check_reenc(void *ctx, EncRcTask *task)
 {
     RcModelV2SmtCtx *p = (RcModelV2SmtCtx *)ctx;
@@ -998,79 +1032,97 @@ MPP_RET rc_model_v2_smt_check_reenc(void *ctx, EncRcTask *task)
     frm->reencode = 0;
 
     if ((usr_cfg->mode == RC_FIXQP) ||
-        (task->force.force_flag & ENC_RC_FORCE_QP))
+        (task->force.force_flag & ENC_RC_FORCE_QP) ||
+        p->on_drop || p->on_pskip)
         return MPP_OK;
 
     if (check_re_enc_smt(p, cfg)) {
-        if (p->usr_cfg.mode == RC_CBR) {
-            reenc_calc_cbr_ratio_smt(p, cfg);
-        } else {
-            reenc_calc_vbr_ratio_smt(p, cfg);
-        }
-        if (p->next_ratio != 0 && cfg->quality_target < cfg->quality_max) {
-            p->reenc_cnt++;
+        MppEncRcDropFrmMode drop_mode = usr_cfg->drop_mode;
+
+        if (frm->is_intra)
+            drop_mode = MPP_ENC_RC_DROP_FRM_DISABLED;
+
+        if (usr_cfg->drop_gap && p->drop_cnt >= usr_cfg->drop_gap)
+            drop_mode = MPP_ENC_RC_DROP_FRM_DISABLED;
+
+        rc_dbg_drop("reenc drop_mode %d drop_cnt %d\n", drop_mode, p->drop_cnt);
+
+        switch (drop_mode) {
+        case MPP_ENC_RC_DROP_FRM_NORMAL : {
+            frm->drop = 1;
+            frm->reencode = 1;
+            p->on_drop = 1;
+            p->drop_cnt++;
+            rc_dbg_drop("drop\n");
+        } break;
+        case MPP_ENC_RC_DROP_FRM_PSKIP : {
+            frm->force_pskip = 1;
             frm->reencode = 1;
+            p->on_pskip = 1;
+            p->drop_cnt++;
+            rc_dbg_drop("force_pskip\n");
+        } break;
+        case MPP_ENC_RC_DROP_FRM_DISABLED :
+        default : {
+            RK_S32 bits_thr = usr_cfg->super_cfg.super_p_thd;
+            if (p->frame_type == INTRA_FRAME)
+                bits_thr = usr_cfg->super_cfg.super_i_thd;
+
+            if (cfg->bit_real > bits_thr * 2)
+                cfg->quality_target += 3;
+            else if (cfg->bit_real > bits_thr * 3 / 2)
+                cfg->quality_target += 2;
+            else if (cfg->bit_real > bits_thr)
+                cfg->quality_target ++;
+
+            if (cfg->quality_target < cfg->quality_max) {
+                p->reenc_cnt++;
+                frm->reencode = 1;
+            }
+            p->drop_cnt = 0;
+        } break;
         }
     }
-    rc_dbg_func("leave %p\n", ctx);
+
     return MPP_OK;
 }
 
-MPP_RET rc_model_v2_smt_end(void *ctx, EncRcTask *task)
+MPP_RET rc_model_v2_smt_end(void *ctx, EncRcTask * task)
 {
-    RcModelV2SmtCtx *p = (RcModelV2SmtCtx *)ctx;
-    EncRcTaskInfo *cfg = (EncRcTaskInfo *)&task->info;
-    MppFrame frame = task->frame;
-    RK_S32 width = mpp_frame_get_width(frame);
-    RK_S32 height = mpp_frame_get_height(frame);
+    RcModelV2SmtCtx *p = (RcModelV2SmtCtx *) ctx;
+    EncRcTaskInfo *cfg = (EncRcTaskInfo *) & task->info;
     RK_S32 bit_real = cfg->bit_real;
-    RK_S32 madi = cfg->madi;
-    RK_S32 cu64_num = (MPP_ALIGN(width, 64) / 64 * MPP_ALIGN(height, 64) / 64) ;
-    RK_U64 sse_dat = cfg->madp * cu64_num;
-    RK_U32 qp_sum;
-    double avg_qp = 0.0;
-    RK_S32 avg_sse = 1;
 
     rc_dbg_func("enter ctx %p cfg %p\n", ctx, cfg);
-
-    if (p->codec_type == 1)
-        qp_sum = cfg->quality_real / 64; // 265
-    else
-        qp_sum = cfg->quality_real / 16; // 264
-
-    avg_qp = qp_sum;
-    avg_sse = (RK_S32)sqrt((double)(sse_dat));
-    p->qp_preavg = (RK_S32)(avg_qp + 0.5);
-    if (p->frame_type == INTER_P_FRAME) {
-        if (madi >= MAD_THDI) {
-            avg_qp = p->qp_out;
-        }
+    rc_dbg_rc("motion_level %u, complex_level %u\n", cfg->motion_level, cfg->complex_level);
+
+    mpp_data_update_v2(p->rt_bits, bit_real);
+    cfg->rt_bits = mpp_data_sum_v2(p->rt_bits);
+    rc_dbg_rc("frame %lld real_bit %d real time bits %d\n",
+              p->frm_num - 1, bit_real, cfg->rt_bits);
+
+    mpp_data_update_v2(p->motion_level, cfg->motion_level);
+    mpp_data_update_v2(p->complex_level, cfg->complex_level);
+    p->first_frm_flg = 0;
+
+    if (p->frame_type == INTER_P_FRAME || p->gop_mode == MPP_GOP_ALL_INTRA)
+        mpp_data_update(p->qp_p, p->qp_out);
+    else {
+        p->pre_qp_i = p->qp_out;
+        p->pre_real_bit_i = bit_real;
     }
 
-    if (p->frame_type == INTER_P_FRAME || p->gop_mode == MPP_GOP_ALL_INTRA) {
-        mpp_data_update(p->qp_p, avg_qp);
-        mpp_data_update(p->sse_p, avg_sse);
-    } else {
-        p->intra_preqp = p->qp_out;
-        p->intra_presse = avg_sse;
-        p->intra_premadi = madi;
-        p->intra_prerealbit = bit_real;
-    }
-
-    p->st_madi = cfg->madi;
-    rc_dbg_rc("bits_mode_update real_bit %d", bit_real);
     bits_model_update_smt(p, bit_real);
-    p->pre_target_bits = cfg->bit_target;
-    p->pre_real_bits = bit_real;
     p->qp_prev_out = p->qp_out;
-    p->last_inst_bps = p->ins_bps;
     p->last_frame_type = p->frame_type;
+    p->pre_iblk4_prop = cfg->iblk4_prop;
+    p->gop_frm_cnt++;
+    p->gop_qp_sum += p->qp_out;
 
     rc_dbg_func("leave %p\n", ctx);
     return MPP_OK;
 }
 
-
 MPP_RET rc_model_v2_smt_hal_start(void *ctx, EncRcTask *task)
 {
     rc_dbg_func("smt_hal_start enter ctx %p task %p\n", ctx, task);
@@ -1084,7 +1136,6 @@ MPP_RET rc_model_v2_smt_hal_end(void *ctx, EncRcTask *task)
     return MPP_OK;
 }
 
-
 const RcImplApi smt_h264e = {
     "smart",
     MPP_VIDEO_CodingAVC,
diff --git a/mpp/common/av1d_syntax.h b/mpp/common/av1d_syntax.h
index fc8356965..bfed7f532 100644
--- a/mpp/common/av1d_syntax.h
+++ b/mpp/common/av1d_syntax.h
@@ -54,8 +54,10 @@ typedef struct _DXVA_PicParams_AV1 {
     USHORT superres_denom      ;
     USHORT bitdepth            ;
     USHORT seq_profile         ;
+    USHORT frame_header_size   ;
     union {
         struct {
+            UINT32 current_operating_point      : 12;
             UINT32 use_128x128_superblock       : 1;
             UINT32 intra_edge_filter            : 1;
             UINT32 interintra_compound          : 1;
@@ -107,6 +109,7 @@ typedef struct _DXVA_PicParams_AV1 {
     } format;
 
     UCHAR primary_ref_frame;
+    UCHAR enable_order_hint;
     UCHAR order_hint;
     UCHAR order_hint_bits;
 
@@ -135,6 +138,7 @@ typedef struct _DXVA_PicParams_AV1 {
         CHAR  v_dc_delta_q   ;
         CHAR  u_ac_delta_q   ;
         CHAR  v_ac_delta_q   ;
+        CHAR  using_qmatrix  ;
         UCHAR qm_y           ;
         UCHAR qm_u           ;
         UCHAR qm_v           ;
@@ -161,6 +165,8 @@ typedef struct _DXVA_PicParams_AV1 {
         UCHAR  temporal_update   ;
         UCHAR  feature_mask[8]   ;
         INT    feature_data[8][8];
+        UCHAR  last_active       ;
+        UCHAR  preskip           ;
     } segmentation;
 
     struct {
@@ -172,6 +178,7 @@ typedef struct _DXVA_PicParams_AV1 {
         UCHAR grain_scale_shift        ;
         UCHAR overlap_flag             ;
         UCHAR clip_to_restricted_range ;
+        UCHAR matrix_coefficients      ;
         UCHAR matrix_coeff_is_identity ;
         UCHAR num_y_points             ;
         UCHAR num_cb_points            ;
@@ -188,10 +195,15 @@ typedef struct _DXVA_PicParams_AV1 {
         UCHAR cr_luma_mult             ;
 
         USHORT grain_seed              ;
+        USHORT update_grain            ;
         USHORT cb_offset               ;
         USHORT cr_offset               ;
     } film_grain;
 
+    UINT32 ref_frame_valued;
+    UINT32 ref_frame_idx[7];
+
+    UINT32 ref_order_hint[8];
     struct {
         UINT32  width;
         UINT32  height;
@@ -209,14 +221,34 @@ typedef struct _DXVA_PicParams_AV1 {
         UCHAR   wminvalid;
         UCHAR   wmtype;
         RK_S32  wmmat[6];
+        RK_S32  wmmat_val[6];
         USHORT  alpha, beta, gamma, delta;
-    } frame_refs[7];
+    } frame_refs[8];
+
+    struct {
+        RK_S32 valid;          // RefValid
+        RK_S32 frame_id;       // RefFrameId
+        RK_S32 upscaled_width; // RefUpscaledWidth
+        RK_S32 frame_width;    // RefFrameWidth
+        RK_S32 frame_height;   // RefFrameHeight
+        RK_S32 render_width;   // RefRenderWidth
+        RK_S32 render_height;  // RefRenderHeight
+        RK_S32 frame_type;     // RefFrameType
+        RK_S32 subsampling_x;  // RefSubsamplingX
+        RK_S32 subsampling_y;  // RefSubsamplingY
+        RK_S32 bit_depth;      // RefBitDepth
+        RK_S32 order_hint;     // RefOrderHint
+    } frame_ref_state[8];
+
+    RK_U8 ref_frame_sign_bias[8];
 
     UCHAR coded_lossless;
+    RK_S32 all_lossless;
     UCHAR interp_filter;
     UCHAR RefFrameMapTextureIndex[7];
     UINT32 upscaled_width;
     UINT32 frame_to_show_map_idx;
+    UINT32 show_existing_frame;
     UINT32 frame_tag_size;
     UINT32 offset_to_dct_parts;
     UCHAR  skip_ref0;
@@ -225,6 +257,7 @@ typedef struct _DXVA_PicParams_AV1 {
     void         *cdfs;
     void          *cdfs_ndvc;
     RK_U8 tile_cols_log2;
+    RK_U8 tile_rows_log2;
 } DXVA_PicParams_AV1, *LPDXVA_PicParams_AV1;
 
 typedef struct _DXVA_Slice_AV1_Short {
diff --git a/mpp/common/avs2d_syntax.h b/mpp/common/avs2d_syntax.h
index d44bb87c4..76a08a077 100644
--- a/mpp/common/avs2d_syntax.h
+++ b/mpp/common/avs2d_syntax.h
@@ -50,6 +50,7 @@ typedef struct _DXVA_PicParams_AVS2 {
     RK_U32      loop_filter_disable_flag : 1;
     RK_S8       alpha_c_offset;                 //!< 5bits signed
     RK_S8       beta_offset;                    //!< 5bits signed
+    RK_S32      cur_poc;
 } PicParams_Avs2d, *LP_PicParams_Avs2d;
 
 typedef struct _DXVA_RefParams_AVS2 {
diff --git a/mpp/common/h264_syntax.h b/mpp/common/h264_syntax.h
index 4c9474ad8..ac1f85c9a 100644
--- a/mpp/common/h264_syntax.h
+++ b/mpp/common/h264_syntax.h
@@ -94,7 +94,8 @@ typedef enum H264NaluType_e {
     H264_NALU_TYPE_SUB_SPS          = 15,
     H264_NALU_TYPE_SLICE_AUX        = 19,
     H264_NALU_TYPE_SLC_EXT          = 20,   // slice extensive
-    H264_NALU_TYPE_VDRD             = 24    // View and Dependency Representation Delimiter NAL Unit
+    H264_NALU_TYPE_VDRD             = 24,    // View and Dependency Representation Delimiter NAL Unit
+    H264_NALU_TYPE_UNSPECIFIED28    = 28,
 } H264NaluType;
 
 typedef enum H264ChromaFmt_e {
diff --git a/mpp/common/h264d_syntax.h b/mpp/common/h264d_syntax.h
index 0435d2e64..5daabb9c7 100644
--- a/mpp/common/h264d_syntax.h
+++ b/mpp/common/h264d_syntax.h
@@ -419,13 +419,14 @@ typedef struct _DXVA_PicParams_H264_MVC {
     //!< extensive
     RK_U32  spspps_update;
 
-    ////!< for fpga test
-    //USHORT seq_parameter_set_id;
-    //USHORT pps_seq_parameter_set_id;
-    //USHORT profile_idc;
-    //UCHAR  constraint_set3_flag;
-    //UCHAR  qpprime_y_zero_transform_bypass_flag;
-    //UCHAR  mvc_extension_enable;
+    //!< for fpga test
+    RK_U16 seq_parameter_set_id;
+    RK_U16 pps_seq_parameter_set_id;
+    RK_U16 pps_pic_parameter_set_id;
+    RK_U16 profile_idc;
+    RK_U8  constraint_set3_flag;
+    RK_U8  qpprime_y_zero_transform_bypass_flag;
+    RK_U8  mvc_extension_enable;
 
 } DXVA_PicParams_H264_MVC, *LPDXVA_PicParams_H264_MVC;
 
diff --git a/mpp/common/h265d_syntax.h b/mpp/common/h265d_syntax.h
index ab25d9997..96b11fcf1 100644
--- a/mpp/common/h265d_syntax.h
+++ b/mpp/common/h265d_syntax.h
@@ -146,7 +146,21 @@ typedef struct _DXVA_PicParams_HEVC {
             UINT32  IrapPicFlag                                 : 1;
             UINT32  IdrPicFlag                                  : 1;
             UINT32  IntraPicFlag                                : 1;
-            UINT32  ReservedBits4                               : 13;
+            // sps exension flags
+            UINT32  sps_extension_flag                          : 1;
+            UINT32  sps_range_extension_flag                    : 1;
+            UINT32  transform_skip_rotation_enabled_flag        : 1;
+            UINT32  transform_skip_context_enabled_flag         : 1;
+            UINT32  implicit_rdpcm_enabled_flag                 : 1;
+            UINT32  explicit_rdpcm_enabled_flag                 : 1;
+            UINT32  extended_precision_processing_flag          : 1;
+            UINT32  intra_smoothing_disabled_flag               : 1;
+            UINT32  high_precision_offsets_enabled_flag         : 1;
+            UINT32  persistent_rice_adaptation_enabled_flag     : 1;
+            UINT32  cabac_bypass_alignment_enabled_flag         : 1;
+            // pps exension flags
+            UINT32  cross_component_prediction_enabled_flag     : 1;
+            UINT32  chroma_qp_offset_list_enabled_flag          : 1;
         };
         UINT32 dwCodingSettingPicturePropertyFlags;
     };
@@ -178,6 +192,13 @@ typedef struct _DXVA_PicParams_HEVC {
     Short_SPS_RPS_HEVC sps_st_rps[64];
     LT_SPS_RPS_HEVC    sps_lt_rps[32];
 
+    // PPS exentison
+    UCHAR log2_max_transform_skip_block_size;
+    UCHAR diff_cu_chroma_qp_offset_depth;
+    CHAR  cb_qp_offset_list[6];
+    CHAR  cr_qp_offset_list[6];
+    UCHAR chroma_qp_offset_list_len_minus1;
+
     UCHAR  scaling_list_data_present_flag;
     UCHAR  ps_update_flag;
 } DXVA_PicParams_HEVC, *LPDXVA_PicParams_HEVC;
diff --git a/mpp/common/h265e_syntax_new.h b/mpp/common/h265e_syntax_new.h
index d74e23cd2..cd77ac0c7 100644
--- a/mpp/common/h265e_syntax_new.h
+++ b/mpp/common/h265e_syntax_new.h
@@ -194,6 +194,7 @@ typedef struct H265eSlicParams_t {
     RK_U32 sli_splt_byte;
     RK_U32 tot_poc_num;
     RK_U32 non_reference_flag;
+    RK_S32 temporal_id;
 } H265eSlicParams;
 /*
  * Split reference frame configure to two parts
@@ -209,6 +210,7 @@ typedef struct UserDatas_t {
 
 typedef struct H265eSyntax_new_t {
     RK_S32          idr_request;
+    RK_S32          pre_ref_idx;
     H265ePicParams  pp;
     H265eSlicParams sp;
     void            *dpb;
diff --git a/mpp/common/jpege_syntax.h b/mpp/common/jpege_syntax.h
index fe7045dc5..d49087cbf 100644
--- a/mpp/common/jpege_syntax.h
+++ b/mpp/common/jpege_syntax.h
@@ -20,14 +20,36 @@
 #include "mpp_frame.h"
 #include "rk_venc_cmd.h"
 
+#define MAX_NUMBER_OF_COMPONENTS 3
+#define DCT_SIZE 8
+
+typedef enum EntroyTblClass_t {
+    TABLE_DC = 0,
+    TABLE_AC = 1,
+} EntroyTblClass;
+
+typedef union JPEGCompInfo_t {
+    struct {
+        RK_U32 component_id     : 8;
+        RK_U32 h_sample_factor  : 8;
+        RK_U32 v_sample_factor  : 8;
+        RK_U32 tbl_selector     : 8;
+    };
+    RK_U32 val;
+} JPEGCompInfo;
+
 typedef struct JpegeSyntax_t {
     RK_U32              width;
     RK_U32              height;
     RK_U32              hor_stride;
     RK_U32              ver_stride;
-    RK_U32              mcu_w;
-    RK_U32              mcu_h;
+    RK_U32              mcu_hor_cnt;
+    RK_U32              mcu_ver_cnt;
+    RK_U32              mcu_cnt;
+    RK_U32              mcu_width;
+    RK_U32              mcu_height;
     MppFrameFormat      format;
+    MppFrameChromaFormat format_out;
     MppFrameColorSpace  color;
     MppEncRotationCfg   rotation;
     RK_S32              mirroring;
@@ -59,7 +81,6 @@ typedef struct JpegeSyntax_t {
     /* For slice encoding mode */
     RK_U32              slice_enable;
     RK_U32              slice_size_mb_rows;
-    RK_U32              restart_interval;
 
     /*
      * For unit type and density
@@ -82,6 +103,9 @@ typedef struct JpegeSyntax_t {
     RK_U32              low_delay;
     RK_U32              part_rows;
     RK_U32              restart_ri;
+
+    RK_U32              nb_components;
+    JPEGCompInfo        comp_info[MAX_NUMBER_OF_COMPONENTS];
 } JpegeSyntax;
 
 typedef struct JpegeFeedback_t {
diff --git a/mpp/common/vp8e_syntax.h b/mpp/common/vp8e_syntax.h
index 673dcd1a4..9c76c9d6a 100644
--- a/mpp/common/vp8e_syntax.h
+++ b/mpp/common/vp8e_syntax.h
@@ -78,7 +78,7 @@ typedef struct {
     RK_S32 qp_max;
     RK_S32 qp_hdr_prev;
     RK_S32 fps_out_num;     //MppEncRcCfg.fps_out_num
-    RK_S32 fps_out_denorm;  //MppEncRcCfg.fps_out_denorm
+    RK_S32 fps_out_denom;  //MppEncRcCfg.fps_out_denom
     RK_S32 fps_out;
 
     RK_S32 target_pic_size;
diff --git a/mpp/hal/common/CMakeLists.txt b/mpp/hal/common/CMakeLists.txt
index c7e706afa..addb9aeb4 100644
--- a/mpp/hal/common/CMakeLists.txt
+++ b/mpp/hal/common/CMakeLists.txt
@@ -15,3 +15,4 @@ set_target_properties(hal_common PROPERTIES FOLDER "mpp/hal/common")
 add_subdirectory(h264)
 add_subdirectory(h265)
 add_subdirectory(jpeg)
+add_subdirectory(av1)
diff --git a/mpp/hal/common/av1/CMakeLists.txt b/mpp/hal/common/av1/CMakeLists.txt
new file mode 100644
index 000000000..18efffc06
--- /dev/null
+++ b/mpp/hal/common/av1/CMakeLists.txt
@@ -0,0 +1,35 @@
+# vim: syntax=cmake
+include_directories(../../rkdec/av1d/)
+include_directories(../../rkdec/inc/)
+include_directories(../../vpu/av1d/)
+
+# hal h264 header
+set(HAL_AV1D_HDR
+    hal_av1d_common.h
+    )
+
+# hal av1 decoder common
+set(HAL_AV1D_COM_SRC
+    film_grain_noise_table.c
+    )
+
+add_library(hal_av1d_com STATIC
+            ${HAL_AV1D_HDR}
+            ${HAL_AV1D_COM_SRC}
+            )
+
+target_link_libraries(hal_av1d_com mpp_base)
+set_target_properties(hal_av1d_com PROPERTIES FOLDER "mpp/hal")
+
+# hal av1 decoder sourse
+set(HAL_AV1D_SRC
+    hal_av1d_api_v2.c
+    )
+
+add_library(${HAL_AV1D} STATIC
+            ${HAL_AV1D_HDR}
+            ${HAL_AV1D_SRC}
+            )
+
+target_link_libraries(${HAL_AV1D} hal_av1d_rkv hal_av1d_vpu mpp_base)
+set_target_properties(${HAL_AV1D} PROPERTIES FOLDER "mpp/hal")
diff --git a/mpp/hal/vpu/av1d/av1d_common.h b/mpp/hal/common/av1/av1d_common.h
similarity index 98%
rename from mpp/hal/vpu/av1d/av1d_common.h
rename to mpp/hal/common/av1/av1d_common.h
index 01e6066ab..dda5858d3 100644
--- a/mpp/hal/vpu/av1d/av1d_common.h
+++ b/mpp/hal/common/av1/av1d_common.h
@@ -29,6 +29,10 @@
 #define AV1_MAX_TILE_COL 64
 #define AV1_MAX_TILE_ROW 64
 
+// Pixels per Mode Info (MI) unit
+#define MI_SIZE_LOG2 2
+#define MI_SIZE (1 << MI_SIZE_LOG2)
+
 #define AV1_MIN_COMP_BASIS 8
 #define AV1_MAX_CODED_FRAME_SIZE \
   (8192 * 4352 * 10 * 6 / 32 / AV1_MIN_COMP_BASIS) /* approx 8 MB */
@@ -214,6 +218,14 @@ typedef RK_U8 av1_coeff_probs[REF_TYPES][COEF_BANDS][PREV_COEF_CONTEXTS]
 
 typedef RK_U16 av1_cdf;
 
+// Frame Restoration types (section 6.10.15)
+enum {
+    AV1_RESTORE_NONE       = 0,
+    AV1_RESTORE_WIENER     = 1,
+    AV1_RESTORE_SGRPROJ    = 2,
+    AV1_RESTORE_SWITCHABLE = 3,
+};
+
 enum BlockSizeType {
     BLOCK_SIZE_AB4X4,
     BLOCK_SIZE_SB4X8,
@@ -263,6 +275,8 @@ enum PartitionType {
 enum FrameType {
     KEY_FRAME = 0,
     INTER_FRAME = 1,
+    INTRA_ONLY_FRAME = 2,  // replaces intra-only
+    S_FRAME = 3,
     NUM_FRAME_TYPES,
 };
 
@@ -371,12 +385,9 @@ enum CompPredModeType {
 
 enum TxfmMode {
     ONLY_4X4 = 0,
-    ALLOW_8X8 = 1,
-    ALLOW_16X16 = 2,
-    ALLOW_32X32 = 3,
-    TX_MODE_LARGEST = ALLOW_32X32,  // AV1
-    TX_MODE_SELECT = 4,
-    NB_TXFM_MODES = 5,
+    TX_MODE_LARGEST,
+    TX_MODE_SELECT,
+    NB_TXFM_MODES,
 };
 
 enum SegLevelFeatures {
diff --git a/mpp/hal/vpu/av1d/film_grain_noise_table.c b/mpp/hal/common/av1/film_grain_noise_table.c
similarity index 100%
rename from mpp/hal/vpu/av1d/film_grain_noise_table.c
rename to mpp/hal/common/av1/film_grain_noise_table.c
diff --git a/mpp/hal/vpu/av1d/film_grain_noise_table.h b/mpp/hal/common/av1/film_grain_noise_table.h
similarity index 100%
rename from mpp/hal/vpu/av1d/film_grain_noise_table.h
rename to mpp/hal/common/av1/film_grain_noise_table.h
diff --git a/mpp/hal/vpu/av1d/hal_av1d_api.c b/mpp/hal/common/av1/hal_av1d_api_v2.c
similarity index 91%
rename from mpp/hal/vpu/av1d/hal_av1d_api.c
rename to mpp/hal/common/av1/hal_av1d_api_v2.c
index 781404324..f9ca5924c 100644
--- a/mpp/hal/vpu/av1d/hal_av1d_api.c
+++ b/mpp/hal/common/av1/hal_av1d_api_v2.c
@@ -31,6 +31,7 @@
 
 #include "hal_av1d_vdpu_reg.h"
 #include "hal_av1d_vdpu.h"
+#include "hal_av1d_vdpu383.h"
 #include "hal_av1d_common.h"
 
 RK_U32 hal_av1d_debug = 0;
@@ -40,19 +41,26 @@ MPP_RET hal_av1d_init(void *hal, MppHalCfg *cfg)
     MPP_RET ret         = MPP_OK;
     Av1dHalCtx *p_hal   = (Av1dHalCtx *)hal;
     RK_U32 vcodec_type  = mpp_get_vcodec_type();
-    MppClientType type  = VPU_CLIENT_AV1DEC;
+    MppClientType type  = VPU_CLIENT_RKVDEC;
+    RK_U32 hw_id = 0;
 
     INP_CHECK(ret, NULL == p_hal);
     memset(p_hal, 0, sizeof(Av1dHalCtx));
     mpp_env_get_u32("hal_av1d_debug", &hal_av1d_debug, 0);
 
     // check codec_type first
-    if (!(vcodec_type & (HAVE_RKVDEC | HAVE_VDPU1 | HAVE_VDPU2))) {
+    if (!(vcodec_type & (HAVE_RKVDEC | HAVE_AV1DEC))) {
         mpp_err_f("can not found av1 decoder hardware on platform %x\n", vcodec_type);
         return ret;
     }
 
-    p_hal->api = &hal_av1d_vdpu;
+    hw_id = mpp_get_client_hw_id(type);
+    if (hw_id == HWID_VDPU383) {
+        p_hal->api = &hal_av1d_vdpu383;
+    } else {
+        p_hal->api = &hal_av1d_vdpu;
+        type  = VPU_CLIENT_AV1DEC;
+    }
 
     //!< callback function to parser module
     p_hal->dec_cb = cfg->dec_cb;
@@ -62,6 +70,8 @@ MPP_RET hal_av1d_init(void *hal, MppHalCfg *cfg)
         mpp_err("mpp_dev_init failed ret: %d\n", ret);
         goto __FAILED;
     }
+    cfg->hw_info = mpp_get_dec_hw_info_by_client_type(type);
+    p_hal->hw_info = cfg->hw_info;
 
     //< get buffer group
     if (p_hal->buf_group == NULL) {
diff --git a/mpp/hal/vpu/av1d/hal_av1d_common.h b/mpp/hal/common/av1/hal_av1d_common.h
similarity index 98%
rename from mpp/hal/vpu/av1d/hal_av1d_common.h
rename to mpp/hal/common/av1/hal_av1d_common.h
index cda674516..63cee11f4 100644
--- a/mpp/hal/vpu/av1d/hal_av1d_common.h
+++ b/mpp/hal/common/av1/hal_av1d_common.h
@@ -34,7 +34,6 @@
 
 extern RK_U32 hal_av1d_debug;
 
-
 #define AV1D_DBG(level, fmt, ...)\
 do {\
     if (level & hal_av1d_debug)\
@@ -189,6 +188,7 @@ typedef struct av1d_hal_ctx_t {
     MppDev                   dev;
     void                     *reg_ctx;
     RK_U32                   fast_mode;
+    const MppDecHwCap       *hw_info;
 } Av1dHalCtx;
 
-#endif /*__HAL_AV1D_GLOBAL_H__*/
+#endif /* __HAL_AV1D_GLOBAL_H__ */
diff --git a/mpp/hal/common/h264/CMakeLists.txt b/mpp/hal/common/h264/CMakeLists.txt
index e258347fa..52c64b900 100644
--- a/mpp/hal/common/h264/CMakeLists.txt
+++ b/mpp/hal/common/h264/CMakeLists.txt
@@ -9,10 +9,22 @@ include_directories(../../../codec/enc/h264/)
 set(HAL_H264E_HDR
     )
 
+# hal h264 encoder common
+set(HAL_H264E_COM_SRC
+    hal_h264e_stream_amend.c
+    )
+
+add_library(hal_h264e_com STATIC
+            ${HAL_H264E_HDR}
+            ${HAL_H264E_COM_SRC}
+            )
+
+target_link_libraries(hal_h264e_com mpp_base)
+set_target_properties(hal_h264e_com PROPERTIES FOLDER "mpp/hal")
+
 # hal h264 encoder sourse
 set(HAL_H264E_SRC
     hal_h264e_api_v2.c
-    hal_h264e_stream_amend.c
     )
 
 add_library(hal_h264e STATIC
diff --git a/mpp/hal/common/h264/hal_h264e_api_v2.c b/mpp/hal/common/h264/hal_h264e_api_v2.c
index c5ccbd2e2..5d56ca8dd 100644
--- a/mpp/hal/common/h264/hal_h264e_api_v2.c
+++ b/mpp/hal/common/h264/hal_h264e_api_v2.c
@@ -33,6 +33,7 @@
 #include "hal_h264e_vepu541.h"
 #include "hal_h264e_vepu580.h"
 #include "hal_h264e_vepu540c.h"
+#include "hal_h264e_vepu510.h"
 
 typedef struct HalH264eCtx_t {
     const MppEncHalApi  *api;
@@ -61,6 +62,9 @@ static MPP_RET hal_h264e_init(void *hal, MppEncHalCfg *cfg)
         case HWID_VEPU540C : {
             api = &hal_h264e_vepu540c;
         } break;
+        case HWID_VEPU510 : {
+            api = &hal_h264e_vepu510;
+        } break;
         default : {
             api = &hal_h264e_vepu541;
         } break;
diff --git a/mpp/hal/common/h264/hal_h264e_stream_amend.c b/mpp/hal/common/h264/hal_h264e_stream_amend.c
index 1276a3541..659e7fba0 100644
--- a/mpp/hal/common/h264/hal_h264e_stream_amend.c
+++ b/mpp/hal/common/h264/hal_h264e_stream_amend.c
@@ -109,7 +109,6 @@ MPP_RET h264e_vepu_stream_amend_config(HalH264eVepuStreamAmend *ctx,
         hw_cfg->hw_log2_max_frame_num_minus4 != h264->log2_max_frame_num) {
         ctx->enable = 1;
         ctx->slice_enabled = 0;
-        ctx->diable_split_out = 1;
 
         if (NULL == ctx->dst_buf)
             ctx->dst_buf = mpp_calloc(RK_U8, ctx->buf_size);
@@ -156,9 +155,17 @@ MPP_RET h264e_vepu_stream_amend_proc(HalH264eVepuStreamAmend *ctx, MppEncH264HwC
     RK_S32 final_len = 0;
     RK_S32 last_slice = 0;
     const MppPktSeg *seg = mpp_packet_get_segment_info(pkt);
+    MppPacket pkt_tmp;
+    RK_S32 offset = 0;
+    RK_U32 is_cabac = ctx->slice->entropy_coding_mode;
+
+    mpp_packet_new(&pkt_tmp);
 
     if (seg) {
         while (seg && seg->type != 1 && seg->type != 5) {
+            mpp_packet_add_segment_info(pkt_tmp, seg->type, offset, seg->len);
+            offset += seg->len;
+
             seg = seg->next;
         }
     }
@@ -193,10 +200,11 @@ MPP_RET h264e_vepu_stream_amend_proc(HalH264eVepuStreamAmend *ctx, MppEncH264HwC
 
     do {
         RK_U32 nal_len = 0;
+
         tail_0bit = 0;
         // copy hw stream to stream buffer first
         if (slice->is_multi_slice) {
-            if ((!seg) || ctx->diable_split_out) {
+            if ((!seg) || !hw_cfg->hw_split_out || !is_cabac) {
                 nal_len = get_next_nal(p, &len);
                 last_slice = (len == 0);
             } else {
@@ -226,6 +234,9 @@ MPP_RET h264e_vepu_stream_amend_proc(HalH264eVepuStreamAmend *ctx, MppEncH264HwC
             dst_buf += prefix_bit;
             buf_size -= prefix_bit;
             final_len += prefix_bit;
+
+            mpp_packet_add_segment_info(pkt_tmp, H264_NALU_TYPE_PREFIX, offset, prefix_bit);
+            offset += prefix_bit;
         }
 
         H264eSlice slice_rd;
@@ -302,6 +313,13 @@ MPP_RET h264e_vepu_stream_amend_proc(HalH264eVepuStreamAmend *ctx, MppEncH264HwC
             final_len += new_len;
         }
 
+        {
+            H264NaluType type = slice->idr_flag ?  H264_NALU_TYPE_IDR : H264_NALU_TYPE_SLICE;
+
+            mpp_packet_add_segment_info(pkt_tmp, type, offset, nal_len);
+            offset += nal_len;
+        }
+
         if (last_slice) {
             p = mpp_packet_get_pos(pkt);
             p += base;
@@ -322,6 +340,11 @@ MPP_RET h264e_vepu_stream_amend_proc(HalH264eVepuStreamAmend *ctx, MppEncH264HwC
 
     ctx->new_length = final_len;
 
+    /* update segment */
+    mpp_packet_copy_segment_info(pkt, pkt_tmp);
+
+    mpp_packet_deinit(&pkt_tmp);
+
     return MPP_OK;
 }
 
diff --git a/mpp/hal/common/h264/hal_h264e_stream_amend.h b/mpp/hal/common/h264/hal_h264e_stream_amend.h
index 9630572b8..dd370ce83 100644
--- a/mpp/hal/common/h264/hal_h264e_stream_amend.h
+++ b/mpp/hal/common/h264/hal_h264e_stream_amend.h
@@ -29,14 +29,15 @@ typedef struct HalH264eVepuStreamAmend_t {
     H264eMarkingInfo *marking;
 
     RK_S32           slice_enabled;
-    RK_S32           diable_split_out;
 
     RK_U8            *src_buf;
     RK_U8            *dst_buf;
     RK_S32           buf_size;
 
     MppPacket        packet;
+    /* sw length */
     RK_S32           buf_base;
+    /* hw length */
     RK_S32           old_length;
     RK_S32           new_length;
 } HalH264eVepuStreamAmend;
diff --git a/mpp/hal/common/h265/CMakeLists.txt b/mpp/hal/common/h265/CMakeLists.txt
index 008050854..19f6503a7 100644
--- a/mpp/hal/common/h265/CMakeLists.txt
+++ b/mpp/hal/common/h265/CMakeLists.txt
@@ -7,6 +7,19 @@ include_directories(../../rkenc/common/)
 set(HAL_H265E_HDR
     )
 
+# hal h265 encoder common
+set(HAL_H265E_COM_SRC
+    hal_h265e_stream_amend.c
+    )
+
+add_library(hal_h265e_com STATIC
+            ${HAL_H265E_HDR}
+            ${HAL_H265E_COM_SRC}
+            )
+
+target_link_libraries(hal_h265e_com hal_h265e_vepu541 mpp_base)
+set_target_properties(hal_h265e_com PROPERTIES FOLDER "mpp/hal")
+
 # hal h265 encoder sourse
 set(HAL_H265E_SRC
     hal_h265e_api_v2.c
diff --git a/mpp/hal/common/h265/hal_h265e_api_v2.c b/mpp/hal/common/h265/hal_h265e_api_v2.c
index 164917d74..c7a62bbd9 100644
--- a/mpp/hal/common/h265/hal_h265e_api_v2.c
+++ b/mpp/hal/common/h265/hal_h265e_api_v2.c
@@ -30,6 +30,7 @@
 #include "hal_h265e_vepu541.h"
 #include "hal_h265e_vepu580.h"
 #include "hal_h265e_vepu540c.h"
+#include "hal_h265e_vepu510.h"
 
 typedef struct HalH265eV2Ctx_t {
     const MppEncHalApi  *api;
@@ -56,6 +57,9 @@ static MPP_RET hal_h265ev2_init(void *hal, MppEncHalCfg *cfg)
         case HWID_VEPU540C : {
             api = &hal_h265e_vepu540c;
         } break;
+        case HWID_VEPU510 : {
+            api = &hal_h265e_vepu510;
+        } break;
         default : {
             api = &hal_h265e_vepu541;
         } break;
diff --git a/mpp/hal/common/h265/hal_h265e_stream_amend.c b/mpp/hal/common/h265/hal_h265e_stream_amend.c
new file mode 100644
index 000000000..2ae0235ee
--- /dev/null
+++ b/mpp/hal/common/h265/hal_h265e_stream_amend.c
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: Apache-2.0 OR MIT */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#include "hal_h265e_stream_amend.h"
+
+#include "mpp_common.h"
+#include "mpp_log.h"
+
+MPP_RET hal_h265e_amend_temporal_id(HalEncTask *enc_task, RK_U32 strm_size)
+{
+    MPP_RET ret = MPP_OK;
+    H265eSyntax_new *syn = (H265eSyntax_new *)enc_task->syntax.data;
+    RK_U32 offset = mpp_packet_get_length(enc_task->packet);
+    RK_U8 *stream_ptr = (RK_U8 *)(mpp_buffer_get_ptr(enc_task->output) + offset);
+
+    if (strm_size < 5) {
+        mpp_err("Stream size is too small, maybe there is hw encoder error!");
+        return MPP_NOK;
+    }
+
+    if (syn->sp.temporal_id)
+        stream_ptr[5] = (stream_ptr[5] & 0xf8) | ((syn->sp.temporal_id + 1) & 0x7);
+
+    return ret;
+}
\ No newline at end of file
diff --git a/mpp/hal/common/h265/hal_h265e_stream_amend.h b/mpp/hal/common/h265/hal_h265e_stream_amend.h
new file mode 100644
index 000000000..087d0f4ab
--- /dev/null
+++ b/mpp/hal/common/h265/hal_h265e_stream_amend.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: Apache-2.0 OR MIT */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef __HAL_H265E_STREAM_AMEND_H__
+#define __HAL_H265E_STREAM_AMEND_H__
+
+#include "hal_enc_task.h"
+#include "h265e_syntax_new.h"
+
+MPP_RET hal_h265e_amend_temporal_id(HalEncTask *enc_task, RK_U32 strm_size);
+
+#endif /* __HAL_H265E_STREAM_AMEND_H__ */
\ No newline at end of file
diff --git a/mpp/hal/common/hal_info.c b/mpp/hal/common/hal_info.c
index 69a323e97..a5d7138d5 100644
--- a/mpp/hal/common/hal_info.c
+++ b/mpp/hal/common/hal_info.c
@@ -234,14 +234,14 @@ RK_U64 hal_info_to_string(HalInfo ctx, RK_U32 type, void *val)
     return ret;
 }
 
-RK_U64 hal_info_to_float(RK_S32 num, RK_S32 denorm)
+RK_U64 hal_info_to_float(RK_S32 num, RK_S32 denom)
 {
     RK_U64 ret = 0;
 
-    if (!denorm)
+    if (!denom)
         snprintf((void *)&ret, sizeof(ret) - 1, "%d", num);
     else
-        snprintf((void *)&ret, sizeof(ret) - 1, "%.2f", (float)num / denorm);
+        snprintf((void *)&ret, sizeof(ret) - 1, "%.2f", (float)num / denom);
 
     return ret;
 }
@@ -262,9 +262,9 @@ MPP_RET hal_info_from_enc_cfg(HalInfo ctx, MppEncCfgSet *cfg)
 
     hal_info_set(ctx, ENC_INFO_FORMAT, CODEC_INFO_FLAG_STRING, val);
     hal_info_set(ctx, ENC_INFO_FPS_IN, CODEC_INFO_FLAG_NUMBER,
-                 rc->fps_in_num / rc->fps_in_denorm);
+                 rc->fps_in_num / rc->fps_in_denom);
     hal_info_set(ctx, ENC_INFO_FPS_OUT, CODEC_INFO_FLAG_NUMBER,
-                 rc->fps_out_num / rc->fps_out_denorm);
+                 rc->fps_out_num / rc->fps_out_denom);
 
     val = hal_info_to_string(ctx, ENC_INFO_RC_MODE, &rc->rc_mode);
     hal_info_set(ctx, ENC_INFO_RC_MODE, CODEC_INFO_FLAG_STRING, val);
diff --git a/mpp/hal/common/hal_info.h b/mpp/hal/common/hal_info.h
index 661719fb0..7737169bb 100644
--- a/mpp/hal/common/hal_info.h
+++ b/mpp/hal/common/hal_info.h
@@ -64,7 +64,7 @@ MPP_RET hal_info_set(HalInfo ctx, RK_U32 type, RK_U32 flag, RK_U64 data);
 MPP_RET hal_info_get(HalInfo ctx, MppDevInfoCfg *data, RK_S32 *size);
 
 RK_U64 hal_info_to_string(HalInfo ctx, RK_U32 type, void *val);
-RK_U64 hal_info_to_float(RK_S32 num, RK_S32 denorm);
+RK_U64 hal_info_to_float(RK_S32 num, RK_S32 denom);
 
 MPP_RET hal_info_from_enc_cfg(HalInfo ctx, MppEncCfgSet *cfg);
 
diff --git a/mpp/hal/common/jpeg/CMakeLists.txt b/mpp/hal/common/jpeg/CMakeLists.txt
index 3f9923f53..38a9f4bfb 100644
--- a/mpp/hal/common/jpeg/CMakeLists.txt
+++ b/mpp/hal/common/jpeg/CMakeLists.txt
@@ -8,10 +8,22 @@ include_directories(../../vpu/jpege/)
 set(HAL_JPEGE_HDR
     )
 
+# hal h264 encoder common
+set(HAL_JPEGE_SRC
+    hal_jpege_hdr.c
+    )
+
+add_library(hal_jpege_com STATIC
+            ${HAL_JPEGE_HDR}
+            ${HAL_JPEGE_SRC}
+            )
+
+target_link_libraries(hal_jpege_com mpp_base)
+set_target_properties(hal_jpege_com PROPERTIES FOLDER "mpp/hal")
+
 # hal h264 encoder sourse
 set(HAL_JPEGE_SRC
     hal_jpege_api_v2.c
-    hal_jpege_hdr.c
     )
 
 add_library(hal_jpege STATIC
diff --git a/mpp/hal/common/jpeg/hal_jpege_api_v2.c b/mpp/hal/common/jpeg/hal_jpege_api_v2.c
index 07cfe610f..d943f9afd 100644
--- a/mpp/hal/common/jpeg/hal_jpege_api_v2.c
+++ b/mpp/hal/common/jpeg/hal_jpege_api_v2.c
@@ -31,6 +31,7 @@
 #include "hal_jpege_vepu1_v2.h"
 #include "hal_jpege_vepu2_v2.h"
 #include "hal_jpege_vepu540c.h"
+#include "hal_jpege_vpu720.h"
 
 typedef struct HaljpegeCtx_t {
     const MppEncHalApi  *api;
@@ -56,6 +57,8 @@ static MPP_RET hal_jpege_init(void *hal, MppEncHalCfg *cfg)
         api = &hal_jpege_vepu2;
     } else if (vcodec_type & HAVE_VEPU1) {
         api = &hal_jpege_vepu1;
+    } else if (vcodec_type & HAVE_JPEG_ENC) {
+        api = &hal_jpege_vpu720;
     } else {
         mpp_err("vcodec type %08x can not find JPEG encoder device\n",
                 vcodec_type);
diff --git a/mpp/hal/common/jpeg/hal_jpege_hdr.c b/mpp/hal/common/jpeg/hal_jpege_hdr.c
index defa03a54..bda623c9d 100644
--- a/mpp/hal/common/jpeg/hal_jpege_hdr.c
+++ b/mpp/hal/common/jpeg/hal_jpege_hdr.c
@@ -20,8 +20,6 @@
 
 #include "hal_jpege_hdr.h"
 
-#define MAX_NUMBER_OF_COMPONENTS 3
-
 /* JPEG markers, table B.1 */
 enum {
     SOI = 0xFFD8,   /* Start of Image                    */
@@ -320,23 +318,6 @@ typedef struct {
     RK_U32 Tqi[MAX_NUMBER_OF_COMPONENTS];
 } JpegeColorInfo;
 
-static const JpegeColorInfo color_info[2] = {
-    {
-        /* YUV420 */
-        {   1,  2,  3,  },
-        {   2,  1,  1,  },
-        {   2,  1,  1,  },
-        {   0,  1,  1,  },
-    },
-    {
-        /* YUV422 */
-        {   1,  2,  3,  },
-        {   2,  1,  1,  },
-        {   1,  1,  1,  },
-        {   0,  1,  1,  },
-    },
-};
-
 typedef struct {
     RK_U32  val_y;
     RK_U32  val_c;
@@ -691,10 +672,9 @@ static void write_jpeg_comment_header(JpegeBits *bits, JpegeSyntax *syntax)
     }
 }
 
-static void write_jpeg_dqt_header(JpegeBits *bits, const RK_U8 *qtables[2])
+static void write_jpeg_dqt_header(JpegeBits *bits, const RK_U8 *qtable, RK_U32 tbl_idx)
 {
     RK_S32 i;
-    const RK_U8 *qtable = qtables[0];
 
     /* DQT */
     jpege_bits_put(bits, DQT, 16);
@@ -703,42 +683,25 @@ static void write_jpeg_dqt_header(JpegeBits *bits, const RK_U8 *qtables[2])
     /* Pq */
     jpege_bits_put(bits, 0, 4);
     /* Tq */
-    jpege_bits_put(bits, 0, 4);
+    jpege_bits_put(bits, tbl_idx, 4);
 
     for (i = 0; i < 64; i++) {
         /* Qk table 0 */
         jpege_bits_put(bits, qtable[zigzag[i]], 8);
     }
-
-    /* DQT */
-    jpege_bits_put(bits, DQT, 16);
-    /* Lq */
-    jpege_bits_put(bits, 2 + 65, 16);
-    /* Pq */
-    jpege_bits_put(bits, 0, 4);
-    /* Tq */
-    jpege_bits_put(bits, 1, 4);
-
-    qtable = qtables[1];
-
-    for (i = 0; i < 64; i++) {
-        /* Qk table 1 */
-        jpege_bits_put(bits, qtable[zigzag[i]], 8);
-    }
 }
 
 static void write_jpeg_SOFO_header(JpegeBits *bits, JpegeSyntax *syntax)
 {
-    RK_S32 i;
+    RK_U32 i;
     RK_U32 width = syntax->width;
     RK_U32 height = syntax->height;
-    const JpegeColorInfo *info = &color_info[0];
 
     /* SOF0 */
     jpege_bits_put(bits, SOF0, 16);
 
     /* Lf */
-    jpege_bits_put(bits, (8 + 3 * 3), 16);
+    jpege_bits_put(bits, (8 + 3 * syntax->nb_components), 16);
     /* P */
     jpege_bits_put(bits, 8, 8);
     /* Y */
@@ -746,22 +709,21 @@ static void write_jpeg_SOFO_header(JpegeBits *bits, JpegeSyntax *syntax)
     /* X */
     jpege_bits_put(bits, width, 16);
     /* Nf */
-    jpege_bits_put(bits, 3, 8);
+    jpege_bits_put(bits, syntax->nb_components, 8);
 
-    /* NOTE: only output 420 bits */
-    for (i = 0; i < 3; i++) {
+    for (i = 0; i < syntax->nb_components; i++) {
         /* Ci */
-        jpege_bits_put(bits, info->Ci[i], 8);
+        jpege_bits_put(bits, syntax->comp_info[i].component_id, 8);
         /* Hi */
-        jpege_bits_put(bits, info->Hi[i], 4);
+        jpege_bits_put(bits, syntax->comp_info[i].h_sample_factor, 4);
         /* Vi */
-        jpege_bits_put(bits, info->Vi[i], 4);
+        jpege_bits_put(bits, syntax->comp_info[i].v_sample_factor, 4);
         /* Tqi */
-        jpege_bits_put(bits, info->Tqi[i], 8);
+        jpege_bits_put(bits, syntax->comp_info[i].tbl_selector, 8);
     }
 }
 
-static void write_jpeg_dht_header(JpegeBits *bits)
+static void write_jpeg_dht_header(JpegeBits *bits, JpegeSyntax *syntax)
 {
     RK_S32 i;
 
@@ -772,9 +734,9 @@ static void write_jpeg_dht_header(JpegeBits *bits)
     /* Lh  */
     jpege_bits_put(bits, 2 + ((17 * 1) + ((1 * 12))), 16);
     /* TC */
-    jpege_bits_put(bits, 0, 4);
+    jpege_bits_put(bits, TABLE_DC, 4);
     /* TH */
-    jpege_bits_put(bits, 0, 4);
+    jpege_bits_put(bits, syntax->comp_info[0].tbl_selector, 4);
 
     for (i = 0; i < 16; i++) {
         /* Dc_Li */
@@ -793,9 +755,9 @@ static void write_jpeg_dht_header(JpegeBits *bits)
     /* Lh */
     jpege_bits_put(bits, 2 + ((17 * 1) + ((1 * 162))), 16);
     /* TC */
-    jpege_bits_put(bits, 1, 4);
+    jpege_bits_put(bits, TABLE_AC, 4);
     /* TH */
-    jpege_bits_put(bits, 0, 4);
+    jpege_bits_put(bits, syntax->comp_info[0].tbl_selector, 4);
 
     for (i = 0; i < 16; i++) {
         /* Ac_Li */
@@ -807,15 +769,18 @@ static void write_jpeg_dht_header(JpegeBits *bits)
         jpege_bits_put(bits, ac_vij[i].val_y, 8);
     }
 
+    if (syntax->nb_components == 1)
+        return;
+
     /* Huffman table for chrominance DC components */
     /* DHT  */
     jpege_bits_put(bits, DHT, 16);
     /* Lh */
     jpege_bits_put(bits, 2 + ((17 * 1) + ((1 * 12))), 16);
     /* TC */
-    jpege_bits_put(bits, 0, 4);
+    jpege_bits_put(bits, TABLE_DC, 4);
     /* TH */
-    jpege_bits_put(bits, 1, 4);
+    jpege_bits_put(bits, syntax->comp_info[1].tbl_selector, 4);
 
     for (i = 0; i < 16; i++) {
         /* Dc_Li */
@@ -833,9 +798,9 @@ static void write_jpeg_dht_header(JpegeBits *bits)
     /* Lh */
     jpege_bits_put(bits, 2 + ((17 * 1) + ((1 * 162))), 16);
     /* TC */
-    jpege_bits_put(bits, 1, 4);
+    jpege_bits_put(bits, TABLE_AC, 4);
     /* TH */
-    jpege_bits_put(bits, 1, 4);
+    jpege_bits_put(bits, syntax->comp_info[1].tbl_selector, 4);
 
     for (i = 0; i < 16; i++) {
         /* Ac_Li */
@@ -848,10 +813,10 @@ static void write_jpeg_dht_header(JpegeBits *bits)
     }
 }
 
-static void write_jpeg_sos_header(JpegeBits *bits)
+static void write_jpeg_sos_header(JpegeBits *bits, JpegeSyntax *syntax)
 {
     RK_U32 i;
-    RK_U32 Ns = 3;
+    RK_U32 Ns = syntax->nb_components;
     RK_U32 Ls = (6 + (2 * Ns));
 
     /* SOS  */
@@ -863,19 +828,11 @@ static void write_jpeg_sos_header(JpegeBits *bits)
 
     for (i = 0; i < Ns; i++) {
         /* Csj */
-        jpege_bits_put(bits, i + 1, 8);
-
-        if (i == 0) {
-            /* Tdj */
-            jpege_bits_put(bits, 0, 4);
-            /* Taj */
-            jpege_bits_put(bits, 0, 4);
-        } else {
-            /* Tdj */
-            jpege_bits_put(bits, 1, 4);
-            /* Taj */
-            jpege_bits_put(bits, 1, 4);
-        }
+        jpege_bits_put(bits, syntax->comp_info[i].component_id, 8);
+        /* Tdj */
+        jpege_bits_put(bits, syntax->comp_info[i].tbl_selector, 4);
+        /* Taj */
+        jpege_bits_put(bits, syntax->comp_info[i].tbl_selector, 4);
     }
 
     /* Ss */
@@ -900,6 +857,9 @@ void write_jpeg_RestartInterval(JpegeBits *bits, JpegeSyntax *syntax)
 
 MPP_RET write_jpeg_header(JpegeBits *bits, JpegeSyntax *syntax, const RK_U8 *qtables[2])
 {
+    RK_U32 i = 0;
+    RK_U32 qtable_number = syntax->nb_components == 1 ? 1 : 2;
+
     /* Com header */
     if (syntax->comment_length)
         write_jpeg_comment_header(bits, syntax);
@@ -919,7 +879,8 @@ MPP_RET write_jpeg_header(JpegeBits *bits, JpegeSyntax *syntax, const RK_U8 *qta
             qtables[1] = qtable_c[syntax->quality];
     }
 
-    write_jpeg_dqt_header(bits, qtables);
+    for (i = 0; i < qtable_number; i++)
+        write_jpeg_dqt_header(bits, qtables[i], i);
 
     /* Frame header */
     write_jpeg_SOFO_header(bits, syntax);
@@ -928,10 +889,10 @@ MPP_RET write_jpeg_header(JpegeBits *bits, JpegeSyntax *syntax, const RK_U8 *qta
     write_jpeg_RestartInterval(bits, syntax);
 
     /* Huffman header */
-    write_jpeg_dht_header(bits);
+    write_jpeg_dht_header(bits, syntax);
 
     /* Scan header */
-    write_jpeg_sos_header(bits);
+    write_jpeg_sos_header(bits, syntax);
 
     jpege_bits_align_byte(bits);
     return MPP_OK;
diff --git a/mpp/hal/inc/hal_enc_task.h b/mpp/hal/inc/hal_enc_task.h
index ce277163b..fe398b489 100644
--- a/mpp/hal/inc/hal_enc_task.h
+++ b/mpp/hal/inc/hal_enc_task.h
@@ -115,6 +115,7 @@ typedef union EncAsyncStatus_u {
 
         RK_U32      hal_task_reset_rdy  : 1;    // reset hal task to start
         RK_U32      rc_check_frm_drop   : 1;    // rc  stage
+        RK_U32      check_frm_pskip     : 1;    // pskip frame check
         RK_U32      pkt_buf_rdy         : 1;    // prepare pkt buf
 
         RK_U32      enc_start           : 1;    // enc stage
diff --git a/mpp/hal/inc/hal_h264d_api.h b/mpp/hal/inc/hal_h264d_api.h
index fe2e92d41..0cde979dd 100644
--- a/mpp/hal/inc/hal_h264d_api.h
+++ b/mpp/hal/inc/hal_h264d_api.h
@@ -31,15 +31,6 @@ extern "C" {
 
 extern const MppHalApi hal_api_h264d;
 
-MPP_RET hal_h264d_init    (void *hal, MppHalCfg *cfg);
-MPP_RET hal_h264d_deinit  (void *hal);
-MPP_RET hal_h264d_gen_regs(void *hal, HalTaskInfo *task);
-MPP_RET hal_h264d_start   (void *hal, HalTaskInfo *task);
-MPP_RET hal_h264d_wait    (void *hal, HalTaskInfo *task);
-MPP_RET hal_h264d_reset   (void *hal);
-MPP_RET hal_h264d_flush   (void *hal);
-MPP_RET hal_h264d_control (void *hal, MpiCmd cmd_type, void *param);
-
 #ifdef __cplusplus
 }
 #endif
diff --git a/mpp/hal/rkdec/CMakeLists.txt b/mpp/hal/rkdec/CMakeLists.txt
index ea0fcd1b0..982c2cb8a 100644
--- a/mpp/hal/rkdec/CMakeLists.txt
+++ b/mpp/hal/rkdec/CMakeLists.txt
@@ -2,6 +2,7 @@
 include_directories(inc)
 
 add_library(vdpu34x_com STATIC vdpu34x_com.c vdpu382_com.c)
+add_library(vdpu383_com STATIC vdpu383_com.c)
 
 if( HAVE_AVSD )
     add_subdirectory(avsd)
@@ -22,3 +23,7 @@ endif()
 if( HAVE_VP9D )
     add_subdirectory(vp9d)
 endif()
+
+if( HAVE_AV1D )
+    add_subdirectory(av1d)
+endif()
\ No newline at end of file
diff --git a/mpp/hal/rkdec/av1d/CMakeLists.txt b/mpp/hal/rkdec/av1d/CMakeLists.txt
new file mode 100644
index 000000000..201ac395d
--- /dev/null
+++ b/mpp/hal/rkdec/av1d/CMakeLists.txt
@@ -0,0 +1,22 @@
+# vim: syntax=cmake
+# hal av1 reg
+
+include_directories(../../common/av1)
+
+set(HAL_AV1D_HDR
+    ../../common/av1/hal_av1d_common.h
+    )
+
+set(HAL_AV1D_SRC
+    hal_av1d_vdpu383.c
+    )
+
+add_library(hal_av1d_rkv STATIC
+            ${HAL_AV1D_SRC}
+            ${HAL_AV1D_HDR}
+            )
+
+set_target_properties(hal_av1d_rkv PROPERTIES FOLDER "mpp/hal")
+target_link_libraries(hal_av1d_rkv mpp_base)
+
+#add_subdirectory(test)
diff --git a/mpp/hal/rkdec/av1d/hal_av1d_vdpu383.c b/mpp/hal/rkdec/av1d/hal_av1d_vdpu383.c
new file mode 100644
index 000000000..4978cf2a6
--- /dev/null
+++ b/mpp/hal/rkdec/av1d/hal_av1d_vdpu383.c
@@ -0,0 +1,2721 @@
+/* SPDX-License-Identifier: Apache-2.0 OR MIT */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#define MODULE_TAG "hal_av1d_vdpu383"
+
+#include <string.h>
+
+#include "mpp_env.h"
+#include "mpp_mem.h"
+#include "mpp_bitput.h"
+#include "mpp_buffer_impl.h"
+
+// #include "av1.h"
+#include "hal_av1d_vdpu383_reg.h"
+#include "hal_av1d_common.h"
+#include "vdpu383_com.h"
+
+#include "av1d_syntax.h"
+#include "film_grain_noise_table.h"
+#include "av1d_common.h"
+
+#define VDPU383_UNCMPS_HEADER_SIZE            (MPP_ALIGN(5159, 128) / 8) // byte, 5159 bit
+
+// bits len
+#define VDPU383_RCB_STRMD_ROW_LEN             (MPP_ALIGN(dxva->width, 8) / 8 * 100)
+#define VDPU383_RCB_STRMD_TILE_ROW_LEN        (MPP_ALIGN(dxva->width, 8) / 8 * 100)
+#define VDPU383_RCB_INTER_ROW_LEN             (MPP_ALIGN(dxva->width, 64) / 64 * 2752)
+#define VDPU383_RCB_INTER_TILE_ROW_LEN        (MPP_ALIGN(dxva->width, 64) / 64 * 2752)
+#define VDPU383_RCB_INTRA_ROW_LEN             (MPP_ALIGN(dxva->width, 512) * 12 * 3)
+#define VDPU383_RCB_INTRA_TILE_ROW_LEN        (MPP_ALIGN(dxva->width, 512) * 12 * 3)
+#define VDPU383_RCB_FILTERD_ROW_LEN           (MPP_ALIGN(dxva->width, 64) * (16 + 1) * (14 + 6 * 3))
+#define VDPU383_RCB_FILTERD_PROTECT_ROW_LEN   (MPP_ALIGN(dxva->width, 64) * (16 + 1) * (14 + 6 * 3))
+#define VDPU383_RCB_FILTERD_TILE_ROW_LEN      (MPP_ALIGN(dxva->width, 64) * (16 + 1) * (14 + 6 * 3))
+#define VDPU383_RCB_FILTERD_TILE_COL_LEN      (MPP_ALIGN(dxva->width, 64) * (16 + 1) * (14 + 7 * 3 + (14 + 13 * 3) + (9 + 7 * 3)))
+#define VDPU383_RCB_FILTERD_AV1_UP_TL_COL_LEN (MPP_ALIGN(dxva->width, 64) * 10 * 22)
+
+#define VDPU383_UNCMPS_HEADER_OFFSET_BASE            (0)
+
+#define VDPU383_INFO_ELEM_SIZE (VDPU383_UNCMPS_HEADER_SIZE)
+
+#define VDPU383_UNCMPS_HEADER_OFFSET(idx)            (VDPU383_INFO_ELEM_SIZE * idx + VDPU383_UNCMPS_HEADER_OFFSET_BASE)
+
+#define VDPU383_INFO_BUF_SIZE(cnt) (VDPU383_INFO_ELEM_SIZE * cnt)
+
+#define NON_COEF_CDF_SIZE (434 * 16) // byte
+#define COEF_CDF_SIZE (354 * 16) // byte
+#define ALL_CDF_SIZE (NON_COEF_CDF_SIZE + COEF_CDF_SIZE * 4)
+
+#define SET_REF_HOR_VIRSTRIDE(regs, ref_index, value)\
+    do{ \
+        switch(ref_index){\
+        case 0: regs.reg83_ref0_hor_virstride = value; break;\
+        case 1: regs.reg86_ref1_hor_virstride = value; break;\
+        case 2: regs.reg89_ref2_hor_virstride = value; break;\
+        case 3: regs.reg92_ref3_hor_virstride = value; break;\
+        case 4: regs.reg95_ref4_hor_virstride = value; break;\
+        case 5: regs.reg98_ref5_hor_virstride = value; break;\
+        case 6: regs.reg101_ref6_hor_virstride = value; break;\
+        case 7: regs.reg104_ref7_hor_virstride = value; break;\
+        default: break;}\
+    }while(0)
+
+#define SET_REF_RASTER_UV_HOR_VIRSTRIDE(regs, ref_index, value)\
+    do{ \
+        switch(ref_index){\
+        case 0: regs.reg84_ref0_raster_uv_hor_virstride = value; break;\
+        case 1: regs.reg87_ref1_raster_uv_hor_virstride = value; break;\
+        case 2: regs.reg90_ref2_raster_uv_hor_virstride = value; break;\
+        case 3: regs.reg93_ref3_raster_uv_hor_virstride = value; break;\
+        case 4: regs.reg96_ref4_raster_uv_hor_virstride = value; break;\
+        case 5: regs.reg99_ref5_raster_uv_hor_virstride = value; break;\
+        case 6: regs.reg102_ref6_raster_uv_hor_virstride = value; break;\
+        case 7: regs.reg105_ref7_raster_uv_hor_virstride = value; break;\
+        default: break;}\
+    }while(0)
+
+#define SET_REF_VIRSTRIDE(regs, ref_index, value)\
+    do{ \
+        switch(ref_index){\
+        case 0: regs.reg85_ref0_virstride = value; break;\
+        case 1: regs.reg88_ref1_virstride = value; break;\
+        case 2: regs.reg91_ref2_virstride = value; break;\
+        case 3: regs.reg94_ref3_virstride = value; break;\
+        case 4: regs.reg97_ref4_virstride = value; break;\
+        case 5: regs.reg100_ref5_virstride = value; break;\
+        case 6: regs.reg103_ref6_virstride = value; break;\
+        case 7: regs.reg106_ref7_virstride = value; break;\
+        default: break;}\
+    }while(0)
+
+#define SET_REF_BASE(regs, ref_index, value)\
+    do{ \
+        switch(ref_index){\
+        case 0: regs.reg170_av1_last_base      = value; break; \
+        case 1: regs.reg171_av1golden_base     = value; break; \
+        case 2: regs.reg172_av1alfter_base     = value; break; \
+        case 3: regs.reg173_refer3_base        = value; break; \
+        case 4: regs.reg174_refer4_base        = value; break; \
+        case 5: regs.reg175_refer5_base        = value; break; \
+        case 6: regs.reg176_refer6_base        = value; break; \
+        case 7: regs.reg177_refer7_base        = value; break; \
+        default: break;}\
+    }while(0)
+
+#define SET_FBC_PAYLOAD_REF_BASE(regs, ref_index, value)\
+    do{ \
+        switch(ref_index){\
+        case 0: regs.reg195_payload_st_ref0_base    = value; break; \
+        case 1: regs.reg196_payload_st_ref1_base    = value; break; \
+        case 2: regs.reg197_payload_st_ref2_base    = value; break; \
+        case 3: regs.reg198_payload_st_ref3_base    = value; break; \
+        case 4: regs.reg199_payload_st_ref4_base    = value; break; \
+        case 5: regs.reg200_payload_st_ref5_base    = value; break; \
+        case 6: regs.reg201_payload_st_ref6_base    = value; break; \
+        case 7: regs.reg202_payload_st_ref7_base    = value; break; \
+        default: break;}\
+    }while(0)
+
+#define VDPU_FAST_REG_SET_CNT    3
+
+#define OFFSET_CTRL_REGS          (8 * sizeof(RK_U32))
+#define OFFSET_COMMON_ADDR_REGS   (128 * sizeof(RK_U32))
+#define OFFSET_RCB_PARAS_REGS     (140 * sizeof(RK_U32))
+#define OFFSET_AV1D_PARAS_REGS    (64 * sizeof(RK_U32))
+#define OFFSET_AV1D_ADDR_REGS     (168 * sizeof(RK_U32))
+#define OFFSET_INTERRUPT_REGS     (15 * sizeof(RK_U32))
+
+typedef struct av1d_rkv_buf_t {
+    RK_U32              valid;
+    Vdpu383Av1dRegSet  *regs;
+} av1dVdpu383Buf;
+
+typedef struct vcpu383_ref_info_t {
+    RK_U32 dpb_idx;
+    RK_U32 seg_idx;
+    RK_U32 colmv_exist_flag;
+    RK_U32 coeff_idx;
+    RK_U32 mi_rows;
+    RK_U32 mi_cols;
+    RK_U32 seg_en;
+    RK_U32 seg_up_map;
+    RK_U32 cdf_update_flag;
+} vdpu383RefInfo;
+
+typedef struct VdpuAv1dRegCtx_t {
+    Vdpu383Av1dRegSet  *regs;
+    RK_U32             offset_uncomps;
+
+    av1dVdpu383Buf     reg_buf[VDPU_FAST_REG_SET_CNT];
+    MppBuffer          bufs;
+    RK_S32             bufs_fd;
+    void               *bufs_ptr;
+    RK_U32             uncmps_offset[VDPU_FAST_REG_SET_CNT];
+
+    Vdpu383RcbInfo  rcb_buf_info[RCB_BUF_COUNT];
+    RK_U32          rcb_buf_size;
+    MppBuffer       rcb_bufs[VDPU_FAST_REG_SET_CNT];
+
+    HalBufs         colmv_bufs;
+    RK_U32          colmv_count;
+    RK_U32          colmv_size;
+
+    vdpu383RefInfo  ref_info_tbl[NUM_REF_FRAMES];
+
+    MppBuffer       cdf_rd_def_base;
+    HalBufs         cdf_bufs;
+    RK_U32          cdf_count;
+    RK_U32          cdf_size;
+    RK_U32          cdf_coeff_cdf_idxs[NUM_REF_FRAMES];
+    // RK_U32          cdfs_last[NUM_REF_FRAMES];
+
+    MppBuffer       tile_info;
+    MppBuffer       film_grain_mem;
+    MppBuffer       global_model;
+    MppBuffer       filter_mem;
+    MppBuffer       tile_buf;
+
+    AV1CDFs         *cdfs;
+    MvCDFs          *cdfs_ndvc;
+    AV1CDFs         default_cdfs;
+    MvCDFs          default_cdfs_ndvc;
+    AV1CDFs         cdfs_last[NUM_REF_FRAMES];
+    MvCDFs          cdfs_last_ndvc[NUM_REF_FRAMES];
+    RK_U32          refresh_frame_flags;
+
+    RK_U32          width;
+    RK_U32          height;
+    RK_S32          hor_stride;
+    RK_S32          ver_stride;
+    RK_U32          luma_size ;
+    RK_U32          chroma_size;
+
+    FilmGrainMemory fgsmem;
+
+    RK_S8           prev_out_buffer_i;
+    RK_U8           fbc_en;
+    RK_U8           resolution_change;
+    RK_U8           tile_transpose;
+    RK_U32          ref_frame_sign_bias[AV1_REF_LIST_SIZE];
+
+    RK_U32          tile_out_count;
+    size_t          tile_out_size;
+
+    RK_U32          num_tile_cols;
+    /* uncompress header data */
+    RK_U8           header_data[VDPU383_UNCMPS_HEADER_SIZE];
+    HalBufs         origin_bufs;
+} Vdpu383Av1dRegCtx;
+
+// #define DUMP_AV1D_VDPU383_DATAS
+
+#ifdef DUMP_AV1D_VDPU383_DATAS
+static RK_U32 dump_cur_frame = 0;
+static char dump_cur_dir[128];
+static char dump_cur_fname_path[512];
+
+static MPP_RET flip_string(char *str)
+{
+    RK_U32 len = strlen(str);
+    RK_U32 i, j;
+
+    for (i = 0, j = len - 1; i <= j; i++, j--) {
+        // swapping characters
+        char c = str[i];
+        str[i] = str[j];
+        str[j] = c;
+    }
+    return MPP_OK;
+}
+
+static MPP_RET dump_data_to_file(char *fname_path, void *data, RK_U32 data_bit_size,
+                                 RK_U32 line_bits, RK_U32 big_end, RK_U32 append)
+{
+    RK_U8 *buf_p = (RK_U8 *)data;
+    RK_U8 cur_data;
+    RK_U32 i;
+    RK_U32 loop_cnt;
+    FILE *dump_fp = NULL;
+    char line_tmp[256];
+    RK_U32 str_idx = 0;
+
+    if (append)
+        dump_fp = fopen(fname_path, "aw+");
+    else
+        dump_fp = fopen(fname_path, "w+");
+    if (!dump_fp) {
+        mpp_err_f("open file: %s error!\n", fname_path);
+        return MPP_NOK;
+    }
+    if (append)
+        fseek(dump_fp, 0, SEEK_END);
+
+    if ((data_bit_size % 4 != 0) || (line_bits % 8 != 0)) {
+        mpp_err_f("line bits not align to 4!\n");
+        return MPP_NOK;
+    }
+
+    loop_cnt = data_bit_size / 8;
+    for (i = 0; i < loop_cnt; i++) {
+        cur_data = buf_p[i];
+
+        sprintf(&line_tmp[str_idx++], "%0x", cur_data & 0xf);
+        if ((i * 8 + 4) % line_bits == 0) {
+            line_tmp[str_idx++] = '\0';
+            str_idx = 0;
+            if (!big_end)
+                flip_string(line_tmp);
+            fprintf(dump_fp, "%s\n", line_tmp);
+        }
+        sprintf(&line_tmp[str_idx++], "%0x", (cur_data >> 4) & 0xf);
+        if ((i * 8 + 8) % line_bits == 0) {
+            line_tmp[str_idx++] = '\0';
+            str_idx = 0;
+            if (!big_end)
+                flip_string(line_tmp);
+            fprintf(dump_fp, "%s\n", line_tmp);
+        }
+    }
+
+    // last line
+    if (data_bit_size % 4) {
+        cur_data = buf_p[i];
+        sprintf(&line_tmp[str_idx++], "%0x", cur_data & 0xf);
+        if ((i * 8 + 8) % line_bits == 0) {
+            line_tmp[str_idx++] = '\0';
+            str_idx = 0;
+            if (!big_end)
+                flip_string(line_tmp);
+            fprintf(dump_fp, "%s\n", line_tmp);
+        }
+    }
+    if (data_bit_size % line_bits) {
+        loop_cnt = (line_bits - (data_bit_size % line_bits)) / 4;
+        for (i = 0; i < loop_cnt; i++)
+            sprintf(&line_tmp[str_idx++], "%0x", 0);
+        line_tmp[str_idx++] = '\0';
+        str_idx = 0;
+        if (!big_end)
+            flip_string(line_tmp);
+        fprintf(dump_fp, "%s\n", line_tmp);
+    }
+
+    fflush(dump_fp);
+    fclose(dump_fp);
+
+    return MPP_OK;
+}
+
+static MPP_RET dump_reg(RK_U32 *reg_s, RK_U32 count, RK_U32 log_start_idx)
+{
+    RK_U32 loop;
+    for (loop = 0; loop < count; loop++) {
+        mpp_log("reg[%03d]: 0%08x", log_start_idx + loop, reg_s[loop]);
+    }
+
+    return MPP_OK;
+}
+#endif
+
+static RK_U32 g_default_prob[7400] = {
+    0x000052ce, 0x90000000, 0x000003e2, 0x3b000000, 0x0013e5db, 0x00000000, 0x00000000, 0x20000000,
+    0x0e2d3544, 0x80000252, 0x11938c99, 0x16000042, 0x0ad1c0cf, 0x95800004, 0x6c0db50d, 0x20000000,
+    0x571fc313, 0x02f5c801, 0x7c7b593f, 0x62112a31, 0x00000003, 0x00000000, 0x00000000, 0x00000000,
+    0xea6ee10b, 0xd5074f9b, 0x94f16a25, 0x761fc65f, 0x0000000b, 0x00000000, 0x00000000, 0x00000000,
+    0x6615eada, 0x85ff113e, 0xfd02628a, 0x8b324070, 0x00000002, 0x00000000, 0x00000000, 0x00000000,
+    0xb393759a, 0x35d09796, 0xf0f9b25f, 0x3d269662, 0x00000006, 0x00000000, 0x00000000, 0x00000000,
+    0x172437e2, 0xd280296b, 0xc474391b, 0xc8143c32, 0x00000004, 0x00000000, 0x00000000, 0x00000000,
+    0x2e4e61f7, 0x43cc143a, 0xe4cdd1bc, 0x8424ee5a, 0x0000000e, 0x00000000, 0x00000000, 0x00000000,
+    0xae67e881, 0xf404162c, 0x04c279cb, 0xd128f459, 0x00000002, 0x00000000, 0x00000000, 0x00000000,
+    0x3bb07a8e, 0xb2075d45, 0xc06730e7, 0x65142e2d, 0x00000003, 0x00000000, 0x00000000, 0x00000000,
+    0x95eab157, 0x31904976, 0x104e58b7, 0x140ea823, 0x00000004, 0x00000000, 0x00000000, 0x00000000,
+    0xf15f65b4, 0x625b16b9, 0x5c84e91a, 0x6818843b, 0x0000000a, 0x00000000, 0x00000000, 0x00000000,
+    0x3108e8c7, 0x31feb7d9, 0x405e58e4, 0x12134c2a, 0x00000002, 0x00000000, 0x00000000, 0x00000000,
+    0x7da27c9a, 0xe0c45e8c, 0x04255055, 0xb406ee10, 0x00000001, 0x00000000, 0x00000000, 0x00000000,
+    0xc8e29305, 0x50238423, 0x0404a80e, 0x31000002, 0xed325966, 0x22505897, 0x06340d70, 0x10000000,
+    0xb2f66acb, 0xd05cb90b, 0xe8076821, 0x39000002, 0xdb3e1d7d, 0x0e60281e, 0x01a004b8, 0x10000000,
+    0xf095ea0a, 0xf718f048, 0xac895935, 0x3e000003, 0xf8dc6548, 0xae43d329, 0x06a03be8, 0x10000000,
+    0x485c9479, 0x31e4c3f3, 0x6403c817, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x10000000,
+    0x20004000, 0xd0893000, 0x4f7103f7, 0x415e3802, 0x00000060, 0x00000000, 0x00000000, 0x30000000,
+    0xc1441200, 0x00000016, 0x6c144120, 0xbd000001, 0x00000008, 0x00000000, 0x00000000, 0x20000000,
+    0xc1441200, 0x00000016, 0x6c144120, 0x00000001, 0x16c14412, 0x20000000, 0x016c1441, 0x20000000,
+    0x9f757cda, 0xf30acc49, 0x41ed9ecd, 0x91f3da2f, 0x0004dcbe, 0x00000000, 0x00000000, 0x30000000,
+    0x99a0ef74, 0xbbc6c189, 0xe01b49f3, 0x05a9f5f1, 0x447d2e17, 0x00013411, 0x00000000, 0x30000000,
+    0x510e9734, 0xbace1440, 0xabda974a, 0xb5b865df, 0x00141ae2, 0x00000000, 0x00000000, 0x30000000,
+    0x92c86b5c, 0x3e1ce0f8, 0x20ef048a, 0xaa88b5cf, 0x00000017, 0x00000000, 0x00000000, 0x30000000,
+    0x5926ecae, 0x7b6081fd, 0x84356a85, 0x688991e8, 0x00000014, 0x00000000, 0x00000000, 0x30000000,
+    0x9e717745, 0x9f4e221c, 0x00473c4b, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x30000000,
+    0x2500e1b0, 0xc762f090, 0xd57a3352, 0x1600005b, 0x59da0256, 0x2194e46b, 0x3f30eeaa, 0x10000000,
+    0x1881d658, 0x94d0caeb, 0xb0e6aa11, 0x0e000043, 0x025ed44c, 0xe154314c, 0x6328dbc1, 0x10000000,
+    0x9271b628, 0x629b0759, 0x688cf130, 0x1b00001f, 0x591de956, 0x17d4db8c, 0x6908ed82, 0x10000000,
+    0x9097bd1b, 0xa29386ca, 0x007f011c, 0x0a000022, 0x11d2a94d, 0x4d535548, 0x35b88731, 0x10000000,
+    0x5f85221d, 0x2be7d105, 0x076de504, 0x00f7c5de, 0x00000000, 0x00000000, 0x00000000, 0x30000000,
+    0x10c2225a, 0x82064e92, 0x41916a10, 0xff402133, 0x00000035, 0x00000000, 0x00000000, 0x30000000,
+    0xd21fa6ef, 0xf3e98846, 0x48cfa9bf, 0xd729cc60, 0x02c6ea12, 0x00012e63, 0x00000000, 0x00000000,
+    0x593db70f, 0x249d49e6, 0x24fdba27, 0x082a3871, 0xb805fd92, 0x0000ef82, 0x00000000, 0x00000000,
+    0x1706b2c6, 0xf44fa927, 0x40fd9214, 0x4a2c7e77, 0xf786a813, 0x000107a2, 0x00000000, 0x00000000,
+    0x9665b145, 0x34aec9b2, 0xa5209a52, 0xf83e388d, 0x9e0c189c, 0x00024de5, 0x00000000, 0x00000000,
+    0x9ebec31c, 0x6620cd1d, 0xfd6c52f3, 0x834a68aa, 0x96c8fda1, 0x00011fc3, 0x00000000, 0x00000000,
+    0x1cb75110, 0x16162cf1, 0x0161e2f1, 0x8e4c10aa, 0x89080720, 0x0000a9e2, 0x00000000, 0x00000000,
+    0x2af6d8bc, 0x14df8a3a, 0xed29ca5f, 0xd037d886, 0xc5c6b419, 0x00009622, 0x00000000, 0x00000000,
+    0xa1e948f5, 0x06d10ff1, 0x899d3354, 0x565360c7, 0xc486379f, 0x00002641, 0x00000000, 0x00000000,
+    0x6617d0a6, 0xf7f170c3, 0x258dfb74, 0xbb3822a2, 0xa7c4e598, 0x000024a1, 0x00000000, 0x00000000,
+    0x19bfd8d9, 0x85880ba4, 0x3d38c2ab, 0xdb445297, 0x3b87551c, 0x0000a682, 0x00000000, 0x00000000,
+    0x10eee8a1, 0x63d94804, 0x1cd9e9e1, 0x2631926b, 0x75059794, 0x000079c1, 0x00000000, 0x00000000,
+    0xe709e2ec, 0xb5e10c4b, 0x995ccada, 0x6b4926a5, 0x97897aa0, 0x00011c83, 0x00000000, 0x00000000,
+    0x234fdea7, 0x07a830ee, 0x61c823c0, 0xb7651ee0, 0xa2070f9f, 0x000045c1, 0x00000000, 0x00000000,
+    0x2434e289, 0xf817b0de, 0x81789ba0, 0x6f4078a8, 0xbec60a9a, 0x000060c1, 0x00000000, 0x00000000,
+    0x6574cebb, 0x85418b1e, 0x5d3e7a8d, 0x7f3c4292, 0x67c64f1b, 0x00005662, 0x00000000, 0x00000000,
+    0xa5b15a29, 0xc69c4ded, 0xa58a6b36, 0x4d53a4bc, 0x7949d0a5, 0x0000e8a3, 0x00000000, 0x00000000,
+    0x334be7d9, 0x232e8696, 0xd8c5f190, 0x75227c58, 0xed847e90, 0x00005541, 0x00000000, 0x00000000,
+    0xa9155622, 0x37971165, 0xfdcfe3b6, 0xba57dadd, 0x6c4768a2, 0x00004082, 0x00000000, 0x00000000,
+    0xecbf5c16, 0x87922fe2, 0x15a8eb80, 0x3f352eaf, 0xfbc54418, 0x00002621, 0x00000000, 0x00000000,
+    0x23e0cec6, 0x670670e0, 0xd1a46b6a, 0x1c58aacb, 0xcec6001e, 0x00002ce1, 0x00000000, 0x00000000,
+    0x2501dff5, 0x17a5f1d1, 0x71c96bbe, 0x7767e8e0, 0x9286699d, 0x00003541, 0x00000000, 0x00000000,
+    0x2cfedefd, 0x4762b159, 0x09c03b9a, 0xe357bcd6, 0xa087211f, 0x00005dc2, 0x00000000, 0x00000000,
+    0x2e5461de, 0xf7dcb6b5, 0xfdecf3e4, 0x896d62f3, 0x3404a597, 0x00001e01, 0x00000000, 0x00000000,
+    0x2bec5d75, 0x488574c6, 0x71cf4bef, 0x574e84d5, 0xbe457f9b, 0x00002361, 0x00000000, 0x00000000,
+    0x654ccede, 0xd7c7d065, 0xcd727b57, 0x95392e98, 0x9484fd19, 0x00002461, 0x00000000, 0x00000000,
+    0x25635aa5, 0x483d9146, 0x05740baa, 0xdc42a8a5, 0x9646159c, 0x00003d61, 0x00000000, 0x00000000,
+    0x2e9ddf5c, 0xa7160ecc, 0xe98bb346, 0x9e354a9e, 0x31459a18, 0x00003f62, 0x00000000, 0x00000000,
+    0x28ecd5ad, 0x682ad32f, 0xf5cc4bd8, 0xd94e3ed7, 0xd746679f, 0x000023c1, 0x00000000, 0x00000000,
+    0x6fd0623e, 0x6ade765f, 0x25b8fc3e, 0x041f309a, 0xf182c28e, 0x000015e0, 0x00000000, 0x00000000,
+    0x762c777c, 0x34e1189c, 0x004fb969, 0x03000000, 0x67f50c77, 0x6a248837, 0x00004c31, 0x10000000,
+    0x6a7b713c, 0x568cd29f, 0x002e525d, 0x1b000000, 0x356a136e, 0xab67a1d1, 0x0000889a, 0x10000000,
+    0xeaa8f937, 0x766f91d4, 0x007b4a72, 0x98000000, 0xceec2075, 0xba0761d3, 0x0000470a, 0x10000000,
+    0xea547740, 0xf61170e8, 0x00785a7d, 0xeb000000, 0xd56ba271, 0xd0475e93, 0x0000420a, 0x10000000,
+    0x90d42799, 0xe3786737, 0x44c341a7, 0xac25da59, 0xc8c54a91, 0x000064e1, 0x00000000, 0x00000000,
+    0xcb7fdad7, 0x22cb45a8, 0x949f8161, 0x3926a04e, 0xe6065f91, 0x00007982, 0x00000000, 0x00000000,
+    0x6ca2d98b, 0xb1fc0402, 0xc87ca0fa, 0x62170437, 0xf7c3ea0b, 0x00005c60, 0x00000000, 0x00000000,
+    0x64dbcab9, 0xa3a1b229, 0x7cdc09bf, 0x5f2be86a, 0x61443610, 0x00002261, 0x00000000, 0x00000000,
+    0xaccad9dc, 0x6b23d64d, 0x28b299cd, 0xad24184b, 0x00034191, 0x000032a1, 0x00000000, 0x00000000,
+    0xe575d1cf, 0x894d12a4, 0x2c6f1c53, 0xf119dc36, 0x4bc3238b, 0x00001b41, 0x00000000, 0x00000000,
+    0x23e0c8a1, 0xa7c96fc8, 0xe5d48bac, 0xdb141041, 0x6a81d189, 0x00000ca0, 0x00000000, 0x00000000,
+    0xa6894dab, 0x7863515f, 0x4213e42c, 0xad1c7103, 0xc9c4268d, 0x00002660, 0x00000000, 0x00000000,
+    0xa551d106, 0xe886f273, 0x16149437, 0xe580df06, 0xf444a610, 0x00002c01, 0x00000000, 0x00000000,
+    0x59403594, 0x25c98be7, 0x0d612ad6, 0x7a4e82aa, 0x5547a1a5, 0x00004a22, 0x00000000, 0x00000000,
+    0x999fb73d, 0xc5a3ab84, 0x255642c0, 0x194b62a5, 0x56cb29a4, 0x00004d81, 0x00000000, 0x00000000,
+    0xdae23d7e, 0x6611ac78, 0x6d6c8af9, 0x2e54dab2, 0x14cd6c28, 0x000076a6, 0x00000000, 0x00000000,
+    0x6520d0a4, 0x18ae1164, 0x6a29ac56, 0x69898514, 0x56613bc4, 0x0007e450, 0x00000000, 0x00000000,
+    0x2a1c5759, 0x19907367, 0x36450ca0, 0x8e85b117, 0x7f58c541, 0x16c5092b, 0x00000002, 0x00000000,
+    0xd95e6e4c, 0x46212c69, 0xc56d8b03, 0xad586ab4, 0xe2d0ae29, 0xce02cd07, 0x00000000, 0x00000000,
+    0xf57eeb67, 0xf61a4c4b, 0xad814b05, 0xf25682b8, 0x5012cf2a, 0x7c93f028, 0x00000001, 0x00000000,
+    0xb200e5ac, 0x89171884, 0x1a31fc73, 0x3d7d3715, 0x5095f838, 0x18a4946a, 0x00000002, 0x00000000,
+    0x35846c85, 0x6d099a36, 0x7d852b55, 0x755226aa, 0x370f58a8, 0x8f834aa7, 0x00000001, 0x00000000,
+    0x728beb06, 0x6c63f8ec, 0x996c35ae, 0x23560eb1, 0x358f9a2a, 0x5d830d67, 0x00000001, 0x00000000,
+    0x364fed30, 0x3c6c58f7, 0xdee8f5dc, 0xbd5e6cc4, 0xcb52b62e, 0xe9440f28, 0x00000001, 0x00000000,
+    0xf2d66630, 0x7b94f7ab, 0xe6dba5bd, 0x8d6ceb67, 0x57146035, 0xf2744c89, 0x00000001, 0x00000000,
+    0xf182e892, 0x9ba37866, 0x9ed59dbd, 0x2eae9f67, 0x67541136, 0xa7b3e889, 0x00000001, 0x00000000,
+    0xa9ef565c, 0x69ac73be, 0xa25644bf, 0x528ac924, 0xb8d78b43, 0xee348daa, 0x00000001, 0x00000000,
+    0x297b56e6, 0xe9abb3be, 0x6e516cbb, 0xe288fb21, 0xd618bd41, 0xb1246449, 0x00000001, 0x00000000,
+    0x6b1ed88d, 0x69a0f3a8, 0x4e54fcbb, 0xec898b23, 0x01999242, 0xd884842c, 0x00000001, 0x00000000,
+    0xb610f3b8, 0x7c5618ca, 0x1f0fb625, 0xd8c10186, 0x5b6df05f, 0xe88adcf6, 0x00000000, 0x00000000,
+    0x3bdafa76, 0x470372f9, 0x688a496a, 0x00000007, 0x00000000, 0x00000000, 0x00000000, 0x10000000,
+    0xd788e22b, 0xf023e155, 0x30028006, 0x44009001, 0x0f002000, 0x03400700, 0x00b00180, 0x00000000,
+    0x51e6c7e3, 0x90c80486, 0x640ba825, 0x94018604, 0x19003c80, 0x05c00c00, 0x015002c0, 0x00000000,
+    0xd44a52f4, 0x30b00438, 0xe007a81a, 0x5f00ee02, 0x15c02d80, 0x04f00a60, 0x011c0258, 0x00000000,
+    0x82ab1692, 0xc018a079, 0x10024004, 0x3c008001, 0x0d001c00, 0x02c00600, 0x00900140, 0x00000000,
+    0x0d1b3ca0, 0x710e03c6, 0x081bd85b, 0x76037e0a, 0x3f009801, 0x0c001a00, 0x02480578, 0x00000000,
+    0x55a9466e, 0x026066d3, 0xf04d10ea, 0x70073a1b, 0x3e00b182, 0x092015c0, 0x01b00380, 0x00000000,
+    0xf2d4edf3, 0x9c28da3e, 0x22da74ef, 0x2c90473e, 0x00145cce, 0x00080010, 0x00000000, 0x30000000,
+    0x20004000, 0xe8001000, 0xeebc04e1, 0x007296c3, 0x00200040, 0x00000000, 0x00000000, 0x30000000,
+    0x670c5d0b, 0x01914f31, 0x02a00700, 0x000000d2, 0x00000040, 0x00000000, 0x00000004, 0x20000000,
+    0x83801000, 0x903800e3, 0x7003800d, 0x06001600, 0x00000080, 0x00000000, 0x00000000, 0x00000000,
+    0x83801000, 0x903800e3, 0x7003800d, 0x06001600, 0x00000080, 0x00000000, 0x00000000, 0x00000000,
+    0x0a001400, 0x07400f00, 0x01800360, 0x004000a0, 0xc0058010, 0x00010002, 0x00000000, 0x30000000,
+    0x1d003c00, 0x06000d80, 0x01000280, 0x00160040, 0x0004000b, 0x00000000, 0x00000000, 0x30000000,
+    0x10004000, 0x00000600, 0x01680500, 0x00000087, 0x00100040, 0x00000006, 0x87016805, 0x20000000,
+    0x18003000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x30000000,
+    0x1e006000, 0x00000b40, 0x01e00600, 0x000000b4, 0x00000040, 0x00000000, 0x00000004, 0x20000000,
+    0x2a007000, 0x00000d20, 0x00000400, 0x00000000, 0x00000040, 0x00000000, 0x00000000, 0x20000000,
+    0x83801000, 0x903800e3, 0x7003800d, 0x06001600, 0x00000080, 0x00000000, 0x00000000, 0x00000000,
+    0x83801000, 0x903800e3, 0x7003800d, 0x06001600, 0x00000080, 0x00000000, 0x00000000, 0x00000000,
+    0x0a001400, 0x07400f00, 0x01800360, 0x004000a0, 0xc0058010, 0x00010002, 0x00000000, 0x30000000,
+    0x1d003c00, 0x06000d80, 0x01000280, 0x00160040, 0x0004000b, 0x00000000, 0x00000000, 0x30000000,
+    0x10004000, 0x00000600, 0x01680500, 0x00000087, 0x00100040, 0x00000006, 0x87016805, 0x20000000,
+    0x18003000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x30000000,
+    0x1e006000, 0x00000b40, 0x01e00600, 0x000000b4, 0x00000040, 0x00000000, 0x00000004, 0x20000000,
+    0x000016f9, 0x30000000, 0x00000143, 0xe3000000, 0x00000009, 0x00000000, 0x00000000, 0x20000000,
+    0x2a5b78ad, 0x7000054f, 0xb2c7a765, 0x72000063, 0xaea977ef, 0x00000006, 0x00000000, 0x20000000,
+    0x0f41b1bc, 0x428ec5ec, 0x2067e0c8, 0x0080005c, 0x00200040, 0x00080010, 0x00000000, 0x30000000,
+    0x20004000, 0x08001000, 0x02000400, 0x65ae7700, 0xfa2dd5db, 0x0008f52e, 0x00000000, 0x30000000,
+    0x4d93c4da, 0x0537a9b6, 0xe036d0a5, 0x00010412, 0xe4200040, 0x0005cb68, 0x00000000, 0x30000000,
+    0x4b80a238, 0x2991a91e, 0xd2ceb533, 0xe4bfaf71, 0x00200067, 0x00080010, 0x00000000, 0x30000000,
+    0x20004000, 0x08001000, 0xae8ea400, 0x00800187, 0x00000040, 0x00000000, 0x00000000, 0x30000000,
+    0x0fa4621d, 0xe0000000, 0x00fa1ed7, 0xf1000000, 0x000e246a, 0x42500000, 0x0000ba33, 0x20000000,
+    0x11e56bfd, 0xa0000000, 0x0108652a, 0x6c000000, 0x00072219, 0x07800000, 0x00009313, 0x20000000,
+    0x0b992b51, 0x40000000, 0x004098cb, 0x1e000000, 0x0004a18f, 0x76200000, 0x00002cc8, 0x20000000,
+    0x00690105, 0x50000000, 0x01555d55, 0x55000000, 0x001555d5, 0xf8100000, 0x00002b10, 0x20000000,
+    0x03e518c1, 0x30000000, 0x0024b0ed, 0xd2000000, 0x00030e8b, 0x00000000, 0x00000000, 0x20000000,
+    0x7754767a, 0x3bc5398e, 0xe66db550, 0x7972a509, 0x70545330, 0x39837348, 0x18f467b1, 0x00000000,
+    0xf99f7cda, 0xecb5da22, 0x9719ce3c, 0x3d8e0986, 0xfb1e14c0, 0x6c96844d, 0x310ccf8a, 0x00000000,
+    0x78b37525, 0x1c7a7b6d, 0xc7057e1a, 0xed8fd778, 0x0e165639, 0xcf029648, 0x116045f8, 0x00000000,
+    0x78ebf96c, 0xac879a75, 0x8e9fb5ba, 0x257a111e, 0xa7170fb5, 0x7a140d29, 0x1d8c7eb1, 0x00000000,
+    0xf92efb8a, 0x7c6dd9de, 0x06faee06, 0xf7959173, 0x4f9f5343, 0x807691ee, 0x3248d322, 0x00000000,
+    0x77cef54a, 0xcc13ba68, 0x7adc45ce, 0x8a91a961, 0x1d97e5bc, 0x2d835189, 0x152063f1, 0x00000000,
+    0xf84a7941, 0xfc319a0a, 0xaa7e4598, 0x626c0109, 0x9954f52f, 0x6943a428, 0x1b707d11, 0x00000000,
+    0x38007800, 0x0c001a00, 0x02800580, 0x00800120, 0x00180038, 0x8004000a, 0x20008001, 0x00000000,
+    0x38007800, 0x0c001a00, 0x02800580, 0x00800120, 0x00180038, 0x8004000a, 0x20008001, 0x00000000,
+    0x38007800, 0x0c001a00, 0x02800580, 0x00800120, 0x00180038, 0x8004000a, 0x20008001, 0x00000000,
+    0x38007800, 0x0c001a00, 0x02800580, 0x00800120, 0x00180038, 0x8004000a, 0x20008001, 0x00000000,
+    0x38007800, 0x0c001a00, 0x02800580, 0x00800120, 0x00180038, 0x8004000a, 0x20008001, 0x00000000,
+    0x38007800, 0x0c001a00, 0x02800580, 0x00800120, 0x00180038, 0x8004000a, 0x20008001, 0x00000000,
+    0x38007800, 0x0c001a00, 0x02800580, 0x00800120, 0x00180038, 0x8004000a, 0x20008001, 0x00000000,
+    0x38007800, 0x0c001a00, 0x02800580, 0x00800120, 0x00180038, 0x8004000a, 0x20008001, 0x00000000,
+    0xfe12ff66, 0x8effbe1e, 0x67be0f7d, 0x694c0fde, 0x99d09223, 0x58537587, 0x1d047969, 0x00000000,
+    0xfd6b7b91, 0x8eb6be8a, 0xbbaa7f57, 0x695bd1d4, 0x634f0fa6, 0xa771c165, 0x0d0c3880, 0x00000000,
+    0x38007800, 0x0c001a00, 0x02800580, 0x00800120, 0x00180038, 0x8004000a, 0x20008001, 0x00000000,
+    0x38007800, 0x0c001a00, 0x02800580, 0x00800120, 0x00180038, 0x8004000a, 0x20008001, 0x00000000,
+    0x134a9811, 0x23fdcd9a, 0xf13b7322, 0x739b7ee2, 0xe2a61ae4, 0x000dbb96, 0x00000000, 0x30000000,
+    0x00180341, 0x00000000, 0x00018ea4, 0x5a000000, 0x003a437e, 0x1ac00000, 0x00000501, 0x20000000,
+    0x0197861a, 0x20000000, 0x00143ed0, 0xfe000000, 0x003dc07c, 0xe6700000, 0x0000deda, 0x20000000,
+    0x0016035a, 0x80000000, 0x0001c6fe, 0xcf000000, 0x003b9cfe, 0x4f500000, 0x00000421, 0x20000000,
+    0x017b86d2, 0xd0000000, 0x00151f46, 0xa7000000, 0x003e28fd, 0x58700000, 0x00016354, 0x20000000,
+    0x516d105b, 0xc420aba4, 0x6684db8e, 0x03aaf2da, 0x770aead5, 0x000a7dec, 0x00000000, 0x30000000,
+    0x1a4a184b, 0x6252321c, 0xee3e02bd, 0x2850fe47, 0x80190041, 0x0004200c, 0x00000000, 0x30000000,
+    0x05125010, 0x00000000, 0x00512501, 0x0b000000, 0x0003c037, 0x00000000, 0x00000000, 0x20000000,
+    0x225a4d46, 0x60000000, 0x0225a4d4, 0x12000000, 0x000dff21, 0x00000000, 0x00000000, 0x20000000,
+    0xf04efa01, 0x59c636c2, 0x009a7a45, 0xcc000000, 0x84f97cfd, 0x921ab156, 0x00009213, 0x10000000,
+    0x2996e96a, 0xa0000000, 0x02996e96, 0x5d000000, 0x00138cbe, 0x00000000, 0x00000000, 0x20000000,
+    0x39a8fd60, 0x9a265c69, 0x012d4b42, 0x61000000, 0xe064e1eb, 0x41973090, 0x00004ea2, 0x10000000,
+    0xf9528444, 0x506b1ec4, 0xc7e1674d, 0xf3e5700e, 0x85c1717c, 0x000f8f1c, 0x00000000, 0x30000000,
+    0xf4236eb9, 0x3aea1833, 0x006c71ba, 0x32000000, 0xc337b7fa, 0xfb8acb56, 0x00009e93, 0x10000000,
+    0xb1ab81cb, 0x103efe92, 0xfbd07f05, 0x7fc1ec04, 0x040099ff, 0x0000000b, 0x00000000, 0x30000000,
+    0xba757e49, 0x6cb5fc8f, 0x0119b397, 0x5a000000, 0x4277bbfb, 0x0c7a4d5b, 0x0001063b, 0x10000000,
+    0xe69c60f0, 0x95834e46, 0x006e39c4, 0x1d000000, 0x2f69b1e4, 0x38e67510, 0x000092ba, 0x10000000,
+    0x77947beb, 0xcb0a378e, 0x006b4b72, 0x36000000, 0x5d78b57f, 0xd19c6fdb, 0x00011183, 0x10000000,
+    0xe71de194, 0x55fd8f14, 0x00847210, 0xb1000000, 0x2ea4885f, 0xe115788e, 0x00008459, 0x10000000,
+    0x77947e41, 0x6ba99957, 0x01167417, 0xeb000000, 0xde7777fe, 0xfafba6fa, 0x0001480b, 0x10000000,
+    0x5a8a4e4b, 0x13df2aa6, 0x0052c147, 0x11000000, 0x7962ec5a, 0xbc35b88f, 0x000098e9, 0x10000000,
+    0x756272af, 0x986235a6, 0x0110c331, 0xb2000000, 0xcfa52978, 0x3267f1d1, 0x00009e72, 0x10000000,
+    0x9761c5a4, 0x7430cad4, 0x0075c966, 0xf7000000, 0x8218fadd, 0x59d18ae5, 0x00000f80, 0x10000000,
+    0x2ed27eba, 0x88a331b6, 0x00a5134b, 0x1c000000, 0x7831347e, 0x5298f2b8, 0x00013e0b, 0x10000000,
+    0xe195e931, 0x82d7a8f8, 0x002160b6, 0xb6000000, 0x6c6a026e, 0xaf9582ae, 0x00006851, 0x10000000,
+    0x620a7b9a, 0x07b0307a, 0x004dcae6, 0x71000000, 0xdff6857d, 0x9add1cfa, 0x0000aff2, 0x10000000,
+    0xed847364, 0x572af15b, 0x00a72280, 0x48000000, 0x376ea571, 0x82174893, 0x0000adca, 0x10000000,
+    0xf3637aed, 0xdb76d752, 0x00e33c5f, 0xc9000000, 0x9435a8fe, 0x115ca37a, 0x00013b84, 0x10000000,
+    0xef7ef660, 0xb5701370, 0x0083a9c4, 0x0b000000, 0xcff562fb, 0xb3c6bdb5, 0x0000d7ba, 0x10000000,
+    0xb042fc8d, 0x7a80d7ec, 0x015e9bc7, 0x1b000000, 0xe6b1327d, 0xed0af2f6, 0x00007453, 0x10000000,
+    0xe0000fda, 0xd2cc95b1, 0x0072f848, 0xb7bbef00, 0x0002430d, 0x00000000, 0x00000000, 0x30000000,
+    0x71897f92, 0x7b82b845, 0x0126fc15, 0x95000000, 0xdcf06d7e, 0x2f3ac9f6, 0x00010334, 0x10000000,
+    0x0473131b, 0x40000000, 0x00dcfd2f, 0x70000000, 0x0004f366, 0x61600000, 0x000092c2, 0x20000000,
+    0x3110ff67, 0x5b261814, 0x018f2443, 0x49000000, 0x18f3a272, 0x48588335, 0x00011eb3, 0x10000000,
+    0x00bf8355, 0x70000000, 0x007139d5, 0x01000000, 0x000ab1d0, 0x48700000, 0x00009646, 0x20000000,
+    0xe666e666, 0x63334ccc, 0xce666e66, 0x663334cc, 0xcce666e6, 0x0003334c, 0x00000000, 0x20000000,
+    0x0e61b14f, 0x00000000, 0x00234887, 0x1c000000, 0xa8c9391c, 0xafa00002, 0x56215d55, 0x20000000,
+    0xe666e666, 0x63334ccc, 0xce666e66, 0x663334cc, 0xcce666e6, 0x0003334c, 0x00000000, 0x20000000,
+    0x0b95e3b0, 0x100002e0, 0x0d02d352, 0x58000045, 0x8181d785, 0x16e00000, 0x2cc4aeca, 0x20000000,
+    0xe666e666, 0x63334ccc, 0xce666e66, 0x663334cc, 0xcce666e6, 0x0003334c, 0x00000000, 0x20000000,
+    0x94475960, 0x3000056c, 0x4cd1de8f, 0x72000036, 0x54d4bc38, 0x90500004, 0x0d283300, 0x20000000,
+    0xe666e666, 0x63334ccc, 0xce666e66, 0x663334cc, 0xcce666e6, 0x0003334c, 0x00000000, 0x20000000,
+    0x0b5a9f35, 0x3136c418, 0xdd83a5e2, 0x61248687, 0x4fca29ef, 0x0000d4a3, 0x00000000, 0x20000000,
+    0xe666e666, 0x63334ccc, 0xce666e66, 0x663334cc, 0xcce666e6, 0x0003334c, 0x00000000, 0x20000000,
+    0x11c33268, 0x2194c5e9, 0xb41b5846, 0x0002ac09, 0x00000000, 0x00000000, 0x00000000, 0x20000000,
+    0xe666e666, 0x63334ccc, 0xce666e66, 0x663334cc, 0xcce666e6, 0x0003334c, 0x00000000, 0x20000000,
+    0xce3ca63c, 0x315bc4de, 0x956305f2, 0x2f1e6c7b, 0x1f867bf7, 0x00009242, 0x00000000, 0x20000000,
+    0xe666e666, 0x63334ccc, 0xce666e66, 0x663334cc, 0xcce666e6, 0x0003334c, 0x00000000, 0x20000000,
+    0x5697350b, 0xc20686b1, 0x9c16a039, 0x0001f407, 0x00000000, 0x00000000, 0x00000000, 0x20000000,
+    0xe666e666, 0x63334ccc, 0xce666e66, 0x663334cc, 0xcce666e6, 0x0003334c, 0x00000000, 0x20000000,
+    0x8e60a5a4, 0x721da5a9, 0x000000a8, 0xed000000, 0xc4de5362, 0x2b23e8cb, 0x00000001, 0x10000000,
+    0xe666e666, 0x63334ccc, 0xce666e66, 0x993334cc, 0xc326f97b, 0x000294a9, 0x00000000, 0x20000000,
+    0x0f716764, 0x11f205b0, 0x00000083, 0x1c000000, 0x535348b6, 0xc2c29aa7, 0x00000000, 0x10000000,
+    0x32cbff6f, 0x62fab44d, 0x8b480fe9, 0x7f7d5749, 0xd96249fe, 0x0001036d, 0x00000000, 0x20000000,
+    0x026105da, 0xf058a0f0, 0x00000019, 0x37000000, 0xfcd004a9, 0x8ac1fea5, 0x00000000, 0x10000000,
+    0xba4f7fe7, 0x42602968, 0x6f7457fc, 0xdb449348, 0xd4797e7f, 0x00058711, 0x00000000, 0x20000000,
+    0x1ff56375, 0x83f90cd3, 0x0000010f, 0xa7000000, 0xc04f0c6e, 0x7391de45, 0x00000000, 0x10000000,
+    0x33a87f63, 0x977c3345, 0x5b2e0ff8, 0xd11a5936, 0xb8352fff, 0x000580b3, 0x00000000, 0x20000000,
+    0x57e83cc6, 0x22f0493a, 0x000000c7, 0x2e000000, 0x57038b88, 0x23108121, 0x00000000, 0x10000000,
+    0xb4227ef3, 0xd4b6b501, 0x7f508ffa, 0x50796944, 0x42752678, 0x0006f1b4, 0x00000000, 0x20000000,
+    0x0ec8a5bf, 0xd27b8628, 0x004c90ef, 0xda000000, 0x7e21d4e4, 0xc214eced, 0x00008369, 0x10000000,
+    0x75246e96, 0xeb42787c, 0xfe31dcbe, 0x0061aced, 0xa093602c, 0x3b138fc8, 0x21647869, 0x00000000,
+    0x92276278, 0x72b7a71b, 0x004060f0, 0x90000000, 0x1dd44db7, 0x229335a8, 0x00005519, 0x10000000,
+    0xbaf9f993, 0x1d363b55, 0x9af29618, 0xf688075b, 0x02d8243a, 0x6143c9ca, 0x1f8c7a41, 0x00000000,
+    0x82928622, 0x506ec112, 0x000bc828, 0x09000000, 0x8b12c02d, 0xfdf2d5c7, 0x000046b0, 0x10000000,
+    0xfb45fcfe, 0x59b2bae5, 0x1db08c23, 0x1d43ceaf, 0x2fc84918, 0x00000002, 0x00000000, 0x00000000,
+    0x22ae666f, 0x1558ee6b, 0x007f19c6, 0x88000000, 0x34cca4f2, 0xa521fc05, 0x00002970, 0x10000000,
+    0x00004000, 0x90000000, 0x000006fb, 0x32000000, 0x00000078, 0xd1400000, 0x00000007, 0x20000000,
+    0x1c36c1ef, 0x03f0cace, 0x0060316a, 0xf4000000, 0x42430e06, 0x31108141, 0x00000dd8, 0x10000000,
+    0x3df8fcb8, 0xed9c3e11, 0x97eb0fe8, 0x00dd13e2, 0x00000000, 0x00000000, 0x00000000, 0x20000000,
+    0x515aab47, 0xe322076d, 0x347b2948, 0x14000028, 0x9421f3e5, 0x1215734e, 0x37b0bbfa, 0x10000000,
+    0xfefc7e70, 0x2ef95f0b, 0x00000667, 0x2e000000, 0xb77f35ff, 0x28fe605e, 0x00000006, 0x10000000,
+    0x92b969ed, 0x230d478b, 0x3069812b, 0x6b00001d, 0x2793e734, 0x47c34ec8, 0x244074c9, 0x10000000,
+    0xff077eb7, 0xff211eec, 0x030d9733, 0xb1000000, 0x937e937e, 0xdcdd515e, 0x000269dd, 0x10000000,
+    0x02ed06cc, 0x9084e13c, 0xe0133834, 0x3e000005, 0xd292842c, 0x3ff32f47, 0x22747661, 0x10000000,
+    0x3f0f7f25, 0x0efabee3, 0x5b43a71a, 0x8d00013b, 0xc6bea2fe, 0xaf9da45e, 0xee9e7775, 0x10000000,
+    0x22d5e919, 0xd5e88edc, 0x9cc6aa37, 0xa9000036, 0xc0cd9772, 0xdd925545, 0x11f84a30, 0x10000000,
+    0x7edc7eca, 0x8e3f7e28, 0xa2f2ee7e, 0x1a85b94e, 0x12bc637c, 0xc43d439d, 0x9a359283, 0x10003822,
+    0x18c639d3, 0xe44b4a4a, 0x28887195, 0x2a000025, 0x3902cf86, 0x3af08821, 0x06f81730, 0x10000000,
+    0x7e14fd7f, 0x6d595c61, 0x722c9580, 0x334918da, 0x0000001a, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x7f2dfe77, 0x8f353f44, 0x7f39873a, 0xd573032f, 0x000d8d27, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x36557351, 0x08e3b68a, 0xb7973789, 0x008d9386, 0x00000000, 0x00000000, 0x00000000, 0x20000000,
+    0x347e0397, 0xf54a342c, 0x64a57b0b, 0xefc43404, 0x45c57033, 0x00013bd6, 0x00000000, 0x30000000,
+    0x37a7f5b4, 0xfa3dd897, 0x00000304, 0x06000000, 0x42b9caf9, 0x592a7479, 0x00000003, 0x10000000,
+    0xbcf984c4, 0x17de161b, 0x9cc9e376, 0x50d5ca03, 0x000566b9, 0x00080010, 0x00000000, 0x30000000,
+    0xb5a4724f, 0xc9415626, 0x0125b3ae, 0xe5000000, 0x3d3aba79, 0x68eaac3b, 0x00014184, 0x10000000,
+    0x75788afb, 0x147e4e62, 0xecd91286, 0x18e27c08, 0x000765c4, 0x00080010, 0x00000000, 0x30000000,
+    0x31706b83, 0xf842936c, 0xa114231b, 0xfa000050, 0x44f93877, 0x8be90d1a, 0x5e017c93, 0x10000000,
+    0xbc733a00, 0x53a8f8e3, 0x4025f555, 0xf4f55402, 0xdb848142, 0x000d7e9f, 0x00000000, 0x30000000,
+    0x39ac7628, 0xfbab5a30, 0x39db54ed, 0x654330c8, 0xbd77ef77, 0xf54ac1b8, 0x6fdd1bfa, 0x10002b06,
+    0xbfc5e75c, 0x0ef1fe66, 0x66aaac00, 0x00800027, 0x00200040, 0x00080010, 0x00000000, 0x30000000,
+    0x33696c19, 0xf97ad63d, 0x25cdf416, 0x2c33deb9, 0x0000000e, 0x00000000, 0x00000000, 0x00000000,
+    0x2000028b, 0x008af000, 0x020c0400, 0x806d0134, 0x2026c044, 0x0000000f, 0x00000000, 0x30000000,
+    0xbc1e78b7, 0xbdeddd23, 0x59fb356d, 0x7e2b12b2, 0x0001ec10, 0x00000000, 0x00000000, 0x00000000,
+    0xde5cbdbf, 0x0800188e, 0x02000400, 0x00800100, 0xc4a41340, 0x0004324b, 0x00000000, 0x40000000,
+    0x82dd2787, 0x98c26090, 0x1c487960, 0xf875b57e, 0xe4fa1924, 0xa009c1d7, 0x8fc37627, 0x80000001,
+    0x84a3b36b, 0x4965a128, 0x084ec197, 0x406e857c, 0xe6788b20, 0xa3783355, 0x95d37f5f, 0x80000001,
+    0xc5e9b95e, 0x49d980de, 0x6847199f, 0x835b056c, 0x36f3ae16, 0x66159c31, 0x6727395f, 0x80000001,
+    0x05d928ae, 0x08cfa15d, 0xbc6f11c8, 0x1a949f97, 0x5ebbf637, 0x000b72da, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x0740ba53, 0x40a54318, 0x881bd078, 0x3e1dd87a, 0x926e8f70, 0x00000013, 0x00000000, 0x50000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x0a2fc288, 0xea86c21d, 0x147c6a30, 0x0b939da3, 0xe577c4b3, 0x4ef937b6, 0x62d73617, 0x80000001,
+    0xc4572f45, 0x59a1a0d1, 0xa452519f, 0x366d7780, 0x7675bc9f, 0x4fc6e713, 0x519f1ed7, 0x80000001,
+    0x7985f960, 0x18f91b3e, 0x5938e321, 0x3e4a9d06, 0xfba83297, 0xc28455ec, 0xc3761745, 0x80000000,
+    0xd9b7cf08, 0x5bbf08c4, 0x999e8c53, 0xb6a7839f, 0x48b6bd43, 0x1259e0d7, 0x5b3b1b5f, 0x80000001,
+    0x1d95d5ac, 0x4be98a9d, 0x15b30c79, 0x80a3fb9a, 0x55b593c1, 0x42694816, 0x7bcb48e7, 0x80000001,
+    0x2748e464, 0x6d3d0f5f, 0xb23bc573, 0xb4d901d7, 0x5fe84c63, 0xa28589ce, 0x817d787c, 0x80000000,
+    0xdebfb04f, 0x29b6f374, 0x0200048f, 0x00800100, 0xa0a3dd40, 0x0004144b, 0x00000000, 0x40000000,
+    0x40ba980e, 0xe6ec401b, 0xf014588d, 0x0236c93d, 0xb1b1148b, 0x4473ef4d, 0x3f170357, 0x80000001,
+    0x41e5a121, 0x77d82052, 0xbc2180e2, 0xcb47fd56, 0xd2b35e0f, 0x6914bdef, 0x5f6b32f7, 0x80000001,
+    0x82a41c8d, 0x07e4608c, 0x003cf127, 0xb94d6f54, 0x1d327e93, 0x5bf51ab0, 0x5b5f2b27, 0x80000001,
+    0x01601e0c, 0x073cc02f, 0x201720a5, 0x3e3ccf44, 0x0ab1518d, 0x3554220e, 0x2fb6ed9f, 0x80000001,
+    0xc246a740, 0x38b2005d, 0xf42cc922, 0xe8527d67, 0x8a33b012, 0x4a251f70, 0x41eb0bb7, 0x80000001,
+    0x4c49e9ab, 0x20852239, 0xc013104c, 0x4809fa30, 0x53ec546e, 0x00000012, 0x00000000, 0x50000000,
+    0x442eb069, 0xc936009f, 0xa03ac956, 0xf857956d, 0x62b46795, 0x5955b031, 0x4f271e3f, 0x80000001,
+    0x8289225e, 0xa79d6061, 0x141770bd, 0xf3393f38, 0xc82e758a, 0xd8835b6c, 0xf7ea9ca6, 0x80000000,
+    0x41ea213f, 0x27c20043, 0x281bc8cf, 0xae3c4545, 0xb8b08a0b, 0x2c93c08d, 0x2deaedbf, 0x80000001,
+    0x39577938, 0x28f45b12, 0x5d34f31b, 0xab4d1b0c, 0x16285d17, 0xc9d45fad, 0xc36a1905, 0x80000000,
+    0xdb12d1d0, 0x7bf7e96e, 0x71b46c7c, 0x46ac0ba4, 0xb6b742c6, 0x1eaa2617, 0x631726b7, 0x80000001,
+    0xd414c582, 0x7a6c263a, 0x8528cb70, 0xd8881575, 0x733207b1, 0x18579053, 0x640b2427, 0x80000001,
+    0x2762e4a9, 0xfd398f5a, 0xea393d6f, 0x4ad585d3, 0xebe12be1, 0x85541b2a, 0x4658eb9b, 0x80000000,
+    0x9e6b229f, 0xe75c3035, 0xf211f49f, 0x00800143, 0x25eb5ec0, 0x000659b0, 0x00000000, 0x40000000,
+    0x40388bf1, 0xe5a9e008, 0x440af855, 0x132b852d, 0xd36ec207, 0xf522844a, 0xf5ca9a2e, 0x80000000,
+    0x00e21590, 0x76bea030, 0x4015a890, 0x85448747, 0x3b31a70f, 0x2b53f72e, 0x2386df0f, 0x80000001,
+    0x88b8aba3, 0xfa9c620b, 0xb4c4a2a3, 0x5873ad80, 0x3ef5c326, 0x89f6f393, 0x802b5d47, 0x80000001,
+    0x405f0fdc, 0x762d0009, 0x1008f05f, 0xa728c52a, 0x03ad9b05, 0xc7921d2a, 0xcfea60ee, 0x80000000,
+    0x40dc1289, 0x26e4a02c, 0xf01970a5, 0x6b3b8d41, 0xe7b0d70c, 0x25c3e7ad, 0x2682e10f, 0x80000001,
+    0x675e7906, 0xd08ee20e, 0x5009601a, 0x91074e19, 0x9d2b926a, 0x00000012, 0x00000000, 0x50000000,
+    0x417c1439, 0xb7a06045, 0x8c2750f4, 0x44447b4c, 0x56b0f78f, 0x3fd42dce, 0x411b060f, 0x80000001,
+    0x808f1194, 0x566a201c, 0x700b606b, 0xd42b0927, 0xe4ed3d86, 0xcf4286ca, 0xe83283f6, 0x80000000,
+    0x813d976a, 0x4749802c, 0x581f48c8, 0x0d411549, 0x3671450e, 0x44f40eae, 0x3f870477, 0x80000001,
+    0xbaee7ae1, 0xca825c42, 0x9598bbfe, 0x356c433f, 0x4e6b61a7, 0x03859aef, 0xe2de4a56, 0x80000000,
+    0x20b559be, 0x7cb44ca9, 0x76138d15, 0x30b83db2, 0xbd787dce, 0x415acfb8, 0x75fb41df, 0x80000001,
+    0x920641b0, 0x29f0e562, 0x81049322, 0x737d7d67, 0x1d305e2c, 0xfd66cfd2, 0x54bf0c76, 0x80000001,
+    0xe9976734, 0x9d7690cc, 0x4e5d45a4, 0x45dca5db, 0xb5a5f3e6, 0x496577ed, 0x3cb8d14b, 0x80000000,
+    0x601c94f9, 0xf6700e5a, 0x61c002f0, 0x9bb0b4ce, 0x6cbb72dd, 0x000d709c, 0x00000000, 0x40000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0xc75115ce, 0x8cbe82e8, 0x1215f4ee, 0x42cfb7de, 0xb37dcd5e, 0xe45dc9bc, 0xdccbd57f, 0x80000001,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x01580c39, 0x083ce037, 0xd04d7146, 0xd9636379, 0xf976739c, 0x74069772, 0x5bfb294f, 0x80000001,
+    0x3b0e7905, 0x008a41e4, 0xec02b03b, 0xeb018e09, 0xef32246b, 0x00000017, 0x00000000, 0x50000000,
+    0xc11d91fb, 0x55e0203e, 0x2c258092, 0xd43f4320, 0xbdb60093, 0x8ee74e73, 0x7eef55ff, 0x80000001,
+    0x00160614, 0xa4990005, 0xcc06f83e, 0xad289d1a, 0x98af6a06, 0x1c42af0b, 0x1272c177, 0x80000001,
+    0x03279a1d, 0x596a4053, 0x5085e9fe, 0x3a8c119a, 0x68396332, 0xa0698357, 0x91cb78f7, 0x80000001,
+    0x3db5fda8, 0xac411e4c, 0xe1de1cc1, 0xd7c321bd, 0xcefa4ed5, 0x6f2c637a, 0x9fe377e7, 0x80000001,
+    0xf6aef4b5, 0x9dc159ff, 0x02cffe23, 0x11ca87c9, 0x067953dc, 0x5d7b729a, 0x8c9f56e7, 0x80000001,
+    0xd714c9eb, 0x2a9a27ca, 0x394c7b9d, 0xa7878571, 0x29f17132, 0x2d677a13, 0x732f383f, 0x80000001,
+    0xb83077b1, 0xaf18da93, 0xbf5b2f26, 0xe5f0e7f0, 0x2f5c4c74, 0x21425568, 0x66dd3b8c, 0x80000000,
+    0x1555a492, 0x88000e00, 0x62777bd3, 0x86510af1, 0x0030002c, 0x00040010, 0x00000000, 0x40000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x524936db, 0x0d556492, 0xeeaaae00, 0x4f89d9c4, 0x6bfaf2ac, 0xf96a1b18, 0xf35bf1b7, 0x80000001,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x00930a2d, 0x07100015, 0x34180090, 0x3130c54d, 0x1134448c, 0x746599b1, 0x745f2e8f, 0x80000001,
+    0xb943f943, 0x706821a0, 0x9004d813, 0xa700ee05, 0xb87e14fd, 0x0000001e, 0x00000000, 0x50000000,
+    0x41278716, 0x6785a031, 0xa834e0c8, 0xee508168, 0x00300014, 0x92558e50, 0x50030497, 0x80000001,
+    0x00110640, 0xf5054005, 0x7c094852, 0xd637cb37, 0x07725e0b, 0x3d94b5cf, 0x2d66ea4f, 0x80000001,
+    0x85f928f6, 0x2bd880da, 0xc8d402e4, 0x5d9cafc5, 0x0e3cd639, 0xd27aae79, 0xc967ba27, 0x80000001,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0xc173a0d7, 0x76e1e02e, 0xb019c8a6, 0x48523960, 0xfcf54494, 0x58c607f1, 0x4c5b184f, 0x80000001,
+    0xd401b583, 0x080012ef, 0x02000400, 0x00800100, 0xa1e0d0c0, 0x00032a49, 0x00000000, 0x40000000,
+    0xc1951f9a, 0xe6e7602d, 0xb01d48b2, 0x355e196d, 0xf8b6ef99, 0x53a72a53, 0x4b17192f, 0x80000001,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x42672600, 0xc8948049, 0x7027c10d, 0x9e4cbd63, 0x88b33d90, 0x22e4866f, 0x1472cd47, 0x80000001,
+    0xc1cf1ca7, 0x76d2a04a, 0x902a68d9, 0xd876a188, 0x32b95823, 0x0008a737, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x055b2c8b, 0x602b2234, 0x08049845, 0x6206ee31, 0xbfdfe267, 0x0000000a, 0x00000000, 0x50000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0xc3e73117, 0x98cbc08b, 0x182f3125, 0x6b624d7d, 0x0f747218, 0xf54544d1, 0xe84e960e, 0x80000000,
+    0xc1bea084, 0x483ee03c, 0xf82368f0, 0xce4d4f64, 0x6eb34090, 0xfee46eaf, 0xf2f29ece, 0x80000000,
+    0xb65d7636, 0x14c118f3, 0xb03940f7, 0xe92f60ce, 0x91e2650b, 0x3702c4e9, 0x8e79b27d, 0x80000000,
+    0x57a94b22, 0x4b5c07ff, 0x057e4c12, 0xf99dd193, 0x2575863d, 0xefb92796, 0x46befa76, 0x80000001,
+    0xd21ec2d4, 0x0a11a535, 0x0102c32c, 0x6f7cf568, 0x0ef088ab, 0xac06b0d2, 0x225ec236, 0x80000001,
+    0xa1d45d4b, 0xbc878c39, 0xe5dfc4dc, 0x28c12fbd, 0x219948d3, 0x6361c386, 0x3bf0d5bb, 0x80000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0xc0a5182c, 0x75d18016, 0xb40d6060, 0xf137393d, 0xa9ef068a, 0xea22d40b, 0xf22e827e, 0x80000000,
+    0x9791af37, 0x08aaf11b, 0x0200045b, 0x00800100, 0xd021ce40, 0x0003906a, 0x00000000, 0x40000000,
+    0x00a9952a, 0xf5908012, 0xfc0f806f, 0x633a9539, 0x90ee040b, 0xc662fe0b, 0xdb525ece, 0x80000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x82141f3a, 0x37c84055, 0x58358105, 0x904da95a, 0x90f2d993, 0x34e4bc2f, 0x2c32e977, 0x80000001,
+    0xc0909529, 0x758d400d, 0xf80be861, 0x6e3c5341, 0xbf70940b, 0xdc23a32d, 0xd8fe6d76, 0x80000000,
+    0x40cb1443, 0xd6baa020, 0x0418b0a7, 0x6442914f, 0xb271d00e, 0x0654390e, 0x035eaf87, 0x80000001,
+    0x09aa4ec0, 0x7043e20a, 0xf40d887a, 0x6b02b216, 0x8edf3ee8, 0x0000000a, 0x00000000, 0x50000000,
+    0x41d49adb, 0x57e7e046, 0xcc2b6905, 0xea4e4960, 0x4eb2a811, 0x18447f8f, 0x106ac417, 0x80000001,
+    0x00f31ad0, 0x865ee01c, 0xb40f607b, 0x3532fb37, 0xdeaf4209, 0xb0c2deab, 0xc03648ae, 0x80000000,
+    0x01121c12, 0xa6e3a019, 0xf8110897, 0xcd33b73b, 0x076f8e08, 0xde42e9ec, 0xe1627be6, 0x80000000,
+    0xb732770d, 0x864e198e, 0xf45be16d, 0x883a6ee7, 0x8c241d0f, 0x562328ea, 0x9969c945, 0x80000000,
+    0x5a67d076, 0xdbbda95a, 0x91a3e454, 0xfea4919b, 0xed366341, 0xfd59a096, 0x53fb0f8e, 0x80000001,
+    0x515fc077, 0x69c544fc, 0x44f44306, 0x377a6d62, 0xb72fe32a, 0xbab680b1, 0x2b2acf7e, 0x80000001,
+    0x6310df19, 0x5cb1acd5, 0x59f3d500, 0xb7c375c0, 0x89993a54, 0x45520006, 0x3b0cd013, 0x80000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x01069b27, 0x96e8c00c, 0x4c0dd857, 0x7a22c525, 0x16a81083, 0xaa70ad26, 0x43795d65, 0x80000000,
+    0xd760a269, 0x2816ad6c, 0x5a4603a2, 0x00800144, 0xb52ac540, 0x0005c56f, 0x00000000, 0x40000000,
+    0x004291e4, 0x353a800b, 0x28014019, 0xf0103ce5, 0xd0244600, 0x01a06023, 0x1dbcda05, 0x80000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x84099975, 0x99c240e9, 0x649b2a31, 0x305e9f71, 0x2c33901b, 0x65f58550, 0x56eb1fbf, 0x80000001,
+    0x0149a190, 0xf7130023, 0x8c1928c0, 0x2046d360, 0x71f0978c, 0x85427c8c, 0x8979f4ce, 0x80000000,
+    0x40e50c3b, 0x7711002b, 0x801df8b2, 0x0957eb61, 0x03b58917, 0x40560ad2, 0x2f7afab7, 0x80000001,
+    0x1163b657, 0x002a814f, 0x840c5840, 0xd701e40f, 0xc0641169, 0x0000000c, 0x00000000, 0x50000000,
+    0x00951014, 0xd76fc017, 0x7011787c, 0xe22dfd26, 0xb2eb8008, 0x3bc26469, 0xae2dffa6, 0x80000000,
+    0x802887e9, 0x44c44005, 0x8808b844, 0x7026991d, 0xbbec2106, 0x79e22809, 0xb736227e, 0x80000000,
+    0x40668af7, 0xd70e400c, 0x7c1998b3, 0x53407d4e, 0xdb70920d, 0x05e37f2c, 0x0d1ab517, 0x80000001,
+    0x39907979, 0x9940bb2d, 0xc1307352, 0xb06ab944, 0x31ab1f25, 0x0d056c2f, 0xe18e45b6, 0x80000000,
+    0x22415a40, 0x3ca34dc2, 0x9e1e850b, 0xefba79b4, 0x01b8e94f, 0x424af6d9, 0x6d57371f, 0x80000001,
+    0x12fc425d, 0x39d44570, 0xf101631a, 0x3476ef58, 0x1b6dffa9, 0xc2a63551, 0x3b3adde6, 0x80000001,
+    0x27fd652c, 0xed6cd041, 0x526de5cd, 0x18d2ebd1, 0xfa59745f, 0x60b1c565, 0x3b20d153, 0x80000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x574f9e9c, 0x67dc5441, 0x0a27f323, 0xac9452ec, 0xfcf4970f, 0x000ab556, 0x00000000, 0x40000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x86301f53, 0x3b60c1bd, 0x01437b5a, 0xc0b781c8, 0x29fd0fc7, 0xd5bd58fc, 0xd543d127, 0x80000001,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x807605bc, 0x38cb6036, 0x2c197096, 0x87a549bb, 0xf73ede37, 0x961c6cdb, 0x2352c23f, 0x80000001,
+    0xd492ca49, 0x402ce0a9, 0x54978163, 0x63015c36, 0xd9724df6, 0x00000016, 0x00000000, 0x50000000,
+    0x40f30ac8, 0x469a802c, 0x501fe0a6, 0x8d434551, 0x6134f70c, 0x7be69ef1, 0x7be3605f, 0x80000001,
+    0x001a0390, 0x04c38005, 0x08062045, 0x542fc12a, 0xf3301908, 0xf633426c, 0xfab2a9ae, 0x80000000,
+    0xc409224d, 0x5961c0a2, 0xf46d8a00, 0x5d8e499e, 0x4939e0ad, 0x67d85ef5, 0x4d77214f, 0x80000001,
+    0x7b5f7bc2, 0xab41dcc7, 0x858123c9, 0x1d94fd7a, 0x3476653d, 0xfdfa2f57, 0x5b1f14a6, 0x80000001,
+    0x392ef6f7, 0x8e895bd3, 0x3315c682, 0x74c5d3da, 0xb47a1359, 0x014aaab7, 0x5486e8bf, 0x80000001,
+    0xda834d5e, 0x1afc0866, 0xd14c7ba4, 0x1288b579, 0xacef0b2f, 0xcfa67a91, 0x31aed2e6, 0x80000001,
+    0xb531f6c4, 0x6f1ad821, 0xff522f22, 0xdbe949e8, 0x4de1e9ef, 0x2b537dab, 0x60fd5204, 0x80000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20004000, 0x08001000, 0x02000400, 0x00800100, 0x00300040, 0x00040010, 0x00000000, 0x40000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x5555d555, 0x55557555, 0x55555d55, 0x00555755, 0x00200060, 0x00000008, 0x00000000, 0x50000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0xfb04f7b3, 0xfba1daf4, 0xf7e81fdf, 0x00ce7be2, 0x00000000, 0x00000000, 0x00000000, 0x20000000,
+    0x515aab47, 0xe322076d, 0x347b2948, 0x14000028, 0x9421f3e5, 0x1215734e, 0x37b0bbfa, 0x10000000,
+    0x7d8ffc23, 0xfdf93e07, 0x0000055d, 0xc7000000, 0xed7f23fe, 0xe8ee937e, 0x00000005, 0x10000000,
+    0x92b969ed, 0x230d478b, 0x3069812b, 0x6b00001d, 0x2793e734, 0x47c34ec8, 0x244074c9, 0x10000000,
+    0xfd2d7b14, 0x4e301dcc, 0x025e3e60, 0x6f000000, 0xfefed1fe, 0x92bebfbe, 0x00027576, 0x10000000,
+    0x02ed06cc, 0x9084e13c, 0xe0133834, 0x3e000005, 0xd292842c, 0x3ff32f47, 0x22747661, 0x10000000,
+    0x3e2dfd53, 0x2eacde8c, 0x2af476d6, 0x270000d3, 0x65bf507f, 0xb73ee03f, 0xef02c87e, 0x10000000,
+    0x22d5e919, 0xd5e88edc, 0x9cc6aa37, 0xa9000036, 0xc0cd9772, 0xdd925545, 0x11f84a30, 0x10000000,
+    0x7be1fa58, 0xfcf13bf2, 0xa261a5b8, 0x7149f8e7, 0x4afe02fe, 0x734e845e, 0x9cb61a35, 0x10002ac4,
+    0x18c639d3, 0xe44b4a4a, 0x28887195, 0x2a000025, 0x3902cf86, 0x3af08821, 0x06f81730, 0x10000000,
+    0x7b8d7b32, 0x1c341b15, 0xea20751a, 0xb33ff0cd, 0x0000000f, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0xfe267d48, 0x6d375ced, 0x1662fda1, 0xa45540e9, 0x00093f1b, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x6d73622b, 0xf6ab9213, 0x7b800763, 0x007b3f75, 0x00000000, 0x00000000, 0x00000000, 0x20000000,
+    0x7137095d, 0x75de3327, 0xccb22ae1, 0xead5120b, 0x0008c439, 0x00080010, 0x00000000, 0x30000000,
+    0x2bc85f36, 0x26cb3265, 0x000001a6, 0xee000000, 0x02f7f275, 0x15695358, 0x00000002, 0x10000000,
+    0xfc6a03da, 0xa767958f, 0xc4a412b8, 0x5add7a05, 0x0008a3c0, 0x00080010, 0x00000000, 0x30000000,
+    0x2b465e5f, 0xa6dcd1b8, 0x0075027a, 0x7d000000, 0x4579e4f8, 0x83bb433a, 0x0000b124, 0x10000000,
+    0x6bdc8363, 0x83e34e60, 0x6097b250, 0x74df1207, 0x0008a5c2, 0x00080010, 0x00000000, 0x30000000,
+    0xea206093, 0x466eb0dd, 0x98a78227, 0xfa00001c, 0xb477e076, 0x9f58ad78, 0x27817703, 0x10000000,
+    0x7df5979a, 0x65f25492, 0xf8d47378, 0xbfd4620c, 0x5fc6992c, 0x000520ff, 0x00000000, 0x30000000,
+    0x701666fe, 0x88a413ac, 0xc5360b6d, 0x761a7e62, 0x66b9a679, 0x883b0a3a, 0x7c2d1832, 0x10000e48,
+    0x7fa21828, 0x6407375c, 0x80444a66, 0x00800002, 0x00200040, 0x00080010, 0x00000000, 0x30000000,
+    0x6c82e39f, 0xc699d08d, 0x4916d2ae, 0xbd222862, 0x00000003, 0x00000000, 0x00000000, 0x00000000,
+    0x20004000, 0x00a49000, 0x020c0400, 0x806d0134, 0x2026c044, 0x0000000f, 0x00000000, 0x30000000,
+    0xb8fcf590, 0xb7a896e3, 0x85092273, 0x27250a61, 0x0003b211, 0x00000000, 0x00000000, 0x00000000,
+    0xd880bbc1, 0x080014e8, 0x02000400, 0x00800100, 0x28e2b6c0, 0x0003ea6b, 0x00000000, 0x40000000,
+    0x816f9c6a, 0x57cf805a, 0xd440112c, 0x2472176c, 0xacfac5a5, 0xa14a3d78, 0x8ffb7847, 0x80000001,
+    0x82b226a1, 0x789220a3, 0x2c38a92a, 0x6e68176d, 0x6af9471e, 0xaa888216, 0x99f38507, 0x80000001,
+    0x43a3b09a, 0x19158081, 0x803fd973, 0x275eb367, 0x65f37818, 0x46a5a3b1, 0x55d7208f, 0x80000001,
+    0xc2911844, 0x57a300a6, 0xf0532166, 0xe788217d, 0x703c48b0, 0x000b607a, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x45a03b68, 0x10986306, 0xa816406e, 0x67159455, 0x7268d968, 0x00000010, 0x00000000, 0x50000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x464bb958, 0xd99f4127, 0x505439b0, 0x157c8b74, 0x17310d29, 0x99b73973, 0x1e22bda6, 0x80000001,
+    0x82b923f1, 0x88afc080, 0x9838f14e, 0x7261ff6c, 0xc8b2ff19, 0x0b45f931, 0x350ef0df, 0x80000001,
+    0xb8eff8c9, 0x58ef1ac5, 0x6945cb33, 0x73433cf9, 0x1326ce14, 0xb3d3eeec, 0xbb0e0885, 0x80000000,
+    0xd85fcc9a, 0x2ba267f9, 0x9d92e442, 0x41a5d79d, 0x2ef697c2, 0x16d9c317, 0x59f71cbf, 0x80000001,
+    0x1a5dd0da, 0x2ba0e8ee, 0x358bb43d, 0xbc9c8d92, 0x57f480bc, 0x12f89b95, 0x5cc71c97, 0x80000001,
+    0x2733e470, 0xdd4b0f41, 0xda3c2579, 0x81d371d1, 0x5a67a85f, 0x386592ce, 0x69394004, 0x80000000,
+    0x57a53032, 0xf7b6d0fe, 0x0200046b, 0x00800100, 0x5020c0c0, 0x000392ea, 0x00000000, 0x40000000,
+    0x80601272, 0xf5a8c012, 0x480ec05a, 0x5233712d, 0x8c72098b, 0x4ef46aae, 0x40770757, 0x80000001,
+    0x80ee1b0c, 0x56adc02e, 0x1414f885, 0xf5403d45, 0x4a73db0e, 0x6dc515d0, 0x5d1b3187, 0x80000001,
+    0xc1e59f1a, 0x9766004d, 0x242ba0e8, 0x9d4af353, 0x44b34392, 0x53451990, 0x49eb1587, 0x80000001,
+    0x807813c2, 0xc5e7c014, 0x0c0fa069, 0xc53d0b3e, 0x7872f60d, 0x46a4b8ef, 0x3626fb9f, 0x80000001,
+    0x81181a7c, 0x0810603d, 0x0426d0f1, 0x1458eb71, 0x6f74e415, 0x56358111, 0x447311af, 0x80000001,
+    0x458a4479, 0xe054216b, 0xc00a7027, 0x8506081d, 0xbca528e5, 0x0000000e, 0x00000000, 0x50000000,
+    0x41c8a598, 0x58274051, 0x082d190b, 0x6b601b78, 0x5f35c298, 0x5c360e32, 0x4b471acf, 0x80000001,
+    0x80d617f4, 0x663d4022, 0x140d586b, 0x95340f31, 0xefef3a09, 0xd933584c, 0xf1a295fe, 0x80000000,
+    0xc0c89d4e, 0x76b24020, 0x5412888a, 0x913b0942, 0x43b1b88b, 0x2bb3f00e, 0x241ae1a7, 0x80000001,
+    0x38a2f894, 0x484a9a8e, 0x1d139aca, 0x9242aaf9, 0x13a6db93, 0xa8a3e2cc, 0xb66a00ad, 0x80000000,
+    0x98f64d06, 0x0bcdc871, 0xbda2745f, 0x7aa973a1, 0x85771b44, 0x1a89f8b7, 0x5e7f20ef, 0x80000001,
+    0xd2e54357, 0x3a4e45b3, 0x151d3b5d, 0x72866174, 0x33b1c7b0, 0xf6875a93, 0x4d43042e, 0x80000001,
+    0xe633e348, 0x3d170eae, 0x82258551, 0xd1cf4dcd, 0xc52137dc, 0x48a4a90b, 0x3ea4d3db, 0x80000000,
+    0x96f62877, 0x3781b0b7, 0x25889c39, 0x008000cf, 0xbd2589c0, 0x0004b14c, 0x00000000, 0x40000000,
+    0x40288a4b, 0xa4bd2007, 0x1007e835, 0x6424db1c, 0xdbee4186, 0xf5b297ea, 0xf24293d6, 0x80000000,
+    0x807811c8, 0x05d1e015, 0xb00e105e, 0xc9365338, 0xa3f1398b, 0x24b3d4ad, 0x1dced61f, 0x80000001,
+    0x431b20a6, 0xe8f8c078, 0x8c4e9978, 0x95673d7c, 0x6136b11d, 0x8136d3f3, 0x70274a97, 0x80000001,
+    0x00268cb2, 0x9509a005, 0xc004d832, 0x2c1f9d17, 0x932d1084, 0xcbc1fa89, 0xcf4a5e96, 0x80000000,
+    0x005d0de8, 0x76338010, 0x74118077, 0x653c0744, 0xaab26e8c, 0x3534306e, 0x2526e38f, 0x80000001,
+    0x8ec975ac, 0x1027a0b6, 0x68024808, 0x7d01f409, 0xeee2d162, 0x0000000d, 0x00000000, 0x50000000,
+    0xc0979521, 0xa6846018, 0xd4129086, 0x753c9d45, 0xbd326d0c, 0x44143ece, 0x3362f73f, 0x80000001,
+    0x402e0eb6, 0x75354008, 0xe0060039, 0x53252f1e, 0xd46e5e85, 0xdaa25caa, 0xdb1273d6, 0x80000000,
+    0x40ca1768, 0x16da801a, 0x0c1a28af, 0x4c462d54, 0x7cf35f0f, 0x41c4854f, 0x2e56f217, 0x80000001,
+    0xb9d479c2, 0xd889fb6f, 0x9518dae0, 0xa0533316, 0x0669ce9a, 0xe5f4dc8e, 0xd15a2fbd, 0x80000000,
+    0x9c1951bc, 0xdc222a46, 0x49d49cac, 0x86b0c3aa, 0x3477dd49, 0x2dca7898, 0x6cb734b7, 0x80000001,
+    0x9035be2a, 0xa9b80495, 0x58f2c2ff, 0xee7b5d64, 0xffb03b2a, 0xe726b311, 0x45faf70e, 0x80000001,
+    0x283465af, 0x9d4fcfe8, 0x4a42557e, 0x44d2cdd1, 0x56d873df, 0xdb229ce7, 0x2b3ca412, 0x80000000,
+    0x58531a79, 0x76644eaf, 0x69e32b72, 0xf276e6ab, 0x53b4dbc2, 0x00085275, 0x00000000, 0x40000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x580f49f3, 0x2d1cc818, 0x99a40487, 0x56afcbc3, 0xf63ae646, 0xbd5a9bd8, 0xb563a28f, 0x80000001,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x00e28d36, 0x779f0024, 0xf82c00eb, 0xfc553569, 0x99347294, 0x51e52f90, 0x43c70cef, 0x80000001,
+    0x7b97fbec, 0x0069a1f7, 0x30025823, 0xfa013208, 0x57b2a4f3, 0x00000016, 0x00000000, 0x50000000,
+    0x409f0dc2, 0x76df001a, 0xc81db0b1, 0x70496f5b, 0xe373d590, 0x5d04b56f, 0x491f1747, 0x80000001,
+    0x001d07df, 0x156f4005, 0xdc084850, 0x6a2e3535, 0xe3300507, 0x1cb2d4cb, 0x0ddebf1f, 0x80000001,
+    0xc2311b27, 0xe94e803b, 0x804a7991, 0xda6ecf8d, 0x3a36d69e, 0x8df69693, 0x7d835bdf, 0x80000001,
+    0x3bd3fbdf, 0x5b1bdcdd, 0xb1606bd5, 0xbb9db58c, 0x68f4263f, 0xc168ffb5, 0x3bd6e096, 0x80000001,
+    0x6711e0f6, 0x5cadf043, 0xaa04f50a, 0x88b0d3aa, 0x2d77d1c8, 0x389a61b8, 0x6d033d5f, 0x80000001,
+    0x94ee468d, 0xca470695, 0xcd282365, 0xd383616d, 0x91f0bf2f, 0x0d971bd2, 0x5ea31adf, 0x80000001,
+    0x705b6f28, 0xae319524, 0x8ece5e4c, 0xe9e605e5, 0xa79b5dec, 0xb1027047, 0x4d5cff63, 0x80000000,
+    0xa9ec1813, 0xe7ea0faa, 0x6920e2e7, 0xd496c6c9, 0x00300025, 0x00040010, 0x00000000, 0x40000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x5c934c96, 0x7eaf0b8d, 0x8eee6e61, 0x3bdf7fea, 0x51bddae5, 0xeacdb29d, 0xe707e01f, 0x80000001,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x82a01204, 0x67bda0d0, 0x104ad939, 0xc15c0571, 0xd9746118, 0x6445ac90, 0x4beb1b0f, 0x80000001,
+    0xfc6b7e22, 0x3061a1b8, 0xbc01601c, 0xf500f01d, 0xf13a84fb, 0x0000001b, 0x00000000, 0x50000000,
+    0x80918876, 0xd638c018, 0xb02580af, 0x37476950, 0x61730212, 0x4084c86f, 0x3436f547, 0x80000001,
+    0x001603e7, 0x95254005, 0xd80c5875, 0xdd3c1340, 0xa031b10b, 0x0a339eed, 0xfc62ab2f, 0x80000000,
+    0x4496a6d6, 0xeaeca09e, 0x28b612af, 0x2f9f13b6, 0x163b38bc, 0xb35ad3f9, 0xa2178bdf, 0x80000001,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x41b61d2e, 0xe74de045, 0xf02740d6, 0x2d595f68, 0x5936ad18, 0x6ee6bc13, 0x4bb32457, 0x80000001,
+    0x95aeb091, 0x08001187, 0x02000400, 0x00800100, 0x4a2196c0, 0x00036d6a, 0x00000000, 0x40000000,
+    0x41a81c80, 0x573b6038, 0x502380d3, 0xe05f1f70, 0x97f6dc18, 0x49b69fd3, 0x2e12f7c7, 0x80000001,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x0175a3f5, 0xa8126029, 0x701a08cf, 0x52448358, 0xe232dd8d, 0x0a94140e, 0xf91eaa8f, 0x80000000,
+    0x81629899, 0x96fcc030, 0xc01ad8ba, 0x9c67f17c, 0x48f88e1a, 0x00079955, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x030a181e, 0x50174186, 0xf404183a, 0xf9046421, 0x341ae2de, 0x00000008, 0x00000000, 0x50000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x423026da, 0xf7d58047, 0xac1a38c3, 0xcb4c0f5f, 0x9432458f, 0xcfd4060e, 0xb00a4e16, 0x80000000,
+    0x80f01937, 0x177d4021, 0x501508a7, 0x113fc552, 0x0c31f28c, 0xd8a3a96e, 0xd2366e66, 0x80000000,
+    0xb459744f, 0x9490176e, 0x643e30f1, 0xae27dcbb, 0x299fd309, 0xf4922ea8, 0x79958964, 0x80000000,
+    0x95dcc756, 0xfb066738, 0xb15dfbd3, 0x0598178d, 0x5834b4ba, 0xd6889555, 0x3382e1ee, 0x80000001,
+    0xce39ba65, 0xb93b83b5, 0x18c512a6, 0x176f8554, 0x71ee83a4, 0x6d05cbf0, 0xfeea8b96, 0x80000000,
+    0x5fccdb3e, 0x2c520b10, 0x21bcfcad, 0x13b51db1, 0x5996cf4b, 0xec417885, 0x2ad8a7b2, 0x80000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x808a1940, 0xc608e011, 0x380bf856, 0x582b552a, 0x432e7908, 0xf762f86b, 0xf76a937e, 0x80000000,
+    0x94fa299b, 0x382acdc9, 0x0200041f, 0x00800100, 0x47e2e6c0, 0x0004092b, 0x00000000, 0x40000000,
+    0x40cd995f, 0x65e8000e, 0x900a385f, 0x4a2b1522, 0x9dacb907, 0xbd42aeaa, 0xd2ea59f6, 0x80000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0xc1d1a0ac, 0xf7b3603c, 0x2c1ec0d0, 0x2342ad50, 0x03b2d08e, 0x25e4448f, 0x12a6ccd7, 0x80000001,
+    0x009a979b, 0xe5c0200a, 0xc4078852, 0xa5317d33, 0x61b00407, 0xd3d2f14c, 0xc92661ce, 0x80000000,
+    0xc09b11cc, 0x46ebc018, 0xb414e099, 0xce415150, 0xc232978d, 0x1a24356e, 0x05eabc37, 0x80000001,
+    0x83841959, 0xf0222196, 0x1c072041, 0x41015c0d, 0x24da3ade, 0x00000008, 0x00000000, 0x50000000,
+    0x013c1b1f, 0x378be026, 0x0c1758b6, 0xe040d351, 0xa2f26e8c, 0x1484156e, 0x01eeb2e7, 0x80000001,
+    0x80861528, 0x45d1c00f, 0xec095851, 0x63278b24, 0xc32e7e06, 0xac32684a, 0xb4f635be, 0x80000000,
+    0x80949955, 0x066e200d, 0x980a3064, 0x532d6d32, 0xe52ff507, 0xda52decb, 0xd272673e, 0x80000000,
+    0xf5867572, 0xc4e4f852, 0xd4485111, 0x1e2becc3, 0xd760f40b, 0x1c028168, 0x86f5a355, 0x80000000,
+    0x5862cb31, 0x2b656884, 0x51839c1a, 0xf49f7b97, 0x8636103e, 0xf6d94d96, 0x48b70136, 0x80000001,
+    0xce84ba8b, 0x494803e3, 0x84ca3ab3, 0xbb702354, 0x94ee55a4, 0x80e5e650, 0x0f06a20e, 0x80000001,
+    0x20e25c5e, 0x3c580b9c, 0x19c234af, 0xc6b541b0, 0x11d749cb, 0xe0b1df86, 0x2d10a8a2, 0x80000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0xc0649afa, 0xe5d8c008, 0x9406482c, 0x0210bef2, 0x05260e82, 0xa3b0a1c5, 0x3c293fe5, 0x80000000,
+    0xd4182164, 0xc6c38ead, 0x91c0a34b, 0x008000d9, 0xd7e4bc40, 0x0004da6c, 0x00000000, 0x40000000,
+    0x002394d5, 0xa3d4c005, 0xdc01b017, 0xe809e0b0, 0xf7dffc00, 0x25407502, 0x39b0f665, 0x80000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x02731d91, 0x38c94066, 0x5c43895f, 0xa458856f, 0x2c74d296, 0x3b2550d1, 0x2976ea8f, 0x80000001,
+    0x40ef217f, 0x06c46008, 0xd0066868, 0x552e4f40, 0xac300a85, 0x3c81ccca, 0x7515e406, 0x80000000,
+    0x40858be0, 0xb77d2012, 0xfc1b08bf, 0x744dad64, 0xedb47c11, 0x29a53990, 0x196ed297, 0x80000001,
+    0x89f63cdd, 0x501b4107, 0x1802d01e, 0xbf019a0d, 0xd21ee166, 0x0000000a, 0x00000000, 0x50000000,
+    0xc080903a, 0x268b800f, 0xdc0fc885, 0x3e32e532, 0xff2ee709, 0xee63170b, 0xf4aa954e, 0x80000000,
+    0x003089ac, 0xd55d8006, 0x58085848, 0xc5269720, 0x326d3a85, 0xce62332a, 0xd61e670e, 0x80000000,
+    0x80fd1693, 0xf7818015, 0x141558b0, 0xa83d774e, 0x9ef1c38b, 0x16a3868d, 0x04aab57f, 0x80000001,
+    0xb89c78a5, 0x46d81a72, 0xe07881bc, 0x823fecf6, 0x70659812, 0x72b3a3eb, 0xa3e1d935, 0x80000000,
+    0x1e21d472, 0xcc824b45, 0xb5e6d4d5, 0xd5b1ddac, 0x7037dcc9, 0x268a99f8, 0x694b30df, 0x80000001,
+    0xcfde3d4c, 0x2979c481, 0x58e91ae3, 0x5973a757, 0xb72e6527, 0x9b461430, 0x1d7eb786, 0x80000001,
+    0x23abdf3e, 0xdcb54d55, 0x3dec84ec, 0x15c069bd, 0xd354cc53, 0xfad13ce4, 0x2ce4a912, 0x80000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x16119827, 0x07572c0c, 0xde23eb4b, 0xbb5072c2, 0x11afd50e, 0x000839d3, 0x00000000, 0x40000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0xcb8b2ffa, 0x3c3682fe, 0x111a4b87, 0xa6b7b1ca, 0xeabc0e4c, 0x8f7bfb7a, 0x848763ff, 0x80000001,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x007c069c, 0xb7272016, 0xf01cb0aa, 0xb04c8f5f, 0x40f6d614, 0x192696f2, 0xedb2931f, 0x80000000,
+    0xccd0acbb, 0x10ed838c, 0x9c3008d8, 0x840d2230, 0x7da8456b, 0x0000000f, 0x00000000, 0x50000000,
+    0x005d8a94, 0x95bda00c, 0x9414407c, 0x973e1945, 0xc0b2188d, 0x10741b8e, 0x0142b177, 0x80000001,
+    0x0012832e, 0x4452e005, 0x8008b841, 0xca24c90d, 0x88298185, 0x7cf20ca9, 0xbdae3aa6, 0x80000000,
+    0x41c71655, 0x5831803b, 0x70432947, 0xa1582970, 0x37b3bf97, 0x3dc4610f, 0x1952dbaf, 0x80000001,
+    0xb93f7968, 0xb9ad3adc, 0x10c392a9, 0xcc82a967, 0x0533adb0, 0xbc18bd55, 0x3baadbde, 0x80000001,
+    0x6102d6cd, 0xeb8dcd86, 0x3d7bfc21, 0xbe9a6395, 0x84369abc, 0x06f933b6, 0x52231a47, 0x80000001,
+    0xd0bbc019, 0x392ee4b3, 0xa0d78ab4, 0xe66e054b, 0xecadb224, 0x8065c50f, 0x0f8aa1b6, 0x80000001,
+    0x2fedeedb, 0xfe39f4c7, 0xc2b4264d, 0x4dca83c7, 0x85d58659, 0x41413a24, 0x3220c15b, 0x80000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20004000, 0x08001000, 0x02000400, 0x00800100, 0x00300040, 0x00040010, 0x00000000, 0x40000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x5555d555, 0x55557555, 0x55555d55, 0x00555755, 0x00200060, 0x00000008, 0x00000000, 0x50000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0xf66ff050, 0x48b11753, 0xabdd7fd3, 0x00b171d6, 0x00000000, 0x00000000, 0x00000000, 0x20000000,
+    0x515aab47, 0xe322076d, 0x347b2948, 0x14000028, 0x9421f3e5, 0x1215734e, 0x37b0bbfa, 0x10000000,
+    0x3a22f62d, 0x7c03dba7, 0x00000415, 0xc2000000, 0x353e65fd, 0xcb8d83fe, 0x00000004, 0x10000000,
+    0x92b969ed, 0x230d478b, 0x3069812b, 0x6b00001d, 0x2793e734, 0x47c34ec8, 0x244074c9, 0x10000000,
+    0x7a9676ba, 0x0c729b86, 0x01983500, 0x0f000000, 0xb77e6b7e, 0x4a4e891e, 0x0002173e, 0x10000000,
+    0x02ed06cc, 0x9084e13c, 0xe0133834, 0x3e000005, 0xd292842c, 0x3ff32f47, 0x22747661, 0x10000000,
+    0x7c9b7aaa, 0x5d8d1d88, 0xf6125db7, 0x9e00007e, 0x143ee97e, 0x389ea71f, 0xabb6495e, 0x10000000,
+    0x22d5e919, 0xd5e88edc, 0x9cc6aa37, 0xa9000036, 0xc0cd9772, 0xdd925545, 0x11f84a30, 0x10000000,
+    0xb85873ef, 0x6b619a1a, 0x6992bc84, 0xc41c106d, 0x983b657b, 0x325d7fdc, 0x6965ca4d, 0x10001732,
+    0x18c639d3, 0xe44b4a4a, 0x28887195, 0x2a000025, 0x3902cf86, 0x3af08821, 0x06f81730, 0x10000000,
+    0x385075c0, 0x5b4559ac, 0x75d61496, 0x9a220c94, 0x00000006, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0xf884f520, 0x1adcf91f, 0x35b32460, 0xd32f8c96, 0x00035d8d, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0xe615547d, 0x847e4e2f, 0x1f62c738, 0x0065ab5f, 0x00000000, 0x00000000, 0x00000000, 0x20000000,
+    0x2e4a0c52, 0x7675d361, 0x38feabab, 0x66dfd221, 0x000de3c1, 0x00080010, 0x00000000, 0x30000000,
+    0xe028cb64, 0xf3bdec1d, 0x000000d9, 0x2a000000, 0xd4754172, 0xbd47d115, 0x00000001, 0x10000000,
+    0xf9b1032b, 0x1726b51b, 0x38c2c315, 0xf5e82c0c, 0x000edec6, 0x00080010, 0x00000000, 0x30000000,
+    0x9e8d4536, 0x43d94b17, 0x003fd120, 0x3e000000, 0x0173b770, 0xd228af56, 0x000085aa, 0x10000000,
+    0xab1e0195, 0x641b6d5b, 0x5c8b4208, 0xb6e38009, 0x000ba0c2, 0x00080010, 0x00000000, 0x30000000,
+    0xe0454ac5, 0x44126c4c, 0x2449892d, 0x7d00000e, 0x93ecafe7, 0x2ac4b091, 0x07c04719, 0x10000000,
+    0x78840833, 0xa6c6f49c, 0x79277b2b, 0xe1d7f816, 0xfd886636, 0x0005c15c, 0x00000000, 0x30000000,
+    0x250f5306, 0x75ddceee, 0x30a8720d, 0x550ba633, 0xd92d3b66, 0xe5c557d0, 0x0e783c98, 0x10000078,
+    0xb9c89063, 0xb350ee9d, 0xf49a417c, 0x00800005, 0x00200040, 0x00080010, 0x00000000, 0x30000000,
+    0x2327d111, 0x253b8cdf, 0x70d96216, 0x8e1bba55, 0x00000002, 0x00000000, 0x00000000, 0x00000000,
+    0x20004000, 0x019fb000, 0x020c0400, 0x806d0134, 0x2026c044, 0x0000000f, 0x00000000, 0x30000000,
+    0x67a75a97, 0x35de4ead, 0x9d2a8a9d, 0x0d38ea7f, 0x0001641b, 0x00000000, 0x00000000, 0x00000000,
+    0xd7f035d9, 0x08001176, 0x02000400, 0x00800100, 0x4c607b40, 0x00038b6a, 0x00000000, 0x40000000,
+    0x01001431, 0x57c4e04d, 0xc43e513f, 0x3c711d6a, 0x46fa0a23, 0x81b91d37, 0x67174757, 0x80000001,
+    0x0189196c, 0xd87b6070, 0xc8342124, 0x0869df67, 0x98f9a19f, 0xa3887fd6, 0x8ad778f7, 0x80000001,
+    0x41ed23b3, 0x5897603c, 0x482d3939, 0x0a5a1f61, 0x7df37615, 0x33b57951, 0x3a6b012f, 0x80000001,
+    0x01788eb3, 0x275e605e, 0x303b893d, 0x4d786970, 0xa93b4ea5, 0x0009be58, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x43e53184, 0x505d8206, 0x1814c866, 0x400ed440, 0xdaa04edd, 0x0000000b, 0x00000000, 0x50000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0xc3e5aef7, 0xb89400a8, 0x603b995a, 0xbd5cef34, 0xc668019b, 0x2d54874d, 0xb03dddbd, 0x80000000,
+    0x017b9efd, 0xb7f06044, 0xcc25290f, 0xe657ed54, 0x71b09b94, 0xaf453610, 0x074aa986, 0x80000001,
+    0xb70af732, 0x48949945, 0xcd2bbb0c, 0xdd3906e1, 0xdb64d110, 0x8bc361ca, 0xa855e815, 0x80000000,
+    0x1431440d, 0x0b4e4649, 0xe16563ea, 0xf5a01b98, 0xcc369abd, 0x15c962b6, 0x4d930bff, 0x80000001,
+    0x14fec822, 0x5ab52643, 0xd52c1392, 0xba850177, 0xbe31482e, 0xadb6f212, 0x1d7abd0e, 0x80000001,
+    0x656162b5, 0x7cfe4dd9, 0x4a0bed36, 0x0cc32fc1, 0x6d629c54, 0x8e64180b, 0x41dce7f3, 0x80000000,
+    0x5608b53d, 0xf5ca4d7c, 0x02000356, 0x00800100, 0x25205540, 0x00036aca, 0x00000000, 0x40000000,
+    0x404a8b4e, 0x15716011, 0x8411b86a, 0xc03eab3c, 0xfd73bb8e, 0x3524e48f, 0x1d7ede17, 0x80000001,
+    0x40a00fa0, 0xf660e023, 0x30175889, 0xc447b74b, 0x51b53211, 0x66458751, 0x4d032097, 0x80000001,
+    0xc0f51776, 0xc7064021, 0xd41da8c4, 0xcd489b55, 0xce73950f, 0x35049e6f, 0x230ee317, 0x80000001,
+    0x00478bed, 0xd5c4400e, 0x7c0f286d, 0x7a471350, 0x4034420f, 0x29d4d590, 0x0f2acc2f, 0x80000001,
+    0x410015aa, 0x18808034, 0x2c286911, 0x4f5ecb76, 0xef353c96, 0x4895a131, 0x3416ff17, 0x80000001,
+    0x8473b97f, 0xd03c4109, 0x08093825, 0x18049013, 0x5d1e395a, 0x0000000b, 0x00000000, 0x50000000,
+    0xc1441ed5, 0x788fe03b, 0x8c295919, 0xcc5f4d79, 0xecf56496, 0x44e5a691, 0x3166fb5f, 0x80000001,
+    0x005211d7, 0xa5b9e011, 0x6c09c052, 0xf5333731, 0x11efe088, 0xcbe3496d, 0xd9ca76be, 0x80000000,
+    0x406195bc, 0x8652c011, 0x100db879, 0xa73bc148, 0x63f2568a, 0x1583c62e, 0x047ab9b7, 0x80000001,
+    0x7714f70b, 0xd841b95d, 0x7117a2cd, 0xca37fce0, 0x8924058f, 0x6533344a, 0x9d01cf7d, 0x80000000,
+    0x5664487b, 0x1b80674c, 0x1580cc23, 0xf5a4259c, 0x0776aac0, 0x11399ed7, 0x54df159f, 0x80000001,
+    0x50213ea8, 0xb9b8647c, 0x90e862f5, 0x6f785f62, 0x692f9aa8, 0x99d640b1, 0x1702b22e, 0x80000001,
+    0x63675f97, 0xbcb4cd02, 0x71f01cf9, 0x06bf8bbc, 0xe05fb652, 0xf4540caa, 0x3070af92, 0x80000000,
+    0xd6013287, 0xf61aaeec, 0x6926fb84, 0x008000b0, 0xb0a3cd40, 0x00043ceb, 0x00000000, 0x40000000,
+    0x40268656, 0x44b7c007, 0xa40a2041, 0x192f1d28, 0xfd30aa09, 0x0ec3662c, 0xf8aea467, 0x80000000,
+    0x40590ae3, 0xd601e012, 0xa412d070, 0xdd47cb4c, 0xb8347211, 0x429538f0, 0x2eaaf31f, 0x80000001,
+    0x41b999d7, 0x48a8403c, 0xc8371133, 0x8a5f5977, 0x4135fc18, 0x5b45fbd2, 0x45af1397, 0x80000001,
+    0x001606da, 0x34766005, 0x94046029, 0x55245b19, 0x41af4f85, 0xe222954b, 0xd616709e, 0x80000000,
+    0xc0438ad9, 0x164aa00b, 0xec11b87e, 0x9b431151, 0x7533760d, 0x2c04644f, 0x13cacf3f, 0x80000001,
+    0x072dcdca, 0x501a407c, 0x38013806, 0xb8016e07, 0x6bdd8ed9, 0x0000000b, 0x00000000, 0x50000000,
+    0x004c10cf, 0x264ec00e, 0x64106081, 0xd9445154, 0x9fb3b50d, 0x35447c4f, 0x1d4eddef, 0x80000001,
+    0x00198ab9, 0x04cc8005, 0xd804702e, 0x0f25d120, 0x2c6f4705, 0xd1225ecb, 0xc8c65d7e, 0x80000000,
+    0xc0841461, 0xa70f4010, 0x7414e0a9, 0x66490960, 0x8533d90e, 0x27a4528f, 0x0ddac8f7, 0x80000001,
+    0x3849783e, 0xd8161a46, 0x9cf4f29a, 0x3f444efd, 0x18e70a14, 0x9d93dbac, 0xb161f8e5, 0x80000000,
+    0xda7eceb3, 0x3c01e971, 0x59c0f48d, 0x88adf7a7, 0xf477ba47, 0x289a4577, 0x66cb2d17, 0x80000001,
+    0xce53bb04, 0x695f43c3, 0xecd372c1, 0x66738f59, 0x0faf2e26, 0xa1961af1, 0x1bf2b82e, 0x80000001,
+    0xa52b61fa, 0x2ce86e08, 0x6e0d252a, 0xacc4dbc2, 0x38936ed5, 0x9301bdc5, 0x1ffc84f2, 0x80000000,
+    0x95cca4f0, 0xe6be6fdc, 0x25b05398, 0x487bce85, 0x8fae583d, 0x00070911, 0x00000000, 0x40000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x0734ad1d, 0x2a8b6120, 0x38834a32, 0x3971178e, 0x06b67321, 0x89e6aab3, 0x78b753e7, 0x80000001,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x80790afe, 0xa8204013, 0xe82378ec, 0x28591f72, 0x8df56e95, 0x48159d31, 0x3256f8d7, 0x80000001,
+    0xda4df507, 0xe012408c, 0x5801301a, 0x9801300f, 0xd4e9fb6e, 0x00000010, 0x00000000, 0x50000000,
+    0x80538c9d, 0xf7266009, 0x2811b894, 0xe443cd5d, 0xec735e0c, 0x4664114e, 0x2c96f19f, 0x80000001,
+    0x001a8740, 0x35e8c005, 0x8c087857, 0x3b2fe13c, 0xdaf04307, 0xf792accb, 0xe5f288d6, 0x80000000,
+    0x413c17e5, 0x28db401e, 0xd029091a, 0xfd59b377, 0x07750894, 0x58d54111, 0x422b0f67, 0x80000001,
+    0x3938f93e, 0x3a3cbaee, 0x953a5b84, 0x2f72ed4d, 0x98ad9b29, 0x28d61db0, 0xec1e5f9e, 0x80000000,
+    0x614d5905, 0x2c22ed0a, 0x75c3cc9a, 0xb0aaefa4, 0x86f707c4, 0x1149e457, 0x576718e7, 0x80000001,
+    0x9160c0d7, 0x69bd84f5, 0x40f23301, 0x3a789960, 0x4e2f5929, 0xc5364a91, 0x330ad9f6, 0x80000001,
+    0x29e5e7a7, 0x8d7df0fa, 0x7e58bda4, 0x63d2e5d1, 0x649694df, 0x3a518705, 0x331cc173, 0x80000000,
+    0x9f4f968a, 0x56c2ce94, 0x2db9a33c, 0x7e84c0f1, 0x00300027, 0x00040010, 0x00000000, 0x40000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x973f494e, 0x0ce72731, 0x1999b453, 0x6fa35dba, 0xe57a67bd, 0xac09e157, 0x9c27849f, 0x80000001,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x01020b2c, 0xc77e602e, 0x7c2548e1, 0x7a52a965, 0xb8748513, 0x502532b0, 0x2fd6f13f, 0x80000001,
+    0xf9657c59, 0xe06b61ee, 0xd0006012, 0xf101fe1d, 0x2ef1c7f5, 0x00000015, 0x00000000, 0x50000000,
+    0xc0640a19, 0xd6f4000d, 0x681678a0, 0x273fc554, 0x42f2698c, 0x24c3ae2e, 0x0e52c3d7, 0x80000001,
+    0x001003ef, 0x05b9e005, 0xa006f05a, 0x422f293b, 0xc4304606, 0xf102756b, 0xe0928306, 0x80000000,
+    0x42fc9f70, 0x49dae04d, 0xcc5781cf, 0x8471758f, 0xa7762fa0, 0x62764a72, 0x4aaf1bc7, 0x80000001,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x01a9961d, 0x372f0054, 0xa030e8f2, 0x74588d60, 0x63f6e617, 0x6c067a53, 0x3ca32777, 0x80000001,
+    0x9a063186, 0x08000f1e, 0x02000400, 0x00800100, 0x12de0740, 0x00026128, 0x00000000, 0x40000000,
+    0xc13116b0, 0xb6e78026, 0x1c1708ac, 0xb850ad60, 0xb6b55091, 0x35d57e91, 0xf4aeaf8f, 0x80000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x00e39b75, 0x578f0017, 0x841118a0, 0x383da54e, 0xa6726d8b, 0xf413d86e, 0xe5a68f66, 0x80000000,
+    0x00a413d0, 0x16380013, 0x100a5064, 0xe6594778, 0x8474f110, 0x00055bb1, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x03449586, 0xd01220f1, 0xc807803e, 0xc8020c14, 0xbc14ec55, 0x00000005, 0x00000000, 0x50000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x40e09b72, 0x46736018, 0xec09d064, 0xdd31e72e, 0x09ac4587, 0xc072f3cb, 0x5cdd99f5, 0x80000000,
+    0xc07b9318, 0x46b4400f, 0xb00b106e, 0xd0322f3b, 0x856fd987, 0x9d62ecac, 0xad5a35fe, 0x80000000,
+    0x32a971ed, 0x856d1618, 0xd050413c, 0xd125eab2, 0x421e2888, 0xb971d767, 0x693d63dc, 0x80000000,
+    0xd24241ef, 0x3a5ae573, 0x8d161354, 0x7c8c497e, 0x3d735032, 0xd5d7eb54, 0x2a4ed4d6, 0x80000001,
+    0x0a11318b, 0x18844249, 0x68830a0f, 0x1667e147, 0xd36c099f, 0x1f73e82d, 0xc27e3916, 0x80000000,
+    0x9df7d86c, 0x8bcf8a2f, 0x099a7c55, 0xe5a657a7, 0xeb10e63f, 0x2d30a4c2, 0x1264600a, 0x80000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0xc0869232, 0x75774018, 0xa4178872, 0xc93e1d38, 0xa1f3378f, 0x1bf4bfcf, 0xf8feb4df, 0x80000000,
+    0xd7a42fc8, 0x26a9abdb, 0x0200045f, 0x00800100, 0x5763cfc0, 0x0003d2cb, 0x00000000, 0x40000000,
+    0x006c11fd, 0x3535600a, 0x60098051, 0x41390132, 0xc131bc8a, 0xb873908d, 0xb8964b4e, 0x80000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0xc0cd9aa6, 0xc743c016, 0x88102090, 0x883b9549, 0xe0b2e00b, 0xf7a3ff0e, 0xe992937e, 0x80000000,
+    0x00449110, 0xf5350006, 0x2c05283c, 0x82306b2c, 0x9af0dd87, 0xcf72f9ac, 0xb43a4996, 0x80000000,
+    0xc06e8ecb, 0x16e0e00f, 0x6410888b, 0x9a43eb55, 0x3473708d, 0x11543e6f, 0xfc5ab907, 0x80000000,
+    0x43c31614, 0x801540c7, 0xf406002a, 0xf800d00a, 0xd594d0d4, 0x00000005, 0x00000000, 0x50000000,
+    0xc096970a, 0x16b3e012, 0xb80d2879, 0xc03b0b47, 0x67728c0a, 0xeee3cece, 0xd7427dae, 0x80000000,
+    0x00310c76, 0x94b12006, 0xb404d82f, 0x44200710, 0xec6dd704, 0x8001f249, 0x99220ebe, 0x80000000,
+    0x40489110, 0xc5aa8005, 0xf0060844, 0x322a092b, 0xbcafeb06, 0xc372a44b, 0xb97e48ce, 0x80000000,
+    0xb382f339, 0x7527d698, 0xc8531934, 0x832a30bb, 0xc11f010b, 0xc4120c67, 0x6d8d6724, 0x80000000,
+    0xd59646be, 0x8b27a70d, 0xe95e5be4, 0xc79a0992, 0xbe756aba, 0xd0c8a6d5, 0x34aae1b6, 0x80000001,
+    0x0a99b252, 0xd860e270, 0x9c939233, 0x95633f44, 0x296d2d9e, 0x2374712e, 0xd4e250be, 0x80000000,
+    0x5e47d8ca, 0xdbcea9f7, 0xcd84cc59, 0x6ca72ba7, 0x1e94fac4, 0x5c617dc5, 0x182c7132, 0x80000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x803a117d, 0x564ee005, 0x38062829, 0xe22e7d18, 0xefabdf0d, 0x62920009, 0x92a1e0c6, 0x80000000,
+    0xd23b29e7, 0x95f6cc77, 0xd98a7ae2, 0x0080010c, 0xaa257fc0, 0x0004ab4c, 0x00000000, 0x40000000,
+    0xc0520eed, 0xf37ce005, 0xe803d01d, 0x552000da, 0x1eac6f85, 0x532212a9, 0xa63622de, 0x80000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0xc1879a1f, 0x882e2024, 0x481ea8eb, 0xea46ed5b, 0x79f2da0d, 0x0b43f36e, 0xfabaa70f, 0x80000000,
+    0x4081a283, 0x96452007, 0x0404484f, 0x6334b346, 0x60b24708, 0x8922b18c, 0x822dca36, 0x80000000,
+    0x80578b13, 0x375f400c, 0xbc132898, 0x1347a15d, 0x2533ce8f, 0x07850f30, 0x05bebb5f, 0x80000001,
+    0xc4b11c7c, 0x100a2095, 0x1c027812, 0x1f010c11, 0xe419895c, 0x00000007, 0x00000000, 0x50000000,
+    0x80679127, 0x968b4007, 0xc408f063, 0x8a2bb32f, 0xb7efdf06, 0xda12bf2b, 0xcee66396, 0x80000000,
+    0x001f0692, 0x24d76005, 0x6405c836, 0x4523cd19, 0x24adde05, 0xa2f2288a, 0xaa522546, 0x80000000,
+    0x006511c0, 0xe6ac8006, 0x4008d865, 0x6130093c, 0x32f0e187, 0xe2a2df6c, 0xd74a6e9e, 0x80000000,
+    0x360af5ef, 0x450cb8c3, 0x3c4438ff, 0x452734b9, 0x74e1100a, 0xfec268c8, 0x801d8e1c, 0x80000000,
+    0xd9164cb8, 0x7beee8b0, 0x39a1ac60, 0x2faa41a0, 0x5e76db45, 0x1b89e357, 0x5a93187f, 0x80000001,
+    0x4d0ab813, 0x688fe33f, 0xd4a9425b, 0x38601139, 0x2b6b191d, 0x043491ee, 0xd39a3c06, 0x80000000,
+    0x9f37d818, 0x5bf16b0b, 0x95aabc88, 0x35a8c1a1, 0xc6d2c144, 0xa750dd43, 0x1f84885a, 0x80000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0xcf59182d, 0xc6550dcc, 0x9acb0b05, 0x6f14150b, 0x13e7e69f, 0x00062a8f, 0x00000000, 0x40000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x02959538, 0x09ef8068, 0x8083c20c, 0xd0727b88, 0xfef4f122, 0x1e564851, 0x0f8abd47, 0x80000001,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x402702ea, 0xb6edc005, 0x3c13708d, 0x29497150, 0x70b4f990, 0xc6f52e4f, 0xfc0e9a66, 0x80000000,
+    0x8727a72f, 0x2032c1e9, 0x000468ac, 0x26018423, 0x1d17b3d8, 0x00000007, 0x00000000, 0x50000000,
+    0x001d0583, 0xa57a0005, 0xf408404f, 0x9427c726, 0x6bae5285, 0xbba23e8a, 0xcf8a5dfe, 0x80000000,
+    0x000e0194, 0xd3df2005, 0xe006c835, 0x301f2af3, 0x6de7ae04, 0x7eb18bc8, 0xa0ce1f1e, 0x80000000,
+    0x004c071f, 0x76e0c008, 0x1c10188d, 0x053a114c, 0x0131738a, 0xe7e33b8d, 0xd8ea682e, 0x80000000,
+    0x750274ca, 0x06347831, 0xf48491c6, 0xdf4d4511, 0x82a6a399, 0x9ca434ac, 0xb195f7fd, 0x80000000,
+    0xd924cb3f, 0x0b312951, 0x415e23dd, 0x5498718e, 0x39f6cc38, 0xef78f156, 0x3d0f08b6, 0x80000001,
+    0xcc64b61b, 0xf8378326, 0xf49cb239, 0x7d5f3737, 0xbe6a5b1d, 0x0fd4960d, 0xd70e3ede, 0x80000000,
+    0x200c5b10, 0x4ca72bba, 0x8dbc1cd7, 0x66ad79a7, 0x1d8de445, 0x7d606d42, 0x1a30726a, 0x80000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20004000, 0x08001000, 0x02000400, 0x00800100, 0x00300040, 0x00040010, 0x00000000, 0x40000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x5555d555, 0x55557555, 0x55555d55, 0x00555755, 0x00200060, 0x00000008, 0x00000000, 0x50000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0xae8165cc, 0xa5317199, 0x47bf37b3, 0x00879db5, 0x00000000, 0x00000000, 0x00000000, 0x20000000,
+    0x515aab47, 0xe322076d, 0x347b2948, 0x14000028, 0x9421f3e5, 0x1215734e, 0x37b0bbfa, 0x10000000,
+    0xb4d9edf7, 0x195e17c0, 0x0000025a, 0x7c000000, 0x697cad7b, 0xfc5b78dc, 0x00000002, 0x10000000,
+    0x92b969ed, 0x230d478b, 0x3069812b, 0x6b00001d, 0x2793e734, 0x47c34ec8, 0x244074c9, 0x10000000,
+    0x3145e75d, 0x78035439, 0x00993a7e, 0xf7000000, 0x1f7b787a, 0x8b7c215c, 0x000108ec, 0x10000000,
+    0x02ed06cc, 0x9084e13c, 0xe0133834, 0x3e000005, 0xd292842c, 0x3ff32f47, 0x22747661, 0x10000000,
+    0xf675f270, 0xb9e7f8af, 0xf501437a, 0x8a000030, 0xce7c9efc, 0x32fbdd7c, 0x44854c94, 0x10000000,
+    0x22d5e919, 0xd5e88edc, 0x9cc6aa37, 0xa9000036, 0xc0cd9772, 0xdd925545, 0x11f84a30, 0x10000000,
+    0x321beb1c, 0x68399475, 0x08bb3a9a, 0x6b07e626, 0xd7774376, 0xfa6bb6f9, 0x3ae1320b, 0x1000098a,
+    0x18c639d3, 0xe44b4a4a, 0x28887195, 0x2a000025, 0x3902cf86, 0x3af08821, 0x06f81730, 0x10000000,
+    0x70bfe8d9, 0x18df7555, 0x610dcb41, 0xc40cb443, 0x00000002, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0xefb965d6, 0x684dd451, 0x59165312, 0x961ae453, 0x00016706, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x157d3389, 0xf17e6691, 0xdeaf8e37, 0x0023bcd2, 0x00000000, 0x00000000, 0x00000000, 0x20000000,
+    0xf2db96f9, 0xb77bd5e1, 0xc1419453, 0xabeace39, 0x00176dd1, 0x00080010, 0x00000000, 0x30000000,
+    0x909329ba, 0x1176c59f, 0x00000040, 0xed000000, 0x996ab7e1, 0x4742da4b, 0x00000000, 0x10000000,
+    0x3c020361, 0xa8dcd8a6, 0x0d0cc40c, 0x46ea3c1b, 0x0018a2d4, 0x00080010, 0x00000000, 0x30000000,
+    0x0dca216c, 0x5155a465, 0x0016785b, 0xea000000, 0x0be7d35d, 0xaaa315cd, 0x00000990, 0x10000000,
+    0xaf890102, 0x6434cf16, 0xd47c5a38, 0xc3e52009, 0x0013a94c, 0x00080010, 0x00000000, 0x30000000,
+    0xcd192107, 0xf14ca447, 0x9c1b3060, 0x33000006, 0x58a60f5c, 0x36a1364b, 0x00e00628, 0x10000000,
+    0xbbfc0449, 0x57c59487, 0x10fbab73, 0x36dba014, 0x3c8fc041, 0x0008d97e, 0x00000000, 0x30000000,
+    0x0ff5a5ba, 0x91e4457f, 0x803988a2, 0xf2054415, 0x699d81d8, 0x5b4247e7, 0x05b416d0, 0x10000092,
+    0x2f8784cd, 0x42600be8, 0x1c55b133, 0x00800005, 0x00200040, 0x00080010, 0x00000000, 0x30000000,
+    0x92fead9b, 0x727ec6dc, 0x1c5f60e5, 0x2c0f382a, 0x00000003, 0x00000000, 0x00000000, 0x00000000,
+    0x20004000, 0x03a11000, 0x020c0400, 0x806d0134, 0x2026c044, 0x0000000f, 0x00000000, 0x30000000,
+    0xd4332fa7, 0xb2e2a707, 0x48787926, 0x9117c833, 0x0000630b, 0x00000000, 0x00000000, 0x00000000,
+    0x9765b12f, 0x08000c36, 0x02000400, 0x00800100, 0x47dc3ac0, 0x00028c28, 0x00000000, 0x40000000,
+    0x00958cf1, 0xb7386025, 0x5c2b211a, 0x8062fd55, 0x72f8b099, 0x6ba6e3f4, 0x0a76d43f, 0x80000001,
+    0xc116110f, 0xf88ac04d, 0xb037e134, 0xf472616d, 0xfffb8aa0, 0xb348a2d7, 0x84df83e7, 0x80000001,
+    0x80fda026, 0x7952a017, 0xc81ee927, 0x115e7d79, 0xab74e594, 0x1b954071, 0x0a36cab7, 0x80000001,
+    0x409706a4, 0xc613e021, 0xb418e8c7, 0x1161c357, 0xd5ba8a96, 0x000785f5, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x4311281f, 0xa0222107, 0x300d7848, 0x6a061425, 0x345fd464, 0x0000000a, 0x00000000, 0x50000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x81b122b0, 0x96e98038, 0x2c1868c0, 0xbf3dd902, 0xec21358d, 0x24928b29, 0x5228fc2b, 0x80000000,
+    0x80af1883, 0x2801001b, 0x781530d6, 0xd64f0f5a, 0x3bb0080e, 0xa1b4222f, 0xd4f67356, 0x80000000,
+    0xf4177515, 0x27a0f6f8, 0x0cbe824e, 0x9c27c0bc, 0x1ce0b009, 0x27b20fc8, 0x781d8c1d, 0x80000000,
+    0x50fe3e2a, 0x9b0c84d1, 0xf92bdb9f, 0xa59a9596, 0x67b6e5b8, 0x1088d1d6, 0x3feb00df, 0x80000001,
+    0x4bcab5ad, 0x58cda29e, 0x88818233, 0x595dad4e, 0x59ea869c, 0xc364304e, 0xbdde2b95, 0x80000000,
+    0x9fe9dbb6, 0xac318a6e, 0x698f946f, 0xdf9f4d9a, 0xeb15a7bb, 0x88b13204, 0x178c7462, 0x80000000,
+    0x56dfb0f2, 0x1517ed4a, 0x02000314, 0x00800100, 0xc4dc4f40, 0x000261c7, 0x00000000, 0x40000000,
+    0x004d8734, 0x267bc00f, 0x8014a8a0, 0xa4448550, 0x7772c78d, 0xed23c6ae, 0xd3ca758e, 0x80000000,
+    0x408f8a27, 0x17988024, 0x2425f0d8, 0xfe598365, 0xffb73c96, 0x5f660d92, 0x369f0d27, 0x80000001,
+    0x40db1bba, 0x785a2013, 0xa81830dd, 0x1a4a1165, 0x5033768e, 0x0ed41e0f, 0xf5c6a82f, 0x80000000,
+    0x8046886f, 0xa68ac00b, 0x9c0f0888, 0x1f477b5c, 0xc6f36a8d, 0xddb3dfce, 0xc5da6266, 0x80000000,
+    0xc092111f, 0x3886c017, 0x5c19f0eb, 0x5e572374, 0xc3745111, 0x1dc4dfd0, 0x03e2bf2f, 0x80000001,
+    0x435eac2f, 0x7023a0cc, 0x3c067026, 0xb6045214, 0x609ee661, 0x0000000a, 0x00000000, 0x50000000,
+    0x40981570, 0x88612019, 0xf417e0e1, 0xbc531371, 0xc233d40f, 0x0314458f, 0xebe29c7f, 0x80000000,
+    0x80450ddc, 0xc667c00c, 0x18099060, 0x95327134, 0x9eadfa07, 0x7fe2968b, 0xa8b6269e, 0x80000000,
+    0xc0569456, 0x476b200a, 0xf40b8888, 0x9b3df556, 0xc0b21609, 0xe813588d, 0xd1d27386, 0x80000000,
+    0xb48e74cd, 0xd7a3978c, 0x50d05a57, 0x3c2956c1, 0xf2dfa18a, 0xe3321687, 0x6ed97494, 0x80000000,
+    0x52c9c34f, 0xcb62e5a1, 0x5155ebe9, 0x939e5d97, 0x5db6423c, 0xf7491156, 0x460b016e, 0x80000001,
+    0xcac0b3e7, 0x1873c277, 0x0090ba3b, 0xa35f013e, 0x696bf59b, 0x0b04a46e, 0xccba360e, 0x80000000,
+    0x9d155807, 0xcbd669b7, 0xd583ac41, 0x81a5219d, 0x1c580740, 0x5ed1b346, 0x18a47052, 0x80000000,
+    0x97e8b21b, 0xa5052b08, 0x55457339, 0x008000c2, 0xd2de93c0, 0x0002c6e8, 0x00000000, 0x40000000,
+    0x80290460, 0xa5c4c006, 0xf00d7868, 0x1d373d3d, 0x2231bc0a, 0xef232f0d, 0xd94280de, 0x80000000,
+    0xc07207c1, 0x876f8014, 0x402260ca, 0x61584961, 0xebf6c617, 0x57263552, 0x334b0097, 0x80000001,
+    0xc1b3223f, 0x98e7e023, 0xbc29292c, 0x865d5d7e, 0xabf5b115, 0x45957f51, 0x24a6ebaf, 0x80000001,
+    0x001684a3, 0xe5906005, 0xe0079849, 0x5b2fff38, 0x27b17c87, 0xdac2d74c, 0xc5c65fae, 0x80000000,
+    0x40430a12, 0x6774e007, 0x2c0f909b, 0x9e469f60, 0x31739c0c, 0x0f74110f, 0xf4b2a25f, 0x80000000,
+    0x4440b1f4, 0xb0156089, 0x1401f00b, 0x3c03c20f, 0xc4defde1, 0x0000000a, 0x00000000, 0x50000000,
+    0x805c9066, 0xf771e00a, 0x5c1090a2, 0x3e47e761, 0x10f3648d, 0x0bd410af, 0xf602a6f7, 0x80000000,
+    0x001a881f, 0x057ac005, 0x5404f03a, 0x1d28872c, 0xc0ee9805, 0xa5422d6a, 0xa78a28c6, 0x80000000,
+    0x00611290, 0xe7782009, 0x400e9899, 0xe0440360, 0x77b31b0b, 0x05e3c48e, 0xea8695ff, 0x80000000,
+    0xb71bf731, 0x871a1960, 0x98b29a0c, 0x522f54d2, 0x8c62d40c, 0x41a2ba09, 0x8cb9afcd, 0x80000000,
+    0x163148c5, 0x6bd30725, 0x45960456, 0xeea921a4, 0x96374cc3, 0x273a0477, 0x5dbb2817, 0x80000001,
+    0x4bbb357d, 0x78ab42ce, 0x78a5fa5b, 0x5064df45, 0x202c951f, 0x40151ecf, 0xeaa26546, 0x80000000,
+    0x217fddae, 0x4c6d6be5, 0x4dcd6cc5, 0x4bb5b1b0, 0x7093c8cb, 0x55013fc4, 0x16d46b6a, 0x80000000,
+    0x54552c3e, 0x7617adee, 0x19669321, 0xc46870b5, 0xa7e83f56, 0x0004f10d, 0x00000000, 0x40000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x02fd27ac, 0x696e004e, 0xfc34895e, 0x78634582, 0x39f5e818, 0x5b85dc92, 0x3e7f0d2f, 0x80000001,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x40638a4a, 0x285d4009, 0x0819b8d1, 0xc6552f71, 0xa674f891, 0x2b64ed90, 0x0e2ecea7, 0x80000001,
+    0x04809fb9, 0xc0092059, 0x6c018012, 0x9801ea17, 0xb2e41068, 0x0000000c, 0x00000000, 0x50000000,
+    0x405b108e, 0x67a1a008, 0xa00ee09a, 0x0b443360, 0xbdb3768c, 0x2283e5ce, 0x08c2c07f, 0x80000001,
+    0x0015059b, 0x15eec005, 0x6c070050, 0x002b5f36, 0xc6af2806, 0xc1023eaa, 0xbbd2448e, 0x80000000,
+    0xc0d41666, 0x9842c00e, 0xa81818d1, 0x574e116b, 0x90b3fc8f, 0x27b44bef, 0x0a5ac64f, 0x80000001,
+    0xb703f74c, 0xb8083918, 0xb88c41f6, 0xe04a270a, 0x1c272515, 0x9483c52c, 0xa8a1ec4d, 0x80000000,
+    0x9987ce33, 0xfbcf88c0, 0x9d843443, 0x61a4379f, 0xd4768e3f, 0x11396f16, 0x4a8f0f0f, 0x80000001,
+    0xce823be0, 0xe922a3ba, 0xa0c29a9f, 0xa66c534f, 0x0aad9ea2, 0x77a58990, 0x06e295e6, 0x80000001,
+    0x643a6130, 0x4cb0ed45, 0xd1ec3500, 0x24bce5b9, 0xc61297d0, 0xdc60e3a3, 0x234097e2, 0x80000000,
+    0xd4d71a30, 0x55fa6cd8, 0xbdf8b3b4, 0x676ba6bf, 0x00300043, 0x00040010, 0x00000000, 0x40000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x8b43ba60, 0x4b0482a5, 0x108bea6f, 0x938383a1, 0x51f87a29, 0x7347ca15, 0x61b73a67, 0x80000001,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x8061087e, 0x07c7800c, 0xb01c68c9, 0x3c4fe56a, 0xaaf3af91, 0x2d04818f, 0x12c2cacf, 0x80000001,
+    0x4f37cfba, 0x602fe167, 0xd4006008, 0xd701b824, 0xafaad0ef, 0x00000010, 0x00000000, 0x50000000,
+    0xc04b8d39, 0x76c6a005, 0x600b787a, 0x21355549, 0xfcf16a08, 0x0bb2fcac, 0xf6329d17, 0x80000000,
+    0x001004b4, 0x55cac005, 0xe4054048, 0xcf283731, 0x7ceee004, 0xc291ff8a, 0xb95a471e, 0x80000000,
+    0x81781b10, 0x489f601a, 0x5c26a919, 0x4c52536d, 0xb8341f11, 0x30a4892f, 0x1a9ed96f, 0x80000001,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x015292b2, 0x46b3602e, 0x8c18e0b5, 0xe4520d5d, 0x9ff44d12, 0x90058092, 0x14032807, 0x80000001,
+    0x9744ac58, 0x08000923, 0x02000400, 0x00800100, 0xb41627c0, 0x00012984, 0x00000000, 0x40000000,
+    0x808591da, 0xf57c400c, 0x6c06384d, 0xbf3aff52, 0x3b34ec8a, 0xdb733b31, 0xdb6e492e, 0x80000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x0098164f, 0x4806a00b, 0xc40e589c, 0xe845035e, 0xf033e98b, 0x1fb43acf, 0xda22abe7, 0x80000000,
+    0xc05e0ff0, 0x14fa0006, 0xf403582b, 0x4c530759, 0x496db711, 0x00024932, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x8250131b, 0x50050095, 0x94028026, 0x98008408, 0xd014d55b, 0x00000004, 0x00000000, 0x50000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x00479268, 0x55122005, 0x1c03182b, 0xfb2c4d0f, 0x20dc9883, 0xaab2b946, 0xaaae0006, 0x80000000,
+    0x00480e9e, 0xd69cc005, 0xb005a84e, 0x1d2daf39, 0xed323b86, 0x1d1281ac, 0x94b2165e, 0x80000000,
+    0x72c471a1, 0x04a0545f, 0xcc2288a3, 0xa4167082, 0x821a6983, 0xc6e10fe5, 0x6371947c, 0x80000000,
+    0x8d893972, 0x7a2983a5, 0x68f8c325, 0x0c8ad187, 0x02b4dd2e, 0xcde81e35, 0xf882e406, 0x80000000,
+    0x486a25dd, 0x68f8016f, 0x0c497a39, 0x5b456d27, 0x99a33311, 0xaab26669, 0x55560006, 0x80000000,
+    0xda4fd2c6, 0xfc0ee89a, 0xad6434c0, 0xdfaaabaa, 0x31ca8cb2, 0xeb806842, 0x0cf04189, 0x80000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x80fb8f5a, 0x26616026, 0xc81a80a0, 0xe350ed50, 0x27f59c12, 0xc474c0d2, 0xe9766d7e, 0x80000000,
+    0x57d8b163, 0xb51d0acd, 0x020003c4, 0x00800100, 0xfd9d9840, 0x00024607, 0x00000000, 0x40000000,
+    0x809494a4, 0xa5b58008, 0x7406784d, 0x15328339, 0xc9b00b86, 0x863238aa, 0x5979a196, 0x80000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x40b517ad, 0x77b3200e, 0x2c0f1098, 0xb23bbb4d, 0x9d337a89, 0x56f37fed, 0xc3a27ab6, 0x80000000,
+    0xc0621397, 0xa5d40005, 0xf8039837, 0x462a4930, 0xff30ed04, 0x3d716bca, 0x70a5c296, 0x80000000,
+    0x40578dbc, 0x47aa0009, 0x8c0ed090, 0x4b436359, 0xebb33c0d, 0xcbf44a2e, 0xc62e6476, 0x80000000,
+    0x0328945a, 0xf01000bb, 0x38060829, 0x4e006208, 0x661868de, 0x00000006, 0x00000000, 0x50000000,
+    0x407d1217, 0x0720a00d, 0x4c0b487c, 0x0539494d, 0xe6b1d609, 0xfe23380d, 0xb83a5ebe, 0x80000000,
+    0x00150646, 0x24c2e005, 0xcc021822, 0xd21b9f0b, 0xe8edaa82, 0x4f619b09, 0x7939d986, 0x80000000,
+    0x002b0b22, 0x55eae005, 0xc404b040, 0xa3270736, 0xc2709404, 0xb742358a, 0x8dba2f56, 0x80000000,
+    0xb1727333, 0x94ca94bf, 0xf03fb107, 0x0f1dee9c, 0x4b1bee87, 0xc4e18e86, 0x6f3d78bc, 0x80000000,
+    0x527ec23f, 0x6abe257b, 0x45187b63, 0x4f90a387, 0x5ab407b6, 0xe7e7c1d4, 0x17ced0c6, 0x80000001,
+    0x4babae97, 0xc8d66317, 0xe880320d, 0xc547af4e, 0x95ae9311, 0xf934d4f1, 0xbf2658c5, 0x80000000,
+    0xdda45453, 0xabf3aa0b, 0xc1000384, 0x78a32f89, 0xadcf4645, 0xbb60caa3, 0x09a44329, 0x80000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0xc0f59478, 0xd7b82015, 0x28150063, 0xc647af5c, 0x00300012, 0xd174aab0, 0xba31d17d, 0x80000000,
+    0x4f292720, 0x45770a71, 0xd55a33ab, 0x008000d3, 0xcba11a40, 0x00031109, 0x00000000, 0x40000000,
+    0x417f13bd, 0xd8a3e026, 0x002220cc, 0x00400150, 0xb6fb6d90, 0x38e4924d, 0x71c9c726, 0x80000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x80f797e6, 0x7801a010, 0x441208af, 0x4343dd53, 0xcb328a0c, 0xc723990d, 0xd36267fe, 0x80000000,
+    0xc115907d, 0x35d9801b, 0x101088bb, 0xd4584796, 0x74745d08, 0x00045d31, 0x5555555c, 0x80000000,
+    0x00760a63, 0xa7d2a00c, 0xa81020a2, 0x00481561, 0x3434b08e, 0xef647f90, 0xf1f2ba96, 0x80000000,
+    0x446a9897, 0xc005a054, 0x7004e823, 0x6701e012, 0x785c1fe1, 0x00000008, 0x00000000, 0x50000000,
+    0x00470ccc, 0x66494005, 0xc8079855, 0x6b2c8335, 0x482fb307, 0x65429e6b, 0x8b35ea0e, 0x80000000,
+    0x001082dd, 0x24ca6005, 0xf004b03a, 0xe420c919, 0x906bc203, 0x4a4191e8, 0x6f25bffe, 0x80000000,
+    0x00330b76, 0x9670e005, 0x8c063059, 0x6e30e740, 0xb7306486, 0x9d32782b, 0x97b60ed6, 0x80000000,
+    0x72057290, 0x54293654, 0x683040e8, 0x5f24cca6, 0xd01fc709, 0xd8822367, 0x679d6a4c, 0x80000000,
+    0x1735cb26, 0x6be6a760, 0x4980e435, 0x049fbf99, 0xd3758bc0, 0xdfb8e315, 0x3e8ef816, 0x80000001,
+    0x486da860, 0x06b241de, 0x2063a1bb, 0x334c091f, 0x8b679892, 0xf662fccb, 0x666984d4, 0x80000000,
+    0x1ba2d616, 0x9b06a73e, 0x8937cc06, 0x918db36e, 0x288f3b29, 0xf1f058e2, 0x10b85851, 0x80000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x0f459fb8, 0xb453ebc7, 0xc6d552fe, 0xcb12c76c, 0x6764b1b4, 0x0004a8cc, 0x00000000, 0x40000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x40f48fa9, 0x0914a018, 0xc425792d, 0x2b4d0b67, 0x88b2948e, 0xca03db8e, 0xd2366506, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x001f042f, 0xf7478005, 0x880d9883, 0xb33e293c, 0x5333ee0d, 0xc4f3edcd, 0xe76658a6, 0x80000000,
+    0x027790be, 0xc008609a, 0xa4055040, 0x3a00700f, 0x0fd6cf54, 0x00000006, 0x00000000, 0x50000000,
+    0x001a04c0, 0x754d8005, 0xe804883e, 0xb323af1d, 0x8ead7584, 0x53620809, 0x86dde546, 0x80000000,
+    0x000800e1, 0xf4244003, 0xa8033029, 0xe81bbf06, 0x55ac1082, 0x4ef15f48, 0x6f31c3fe, 0x80000000,
+    0x0035869b, 0x56870005, 0xc007e862, 0xc02e2d38, 0x6bafa706, 0xaaf20a2a, 0xa39a1f9e, 0x80000000,
+    0x719af114, 0x35b4d61e, 0xc860a96d, 0x68205ab3, 0x2a9c1406, 0x5ea12366, 0x58a13414, 0x80000000,
+    0x51f23de6, 0x1aa065d8, 0x8d02cb5a, 0xaa90ed8c, 0xc3f51132, 0x83679954, 0x0b56a19e, 0x80000001,
+    0xc6d82b5c, 0x87112115, 0xc454316a, 0x7f4134ff, 0x83a3fa8d, 0xfae24709, 0x818d9514, 0x80000000,
+    0x19f24eb4, 0x7b76c7ad, 0xd13773f5, 0xdc906197, 0xac49e431, 0xf7b06661, 0x0f505731, 0x80000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20004000, 0x08001000, 0x02000400, 0x00800100, 0x00300040, 0x00040010, 0x00000000, 0x40000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x5555d555, 0x55557555, 0x55555d55, 0x00555755, 0x00200060, 0x00000008, 0x00000000, 0x50000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+    0x20006000, 0x0c000800, 0x01000400, 0x00800180, 0x00300020, 0x00040010, 0x80020006, 0x80000000,
+};
+
+
+static RK_U32 rkv_ver_align(RK_U32 val)
+{
+    return MPP_ALIGN(val, 8);
+}
+
+static RK_U32 rkv_len_align(RK_U32 val)
+{
+    return (2 * MPP_ALIGN(val, 128));
+}
+
+static RK_U32 rkv_len_align_422(RK_U32 val)
+{
+    return ((5 * MPP_ALIGN(val, 64)) / 2);
+}
+
+static MPP_RET vdpu383_setup_scale_origin_bufs(Av1dHalCtx *p_hal, MppFrame mframe)
+{
+    Vdpu383Av1dRegCtx *ctx = (Vdpu383Av1dRegCtx *)p_hal->reg_ctx;
+    /* for 8K FrameBuf scale mode */
+    size_t origin_buf_size = 0;
+
+    origin_buf_size = mpp_frame_get_buf_size(mframe);
+
+    if (!origin_buf_size) {
+        mpp_err_f("origin_bufs get buf size failed\n");
+        return MPP_NOK;
+    }
+    if (ctx->origin_bufs) {
+        hal_bufs_deinit(ctx->origin_bufs);
+        ctx->origin_bufs = NULL;
+    }
+    hal_bufs_init(&ctx->origin_bufs);
+    if (!ctx->origin_bufs) {
+        mpp_err_f("origin_bufs init fail\n");
+        return MPP_ERR_NOMEM;
+    }
+    hal_bufs_setup(ctx->origin_bufs, 16, 1, &origin_buf_size);
+
+    return MPP_OK;
+}
+
+
+static MPP_RET hal_av1d_alloc_res(void *hal)
+{
+    MPP_RET ret = MPP_OK;
+    Av1dHalCtx *p_hal = (Av1dHalCtx *)hal;
+    RK_U32 max_cnt = p_hal->fast_mode ? VDPU_FAST_REG_SET_CNT : 1;
+    RK_U32 i = 0;
+    void *cdf_ptr;
+    INP_CHECK(ret, NULL == p_hal);
+
+    MEM_CHECK(ret, p_hal->reg_ctx = mpp_calloc_size(void, sizeof(Vdpu383Av1dRegCtx)));
+    Vdpu383Av1dRegCtx *reg_ctx = (Vdpu383Av1dRegCtx *)p_hal->reg_ctx;
+
+    //!< malloc buffers
+    BUF_CHECK(ret, mpp_buffer_get(p_hal->buf_group, &reg_ctx->bufs, MPP_ALIGN(VDPU383_INFO_BUF_SIZE(max_cnt), SZ_2K)));
+    mpp_buffer_attach_dev(reg_ctx->bufs, p_hal->dev);
+    reg_ctx->bufs_fd = mpp_buffer_get_fd(reg_ctx->bufs);
+    reg_ctx->bufs_ptr = mpp_buffer_get_ptr(reg_ctx->bufs);
+
+
+    for (i = 0; i < max_cnt; i++) {
+        reg_ctx->reg_buf[i].regs = mpp_calloc(Vdpu383Av1dRegSet, 1);
+        memset(reg_ctx->reg_buf[i].regs, 0, sizeof(Vdpu383Av1dRegSet));
+        reg_ctx->uncmps_offset[i] = VDPU383_UNCMPS_HEADER_OFFSET(i);
+    }
+
+    if (!p_hal->fast_mode) {
+        reg_ctx->regs = reg_ctx->reg_buf[0].regs;
+        reg_ctx->offset_uncomps = reg_ctx->uncmps_offset[0];
+    }
+
+    BUF_CHECK(ret, mpp_buffer_get(p_hal->buf_group, &reg_ctx->cdf_rd_def_base, 200 * MPP_ALIGN(sizeof(g_default_prob), 2048)));
+    mpp_buffer_attach_dev(reg_ctx->cdf_rd_def_base, p_hal->dev);
+    cdf_ptr = mpp_buffer_get_ptr(reg_ctx->cdf_rd_def_base);
+    memcpy(cdf_ptr, g_default_prob, sizeof(g_default_prob));
+    mpp_buffer_sync_end(reg_ctx->cdf_rd_def_base);
+
+__RETURN:
+    return ret;
+__FAILED:
+    return ret;
+}
+
+static void vdpu_av1d_filtermem_release(Vdpu383Av1dRegCtx *ctx)
+{
+    BUF_PUT(ctx->filter_mem);
+}
+
+static void hal_av1d_release_res(void *hal)
+{
+    Av1dHalCtx *p_hal = (Av1dHalCtx *)hal;
+    Vdpu383Av1dRegCtx *reg_ctx = (Vdpu383Av1dRegCtx *)p_hal->reg_ctx;
+    RK_U32 i = 0;
+    RK_U32 max_cnt = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1;
+
+    for (i = 0; i < max_cnt; i++)
+        MPP_FREE(reg_ctx->reg_buf[i].regs);
+
+    BUF_PUT(reg_ctx->cdf_rd_def_base);
+    BUF_PUT(reg_ctx->bufs);
+    for (i = 0; i < max_cnt; i++)
+        BUF_PUT(reg_ctx->rcb_bufs[i]);
+
+    vdpu_av1d_filtermem_release(reg_ctx);
+    if (reg_ctx->cdf_bufs) {
+        hal_bufs_deinit(reg_ctx->cdf_bufs);
+        reg_ctx->cdf_bufs = NULL;
+    }
+    if (reg_ctx->colmv_bufs) {
+        hal_bufs_deinit(reg_ctx->colmv_bufs);
+        reg_ctx->colmv_bufs = NULL;
+    }
+    if (reg_ctx->origin_bufs) {
+        hal_bufs_deinit(reg_ctx->origin_bufs);
+        reg_ctx->origin_bufs = NULL;
+    }
+
+    MPP_FREE(p_hal->reg_ctx);
+}
+
+MPP_RET vdpu383_av1d_deinit(void *hal)
+{
+    hal_av1d_release_res(hal);
+
+    return MPP_OK;
+}
+
+MPP_RET vdpu383_av1d_init(void *hal, MppHalCfg *cfg)
+{
+    MPP_RET ret = MPP_OK;
+    Av1dHalCtx *p_hal = (Av1dHalCtx *)hal;
+    INP_CHECK(ret, NULL == p_hal);
+    (void) cfg;
+
+    FUN_CHECK(hal_av1d_alloc_res(hal));
+
+    mpp_slots_set_prop(p_hal->slots, SLOTS_HOR_ALIGN, mpp_align_128_odd_plus_64);
+    mpp_slots_set_prop(p_hal->slots, SLOTS_VER_ALIGN, rkv_ver_align);
+    mpp_slots_set_prop(p_hal->slots, SLOTS_LEN_ALIGN, rkv_len_align);
+
+__RETURN:
+    return MPP_OK;
+__FAILED:
+    vdpu383_av1d_deinit(hal);
+
+    return ret;
+}
+
+#define MAX_FRAME_DISTANCE 31
+#define MAX_ACTIVE_REFS AV1_ACTIVE_REFS_EX
+
+static RK_S32 GetRelativeDist(DXVA_PicParams_AV1 *dxva, RK_S32 a, RK_S32 b)
+{
+    if (!dxva->order_hint_bits) return 0;
+    const RK_S32 bits = dxva->order_hint_bits - 1;
+
+    RK_S32 diff = a - b;
+    RK_S32 m = 1 << bits;
+    diff = (diff & (m - 1)) - (diff & m);
+    return diff;
+}
+
+#undef MAX_FRAME_DISTANCE
+
+static RK_U32 mpp_clip_uintp2(RK_S32 a, RK_S32 p)
+{
+    if (a & ~((1 << p) - 1)) return -a >> 31 & ((1 << p) - 1);
+    else                   return  a;
+}
+
+static MPP_RET prepare_uncompress_header(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva,
+                                         RK_U64 *data, RK_U32 len)
+{
+    BitputCtx_t bp;
+    RK_S32 i, j;
+    (void) p_hal;
+
+    mpp_set_bitput_ctx(&bp, data, len);
+
+    /* sequence header */
+    mpp_put_bits(&bp, dxva->coding.current_operating_point, 12);
+    mpp_put_bits(&bp, dxva->coding.use_128x128_superblock, 1);
+    mpp_put_bits(&bp, dxva->coding.filter_intra, 1);
+    mpp_put_bits(&bp, dxva->coding.intra_edge_filter, 1);
+    mpp_put_bits(&bp, dxva->coding.interintra_compound, 1);
+    mpp_put_bits(&bp, dxva->coding.masked_compound, 1);
+    mpp_put_bits(&bp, dxva->coding.dual_filter, 1);
+    mpp_put_bits(&bp, dxva->enable_order_hint, 1);
+    mpp_put_bits(&bp, dxva->coding.jnt_comp, 1);
+    mpp_put_bits(&bp, dxva->coding.enable_ref_frame_mvs, 1);
+    {
+        RK_S32 order_hint_bits_minus_1 = dxva->order_hint_bits ? (dxva->order_hint_bits - 1) : 0;
+
+        mpp_put_bits(&bp, order_hint_bits_minus_1, 3);
+    }
+    {
+        RK_U32 skip_loop_filter = 0; // TODO: control by user
+        RK_U32 enable_cdef = !skip_loop_filter && !dxva->coded_lossless;
+        RK_U32 enable_cdef_y = dxva->cdef.y_strengths[0].primary || dxva->cdef.y_strengths[0].secondary;
+        RK_U32 enable_cdef_uv = dxva->cdef.uv_strengths[0].primary || dxva->cdef.uv_strengths[0].secondary;
+
+        enable_cdef = enable_cdef && (dxva->cdef.bits || enable_cdef_y || enable_cdef_uv);
+        mpp_put_bits(&bp, enable_cdef, 1);
+    }
+    mpp_put_bits(&bp, (dxva->bitdepth > 8) ? (dxva->bitdepth - 8) : 0, 3);
+    {
+        RK_U32 yuv_format = 0;
+
+        if (dxva->format.mono_chrome)
+            yuv_format = 0;  // 400
+        else if (dxva->format.subsampling_y == 1 && dxva->format.subsampling_y == 1)
+            yuv_format = 1;  // 420
+        else if (dxva->format.subsampling_x == 1)
+            yuv_format = 2;  // 422
+        else
+            yuv_format = 3;  // 444
+
+        mpp_put_bits(&bp, yuv_format, 2);
+    }
+
+    mpp_put_bits(&bp, dxva->film_grain.matrix_coefficients, 8);
+    mpp_put_bits(&bp, dxva->coding.film_grain_en, 1);
+
+    /* frame uncompresss header */
+    {
+        RK_U32 frame_is_intra = dxva->format.frame_type == KEY_FRAME ||
+                                dxva->format.frame_type == INTRA_ONLY_FRAME;
+
+        mpp_put_bits(&bp, frame_is_intra, 1);
+        mpp_put_bits(&bp, dxva->coding.disable_cdf_update, 1);
+        mpp_put_bits(&bp, dxva->coding.screen_content_tools, 1);
+        mpp_put_bits(&bp, dxva->coding.integer_mv || frame_is_intra, 1);
+        mpp_put_bits(&bp, dxva->order_hint, 8);
+        mpp_put_bits(&bp, dxva->width, 16);
+        mpp_put_bits(&bp, dxva->height, 16);
+        mpp_put_bits(&bp, dxva->coding.superres, 1);
+        mpp_put_bits(&bp, dxva->superres_denom, 5);
+        mpp_put_bits(&bp, dxva->upscaled_width, 16);
+        mpp_put_bits(&bp, dxva->coding.high_precision_mv, 1);
+        mpp_put_bits(&bp, dxva->coding.intrabc, 1);
+    }
+
+    for (i = 0; i < ALLOWED_REFS_PER_FRAME_EX; i++)
+        mpp_put_bits(&bp, dxva->ref_frame_valued ? dxva->ref_frame_idx[i] : (RK_U32) - 1, 3);
+
+    mpp_put_bits(&bp, dxva->interp_filter, 3);
+    mpp_put_bits(&bp, dxva->coding.switchable_motion_mode, 1);
+    mpp_put_bits(&bp, dxva->coding.use_ref_frame_mvs, 1);
+
+    {
+        RK_U32 mapped_idx = 0;
+
+        for (i = 0; i < NUM_REF_FRAMES; i++) {
+            mpp_put_bits(&bp, dxva->frame_refs[i].order_hint, 8);
+        }
+        for (i = 0; i < ALLOWED_REFS_PER_FRAME_EX; i++) {
+            mapped_idx = dxva->ref_frame_idx[i];
+            mpp_put_bits(&bp, dxva->ref_order_hint[mapped_idx], 8);
+        }
+    }
+
+    for (i = 0; i < ALLOWED_REFS_PER_FRAME_EX; ++i) {
+        if (!dxva->order_hint_bits) {
+            dxva->ref_frame_sign_bias[i] = 0;
+        } else {
+            if (dxva->frame_refs[i].Index >= 0) {
+                RK_S32 ref_frame_offset = dxva->frame_refs[dxva->ref_frame_idx[i]].order_hint;
+                RK_S32 rel_off = GetRelativeDist(dxva, ref_frame_offset, dxva->order_hint);
+
+                dxva->ref_frame_sign_bias[i] = (rel_off <= 0) ? 0 : 1;
+            }
+        }
+        mpp_put_bits(&bp, dxva->ref_frame_sign_bias[i], 1);
+    }
+
+    mpp_put_bits(&bp, dxva->coding.disable_frame_end_update_cdf, 1);
+
+    /* quantization params */
+    mpp_put_bits(&bp, dxva->quantization.base_qindex, 8);
+    mpp_put_bits(&bp, dxva->quantization.y_dc_delta_q, 7);
+    mpp_put_bits(&bp, dxva->quantization.u_dc_delta_q, 7);
+    mpp_put_bits(&bp, dxva->quantization.u_ac_delta_q, 7);
+    mpp_put_bits(&bp, dxva->quantization.v_dc_delta_q, 7);
+    mpp_put_bits(&bp, dxva->quantization.v_ac_delta_q, 7);
+    mpp_put_bits(&bp, dxva->quantization.using_qmatrix, 1);
+
+    /* segmentation params */
+    mpp_put_bits(&bp, dxva->segmentation.enabled, 1);
+    mpp_put_bits(&bp, dxva->segmentation.update_map, 1);
+    mpp_put_bits(&bp, dxva->segmentation.temporal_update, 1);
+
+    {
+        RK_U32 mi_rows = MPP_ALIGN(dxva->width, 8) >> MI_SIZE_LOG2;
+        RK_U32 mi_cols = MPP_ALIGN(dxva->height, 8) >> MI_SIZE_LOG2;
+        /* index 0: AV1_REF_FRAME_LAST - AV1_REF_FRAME_LAST */
+        RK_U32 prev_mi_rows = MPP_ALIGN(dxva->frame_refs[0].width, 8) >> MI_SIZE_LOG2;
+        RK_U32 prev_mi_cols = MPP_ALIGN(dxva->frame_refs[0].height, 8) >> MI_SIZE_LOG2;
+        RK_U32 use_prev_segmentation_ids  = dxva->segmentation.enabled && dxva->primary_ref_frame &&
+                                            (mi_rows == prev_mi_rows) &&
+                                            (mi_cols == prev_mi_cols);
+
+        mpp_put_bits(&bp, use_prev_segmentation_ids, 1);
+    }
+
+    /* Segmentation data update */
+    for (i = 0; i < MAX_SEGMENTS; i++)
+        mpp_put_bits(&bp, dxva->segmentation.feature_mask[i], 8);
+
+    for (i = 0; i < MAX_SEGMENTS; i++) {
+        mpp_put_bits(&bp, dxva->segmentation.feature_data[i][0], 9);
+        mpp_put_bits(&bp, dxva->segmentation.feature_data[i][1], 7);
+        mpp_put_bits(&bp, dxva->segmentation.feature_data[i][2], 7);
+        mpp_put_bits(&bp, dxva->segmentation.feature_data[i][3], 7);
+        mpp_put_bits(&bp, dxva->segmentation.feature_data[i][4], 7);
+        mpp_put_bits(&bp, dxva->segmentation.feature_data[i][5], 3);
+    }
+    mpp_put_bits(&bp, dxva->segmentation.last_active, 3);
+    mpp_put_bits(&bp, dxva->segmentation.preskip, 1);
+    mpp_put_bits(&bp, dxva->quantization.delta_q_present, 1);
+    if (dxva->quantization.delta_q_present)
+        mpp_put_bits(&bp, dxva->quantization.delta_q_res, 2);
+    else
+        mpp_put_bits(&bp, 1 << dxva->quantization.delta_q_res, 2);
+
+    /* delta lf params */
+    mpp_put_bits(&bp, dxva->loop_filter.delta_lf_present, 1);
+    mpp_put_bits(&bp, 1 << dxva->loop_filter.delta_lf_res, 2);
+    mpp_put_bits(&bp, dxva->loop_filter.delta_lf_multi, 1);
+    mpp_put_bits(&bp, dxva->coded_lossless, 1);
+    for (i = 0; i < MAX_SEGMENTS; ++i) {
+        RK_S32 qindex, lossless;
+
+        if (dxva->segmentation.feature_mask[i] & 0x1) {
+            qindex = (dxva->quantization.base_qindex + dxva->segmentation.feature_data[i][SEG_LVL_ALT_Q]);
+        } else {
+            qindex = dxva->quantization.base_qindex;
+        }
+        qindex = mpp_clip_uintp2(qindex, 8);
+        lossless = qindex == 0 && dxva->quantization.y_dc_delta_q == 0 &&
+                   dxva->quantization.u_dc_delta_q == 0 &&
+                   dxva->quantization.v_dc_delta_q == 0 &&
+                   dxva->quantization.u_ac_delta_q == 0 &&
+                   dxva->quantization.v_ac_delta_q == 0;
+
+        mpp_put_bits(&bp, lossless, 1);
+    }
+    mpp_put_bits(&bp, dxva->all_lossless, 1);
+
+    /* segmentation dequant */
+    mpp_put_bits(&bp, dxva->quantization.qm_y, 4);
+    mpp_put_bits(&bp, dxva->quantization.qm_u, 4);
+    mpp_put_bits(&bp, dxva->quantization.qm_v, 4);
+    mpp_put_bits(&bp, dxva->loop_filter.filter_level[0], 6);
+    mpp_put_bits(&bp, dxva->loop_filter.filter_level[1], 6);
+    mpp_put_bits(&bp, dxva->loop_filter.filter_level_u, 6);
+    mpp_put_bits(&bp, dxva->loop_filter.filter_level_v, 6);
+    mpp_put_bits(&bp, dxva->loop_filter.sharpness_level, 3);
+    mpp_put_bits(&bp, dxva->loop_filter.mode_ref_delta_enabled, 1);
+
+    for (i = 0; i < NUM_REF_FRAMES; i++)
+        mpp_put_bits(&bp, dxva->loop_filter.ref_deltas[i], 7);
+
+    for (i = 0; i < MAX_MODE_LF_DELTAS; i++)
+        mpp_put_bits(&bp, dxva->loop_filter.mode_deltas[i], 7);
+
+    /* cdef params */
+    mpp_put_bits(&bp, dxva->cdef.damping + 3, 3);
+    mpp_put_bits(&bp, dxva->cdef.bits, 2);
+
+    for (i = 0; i < 8; i++)
+        mpp_put_bits(&bp, dxva->cdef.y_strengths[i].primary, 4);
+
+    for (i = 0; i < 8; i++)
+        mpp_put_bits(&bp, dxva->cdef.uv_strengths[i].primary, 4);
+
+    for (i = 0; i < 8; i++)
+        mpp_put_bits(&bp, dxva->cdef.y_strengths[i].secondary, 2);
+
+    for (i = 0; i < 8; i++)
+        mpp_put_bits(&bp, dxva->cdef.uv_strengths[i].secondary, 2);
+
+    {
+        RK_U32 uses_lr = 0;
+
+        for (i = 0; i < (dxva->format.mono_chrome ? 1 : 3); i++)
+            uses_lr |= (dxva->loop_filter.frame_restoration_type[i] != AV1_RESTORE_NONE) ? 1 : 0;
+        mpp_put_bits(&bp, uses_lr, 1);
+    }
+    for (i = 0; i < 3; ++i)
+        mpp_put_bits(&bp, dxva->loop_filter.frame_restoration_type[i], 2);
+    for (i = 0; i < 2; ++i) // 0:32x32, 1:64x64, 2:128x128, 3:256x256
+        mpp_put_bits(&bp, dxva->loop_filter.log2_restoration_unit_size[i], 2);
+
+    mpp_put_bits(&bp, dxva->coding.tx_mode, 2);
+    mpp_put_bits(&bp, dxva->coding.reference_mode, 1);
+    mpp_put_bits(&bp, dxva->skip_ref0, 3);
+    mpp_put_bits(&bp, dxva->skip_ref1, 3);
+    mpp_put_bits(&bp, dxva->coding.skip_mode, 1);
+    mpp_put_bits(&bp, dxva->coding.warped_motion, 1);
+    mpp_put_bits(&bp, dxva->coding.reduced_tx_set, 1);
+
+    /* gm_type and gm_params */
+    for (i = 0; i < ALLOWED_REFS_PER_FRAME_EX; ++i)
+        mpp_put_bits(&bp, dxva->frame_refs[i].wmtype, 2);
+
+    for (i = 0; i < ALLOWED_REFS_PER_FRAME_EX; ++i)
+        for (j = 0; j < 6; j++)
+            mpp_put_bits(&bp, dxva->frame_refs[i].wmmat_val[j], 17);
+
+    /* film_grain_params */
+    {
+        mpp_put_bits(&bp, dxva->film_grain.apply_grain, 1);
+        mpp_put_bits(&bp, dxva->film_grain.grain_seed, 16);
+        mpp_put_bits(&bp, dxva->film_grain.update_grain, 1);
+        mpp_put_bits(&bp, dxva->film_grain.num_y_points, 4);
+
+        for (i = 0; i < 14; i++)
+            mpp_put_bits(&bp, dxva->film_grain.scaling_points_y[i][0], 8);
+
+        for (i = 0; i < 14; i++)
+            mpp_put_bits(&bp, dxva->film_grain.scaling_points_y[i][1], 8);
+
+        mpp_put_bits(&bp, dxva->film_grain.chroma_scaling_from_luma, 1);
+        mpp_put_bits(&bp, dxva->film_grain.num_cb_points, 4);
+
+        for (i = 0; i < 10; ++i)
+            mpp_put_bits(&bp, dxva->film_grain.scaling_points_cb[i][0], 8);
+
+        for (i = 0; i < 10; ++i)
+            mpp_put_bits(&bp, dxva->film_grain.scaling_points_cb[i][1], 8);
+
+        mpp_put_bits(&bp, dxva->film_grain.num_cr_points, 4);
+        for (i = 0; i < 10; ++i)
+            mpp_put_bits(&bp, dxva->film_grain.scaling_points_cr[i][0], 8);
+
+        for (i = 0; i < 10; ++i)
+            mpp_put_bits(&bp, dxva->film_grain.scaling_points_cr[i][1], 8);
+
+        mpp_put_bits(&bp, dxva->film_grain.scaling_shift_minus8, 2);
+        mpp_put_bits(&bp, dxva->film_grain.ar_coeff_lag, 2);
+        for (i = 0; i < 24; ++i)
+            mpp_put_bits(&bp, dxva->film_grain.ar_coeffs_y[i], 8);
+
+        for (i = 0; i < 25; ++i)
+            mpp_put_bits(&bp, dxva->film_grain.ar_coeffs_cb[i], 8);
+
+        for (i = 0; i < 25; ++i)
+            mpp_put_bits(&bp, dxva->film_grain.ar_coeffs_cr[i], 8);
+
+        mpp_put_bits(&bp, dxva->film_grain.ar_coeff_shift_minus6, 2);
+        mpp_put_bits(&bp, dxva->film_grain.grain_scale_shift, 2);
+        mpp_put_bits(&bp, dxva->film_grain.cb_mult, 8);
+        mpp_put_bits(&bp, dxva->film_grain.cb_luma_mult, 8);
+        mpp_put_bits(&bp, dxva->film_grain.cb_offset, 9);
+        mpp_put_bits(&bp, dxva->film_grain.cr_mult, 8);
+        mpp_put_bits(&bp, dxva->film_grain.cr_luma_mult, 8);
+        mpp_put_bits(&bp, dxva->film_grain.cr_offset, 9);
+        mpp_put_bits(&bp, dxva->film_grain.overlap_flag, 1);
+        mpp_put_bits(&bp, dxva->film_grain.clip_to_restricted_range, 1);
+    }
+
+    /* ref frame info */
+    for (i = 0; i < NUM_REF_FRAMES; ++i)
+        mpp_put_bits(&bp, dxva->frame_ref_state[i].upscaled_width, 16);
+
+    for (i = 0; i < NUM_REF_FRAMES; ++i)
+        mpp_put_bits(&bp, dxva->frame_ref_state[i].frame_height, 16);
+
+    for (i = 0; i < NUM_REF_FRAMES; ++i)
+        mpp_put_bits(&bp, dxva->frame_ref_state[i].frame_width, 16);
+
+    for (i = 0; i < NUM_REF_FRAMES; ++i)
+        mpp_put_bits(&bp, dxva->frame_ref_state[i].frame_type, 2);
+
+    for (i = 0; i < NUM_REF_FRAMES; ++i) {
+        mpp_put_bits(&bp, dxva->frame_refs[i].lst_frame_offset, 8);
+        mpp_put_bits(&bp, dxva->frame_refs[i].lst2_frame_offset, 8);
+        mpp_put_bits(&bp, dxva->frame_refs[i].lst3_frame_offset, 8);
+        mpp_put_bits(&bp, dxva->frame_refs[i].gld_frame_offset, 8);
+        mpp_put_bits(&bp, dxva->frame_refs[i].bwd_frame_offset, 8);
+        mpp_put_bits(&bp, dxva->frame_refs[i].alt2_frame_offset, 8);
+        mpp_put_bits(&bp, dxva->frame_refs[i].alt_frame_offset, 8);
+    }
+
+    {
+        RK_U32 mapped_idx = 0;
+        RK_U32 mapped_frame_width[8] = {0};
+        RK_U32 mapped_frame_height[8] = {0};
+
+        for (i = 0; i < ALLOWED_REFS_PER_FRAME_EX; i++) {
+            mapped_idx = dxva->ref_frame_idx[i];
+            mapped_frame_width[mapped_idx] = dxva->frame_ref_state[mapped_idx].frame_width;
+            mapped_frame_height[mapped_idx] = dxva->frame_ref_state[mapped_idx].frame_height;
+        }
+        for (i = 0; i <= ALLOWED_REFS_PER_FRAME_EX; ++i) {
+            RK_U32 hor_scale, ver_scale;
+
+            if (dxva->coding.intrabc) {
+                hor_scale = dxva->width;
+                ver_scale = dxva->height;
+            } else {
+                hor_scale = mapped_frame_width[i];
+                ver_scale = mapped_frame_height[i];
+            }
+            hor_scale = ((hor_scale << AV1_REF_SCALE_SHIFT) + dxva->width / 2) / dxva->width;
+            ver_scale = ((ver_scale << AV1_REF_SCALE_SHIFT) + dxva->height / 2) / dxva->height;
+
+            mpp_put_bits(&bp, hor_scale, 16);
+            mpp_put_bits(&bp, ver_scale, 16);
+        }
+    }
+
+    mpp_put_bits(&bp, (dxva->frame_header_size + 7) >> 3, 10);
+    /* tile info */
+    mpp_put_bits(&bp, dxva->tiles.cols, 7);
+    mpp_put_bits(&bp, dxva->tiles.rows, 7);
+    mpp_put_bits(&bp, dxva->tiles.context_update_id, 12);
+    mpp_put_bits(&bp, dxva->tiles.tile_sz_mag + 1, 3);
+    mpp_put_bits(&bp, dxva->tiles.cols * dxva->tiles.rows, 13);
+    mpp_put_bits(&bp, dxva->tile_cols_log2 + dxva->tile_rows_log2, 12);
+
+    for (i = 0; i < 64; i++)
+        mpp_put_bits(&bp, dxva->tiles.widths[i], 7);
+
+    for (i = 0; i < 64; i++)
+        mpp_put_bits(&bp, dxva->tiles.heights[i], 10);
+
+    mpp_put_align(&bp, 128, 0);
+
+    return MPP_OK;
+}
+
+static RK_S32 update_size_offset(Vdpu383RcbInfo *info, RK_U32 reg_idx,
+                                 RK_S32 offset, RK_S32 len, RK_S32 rcb_buf_idx)
+{
+    RK_S32 buf_size = 0;
+
+    buf_size = MPP_RCB_BYTES(len);
+    info[rcb_buf_idx].reg_idx = reg_idx;
+    info[rcb_buf_idx].offset = offset;
+    info[rcb_buf_idx].size = buf_size;
+
+    return buf_size;
+}
+
+#define VDPU383_SET_BUF_PROTECT_VAL(buf_p, buf_size, val, set_byte_cnt) \
+do { \
+    RK_U8 *but_p_tmp = (RK_U8 *)buf_p; \
+    memset(&but_p_tmp[0], val, set_byte_cnt); \
+    memset(&but_p_tmp[buf_size - set_byte_cnt], val, set_byte_cnt); \
+} while (0)
+
+#define VDPU383_DUMP_BUF_PROTECT_VAL(buf_p, buf_size, dump_byte_cnt) \
+do { \
+    RK_U32 prot_loop; \
+    RK_U8 *buf_p_tmp = (RK_U8 *)buf_p; \
+    printf("======> protect buffer begin\n"); \
+    for (prot_loop = 0; prot_loop < dump_byte_cnt; prot_loop++) { \
+        if (prot_loop % 32 == 0 && prot_loop != 0) \
+            printf("\n"); \
+        printf("0x%02x ", buf_p_tmp[prot_loop]); \
+    } \
+    printf("\n"); \
+    printf("======> protect buffer end\n"); \
+    for (prot_loop = 0; prot_loop < dump_byte_cnt; prot_loop++) { \
+        if (prot_loop % 32 == 0 && prot_loop != 0) \
+            printf("\n"); \
+        printf("0x%02x ", buf_p_tmp[buf_size - 1 - prot_loop]); \
+    } \
+    printf("\n"); \
+} while (0)
+
+#if 0
+static void rcb_buf_set_edge(Vdpu383Av1dRegCtx *reg_ctx, MppBuffer buf)
+{
+    RK_U32 loop;
+    RK_U8 *buf_p = mpp_buffer_get_ptr(buf);
+
+    for (loop = 0; loop < RCB_BUF_COUNT; loop++) {
+        VDPU383_SET_BUF_PROTECT_VAL(&buf_p[reg_ctx->rcb_buf_info[loop].offset],
+                                    reg_ctx->rcb_buf_info[loop].size, 0xaa, 128);
+    }
+}
+
+static void rcb_buf_dump_edge(Vdpu383Av1dRegCtx *reg_ctx, MppBuffer buf)
+{
+    RK_U8 *buf_p = mpp_buffer_get_ptr(buf);
+    RK_U32 loop;
+
+    for (loop = 0; loop < RCB_BUF_COUNT; loop++) {
+        // reg_ctx->rcb_buf_info[loop].reg;
+        // reg_ctx->rcb_buf_info[loop].offset;
+        // reg_ctx->rcb_buf_info[loop].size;
+
+        printf("======> reg idx:%d\n", reg_ctx->rcb_buf_info[loop].reg);
+        VDPU383_DUMP_BUF_PROTECT_VAL(&buf_p[reg_ctx->rcb_buf_info[loop].offset],
+                                     reg_ctx->rcb_buf_info[loop].size, 128);
+    }
+}
+#endif
+
+static void av1d_refine_rcb_size(Vdpu383RcbInfo *rcb_info,
+                                 RK_S32 width, RK_S32 height, void* data)
+{
+    RK_U32 rcb_bits = 0;
+    DXVA_PicParams_AV1 *pic_param = (DXVA_PicParams_AV1*)data;
+    RK_U32 tile_row_num = pic_param->tiles.rows;
+    RK_U32 tile_col_num = pic_param->tiles.cols;
+    RK_U32 bit_depth = pic_param->bitdepth;
+    RK_U32 sb_size = pic_param->coding.use_128x128_superblock ? 128 : 64;
+    RK_U32 ext_row_align_size = tile_row_num * 64 * 8;
+    RK_U32 ext_col_align_size = tile_col_num * 64 * 8;
+    RK_U32 filterd_row_append = 8192;
+
+    width = MPP_ALIGN(width, sb_size);
+    height = MPP_ALIGN(height, sb_size);
+    /* RCB_STRMD_ROW && RCB_STRMD_TILE_ROW*/
+    rcb_bits = ((width + 7) / 8) * 100;
+    rcb_info[RCB_STRMD_ROW].size = MPP_RCB_BYTES(rcb_bits);
+    rcb_info[RCB_STRMD_TILE_ROW].size = 0;
+
+    /* RCB_INTER_ROW && RCB_INTER_TILE_ROW*/
+    rcb_bits = ((width + 63) / 64) * 2752;
+    rcb_info[RCB_INTER_ROW].size = MPP_RCB_BYTES(rcb_bits);
+    rcb_bits += ext_row_align_size;
+    if (tile_row_num > 1)
+        rcb_info[RCB_INTER_TILE_ROW].size = MPP_RCB_BYTES(rcb_bits);
+    else
+        rcb_info[RCB_INTER_TILE_ROW].size = 0;
+
+    /* RCB_INTRA_ROW && RCB_INTRA_TILE_ROW*/
+    rcb_bits = MPP_ALIGN(width, 512) * (bit_depth + 2);
+    rcb_bits = rcb_bits * 3; //TODO:
+    rcb_info[RCB_INTRA_ROW].size = MPP_RCB_BYTES(rcb_bits);
+    rcb_bits += ext_row_align_size;
+    if (tile_row_num > 1)
+        rcb_info[RCB_INTRA_TILE_ROW].size = MPP_RCB_BYTES(rcb_bits);
+    else
+        rcb_info[RCB_INTRA_TILE_ROW].size = 0;
+
+    /* RCB_FILTERD_ROW && RCB_FILTERD_TILE_ROW*/
+    if (width > 4096)
+        filterd_row_append = 27648;
+    rcb_bits = (RK_U32)(MPP_ALIGN(width, 64) * (32 * bit_depth + 10));
+    rcb_info[RCB_FILTERD_ROW].size = MPP_RCB_BYTES(rcb_bits / 2);
+    rcb_info[RCB_FILTERD_PROTECT_ROW].size = filterd_row_append + MPP_RCB_BYTES(rcb_bits / 2);
+    rcb_bits += ext_row_align_size;
+    if (tile_row_num > 1)
+        rcb_info[RCB_FILTERD_TILE_ROW].size = MPP_RCB_BYTES(rcb_bits);
+    else
+        rcb_info[RCB_FILTERD_TILE_ROW].size = 0;
+
+    /* RCB_FILTERD_TILE_COL */
+    if (tile_col_num > 1) {
+        rcb_bits = (MPP_ALIGN(height, 64) * (101 * bit_depth + 32)) + ext_col_align_size;
+        rcb_info[RCB_FILTERD_TILE_COL].size = MPP_RCB_BYTES(rcb_bits);
+    } else {
+        rcb_info[RCB_FILTERD_TILE_COL].size = 0;
+    }
+
+}
+
+static void vdpu383_av1d_rcb_setup(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)
+{
+    Vdpu383Av1dRegCtx *reg_ctx = (Vdpu383Av1dRegCtx *)p_hal->reg_ctx;
+    RK_U32 offset = 0;
+    RK_U32 max_cnt = p_hal->fast_mode ? VDPU_FAST_REG_SET_CNT : 1;
+    RK_U32 i;
+
+    offset += update_size_offset(reg_ctx->rcb_buf_info, 140, offset, VDPU383_RCB_STRMD_ROW_LEN,             RCB_STRMD_ROW          );
+    offset += update_size_offset(reg_ctx->rcb_buf_info, 142, offset, VDPU383_RCB_STRMD_TILE_ROW_LEN,        RCB_STRMD_TILE_ROW     );
+    offset += update_size_offset(reg_ctx->rcb_buf_info, 144, offset, VDPU383_RCB_INTER_ROW_LEN,             RCB_INTER_ROW          );
+    offset += update_size_offset(reg_ctx->rcb_buf_info, 146, offset, VDPU383_RCB_INTER_TILE_ROW_LEN,        RCB_INTER_TILE_ROW     );
+    offset += update_size_offset(reg_ctx->rcb_buf_info, 148, offset, VDPU383_RCB_INTRA_ROW_LEN,             RCB_INTRA_ROW          );
+    offset += update_size_offset(reg_ctx->rcb_buf_info, 150, offset, VDPU383_RCB_INTRA_TILE_ROW_LEN,        RCB_INTRA_TILE_ROW     );
+    offset += update_size_offset(reg_ctx->rcb_buf_info, 152, offset, VDPU383_RCB_FILTERD_ROW_LEN,           RCB_FILTERD_ROW        );
+    offset += update_size_offset(reg_ctx->rcb_buf_info, 154, offset, VDPU383_RCB_FILTERD_PROTECT_ROW_LEN,   RCB_FILTERD_PROTECT_ROW);
+    offset += update_size_offset(reg_ctx->rcb_buf_info, 156, offset, VDPU383_RCB_FILTERD_TILE_ROW_LEN,      RCB_FILTERD_TILE_ROW   );
+    offset += update_size_offset(reg_ctx->rcb_buf_info, 158, offset, VDPU383_RCB_FILTERD_TILE_COL_LEN,      RCB_FILTERD_TILE_COL   );
+    offset += update_size_offset(reg_ctx->rcb_buf_info, 160, offset, VDPU383_RCB_FILTERD_AV1_UP_TL_COL_LEN, RCB_FILTERD_AV1_UP_TILE_COL);
+    reg_ctx->rcb_buf_size = offset;
+
+    av1d_refine_rcb_size(reg_ctx->rcb_buf_info, dxva->width, dxva->height, dxva);
+
+    for (i = 0; i < max_cnt; i++) {
+        MppBuffer rcb_buf = reg_ctx->rcb_bufs[i];
+
+        if (rcb_buf) {
+            mpp_buffer_put(rcb_buf);
+            reg_ctx->rcb_bufs[i] = NULL;
+        }
+        mpp_buffer_get(p_hal->buf_group, &rcb_buf, reg_ctx->rcb_buf_size);
+        reg_ctx->rcb_bufs[i] = rcb_buf;
+
+        // rcb_buf_set_edge(reg_ctx, rcb_buf);
+        // rcb_buf_dump_edge(reg_ctx, rcb_buf);
+    }
+
+    return;
+}
+
+static void vdpu383_av1d_rcb_reg_cfg(Av1dHalCtx *p_hal, MppBuffer buf)
+{
+    Vdpu383Av1dRegCtx *reg_ctx = (Vdpu383Av1dRegCtx *)p_hal->reg_ctx;
+    Vdpu383Av1dRegSet *regs = reg_ctx->regs;
+    RK_U32 fd = mpp_buffer_get_fd(buf);
+    RK_U32 i;
+
+    regs->rcb_paras.reg140_rcb_strmd_row_offset           = fd;
+    regs->rcb_paras.reg142_rcb_strmd_tile_row_offset      = fd;
+    regs->rcb_paras.reg144_rcb_inter_row_offset           = fd;
+    regs->rcb_paras.reg146_rcb_inter_tile_row_offset      = fd;
+    regs->rcb_paras.reg148_rcb_intra_row_offset           = fd;
+    regs->rcb_paras.reg150_rcb_intra_tile_row_offset      = fd;
+    regs->rcb_paras.reg152_rcb_filterd_row_offset         = fd;
+    regs->rcb_paras.reg154_rcb_filterd_protect_row_offset = fd;
+    regs->rcb_paras.reg156_rcb_filterd_tile_row_offset    = fd;
+    regs->rcb_paras.reg158_rcb_filterd_tile_col_offset    = fd;
+    regs->rcb_paras.reg160_rcb_filterd_av1_upscale_tile_col_offset = fd;
+
+    regs->rcb_paras.reg141_rcb_strmd_row_len            = reg_ctx->rcb_buf_info[RCB_STRMD_ROW].size;
+    regs->rcb_paras.reg143_rcb_strmd_tile_row_len       = reg_ctx->rcb_buf_info[RCB_STRMD_TILE_ROW].size;
+    regs->rcb_paras.reg145_rcb_inter_row_len            = reg_ctx->rcb_buf_info[RCB_INTER_ROW].size;
+    regs->rcb_paras.reg147_rcb_inter_tile_row_len       = reg_ctx->rcb_buf_info[RCB_INTER_TILE_ROW].size;
+    regs->rcb_paras.reg149_rcb_intra_row_len            = reg_ctx->rcb_buf_info[RCB_INTRA_ROW].size;
+    regs->rcb_paras.reg151_rcb_intra_tile_row_len       = reg_ctx->rcb_buf_info[RCB_INTRA_TILE_ROW].size;
+    regs->rcb_paras.reg153_rcb_filterd_row_len          = reg_ctx->rcb_buf_info[RCB_FILTERD_ROW].size;
+    regs->rcb_paras.reg155_rcb_filterd_protect_row_len  = reg_ctx->rcb_buf_info[RCB_FILTERD_PROTECT_ROW].size;
+    regs->rcb_paras.reg157_rcb_filterd_tile_row_len     = reg_ctx->rcb_buf_info[RCB_FILTERD_TILE_ROW].size;
+    regs->rcb_paras.reg159_rcb_filterd_tile_col_len     = reg_ctx->rcb_buf_info[RCB_FILTERD_TILE_COL].size;
+    regs->rcb_paras.reg161_rcb_filterd_av1_upscale_tile_col_len  = reg_ctx->rcb_buf_info[RCB_FILTERD_AV1_UP_TILE_COL].size;
+
+    for (i = 0; i < RCB_BUF_COUNT; i++)
+        mpp_dev_set_reg_offset(p_hal->dev, reg_ctx->rcb_buf_info[i].reg_idx, reg_ctx->rcb_buf_info[i].offset);
+}
+
+static MPP_RET vdpu383_av1d_colmv_setup(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)
+{
+    MPP_RET ret = MPP_ERR_UNKNOW;
+    Vdpu383Av1dRegCtx *reg_ctx = (Vdpu383Av1dRegCtx *)p_hal->reg_ctx;
+    size_t mv_size;
+
+    /* the worst case is the frame is error with whole frame */
+    mv_size = MPP_ALIGN(dxva->width, 64) / 64 * MPP_ALIGN(dxva->height, 64) / 64 * 1024;
+    if (reg_ctx->colmv_bufs == NULL || reg_ctx->colmv_size < mv_size) {
+        if (reg_ctx->colmv_bufs) {
+            hal_bufs_deinit(reg_ctx->colmv_bufs);
+            reg_ctx->colmv_bufs = NULL;
+        }
+
+        hal_bufs_init(&reg_ctx->colmv_bufs);
+        if (reg_ctx->colmv_bufs == NULL) {
+            mpp_err_f("colmv bufs init fail");
+            goto __RETURN;
+        }
+        reg_ctx->colmv_size = mv_size;
+        reg_ctx->colmv_count = mpp_buf_slot_get_count(p_hal->slots);
+        hal_bufs_setup(reg_ctx->colmv_bufs, reg_ctx->colmv_count, 1, &mv_size);
+    }
+
+__RETURN:
+    return ret;
+}
+
+static MPP_RET vdpu383_av1d_cdf_setup(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)
+{
+    MPP_RET ret = MPP_ERR_UNKNOW;
+    Vdpu383Av1dRegCtx *reg_ctx = (Vdpu383Av1dRegCtx *)p_hal->reg_ctx;
+
+    /* the worst case is the frame is error with whole frame */
+    if (reg_ctx->cdf_bufs == NULL) {
+        size_t size = ALL_CDF_SIZE;
+        size_t segid_size = (MPP_ALIGN(dxva->width, 128) / 128) * \
+                            (MPP_ALIGN(dxva->height, 128) / 128) * \
+                            32 * 16;
+
+        size += segid_size;
+
+        if (reg_ctx->cdf_bufs) {
+            hal_bufs_deinit(reg_ctx->cdf_bufs);
+            reg_ctx->cdf_bufs = NULL;
+        }
+
+        hal_bufs_init(&reg_ctx->cdf_bufs);
+        if (reg_ctx->cdf_bufs == NULL) {
+            mpp_err_f("cdf bufs init fail");
+            goto __RETURN;
+        }
+
+        reg_ctx->cdf_size = size;
+        reg_ctx->cdf_count = mpp_buf_slot_get_count(p_hal->slots);
+        hal_bufs_setup(reg_ctx->cdf_bufs, reg_ctx->cdf_count, 1, &size);
+    }
+
+__RETURN:
+    return ret;
+}
+
+static void vdpu383_av1d_set_cdf(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)
+{
+    Vdpu383Av1dRegCtx *reg_ctx = (Vdpu383Av1dRegCtx *)p_hal->reg_ctx;
+    Vdpu383Av1dRegSet *regs = reg_ctx->regs;
+    RK_U32 coeff_cdf_idx = 0;
+    RK_U32 mapped_idx = 0;
+    HalBuf *cdf_buf = NULL;
+    RK_U32 i = 0;
+    MppBuffer buf_tmp = NULL;
+
+    /* use para in decoder */
+#ifdef DUMP_AV1D_VDPU383_DATAS
+    {
+        char *cur_fname = "cabac_cdf_in.dat";
+        memset(dump_cur_fname_path, 0, sizeof(dump_cur_fname_path));
+        sprintf(dump_cur_fname_path, "%s/%s", dump_cur_dir, cur_fname);
+    }
+#endif
+    if (dxva->format.frame_type == AV1_FRAME_KEY || dxva->primary_ref_frame == 7 /* AV1_PRIMARY_REF_NONE */) {
+        if (dxva->quantization.base_qindex <= 20)
+            coeff_cdf_idx = 0;
+        else if (dxva->quantization.base_qindex <= 60)
+            coeff_cdf_idx = 1;
+        else if (dxva->quantization.base_qindex <= 120)
+            coeff_cdf_idx = 2;
+        else
+            coeff_cdf_idx = 3;
+
+        regs->av1d_addrs.reg184_av1_noncoef_rd_base = mpp_buffer_get_fd(reg_ctx->cdf_rd_def_base);
+        regs->av1d_addrs.reg178_av1_coef_rd_base = mpp_buffer_get_fd(reg_ctx->cdf_rd_def_base);
+#ifdef DUMP_AV1D_VDPU383_DATAS
+        {
+            dump_data_to_file(dump_cur_fname_path, (void *)mpp_buffer_get_ptr(reg_ctx->cdf_rd_def_base),
+                              8 * NON_COEF_CDF_SIZE, 128, 0, 0);
+            dump_data_to_file(dump_cur_fname_path, (RK_U8 *)mpp_buffer_get_ptr(reg_ctx->cdf_rd_def_base)
+                              + NON_COEF_CDF_SIZE + COEF_CDF_SIZE * coeff_cdf_idx,
+                              8 * COEF_CDF_SIZE, 128, 0, 1);
+        }
+#endif
+    } else {
+        mapped_idx = dxva->ref_frame_idx[dxva->primary_ref_frame];
+
+        coeff_cdf_idx = reg_ctx->ref_info_tbl[mapped_idx].coeff_idx;
+        if (!dxva->coding.disable_frame_end_update_cdf) {
+            cdf_buf = hal_bufs_get_buf(reg_ctx->cdf_bufs, dxva->frame_refs[mapped_idx].Index);
+            buf_tmp = cdf_buf->buf[0];
+        } else {
+            buf_tmp = reg_ctx->cdf_rd_def_base;
+        }
+        regs->av1d_addrs.reg184_av1_noncoef_rd_base = mpp_buffer_get_fd(buf_tmp);
+        regs->av1d_addrs.reg178_av1_coef_rd_base = mpp_buffer_get_fd(buf_tmp);
+        regs->av1d_addrs.reg181_av1_rd_segid_base = mpp_buffer_get_fd(buf_tmp);
+#ifdef DUMP_AV1D_VDPU383_DATAS
+        {
+            dump_data_to_file(dump_cur_fname_path, (void *)mpp_buffer_get_ptr(buf_tmp),
+                              8 * NON_COEF_CDF_SIZE, 128, 0, 0);
+            dump_data_to_file(dump_cur_fname_path, (RK_U8 *)mpp_buffer_get_ptr(buf_tmp)
+                              + NON_COEF_CDF_SIZE + COEF_CDF_SIZE * coeff_cdf_idx,
+                              8 * COEF_CDF_SIZE, 128, 0, 1);
+        }
+#endif
+    }
+    cdf_buf = hal_bufs_get_buf(reg_ctx->cdf_bufs, dxva->CurrPic.Index7Bits);
+    regs->av1d_addrs.reg185_av1_noncoef_wr_base = mpp_buffer_get_fd(cdf_buf->buf[0]);
+    regs->av1d_addrs.reg179_av1_coef_wr_base = mpp_buffer_get_fd(cdf_buf->buf[0]);
+    regs->av1d_addrs.reg182_av1_wr_segid_base = mpp_buffer_get_fd(cdf_buf->buf[0]);
+
+    /* byte, 434 x 128 bit = 434 x 16 byte */
+    mpp_dev_set_reg_offset(p_hal->dev, 178, NON_COEF_CDF_SIZE + COEF_CDF_SIZE * coeff_cdf_idx);
+    mpp_dev_set_reg_offset(p_hal->dev, 179, NON_COEF_CDF_SIZE);
+    mpp_dev_set_reg_offset(p_hal->dev, 181, ALL_CDF_SIZE);
+    mpp_dev_set_reg_offset(p_hal->dev, 182, ALL_CDF_SIZE);
+
+    /* update params sync with "update buffer" */
+    for (i = 0; i < NUM_REF_FRAMES; i++) {
+        if (dxva->refresh_frame_flags & (1 << i)) {
+            if (dxva->coding.disable_frame_end_update_cdf) {
+                if (dxva->show_existing_frame && dxva->format.frame_type == AV1_FRAME_KEY)
+                    reg_ctx->ref_info_tbl[i].coeff_idx
+                        = reg_ctx->ref_info_tbl[dxva->frame_to_show_map_idx].coeff_idx;
+                else
+                    reg_ctx->ref_info_tbl[i].coeff_idx = coeff_cdf_idx;
+            } else {
+                reg_ctx->ref_info_tbl[i].coeff_idx = 0;
+            }
+        }
+    }
+
+#ifdef DUMP_AV1D_VDPU383_DATAS
+    {
+        char *cur_fname = "cdf_rd_def.dat";
+        memset(dump_cur_fname_path, 0, sizeof(dump_cur_fname_path));
+        sprintf(dump_cur_fname_path, "%s/%s", dump_cur_dir, cur_fname);
+        dump_data_to_file(dump_cur_fname_path, (void *)mpp_buffer_get_ptr(reg_ctx->cdf_rd_def_base),
+                          (NON_COEF_CDF_SIZE + COEF_CDF_SIZE * 4) * 8, 128, 0, 0);
+    }
+#endif
+
+}
+
+MPP_RET vdpu383_av1d_gen_regs(void *hal, HalTaskInfo *task)
+{
+    MPP_RET ret = MPP_ERR_UNKNOW;
+    Av1dHalCtx *p_hal = (Av1dHalCtx *)hal;
+    Vdpu383Av1dRegCtx *ctx = (Vdpu383Av1dRegCtx *)p_hal->reg_ctx;
+    Vdpu383Av1dRegSet *regs;
+    DXVA_PicParams_AV1 *dxva = (DXVA_PicParams_AV1*)task->dec.syntax.data;
+    RK_U32 i = 0;
+    HalBuf *origin_buf = NULL;
+    MppFrame mframe;
+
+    INP_CHECK(ret, NULL == p_hal);
+
+    ctx->refresh_frame_flags = dxva->refresh_frame_flags;
+
+    if (task->dec.flags.parse_err ||
+        task->dec.flags.ref_err) {
+        mpp_err_f("parse err %d ref err %d\n",
+                  task->dec.flags.parse_err, task->dec.flags.ref_err);
+        goto __RETURN;
+    }
+
+    mpp_buf_slot_get_prop(p_hal->slots, dxva->CurrPic.Index7Bits, SLOT_FRAME_PTR, &mframe);
+    if (mpp_frame_get_thumbnail_en(mframe) == MPP_FRAME_THUMBNAIL_ONLY &&
+        MPP_MAX(dxva->width, dxva->height) > 4096 && ctx->origin_bufs == NULL) {
+        vdpu383_setup_scale_origin_bufs(p_hal, mframe);
+    }
+
+    if (p_hal->fast_mode) {
+        for (i = 0; i <  MPP_ARRAY_ELEMS(ctx->reg_buf); i++) {
+            if (!ctx->reg_buf[i].valid) {
+                task->dec.reg_index = i;
+                ctx->regs = ctx->reg_buf[i].regs;
+                ctx->reg_buf[i].valid = 1;
+                ctx->offset_uncomps = ctx->uncmps_offset[i];
+                break;
+            }
+        }
+    }
+    regs = ctx->regs;
+    memset(regs, 0, sizeof(*regs));
+    p_hal->strm_len = (RK_S32)mpp_packet_get_length(task->dec.input_packet);
+
+#ifdef DUMP_AV1D_VDPU383_DATAS
+    {
+        memset(dump_cur_dir, 0, sizeof(dump_cur_dir));
+        sprintf(dump_cur_dir, "av1/Frame%04d", dump_cur_frame);
+        if (access(dump_cur_dir, 0)) {
+            if (mkdir(dump_cur_dir))
+                mpp_err_f("error: mkdir %s\n", dump_cur_dir);
+        }
+        dump_cur_frame++;
+    }
+#endif
+
+    /* set reg -> ctrl reg */
+    {
+        regs->ctrl_regs.reg8_dec_mode          = 4; // av1
+        regs->ctrl_regs.reg9.fbc_e             = 0;
+        regs->ctrl_regs.reg9.buf_empty_en      = 0;
+
+        regs->ctrl_regs.reg10.strmd_auto_gating_e    = 1;
+        regs->ctrl_regs.reg10.inter_auto_gating_e    = 1;
+        regs->ctrl_regs.reg10.intra_auto_gating_e    = 1;
+        regs->ctrl_regs.reg10.transd_auto_gating_e   = 1;
+        regs->ctrl_regs.reg10.recon_auto_gating_e    = 1;
+        regs->ctrl_regs.reg10.filterd_auto_gating_e  = 1;
+        regs->ctrl_regs.reg10.bus_auto_gating_e      = 1;
+        regs->ctrl_regs.reg10.ctrl_auto_gating_e     = 1;
+        regs->ctrl_regs.reg10.rcb_auto_gating_e      = 1;
+        regs->ctrl_regs.reg10.err_prc_auto_gating_e  = 1;
+
+        // regs->ctrl_regs.reg11.dec_timeout_dis        = 1;
+
+        regs->ctrl_regs.reg13_core_timeout_threshold  = 0x3fffff;
+
+        regs->ctrl_regs.reg16.error_proc_disable     = 1;
+        regs->ctrl_regs.reg16.error_spread_disable   = 0;
+        regs->ctrl_regs.reg16.roi_error_ctu_cal_en   = 0;
+
+        regs->ctrl_regs.reg20_cabac_error_en_lowbits  = 0xffffffdf;
+        regs->ctrl_regs.reg21_cabac_error_en_highbits = 0x3fffffff;
+
+        regs->ctrl_regs.reg28.axi_perf_work_e = 1;
+        regs->ctrl_regs.reg28.axi_cnt_type    = 1;
+        regs->ctrl_regs.reg28.rd_latency_id   = 11;
+
+        regs->ctrl_regs.reg29.addr_align_type     = 1;
+        regs->ctrl_regs.reg29.ar_cnt_id_type      = 0;
+        regs->ctrl_regs.reg29.aw_cnt_id_type      = 1;
+        regs->ctrl_regs.reg29.ar_count_id         = 17;
+        regs->ctrl_regs.reg29.aw_count_id         = 0;
+        regs->ctrl_regs.reg29.rd_band_width_mode  = 0;
+
+        regs->ctrl_regs.reg30.axi_wr_qos = 0;
+        regs->ctrl_regs.reg30.axi_rd_qos = 0;
+    }
+
+    /* set reg -> pkt data */
+    {
+        MppBuffer mbuffer = NULL;
+
+        /* uncompress header data */
+        prepare_uncompress_header(p_hal, dxva, (RK_U64 *)ctx->header_data, sizeof(ctx->header_data) / 8);
+        memcpy((char *)ctx->bufs_ptr, (void *)ctx->header_data, sizeof(ctx->header_data));
+        regs->av1d_paras.reg67_global_len = VDPU383_UNCMPS_HEADER_SIZE / 16; // 128 bit as unit
+        regs->com_pkt_addr.reg131_gbl_base = ctx->bufs_fd;
+        // mpp_dev_set_reg_offset(p_hal->dev, 131, ctx->offset_uncomps);
+#ifdef DUMP_AV1D_VDPU383_DATAS
+        {
+            char *cur_fname = "global_cfg.dat";
+            memset(dump_cur_fname_path, 0, sizeof(dump_cur_fname_path));
+            sprintf(dump_cur_fname_path, "%s/%s", dump_cur_dir, cur_fname);
+            dump_data_to_file(dump_cur_fname_path, ctx->bufs_ptr,
+                              8 * regs->av1d_paras.reg67_global_len * 16, 64, 0, 0);
+        }
+#endif
+        // input strm
+        p_hal->strm_len = (RK_S32)mpp_packet_get_length(task->dec.input_packet);
+        regs->av1d_paras.reg66_stream_len = MPP_ALIGN(p_hal->strm_len + 15, 128);
+        mpp_buf_slot_get_prop(p_hal->packet_slots, task->dec.input, SLOT_BUFFER, &mbuffer);
+        regs->com_pkt_addr.reg128_strm_base = mpp_buffer_get_fd(mbuffer);
+        regs->av1d_paras.reg65_strm_start_bit = (ctx->offset_uncomps & 0xf) * 8; // bit start to decode
+        mpp_dev_set_reg_offset(p_hal->dev, 128, ctx->offset_uncomps & 0xfffffff0);
+        /* error */
+        regs->av1d_addrs.reg169_error_ref_base = mpp_buffer_get_fd(mbuffer);
+#ifdef DUMP_AV1D_VDPU383_DATAS
+        {
+            char *cur_fname = "stream_in.dat";
+            memset(dump_cur_fname_path, 0, sizeof(dump_cur_fname_path));
+            sprintf(dump_cur_fname_path, "%s/%s", dump_cur_dir, cur_fname);
+            dump_data_to_file(dump_cur_fname_path, (void *)mpp_buffer_get_ptr(mbuffer)
+                              + ctx->offset_uncomps,
+                              8 * p_hal->strm_len, 128, 0, 0);
+        }
+        {
+            char *cur_fname = "stream_in_no_offset.dat";
+            memset(dump_cur_fname_path, 0, sizeof(dump_cur_fname_path));
+            sprintf(dump_cur_fname_path, "%s/%s", dump_cur_dir, cur_fname);
+            dump_data_to_file(dump_cur_fname_path, (void *)mpp_buffer_get_ptr(mbuffer),
+                              8 * p_hal->strm_len, 128, 0, 0);
+        }
+#endif
+    }
+
+    /* set reg -> rcb */
+    vdpu383_av1d_rcb_setup(p_hal, dxva);
+    vdpu383_av1d_rcb_reg_cfg(p_hal, p_hal->fast_mode ? ctx->rcb_bufs[task->dec.reg_index] : ctx->rcb_bufs[0]);
+
+    /* set reg -> para (stride, len) */
+    {
+        RK_U32 hor_virstride = 0;
+        RK_U32 ver_virstride = 0;
+        RK_U32 y_virstride = 0;
+        RK_U32 uv_virstride = 0;
+        RK_U32 mapped_idx;
+
+        mpp_buf_slot_get_prop(p_hal->slots, dxva->CurrPic.Index7Bits, SLOT_FRAME_PTR, &mframe);
+        if (mframe) {
+            hor_virstride = mpp_frame_get_hor_stride(mframe);
+            ver_virstride = mpp_frame_get_ver_stride(mframe);
+            y_virstride = hor_virstride * ver_virstride;
+            uv_virstride = hor_virstride * ver_virstride / 2;
+
+            if (MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(mframe))) {
+                RK_U32 fbd_offset;
+                RK_U32 w = MPP_ALIGN(mpp_frame_get_width(mframe), 64);
+                RK_U32 h = MPP_ALIGN(mpp_frame_get_height(mframe), 8);
+
+                regs->ctrl_regs.reg9.fbc_e = 1;
+                regs->av1d_paras.reg68_hor_virstride = w / 64;
+                fbd_offset = regs->av1d_paras.reg68_hor_virstride * h * 4;
+                regs->av1d_addrs.reg193_fbc_payload_offset = fbd_offset;
+            } else if (MPP_FRAME_FMT_IS_TILE(mpp_frame_get_fmt(mframe))) {
+                regs->ctrl_regs.reg9.tile_e = 1;
+                regs->av1d_paras.reg68_hor_virstride = MPP_ALIGN(hor_virstride * 6, 16) >> 4;
+                regs->av1d_paras.reg70_y_virstride = (y_virstride + uv_virstride) >> 4;
+            } else {
+                regs->ctrl_regs.reg9.fbc_e = 0;
+                regs->av1d_paras.reg68_hor_virstride = hor_virstride >> 4;
+                regs->av1d_paras.reg69_raster_uv_hor_virstride = hor_virstride >> 4;
+                regs->av1d_paras.reg70_y_virstride = y_virstride >> 4;
+            }
+            /* error */
+            regs->av1d_paras.reg80_error_ref_hor_virstride = regs->av1d_paras.reg68_hor_virstride;
+            regs->av1d_paras.reg81_error_ref_raster_uv_hor_virstride = regs->av1d_paras.reg69_raster_uv_hor_virstride;
+            regs->av1d_paras.reg82_error_ref_virstride = regs->av1d_paras.reg70_y_virstride;
+        }
+
+        for (i = 0; i < ALLOWED_REFS_PER_FRAME_EX; ++i) {
+            mapped_idx = dxva->ref_frame_idx[i];
+            if (dxva->frame_refs[mapped_idx].Index != (CHAR)0xff && dxva->frame_refs[mapped_idx].Index != 0x7f) {
+                mpp_buf_slot_get_prop(p_hal->slots, dxva->frame_refs[mapped_idx].Index, SLOT_FRAME_PTR, &mframe);
+                if (mframe) {
+                    hor_virstride = mpp_frame_get_hor_stride(mframe);
+                    ver_virstride = mpp_frame_get_ver_stride(mframe);
+                    y_virstride = hor_virstride * ver_virstride;
+                    if (MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(mframe))) {
+                        hor_virstride = MPP_ALIGN(mpp_frame_get_width(mframe), 64) / 4;
+                    } else if (MPP_FRAME_FMT_IS_TILE(mpp_frame_get_fmt(mframe))) {
+                        hor_virstride = MPP_ALIGN(hor_virstride * 6, 16);
+                        y_virstride += y_virstride / 2;
+                    }
+                    SET_REF_HOR_VIRSTRIDE(regs->av1d_paras, mapped_idx, hor_virstride >> 4);
+                    SET_REF_RASTER_UV_HOR_VIRSTRIDE(regs->av1d_paras, mapped_idx, hor_virstride >> 4);
+                    SET_REF_VIRSTRIDE(regs->av1d_paras, mapped_idx, y_virstride >> 4);
+                }
+            }
+        }
+    }
+
+    /* set reg -> para (ref, fbc, colmv) */
+    {
+        MppBuffer mbuffer = NULL;
+        RK_U32 mapped_idx;
+        mpp_buf_slot_get_prop(p_hal->slots, task->dec.output, SLOT_FRAME_PTR, &mframe);
+        mpp_buf_slot_get_prop(p_hal->slots, task->dec.output, SLOT_BUFFER, &mbuffer);
+        regs->av1d_addrs.reg168_decout_base = mpp_buffer_get_fd(mbuffer);
+        regs->av1d_addrs.reg192_payload_st_cur_base = mpp_buffer_get_fd(mbuffer);
+        // VDPU383_SET_BUF_PROTECT_VAL(mpp_buffer_get_ptr(mbuffer), mpp_buffer_get_size(mbuffer), 0xbb, 128);
+
+        for (i = 0; i < ALLOWED_REFS_PER_FRAME_EX; i++) {
+            mapped_idx = dxva->ref_frame_idx[i];
+            if (dxva->frame_refs[mapped_idx].Index != (CHAR)0xff && dxva->frame_refs[mapped_idx].Index != 0x7f) {
+                mpp_buf_slot_get_prop(p_hal->slots, dxva->frame_refs[mapped_idx].Index, SLOT_BUFFER, &mbuffer);
+                if (ctx->origin_bufs && mpp_frame_get_thumbnail_en(mframe) == MPP_FRAME_THUMBNAIL_ONLY) {
+                    origin_buf = hal_bufs_get_buf(ctx->origin_bufs, dxva->frame_refs[mapped_idx].Index);
+                    mbuffer = origin_buf->buf[0];
+                }
+                if (mbuffer) {
+                    SET_REF_BASE(regs->av1d_addrs, mapped_idx, mpp_buffer_get_fd(mbuffer));
+                    SET_FBC_PAYLOAD_REF_BASE(regs->av1d_addrs, mapped_idx, mpp_buffer_get_fd(mbuffer));
+                }
+            }
+        }
+
+        // regs->av1d_addrs.reg192_payload_st_cur_base;
+        // regs->av1d_addrs.reg193_fbc_payload_offset;
+        // regs->av1d_addrs.reg194_payload_st_error_ref_base;
+        // regs->av1d_addrs.reg195_payload_st_ref0_base;
+        // regs->av1d_addrs.reg196_payload_st_ref1_base;
+        // regs->av1d_addrs.reg197_payload_st_ref2_base;
+        // regs->av1d_addrs.reg198_payload_st_ref3_base;
+        // regs->av1d_addrs.reg199_payload_st_ref4_base;
+        // regs->av1d_addrs.reg200_payload_st_ref5_base;
+        // regs->av1d_addrs.reg201_payload_st_ref6_base;
+        // regs->av1d_addrs.reg202_payload_st_ref7_base;
+        // regs->av1d_addrs.reg203_payload_st_ref8_base;
+        // regs->av1d_addrs.reg204_payload_st_ref9_base;
+        // regs->av1d_addrs.reg205_payload_st_ref10_base;
+        // regs->av1d_addrs.reg206_payload_st_ref11_base;
+        // regs->av1d_addrs.reg207_payload_st_ref12_base;
+        // regs->av1d_addrs.reg208_payload_st_ref13_base;
+        // regs->av1d_addrs.reg209_payload_st_ref14_base;
+        // regs->av1d_addrs.reg210_payload_st_ref15_base;
+
+        HalBuf *mv_buf = NULL;
+        vdpu383_av1d_colmv_setup(p_hal, dxva);
+        mv_buf = hal_bufs_get_buf(ctx->colmv_bufs, dxva->CurrPic.Index7Bits);
+        regs->av1d_addrs.reg216_colmv_cur_base = mpp_buffer_get_fd(mv_buf->buf[0]);
+#ifdef DUMP_AV1D_VDPU383_DATAS
+        memset(mpp_buffer_get_ptr(mv_buf->buf[0]), 0, mpp_buffer_get_size(mv_buf->buf[0]));
+#endif
+        for (i = 0; i < NUM_REF_FRAMES; i++) {
+            if (dxva->frame_refs[i].Index != (CHAR)0xff && dxva->frame_refs[i].Index != 0x7f) {
+                mv_buf = hal_bufs_get_buf(ctx->colmv_bufs, dxva->frame_refs[i].Index);
+                regs->av1d_addrs.reg217_232_colmv_ref_base[i] = mpp_buffer_get_fd(mv_buf->buf[0]);
+#ifdef DUMP_AV1D_VDPU383_DATAS
+                {
+                    char *cur_fname = "colmv_ref_frame";
+                    memset(dump_cur_fname_path, 0, sizeof(dump_cur_fname_path));
+                    sprintf(dump_cur_fname_path, "%s/%s%d.dat", dump_cur_dir, cur_fname, i);
+                    dump_data_to_file(dump_cur_fname_path, (void *)mpp_buffer_get_ptr(mv_buf->buf[0]),
+                                      8 * mpp_buffer_get_size(mv_buf->buf[0]), 64, 0, 0);
+                }
+#endif
+            }
+        }
+    }
+
+    {
+        vdpu383_av1d_cdf_setup(p_hal, dxva);
+        vdpu383_av1d_set_cdf(p_hal, dxva);
+    }
+    mpp_buffer_sync_end(ctx->bufs);
+
+    {
+        //scale down config
+        MppBuffer mbuffer = NULL;
+        RK_S32 fd = -1;
+        MppFrameThumbnailMode thumbnail_mode;
+
+        mpp_buf_slot_get_prop(p_hal->slots, dxva->CurrPic.Index7Bits, SLOT_BUFFER, &mbuffer);
+        mpp_buf_slot_get_prop(p_hal->slots, dxva->CurrPic.Index7Bits,
+                              SLOT_FRAME_PTR, &mframe);
+        thumbnail_mode = mpp_frame_get_thumbnail_en(mframe);
+        fd = mpp_buffer_get_fd(mbuffer);
+
+        switch (thumbnail_mode) {
+        case MPP_FRAME_THUMBNAIL_ONLY:
+            regs->com_pkt_addr.reg133_scale_down_tile_base = fd;
+            origin_buf = hal_bufs_get_buf(ctx->origin_bufs, dxva->CurrPic.Index7Bits);
+            fd = mpp_buffer_get_fd(origin_buf->buf[0]);
+            regs->av1d_addrs.reg168_decout_base = fd;
+            regs->av1d_addrs.reg192_payload_st_cur_base = fd;
+            regs->av1d_addrs.reg169_error_ref_base = fd;
+            vdpu383_setup_down_scale(mframe, p_hal->dev, &regs->ctrl_regs,
+                                     (void *)&regs->av1d_paras);
+            break;
+        case MPP_FRAME_THUMBNAIL_MIXED:
+            regs->com_pkt_addr.reg133_scale_down_tile_base = fd;
+            vdpu383_setup_down_scale(mframe, p_hal->dev, &regs->ctrl_regs,
+                                     (void *)&regs->av1d_paras);
+            break;
+        case MPP_FRAME_THUMBNAIL_NONE:
+        default:
+            regs->ctrl_regs.reg9.scale_down_en = 0;
+            break;
+        }
+    }
+
+__RETURN:
+    return ret = MPP_OK;
+}
+
+MPP_RET vdpu383_av1d_start(void *hal, HalTaskInfo *task)
+{
+    MPP_RET ret = MPP_ERR_UNKNOW;
+    Av1dHalCtx *p_hal = (Av1dHalCtx *)hal;
+    INP_CHECK(ret, NULL == p_hal);
+    if (task->dec.flags.parse_err ||
+        task->dec.flags.ref_err) {
+        goto __RETURN;
+    }
+
+    Vdpu383Av1dRegCtx *reg_ctx = (Vdpu383Av1dRegCtx *)p_hal->reg_ctx;
+    Vdpu383Av1dRegSet *regs = p_hal->fast_mode ?
+                              reg_ctx->reg_buf[task->dec.reg_index].regs :
+                              reg_ctx->regs;
+    MppDev dev = p_hal->dev;
+    do {
+        MppDevRegWrCfg wr_cfg;
+        MppDevRegRdCfg rd_cfg;
+
+        wr_cfg.reg = &regs->ctrl_regs;
+        wr_cfg.size = sizeof(regs->ctrl_regs);
+        wr_cfg.offset = OFFSET_CTRL_REGS;
+        ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
+        if (ret) {
+            mpp_err_f("set register write failed %d\n", ret);
+            break;
+        }
+
+        wr_cfg.reg = &regs->com_pkt_addr;
+        wr_cfg.size = sizeof(regs->com_pkt_addr);
+        wr_cfg.offset = OFFSET_COMMON_ADDR_REGS;
+        ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
+        if (ret) {
+            mpp_err_f("set register write failed %d\n", ret);
+            break;
+        }
+
+        wr_cfg.reg = &regs->rcb_paras;
+        wr_cfg.size = sizeof(regs->rcb_paras);
+        wr_cfg.offset = OFFSET_RCB_PARAS_REGS;
+        ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
+        if (ret) {
+            mpp_err_f("set register write failed %d\n", ret);
+            break;
+        }
+
+        wr_cfg.reg = &regs->av1d_paras;
+        wr_cfg.size = sizeof(regs->av1d_paras);
+        wr_cfg.offset = OFFSET_AV1D_PARAS_REGS;
+        ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
+        if (ret) {
+            mpp_err_f("set register write failed %d\n", ret);
+            break;
+        }
+
+        wr_cfg.reg = &regs->av1d_addrs;
+        wr_cfg.size = sizeof(regs->av1d_addrs);
+        wr_cfg.offset = OFFSET_AV1D_ADDR_REGS;
+        ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
+        if (ret) {
+            mpp_err_f("set register write failed %d\n", ret);
+            break;
+        }
+
+        rd_cfg.reg = &regs->ctrl_regs.reg15;
+        rd_cfg.size = sizeof(regs->ctrl_regs.reg15);
+        rd_cfg.offset = OFFSET_INTERRUPT_REGS;
+        ret = mpp_dev_ioctl(dev, MPP_DEV_REG_RD, &rd_cfg);
+        if (ret) {
+            mpp_err_f("set register read failed %d\n", ret);
+            break;
+        }
+
+        /* rcb info for sram */
+        vdpu383_set_rcbinfo(dev, (Vdpu383RcbInfo*)reg_ctx->rcb_buf_info);
+
+        /* send request to hardware */
+        ret = mpp_dev_ioctl(dev, MPP_DEV_CMD_SEND, NULL);
+        if (ret) {
+            mpp_err_f("send cmd failed %d\n", ret);
+            break;
+        }
+    } while (0);
+
+__RETURN:
+    return ret = MPP_OK;
+}
+
+MPP_RET vdpu383_av1d_wait(void *hal, HalTaskInfo *task)
+{
+    MPP_RET ret = MPP_ERR_UNKNOW;
+    Av1dHalCtx *p_hal = (Av1dHalCtx *)hal;
+
+    INP_CHECK(ret, NULL == p_hal);
+    Vdpu383Av1dRegCtx *reg_ctx = (Vdpu383Av1dRegCtx *)p_hal->reg_ctx;
+    Vdpu383Av1dRegSet *p_regs = p_hal->fast_mode ?
+                                reg_ctx->reg_buf[task->dec.reg_index].regs :
+                                reg_ctx->regs;
+#ifdef DUMP_AV1D_VDPU383_DATAS
+    {
+        char *cur_fname = "colmv_cur_frame.dat";
+        DXVA_PicParams_AV1 *dxva = (DXVA_PicParams_AV1*)task->dec.syntax.data;
+        HalBuf *mv_buf = NULL;
+        mv_buf = hal_bufs_get_buf(reg_ctx->colmv_bufs, dxva->CurrPic.Index7Bits);
+        memset(dump_cur_fname_path, 0, sizeof(dump_cur_fname_path));
+        sprintf(dump_cur_fname_path, "%s/%s", dump_cur_dir, cur_fname);
+        dump_data_to_file(dump_cur_fname_path, (void *)mpp_buffer_get_ptr(mv_buf->buf[0]),
+                          8 * mpp_buffer_get_size(mv_buf->buf[0]), 64, 0, 0);
+    }
+    {
+        char *cur_fname = "decout.dat";
+        MppBuffer mbuffer = NULL;
+        mpp_buf_slot_get_prop(p_hal->slots, task->dec.output, SLOT_BUFFER, &mbuffer);
+        memset(dump_cur_fname_path, 0, sizeof(dump_cur_fname_path));
+        sprintf(dump_cur_fname_path, "%s/%s", dump_cur_dir, cur_fname);
+        dump_data_to_file(dump_cur_fname_path, (void *)mpp_buffer_get_ptr(mbuffer),
+                          8 * mpp_buffer_get_size(mbuffer), 128, 0, 0);
+    }
+#endif
+
+    if (task->dec.flags.parse_err ||
+        task->dec.flags.ref_err) {
+        goto __SKIP_HARD;
+    }
+
+    // rcb_buf_dump_edge(reg_ctx, p_hal->fast_mode ? reg_ctx->rcb_bufs[task->dec.reg_index] : reg_ctx->rcb_bufs[0]);
+    // {
+    //     MppBuffer mbuffer = NULL;
+    //     mpp_buf_slot_get_prop(p_hal->slots, task->dec.output, SLOT_BUFFER, &mbuffer);
+    //     VDPU383_DUMP_BUF_PROTECT_VAL(mpp_buffer_get_ptr(mbuffer), mpp_buffer_get_size(mbuffer), 128);
+    // }
+
+    ret = mpp_dev_ioctl(p_hal->dev, MPP_DEV_CMD_POLL, NULL);
+    if (ret)
+        mpp_err_f("poll cmd failed %d\n", ret);
+#ifdef DUMP_AV1D_VDPU383_DATAS
+    {
+        char *cur_fname = "cabac_cdf_out.dat";
+        HalBuf *cdf_buf = NULL;
+        DXVA_PicParams_AV1 *dxva = (DXVA_PicParams_AV1*)task->dec.syntax.data;
+        memset(dump_cur_fname_path, 0, sizeof(dump_cur_fname_path));
+        sprintf(dump_cur_fname_path, "%s/%s", dump_cur_dir, cur_fname);
+        cdf_buf = hal_bufs_get_buf(reg_ctx->cdf_bufs, dxva->CurrPic.Index7Bits);
+        dump_data_to_file(dump_cur_fname_path, (void *)mpp_buffer_get_ptr(cdf_buf->buf[0]),
+                          (NON_COEF_CDF_SIZE + COEF_CDF_SIZE) * 8, 128, 0, 0);
+    }
+#endif
+
+    if (task->dec.flags.parse_err ||
+        task->dec.flags.ref_err ||
+        (!p_regs->ctrl_regs.reg15.rkvdec_frame_rdy_sta) ||
+        p_regs->ctrl_regs.reg15.rkvdec_strm_error_sta ||
+        p_regs->ctrl_regs.reg15.rkvdec_core_timeout_sta ||
+        p_regs->ctrl_regs.reg15.rkvdec_ip_timeout_sta ||
+        p_regs->ctrl_regs.reg15.rkvdec_bus_error_sta ||
+        p_regs->ctrl_regs.reg15.rkvdec_buffer_empty_sta ||
+        p_regs->ctrl_regs.reg15.rkvdec_colmv_ref_error_sta) {
+        MppFrame mframe = NULL;
+
+        mpp_buf_slot_get_prop(p_hal->slots, task->dec.output, SLOT_FRAME_PTR, &mframe);
+        mpp_frame_set_errinfo(mframe, 1);
+    }
+
+__SKIP_HARD:
+    if (p_hal->fast_mode)
+        reg_ctx->reg_buf[task->dec.reg_index].valid = 0;
+
+    (void)task;
+__RETURN:
+    return ret = MPP_OK;
+}
+
+MPP_RET vdpu383_av1d_reset(void *hal)
+{
+    MPP_RET ret = MPP_ERR_UNKNOW;
+    Av1dHalCtx *p_hal = (Av1dHalCtx *)hal;
+
+    INP_CHECK(ret, NULL == p_hal);
+
+
+__RETURN:
+    return ret = MPP_OK;
+}
+
+MPP_RET vdpu383_av1d_flush(void *hal)
+{
+    MPP_RET ret = MPP_ERR_UNKNOW;
+    Av1dHalCtx *p_hal = (Av1dHalCtx *)hal;
+
+    INP_CHECK(ret, NULL == p_hal);
+
+__RETURN:
+    return ret = MPP_OK;
+}
+
+MPP_RET vdpu383_av1d_control(void *hal, MpiCmd cmd_type, void *param)
+{
+    Av1dHalCtx *p_hal = (Av1dHalCtx *)hal;
+    MPP_RET ret = MPP_ERR_UNKNOW;
+
+    INP_CHECK(ret, NULL == p_hal);
+
+    switch ((MpiCmd)cmd_type) {
+    case MPP_DEC_SET_FRAME_INFO : {
+        MppFrameFormat fmt = mpp_frame_get_fmt((MppFrame)param);
+        RK_U32 imgwidth = mpp_frame_get_width((MppFrame)param);
+        RK_U32 imgheight = mpp_frame_get_height((MppFrame)param);
+
+        AV1D_DBG(AV1D_DBG_LOG, "control info: fmt %d, w %d, h %d\n", fmt, imgwidth, imgheight);
+        if ((fmt & MPP_FRAME_FMT_MASK) == MPP_FMT_YUV422SP) {
+            mpp_slots_set_prop(p_hal->slots, SLOTS_LEN_ALIGN, rkv_len_align_422);
+        }
+        if (MPP_FRAME_FMT_IS_FBC(fmt)) {
+            vdpu383_afbc_align_calc(p_hal->slots, (MppFrame)param, 16);
+        } else if (imgwidth > 1920 || imgheight > 1088) {
+            mpp_slots_set_prop(p_hal->slots, SLOTS_HOR_ALIGN, mpp_align_128_odd_plus_64);
+        }
+        break;
+    }
+    case MPP_DEC_GET_THUMBNAIL_FRAME_INFO: {
+        vdpu383_update_thumbnail_frame_info((MppFrame)param);
+    } break;
+    case MPP_DEC_SET_OUTPUT_FORMAT : {
+    } break;
+    default : {
+    } break;
+    }
+
+__RETURN:
+    return ret = MPP_OK;
+}
+
+const MppHalApi hal_av1d_vdpu383 = {
+    .name       = "av1d_vdpu383",
+    .type       = MPP_CTX_DEC,
+    .coding     = MPP_VIDEO_CodingAV1,
+    .ctx_size   = sizeof(Vdpu383Av1dRegCtx),
+    .flag       = 0,
+    .init       = vdpu383_av1d_init,
+    .deinit     = vdpu383_av1d_deinit,
+    .reg_gen    = vdpu383_av1d_gen_regs,
+    .start      = vdpu383_av1d_start,
+    .wait       = vdpu383_av1d_wait,
+    .reset      = vdpu383_av1d_reset,
+    .flush      = vdpu383_av1d_flush,
+    .control    = vdpu383_av1d_control,
+};
diff --git a/mpp/hal/rkdec/av1d/hal_av1d_vdpu383.h b/mpp/hal/rkdec/av1d/hal_av1d_vdpu383.h
new file mode 100644
index 000000000..536e856d6
--- /dev/null
+++ b/mpp/hal/rkdec/av1d/hal_av1d_vdpu383.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: Apache-2.0 OR MIT */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef __HAL_AV1D_VDPU383_H__
+#define __HAL_AV1D_VDPU383_H__
+
+#include "mpp_hal.h"
+#include "vdpu383.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern const MppHalApi hal_av1d_vdpu383;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HAL_AV1D_VDPU383_H__ */
diff --git a/mpp/hal/rkdec/av1d/hal_av1d_vdpu383_reg.h b/mpp/hal/rkdec/av1d/hal_av1d_vdpu383_reg.h
new file mode 100644
index 000000000..7adef3b2c
--- /dev/null
+++ b/mpp/hal/rkdec/av1d/hal_av1d_vdpu383_reg.h
@@ -0,0 +1,364 @@
+/* SPDX-License-Identifier: Apache-2.0 OR MIT */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef __HAL_AV1D_VDPU383_REG_H__
+#define __HAL_AV1D_VDPU383_REG_H__
+
+#include "rk_type.h"
+#include "vdpu383_com.h"
+
+typedef struct Vdpu383RegComPktAddr_t {
+    /* SWREG128_STRM_BASE */
+    RK_U32 reg128_strm_base;
+
+    /* SWREG129_RPS_BASE */
+    RK_U32 reg129_rps_base;
+
+    /* SWREG130_CABACTBL_BASE */
+    RK_U32 reg130_cabactbl_base;
+
+    /* SWREG131_GBL_BASE */
+    RK_U32 reg131_gbl_base;
+
+    /* SWREG132_SCANLIST_ADDR */
+    RK_U32 reg132_scanlist_addr;
+
+    /* SWREG133_SCALE_DOWN_TILE_BASE */
+    RK_U32 reg133_scale_down_tile_base;
+
+    /* SWREG134_SCALE_DOWN_TILE_BASE */
+    RK_U32 reg134_fgs_base;
+} Vdpu383RegComPktAddr;
+
+typedef struct Vdpu383RegRcbParas_t {
+    /* SWREG140_RCB_STRMD_ROW_OFFSET */
+    RK_U32 reg140_rcb_strmd_row_offset;
+
+    /* SWREG141_RCB_STRMD_ROW_LEN */
+    RK_U32 reg141_rcb_strmd_row_len;
+
+    /* SWREG142_RCB_STRMD_TILE_ROW_OFFSET */
+    RK_U32 reg142_rcb_strmd_tile_row_offset;
+
+    /* SWREG143_RCB_STRMD_TILE_ROW_LEN */
+    RK_U32 reg143_rcb_strmd_tile_row_len;
+
+    /* SWREG144_RCB_INTER_ROW_OFFSET */
+    RK_U32 reg144_rcb_inter_row_offset;
+
+    /* SWREG145_RCB_INTER_ROW_LEN */
+    RK_U32 reg145_rcb_inter_row_len;
+
+    /* SWREG146_RCB_INTER_TILE_ROW_OFFSET */
+    RK_U32 reg146_rcb_inter_tile_row_offset;
+
+    /* SWREG147_RCB_INTER_TILE_ROW_LEN */
+    RK_U32 reg147_rcb_inter_tile_row_len;
+
+    /* SWREG148_RCB_INTRA_ROW_OFFSET */
+    RK_U32 reg148_rcb_intra_row_offset;
+
+    /* SWREG149_RCB_INTRA_ROW_LEN */
+    RK_U32 reg149_rcb_intra_row_len;
+
+    /* SWREG150_RCB_INTRA_TILE_ROW_OFFSET */
+    RK_U32 reg150_rcb_intra_tile_row_offset;
+
+    /* SWREG151_RCB_INTRA_TILE_ROW_LEN */
+    RK_U32 reg151_rcb_intra_tile_row_len;
+
+    /* SWREG152_RCB_FILTERD_ROW_OFFSET */
+    RK_U32 reg152_rcb_filterd_row_offset;
+
+    /* SWREG153_RCB_FILTERD_ROW_LEN */
+    RK_U32 reg153_rcb_filterd_row_len;
+
+    /* SWREG154_RCB_FILTERD_PROTECT_ROW_OFFSET */
+    RK_U32 reg154_rcb_filterd_protect_row_offset;
+
+    /* SWREG155_RCB_FILTERD_PROTECT_ROW_LEN */
+    RK_U32 reg155_rcb_filterd_protect_row_len;
+
+    /* SWREG156_RCB_FILTERD_TILE_ROW_OFFSET */
+    RK_U32 reg156_rcb_filterd_tile_row_offset;
+
+    /* SWREG157_RCB_FILTERD_TILE_ROW_LEN */
+    RK_U32 reg157_rcb_filterd_tile_row_len;
+
+    /* SWREG158_RCB_FILTERD_TILE_COL_OFFSET */
+    RK_U32 reg158_rcb_filterd_tile_col_offset;
+
+    /* SWREG159_RCB_FILTERD_TILE_COL_LEN */
+    RK_U32 reg159_rcb_filterd_tile_col_len;
+
+    /* SWREG160_RCB_FILTERD_AV1_UPSCALE_TILE_COL_OFFSET */
+    RK_U32 reg160_rcb_filterd_av1_upscale_tile_col_offset;
+
+    /* SWREG161_RCB_FILTERD_AV1_UPSCALE_TILE_COL_LEN */
+    RK_U32 reg161_rcb_filterd_av1_upscale_tile_col_len;
+
+} Vdpu383RegRcbParas;
+
+typedef struct Vdpu383RegAv1dParas_t {
+    struct SWREG64_H26X_PARA {
+        RK_U32 reserve0                       : 4;
+        RK_U32 unused_bits                    : 28;
+    } reg64;
+
+    /* SWREG65_STREAM_PARAM_SET */
+    RK_U32 reg65_strm_start_bit;
+
+    /* SWREG66_STREAM_LEN */
+    RK_U32 reg66_stream_len;
+
+    /* SWREG67_GLOBAL_LEN */
+    RK_U32 reg67_global_len;
+
+    /* SWREG68_HOR_STRIDE */
+    RK_U32 reg68_hor_virstride;
+
+    /* SWREG69_RASTER_UV_HOR_STRIDE */
+    RK_U32 reg69_raster_uv_hor_virstride;
+
+    /* SWREG70_Y_STRIDE */
+    RK_U32 reg70_y_virstride;
+
+    /* SWREG71_SCL_Y_HOR_VIRSTRIDE */
+    RK_U32 reg71_scl_ref_hor_virstride;
+
+    /* SWREG72_SCL_UV_HOR_VIRSTRIDE */
+    RK_U32 reg72_scl_ref_raster_uv_hor_virstride;
+
+    /* SWREG73_SCL_Y_VIRSTRIDE */
+    RK_U32 reg73_scl_ref_virstride;
+
+    /* SWREG74_FGS_Y_HOR_VIRSTRIDE */
+    RK_U32 reg74_fgs_ref_hor_virstride;
+
+    RK_U32 reserve_reg75_79[5];
+
+    /* SWREG80_ERROR_REF_Y_HOR_VIRSTRIDE */
+    RK_U32 reg80_error_ref_hor_virstride;
+
+    /* SWREG81_ERROR_REF_UV_HOR_VIRSTRIDE */
+    RK_U32 reg81_error_ref_raster_uv_hor_virstride;
+
+    /* SWREG82_ERROR_REF_Y_VIRSTRIDE */
+    RK_U32 reg82_error_ref_virstride;
+
+    /* SWREG83_REF0_Y_HOR_VIRSTRIDE */
+    RK_U32 reg83_ref0_hor_virstride;
+
+    /* SWREG84_REF0_UV_HOR_VIRSTRIDE */
+    RK_U32 reg84_ref0_raster_uv_hor_virstride;
+
+    /* SWREG85_REF0_Y_VIRSTRIDE */
+    RK_U32 reg85_ref0_virstride;
+
+    /* SWREG86_REF1_Y_HOR_VIRSTRIDE */
+    RK_U32 reg86_ref1_hor_virstride;
+
+    /* SWREG87_REF1_UV_HOR_VIRSTRIDE */
+    RK_U32 reg87_ref1_raster_uv_hor_virstride;
+
+    /* SWREG88_REF1_Y_VIRSTRIDE */
+    RK_U32 reg88_ref1_virstride;
+
+    /* SWREG89_REF2_Y_HOR_VIRSTRIDE */
+    RK_U32 reg89_ref2_hor_virstride;
+
+    /* SWREG90_REF2_UV_HOR_VIRSTRIDE */
+    RK_U32 reg90_ref2_raster_uv_hor_virstride;
+
+    /* SWREG91_REF2_Y_VIRSTRIDE */
+    RK_U32 reg91_ref2_virstride;
+
+    /* SWREG92_REF3_Y_HOR_VIRSTRIDE */
+    RK_U32 reg92_ref3_hor_virstride;
+
+    /* SWREG93_REF3_UV_HOR_VIRSTRIDE */
+    RK_U32 reg93_ref3_raster_uv_hor_virstride;
+
+    /* SWREG94_REF3_Y_VIRSTRIDE */
+    RK_U32 reg94_ref3_virstride;
+
+    /* SWREG95_REF4_Y_HOR_VIRSTRIDE */
+    RK_U32 reg95_ref4_hor_virstride;
+
+    /* SWREG96_REF4_UV_HOR_VIRSTRIDE */
+    RK_U32 reg96_ref4_raster_uv_hor_virstride;
+
+    /* SWREG97_REF4_Y_VIRSTRIDE */
+    RK_U32 reg97_ref4_virstride;
+
+    /* SWREG98_REF5_Y_HOR_VIRSTRIDE */
+    RK_U32 reg98_ref5_hor_virstride;
+
+    /* SWREG99_REF5_UV_HOR_VIRSTRIDE */
+    RK_U32 reg99_ref5_raster_uv_hor_virstride;
+
+    /* SWREG100_REF5_Y_VIRSTRIDE */
+    RK_U32 reg100_ref5_virstride;
+
+    /* SWREG101_REF6_Y_HOR_VIRSTRIDE */
+    RK_U32 reg101_ref6_hor_virstride;
+
+    /* SWREG102_REF6_UV_HOR_VIRSTRIDE */
+    RK_U32 reg102_ref6_raster_uv_hor_virstride;
+
+    /* SWREG103_REF6_Y_VIRSTRIDE */
+    RK_U32 reg103_ref6_virstride;
+
+    /* SWREG104_REF7_Y_HOR_VIRSTRIDE */
+    RK_U32 reg104_ref7_hor_virstride;
+
+    /* SWREG105_REF7_UV_HOR_VIRSTRIDE */
+    RK_U32 reg105_ref7_raster_uv_hor_virstride;
+
+    /* SWREG106_REF7_Y_VIRSTRIDE */
+    RK_U32 reg106_ref7_virstride;
+
+} Vdpu383RegAv1dParas;
+
+typedef struct Vdpu383RegAv1dAddr_t {
+    /* SWREG168_DECOUT_BASE */
+    RK_U32 reg168_decout_base;
+
+    /* SWREG169_ERROR_REF_BASE */
+    RK_U32 reg169_error_ref_base;
+
+    /* SWREG170_REF0_BASE */
+    // RK_U32 reg170_refer0_base;
+    RK_U32 reg170_av1_last_base;
+
+    /* SWREG171_REF1_BASE */
+    // RK_U32 reg171_refer1_base;
+    RK_U32 reg171_av1golden_base;
+
+    /* SWREG172_REF2_BASE */
+    // RK_U32 reg172_refer2_base;
+    RK_U32 reg172_av1alfter_base;
+
+    /* SWREG173_REF3_BASE */
+    RK_U32 reg173_refer3_base;
+
+    /* SWREG174_REF4_BASE */
+    RK_U32 reg174_refer4_base;
+
+    /* SWREG175_REF5_BASE */
+    RK_U32 reg175_refer5_base;
+
+    /* SWREG176_REF6_BASE */
+    RK_U32 reg176_refer6_base;
+
+    /* SWREG177_REF7_BASE */
+    RK_U32 reg177_refer7_base;
+
+    /* SWREG178_H26X_REF8_BASE */
+    // RK_U32 reg178_refer8_base;
+    RK_U32 reg178_av1_coef_rd_base;
+
+    /* SWREG179_H26X_REF9_BASE */
+    // RK_U32 reg179_refer9_base;
+    RK_U32 reg179_av1_coef_wr_base;
+
+    /* SWREG180_H26X_REF10_BASE */
+    RK_U32 reg180_refer10_base;
+
+    /* SWREG181_H26X_REF11_BASE */
+    RK_U32 reg181_av1_rd_segid_base;
+
+    /* SWREG182_H26X_REF12_BASE */
+    RK_U32 reg182_av1_wr_segid_base;
+
+    /* SWREG183_H26X_REF13_BASE */
+    RK_U32 reg183_kf_prob_base;
+
+    /* SWREG184_H26X_REF14_BASE */
+    RK_U32 reg184_av1_noncoef_rd_base;
+
+    /* SWREG185_H26X_REF15_BASE */
+    RK_U32 reg185_av1_noncoef_wr_base;
+
+    RK_U32 reserve_reg186_191[6];
+
+    /* SWREG192_PAYLOAD_ST_CUR_BASE */
+    RK_U32 reg192_payload_st_cur_base;
+
+    /* SWREG193_FBC_PAYLOAD_OFFSET */
+    RK_U32 reg193_fbc_payload_offset;
+
+    /* SWREG194_PAYLOAD_ST_ERROR_REF_BASE */
+    RK_U32 reg194_payload_st_error_ref_base;
+
+    /* SWREG195_PAYLOAD_ST_REF0_BASE */
+    RK_U32 reg195_payload_st_ref0_base;
+
+    /* SWREG196_PAYLOAD_ST_REF1_BASE */
+    RK_U32 reg196_payload_st_ref1_base;
+
+    /* SWREG197_PAYLOAD_ST_REF2_BASE */
+    RK_U32 reg197_payload_st_ref2_base;
+
+    /* SWREG198_PAYLOAD_ST_REF3_BASE */
+    RK_U32 reg198_payload_st_ref3_base;
+
+    /* SWREG199_PAYLOAD_ST_REF4_BASE */
+    RK_U32 reg199_payload_st_ref4_base;
+
+    /* SWREG200_PAYLOAD_ST_REF5_BASE */
+    RK_U32 reg200_payload_st_ref5_base;
+
+    /* SWREG201_PAYLOAD_ST_REF6_BASE */
+    RK_U32 reg201_payload_st_ref6_base;
+
+    /* SWREG202_PAYLOAD_ST_REF7_BASE */
+    RK_U32 reg202_payload_st_ref7_base;
+
+    /* SWREG203_PAYLOAD_ST_REF8_BASE */
+    RK_U32 reg203_payload_st_ref8_base;
+
+    /* SWREG204_PAYLOAD_ST_REF9_BASE */
+    RK_U32 reg204_payload_st_ref9_base;
+
+    /* SWREG205_PAYLOAD_ST_REF10_BASE */
+    RK_U32 reg205_payload_st_ref10_base;
+
+    /* SWREG206_PAYLOAD_ST_REF11_BASE */
+    RK_U32 reg206_payload_st_ref11_base;
+
+    /* SWREG207_PAYLOAD_ST_REF12_BASE */
+    RK_U32 reg207_payload_st_ref12_base;
+
+    /* SWREG208_PAYLOAD_ST_REF13_BASE */
+    RK_U32 reg208_payload_st_ref13_base;
+
+    /* SWREG209_PAYLOAD_ST_REF14_BASE */
+    RK_U32 reg209_payload_st_ref14_base;
+
+    /* SWREG210_PAYLOAD_ST_REF15_BASE */
+    RK_U32 reg210_payload_st_ref15_base;
+
+    RK_U32 reserve_reg211_215[5];
+
+    /* SWREG216_COLMV_CUR_BASE */
+    RK_U32 reg216_colmv_cur_base;
+
+    /* SWREG217_232_COLMV_REF0_BASE */
+    RK_U32 reg217_232_colmv_ref_base[16];
+} Vdpu383RegAv1dAddr;
+
+typedef struct Vdpu383Av1dRegSet_t {
+    Vdpu383RegVersion     reg_version;
+    Vdpu383CtrlReg        ctrl_regs;         /* 8-30 */
+    Vdpu383RegComPktAddr  com_pkt_addr;      /* 128-133 */
+    Vdpu383RegRcbParas    rcb_paras;         /* 140-161 */
+    Vdpu383RegAv1dParas   av1d_paras;        /* 64-106 */
+    Vdpu383RegAv1dAddr    av1d_addrs;        /* 168-185(ref) */
+    /* 192-210(fbc) */
+    /* 216-232(col mv) */
+} Vdpu383Av1dRegSet;
+
+#endif /* __HAL_AV1D_VDPU383_REG_H__ */
\ No newline at end of file
diff --git a/mpp/hal/rkdec/avs2d/CMakeLists.txt b/mpp/hal/rkdec/avs2d/CMakeLists.txt
index b838f735f..6e9a0bfdf 100644
--- a/mpp/hal/rkdec/avs2d/CMakeLists.txt
+++ b/mpp/hal/rkdec/avs2d/CMakeLists.txt
@@ -14,6 +14,7 @@ set(HAL_AVS2D_HDR
 set(HAL_AVS2D_SRC
     hal_avs2d_rkv.c
     hal_avs2d_vdpu382.c
+    hal_avs2d_vdpu383.c
     hal_avs2d_api.c
     )
 
@@ -23,6 +24,6 @@ add_library(hal_avs2d STATIC
             ${HAL_AVS2D_SRC}
             )
 
-target_link_libraries(hal_avs2d mpp_base)
+target_link_libraries(hal_avs2d mpp_base vdpu383_com)
 set_target_properties(hal_avs2d PROPERTIES FOLDER "mpp/hal")
 
diff --git a/mpp/hal/rkdec/avs2d/hal_avs2d_api.c b/mpp/hal/rkdec/avs2d/hal_avs2d_api.c
index f616c58b8..98c898122 100644
--- a/mpp/hal/rkdec/avs2d/hal_avs2d_api.c
+++ b/mpp/hal/rkdec/avs2d/hal_avs2d_api.c
@@ -32,6 +32,7 @@
 #include "hal_avs2d_api.h"
 #include "hal_avs2d_rkv.h"
 #include "hal_avs2d_vdpu382.h"
+#include "hal_avs2d_vdpu383.h"
 
 RK_U32 avs2d_hal_debug = 0;
 
@@ -48,7 +49,7 @@ MPP_RET hal_avs2d_deinit(void *hal)
     AVS2D_HAL_TRACE("In.");
     INP_CHECK(ret, NULL == hal);
 
-    FUN_CHECK(ret = p_hal->hal_api.deinit(hal));
+    FUN_CHECK(ret = p_hal->hal_api->deinit(hal));
 
     if (p_hal->buf_group) {
         FUN_CHECK(ret = mpp_buffer_group_put(p_hal->buf_group));
@@ -72,7 +73,7 @@ MPP_RET hal_avs2d_init(void *hal, MppHalCfg *cfg)
 {
     MPP_RET ret = MPP_OK;
     Avs2dHalCtx_t *p_hal = NULL;
-    MppHalApi *p_api = NULL;
+    const MppHalApi *api;
 
     AVS2D_HAL_TRACE("In.");
     INP_CHECK(ret, NULL == hal);
@@ -85,30 +86,25 @@ MPP_RET hal_avs2d_init(void *hal, MppHalCfg *cfg)
 
     RK_U32 hw_id = mpp_get_client_hw_id(VPU_CLIENT_RKVDEC);
 
-    p_api          = &p_hal->hal_api;
-    if (hw_id == HWID_VDPU382_RK3528) {
-        p_api->init    = hal_avs2d_vdpu382_init;
-        p_api->deinit  = hal_avs2d_vdpu382_deinit;
-        p_api->reg_gen = hal_avs2d_vdpu382_gen_regs;
-        p_api->start   = hal_avs2d_vdpu382_start;
-        p_api->wait    = hal_avs2d_vdpu382_wait;
-    } else {
-        p_api->init    = hal_avs2d_rkv_init;
-        p_api->deinit  = hal_avs2d_rkv_deinit;
-        p_api->reg_gen = hal_avs2d_rkv_gen_regs;
-        p_api->start   = hal_avs2d_rkv_start;
-        p_api->wait    = hal_avs2d_rkv_wait;
+    switch (hw_id) {
+    case HWID_VDPU383 : {
+        api = &hal_avs2d_vdpu383;
+    } break;
+    case HWID_VDPU382_RK3528 : {
+        api = &hal_avs2d_vdpu382;
+    } break;
+    default : {
+        api = &hal_avs2d_rkvdpu;
+    } break;
     }
 
-    p_api->reset   = NULL;
-    p_api->flush   = NULL;
-    p_api->control = NULL;
-
     ret = mpp_dev_init(&cfg->dev, VPU_CLIENT_RKVDEC);
     if (ret) {
         mpp_err("mpp_dev_init failed. ret: %d\n", ret);
         return ret;
     }
+    cfg->hw_info = mpp_get_dec_hw_info_by_client_type(VPU_CLIENT_RKVDEC);
+    p_hal->hw_info = cfg->hw_info;
     cfg->support_fast_mode = 1;
 
     p_hal->cfg = cfg->cfg;
@@ -123,7 +119,9 @@ MPP_RET hal_avs2d_init(void *hal, MppHalCfg *cfg)
         FUN_CHECK(ret = mpp_buffer_group_get_internal(&p_hal->buf_group, MPP_BUFFER_TYPE_ION));
 
     //!< run init funtion
-    FUN_CHECK(ret = p_api->init(hal, cfg));
+    FUN_CHECK(ret = api->init(hal, cfg));
+
+    p_hal->hal_api = api;
 
 __RETURN:
     AVS2D_HAL_TRACE("Out.");
@@ -138,36 +136,38 @@ MPP_RET hal_avs2d_gen_regs(void *hal, HalTaskInfo *task)
     Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
 
     explain_input_buffer(hal, &task->dec);
-    return p_hal->hal_api.reg_gen(hal, task);
-}
-
-MPP_RET hal_avs2d_start(void *hal, HalTaskInfo *task)
-{
-    Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
-
-    return p_hal->hal_api.start(hal, task);
+    if (!p_hal || !p_hal->hal_api || !p_hal->hal_api->reg_gen)
+        return MPP_NOK;
 
+    return p_hal->hal_api->reg_gen(hal, task);
 }
 
-MPP_RET hal_avs2d_wait(void *hal, HalTaskInfo *task)
-{
-    Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
+#define HAL_AVS2D_TASK_FUNC(func) \
+    static MPP_RET hal_avs2d_##func(void *hal, HalTaskInfo *task)   \
+    {                                                               \
+        Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;                \
+                                                                    \
+        if (!p_hal || !p_hal->hal_api || !p_hal->hal_api->func)     \
+            return MPP_OK;                                          \
+                                                                    \
+        return p_hal->hal_api->func(hal, task);                     \
+    }
 
-    return p_hal->hal_api.wait(hal, task);
-}
+HAL_AVS2D_TASK_FUNC(start);
+HAL_AVS2D_TASK_FUNC(wait);
 
 const MppHalApi hal_api_avs2d = {
-    .name = "avs2d_rkdec",
-    .type = MPP_CTX_DEC,
-    .coding = MPP_VIDEO_CodingAVS2,
+    .name     = "avs2d_rkdec",
+    .type     = MPP_CTX_DEC,
+    .coding   = MPP_VIDEO_CodingAVS2,
     .ctx_size = sizeof(Avs2dHalCtx_t),
-    .flag = 0,
-    .init = hal_avs2d_init,
-    .deinit = hal_avs2d_deinit,
-    .reg_gen = hal_avs2d_gen_regs,
-    .start = hal_avs2d_start,
-    .wait = hal_avs2d_wait,
-    .reset = NULL,
-    .flush = NULL,
-    .control = NULL,
+    .flag     = 0,
+    .init     = hal_avs2d_init,
+    .deinit   = hal_avs2d_deinit,
+    .reg_gen  = hal_avs2d_gen_regs,
+    .start    = hal_avs2d_start,
+    .wait     = hal_avs2d_wait,
+    .reset    = NULL,
+    .flush    = NULL,
+    .control  = NULL,
 };
diff --git a/mpp/hal/rkdec/avs2d/hal_avs2d_global.h b/mpp/hal/rkdec/avs2d/hal_avs2d_global.h
index 9a2c2d5b0..88f1d5285 100644
--- a/mpp/hal/rkdec/avs2d/hal_avs2d_global.h
+++ b/mpp/hal/rkdec/avs2d/hal_avs2d_global.h
@@ -1,17 +1,6 @@
+/* SPDX-License-Identifier: Apache-2.0 OR MIT */
 /*
- * Copyright 2021 Rockchip Electronics Co. LTD
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *      http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
  */
 
 #ifndef __HAL_AVS2D_GLOBAL_H__
@@ -89,7 +78,7 @@ enum {
 };
 
 typedef struct avs2d_hal_ctx_t {
-    MppHalApi               hal_api;
+    const MppHalApi         *hal_api;
     MppDecCfgSet            *cfg;
     MppBufSlots             frame_slots;
     MppBufSlots             packet_slots;
diff --git a/mpp/hal/rkdec/avs2d/hal_avs2d_rkv.c b/mpp/hal/rkdec/avs2d/hal_avs2d_rkv.c
index bf1eb003e..9ad2c349f 100644
--- a/mpp/hal/rkdec/avs2d/hal_avs2d_rkv.c
+++ b/mpp/hal/rkdec/avs2d/hal_avs2d_rkv.c
@@ -30,7 +30,6 @@
 #include "hal_avs2d_rkv.h"
 #include "mpp_dec_cb_param.h"
 #include "vdpu34x_avs2d.h"
-#include "rk_hdr_meta_com.h"
 
 #define VDPU34X_FAST_REG_SET_CNT    (3)
 #define MAX_REF_NUM                 (8)
@@ -79,6 +78,7 @@ typedef struct avs2d_reg_ctx_t {
 
 } Avs2dRkvRegCtx_t;
 
+MPP_RET hal_avs2d_rkv_deinit(void *hal);
 static RK_U32 avs2d_ver_align(RK_U32 val)
 {
     return MPP_ALIGN(val, 16);
@@ -403,7 +403,7 @@ static MPP_RET fill_registers(Avs2dHalCtx_t *p_hal, Vdpu34xAvs2dRegSet *p_regs,
         for (i = 0; i < refp->ref_pic_num; i++) {
             MppFrame frame_ref = NULL;
 
-            RK_S32 slot_idx = task_dec->refer[i] < 0 ? valid_slot : task_dec->refer[i];
+            RK_S32 slot_idx = task_dec->refer[i] < 0 ? task_dec->refer[valid_slot] : task_dec->refer[i];
 
             if (slot_idx < 0) {
                 AVS2D_HAL_DBG(AVS2D_HAL_DBG_ERROR, "missing ref, could not found valid ref");
@@ -467,8 +467,7 @@ static MPP_RET fill_registers(Avs2dHalCtx_t *p_hal, Vdpu34xAvs2dRegSet *p_regs,
         p_regs->common_addr.reg129_rlcwrite_base = p_regs->common_addr.reg128_rlc_base;
         common->reg016_str_len = MPP_ALIGN(mpp_packet_get_length(task_dec->input_packet), 16) + 64;
     }
-    if (MPP_FRAME_FMT_IS_HDR(mpp_frame_get_fmt(mframe)) && p_hal->cfg->base.enable_hdr_meta)
-        fill_hdr_meta_to_frame(mframe, HDR_AVS2);
+
     return ret;
 }
 
@@ -552,22 +551,6 @@ MPP_RET hal_avs2d_rkv_init(void *hal, MppHalCfg *cfg)
     mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, avs2d_ver_align);
     mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, avs2d_len_align);
 
-    {
-        // report hw_info to parser
-        const MppSocInfo *info = mpp_get_soc_info();
-        const void *hw_info = NULL;
-
-        for (i = 0; i < MPP_ARRAY_ELEMS(info->dec_caps); i++) {
-            if (info->dec_caps[i] && info->dec_caps[i]->type == VPU_CLIENT_RKVDEC) {
-                hw_info = info->dec_caps[i];
-                break;
-            }
-        }
-
-        mpp_assert(hw_info);
-        cfg->hw_info = hw_info;
-    }
-
 __RETURN:
     AVS2D_HAL_TRACE("Out. ret %d", ret);
     (void)cfg;
@@ -585,29 +568,12 @@ static MPP_RET set_up_colmv_buf(void *hal)
     Avs2dSyntax_t *syntax = &p_hal->syntax;
     PicParams_Avs2d *pp   = &syntax->pp;
     RK_U32 mv_size = 0;
-
     RK_U32 ctu_size = 1 << (p_hal->syntax.pp.lcu_size);
-    RK_U32 segment_w = 64 * COLMV_BLOCK_SIZE * COLMV_BLOCK_SIZE / ctu_size;
-    RK_U32 segment_h = ctu_size;
-    RK_U32 pic_w_align = MPP_ALIGN(pp->pic_width_in_luma_samples, segment_w);
-    RK_U32 pic_h_align = MPP_ALIGN(pp->pic_height_in_luma_samples, segment_h);
-    RK_U32 seg_cnt_w = pic_w_align / segment_w;
-    RK_U32 seg_cnt_h = pic_h_align / segment_h;
-    RK_U32 seg_head_line_size = MPP_ALIGN(seg_cnt_w, 16);
-    RK_U32 seg_head_size = seg_head_line_size * seg_cnt_h;
-    RK_U32 seg_payload_size = seg_cnt_w * seg_cnt_h * 64 * COLMV_BYTES;
-
-    if (COLMV_COMPRESS_EN)
-        mv_size = seg_payload_size + seg_head_size;
-    else
-        mv_size = (MPP_ALIGN(p_hal->syntax.pp.pic_width_in_luma_samples, 64) *
-                   MPP_ALIGN(p_hal->syntax.pp.pic_height_in_luma_samples, 64)) >> 5;
-
-    // colmv frame size align to 128byte
-    if ((mv_size / 8) % 2 == 1) {
-        mv_size += 8;
-    }
+    RK_U32 width = p_hal->syntax.pp.pic_width_in_luma_samples;
+    RK_U32 height = p_hal->syntax.pp.pic_height_in_luma_samples;
 
+    mv_size = vdpu34x_get_colmv_size(width, height, ctu_size, COLMV_BYTES,
+                                     COLMV_BLOCK_SIZE, COLMV_COMPRESS_EN);
     if (pp->field_coded_sequence)
         mv_size *= 2;
     AVS2D_HAL_TRACE("mv_size %d", mv_size);
@@ -1118,6 +1084,7 @@ MPP_RET hal_avs2d_rkv_wait(void *hal, HalTaskInfo *task)
             param.hard_err = 0;
 
         task->dec.flags.ref_used = p_regs->statistic.reg266_perf_cnt0;
+        task->dec.flags.ref_info_valid = 1;
 
         if (task->dec.flags.ref_miss) {
             RK_U32 ref_hw_usage = p_regs->statistic.reg266_perf_cnt0;
@@ -1140,3 +1107,19 @@ MPP_RET hal_avs2d_rkv_wait(void *hal, HalTaskInfo *task)
     AVS2D_HAL_TRACE("Out. ret %d", ret);
     return ret;
 }
+
+const MppHalApi hal_avs2d_rkvdpu = {
+    .name     = "avs2d_rkvdpu",
+    .type     = MPP_CTX_DEC,
+    .coding   = MPP_VIDEO_CodingAVS2,
+    .ctx_size = sizeof(Avs2dRkvRegCtx_t),
+    .flag     = 0,
+    .init     = hal_avs2d_rkv_init,
+    .deinit   = hal_avs2d_rkv_deinit,
+    .reg_gen  = hal_avs2d_rkv_gen_regs,
+    .start    = hal_avs2d_rkv_start,
+    .wait     = hal_avs2d_rkv_wait,
+    .reset    = NULL,
+    .flush    = NULL,
+    .control  = NULL,
+};
diff --git a/mpp/hal/rkdec/avs2d/hal_avs2d_rkv.h b/mpp/hal/rkdec/avs2d/hal_avs2d_rkv.h
index 4c958932d..b207007b1 100644
--- a/mpp/hal/rkdec/avs2d/hal_avs2d_rkv.h
+++ b/mpp/hal/rkdec/avs2d/hal_avs2d_rkv.h
@@ -31,11 +31,7 @@
 extern "C" {
 #endif
 
-MPP_RET hal_avs2d_rkv_init    (void *hal, MppHalCfg *cfg);
-MPP_RET hal_avs2d_rkv_deinit  (void *hal);
-MPP_RET hal_avs2d_rkv_gen_regs(void *hal, HalTaskInfo *task);
-MPP_RET hal_avs2d_rkv_start   (void *hal, HalTaskInfo *task);
-MPP_RET hal_avs2d_rkv_wait    (void *hal, HalTaskInfo *task);
+extern const MppHalApi hal_avs2d_rkvdpu;
 
 #ifdef  __cplusplus
 }
diff --git a/mpp/hal/rkdec/avs2d/hal_avs2d_vdpu382.c b/mpp/hal/rkdec/avs2d/hal_avs2d_vdpu382.c
index a52ba5be0..3bee7808e 100644
--- a/mpp/hal/rkdec/avs2d/hal_avs2d_vdpu382.c
+++ b/mpp/hal/rkdec/avs2d/hal_avs2d_vdpu382.c
@@ -30,7 +30,6 @@
 #include "hal_avs2d_vdpu382.h"
 #include "mpp_dec_cb_param.h"
 #include "vdpu382_avs2d.h"
-#include "rk_hdr_meta_com.h"
 
 #define VDPU382_FAST_REG_SET_CNT    (3)
 #define MAX_REF_NUM                 (8)
@@ -79,6 +78,7 @@ typedef struct avs2d_reg_ctx_t {
 
 } Avs2dVdpu382RegCtx_t;
 
+MPP_RET hal_avs2d_vdpu382_deinit(void *hal);
 static RK_U32 avs2d_ver_align(RK_U32 val)
 {
     return MPP_ALIGN(val, 16);
@@ -459,7 +459,7 @@ static MPP_RET fill_registers(Avs2dHalCtx_t *p_hal, Vdpu382Avs2dRegSet *p_regs,
         for (i = 0; i < refp->ref_pic_num; i++) {
             MppFrame frame_ref = NULL;
 
-            RK_S32 slot_idx = task_dec->refer[i] < 0 ? valid_slot : task_dec->refer[i];
+            RK_S32 slot_idx = task_dec->refer[i] < 0 ? task_dec->refer[valid_slot] : task_dec->refer[i];
 
             if (slot_idx < 0) {
                 AVS2D_HAL_DBG(AVS2D_HAL_DBG_ERROR, "missing ref, could not found valid ref");
@@ -523,9 +523,6 @@ static MPP_RET fill_registers(Avs2dHalCtx_t *p_hal, Vdpu382Avs2dRegSet *p_regs,
         common->reg016_str_len = MPP_ALIGN(mpp_packet_get_length(task_dec->input_packet), 16) + 64;
     }
 
-    if (MPP_FRAME_FMT_IS_HDR(mpp_frame_get_fmt(mframe)) && p_hal->cfg->base.enable_hdr_meta)
-        fill_hdr_meta_to_frame(mframe, HDR_AVS2);
-
     /* set scale down info */
     if (mpp_frame_get_thumbnail_en(mframe)) {
         p_regs->avs2d_addr.scale_down_luma_base = p_regs->common_addr.reg130_decout_base;
@@ -621,23 +618,6 @@ MPP_RET hal_avs2d_vdpu382_init(void *hal, MppHalCfg *cfg)
     mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, avs2d_ver_align);
     mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, avs2d_len_align);
 
-    {
-        // report hw_info to parser
-        const MppSocInfo *info = mpp_get_soc_info();
-        const void *hw_info = NULL;
-
-        for (i = 0; i < MPP_ARRAY_ELEMS(info->dec_caps); i++) {
-            if (info->dec_caps[i] && info->dec_caps[i]->type == VPU_CLIENT_RKVDEC) {
-                hw_info = info->dec_caps[i];
-                break;
-            }
-        }
-
-        mpp_assert(hw_info);
-        cfg->hw_info = hw_info;
-        p_hal->hw_info = hw_info;
-    }
-
 __RETURN:
     AVS2D_HAL_TRACE("Out. ret %d", ret);
     (void)cfg;
@@ -655,29 +635,12 @@ static MPP_RET set_up_colmv_buf(void *hal)
     Avs2dSyntax_t *syntax = &p_hal->syntax;
     PicParams_Avs2d *pp   = &syntax->pp;
     RK_U32 mv_size = 0;
-
     RK_U32 ctu_size = 1 << (p_hal->syntax.pp.lcu_size);
-    RK_U32 segment_w = 64 * COLMV_BLOCK_SIZE * COLMV_BLOCK_SIZE / ctu_size;
-    RK_U32 segment_h = ctu_size;
-    RK_U32 pic_w_align = MPP_ALIGN(pp->pic_width_in_luma_samples, segment_w);
-    RK_U32 pic_h_align = MPP_ALIGN(pp->pic_height_in_luma_samples, segment_h);
-    RK_U32 seg_cnt_w = pic_w_align / segment_w;
-    RK_U32 seg_cnt_h = pic_h_align / segment_h;
-    RK_U32 seg_head_line_size = MPP_ALIGN(seg_cnt_w, 16);
-    RK_U32 seg_head_size = seg_head_line_size * seg_cnt_h;
-    RK_U32 seg_payload_size = seg_cnt_w * seg_cnt_h * 64 * COLMV_BYTES;
-
-    if (COLMV_COMPRESS_EN)
-        mv_size = seg_payload_size + seg_head_size;
-    else
-        mv_size = (MPP_ALIGN(p_hal->syntax.pp.pic_width_in_luma_samples, 64) *
-                   MPP_ALIGN(p_hal->syntax.pp.pic_height_in_luma_samples, 64)) >> 5;
-
-    // colmv frame size align to 128byte
-    if ((mv_size / 8) % 2 == 1) {
-        mv_size += 8;
-    }
+    RK_U32 width = p_hal->syntax.pp.pic_width_in_luma_samples;
+    RK_U32 height = p_hal->syntax.pp.pic_height_in_luma_samples;
 
+    mv_size = vdpu382_get_colmv_size(width, height, ctu_size, COLMV_BYTES,
+                                     COLMV_BLOCK_SIZE, COLMV_COMPRESS_EN);
     if (pp->field_coded_sequence)
         mv_size *= 2;
     AVS2D_HAL_TRACE("mv_size %d", mv_size);
@@ -1187,6 +1150,7 @@ MPP_RET hal_avs2d_vdpu382_wait(void *hal, HalTaskInfo *task)
             param.hard_err = 0;
 
         task->dec.flags.ref_used = p_regs->statistic.reg265.link_perf_cnt0;
+        task->dec.flags.ref_info_valid = 1;
 
         if (task->dec.flags.ref_miss) {
             RK_U32 ref_hw_usage = p_regs->statistic.reg265.link_perf_cnt0;
@@ -1209,3 +1173,19 @@ MPP_RET hal_avs2d_vdpu382_wait(void *hal, HalTaskInfo *task)
     AVS2D_HAL_TRACE("Out. ret %d", ret);
     return ret;
 }
+
+const MppHalApi hal_avs2d_vdpu382 = {
+    .name     = "avs2d_vdpu382",
+    .type     = MPP_CTX_DEC,
+    .coding   = MPP_VIDEO_CodingAVS2,
+    .ctx_size = sizeof(Avs2dVdpu382RegCtx_t),
+    .flag     = 0,
+    .init     = hal_avs2d_vdpu382_init,
+    .deinit   = hal_avs2d_vdpu382_deinit,
+    .reg_gen  = hal_avs2d_vdpu382_gen_regs,
+    .start    = hal_avs2d_vdpu382_start,
+    .wait     = hal_avs2d_vdpu382_wait,
+    .reset    = NULL,
+    .flush    = NULL,
+    .control  = NULL,
+};
diff --git a/mpp/hal/rkdec/avs2d/hal_avs2d_vdpu382.h b/mpp/hal/rkdec/avs2d/hal_avs2d_vdpu382.h
index 0cddfc2a7..d40393758 100644
--- a/mpp/hal/rkdec/avs2d/hal_avs2d_vdpu382.h
+++ b/mpp/hal/rkdec/avs2d/hal_avs2d_vdpu382.h
@@ -31,11 +31,7 @@
 extern "C" {
 #endif
 
-MPP_RET hal_avs2d_vdpu382_init    (void *hal, MppHalCfg *cfg);
-MPP_RET hal_avs2d_vdpu382_deinit  (void *hal);
-MPP_RET hal_avs2d_vdpu382_gen_regs(void *hal, HalTaskInfo *task);
-MPP_RET hal_avs2d_vdpu382_start   (void *hal, HalTaskInfo *task);
-MPP_RET hal_avs2d_vdpu382_wait    (void *hal, HalTaskInfo *task);
+extern const MppHalApi hal_avs2d_vdpu382;
 
 #ifdef  __cplusplus
 }
diff --git a/mpp/hal/rkdec/avs2d/hal_avs2d_vdpu383.c b/mpp/hal/rkdec/avs2d/hal_avs2d_vdpu383.c
new file mode 100644
index 000000000..f204c9716
--- /dev/null
+++ b/mpp/hal/rkdec/avs2d/hal_avs2d_vdpu383.c
@@ -0,0 +1,946 @@
+/* SPDX-License-Identifier: Apache-2.0 OR MIT */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#define MODULE_TAG "hal_avs2d_vdpu383"
+
+#include <string.h>
+#include <stdio.h>
+
+#include "mpp_env.h"
+#include "mpp_log.h"
+#include "mpp_mem.h"
+#include "mpp_common.h"
+#include "mpp_debug.h"
+#include "mpp_bitput.h"
+#include "mpp_buffer_impl.h"
+
+#include "avs2d_syntax.h"
+#include "vdpu383_com.h"
+#include "vdpu383_avs2d.h"
+#include "hal_avs2d_global.h"
+#include "hal_avs2d_vdpu383.h"
+#include "mpp_dec_cb_param.h"
+
+#define VDPU383_FAST_REG_SET_CNT    (3)
+#define MAX_REF_NUM                 (8)
+#define AVS2_383_SHPH_SIZE          (208)            /* bytes */
+#define AVS2_383_SCALIST_SIZE       (80)             /* bytes */
+#define VDPU34x_TOTAL_REG_CNT       (278)
+
+#define AVS2_383_SHPH_ALIGNED_SIZE          (MPP_ALIGN(AVS2_383_SHPH_SIZE, SZ_4K))
+#define AVS2_383_SCALIST_ALIGNED_SIZE       (MPP_ALIGN(AVS2_383_SCALIST_SIZE, SZ_4K))
+#define AVS2_383_STREAM_INFO_SET_SIZE       (AVS2_383_SHPH_ALIGNED_SIZE + \
+                                            AVS2_383_SCALIST_ALIGNED_SIZE)
+#define AVS2_ALL_TBL_BUF_SIZE(cnt)          (AVS2_383_STREAM_INFO_SET_SIZE * (cnt))
+#define AVS2_SHPH_OFFSET(pos)               (AVS2_383_STREAM_INFO_SET_SIZE * (pos))
+#define AVS2_SCALIST_OFFSET(pos)            (AVS2_SHPH_OFFSET(pos) + AVS2_383_SHPH_ALIGNED_SIZE)
+
+#define COLMV_COMPRESS_EN       (1)
+#define COLMV_BLOCK_SIZE        (16)
+#define COLMV_BYTES             (16)
+
+typedef struct avs2d_buf_t {
+    RK_U32                  valid;
+    RK_U32                  offset_shph;
+    RK_U32                  offset_sclst;
+    Vdpu383Avs2dRegSet      *regs;
+} Avs2dRkvBuf_t;
+
+typedef struct avs2d_reg_ctx_t {
+    Avs2dRkvBuf_t           reg_buf[VDPU383_FAST_REG_SET_CNT];
+
+    RK_U32                  shph_offset;
+    RK_U32                  sclst_offset;
+
+    Vdpu383Avs2dRegSet      *regs;
+
+    RK_U8                   shph_dat[AVS2_383_SHPH_SIZE];
+    RK_U8                   scalist_dat[AVS2_383_SCALIST_SIZE];
+
+    MppBuffer               bufs;
+    RK_S32                  bufs_fd;
+    void                    *bufs_ptr;
+
+    MppBuffer               rcb_buf[VDPU383_FAST_REG_SET_CNT];
+    RK_S32                  rcb_buf_size;
+    Vdpu383RcbInfo          rcb_info[RCB_BUF_COUNT];
+    RK_U32                  reg_out[VDPU34x_TOTAL_REG_CNT];
+
+} Avs2dRkvRegCtx_t;
+
+MPP_RET hal_avs2d_vdpu383_deinit(void *hal);
+static RK_U32 avs2d_ver_align(RK_U32 val)
+{
+    return MPP_ALIGN(val, 16);
+}
+
+static RK_U32 avs2d_len_align(RK_U32 val)
+{
+    return (2 * MPP_ALIGN(val, 16));
+}
+
+static MPP_RET prepare_header(Avs2dHalCtx_t *p_hal, RK_U8 *data, RK_U32 len)
+{
+    RK_U32 i, j;
+    BitputCtx_t bp;
+    RK_U64 *bit_buf = (RK_U64 *)data;
+    Avs2dSyntax_t *syntax = &p_hal->syntax;
+    PicParams_Avs2d *pp   = &syntax->pp;
+    AlfParams_Avs2d *alfp = &syntax->alfp;
+    RefParams_Avs2d *refp = &syntax->refp;
+    WqmParams_Avs2d *wqmp = &syntax->wqmp;
+
+    memset(data, 0, len);
+
+    mpp_set_bitput_ctx(&bp, bit_buf, len);
+
+    //!< sequence header syntax
+    mpp_put_bits(&bp, pp->chroma_format_idc, 2);
+    mpp_put_bits(&bp, pp->pic_width_in_luma_samples, 16);
+    mpp_put_bits(&bp, pp->pic_height_in_luma_samples, 16);
+    mpp_put_bits(&bp, pp->bit_depth_luma_minus8, 3);
+    mpp_put_bits(&bp, pp->bit_depth_chroma_minus8, 3);
+    mpp_put_bits(&bp, pp->lcu_size, 3);
+    mpp_put_bits(&bp, pp->progressive_sequence, 1);
+    mpp_put_bits(&bp, pp->field_coded_sequence, 1);
+
+    mpp_put_bits(&bp, pp->secondary_transform_enable_flag, 1);
+    mpp_put_bits(&bp, pp->sample_adaptive_offset_enable_flag, 1);
+    mpp_put_bits(&bp, pp->adaptive_loop_filter_enable_flag, 1);
+    mpp_put_bits(&bp, pp->pmvr_enable_flag, 1);
+    mpp_put_bits(&bp, pp->cross_slice_loopfilter_enable_flag, 1);
+
+    //!< picture header syntax
+    mpp_put_bits(&bp, pp->picture_type, 3);
+    mpp_put_bits(&bp, refp->ref_pic_num, 3);
+    mpp_put_bits(&bp, pp->scene_reference_enable_flag, 1);
+    mpp_put_bits(&bp, pp->bottom_field_picture_flag, 1);
+    mpp_put_bits(&bp, pp->fixed_picture_qp, 1);
+    mpp_put_bits(&bp, pp->picture_qp, 7);
+    mpp_put_bits(&bp, pp->loop_filter_disable_flag, 1);
+    mpp_put_bits(&bp, pp->alpha_c_offset, 5);
+    mpp_put_bits(&bp, pp->beta_offset, 5);
+
+    //!< weight quant param
+    mpp_put_bits(&bp, wqmp->chroma_quant_param_delta_cb, 6);
+    mpp_put_bits(&bp, wqmp->chroma_quant_param_delta_cr, 6);
+    mpp_put_bits(&bp, wqmp->pic_weight_quant_enable_flag, 1);
+
+    //!< alf param
+    mpp_put_bits(&bp, alfp->enable_pic_alf_y, 1);
+    mpp_put_bits(&bp, alfp->enable_pic_alf_cb, 1);
+    mpp_put_bits(&bp, alfp->enable_pic_alf_cr, 1);
+
+    mpp_put_bits(&bp, alfp->alf_filter_num_minus1, 4);
+    for (i = 0; i < 16; i++)
+        mpp_put_bits(&bp, alfp->alf_coeff_idx_tab[i], 4);
+
+    for (i = 0; i < 16; i++)
+        for (j = 0; j < 9; j++)
+            mpp_put_bits(&bp, alfp->alf_coeff_y[i][j], 7);
+
+    for (j = 0; j < 9; j++)
+        mpp_put_bits(&bp, alfp->alf_coeff_cb[j], 7);
+
+    for (j = 0; j < 9; j++)
+        mpp_put_bits(&bp, alfp->alf_coeff_cr[j], 7);
+
+    /* other flags */
+    mpp_put_bits(&bp, pp->multi_hypothesis_skip_enable_flag, 1);
+    mpp_put_bits(&bp, pp->dual_hypothesis_prediction_enable_flag, 1);
+    mpp_put_bits(&bp, pp->weighted_skip_enable_flag, 1);
+    mpp_put_bits(&bp, pp->asymmetrc_motion_partitions_enable_flag, 1);
+    mpp_put_bits(&bp, pp->nonsquare_quadtree_transform_enable_flag, 1);
+    mpp_put_bits(&bp, pp->nonsquare_intra_prediction_enable_flag, 1);
+
+    //!< picture reference params
+    mpp_put_bits(&bp, pp->cur_poc, 32);
+    for (i = 0; i < 8; i++)
+        mpp_put_bits(&bp, (i < refp->ref_pic_num) ? refp->ref_poc_list[i] : 0, 32);
+    for (i = 0; i < 8; i++)
+        mpp_put_bits(&bp, (i < refp->ref_pic_num) ? pp->field_coded_sequence : 0, 1);
+    for (i = 0; i < 8; i++)
+        mpp_put_bits(&bp, (i < refp->ref_pic_num) ? pp->bottom_field_picture_flag : 0, 1);
+    for (i = 0; i < 8; i++)
+        mpp_put_bits(&bp, (i < refp->ref_pic_num), 1);
+
+    return MPP_OK;
+}
+
+static MPP_RET prepare_scalist(Avs2dHalCtx_t *p_hal, RK_U8 *data, RK_U32 len)
+{
+    Avs2dSyntax_t *syntax = &p_hal->syntax;
+    WqmParams_Avs2d *wqmp = &syntax->wqmp;
+    RK_U32 i = 0;
+    RK_U32 n = 0;
+
+    if (!wqmp->pic_weight_quant_enable_flag)
+        return MPP_OK;
+
+    memset(data, 0, len);
+
+    /* dump by block4x4, vectial direction */
+    for (i = 0; i < 4; i++) {
+        data[n++] = wqmp->wq_matrix[0][i + 0];
+        data[n++] = wqmp->wq_matrix[0][i + 4];
+        data[n++] = wqmp->wq_matrix[0][i + 8];
+        data[n++] = wqmp->wq_matrix[0][i + 12];
+    }
+
+    /* block8x8 */
+    {
+        RK_S32 blk4_x = 0, blk4_y = 0;
+
+        /* dump by block4x4, vectial direction */
+        for (blk4_x = 0; blk4_x < 8; blk4_x += 4) {
+            for (blk4_y = 0; blk4_y < 8; blk4_y += 4) {
+                RK_S32 pos = blk4_y * 8 + blk4_x;
+
+                for (i = 0; i < 4; i++) {
+                    data[n++] = wqmp->wq_matrix[1][pos + i + 0];
+                    data[n++] = wqmp->wq_matrix[1][pos + i + 8];
+                    data[n++] = wqmp->wq_matrix[1][pos + i + 16];
+                    data[n++] = wqmp->wq_matrix[1][pos + i + 24];
+                }
+            }
+        }
+    }
+
+    return MPP_OK;
+}
+
+static RK_S32 get_frame_fd(Avs2dHalCtx_t *p_hal, RK_S32 idx)
+{
+    RK_S32 ret_fd = 0;
+    MppBuffer mbuffer = NULL;
+
+    mpp_buf_slot_get_prop(p_hal->frame_slots, idx, SLOT_BUFFER, &mbuffer);
+    ret_fd = mpp_buffer_get_fd(mbuffer);
+
+    return ret_fd;
+}
+
+static RK_S32 get_packet_fd(Avs2dHalCtx_t *p_hal, RK_S32 idx)
+{
+    RK_S32 ret_fd = 0;
+    MppBuffer mbuffer = NULL;
+
+    mpp_buf_slot_get_prop(p_hal->packet_slots, idx, SLOT_BUFFER, &mbuffer);
+    ret_fd =  mpp_buffer_get_fd(mbuffer);
+
+    return ret_fd;
+}
+
+static void init_ctrl_regs(Vdpu383Avs2dRegSet *regs)
+{
+    Vdpu383CtrlReg *ctrl_regs = &regs->ctrl_regs;
+
+    ctrl_regs->reg8_dec_mode = 3;  // AVS2
+    ctrl_regs->reg9.buf_empty_en = 1;
+
+    ctrl_regs->reg10.strmd_auto_gating_e      = 1;
+    ctrl_regs->reg10.inter_auto_gating_e      = 1;
+    ctrl_regs->reg10.intra_auto_gating_e      = 1;
+    ctrl_regs->reg10.transd_auto_gating_e     = 1;
+    ctrl_regs->reg10.recon_auto_gating_e      = 1;
+    ctrl_regs->reg10.filterd_auto_gating_e    = 1;
+    ctrl_regs->reg10.bus_auto_gating_e        = 1;
+    ctrl_regs->reg10.ctrl_auto_gating_e       = 1;
+    ctrl_regs->reg10.rcb_auto_gating_e        = 1;
+    ctrl_regs->reg10.err_prc_auto_gating_e    = 1;
+
+    ctrl_regs->reg13_core_timeout_threshold = 0xffffff;
+
+    ctrl_regs->reg16.error_proc_disable = 1;
+    ctrl_regs->reg16.error_spread_disable = 0;
+    ctrl_regs->reg16.roi_error_ctu_cal_en = 0;
+
+    ctrl_regs->reg20_cabac_error_en_lowbits = 0xffffffff;
+    ctrl_regs->reg21_cabac_error_en_highbits = 0x3fffffff;
+
+    /* performance */
+    ctrl_regs->reg28.axi_perf_work_e = 1;
+    ctrl_regs->reg28.axi_cnt_type = 1;
+    ctrl_regs->reg28.rd_latency_id = 0xb;
+    ctrl_regs->reg28.rd_latency_thr = 0;
+
+    ctrl_regs->reg29.addr_align_type = 2;
+    ctrl_regs->reg29.ar_cnt_id_type = 0;
+    ctrl_regs->reg29.aw_cnt_id_type = 0;
+    ctrl_regs->reg29.ar_count_id = 0xa;
+    ctrl_regs->reg29.aw_count_id = 0;
+    ctrl_regs->reg29.rd_band_width_mode = 0;
+}
+
+static void avs2d_refine_rcb_size(Vdpu383RcbInfo *rcb_info,
+                                  RK_S32 width, RK_S32 height, void *dxva)
+{
+    (void) height;
+    Avs2dSyntax_t *syntax = dxva;
+    RK_U8 ctu_size = 1 << syntax->pp.lcu_size;
+    RK_U8 bit_depth = syntax->pp.bit_depth_chroma_minus8 + 8;
+    RK_U32 rcb_bits = 0;
+    RK_U32 filterd_row_append = 8192;
+
+    width = MPP_ALIGN(width, ctu_size);
+
+    /* RCB_STRMD_ROW && RCB_STRMD_TILE_ROW*/
+    if (width > 8192)
+        rcb_bits = ((width + 63) / 64) * 112;
+    else
+        rcb_bits = 0;
+    rcb_info[RCB_STRMD_ROW].size = MPP_RCB_BYTES(rcb_bits);
+    rcb_info[RCB_STRMD_TILE_ROW].size = 0;
+
+    /* RCB_INTER_ROW && RCB_INTER_TILE_ROW*/
+    rcb_bits = ((width + 7) / 8) * 166;
+    rcb_info[RCB_INTER_ROW].size = MPP_RCB_BYTES(rcb_bits);
+    rcb_info[RCB_INTER_TILE_ROW].size = 0;
+
+    /* RCB_INTRA_ROW && RCB_INTRA_TILE_ROW*/
+    rcb_bits = MPP_ALIGN(width, 512) * (bit_depth + 2);
+    rcb_bits = rcb_bits * 3; //TODO:
+    rcb_info[RCB_INTRA_ROW].size = MPP_RCB_BYTES(rcb_bits);
+    rcb_info[RCB_INTRA_TILE_ROW].size = 0;
+
+    /* RCB_FILTERD_ROW && RCB_FILTERD_TILE_ROW*/
+    if (width > 4096)
+        filterd_row_append = 27648;
+    rcb_bits = MPP_ALIGN(width, 64) * (30 * bit_depth + 9);
+    rcb_info[RCB_FILTERD_ROW].size = MPP_RCB_BYTES(rcb_bits / 2);
+    rcb_info[RCB_FILTERD_PROTECT_ROW].size = filterd_row_append + MPP_RCB_BYTES(rcb_bits / 2);
+    rcb_info[RCB_FILTERD_TILE_ROW].size = 0;
+
+    /* RCB_FILTERD_TILE_COL */
+    rcb_info[RCB_FILTERD_TILE_COL].size = 0;
+}
+
+static void hal_avs2d_rcb_info_update(void *hal, Vdpu383Avs2dRegSet *regs)
+{
+    MPP_RET ret = MPP_OK;
+    Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
+    Avs2dRkvRegCtx_t *reg_ctx = (Avs2dRkvRegCtx_t *)p_hal->reg_ctx;
+    RK_S32 width = p_hal->syntax.pp.pic_width_in_luma_samples;
+    RK_S32 height = p_hal->syntax.pp.pic_height_in_luma_samples;
+    RK_S32 i = 0;
+    RK_S32 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1;
+
+    (void) regs;
+
+    reg_ctx->rcb_buf_size = vdpu383_get_rcb_buf_size(reg_ctx->rcb_info, width, height);
+    avs2d_refine_rcb_size(reg_ctx->rcb_info, width, height, (void *)&p_hal->syntax);
+
+    for (i = 0; i < loop; i++) {
+        MppBuffer rcb_buf = NULL;
+
+        if (reg_ctx->rcb_buf[i]) {
+            mpp_buffer_put(reg_ctx->rcb_buf[i]);
+            reg_ctx->rcb_buf[i] = NULL;
+        }
+
+        ret = mpp_buffer_get(p_hal->buf_group, &rcb_buf, reg_ctx->rcb_buf_size);
+        if (ret)
+            mpp_err_f("AVS2D mpp_buffer_group_get failed\n");
+
+        reg_ctx->rcb_buf[i] = rcb_buf;
+    }
+}
+
+static MPP_RET fill_registers(Avs2dHalCtx_t *p_hal, Vdpu383Avs2dRegSet *regs, HalTaskInfo *task)
+{
+    MPP_RET ret = MPP_OK;
+    RK_U32 i;
+    MppFrame mframe = NULL;
+    Avs2dSyntax_t *syntax = &p_hal->syntax;
+    RefParams_Avs2d *refp = &syntax->refp;
+    HalDecTask *task_dec  = &task->dec;
+
+    RK_U32 is_fbc = 0;
+    RK_U32 is_tile = 0;
+    HalBuf *mv_buf = NULL;
+
+    mpp_buf_slot_get_prop(p_hal->frame_slots, task_dec->output, SLOT_FRAME_PTR, &mframe);
+    is_fbc = MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(mframe));
+    is_tile = MPP_FRAME_FMT_IS_TILE(mpp_frame_get_fmt(mframe));
+
+    //!< caculate the yuv_frame_size
+    {
+        RK_U32 hor_virstride = 0;
+        RK_U32 ver_virstride = 0;
+        RK_U32 y_virstride = 0;
+        RK_U32 uv_virstride = 0;
+
+        hor_virstride = mpp_frame_get_hor_stride(mframe);
+        ver_virstride = mpp_frame_get_ver_stride(mframe);
+        y_virstride = hor_virstride * ver_virstride;
+        uv_virstride = hor_virstride * ver_virstride / 2;
+        AVS2D_HAL_TRACE("is_fbc %d y_virstride %d, hor_virstride %d, ver_virstride %d\n",
+                        is_fbc, y_virstride, hor_virstride, ver_virstride);
+
+        if (is_fbc) {
+            RK_U32 pixel_width = MPP_ALIGN(mpp_frame_get_width(mframe), 64);
+            RK_U32 fbd_offset;
+
+            regs->ctrl_regs.reg9.fbc_e = 1;
+            regs->avs2d_paras.reg68_hor_virstride = pixel_width / 64;
+            fbd_offset = regs->avs2d_paras.reg68_hor_virstride * MPP_ALIGN(ver_virstride, 64) * 4;
+            regs->avs2d_addrs.reg193_fbc_payload_offset = fbd_offset;
+        } else if (is_tile) {
+            regs->ctrl_regs.reg9.tile_e = 1;
+            regs->avs2d_paras.reg68_hor_virstride = hor_virstride * 6 / 16;
+            regs->avs2d_paras.reg70_y_virstride = (y_virstride + uv_virstride) / 16;
+        } else {
+            regs->ctrl_regs.reg9.fbc_e = 0;
+            regs->ctrl_regs.reg9.tile_e = 0;
+            regs->avs2d_paras.reg68_hor_virstride = hor_virstride / 16;
+            regs->avs2d_paras.reg69_raster_uv_hor_virstride = hor_virstride / 16;
+            regs->avs2d_paras.reg70_y_virstride = y_virstride / 16;
+        }
+    }
+
+    // set current
+    {
+        RK_S32 fd = get_frame_fd(p_hal, task_dec->output);
+
+        mpp_assert(fd >= 0);
+
+        regs->avs2d_addrs.reg168_decout_base = fd;
+        regs->avs2d_addrs.reg192_payload_st_cur_base = fd;
+        mv_buf = hal_bufs_get_buf(p_hal->cmv_bufs, task_dec->output);
+        regs->avs2d_addrs.reg216_colmv_cur_base = mpp_buffer_get_fd(mv_buf->buf[0]);
+        AVS2D_HAL_TRACE("cur frame index %d, fd %d, colmv fd %d", task_dec->output, fd, regs->avs2d_addrs.reg216_colmv_cur_base);
+
+        // TODO: set up error_ref_base
+        // regs->avs2d_addr.reg169_err_ref_base.base = regs->avs2d_addr.reg216_colmv_cur_base.base;
+    }
+
+    // set reference
+    {
+        RK_S32 valid_slot = -1;
+
+        AVS2D_HAL_TRACE("num of ref %d", refp->ref_pic_num);
+
+        for (i = 0; i < refp->ref_pic_num; i++) {
+            if (task_dec->refer[i] < 0)
+                continue;
+
+            valid_slot = i;
+            break;
+        }
+
+        for (i = 0; i < MAX_REF_NUM; i++) {
+            if (i < refp->ref_pic_num) {
+                MppFrame frame_ref = NULL;
+
+                RK_S32 slot_idx = task_dec->refer[i] < 0 ? task_dec->refer[valid_slot] : task_dec->refer[i];
+
+                if (slot_idx < 0) {
+                    AVS2D_HAL_TRACE("missing ref, could not found valid ref");
+                    task->dec.flags.ref_err = 1;
+                    return ret = MPP_ERR_UNKNOW;
+                }
+
+                mpp_buf_slot_get_prop(p_hal->frame_slots, slot_idx, SLOT_FRAME_PTR, &frame_ref);
+
+                if (frame_ref) {
+                    regs->avs2d_addrs.reg170_185_ref_base[i] = get_frame_fd(p_hal, slot_idx);
+                    regs->avs2d_addrs.reg195_210_payload_st_ref_base[i] = get_frame_fd(p_hal, slot_idx);
+                    mv_buf = hal_bufs_get_buf(p_hal->cmv_bufs, slot_idx);
+                    regs->avs2d_addrs.reg217_232_colmv_ref_base[i] = mpp_buffer_get_fd(mv_buf->buf[0]);
+                }
+            }
+        }
+
+        regs->avs2d_addrs.reg169_error_ref_base = regs->avs2d_addrs.reg170_185_ref_base[0];
+        regs->avs2d_addrs.reg194_payload_st_error_ref_base = regs->avs2d_addrs.reg195_210_payload_st_ref_base[0];
+    }
+
+    // set rlc
+    regs->common_addr.reg128_strm_base = get_packet_fd(p_hal, task_dec->input);
+    AVS2D_HAL_TRACE("packet fd %d from slot %d", regs->common_addr.reg128_strm_base, task_dec->input);
+
+    regs->avs2d_paras.reg66_stream_len = MPP_ALIGN(mpp_packet_get_length(task_dec->input_packet), 16) + 64;
+
+    {
+        //scale down config
+        mpp_buf_slot_get_prop(p_hal->frame_slots, task_dec->output,
+                              SLOT_FRAME_PTR, &mframe);
+        if (mpp_frame_get_thumbnail_en(mframe)) {
+            regs->common_addr.reg133_scale_down_base = regs->avs2d_addrs.reg168_decout_base;
+            vdpu383_setup_down_scale(mframe, p_hal->dev, &regs->ctrl_regs,
+                                     (void *)&regs->avs2d_paras);
+        } else {
+            regs->ctrl_regs.reg9.scale_down_en = 0;
+        }
+    }
+
+    return ret;
+}
+
+MPP_RET hal_avs2d_vdpu383_deinit(void *hal)
+{
+    MPP_RET ret = MPP_OK;
+    RK_U32 i, loop;
+    Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
+    Avs2dRkvRegCtx_t *reg_ctx = (Avs2dRkvRegCtx_t *)p_hal->reg_ctx;
+
+    AVS2D_HAL_TRACE("In.");
+
+    INP_CHECK(ret, NULL == reg_ctx);
+
+    //!< malloc buffers
+    loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1;
+    for (i = 0; i < loop; i++) {
+        if (reg_ctx->rcb_buf[i]) {
+            mpp_buffer_put(reg_ctx->rcb_buf[i]);
+            reg_ctx->rcb_buf[i] = NULL;
+        }
+
+        MPP_FREE(reg_ctx->reg_buf[i].regs);
+    }
+
+    if (reg_ctx->bufs) {
+        mpp_buffer_put(reg_ctx->bufs);
+        reg_ctx->bufs = NULL;
+    }
+
+    if (p_hal->cmv_bufs) {
+        hal_bufs_deinit(p_hal->cmv_bufs);
+        p_hal->cmv_bufs = NULL;
+    }
+
+    MPP_FREE(p_hal->reg_ctx);
+
+__RETURN:
+    AVS2D_HAL_TRACE("Out. ret %d", ret);
+    return ret;
+}
+
+MPP_RET hal_avs2d_vdpu383_init(void *hal, MppHalCfg *cfg)
+{
+    MPP_RET ret = MPP_OK;
+    RK_U32 i, loop;
+    Avs2dRkvRegCtx_t *reg_ctx;
+    Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
+
+    AVS2D_HAL_TRACE("In.");
+
+    INP_CHECK(ret, NULL == p_hal);
+
+    MEM_CHECK(ret, p_hal->reg_ctx = mpp_calloc_size(void, sizeof(Avs2dRkvRegCtx_t)));
+    reg_ctx = (Avs2dRkvRegCtx_t *)p_hal->reg_ctx;
+
+    //!< malloc buffers
+    loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1;
+    FUN_CHECK(ret = mpp_buffer_get(p_hal->buf_group, &reg_ctx->bufs, AVS2_ALL_TBL_BUF_SIZE(loop)));
+    reg_ctx->bufs_fd = mpp_buffer_get_fd(reg_ctx->bufs);
+    reg_ctx->bufs_ptr = mpp_buffer_get_ptr(reg_ctx->bufs);
+    mpp_buffer_attach_dev(reg_ctx->bufs, p_hal->dev);
+
+    for (i = 0; i < loop; i++) {
+        reg_ctx->reg_buf[i].regs = mpp_calloc(Vdpu383Avs2dRegSet, 1);
+        init_ctrl_regs(reg_ctx->reg_buf[i].regs);
+        reg_ctx->reg_buf[i].offset_shph = AVS2_SHPH_OFFSET(i);
+        reg_ctx->reg_buf[i].offset_sclst = AVS2_SCALIST_OFFSET(i);
+    }
+
+    if (!p_hal->fast_mode) {
+        reg_ctx->regs = reg_ctx->reg_buf[0].regs;
+        reg_ctx->shph_offset = reg_ctx->reg_buf[0].offset_shph;
+        reg_ctx->sclst_offset = reg_ctx->reg_buf[0].offset_sclst;
+    }
+
+    mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, mpp_align_128_odd_plus_64);
+    mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, avs2d_ver_align);
+    mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, avs2d_len_align);
+
+__RETURN:
+    AVS2D_HAL_TRACE("Out. ret %d", ret);
+    (void)cfg;
+    return ret;
+__FAILED:
+    hal_avs2d_vdpu383_deinit(p_hal);
+    AVS2D_HAL_TRACE("Out. ret %d", ret);
+    return ret;
+}
+
+static RK_S32 calc_mv_size(RK_S32 pic_w, RK_S32 pic_h, RK_S32 ctu_w)
+{
+    RK_S32 seg_w = 64 * 16 * 16 / ctu_w; // colmv_block_size = 16, colmv_per_bytes = 16
+    RK_S32 seg_cnt_w = MPP_ALIGN(pic_w, seg_w) / seg_w;
+    RK_S32 seg_cnt_h = MPP_ALIGN(pic_h, ctu_w) / ctu_w;
+    RK_S32 mv_size   = seg_cnt_w * seg_cnt_h * 64 * 16;
+
+    return mv_size;
+}
+
+static MPP_RET set_up_colmv_buf(void *hal)
+{
+    MPP_RET ret = MPP_OK;
+    Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
+    Avs2dSyntax_t *syntax = &p_hal->syntax;
+    PicParams_Avs2d *pp   = &syntax->pp;
+    RK_U32 ctu_size = 1 << (p_hal->syntax.pp.lcu_size);
+    RK_S32 mv_size = calc_mv_size(pp->pic_width_in_luma_samples,
+                                  pp->pic_height_in_luma_samples * (1 + pp->field_coded_sequence),
+                                  ctu_size);
+
+    AVS2D_HAL_TRACE("mv_size %d", mv_size);
+
+    if (p_hal->cmv_bufs == NULL || p_hal->mv_size < (RK_U32)mv_size) {
+        size_t size = mv_size;
+
+        if (p_hal->cmv_bufs) {
+            hal_bufs_deinit(p_hal->cmv_bufs);
+            p_hal->cmv_bufs = NULL;
+        }
+
+        hal_bufs_init(&p_hal->cmv_bufs);
+        if (p_hal->cmv_bufs == NULL) {
+            mpp_err_f("colmv bufs init fail");
+            ret = MPP_ERR_INIT;
+            goto __RETURN;
+        }
+
+        p_hal->mv_size = mv_size;
+        p_hal->mv_count = mpp_buf_slot_get_count(p_hal->frame_slots);
+        hal_bufs_setup(p_hal->cmv_bufs, p_hal->mv_count, 1, &size);
+    }
+
+__RETURN:
+    return ret;
+}
+
+MPP_RET hal_avs2d_vdpu383_gen_regs(void *hal, HalTaskInfo *task)
+{
+    MPP_RET ret = MPP_OK;
+    Avs2dRkvRegCtx_t *reg_ctx;
+    Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
+    Vdpu383Avs2dRegSet *regs = NULL;
+
+    AVS2D_HAL_TRACE("In.");
+
+    INP_CHECK(ret, NULL == p_hal);
+    if (task->dec.flags.parse_err || task->dec.flags.ref_err) {
+        ret = MPP_NOK;
+        goto __RETURN;
+    }
+
+    ret = set_up_colmv_buf(p_hal);
+    if (ret)
+        goto __RETURN;
+
+    reg_ctx = (Avs2dRkvRegCtx_t *)p_hal->reg_ctx;
+
+    if (p_hal->fast_mode) {
+        RK_U32 i = 0;
+
+        for (i = 0; i <  MPP_ARRAY_ELEMS(reg_ctx->reg_buf); i++) {
+            if (!reg_ctx->reg_buf[i].valid) {
+                task->dec.reg_index = i;
+                regs = reg_ctx->reg_buf[i].regs;
+                reg_ctx->shph_offset = reg_ctx->reg_buf[i].offset_shph;
+                reg_ctx->sclst_offset = reg_ctx->reg_buf[i].offset_sclst;
+                reg_ctx->regs = reg_ctx->reg_buf[i].regs;
+                reg_ctx->reg_buf[i].valid = 1;
+                break;
+            }
+        }
+
+        mpp_assert(regs);
+    }
+
+    regs = reg_ctx->regs;
+
+    prepare_header(p_hal, reg_ctx->shph_dat, sizeof(reg_ctx->shph_dat) / 8);
+    prepare_scalist(p_hal, reg_ctx->scalist_dat, sizeof(reg_ctx->scalist_dat));
+
+    ret = fill_registers(p_hal, regs, task);
+
+    if (ret)
+        goto __RETURN;
+
+    {
+        memcpy(reg_ctx->bufs_ptr + reg_ctx->shph_offset, reg_ctx->shph_dat, sizeof(reg_ctx->shph_dat));
+        memcpy(reg_ctx->bufs_ptr + reg_ctx->sclst_offset, reg_ctx->scalist_dat, sizeof(reg_ctx->scalist_dat));
+
+        MppDevRegOffsetCfg trans_cfg;
+        trans_cfg.reg_idx = 131;
+        trans_cfg.offset = reg_ctx->shph_offset;
+        regs->common_addr.reg131_gbl_base = reg_ctx->bufs_fd;
+        mpp_dev_ioctl(p_hal->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
+        regs->avs2d_paras.reg67_global_len = AVS2_383_SHPH_SIZE;
+
+        trans_cfg.reg_idx = 132;
+        trans_cfg.offset = reg_ctx->sclst_offset;
+        regs->common_addr.reg132_scanlist_addr = reg_ctx->bufs_fd;
+        mpp_dev_ioctl(p_hal->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
+    }
+
+    // set rcb
+    {
+        hal_avs2d_rcb_info_update(p_hal, regs);
+        vdpu383_setup_rcb(&regs->common_addr, p_hal->dev, p_hal->fast_mode ?
+                          reg_ctx->rcb_buf[task->dec.reg_index] : reg_ctx->rcb_buf[0],
+                          reg_ctx->rcb_info);
+
+    }
+
+    vdpu383_setup_statistic(&regs->ctrl_regs);
+    mpp_buffer_sync_end(reg_ctx->bufs);
+
+__RETURN:
+    AVS2D_HAL_TRACE("Out. ret %d", ret);
+    return ret;
+}
+
+MPP_RET hal_avs2d_vdpu383_start(void *hal, HalTaskInfo *task)
+{
+    MPP_RET ret = MPP_OK;
+    Vdpu383Avs2dRegSet *regs = NULL;
+    Avs2dRkvRegCtx_t *reg_ctx;
+    MppDev dev = NULL;
+    Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
+
+    AVS2D_HAL_TRACE("In.");
+    INP_CHECK(ret, NULL == p_hal);
+
+    if (task->dec.flags.parse_err ||
+        task->dec.flags.ref_err) {
+        goto __RETURN;
+    }
+
+    reg_ctx = (Avs2dRkvRegCtx_t *)p_hal->reg_ctx;
+    regs = p_hal->fast_mode ? reg_ctx->reg_buf[task->dec.reg_index].regs : reg_ctx->regs;
+    dev = p_hal->dev;
+
+    p_hal->frame_no++;
+
+    do {
+        MppDevRegWrCfg wr_cfg;
+        MppDevRegRdCfg rd_cfg;
+
+        wr_cfg.reg = &regs->ctrl_regs;
+        wr_cfg.size = sizeof(regs->ctrl_regs);
+        wr_cfg.offset = OFFSET_CTRL_REGS;
+        ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
+        if (ret) {
+            mpp_err_f("set register write failed %d\n", ret);
+            break;
+        }
+
+        wr_cfg.reg = &regs->common_addr;
+        wr_cfg.size = sizeof(regs->common_addr);
+        wr_cfg.offset = OFFSET_COMMON_ADDR_REGS;
+        ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
+        if (ret) {
+            mpp_err_f("set register write failed %d\n", ret);
+            break;
+        }
+
+        wr_cfg.reg = &regs->avs2d_paras;
+        wr_cfg.size = sizeof(regs->avs2d_paras);
+        wr_cfg.offset = OFFSET_CODEC_PARAS_REGS;
+        ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
+        if (ret) {
+            mpp_err_f("set register write failed %d\n", ret);
+            break;
+        }
+
+        wr_cfg.reg = &regs->avs2d_addrs;
+        wr_cfg.size = sizeof(regs->avs2d_addrs);
+        wr_cfg.offset = OFFSET_CODEC_ADDR_REGS;
+        ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
+        if (ret) {
+            mpp_err_f("set register write failed %d\n", ret);
+            break;
+        }
+
+        rd_cfg.reg = &regs->ctrl_regs.reg15;
+        rd_cfg.size = sizeof(regs->ctrl_regs.reg15);
+        rd_cfg.offset = OFFSET_INTERRUPT_REGS;
+        ret = mpp_dev_ioctl(dev, MPP_DEV_REG_RD, &rd_cfg);
+        if (ret) {
+            mpp_err_f("set register read failed %d\n", ret);
+            break;
+        }
+
+        if (avs2d_hal_debug & AVS2D_HAL_DBG_REG) {
+            memset(reg_ctx->reg_out, 0, sizeof(reg_ctx->reg_out));
+            rd_cfg.reg = reg_ctx->reg_out;
+            rd_cfg.size = sizeof(reg_ctx->reg_out);
+            rd_cfg.offset = 0;
+            ret = mpp_dev_ioctl(dev, MPP_DEV_REG_RD, &rd_cfg);
+        }
+
+        /* rcb info for sram */
+        vdpu383_set_rcbinfo(dev, (Vdpu383RcbInfo*)reg_ctx->rcb_info);
+
+        // send request to hardware
+        ret = mpp_dev_ioctl(dev, MPP_DEV_CMD_SEND, NULL);
+        if (ret) {
+            mpp_err_f("send cmd failed %d\n", ret);
+            break;
+        }
+
+    } while (0);
+
+__RETURN:
+    AVS2D_HAL_TRACE("Out.");
+    return ret;
+}
+
+static RK_U8 fetch_data(RK_U32 fmt, RK_U8 *line, RK_U32 num)
+{
+    RK_U32 offset = 0;
+    RK_U32 value = 0;
+
+    if (fmt == MPP_FMT_YUV420SP_10BIT) {
+        offset = (num * 2) & 7;
+        value = (line[num * 10 / 8] >> offset) |
+                (line[num * 10 / 8 + 1] << (8 - offset));
+
+        value = (value & 0x3ff) >> 2;
+    } else if (fmt == MPP_FMT_YUV420SP) {
+        value = line[num];
+    }
+
+    return value;
+}
+
+static MPP_RET hal_avs2d_vdpu383_dump_yuv(void *hal, HalTaskInfo *task)
+{
+    MPP_RET ret = MPP_OK;
+    Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
+
+    MppFrameFormat fmt = MPP_FMT_YUV420SP;
+    RK_U32 vir_w = 0;
+    RK_U32 vir_h = 0;
+    RK_U32 i = 0;
+    RK_U32 j = 0;
+    FILE *fp_stream = NULL;
+    char name[50];
+    MppBuffer buffer = NULL;
+    MppFrame frame;
+    void *base = NULL;
+
+    ret = mpp_buf_slot_get_prop(p_hal->frame_slots, task->dec.output, SLOT_FRAME_PTR, &frame);
+
+    if (ret != MPP_OK || frame == NULL)
+        mpp_log_f("failed to get frame slot %d", task->dec.output);
+
+    ret = mpp_buf_slot_get_prop(p_hal->frame_slots, task->dec.output, SLOT_BUFFER, &buffer);
+
+    if (ret != MPP_OK || buffer == NULL)
+        mpp_log_f("failed to get frame buffer slot %d", task->dec.output);
+
+    AVS2D_HAL_TRACE("frame slot %d, fd %d\n", task->dec.output, mpp_buffer_get_fd(buffer));
+    base = mpp_buffer_get_ptr(buffer);
+    vir_w = mpp_frame_get_hor_stride(frame);
+    vir_h = mpp_frame_get_ver_stride(frame);
+    fmt = mpp_frame_get_fmt(frame);
+    snprintf(name, sizeof(name), "/data/tmp/rkv_out_%dx%d_nv12_%03d.yuv", vir_w, vir_h,
+             p_hal->frame_no);
+    fp_stream = fopen(name, "wb");
+
+    if (fmt != MPP_FMT_YUV420SP_10BIT) {
+        fwrite(base, 1, vir_w * vir_h * 3 / 2, fp_stream);
+    } else {
+        RK_U8 tmp = 0;
+        for (i = 0; i < vir_h; i++) {
+            for (j = 0; j < vir_w; j++) {
+                tmp = fetch_data(fmt, base, j);
+                fwrite(&tmp, 1, 1, fp_stream);
+            }
+            base += vir_w;
+        }
+
+        for (i = 0; i < vir_h / 2; i++) {
+            for (j = 0; j < vir_w; j++) {
+                tmp = fetch_data(fmt, base, j);
+                fwrite(&tmp, 1, 1, fp_stream);
+            }
+            base += vir_w;
+        }
+    }
+    fclose(fp_stream);
+
+    return ret;
+}
+
+MPP_RET hal_avs2d_vdpu383_wait(void *hal, HalTaskInfo *task)
+{
+    MPP_RET ret = MPP_OK;
+    Avs2dHalCtx_t *p_hal = (Avs2dHalCtx_t *)hal;
+    Avs2dRkvRegCtx_t *reg_ctx;
+    Vdpu383Avs2dRegSet *regs;
+
+    INP_CHECK(ret, NULL == p_hal);
+    reg_ctx = (Avs2dRkvRegCtx_t *)p_hal->reg_ctx;
+    regs = p_hal->fast_mode ? reg_ctx->reg_buf[task->dec.reg_index].regs : reg_ctx->regs;
+
+    if (task->dec.flags.parse_err || task->dec.flags.ref_err) {
+        AVS2D_HAL_DBG(AVS2D_HAL_DBG_ERROR, "found task error.\n");
+        ret = MPP_NOK;
+        goto __RETURN;
+    } else {
+        ret = mpp_dev_ioctl(p_hal->dev, MPP_DEV_CMD_POLL, NULL);
+        if (ret)
+            mpp_err_f("poll cmd failed %d\n", ret);
+    }
+
+    if (avs2d_hal_debug & AVS2D_HAL_DBG_OUT)
+        hal_avs2d_vdpu383_dump_yuv(hal, task);
+
+    AVS2D_HAL_TRACE("read irq_status 0x%08x\n", regs->ctrl_regs.reg19);
+
+    if (p_hal->dec_cb) {
+        DecCbHalDone param;
+
+        param.task = (void *)&task->dec;
+        param.regs = (RK_U32 *)regs;
+
+        if ((!regs->ctrl_regs.reg15.rkvdec_frame_rdy_sta) ||
+            regs->ctrl_regs.reg15.rkvdec_strm_error_sta ||
+            regs->ctrl_regs.reg15.rkvdec_core_timeout_sta ||
+            regs->ctrl_regs.reg15.rkvdec_ip_timeout_sta ||
+            regs->ctrl_regs.reg15.rkvdec_bus_error_sta ||
+            regs->ctrl_regs.reg15.rkvdec_buffer_empty_sta ||
+            regs->ctrl_regs.reg15.rkvdec_colmv_ref_error_sta)
+            param.hard_err = 1;
+        else
+            param.hard_err = 0;
+
+        task->dec.flags.ref_info_valid = 0;
+
+        AVS2D_HAL_TRACE("hal frame %d hard_err= %d", p_hal->frame_no, param.hard_err);
+
+        mpp_callback(p_hal->dec_cb, &param);
+    }
+
+    memset(&regs->ctrl_regs.reg19, 0, sizeof(RK_U32));
+    if (p_hal->fast_mode)
+        reg_ctx->reg_buf[task->dec.reg_index].valid = 0;
+
+__RETURN:
+    AVS2D_HAL_TRACE("Out. ret %d", ret);
+    return ret;
+}
+
+const MppHalApi hal_avs2d_vdpu383 = {
+    .name     = "avs2d_vdpu383",
+    .type     = MPP_CTX_DEC,
+    .coding   = MPP_VIDEO_CodingAVS2,
+    .ctx_size = sizeof(Avs2dRkvRegCtx_t),
+    .flag     = 0,
+    .init     = hal_avs2d_vdpu383_init,
+    .deinit   = hal_avs2d_vdpu383_deinit,
+    .reg_gen  = hal_avs2d_vdpu383_gen_regs,
+    .start    = hal_avs2d_vdpu383_start,
+    .wait     = hal_avs2d_vdpu383_wait,
+    .reset    = NULL,
+    .flush    = NULL,
+    .control  = NULL,
+};
diff --git a/mpp/hal/rkdec/avs2d/hal_avs2d_vdpu383.h b/mpp/hal/rkdec/avs2d/hal_avs2d_vdpu383.h
new file mode 100644
index 000000000..d9950c344
--- /dev/null
+++ b/mpp/hal/rkdec/avs2d/hal_avs2d_vdpu383.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: Apache-2.0 OR MIT */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef __HAL_AVS2D_VDPU383_H__
+#define __HAL_AVS2D_VDPU383_H__
+
+#include "mpp_hal.h"
+#include "vdpu383.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif
+
+extern const MppHalApi hal_avs2d_vdpu383;
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /*__HAL_AVS2D_RKV_H__*/
diff --git a/mpp/hal/rkdec/avsd/hal_avsd_api.c b/mpp/hal/rkdec/avsd/hal_avsd_api.c
index 16c2def3c..a5b8f6dbd 100644
--- a/mpp/hal/rkdec/avsd/hal_avsd_api.c
+++ b/mpp/hal/rkdec/avsd/hal_avsd_api.c
@@ -165,6 +165,7 @@ MPP_RET hal_avsd_init(void *decoder, MppHalCfg *cfg)
     FUN_CHECK(ret = mpp_buffer_group_get_internal(&p_hal->buf_group, MPP_BUFFER_TYPE_ION));
 
     FUN_CHECK(ret = init_hard_platform(p_hal, cfg->coding));
+    cfg->dev = p_hal->dev;
 
     //!< run init funtion
     FUN_CHECK(ret = p_hal->hal_api.init(decoder, cfg));
@@ -193,7 +194,7 @@ MPP_RET hal_avsd_gen_regs(void *decoder, HalTaskInfo *task)
 
     memcpy(&p_hal->syn, task->dec.syntax.data, sizeof(AvsdSyntax_t));
     // check coding
-    coding = (p_hal->syn.pp.profileId == 0x48) ? MPP_VIDEO_CodingAVSPLUS : MPP_VIDEO_CodingAVS;
+    coding = (p_hal->syn.pp.profileId == 0x48) ? MPP_VIDEO_CodingAVSPLUS : p_hal->coding;
     if (coding != p_hal->coding) {
         if (p_hal->dev) {
             ret = mpp_dev_deinit(p_hal->dev);
diff --git a/mpp/hal/rkdec/avsd/hal_avsd_plus.c b/mpp/hal/rkdec/avsd/hal_avsd_plus.c
index 352eabd6e..015ab1a6e 100644
--- a/mpp/hal/rkdec/avsd/hal_avsd_plus.c
+++ b/mpp/hal/rkdec/avsd/hal_avsd_plus.c
@@ -511,7 +511,8 @@ static MPP_RET update_parameters(AvsdHalCtx_t *p_hal)
             p_hal->work1 =  p_hal->work0;
             p_hal->work0 =  p_hal->work_out;
 
-            p_hal->pic[p_hal->work_out].pic_type = p_syn->pp.picCodingType == IFRAME;
+            if (p_hal->work_out >= 0)
+                p_hal->pic[p_hal->work_out].pic_type = p_syn->pp.picCodingType == IFRAME;
             p_hal->work_out = temp;
             p_hal->prev_pic_structure = p_syn->pp.pictureStructure;
         }
diff --git a/mpp/hal/rkdec/avsd/hal_avsd_vdpu1.c b/mpp/hal/rkdec/avsd/hal_avsd_vdpu1.c
index 4bf9e4eff..a894c3447 100644
--- a/mpp/hal/rkdec/avsd/hal_avsd_vdpu1.c
+++ b/mpp/hal/rkdec/avsd/hal_avsd_vdpu1.c
@@ -420,7 +420,8 @@ static MPP_RET update_parameters(AvsdHalCtx_t *p_hal)
             p_hal->work1 =  p_hal->work0;
             p_hal->work0 =  p_hal->work_out;
 
-            p_hal->pic[p_hal->work_out].pic_type = p_syn->pp.picCodingType == IFRAME;
+            if (p_hal->work_out >= 0)
+                p_hal->pic[p_hal->work_out].pic_type = p_syn->pp.picCodingType == IFRAME;
             p_hal->work_out = temp;
             p_hal->prev_pic_structure = p_syn->pp.pictureStructure;
         }
diff --git a/mpp/hal/rkdec/avsd/hal_avsd_vdpu2.c b/mpp/hal/rkdec/avsd/hal_avsd_vdpu2.c
index 521343c56..69770c162 100644
--- a/mpp/hal/rkdec/avsd/hal_avsd_vdpu2.c
+++ b/mpp/hal/rkdec/avsd/hal_avsd_vdpu2.c
@@ -413,7 +413,8 @@ static MPP_RET update_parameters(AvsdHalCtx_t *p_hal)
             p_hal->work1 =  p_hal->work0;
             p_hal->work0 =  p_hal->work_out;
 
-            p_hal->pic[p_hal->work_out].pic_type = p_syn->pp.picCodingType == IFRAME;
+            if (p_hal->work_out >= 0)
+                p_hal->pic[p_hal->work_out].pic_type = p_syn->pp.picCodingType == IFRAME;
             p_hal->work_out = temp;
             p_hal->prev_pic_structure = p_syn->pp.pictureStructure;
         }
diff --git a/mpp/hal/rkdec/h264d/CMakeLists.txt b/mpp/hal/rkdec/h264d/CMakeLists.txt
index 12118bded..788747f71 100644
--- a/mpp/hal/rkdec/h264d/CMakeLists.txt
+++ b/mpp/hal/rkdec/h264d/CMakeLists.txt
@@ -5,6 +5,7 @@ set(HAL_H264D_SRC
     hal_h264d_api.c
     hal_h264d_vdpu34x.c
     hal_h264d_vdpu382.c
+    hal_h264d_vdpu383.c
     hal_h264d_rkv_reg.c
     hal_h264d_vdpu2.c
     hal_h264d_vdpu1.c
@@ -13,6 +14,6 @@ set(HAL_H264D_SRC
 
 add_library(hal_h264d STATIC ${HAL_H264D_SRC})
 
-target_link_libraries(hal_h264d vdpu34x_com mpp_base mpp_hal)
+target_link_libraries(hal_h264d vdpu34x_com vdpu383_com mpp_base mpp_hal)
 set_target_properties(hal_h264d PROPERTIES FOLDER "mpp/hal")
 
diff --git a/mpp/hal/rkdec/h264d/hal_h264d_api.c b/mpp/hal/rkdec/h264d/hal_h264d_api.c
index 51a5afb18..18dc80a0d 100644
--- a/mpp/hal/rkdec/h264d/hal_h264d_api.c
+++ b/mpp/hal/rkdec/h264d/hal_h264d_api.c
@@ -39,11 +39,171 @@
 #include "hal_h264d_rkv_reg.h"
 #include "hal_h264d_vdpu34x.h"
 #include "hal_h264d_vdpu382.h"
+#include "hal_h264d_vdpu383.h"
 #include "hal_h264d_vdpu2.h"
 #include "hal_h264d_vdpu1.h"
 
 RK_U32 hal_h264d_debug = 0;
 
+// merge with vdpu34x and rkv is necessary
+const RK_U32 h264_cabac_table[928] = {
+    0x3602f114, 0xf1144a03, 0x4a033602, 0x68e97fe4, 0x36ff35fa, 0x21173307,
+    0x00150217, 0x31000901, 0x390576db, 0x41f54ef3, 0x310c3e01, 0x321149fc,
+    0x2b094012, 0x431a001d, 0x68095a10, 0x68ec7fd2, 0x4ef34301, 0x3e0141f5,
+    0x5fef56fa, 0x2d093dfa, 0x51fa45fd, 0x370660f5, 0x56fb4307, 0x3a005802,
+    0x5ef64cfd, 0x45043605, 0x580051fd, 0x4afb43f9, 0x50fb4afc, 0x3a0148f9,
+    0x3f002900, 0x3f003f00, 0x560453f7, 0x48f96100, 0x3e03290d, 0x4efc2d00,
+    0x7ee560fd, 0x65e762e4, 0x52e443e9, 0x53f05eec, 0x5beb6eea, 0x5df366ee,
+    0x5cf97fe3, 0x60f959fb, 0x2efd6cf3, 0x39ff41ff, 0x4afd5df7, 0x57f85cf7,
+    0x36057ee9, 0x3b063c06, 0x30ff4506, 0x45fc4400, 0x55fe58f8, 0x4bff4efa,
+    0x36024df9, 0x44fd3205, 0x2a063201, 0x3f0151fc, 0x430046fc, 0x4cfe3902,
+    0x4004230b, 0x230b3d01, 0x180c1912, 0x240d1d0d, 0x49f95df6, 0x2e0d49fe,
+    0x64f93109, 0x35023509, 0x3dfe3505, 0x38003800, 0x3cfb3ff3, 0x39043eff,
+    0x390445fa, 0x3304270e, 0x4003440d, 0x3f093d01, 0x27103207, 0x34042c05,
+    0x3cfb300b, 0x3b003bff, 0x2c052116, 0x4eff2b0e, 0x45093c00, 0x28021c0b,
+    0x31002c03, 0x2c022e00, 0x2f003302, 0x3e022704, 0x36002e06, 0x3a023603,
+    0x33063f04, 0x35073906, 0x37063406, 0x240e2d0b, 0x52ff3508, 0x4efd3707,
+    0x1f162e0f, 0x071954ff, 0x031cf91e, 0x0020041c, 0x061eff22, 0x0920061e,
+    0x1b1a131f, 0x14251e1a, 0x4611221c, 0x3b054301, 0x1e104309, 0x23122012,
+    0x1f181d16, 0x2b122617, 0x3f0b2914, 0x40093b09, 0x59fe5eff, 0x4cfa6cf7,
+    0x2d002cfe, 0x40fd3400, 0x46fc3bfe, 0x52f84bfc, 0x4df766ef, 0x2a001803,
+    0x37003000, 0x47f93bfa, 0x57f553f4, 0x3a0177e2, 0x24ff1dfd, 0x2b022601,
+    0x3a0037fa, 0x4afd4000, 0x46005af6, 0x1f051dfc, 0x3b012a07, 0x48fd3afe,
+    0x61f551fd, 0x05083a00, 0x120e0e0a, 0x28021b0d, 0x46fd3a00, 0x55f84ffa,
+    0x6af30000, 0x57f66af0, 0x6eee72eb, 0x6eea62f2, 0x67ee6aeb, 0x6ce96beb,
+    0x60f670e6, 0x5bfb5ff4, 0x5eea5df7, 0x430956fb, 0x55f650fc, 0x3c0746ff,
+    0x3d053a09, 0x320f320c, 0x36113112, 0x2e07290a, 0x310733ff, 0x29093408,
+    0x37022f06, 0x2c0a290d, 0x35053206, 0x3f04310d, 0x45fe4006, 0x46063bfe,
+    0x1f092c0a, 0x35032b0c, 0x260a220e, 0x280d34fd, 0x2c072011, 0x320d2607,
+    0x2b1a390a, 0x0e0b0b0e, 0x0b120b09, 0xfe170915, 0xf120f120, 0xe927eb22,
+    0xe129df2a, 0xf426e42e, 0xe82d1d15, 0xe630d335, 0xed2bd541, 0x091ef627,
+    0x1b141a12, 0x52f23900, 0x61ed4bfb, 0x001b7ddd, 0xfc1f001c, 0x0822061b,
+    0x16180a1e, 0x20161321, 0x29151f1a, 0x2f172c1a, 0x470e4110, 0x3f063c08,
+    0x18154111, 0x171a1417, 0x171c201b, 0x2817181c, 0x1d1c2018, 0x39132a17,
+    0x3d163516, 0x280c560b, 0x3b0e330b, 0x47f94ffc, 0x46f745fb, 0x44f642f8,
+    0x45f449ed, 0x43f146f0, 0x46ed3eec, 0x41ea42f0, 0xfe093fec, 0xf721f71a,
+    0xfe29f927, 0x0931032d, 0x3b241b2d, 0x23f942fa, 0x2df82af9, 0x38f430fb,
+    0x3efb3cfa, 0x4cf842f8, 0x51fa55fb, 0x51f94df6, 0x49ee50ef, 0x53f64afc,
+    0x43f747f7, 0x42f83dff, 0x3b0042f2, 0xf3153b02, 0xf927f221, 0x0233fe2e,
+    0x113d063c, 0x3e2a2237, 0x00000000, 0x00000000, 0x3602f114, 0xf1144a03,
+    0x4a033602, 0x68e97fe4, 0x36ff35fa, 0x19163307, 0x00100022, 0x290409fe,
+    0x410276e3, 0x4ff347fa, 0x32093405, 0x360a46fd, 0x1613221a, 0x02390028,
+    0x451a2429, 0x65f17fd3, 0x47fa4cfc, 0x34054ff3, 0x5af34506, 0x2b083400,
+    0x52fb45fe, 0x3b0260f6, 0x57fd4b02, 0x380164fd, 0x55fa4afd, 0x51fd3b00,
+    0x5ffb56f9, 0x4dff42ff, 0x56fe4601, 0x3d0048fb, 0x3f002900, 0x3f003f00,
+    0x560453f7, 0x48f96100, 0x3e03290d, 0x33070f0d, 0x7fd95002, 0x60ef5bee,
+    0x62dd51e6, 0x61e966e8, 0x63e877e5, 0x66ee6eeb, 0x50007fdc, 0x5ef959fb,
+    0x27005cfc, 0x54f14100, 0x49fe7fdd, 0x5bf768f4, 0x37037fe1, 0x37073807,
+    0x35fd3d08, 0x4af94400, 0x67f358f7, 0x59f75bf3, 0x4cf85cf2, 0x6ee957f4,
+    0x4ef669e8, 0x63ef70ec, 0x7fba7fb2, 0x7fd27fce, 0x4efb42fc, 0x48f847fc,
+    0x37ff3b02, 0x4bfa46f9, 0x77de59f8, 0x14204bfd, 0x7fd4161e, 0x3dfb3600,
+    0x3cff3a00, 0x43f83dfd, 0x4af254e7, 0x340541fb, 0x3d003902, 0x46f545f7,
+    0x47fc3712, 0x3d073a00, 0x19122909, 0x2b052009, 0x2c002f09, 0x2e023300,
+    0x42fc2613, 0x2a0c260f, 0x59002209, 0x1c0a2d04, 0xf5211f0a, 0x0f12d534,
+    0xea23001c, 0x0022e726, 0xf420ee27, 0x0000a266, 0xfc21f138, 0xfb250a1d,
+    0xf727e333, 0xc645de34, 0xfb2cc143, 0xe3370720, 0x00000120, 0xe721241b,
+    0xe424e222, 0xe526e426, 0xf023ee22, 0xf820f222, 0x0023fa25, 0x121c0a1e,
+    0x291d191a, 0x48024b00, 0x230e4d08, 0x23111f12, 0x2d111e15, 0x2d122a14,
+    0x36101a1b, 0x38104207, 0x430a490b, 0x70e974f6, 0x3df947f1, 0x42fb3500,
+    0x50f74df5, 0x57f654f7, 0x65eb7fde, 0x35fb27fd, 0x4bf53df9, 0x5bef4df1,
+    0x6fe76be7, 0x4cf57ae4, 0x34f62cf6, 0x3af739f6, 0x45f948f0, 0x4afb45fc,
+    0x420256f7, 0x200122f7, 0x34051f0b, 0x43fe37fe, 0x59f84900, 0x04073403,
+    0x0811080a, 0x25031310, 0x49fb3dff, 0x4efc46ff, 0x7eeb0000, 0x6eec7ce9,
+    0x7ce77ee6, 0x79e569ef, 0x66ef75e5, 0x74e575e6, 0x5ff67adf, 0x5ff864f2,
+    0x72e46fef, 0x50fe59fa, 0x55f752fc, 0x48ff51f8, 0x43014005, 0x45003809,
+    0x45074501, 0x43fa45f9, 0x40fe4df0, 0x43fa3d02, 0x390240fd, 0x42fd41fd,
+    0x33093e00, 0x47fe42ff, 0x46ff4bfe, 0x3c0e48f7, 0x2f002510, 0x250b2312,
+    0x290a290c, 0x290c3002, 0x3b00290d, 0x28133203, 0x32124203, 0xfa12fa13,
+    0xf41a000e, 0xe721f01f, 0xe425ea21, 0xe22ae227, 0xdc2dd62f, 0xef29de31,
+    0xb9450920, 0xc042c13f, 0xd936b64d, 0xf629dd34, 0xff280024, 0x1a1c0e1e,
+    0x370c2517, 0xdf25410b, 0xdb28dc27, 0xdf2ee226, 0xe828e22a, 0xf426e331,
+    0xfd26f628, 0x141ffb2e, 0x2c191e1d, 0x310b300c, 0x16162d1a, 0x151b1617,
+    0x1c1a1421, 0x221b181e, 0x27192a12, 0x460c3212, 0x470e3615, 0x2019530b,
+    0x36153115, 0x51fa55fb, 0x51f94df6, 0x49ee50ef, 0x53f64afc, 0x43f747f7,
+    0x42f83dff, 0x3b0042f2, 0xf6113b02, 0xf72af320, 0x0035fb31, 0x0a440340,
+    0x392f1b42, 0x180047fb, 0x2afe24ff, 0x39f734fe, 0x41fc3ffa, 0x52f943fc,
+    0x4cfd51fd, 0x4efa48f9, 0x44f248f4, 0x4cfa46fd, 0x3efb42fb, 0x3dfc3900,
+    0x36013cf7, 0xf6113a02, 0xf72af320, 0x0035fb31, 0x0a440340, 0x392f1b42,
+    0x00000000, 0x00000000, 0x3602f114, 0xf1144a03, 0x4a033602, 0x68e97fe4,
+    0x36ff35fa, 0x101d3307, 0x000e0019, 0x3efd33f6, 0x101a63e5, 0x66e855fc,
+    0x39063905, 0x390e49ef, 0x0a142814, 0x0036001d, 0x610c2a25, 0x75ea7fe0,
+    0x55fc4afe, 0x390566e8, 0x58f25dfa, 0x37042cfa, 0x67f159f5, 0x391374eb,
+    0x54043a14, 0x3f016006, 0x6af355fb, 0x4b063f05, 0x65ff5afd, 0x4ffc3703,
+    0x61f44bfe, 0x3c0132f9, 0x3f002900, 0x3f003f00, 0x560453f7, 0x48f96100,
+    0x3e03290d, 0x58f72207, 0x7fdc7fec, 0x5ff25bef, 0x56e754e7, 0x5bef59f4,
+    0x4cf27fe1, 0x5af367ee, 0x500b7fdb, 0x54024c05, 0x37fa4e05, 0x53f23d04,
+    0x4ffb7fdb, 0x5bf568f5, 0x41007fe2, 0x48004ffe, 0x38fa5cfc, 0x47f84403,
+    0x56fc62f3, 0x52fb58f4, 0x43fc48fd, 0x59f048f8, 0x3bff45f7, 0x39044205,
+    0x47fe47fc, 0x4aff3a02, 0x45ff2cfc, 0x33f93e00, 0x2afa2ffc, 0x35fa29fd,
+    0x4ef74c08, 0x340953f5, 0x5afb4300, 0x48f14301, 0x50f84bfb, 0x40eb53eb,
+    0x40e71ff3, 0x4b095ee3, 0x4af83f11, 0x1bfe23fb, 0x41035b0d, 0x4d0845f9,
+    0x3e0342f6, 0x51ec44fd, 0x07011e00, 0x4aeb17fd, 0x7ce94210, 0xee2c2511,
+    0x7feade32, 0x2a002704, 0x1d0b2207, 0x25061f08, 0x28032a07, 0x2b0d2108,
+    0x2f04240d, 0x3a023703, 0x2c083c06, 0x2a0e2c0b, 0x38043007, 0x250d3404,
+    0x3a133109, 0x2d0c300a, 0x21144500, 0xee233f08, 0xfd1ce721, 0x001b0a18,
+    0xd434f222, 0x1113e827, 0x1d24191f, 0x0f222118, 0x4916141e, 0x1f132214,
+    0x10132c1b, 0x240f240f, 0x15191c15, 0x0c1f141e, 0x2a18101b, 0x380e5d00,
+    0x261a390f, 0x73e87fe8, 0x3ef752ea, 0x3b003500, 0x59f355f2, 0x5cf55ef3,
+    0x64eb7fe3, 0x43f439f2, 0x4df647f5, 0x58f055eb, 0x62f168e9, 0x52f67fdb,
+    0x3df830f8, 0x46f942f8, 0x4ff64bf2, 0x5cf453f7, 0x4ffc6cee, 0x4bf045ea,
+    0x3a013afe, 0x53f74ef3, 0x63f351fc, 0x26fa51f3, 0x3afa3ef3, 0x49f03bfe,
+    0x56f34cf6, 0x57f653f7, 0x7fea0000, 0x78e77fe7, 0x72ed7fe5, 0x76e775e9,
+    0x71e875e6, 0x78e176e4, 0x5ef67cdb, 0x63f666f1, 0x7fce6af3, 0x39115cfb,
+    0x5ef356fb, 0x4dfe5bf4, 0x49ff4700, 0x51f94004, 0x390f4005, 0x44004301,
+    0x440143f6, 0x40024d00, 0x4efb4400, 0x3b053707, 0x360e4102, 0x3c052c0f,
+    0x4cfe4602, 0x460c56ee, 0x46f44005, 0x3805370b, 0x41024500, 0x36054afa,
+    0x4cfa3607, 0x4dfe52f5, 0x2a194dfe, 0xf710f311, 0xeb1bf411, 0xd829e225,
+    0xd130d72a, 0xd82ee027, 0xd72ecd34, 0xed2bd934, 0xc93d0b20, 0xce3ed238,
+    0xec2dbd51, 0x0f1cfe23, 0x01270122, 0x2614111e, 0x360f2d12, 0xf0244f00,
+    0xef25f225, 0x0f220120, 0x19180f1d, 0x101f1622, 0x1c1f1223, 0x1c242921,
+    0x3e152f1b, 0x1a131f12, 0x17181824, 0x1e18101b, 0x29161d1f, 0x3c102a16,
+    0x3c0e340f, 0x7bf04e03, 0x38163515, 0x21153d19, 0x3d113213, 0x4af84efd,
+    0x48f648f7, 0x47f44bee, 0x46fb3ff5, 0x48f24bef, 0x35f843f0, 0x34f73bf2,
+    0xfe0944f5, 0xfc1ff61e, 0x0721ff21, 0x17250c1f, 0x4014261f, 0x25f947f7,
+    0x31f52cf8, 0x3bf438f6, 0x43f73ff8, 0x4ff644fa, 0x4af84efd, 0x48f648f7,
+    0x47f44bee, 0x46fb3ff5, 0x48f24bef, 0x35f843f0, 0x34f73bf2, 0xfe0944f5,
+    0xfc1ff61e, 0x0721ff21, 0x17250c1f, 0x4014261f, 0x00000000, 0x00000000,
+    0x3602f114, 0xf1144a03, 0x4a033602, 0x68e97fe4, 0x36ff35fa, 0x00003307,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+    0x3f002900, 0x3f003f00, 0x560453f7, 0x48f96100, 0x3e03290d, 0x37010b00,
+    0x7fef4500, 0x520066f3, 0x6beb4af9, 0x7fe17fe5, 0x5fee7fe8, 0x72eb7fe5,
+    0x7bef7fe2, 0x7af073f4, 0x3ff473f5, 0x54f144fe, 0x46fd68f3, 0x5af65df8,
+    0x4aff7fe2, 0x5bf961fa, 0x38fc7fec, 0x4cf952fb, 0x5df97dea, 0x4dfd57f5,
+    0x3ffc47fb, 0x54f444fc, 0x41f93ef9, 0x38053d08, 0x400142fe, 0x4efe3d00,
+    0x34073201, 0x2c00230a, 0x2d01260b, 0x2c052e00, 0x3301111f, 0x131c3207,
+    0x3e0e2110, 0x64f16cf3, 0x5bf365f3, 0x58f65ef4, 0x56f654f0, 0x57f353f9,
+    0x46015eed, 0x4afb4800, 0x66f83b12, 0x5f0064f1, 0x48024bfc, 0x47fd4bf5,
+    0x45f32e0f, 0x41003e00, 0x48f12515, 0x36103909, 0x480c3e00, 0x090f0018,
+    0x120d1908, 0x130d090f, 0x120c250a, 0x21141d06, 0x2d041e0f, 0x3e003a01,
+    0x260c3d07, 0x270f2d0b, 0x2c0d2a0b, 0x290c2d10, 0x221e310a, 0x370a2a12,
+    0x2e113311, 0xed1a5900, 0xef1aef16, 0xec1ce71e, 0xe525e921, 0xe428e921,
+    0xf521ef26, 0xfa29f128, 0x11290126, 0x031bfa1e, 0xf025161a, 0xf826fc23,
+    0x0325fd26, 0x002a0526, 0x16271023, 0x251b300e, 0x440c3c15, 0x47fd6102,
+    0x32fb2afa, 0x3efe36fd, 0x3f013a00, 0x4aff48fe, 0x43fb5bf7, 0x27fd1bfb,
+    0x2e002cfe, 0x44f840f0, 0x4dfa4ef6, 0x5cf456f6, 0x3cf637f1, 0x41fc3efa,
+    0x4cf849f4, 0x58f750f9, 0x61f56eef, 0x4ff554ec, 0x4afc49fa, 0x60f356f3,
+    0x75ed61f5, 0x21fb4ef8, 0x35fe30fc, 0x47f33efd, 0x56f44ff6, 0x61f25af3,
+    0x5dfa0000, 0x4ff854fa, 0x47ff4200, 0x3cfe3e00, 0x4bfb3bfe, 0x3afc3efd,
+    0x4fff42f7, 0x44034700, 0x3ef92c0a, 0x280e240f, 0x1d0c1b10, 0x24142c01,
+    0x2a052012, 0x3e0a3001, 0x40092e11, 0x61f568f4, 0x58f960f0, 0x55f955f8,
+    0x58f355f7, 0x4dfd4204, 0x4cfa4cfd, 0x4cff3a0a, 0x63f953ff, 0x5f025ff2,
+    0x4afb4c00, 0x4bf54600, 0x41004401, 0x3e0349f2, 0x44ff3e04, 0x370b4bf3,
+    0x460c4005, 0x1306060f, 0x0e0c1007, 0x0b0d0d12, 0x100f0f0d, 0x170d170c,
+    0x1a0e140f, 0x28112c0e, 0x11182f11, 0x16191515, 0x1d161b1f, 0x320e2313,
+    0x3f07390a, 0x52fc4dfe, 0x45095efd, 0xdd246df4, 0xe620de24, 0xe02ce225,
+    0xf122ee22, 0xf921f128, 0x0021fb23, 0x0d210226, 0x3a0d2317, 0x001afd1d,
+    0xf91f1e16, 0xfd22f123, 0xff240322, 0x0b200522, 0x0c220523, 0x1d1e0b27,
+    0x271d1a22, 0x151f4213, 0x32191f1f, 0x70ec78ef, 0x55f572ee, 0x59f25cf1,
+    0x51f147e6, 0x440050f2, 0x38e846f2, 0x32e844e9, 0xf3174af5, 0xf128f31a,
+    0x032cf231, 0x222c062d, 0x52133621, 0x17ff4bfd, 0x2b012201, 0x37fe3600,
+    0x40013d00, 0x5cf74400, 0x61f36af2, 0x5af45af1, 0x49f658ee, 0x56f24ff7,
+    0x46f649f6, 0x42fb45f6, 0x3afb40f7, 0xf6153b02, 0xf81cf518, 0x031dff1c,
+    0x1423091d, 0x430e241d, 0x00000000, 0x00000000
+};
+
 static void explain_input_buffer(void *hal, HalDecTask *task)
 {
     RK_U32 i = 0;
@@ -80,7 +240,6 @@ static void explain_input_buffer(void *hal, HalDecTask *task)
 //extern "C"
 MPP_RET hal_h264d_init(void *hal, MppHalCfg *cfg)
 {
-    MppHalApi *p_api = NULL;
     MPP_RET ret = MPP_ERR_UNKNOW;
     H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
     MppClientType client_type = VPU_CLIENT_BUTT;
@@ -130,61 +289,34 @@ MPP_RET hal_h264d_init(void *hal, MppHalCfg *cfg)
         H264D_DBG(H264D_DBG_HARD_MODE, "client_type %d\n", client_type);
     }
 
-    p_api = &p_hal->hal_api;
     switch (client_type) {
     case VPU_CLIENT_RKVDEC : {
         RK_U32 hw_id = mpp_get_client_hw_id(client_type);
 
-        if (hw_id == HWID_VDPU382_RK3528 || hw_id == HWID_VDPU382_RK3562) {
-            p_api->init    = vdpu382_h264d_init;
-            p_api->deinit  = vdpu382_h264d_deinit;
-            p_api->reg_gen = vdpu382_h264d_gen_regs;
-            p_api->start   = vdpu382_h264d_start;
-            p_api->wait    = vdpu382_h264d_wait;
-            p_api->reset   = vdpu382_h264d_reset;
-            p_api->flush   = vdpu382_h264d_flush;
-            p_api->control = vdpu382_h264d_control;
-        } else if (hw_id == HWID_VDPU34X || hw_id == HWID_VDPU38X) {
-            p_api->init    = vdpu34x_h264d_init;
-            p_api->deinit  = vdpu34x_h264d_deinit;
-            p_api->reg_gen = vdpu34x_h264d_gen_regs;
-            p_api->start   = vdpu34x_h264d_start;
-            p_api->wait    = vdpu34x_h264d_wait;
-            p_api->reset   = vdpu34x_h264d_reset;
-            p_api->flush   = vdpu34x_h264d_flush;
-            p_api->control = vdpu34x_h264d_control;
-        } else {
-            p_api->init    = rkv_h264d_init;
-            p_api->deinit  = rkv_h264d_deinit;
-            p_api->reg_gen = rkv_h264d_gen_regs;
-            p_api->start   = rkv_h264d_start;
-            p_api->wait    = rkv_h264d_wait;
-            p_api->reset   = rkv_h264d_reset;
-            p_api->flush   = rkv_h264d_flush;
-            p_api->control = rkv_h264d_control;
+        switch (hw_id) {
+        case HWID_VDPU383 : {
+            p_hal->hal_api = &hal_h264d_vdpu383;
+        } break;
+        case HWID_VDPU382_RK3528 :
+        case HWID_VDPU382_RK3562 : {
+            p_hal->hal_api = &hal_h264d_vdpu382;
+        } break;
+        case HWID_VDPU34X :
+        case HWID_VDPU38X : {
+            p_hal->hal_api = &hal_h264d_vdpu34x;
+        } break;
+        default : {
+            p_hal->hal_api = &hal_h264d_rkvdpu;
+        } break;
         }
 
         cfg->support_fast_mode = 1;
     } break;
     case VPU_CLIENT_VDPU1 : {
-        p_api->init    = vdpu1_h264d_init;
-        p_api->deinit  = vdpu1_h264d_deinit;
-        p_api->reg_gen = vdpu1_h264d_gen_regs;
-        p_api->start   = vdpu1_h264d_start;
-        p_api->wait    = vdpu1_h264d_wait;
-        p_api->reset   = vdpu1_h264d_reset;
-        p_api->flush   = vdpu1_h264d_flush;
-        p_api->control = vdpu1_h264d_control;
+        p_hal->hal_api = &hal_h264d_vdpu1;
     } break;
     case VPU_CLIENT_VDPU2 : {
-        p_api->init    = vdpu2_h264d_init;
-        p_api->deinit  = vdpu2_h264d_deinit;
-        p_api->reg_gen = vdpu2_h264d_gen_regs;
-        p_api->start   = vdpu2_h264d_start;
-        p_api->wait    = vdpu2_h264d_wait;
-        p_api->reset   = vdpu2_h264d_reset;
-        p_api->flush   = vdpu2_h264d_flush;
-        p_api->control = vdpu2_h264d_control;
+        p_hal->hal_api = &hal_h264d_vdpu2;
     } break;
     default : {
         mpp_err_f("client_type error, value=%d\n", client_type);
@@ -197,6 +329,8 @@ MPP_RET hal_h264d_init(void *hal, MppHalCfg *cfg)
         mpp_err("mpp_dev_init failed ret: %d\n", ret);
         goto __FAILED;
     }
+    cfg->hw_info = mpp_get_dec_hw_info_by_client_type(client_type);
+    p_hal->hw_info = cfg->hw_info;
 
     //!< callback function to parser module
     p_hal->dec_cb       = cfg->dec_cb;
@@ -213,7 +347,7 @@ MPP_RET hal_h264d_init(void *hal, MppHalCfg *cfg)
     }
 
     //!< run init funtion
-    FUN_CHECK(ret = p_api->init(hal, cfg));
+    FUN_CHECK(ret = p_hal->hal_api->init(hal, cfg));
 __RETURN:
     return MPP_OK;
 __FAILED:
@@ -232,7 +366,7 @@ MPP_RET hal_h264d_deinit(void *hal)
     MPP_RET ret = MPP_ERR_UNKNOW;
     H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
 
-    FUN_CHECK(ret = p_hal->hal_api.deinit(hal));
+    FUN_CHECK(ret = p_hal->hal_api->deinit(hal));
 
     if (p_hal->dev) {
         mpp_dev_deinit(p_hal->dev);
@@ -260,93 +394,68 @@ MPP_RET hal_h264d_gen_regs(void *hal, HalTaskInfo *task)
     H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
 
     explain_input_buffer(hal, &task->dec);
-    return p_hal->hal_api.reg_gen(hal, task);
-}
-
-/*!
-***********************************************************************
-* \brief h
-*    start hard
-***********************************************************************
-*/
-//extern "C"
-MPP_RET hal_h264d_start(void *hal, HalTaskInfo *task)
-{
-    H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
-
-    return p_hal->hal_api.start(hal, task);
-}
-
-/*!
-***********************************************************************
-* \brief
-*    wait hard
-***********************************************************************
-*/
-//extern "C"
-MPP_RET hal_h264d_wait(void *hal, HalTaskInfo *task)
-{
-    H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
+    if (!p_hal || !p_hal->hal_api || !p_hal->hal_api->reg_gen)
+        return MPP_NOK;
 
-    return p_hal->hal_api.wait(hal, task);
+    return p_hal->hal_api->reg_gen(hal, task);
 }
 
 /*!
 ***********************************************************************
 * \brief
-*    reset
+*    control
 ***********************************************************************
 */
 //extern "C"
-MPP_RET hal_h264d_reset(void *hal)
+MPP_RET hal_h264d_control(void *hal, MpiCmd cmd_type, void *param)
 {
     H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
 
-    return p_hal->hal_api.reset(hal);
-}
-
-/*!
-***********************************************************************
-* \brief
-*    flush
-***********************************************************************
-*/
-//extern "C"
-MPP_RET hal_h264d_flush(void *hal)
-{
-    H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
+    if (!p_hal || !p_hal->hal_api || !p_hal->hal_api->control)
+        return MPP_NOK;
 
-    return p_hal->hal_api.flush(hal);
+    return p_hal->hal_api->control(hal, cmd_type, param);
 }
 
-/*!
-***********************************************************************
-* \brief
-*    control
-***********************************************************************
-*/
-//extern "C"
-MPP_RET hal_h264d_control(void *hal, MpiCmd cmd_type, void *param)
-{
-    H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
+#define HAL_H264D_FUNC(func) \
+    static MPP_RET hal_h264d_##func(void *hal)                      \
+    {                                                               \
+        H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;                \
+                                                                    \
+        if (!p_hal || !p_hal->hal_api || !p_hal->hal_api->func)     \
+            return MPP_OK;                                          \
+                                                                    \
+        return p_hal->hal_api->func(hal);                           \
+    }
 
-    return p_hal->hal_api.control(hal, cmd_type, param);
-}
+#define HAL_H264D_TASK_FUNC(func) \
+    static MPP_RET hal_h264d_##func(void *hal, HalTaskInfo *task)   \
+    {                                                               \
+        H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;                \
+                                                                    \
+        if (!p_hal || !p_hal->hal_api || !p_hal->hal_api->func)     \
+            return MPP_OK;                                          \
+                                                                    \
+        return p_hal->hal_api->func(hal, task);                     \
+    }
 
+HAL_H264D_FUNC(flush);
+HAL_H264D_FUNC(reset);
+HAL_H264D_TASK_FUNC(start);
+HAL_H264D_TASK_FUNC(wait);
 
 const MppHalApi hal_api_h264d = {
-    .name = "h264d_rkdec",
-    .type = MPP_CTX_DEC,
-    .coding = MPP_VIDEO_CodingAVC,
+    .name     = "h264d_rkdec",
+    .type     = MPP_CTX_DEC,
+    .coding   = MPP_VIDEO_CodingAVC,
     .ctx_size = sizeof(H264dHalCtx_t),
-    .flag = 0,
-    .init = hal_h264d_init,
-    .deinit = hal_h264d_deinit,
-    .reg_gen = hal_h264d_gen_regs,
-    .start = hal_h264d_start,
-    .wait = hal_h264d_wait,
-    .reset = hal_h264d_reset,
-    .flush = hal_h264d_flush,
-    .control = hal_h264d_control,
+    .flag     = 0,
+    .init     = hal_h264d_init,
+    .deinit   = hal_h264d_deinit,
+    .reg_gen  = hal_h264d_gen_regs,
+    .start    = hal_h264d_start,
+    .wait     = hal_h264d_wait,
+    .reset    = hal_h264d_reset,
+    .flush    = hal_h264d_flush,
+    .control  = hal_h264d_control,
 };
-
diff --git a/mpp/hal/rkdec/h264d/hal_h264d_global.h b/mpp/hal/rkdec/h264d/hal_h264d_global.h
index ab11ef6a5..3e8961bac 100644
--- a/mpp/hal/rkdec/h264d/hal_h264d_global.h
+++ b/mpp/hal/rkdec/h264d/hal_h264d_global.h
@@ -1,20 +1,7 @@
+/* SPDX-License-Identifier: Apache-2.0 OR MIT */
 /*
-*
-* Copyright 2015 Rockchip Electronics Co. LTD
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*      http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*/
-
+ * Copyright (c) 2015 Rockchip Electronics Co., Ltd.
+ */
 
 #ifndef __HAL_H264D_GLOBAL_H__
 #define __HAL_H264D_GLOBAL_H__
@@ -27,8 +14,6 @@
 #include "dxva_syntax.h"
 #include "h264d_syntax.h"
 
-
-
 #define H264D_DBG_ERROR             (0x00000001)
 #define H264D_DBG_ASSERT            (0x00000002)
 #define H264D_DBG_WARNNING          (0x00000004)
@@ -107,7 +92,7 @@ do{\
 
 
 typedef struct h264d_hal_ctx_t {
-    MppHalApi                hal_api;
+    const MppHalApi          *hal_api;
 
     DXVA_PicParams_H264_MVC  *pp;
     DXVA_Qmatrix_H264        *qm;
@@ -136,4 +121,6 @@ typedef struct h264d_hal_ctx_t {
     const MppDecHwCap        *hw_info;
 } H264dHalCtx_t;
 
+extern const RK_U32 h264_cabac_table[928];
+
 #endif /*__HAL_H264D_GLOBAL_H__*/
diff --git a/mpp/hal/rkdec/h264d/hal_h264d_rkv_reg.c b/mpp/hal/rkdec/h264d/hal_h264d_rkv_reg.c
index 2e1adfcd0..217aeac91 100644
--- a/mpp/hal/rkdec/h264d/hal_h264d_rkv_reg.c
+++ b/mpp/hal/rkdec/h264d/hal_h264d_rkv_reg.c
@@ -221,8 +221,7 @@ const RK_U32 rkv_cabac_table[928] = {
     0x1423091d, 0x430e241d, 0x00000000, 0x00000000
 };
 
-
-
+MPP_RET rkv_h264d_deinit(void *hal);
 static RK_U32 rkv_ver_align(RK_U32 val)
 {
     return MPP_ALIGN(val, 16);
@@ -584,22 +583,6 @@ MPP_RET rkv_h264d_init(void *hal, MppHalCfg *cfg)
     mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, rkv_ver_align);
     mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, rkv_len_align);
 
-    {
-        // report hw_info to parser
-        const MppSocInfo *info = mpp_get_soc_info();
-        const void *hw_info = NULL;
-
-        for (i = 0; i < MPP_ARRAY_ELEMS(info->dec_caps); i++) {
-            if (info->dec_caps[i] && info->dec_caps[i]->type == VPU_CLIENT_RKVDEC) {
-                hw_info = info->dec_caps[i];
-                break;
-            }
-        }
-
-        mpp_assert(hw_info);
-        cfg->hw_info = hw_info;
-    }
-
     (void)cfg;
 __RETURN:
     return MPP_OK;
@@ -892,3 +875,19 @@ MPP_RET rkv_h264d_control(void *hal, MpiCmd cmd_type, void *param)
 __RETURN:
     return ret = MPP_OK;
 }
+
+const MppHalApi hal_h264d_rkvdpu = {
+    .name     = "h264d_rkvdpu",
+    .type     = MPP_CTX_DEC,
+    .coding   = MPP_VIDEO_CodingAVC,
+    .ctx_size = sizeof(H264dRkvRegCtx_t),
+    .flag     = 0,
+    .init     = rkv_h264d_init,
+    .deinit   = rkv_h264d_deinit,
+    .reg_gen  = rkv_h264d_gen_regs,
+    .start    = rkv_h264d_start,
+    .wait     = rkv_h264d_wait,
+    .reset    = rkv_h264d_reset,
+    .flush    = rkv_h264d_flush,
+    .control  = rkv_h264d_control,
+};
diff --git a/mpp/hal/rkdec/h264d/hal_h264d_rkv_reg.h b/mpp/hal/rkdec/h264d/hal_h264d_rkv_reg.h
index 6fbc0d07f..8f89fe0e2 100644
--- a/mpp/hal/rkdec/h264d/hal_h264d_rkv_reg.h
+++ b/mpp/hal/rkdec/h264d/hal_h264d_rkv_reg.h
@@ -234,14 +234,7 @@ typedef struct h264d_rkv_regs_t {
 extern "C" {
 #endif
 
-MPP_RET rkv_h264d_init    (void *hal, MppHalCfg *cfg);
-MPP_RET rkv_h264d_deinit  (void *hal);
-MPP_RET rkv_h264d_gen_regs(void *hal, HalTaskInfo *task);
-MPP_RET rkv_h264d_start   (void *hal, HalTaskInfo *task);
-MPP_RET rkv_h264d_wait    (void *hal, HalTaskInfo *task);
-MPP_RET rkv_h264d_reset   (void *hal);
-MPP_RET rkv_h264d_flush   (void *hal);
-MPP_RET rkv_h264d_control (void *hal, MpiCmd cmd_type, void *param);
+extern const MppHalApi hal_h264d_rkvdpu;
 
 #ifdef __cplusplus
 }
diff --git a/mpp/hal/rkdec/h264d/hal_h264d_vdpu1.c b/mpp/hal/rkdec/h264d/hal_h264d_vdpu1.c
index b56017db2..21808a250 100644
--- a/mpp/hal/rkdec/h264d/hal_h264d_vdpu1.c
+++ b/mpp/hal/rkdec/h264d/hal_h264d_vdpu1.c
@@ -38,6 +38,7 @@ const RK_U32 vdpu1_ref_idx[16] = {
     22, 23, 24, 25, 26, 27, 28, 29
 };
 
+MPP_RET vdpu1_h264d_deinit(void *hal);
 static MPP_RET vdpu1_set_refer_pic_idx(H264dVdpu1Regs_t *p_regs, RK_U32 i,
                                        RK_U16 val)
 {
@@ -742,6 +743,7 @@ MPP_RET vdpu1_h264d_init(void *hal, MppHalCfg *cfg)
     MPP_RET ret = MPP_ERR_UNKNOW;
     H264dHalCtx_t  *p_hal = (H264dHalCtx_t *)hal;
     INP_CHECK(ret, NULL == hal);
+    (void) cfg;
 
     //!< malloc init registers
     MEM_CHECK(ret, p_hal->priv =
@@ -776,23 +778,6 @@ MPP_RET vdpu1_h264d_init(void *hal, MppHalCfg *cfg)
     mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, vdpu_hor_align);
     mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, vdpu_ver_align);
 
-    {
-        // report hw_info to parser
-        const MppSocInfo *info = mpp_get_soc_info();
-        const void *hw_info = NULL;
-        RK_U32 i;
-
-        for (i = 0; i < MPP_ARRAY_ELEMS(info->dec_caps); i++) {
-            if (info->dec_caps[i] && info->dec_caps[i]->type == VPU_CLIENT_VDPU1) {
-                hw_info = info->dec_caps[i];
-                break;
-            }
-        }
-
-        mpp_assert(hw_info);
-        cfg->hw_info = hw_info;
-    }
-
 __RETURN:
     return MPP_OK;
 __FAILED:
@@ -1046,3 +1031,19 @@ MPP_RET vdpu1_h264d_control(void *hal, MpiCmd cmd_type, void *param)
 __RETURN:
     return ret = MPP_OK;
 }
+
+const MppHalApi hal_h264d_vdpu1 = {
+    .name     = "h264d_vdpu1",
+    .type     = MPP_CTX_DEC,
+    .coding   = MPP_VIDEO_CodingAVC,
+    .ctx_size = sizeof(H264dVdpuRegCtx_t),
+    .flag     = 0,
+    .init     = vdpu1_h264d_init,
+    .deinit   = vdpu1_h264d_deinit,
+    .reg_gen  = vdpu1_h264d_gen_regs,
+    .start    = vdpu1_h264d_start,
+    .wait     = vdpu1_h264d_wait,
+    .reset    = vdpu1_h264d_reset,
+    .flush    = vdpu1_h264d_flush,
+    .control  = vdpu1_h264d_control,
+};
diff --git a/mpp/hal/rkdec/h264d/hal_h264d_vdpu1.h b/mpp/hal/rkdec/h264d/hal_h264d_vdpu1.h
index 4bc187b62..3a304595a 100644
--- a/mpp/hal/rkdec/h264d/hal_h264d_vdpu1.h
+++ b/mpp/hal/rkdec/h264d/hal_h264d_vdpu1.h
@@ -24,14 +24,7 @@
 extern "C" {
 #endif
 
-MPP_RET vdpu1_h264d_init    (void *hal, MppHalCfg *cfg);
-MPP_RET vdpu1_h264d_deinit  (void *hal);
-MPP_RET vdpu1_h264d_gen_regs(void *hal, HalTaskInfo *task);
-MPP_RET vdpu1_h264d_start   (void *hal, HalTaskInfo *task);
-MPP_RET vdpu1_h264d_wait    (void *hal, HalTaskInfo *task);
-MPP_RET vdpu1_h264d_reset   (void *hal);
-MPP_RET vdpu1_h264d_flush   (void *hal);
-MPP_RET vdpu1_h264d_control (void *hal, MpiCmd cmd_type, void *param);
+extern const MppHalApi hal_h264d_vdpu1;
 
 #ifdef __cplusplus
 }
diff --git a/mpp/hal/rkdec/h264d/hal_h264d_vdpu2.c b/mpp/hal/rkdec/h264d/hal_h264d_vdpu2.c
index 05c22e898..86cc8f7e7 100644
--- a/mpp/hal/rkdec/h264d/hal_h264d_vdpu2.c
+++ b/mpp/hal/rkdec/h264d/hal_h264d_vdpu2.c
@@ -39,6 +39,7 @@ const RK_U32 vdpu2_ref_idx[16] = {
     92, 93, 94, 95, 96, 97, 98, 99
 };
 
+MPP_RET vdpu2_h264d_deinit(void *hal);
 static MPP_RET set_device_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_reg)
 {
     MPP_RET ret = MPP_ERR_UNKNOW;
@@ -801,6 +802,7 @@ MPP_RET vdpu2_h264d_init(void *hal, MppHalCfg *cfg)
     MPP_RET ret = MPP_ERR_UNKNOW;
     H264dHalCtx_t  *p_hal = (H264dHalCtx_t *)hal;
     INP_CHECK(ret, NULL == hal);
+    (void) cfg;
 
     MEM_CHECK(ret, p_hal->priv = mpp_calloc_size(void,
                                                  sizeof(H264dVdpuPriv_t)));
@@ -834,23 +836,6 @@ MPP_RET vdpu2_h264d_init(void *hal, MppHalCfg *cfg)
     mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, vdpu_hor_align);
     mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, vdpu_ver_align);
 
-    {
-        // report hw_info to parser
-        const MppSocInfo *info = mpp_get_soc_info();
-        const void *hw_info = NULL;
-        RK_U32 i;
-
-        for (i = 0; i < MPP_ARRAY_ELEMS(info->dec_caps); i++) {
-            if (info->dec_caps[i] && info->dec_caps[i]->type == VPU_CLIENT_VDPU2) {
-                hw_info = info->dec_caps[i];
-                break;
-            }
-        }
-
-        mpp_assert(hw_info);
-        cfg->hw_info = hw_info;
-    }
-
 __RETURN:
     return MPP_OK;
 __FAILED:
@@ -955,15 +940,16 @@ MPP_RET vdpu2_h264d_start(void *hal, HalTaskInfo *task)
     RK_U32 w = p_regs->sw110.pic_mb_w * 16;
     RK_U32 h = p_regs->sw110.pic_mb_h * 16;
     RK_U32 cache_en = 1;
-    const char *soc_name = NULL;
+    RockchipSocType soc_type = mpp_get_soc_type();
 
     if (task->dec.flags.parse_err ||
         task->dec.flags.ref_err) {
         goto __RETURN;
     }
 
-    soc_name = mpp_get_soc_name();
-    if (strstr(soc_name, "rk3326") || strstr(soc_name, "px30") || strstr(soc_name, "rk3228H"))
+    if (soc_type == ROCKCHIP_SOC_RK3326 ||
+        soc_type == ROCKCHIP_SOC_PX30 ||
+        soc_type == ROCKCHIP_SOC_RK3228H)
         cache_en = ((w * h) >= (1280 * 720)) ? 1 : 0;
 
     p_regs->sw57.cache_en       = cache_en;
@@ -1130,3 +1116,19 @@ MPP_RET vdpu2_h264d_control(void *hal, MpiCmd cmd_type, void *param)
 __RETURN:
     return ret = MPP_OK;
 }
+
+const MppHalApi hal_h264d_vdpu2 = {
+    .name     = "h264d_vdpu2",
+    .type     = MPP_CTX_DEC,
+    .coding   = MPP_VIDEO_CodingAVC,
+    .ctx_size = sizeof(H264dVdpuRegCtx_t),
+    .flag     = 0,
+    .init     = vdpu2_h264d_init,
+    .deinit   = vdpu2_h264d_deinit,
+    .reg_gen  = vdpu2_h264d_gen_regs,
+    .start    = vdpu2_h264d_start,
+    .wait     = vdpu2_h264d_wait,
+    .reset    = vdpu2_h264d_reset,
+    .flush    = vdpu2_h264d_flush,
+    .control  = vdpu2_h264d_control,
+};
diff --git a/mpp/hal/rkdec/h264d/hal_h264d_vdpu2.h b/mpp/hal/rkdec/h264d/hal_h264d_vdpu2.h
index b4f0eb22a..f3a9a17a0 100644
--- a/mpp/hal/rkdec/h264d/hal_h264d_vdpu2.h
+++ b/mpp/hal/rkdec/h264d/hal_h264d_vdpu2.h
@@ -24,15 +24,7 @@
 extern "C" {
 #endif
 
-MPP_RET vdpu2_h264d_init    (void *hal, MppHalCfg *cfg);
-MPP_RET vdpu2_h264d_deinit  (void *hal);
-MPP_RET vdpu2_h264d_gen_regs(void *hal, HalTaskInfo *task);
-MPP_RET vdpu2_h264d_start   (void *hal, HalTaskInfo *task);
-MPP_RET vdpu2_h264d_wait    (void *hal, HalTaskInfo *task);
-MPP_RET vdpu2_h264d_reset   (void *hal);
-MPP_RET vdpu2_h264d_flush   (void *hal);
-MPP_RET vdpu2_h264d_control (void *hal, MpiCmd cmd_type, void *param);
-
+extern const MppHalApi hal_h264d_vdpu2;
 
 #ifdef __cplusplus
 }
diff --git a/mpp/hal/rkdec/h264d/hal_h264d_vdpu34x.c b/mpp/hal/rkdec/h264d/hal_h264d_vdpu34x.c
index 45081534a..ac303fbac 100644
--- a/mpp/hal/rkdec/h264d/hal_h264d_vdpu34x.c
+++ b/mpp/hal/rkdec/h264d/hal_h264d_vdpu34x.c
@@ -321,6 +321,7 @@ const RK_U32 rkv_cabac_table_v34x[928] = {
     0x1423091d, 0x430e241d, 0x00000000, 0x00000000
 };
 
+MPP_RET vdpu34x_h264d_deinit(void *hal);
 static RK_U32 rkv_ver_align(RK_U32 val)
 {
     return MPP_ALIGN(val, 16);
@@ -746,21 +747,6 @@ MPP_RET vdpu34x_h264d_init(void *hal, MppHalCfg *cfg)
     mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, rkv_ver_align);
     mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, rkv_len_align);
 
-    {
-        // report hw_info to parser
-        const MppSocInfo *info = mpp_get_soc_info();
-        const void *hw_info = NULL;
-
-        for (i = 0; i < MPP_ARRAY_ELEMS(info->dec_caps); i++) {
-            if (info->dec_caps[i] && info->dec_caps[i]->type == VPU_CLIENT_RKVDEC) {
-                hw_info = info->dec_caps[i];
-                break;
-            }
-        }
-
-        mpp_assert(hw_info);
-        cfg->hw_info = hw_info;
-    }
     if (cfg->hal_fbc_adj_cfg) {
         cfg->hal_fbc_adj_cfg->func = vdpu34x_afbc_align_calc;
         cfg->hal_fbc_adj_cfg->expand = 16;
@@ -899,21 +885,14 @@ static void hal_h264d_rcb_info_update(void *hal, Vdpu34xH264dRegSet *regs)
     }
 }
 
-MPP_RET vdpu34x_h264d_gen_regs(void *hal, HalTaskInfo *task)
+static MPP_RET vdpu34x_h264d_setup_colmv_buf(void *hal, RK_U32 width, RK_U32 height)
 {
-    MPP_RET ret = MPP_ERR_UNKNOW;
     H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
-    RK_S32 width = MPP_ALIGN((p_hal->pp->wFrameWidthInMbsMinus1 + 1) << 4, 64);
-    RK_S32 height = MPP_ALIGN((p_hal->pp->wFrameHeightInMbsMinus1 + 1) << 4, 64);
-    Vdpu34xH264dRegCtx *ctx = (Vdpu34xH264dRegCtx *)p_hal->reg_ctx;
-    Vdpu34xH264dRegSet *regs = ctx->regs;
-    RK_S32 mv_size = width * height / 2;
-    INP_CHECK(ret, NULL == p_hal);
+    RK_U32 ctu_size = 16, colmv_size = 4, colmv_byte = 16;
+    RK_U32 colmv_compress = p_hal->pp->frame_mbs_only_flag ? 1 : 0;
+    RK_S32 mv_size;
 
-    if (task->dec.flags.parse_err ||
-        task->dec.flags.ref_err) {
-        goto __RETURN;
-    }
+    mv_size = vdpu34x_get_colmv_size(width, height, ctu_size, colmv_byte, colmv_size, colmv_compress);
 
     /* if is field mode is enabled enlarge colmv buffer and disable colmv compression */
     if (!p_hal->pp->frame_mbs_only_flag)
@@ -930,13 +909,31 @@ MPP_RET vdpu34x_h264d_gen_regs(void *hal, HalTaskInfo *task)
         hal_bufs_init(&p_hal->cmv_bufs);
         if (p_hal->cmv_bufs == NULL) {
             mpp_err_f("colmv bufs init fail");
-            goto __RETURN;
+            return MPP_NOK;
         }
         p_hal->mv_size = mv_size;
         p_hal->mv_count = mpp_buf_slot_get_count(p_hal->frame_slots);
         hal_bufs_setup(p_hal->cmv_bufs, p_hal->mv_count, 1, &size);
     }
 
+    return MPP_OK;
+}
+
+MPP_RET vdpu34x_h264d_gen_regs(void *hal, HalTaskInfo *task)
+{
+    MPP_RET ret = MPP_ERR_UNKNOW;
+    H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
+    RK_S32 width = MPP_ALIGN((p_hal->pp->wFrameWidthInMbsMinus1 + 1) << 4, 64);
+    RK_S32 height = MPP_ALIGN((p_hal->pp->wFrameHeightInMbsMinus1 + 1) << 4, 64);
+    Vdpu34xH264dRegCtx *ctx = (Vdpu34xH264dRegCtx *)p_hal->reg_ctx;
+    Vdpu34xH264dRegSet *regs = ctx->regs;
+    INP_CHECK(ret, NULL == p_hal);
+
+    if (task->dec.flags.parse_err ||
+        task->dec.flags.ref_err) {
+        goto __RETURN;
+    }
+
     if (p_hal->fast_mode) {
         RK_U32 i = 0;
         for (i = 0; i <  MPP_ARRAY_ELEMS(ctx->reg_buf); i++) {
@@ -952,6 +949,9 @@ MPP_RET vdpu34x_h264d_gen_regs(void *hal, HalTaskInfo *task)
             }
         }
     }
+
+    if (vdpu34x_h264d_setup_colmv_buf(hal, width, height))
+        goto __RETURN;
     prepare_spspps(p_hal, (RK_U64 *)&ctx->spspps, sizeof(ctx->spspps));
     prepare_framerps(p_hal, (RK_U64 *)&ctx->rps, sizeof(ctx->rps));
     prepare_scanlist(p_hal, ctx->sclst, sizeof(ctx->sclst));
@@ -1221,3 +1221,19 @@ MPP_RET vdpu34x_h264d_control(void *hal, MpiCmd cmd_type, void *param)
 __RETURN:
     return ret = MPP_OK;
 }
+
+const MppHalApi hal_h264d_vdpu34x = {
+    .name     = "h264d_vdpu34x",
+    .type     = MPP_CTX_DEC,
+    .coding   = MPP_VIDEO_CodingAVC,
+    .ctx_size = sizeof(Vdpu34xH264dRegCtx),
+    .flag     = 0,
+    .init     = vdpu34x_h264d_init,
+    .deinit   = vdpu34x_h264d_deinit,
+    .reg_gen  = vdpu34x_h264d_gen_regs,
+    .start    = vdpu34x_h264d_start,
+    .wait     = vdpu34x_h264d_wait,
+    .reset    = vdpu34x_h264d_reset,
+    .flush    = vdpu34x_h264d_flush,
+    .control  = vdpu34x_h264d_control,
+};
diff --git a/mpp/hal/rkdec/h264d/hal_h264d_vdpu34x.h b/mpp/hal/rkdec/h264d/hal_h264d_vdpu34x.h
index 1067a14e0..25a45a01e 100644
--- a/mpp/hal/rkdec/h264d/hal_h264d_vdpu34x.h
+++ b/mpp/hal/rkdec/h264d/hal_h264d_vdpu34x.h
@@ -24,14 +24,7 @@
 extern "C" {
 #endif
 
-MPP_RET vdpu34x_h264d_init    (void *hal, MppHalCfg *cfg);
-MPP_RET vdpu34x_h264d_deinit  (void *hal);
-MPP_RET vdpu34x_h264d_gen_regs(void *hal, HalTaskInfo *task);
-MPP_RET vdpu34x_h264d_start   (void *hal, HalTaskInfo *task);
-MPP_RET vdpu34x_h264d_wait    (void *hal, HalTaskInfo *task);
-MPP_RET vdpu34x_h264d_reset   (void *hal);
-MPP_RET vdpu34x_h264d_flush   (void *hal);
-MPP_RET vdpu34x_h264d_control (void *hal, MpiCmd cmd_type, void *param);
+extern const MppHalApi hal_h264d_vdpu34x;
 
 #ifdef __cplusplus
 }
diff --git a/mpp/hal/rkdec/h264d/hal_h264d_vdpu382.c b/mpp/hal/rkdec/h264d/hal_h264d_vdpu382.c
index d36c40589..b20ddbed9 100644
--- a/mpp/hal/rkdec/h264d/hal_h264d_vdpu382.c
+++ b/mpp/hal/rkdec/h264d/hal_h264d_vdpu382.c
@@ -327,6 +327,7 @@ const RK_U32 rkv_cabac_table_v382[928] = {
     0x1423091d, 0x430e241d, 0x00000000, 0x00000000
 };
 
+MPP_RET vdpu382_h264d_deinit(void *hal);
 static RK_U32 rkv_ver_align(RK_U32 val)
 {
     return MPP_ALIGN(val, 16);
@@ -767,24 +768,6 @@ MPP_RET vdpu382_h264d_init(void *hal, MppHalCfg *cfg)
     mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, rkv_ver_align);
     mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, rkv_len_align);
 
-    {
-        // report hw_info to parser
-        const MppSocInfo *info = mpp_get_soc_info();
-        const void *hw_info = NULL;
-
-        for (i = 0; i < MPP_ARRAY_ELEMS(info->dec_caps); i++) {
-            if (info->dec_caps[i] && info->dec_caps[i]->type == VPU_CLIENT_RKVDEC) {
-                hw_info = info->dec_caps[i];
-                break;
-            }
-        }
-
-        mpp_assert(hw_info);
-        cfg->hw_info = hw_info;
-
-        p_hal->hw_info = hw_info;
-    }
-
     {
         /* check kernel support err ref hack process */
         const MppServiceCmdCap *cap = mpp_get_mpp_service_cmd_cap();
@@ -938,14 +921,13 @@ static void hal_h264d_rcb_info_update(void *hal, Vdpu382H264dRegSet *regs)
 
 static MPP_RET vdpu382_h264d_setup_colmv_buf(void *hal)
 {
-    MPP_RET ret = MPP_ERR_UNKNOW;
     H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
     RK_S32 width = MPP_ALIGN((p_hal->pp->wFrameWidthInMbsMinus1 + 1) << 4, 64);
     RK_S32 height = MPP_ALIGN((p_hal->pp->wFrameHeightInMbsMinus1 + 1) << 4, 64);
+    RK_U32 ctu_size = 16, colmv_size = 4, colmv_byte = 16;
     RK_S32 mv_size;
 
-    /* the worst case is the frame is error with whole frame */
-    mv_size = width * height;
+    mv_size = vdpu382_get_colmv_size(width, height, ctu_size, colmv_byte, colmv_size, 1);
     if (p_hal->cmv_bufs == NULL || p_hal->mv_size < mv_size) {
         size_t size = mv_size;
 
@@ -957,15 +939,14 @@ static MPP_RET vdpu382_h264d_setup_colmv_buf(void *hal)
         hal_bufs_init(&p_hal->cmv_bufs);
         if (p_hal->cmv_bufs == NULL) {
             mpp_err_f("colmv bufs init fail");
-            goto __RETURN;
+            return MPP_OK;
         }
         p_hal->mv_size = mv_size;
         p_hal->mv_count = mpp_buf_slot_get_count(p_hal->frame_slots);
         hal_bufs_setup(p_hal->cmv_bufs, p_hal->mv_count, 1, &size);
     }
 
-__RETURN:
-    return ret;
+    return MPP_OK;
 }
 
 MPP_RET vdpu382_h264d_gen_regs(void *hal, HalTaskInfo *task)
@@ -997,7 +978,8 @@ MPP_RET vdpu382_h264d_gen_regs(void *hal, HalTaskInfo *task)
             }
         }
     }
-    vdpu382_h264d_setup_colmv_buf(hal);
+    if (vdpu382_h264d_setup_colmv_buf(hal))
+        goto __RETURN;
     prepare_spspps(p_hal, (RK_U64 *)&ctx->spspps, sizeof(ctx->spspps));
     prepare_framerps(p_hal, (RK_U64 *)&ctx->rps, sizeof(ctx->rps));
     prepare_scanlist(p_hal, ctx->sclst, sizeof(ctx->sclst));
@@ -1355,3 +1337,19 @@ MPP_RET vdpu382_h264d_control(void *hal, MpiCmd cmd_type, void *param)
 __RETURN:
     return ret = MPP_OK;
 }
+
+const MppHalApi hal_h264d_vdpu382 = {
+    .name     = "h264d_vdpu382",
+    .type     = MPP_CTX_DEC,
+    .coding   = MPP_VIDEO_CodingAVC,
+    .ctx_size = sizeof(Vdpu382H264dRegCtx),
+    .flag     = 0,
+    .init     = vdpu382_h264d_init,
+    .deinit   = vdpu382_h264d_deinit,
+    .reg_gen  = vdpu382_h264d_gen_regs,
+    .start    = vdpu382_h264d_start,
+    .wait     = vdpu382_h264d_wait,
+    .reset    = vdpu382_h264d_reset,
+    .flush    = vdpu382_h264d_flush,
+    .control  = vdpu382_h264d_control,
+};
diff --git a/mpp/hal/rkdec/h264d/hal_h264d_vdpu382.h b/mpp/hal/rkdec/h264d/hal_h264d_vdpu382.h
index b437b6b7c..9c9b4f354 100644
--- a/mpp/hal/rkdec/h264d/hal_h264d_vdpu382.h
+++ b/mpp/hal/rkdec/h264d/hal_h264d_vdpu382.h
@@ -24,14 +24,7 @@
 extern "C" {
 #endif
 
-MPP_RET vdpu382_h264d_init    (void *hal, MppHalCfg *cfg);
-MPP_RET vdpu382_h264d_deinit  (void *hal);
-MPP_RET vdpu382_h264d_gen_regs(void *hal, HalTaskInfo *task);
-MPP_RET vdpu382_h264d_start   (void *hal, HalTaskInfo *task);
-MPP_RET vdpu382_h264d_wait    (void *hal, HalTaskInfo *task);
-MPP_RET vdpu382_h264d_reset   (void *hal);
-MPP_RET vdpu382_h264d_flush   (void *hal);
-MPP_RET vdpu382_h264d_control (void *hal, MpiCmd cmd_type, void *param);
+extern const MppHalApi hal_h264d_vdpu382;
 
 #ifdef __cplusplus
 }
diff --git a/mpp/hal/rkdec/h264d/hal_h264d_vdpu383.c b/mpp/hal/rkdec/h264d/hal_h264d_vdpu383.c
new file mode 100644
index 000000000..478cf209a
--- /dev/null
+++ b/mpp/hal/rkdec/h264d/hal_h264d_vdpu383.c
@@ -0,0 +1,1127 @@
+/* SPDX-License-Identifier: Apache-2.0 OR MIT */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#define MODULE_TAG "hal_h264d_vdpu383"
+
+#include <string.h>
+
+#include "mpp_env.h"
+#include "mpp_mem.h"
+#include "mpp_common.h"
+#include "mpp_bitput.h"
+#include "mpp_buffer_impl.h"
+
+#include "hal_h264d_global.h"
+#include "hal_h264d_vdpu383.h"
+#include "vdpu383_h264d.h"
+#include "mpp_dec_cb_param.h"
+
+/* Number registers for the decoder */
+#define DEC_VDPU383_REGISTERS       276
+
+#define VDPU383_CABAC_TAB_SIZE      (928*4 + 128)       /* bytes */
+#define VDPU383_SPSPPS_SIZE         (168 + 128)     /* bytes */
+#define VDPU383_RPS_SIZE            (128 + 128 + 128)   /* bytes */
+#define VDPU383_SCALING_LIST_SIZE   (6*16+2*64 + 128)   /* bytes */
+#define VDPU383_ERROR_INFO_SIZE     (256*144*4)         /* bytes */
+#define H264_CTU_SIZE               16
+
+#define VDPU383_CABAC_TAB_ALIGNED_SIZE      (MPP_ALIGN(VDPU383_CABAC_TAB_SIZE, SZ_4K))
+#define VDPU383_ERROR_INFO_ALIGNED_SIZE     (0)
+#define VDPU383_SPSPPS_ALIGNED_SIZE         (MPP_ALIGN(VDPU383_SPSPPS_SIZE, SZ_4K))
+#define VDPU383_RPS_ALIGNED_SIZE            (MPP_ALIGN(VDPU383_RPS_SIZE, SZ_4K))
+#define VDPU383_SCALING_LIST_ALIGNED_SIZE   (MPP_ALIGN(VDPU383_SCALING_LIST_SIZE, SZ_4K))
+#define VDPU383_STREAM_INFO_SET_SIZE        (VDPU383_SPSPPS_ALIGNED_SIZE + \
+                                             VDPU383_RPS_ALIGNED_SIZE + \
+                                             VDPU383_SCALING_LIST_ALIGNED_SIZE)
+
+#define VDPU383_CABAC_TAB_OFFSET            (0)
+#define VDPU383_ERROR_INFO_OFFSET           (VDPU383_CABAC_TAB_OFFSET + VDPU383_CABAC_TAB_ALIGNED_SIZE)
+#define VDPU383_STREAM_INFO_OFFSET_BASE     (VDPU383_ERROR_INFO_OFFSET + VDPU383_ERROR_INFO_ALIGNED_SIZE)
+#define VDPU383_SPSPPS_OFFSET(pos)          (VDPU383_STREAM_INFO_OFFSET_BASE + (VDPU383_STREAM_INFO_SET_SIZE * pos))
+#define VDPU383_RPS_OFFSET(pos)             (VDPU383_SPSPPS_OFFSET(pos) + VDPU383_SPSPPS_ALIGNED_SIZE)
+#define VDPU383_SCALING_LIST_OFFSET(pos)    (VDPU383_RPS_OFFSET(pos) + VDPU383_RPS_ALIGNED_SIZE)
+#define VDPU383_INFO_BUFFER_SIZE(cnt)       (VDPU383_STREAM_INFO_OFFSET_BASE + (VDPU383_STREAM_INFO_SET_SIZE * cnt))
+
+#define VDPU383_SPS_PPS_LEN            (MPP_ALIGN(1338, 128) / 8) // byte, 1338 bit
+
+#define SET_REF_INFO(regs, index, field, value)\
+    do{ \
+        switch(index){\
+        case 0: regs.reg99.ref0_##field = value; break;\
+        case 1: regs.reg99.ref1_##field = value; break;\
+        case 2: regs.reg99.ref2_##field = value; break;\
+        case 3: regs.reg99.ref3_##field = value; break;\
+        case 4: regs.reg100.ref4_##field = value; break;\
+        case 5: regs.reg100.ref5_##field = value; break;\
+        case 6: regs.reg100.ref6_##field = value; break;\
+        case 7: regs.reg100.ref7_##field = value; break;\
+        case 8: regs.reg101.ref8_##field = value; break;\
+        case 9: regs.reg101.ref9_##field = value; break;\
+        case 10: regs.reg101.ref10_##field = value; break;\
+        case 11: regs.reg101.ref11_##field = value; break;\
+        case 12: regs.reg102.ref12_##field = value; break;\
+        case 13: regs.reg102.ref13_##field = value; break;\
+        case 14: regs.reg102.ref14_##field = value; break;\
+        case 15: regs.reg102.ref15_##field = value; break;\
+        default: break;}\
+    }while(0)
+
+#define VDPU383_FAST_REG_SET_CNT    3
+
+typedef struct h264d_rkv_buf_t {
+    RK_U32              valid;
+    Vdpu383H264dRegSet  *regs;
+} H264dRkvBuf_t;
+
+typedef struct Vdpu383H264dRegCtx_t {
+    RK_U8               spspps[VDPU383_SPS_PPS_LEN];
+    RK_U8               rps[VDPU383_RPS_SIZE];
+    RK_U8               sclst[VDPU383_SCALING_LIST_SIZE];
+
+    MppBuffer           bufs;
+    RK_S32              bufs_fd;
+    void                *bufs_ptr;
+    RK_U32              offset_cabac;
+    RK_U32              offset_errinfo;
+    RK_U32              offset_spspps[VDPU383_FAST_REG_SET_CNT];
+    RK_U32              offset_rps[VDPU383_FAST_REG_SET_CNT];
+    RK_U32              offset_sclst[VDPU383_FAST_REG_SET_CNT];
+
+    H264dRkvBuf_t       reg_buf[VDPU383_FAST_REG_SET_CNT];
+
+    RK_U32              spspps_offset;
+    RK_U32              rps_offset;
+    RK_U32              sclst_offset;
+
+    RK_S32              width;
+    RK_S32              height;
+    /* rcb buffers info */
+    RK_U32              bit_depth;
+    RK_U32              mbaff;
+    RK_U32              chroma_format_idc;
+
+    RK_S32              rcb_buf_size;
+    Vdpu383RcbInfo      rcb_info[RCB_BUF_COUNT];
+    MppBuffer           rcb_buf[VDPU383_FAST_REG_SET_CNT];
+
+    Vdpu383H264dRegSet  *regs;
+    HalBufs             origin_bufs;
+} Vdpu383H264dRegCtx;
+
+MPP_RET vdpu383_h264d_deinit(void *hal);
+static RK_U32 rkv_ver_align(RK_U32 val)
+{
+    return MPP_ALIGN(val, 16);
+}
+
+static RK_U32 rkv_len_align(RK_U32 val)
+{
+    return (2 * MPP_ALIGN(val, 16));
+}
+
+static RK_U32 rkv_len_align_422(RK_U32 val)
+{
+    return ((5 * MPP_ALIGN(val, 16)) / 2);
+}
+
+static MPP_RET vdpu383_setup_scale_origin_bufs(H264dHalCtx_t *p_hal, MppFrame mframe)
+{
+    Vdpu383H264dRegCtx *ctx = (Vdpu383H264dRegCtx *)p_hal->reg_ctx;
+    /* for 8K FrameBuf scale mode */
+    size_t origin_buf_size = 0;
+
+    origin_buf_size = mpp_frame_get_buf_size(mframe);
+
+    if (!origin_buf_size) {
+        mpp_err_f("origin_bufs get buf size failed\n");
+        return MPP_NOK;
+    }
+    if (ctx->origin_bufs) {
+        hal_bufs_deinit(ctx->origin_bufs);
+        ctx->origin_bufs = NULL;
+    }
+    hal_bufs_init(&ctx->origin_bufs);
+    if (!ctx->origin_bufs) {
+        mpp_err_f("origin_bufs init fail\n");
+        return MPP_ERR_NOMEM;
+    }
+    hal_bufs_setup(ctx->origin_bufs, 16, 1, &origin_buf_size);
+
+    return MPP_OK;
+}
+
+static MPP_RET prepare_spspps(H264dHalCtx_t *p_hal, RK_U64 *data, RK_U32 len)
+{
+    RK_S32 i = 0;
+    RK_S32 is_long_term = 0, voidx = 0;
+    DXVA_PicParams_H264_MVC *pp = p_hal->pp;
+    RK_U32 tmp = 0;
+    BitputCtx_t bp;
+
+    mpp_set_bitput_ctx(&bp, data, len);
+
+    if (!p_hal->fast_mode && !pp->spspps_update) {
+        bp.index = 2;
+        bp.bitpos = 24;
+        bp.bvalue = bp.pbuf[bp.index] & 0xFFFFFF;
+    } else {
+        RK_U32 pic_width, pic_height;
+
+        //!< sps syntax
+        pic_width   = 16 * (pp->wFrameWidthInMbsMinus1 + 1);
+        pic_height  = 16 * (pp->wFrameHeightInMbsMinus1 + 1);
+        pic_height *= (2 - pp->frame_mbs_only_flag);
+        pic_height /= (1 + pp->field_pic_flag);
+        mpp_put_bits(&bp, pp->seq_parameter_set_id, 4);
+        mpp_put_bits(&bp, pp->profile_idc, 8);
+        mpp_put_bits(&bp, pp->constraint_set3_flag, 1);
+        mpp_put_bits(&bp, pp->chroma_format_idc, 2);
+        mpp_put_bits(&bp, pp->bit_depth_luma_minus8, 3);
+        mpp_put_bits(&bp, pp->bit_depth_chroma_minus8, 3);
+        mpp_put_bits(&bp, 0, 1); // set 0
+        mpp_put_bits(&bp, pp->log2_max_frame_num_minus4, 4);
+        mpp_put_bits(&bp, pp->num_ref_frames, 5);
+        mpp_put_bits(&bp, pp->pic_order_cnt_type, 2);
+        mpp_put_bits(&bp, pp->log2_max_pic_order_cnt_lsb_minus4, 4);
+        mpp_put_bits(&bp, pp->delta_pic_order_always_zero_flag, 1);
+        mpp_put_bits(&bp, pic_width, 16);
+        mpp_put_bits(&bp, pic_height, 16);
+        mpp_put_bits(&bp, pp->frame_mbs_only_flag, 1);
+        mpp_put_bits(&bp, pp->MbaffFrameFlag, 1);
+        mpp_put_bits(&bp, pp->direct_8x8_inference_flag, 1);
+        /* multi-view */
+        mpp_put_bits(&bp, pp->mvc_extension_enable, 1);
+        if (pp->mvc_extension_enable) {
+            mpp_put_bits(&bp, (pp->num_views_minus1 + 1), 2);
+            mpp_put_bits(&bp, pp->view_id[0], 10);
+            mpp_put_bits(&bp, pp->view_id[1], 10);
+        } else {
+            mpp_put_bits(&bp, 0, 22);
+        }
+        // hw_fifo_align_bits(&bp, 128);
+        //!< pps syntax
+        mpp_put_bits(&bp, pp->pps_pic_parameter_set_id, 8);
+        mpp_put_bits(&bp, pp->pps_seq_parameter_set_id, 5);
+        mpp_put_bits(&bp, pp->entropy_coding_mode_flag, 1);
+        mpp_put_bits(&bp, pp->pic_order_present_flag, 1);
+
+        mpp_put_bits(&bp, pp->num_ref_idx_l0_active_minus1, 5);
+        mpp_put_bits(&bp, pp->num_ref_idx_l1_active_minus1, 5);
+        mpp_put_bits(&bp, pp->weighted_pred_flag, 1);
+        mpp_put_bits(&bp, pp->weighted_bipred_idc, 2);
+        mpp_put_bits(&bp, pp->pic_init_qp_minus26, 7);
+        mpp_put_bits(&bp, pp->pic_init_qs_minus26, 6);
+        mpp_put_bits(&bp, pp->chroma_qp_index_offset, 5);
+        mpp_put_bits(&bp, pp->deblocking_filter_control_present_flag, 1);
+        mpp_put_bits(&bp, pp->constrained_intra_pred_flag, 1);
+        mpp_put_bits(&bp, pp->redundant_pic_cnt_present_flag, 1);
+        mpp_put_bits(&bp, pp->transform_8x8_mode_flag, 1);
+        mpp_put_bits(&bp, pp->second_chroma_qp_index_offset, 5);
+        mpp_put_bits(&bp, pp->scaleing_list_enable_flag, 1);
+    }
+
+    //!< set dpb
+    for (i = 0; i < 16; i++) {
+        is_long_term = (pp->RefFrameList[i].bPicEntry != 0xff) ? pp->RefFrameList[i].AssociatedFlag : 0;
+        tmp |= (RK_U32)(is_long_term & 0x1) << i;
+    }
+    for (i = 0; i < 16; i++) {
+        voidx = (pp->RefFrameList[i].bPicEntry != 0xff) ? pp->RefPicLayerIdList[i] : 0;
+        tmp |= (RK_U32)(voidx & 0x1) << (i + 16);
+    }
+    mpp_put_bits(&bp, tmp, 32);
+    /* set current frame */
+    mpp_put_bits(&bp, pp->field_pic_flag, 1);
+    mpp_put_bits(&bp, (pp->field_pic_flag && pp->CurrPic.AssociatedFlag), 1);
+
+    mpp_put_bits(&bp, pp->CurrFieldOrderCnt[0], 32);
+    mpp_put_bits(&bp, pp->CurrFieldOrderCnt[1], 32);
+
+    /* refer poc */
+    for (i = 0; i < 16; i++) {
+        mpp_put_bits(&bp, pp->FieldOrderCntList[i][0], 32);
+        mpp_put_bits(&bp, pp->FieldOrderCntList[i][1], 32);
+    }
+
+    tmp = 0;
+    for (i = 0; i < 16; i++) {
+        RK_U32 field_flag = (pp->RefPicFiledFlags >> i) & 0x01;
+
+        tmp |= field_flag << i;
+    }
+    for (i = 0; i < 16; i++) {
+        RK_U32 top_used = (pp->UsedForReferenceFlags >> (2 * i + 0)) & 0x01;
+
+        tmp |= top_used << (i + 16);
+    }
+    mpp_put_bits(&bp, tmp, 32);
+
+    tmp = 0;
+    for (i = 0; i < 16; i++) {
+        RK_U32 bot_used = (pp->UsedForReferenceFlags >> (2 * i + 1)) & 0x01;
+
+        tmp |= bot_used << i;
+    }
+    for (i = 0; i < 16; i++) {
+        RK_U32 ref_colmv_used = (pp->RefPicColmvUsedFlags >> i) & 0x01;
+
+        tmp |= ref_colmv_used << (i + 16);
+    }
+    mpp_put_bits(&bp, tmp, 32);
+    mpp_put_align(&bp, 64, 0);//128
+
+#ifdef DUMP_VDPU383_DATAS
+    {
+        char *cur_fname = "global_cfg.dat";
+        memset(dump_cur_fname_path, 0, sizeof(dump_cur_fname_path));
+        sprintf(dump_cur_fname_path, "%s/%s", dump_cur_dir, cur_fname);
+        dump_data_to_file(dump_cur_fname_path, (void *)bp.pbuf, 64 * bp.index + bp.bitpos, 64, 0);
+    }
+#endif
+
+    return MPP_OK;
+}
+
+static MPP_RET prepare_framerps(H264dHalCtx_t *p_hal, RK_U64 *data, RK_U32 len)
+{
+    RK_S32 i = 0, j = 0;
+    RK_S32 dpb_idx = 0, voidx = 0;
+    RK_S32 dpb_valid = 0, bottom_flag = 0;
+    RK_U32 max_frame_num = 0;
+    RK_U16 frame_num_wrap = 0;
+    RK_U32 tmp = 0;
+
+    BitputCtx_t bp;
+    DXVA_PicParams_H264_MVC *pp = p_hal->pp;
+
+    mpp_set_bitput_ctx(&bp, data, len);
+
+    max_frame_num = 1 << (pp->log2_max_frame_num_minus4 + 4);
+    for (i = 0; i < 16; i++) {
+        if ((pp->NonExistingFrameFlags >> i) & 0x01) {
+            frame_num_wrap = 0;
+        } else {
+            if (pp->RefFrameList[i].AssociatedFlag) {
+                frame_num_wrap = pp->FrameNumList[i];
+            } else {
+                frame_num_wrap = (pp->FrameNumList[i] > pp->frame_num) ?
+                                 (pp->FrameNumList[i] - max_frame_num) : pp->FrameNumList[i];
+            }
+        }
+        mpp_put_bits(&bp, frame_num_wrap, 16);
+    }
+
+    tmp = 0;
+    for (i = 0; i < 16; i++) {
+        tmp |= (RK_U32)pp->RefPicLayerIdList[i] << (i + 16);
+    }
+    mpp_put_bits(&bp, tmp, 32);
+
+    for (i = 0; i < 32; i++) {
+        tmp = 0;
+        dpb_valid = (p_hal->slice_long[0].RefPicList[0][i].bPicEntry == 0xff) ? 0 : 1;
+        dpb_idx = dpb_valid ? p_hal->slice_long[0].RefPicList[0][i].Index7Bits : 0;
+        bottom_flag = dpb_valid ? p_hal->slice_long[0].RefPicList[0][i].AssociatedFlag : 0;
+        voidx = dpb_valid ? pp->RefPicLayerIdList[dpb_idx] : 0;
+
+        tmp |= (RK_U32)(dpb_idx | (dpb_valid << 4)) & 0x1f;
+        tmp |= (RK_U32)(bottom_flag & 0x1) << 5;
+        if (dpb_valid)
+            tmp |= (RK_U32)(voidx & 0x1) << 6;
+        mpp_put_bits(&bp, tmp, 7);
+    }
+
+    for (j = 1; j < 3; j++) {
+        for (i = 0; i < 32; i++) {
+            tmp = 0;
+            dpb_valid = (p_hal->slice_long[0].RefPicList[j][i].bPicEntry == 0xff) ? 0 : 1;
+            dpb_idx = dpb_valid ? p_hal->slice_long[0].RefPicList[j][i].Index7Bits : 0;
+            bottom_flag = dpb_valid ? p_hal->slice_long[0].RefPicList[j][i].AssociatedFlag : 0;
+            voidx = dpb_valid ? pp->RefPicLayerIdList[dpb_idx] : 0;
+            tmp |= (RK_U32)(dpb_idx | (dpb_valid << 4)) & 0x1f;
+            tmp |= (RK_U32)(bottom_flag & 0x1) << 5;
+            if (dpb_valid)
+                tmp |= (RK_U32)(voidx & 0x1) << 6;
+            mpp_put_bits(&bp, tmp, 7);
+        }
+    }
+
+    mpp_put_align(&bp, 128, 0);
+
+#ifdef DUMP_VDPU383_DATAS
+    {
+        char *cur_fname = "rps.dat";
+        memset(dump_cur_fname_path, 0, sizeof(dump_cur_fname_path));
+        sprintf(dump_cur_fname_path, "%s/%s", dump_cur_dir, cur_fname);
+        dump_data_to_file(dump_cur_fname_path, (void *)bp.pbuf, 64 * bp.index + bp.bitpos, 64, 0);
+    }
+#endif
+
+    return MPP_OK;
+}
+
+static MPP_RET prepare_scanlist(H264dHalCtx_t *p_hal, RK_U8 *data, RK_U32 len)
+{
+    RK_U32 i = 0, j = 0, n = 0;
+
+    if (!p_hal->pp->scaleing_list_enable_flag)
+        return MPP_OK;
+
+    for (i = 0; i < 6; i++) { //4x4, 6 lists
+        /* dump by block4x4, vectial direction */
+        for (j = 0; j < 4; j++) {
+            data[n++] = p_hal->qm->bScalingLists4x4[i][j * 4 + 0];
+            data[n++] = p_hal->qm->bScalingLists4x4[i][j * 4 + 1];
+            data[n++] = p_hal->qm->bScalingLists4x4[i][j * 4 + 2];
+            data[n++] = p_hal->qm->bScalingLists4x4[i][j * 4 + 3];
+        }
+    }
+
+    for (i = 0; i < 2; i++) { //8x8, 2 lists
+        RK_U32 blk4_x = 0, blk4_y = 0;
+
+        /* dump by block4x4, vectial direction */
+        for (blk4_y = 0; blk4_y < 8; blk4_y += 4) {
+            for (blk4_x = 0; blk4_x < 8; blk4_x += 4) {
+                RK_U32 pos = blk4_y * 8 + blk4_x;
+
+                for (j = 0; j < 4; j++) {
+                    data[n++] = p_hal->qm->bScalingLists8x8[i][pos + j * 8 + 0];
+                    data[n++] = p_hal->qm->bScalingLists8x8[i][pos + j * 8 + 1];
+                    data[n++] = p_hal->qm->bScalingLists8x8[i][pos + j * 8 + 2];
+                    data[n++] = p_hal->qm->bScalingLists8x8[i][pos + j * 8 + 3];
+                }
+            }
+        }
+    }
+
+    mpp_assert(n <= len);
+
+#ifdef DUMP_VDPU383_DATAS
+    {
+        char *cur_fname = "scanlist.dat";
+        memset(dump_cur_fname_path, 0, sizeof(dump_cur_fname_path));
+        sprintf(dump_cur_fname_path, "%s/%s", dump_cur_dir, cur_fname);
+        dump_data_to_file(dump_cur_fname_path, (void *)data, 8 * n, 128, 0);
+    }
+#endif
+
+    return MPP_OK;
+}
+
+static MPP_RET set_registers(H264dHalCtx_t *p_hal, Vdpu383H264dRegSet *regs, HalTaskInfo *task)
+{
+    DXVA_PicParams_H264_MVC *pp = p_hal->pp;
+    HalBuf *mv_buf = NULL;
+    HalBuf *origin_buf = NULL;
+    Vdpu383H264dRegCtx *ctx = (Vdpu383H264dRegCtx *)p_hal->reg_ctx;
+
+    // memset(regs, 0, sizeof(Vdpu383H264dRegSet));
+    regs->h264d_paras.reg66_stream_len = p_hal->strm_len;
+
+    //!< caculate the yuv_frame_size
+    {
+        MppFrame mframe = NULL;
+        RK_U32 hor_virstride = 0;
+        RK_U32 ver_virstride = 0;
+        RK_U32 y_virstride = 0;
+        RK_U32 uv_virstride = 0;
+
+        mpp_buf_slot_get_prop(p_hal->frame_slots, pp->CurrPic.Index7Bits, SLOT_FRAME_PTR, &mframe);
+        hor_virstride = mpp_frame_get_hor_stride(mframe);
+        ver_virstride = mpp_frame_get_ver_stride(mframe);
+        y_virstride = hor_virstride * ver_virstride;
+        uv_virstride = hor_virstride * ver_virstride / 2;
+
+        if (MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(mframe))) {
+            RK_U32 pixel_width = MPP_ALIGN(mpp_frame_get_width(mframe), 64);
+            RK_U32 fbd_offset;
+
+            fbd_offset = pixel_width * MPP_ALIGN(ver_virstride, 64) / 16;
+
+            regs->ctrl_regs.reg9.fbc_e = 1;
+            regs->h264d_paras.reg68_hor_virstride = pixel_width / 64;
+            regs->h264d_addrs.reg193_fbc_payload_offset = fbd_offset;
+        } else if (MPP_FRAME_FMT_IS_TILE(mpp_frame_get_fmt(mframe))) {
+            regs->ctrl_regs.reg9.tile_e = 1;
+            regs->h264d_paras.reg68_hor_virstride = hor_virstride * 6 / 16;
+            regs->h264d_paras.reg70_y_virstride = (y_virstride + uv_virstride) / 16;
+        } else {
+            regs->ctrl_regs.reg9.fbc_e = 0;
+            regs->h264d_paras.reg68_hor_virstride = hor_virstride / 16;
+            regs->h264d_paras.reg69_raster_uv_hor_virstride = hor_virstride / 16;
+            regs->h264d_paras.reg70_y_virstride = y_virstride / 16;
+        }
+    }
+    //!< set current
+    {
+        MppBuffer mbuffer = NULL;
+        RK_S32 fd = -1;
+
+        mpp_buf_slot_get_prop(p_hal->frame_slots, pp->CurrPic.Index7Bits, SLOT_BUFFER, &mbuffer);
+        fd = mpp_buffer_get_fd(mbuffer);
+        regs->h264d_addrs.reg168_decout_base = fd;
+        regs->h264d_addrs.reg192_payload_st_cur_base = fd;
+
+        //colmv_cur_base
+        mv_buf = hal_bufs_get_buf(p_hal->cmv_bufs, pp->CurrPic.Index7Bits);
+        regs->h264d_addrs.reg216_colmv_cur_base = mpp_buffer_get_fd(mv_buf->buf[0]);
+        regs->h264d_addrs.reg169_error_ref_base = fd;
+    }
+    //!< set reference
+    {
+        RK_S32 i = 0;
+        RK_S32 fd = -1;
+        RK_S32 ref_index = -1;
+        RK_S32 near_index = -1;
+        MppBuffer mbuffer = NULL;
+        RK_U32 min_frame_num  = 0;
+        MppFrame mframe = NULL;
+
+        for (i = 0; i < 15; i++) {
+            if (pp->RefFrameList[i].bPicEntry != 0xff) {
+                ref_index = pp->RefFrameList[i].Index7Bits;
+                near_index = pp->RefFrameList[i].Index7Bits;
+            } else {
+                ref_index = (near_index < 0) ? pp->CurrPic.Index7Bits : near_index;
+            }
+            /* mark 3 to differ from current frame */
+            mpp_buf_slot_get_prop(p_hal->frame_slots, ref_index, SLOT_BUFFER, &mbuffer);
+            mpp_buf_slot_get_prop(p_hal->frame_slots, ref_index, SLOT_FRAME_PTR, &mframe);
+            if (ctx->origin_bufs && mpp_frame_get_thumbnail_en(mframe) == MPP_FRAME_THUMBNAIL_ONLY) {
+                origin_buf = hal_bufs_get_buf(ctx->origin_bufs, ref_index);
+                mbuffer = origin_buf->buf[0];
+            }
+
+            if (pp->FrameNumList[i] < pp->frame_num &&
+                pp->FrameNumList[i] > min_frame_num &&
+                (!mpp_frame_get_errinfo(mframe))) {
+                min_frame_num = pp->FrameNumList[i];
+                regs->h264d_addrs.reg169_error_ref_base = mpp_buffer_get_fd(mbuffer);
+            }
+
+            fd = mpp_buffer_get_fd(mbuffer);
+            regs->h264d_addrs.reg170_185_ref_base[i] = fd;
+            regs->h264d_addrs.reg195_210_payload_st_ref_base[i] = fd;
+            mv_buf = hal_bufs_get_buf(p_hal->cmv_bufs, ref_index);
+            regs->h264d_addrs.reg217_232_colmv_ref_base[i] = mpp_buffer_get_fd(mv_buf->buf[0]);
+        }
+
+        if (pp->RefFrameList[15].bPicEntry != 0xff) {
+            ref_index = pp->RefFrameList[15].Index7Bits;
+        } else {
+            ref_index = (near_index < 0) ? pp->CurrPic.Index7Bits : near_index;
+        }
+
+        mpp_buf_slot_get_prop(p_hal->frame_slots, ref_index, SLOT_BUFFER, &mbuffer);
+        fd = mpp_buffer_get_fd(mbuffer);
+        if (mpp_frame_get_thumbnail_en(mframe) == 2) {
+            origin_buf = hal_bufs_get_buf(ctx->origin_bufs, ref_index);
+            fd = mpp_buffer_get_fd(origin_buf->buf[0]);
+        }
+        regs->h264d_addrs.reg170_185_ref_base[15] = fd;
+        regs->h264d_addrs.reg195_210_payload_st_ref_base[15] = fd;
+        mv_buf = hal_bufs_get_buf(p_hal->cmv_bufs, ref_index);
+        regs->h264d_addrs.reg217_232_colmv_ref_base[15] = mpp_buffer_get_fd(mv_buf->buf[0]);
+    }
+    {
+        MppBuffer mbuffer = NULL;
+        Vdpu383H264dRegCtx *reg_ctx = (Vdpu383H264dRegCtx *)p_hal->reg_ctx;
+
+        mpp_buf_slot_get_prop(p_hal->packet_slots, task->dec.input, SLOT_BUFFER, &mbuffer);
+        regs->common_addr.reg128_strm_base = mpp_buffer_get_fd(mbuffer);
+        // regs->h264d_paras.reg65_strm_start_bit = 2 * 8;
+#ifdef DUMP_VDPU383_DATAS
+        {
+            char *cur_fname = "stream_in.dat";
+            memset(dump_cur_fname_path, 0, sizeof(dump_cur_fname_path));
+            sprintf(dump_cur_fname_path, "%s/%s", dump_cur_dir, cur_fname);
+            dump_data_to_file(dump_cur_fname_path, (void *)mpp_buffer_get_ptr(mbuffer),
+                              8 * p_hal->strm_len, 128, 0);
+        }
+#endif
+
+        regs->common_addr.reg130_cabactbl_base = reg_ctx->bufs_fd;
+        mpp_dev_set_reg_offset(p_hal->dev, 130, reg_ctx->offset_cabac);
+    }
+
+    {
+        //scale down config
+        MppFrame mframe = NULL;
+        MppBuffer mbuffer = NULL;
+        RK_S32 fd = -1;
+        MppFrameThumbnailMode thumbnail_mode;
+
+        mpp_buf_slot_get_prop(p_hal->frame_slots, pp->CurrPic.Index7Bits, SLOT_BUFFER, &mbuffer);
+        mpp_buf_slot_get_prop(p_hal->frame_slots, pp->CurrPic.Index7Bits,
+                              SLOT_FRAME_PTR, &mframe);
+        fd = mpp_buffer_get_fd(mbuffer);
+        thumbnail_mode = mpp_frame_get_thumbnail_en(mframe);
+        switch (thumbnail_mode) {
+        case MPP_FRAME_THUMBNAIL_ONLY:
+            regs->common_addr.reg133_scale_down_base = fd;
+            origin_buf = hal_bufs_get_buf(ctx->origin_bufs, pp->CurrPic.Index7Bits);
+            fd = mpp_buffer_get_fd(origin_buf->buf[0]);
+            regs->h264d_addrs.reg168_decout_base = fd;
+            regs->h264d_addrs.reg192_payload_st_cur_base = fd;
+            regs->h264d_addrs.reg169_error_ref_base = fd;
+            vdpu383_setup_down_scale(mframe, p_hal->dev, &regs->ctrl_regs, (void*)&regs->h264d_paras);
+            break;
+        case MPP_FRAME_THUMBNAIL_MIXED:
+            regs->common_addr.reg133_scale_down_base = fd;
+            vdpu383_setup_down_scale(mframe, p_hal->dev, &regs->ctrl_regs, (void*)&regs->h264d_paras);
+            break;
+        case MPP_FRAME_THUMBNAIL_NONE:
+        default:
+            regs->ctrl_regs.reg9.scale_down_en = 0;
+            break;
+        }
+    }
+
+    return MPP_OK;
+}
+
+static MPP_RET init_ctrl_regs(Vdpu383H264dRegSet *regs)
+{
+    Vdpu383CtrlReg *ctrl_regs = &regs->ctrl_regs;
+
+    ctrl_regs->reg8_dec_mode = 1;  //!< h264
+    ctrl_regs->reg9.buf_empty_en = 0;
+
+    ctrl_regs->reg10.strmd_auto_gating_e      = 1;
+    ctrl_regs->reg10.inter_auto_gating_e      = 1;
+    ctrl_regs->reg10.intra_auto_gating_e      = 1;
+    ctrl_regs->reg10.transd_auto_gating_e     = 1;
+    ctrl_regs->reg10.recon_auto_gating_e      = 1;
+    ctrl_regs->reg10.filterd_auto_gating_e    = 1;
+    ctrl_regs->reg10.bus_auto_gating_e        = 1;
+    ctrl_regs->reg10.ctrl_auto_gating_e       = 1;
+    ctrl_regs->reg10.rcb_auto_gating_e        = 1;
+    ctrl_regs->reg10.err_prc_auto_gating_e    = 1;
+
+    ctrl_regs->reg13_core_timeout_threshold = 0xffffff;
+
+    ctrl_regs->reg16.error_proc_disable = 1;
+    ctrl_regs->reg16.error_spread_disable = 0;
+    ctrl_regs->reg16.roi_error_ctu_cal_en = 0;
+
+    ctrl_regs->reg20_cabac_error_en_lowbits = 0xfffedfff;
+    ctrl_regs->reg21_cabac_error_en_highbits = 0x0ffbf9ff;
+
+    /* performance */
+    ctrl_regs->reg28.axi_perf_work_e = 1;
+    ctrl_regs->reg28.axi_cnt_type = 1;
+    ctrl_regs->reg28.rd_latency_id = 11;
+
+    ctrl_regs->reg29.addr_align_type = 2;
+    ctrl_regs->reg29.ar_cnt_id_type = 0;
+    ctrl_regs->reg29.aw_cnt_id_type = 0;
+    ctrl_regs->reg29.ar_count_id = 0xa;
+    ctrl_regs->reg29.aw_count_id = 0;
+    ctrl_regs->reg29.rd_band_width_mode = 0;
+
+    return MPP_OK;
+}
+
+MPP_RET vdpu383_h264d_init(void *hal, MppHalCfg *cfg)
+{
+    MPP_RET ret = MPP_ERR_UNKNOW;
+    H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
+
+    INP_CHECK(ret, NULL == p_hal);
+    (void) cfg;
+
+    MEM_CHECK(ret, p_hal->reg_ctx = mpp_calloc_size(void, sizeof(Vdpu383H264dRegCtx)));
+    Vdpu383H264dRegCtx *reg_ctx = (Vdpu383H264dRegCtx *)p_hal->reg_ctx;
+    RK_U32 max_cnt = p_hal->fast_mode ? VDPU383_FAST_REG_SET_CNT : 1;
+    RK_U32 i = 0;
+
+    //!< malloc buffers
+    FUN_CHECK(ret = mpp_buffer_get(p_hal->buf_group, &reg_ctx->bufs,
+                                   VDPU383_INFO_BUFFER_SIZE(max_cnt)));
+    reg_ctx->bufs_fd = mpp_buffer_get_fd(reg_ctx->bufs);
+    reg_ctx->bufs_ptr = mpp_buffer_get_ptr(reg_ctx->bufs);
+    reg_ctx->offset_cabac = VDPU383_CABAC_TAB_OFFSET;
+    reg_ctx->offset_errinfo = VDPU383_ERROR_INFO_OFFSET;
+    for (i = 0; i < max_cnt; i++) {
+        reg_ctx->reg_buf[i].regs = mpp_calloc(Vdpu383H264dRegSet, 1);
+        init_ctrl_regs(reg_ctx->reg_buf[i].regs);
+        reg_ctx->offset_spspps[i] = VDPU383_SPSPPS_OFFSET(i);
+        reg_ctx->offset_rps[i] = VDPU383_RPS_OFFSET(i);
+        reg_ctx->offset_sclst[i] = VDPU383_SCALING_LIST_OFFSET(i);
+    }
+
+    mpp_buffer_attach_dev(reg_ctx->bufs, p_hal->dev);
+
+    if (!p_hal->fast_mode) {
+        reg_ctx->regs = reg_ctx->reg_buf[0].regs;
+        reg_ctx->spspps_offset = reg_ctx->offset_spspps[0];
+        reg_ctx->rps_offset = reg_ctx->offset_rps[0];
+        reg_ctx->sclst_offset = reg_ctx->offset_sclst[0];
+    }
+
+    //!< copy cabac table bytes
+    memcpy((char *)reg_ctx->bufs_ptr + reg_ctx->offset_cabac,
+           (void *)h264_cabac_table, sizeof(h264_cabac_table));
+
+    mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, mpp_align_128_odd_plus_64);
+    mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, rkv_ver_align);
+    mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, rkv_len_align);
+
+__RETURN:
+    return MPP_OK;
+__FAILED:
+    vdpu383_h264d_deinit(hal);
+
+    return ret;
+}
+
+MPP_RET vdpu383_h264d_deinit(void *hal)
+{
+    H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
+    Vdpu383H264dRegCtx *reg_ctx = (Vdpu383H264dRegCtx *)p_hal->reg_ctx;
+
+    RK_U32 i = 0;
+    RK_U32 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1;
+
+    if (reg_ctx->bufs) {
+        mpp_buffer_put(reg_ctx->bufs);
+        reg_ctx->bufs = NULL;
+    }
+
+    for (i = 0; i < loop; i++)
+        MPP_FREE(reg_ctx->reg_buf[i].regs);
+
+    loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->rcb_buf) : 1;
+    for (i = 0; i < loop; i++) {
+        if (reg_ctx->rcb_buf[i]) {
+            mpp_buffer_put(reg_ctx->rcb_buf[i]);
+            reg_ctx->rcb_buf[i] = NULL;
+        }
+    }
+
+    if (p_hal->cmv_bufs) {
+        hal_bufs_deinit(p_hal->cmv_bufs);
+        p_hal->cmv_bufs = NULL;
+    }
+
+    if (reg_ctx->origin_bufs) {
+        hal_bufs_deinit(reg_ctx->origin_bufs);
+        reg_ctx->origin_bufs = NULL;
+    }
+
+    MPP_FREE(p_hal->reg_ctx);
+
+    return MPP_OK;
+}
+
+static void h264d_refine_rcb_size(H264dHalCtx_t *p_hal, Vdpu383RcbInfo *rcb_info,
+                                  RK_S32 width, RK_S32 height)
+{
+    RK_U32 rcb_bits = 0;
+    RK_U32 mbaff = p_hal->pp->MbaffFrameFlag;
+    RK_U32 bit_depth = p_hal->pp->bit_depth_luma_minus8 + 8;
+    RK_U32 chroma_format_idc = p_hal->pp->chroma_format_idc;
+    RK_U32 row_uv_para = 1; // for yuv420/yuv422
+    RK_U32 filterd_row_append = 8192;
+
+    // vdpu383 h264d support yuv400/yuv420/yuv422
+    if (chroma_format_idc == 0)
+        row_uv_para = 0;
+
+    width = MPP_ALIGN(width, H264_CTU_SIZE);
+    height = MPP_ALIGN(height, H264_CTU_SIZE);
+    /* RCB_STRMD_ROW && RCB_STRMD_TILE_ROW*/
+    if (width > 4096)
+        rcb_bits = ((width + 15) / 16) * 154 * (mbaff ? 2 : 1);
+    else
+        rcb_bits = 0;
+    rcb_info[RCB_STRMD_ROW].size = MPP_RCB_BYTES(rcb_bits);
+    rcb_info[RCB_STRMD_TILE_ROW].size = MPP_RCB_BYTES(rcb_bits);
+    /* RCB_INTER_ROW && RCB_INTER_TILE_ROW*/
+    rcb_bits = ((width + 3) / 4) * 92 * (mbaff ? 2 : 1);
+    rcb_info[RCB_INTER_ROW].size = MPP_RCB_BYTES(rcb_bits);
+    rcb_info[RCB_INTER_TILE_ROW].size = MPP_RCB_BYTES(rcb_bits);
+    /* RCB_INTRA_ROW && RCB_INTRA_TILE_ROW*/
+    rcb_bits = MPP_ALIGN(width, 512) * (bit_depth + 2) * (mbaff ? 2 : 1);
+    if (chroma_format_idc == 1 || chroma_format_idc == 2)
+        rcb_bits = rcb_bits * 5 / 2; //TODO:
+
+    rcb_info[RCB_INTRA_ROW].size = MPP_RCB_BYTES(rcb_bits);
+    rcb_info[RCB_INTRA_TILE_ROW].size = 0;
+    /* RCB_FILTERD_ROW && RCB_FILTERD_PROTECT_ROW*/
+    // save space mode : half for RCB_FILTERD_ROW, half for RCB_FILTERD_PROTECT_ROW
+    rcb_bits = width * 17 * ((6 + 3 * row_uv_para) * (mbaff ? 2 : 1) + 2 * row_uv_para + 1.5);
+    if (width > 4096)
+        filterd_row_append = 27648;
+    rcb_info[RCB_FILTERD_ROW].size = MPP_RCB_BYTES(rcb_bits / 2);
+    rcb_info[RCB_FILTERD_PROTECT_ROW].size = filterd_row_append + MPP_RCB_BYTES(rcb_bits / 2);
+
+    rcb_info[RCB_FILTERD_TILE_ROW].size = 0;
+    /* RCB_FILTERD_TILE_COL */
+    rcb_info[RCB_FILTERD_TILE_COL].size = 0;
+
+}
+
+static void hal_h264d_rcb_info_update(void *hal)
+{
+    H264dHalCtx_t *p_hal = (H264dHalCtx_t*)hal;
+    RK_U32 mbaff = p_hal->pp->MbaffFrameFlag;
+    RK_U32 bit_depth = p_hal->pp->bit_depth_luma_minus8 + 8;
+    RK_U32 chroma_format_idc = p_hal->pp->chroma_format_idc;
+    Vdpu383H264dRegCtx *ctx = (Vdpu383H264dRegCtx *)p_hal->reg_ctx;
+    RK_S32 width = MPP_ALIGN((p_hal->pp->wFrameWidthInMbsMinus1 + 1) << 4, 64);
+    RK_S32 height = MPP_ALIGN((p_hal->pp->wFrameHeightInMbsMinus1 + 1) << 4, 64);
+
+    if ( ctx->bit_depth != bit_depth ||
+         ctx->chroma_format_idc != chroma_format_idc ||
+         ctx->mbaff != mbaff ||
+         ctx->width != width ||
+         ctx->height != height) {
+        RK_U32 i;
+        RK_U32 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(ctx->reg_buf) : 1;
+
+        ctx->rcb_buf_size = vdpu383_get_rcb_buf_size(ctx->rcb_info, width, height);
+        h264d_refine_rcb_size(hal, ctx->rcb_info, width, height);
+        for (i = 0; i < loop; i++) {
+            MppBuffer rcb_buf = ctx->rcb_buf[i];
+
+            if (rcb_buf) {
+                mpp_buffer_put(rcb_buf);
+                ctx->rcb_buf[i] = NULL;
+            }
+            mpp_buffer_get(p_hal->buf_group, &rcb_buf, ctx->rcb_buf_size);
+            ctx->rcb_buf[i] = rcb_buf;
+        }
+        ctx->bit_depth      = bit_depth;
+        ctx->width          = width;
+        ctx->height         = height;
+        ctx->mbaff          = mbaff;
+        ctx->chroma_format_idc = chroma_format_idc;
+    }
+}
+
+MPP_RET vdpu383_h264d_gen_regs(void *hal, HalTaskInfo *task)
+{
+    MPP_RET ret = MPP_ERR_UNKNOW;
+    H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
+    RK_S32 width = MPP_ALIGN((p_hal->pp->wFrameWidthInMbsMinus1 + 1) << 4, 64);
+    RK_S32 height = MPP_ALIGN((p_hal->pp->wFrameHeightInMbsMinus1 + 1) << 4, 64);
+    Vdpu383H264dRegCtx *ctx = (Vdpu383H264dRegCtx *)p_hal->reg_ctx;
+    Vdpu383H264dRegSet *regs = ctx->regs;
+    MppFrame mframe;
+    RK_S32 mv_size = MPP_ALIGN(width, 64) * MPP_ALIGN(height, 16); // 16 byte unit
+
+    INP_CHECK(ret, NULL == p_hal);
+
+    if (task->dec.flags.parse_err ||
+        task->dec.flags.ref_err) {
+        goto __RETURN;
+    }
+
+    /* if is field mode is enabled enlarge colmv buffer and disable colmv compression */
+    if (!p_hal->pp->frame_mbs_only_flag)
+        mv_size *= 2;
+
+    if (p_hal->cmv_bufs == NULL || p_hal->mv_size < mv_size) {
+        size_t size = mv_size;
+
+        if (p_hal->cmv_bufs) {
+            hal_bufs_deinit(p_hal->cmv_bufs);
+            p_hal->cmv_bufs = NULL;
+        }
+
+        hal_bufs_init(&p_hal->cmv_bufs);
+        if (p_hal->cmv_bufs == NULL) {
+            mpp_err_f("colmv bufs init fail");
+            goto __RETURN;
+        }
+        p_hal->mv_size = mv_size;
+        p_hal->mv_count = mpp_buf_slot_get_count(p_hal->frame_slots);
+        hal_bufs_setup(p_hal->cmv_bufs, p_hal->mv_count, 1, &size);
+    }
+
+    mpp_buf_slot_get_prop(p_hal->frame_slots, p_hal->pp->CurrPic.Index7Bits, SLOT_FRAME_PTR, &mframe);
+    if (mpp_frame_get_thumbnail_en(mframe) == MPP_FRAME_THUMBNAIL_ONLY &&
+        ctx->origin_bufs == NULL) {
+        vdpu383_setup_scale_origin_bufs(p_hal, mframe);
+    }
+
+    if (p_hal->fast_mode) {
+        RK_U32 i = 0;
+        for (i = 0; i <  MPP_ARRAY_ELEMS(ctx->reg_buf); i++) {
+            if (!ctx->reg_buf[i].valid) {
+                task->dec.reg_index = i;
+                regs = ctx->reg_buf[i].regs;
+
+                ctx->spspps_offset = ctx->offset_spspps[i];
+                ctx->rps_offset = ctx->offset_rps[i];
+                ctx->sclst_offset = ctx->offset_sclst[i];
+                ctx->reg_buf[i].valid = 1;
+                break;
+            }
+        }
+    }
+
+#ifdef DUMP_VDPU383_DATAS
+    {
+        memset(dump_cur_dir, 0, sizeof(dump_cur_dir));
+        sprintf(dump_cur_dir, "avc/Frame%04d", dump_cur_frame);
+        if (access(dump_cur_dir, 0)) {
+            if (mkdir(dump_cur_dir))
+                mpp_err_f("error: mkdir %s\n", dump_cur_dir);
+        }
+        dump_cur_frame++;
+    }
+#endif
+
+    prepare_spspps(p_hal, (RK_U64 *)&ctx->spspps, sizeof(ctx->spspps) / 8);
+    prepare_framerps(p_hal, (RK_U64 *)&ctx->rps, sizeof(ctx->rps) / 8);
+    prepare_scanlist(p_hal, ctx->sclst, sizeof(ctx->sclst));
+    set_registers(p_hal, regs, task);
+
+    //!< copy spspps datas
+    memcpy((char *)ctx->bufs_ptr + ctx->spspps_offset, (char *)ctx->spspps, sizeof(ctx->spspps));
+
+    regs->common_addr.reg131_gbl_base = ctx->bufs_fd;
+    regs->h264d_paras.reg67_global_len = VDPU383_SPS_PPS_LEN / 16; // 128 bit as unit
+    MppDevRegOffsetCfg trans_cfg;
+    trans_cfg.reg_idx = 131;
+    trans_cfg.offset = ctx->spspps_offset;
+    mpp_dev_ioctl(p_hal->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
+
+    memcpy((char *)ctx->bufs_ptr + ctx->rps_offset, (void *)ctx->rps, sizeof(ctx->rps));
+    regs->common_addr.reg129_rps_base = ctx->bufs_fd;
+    trans_cfg.reg_idx = 129;
+    trans_cfg.offset = ctx->rps_offset;
+    mpp_dev_ioctl(p_hal->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
+
+    if (p_hal->pp->scaleing_list_enable_flag) {
+        memcpy((char *)ctx->bufs_ptr + ctx->sclst_offset, (void *)ctx->sclst, sizeof(ctx->sclst));
+        regs->common_addr.reg132_scanlist_addr = ctx->bufs_fd;
+        trans_cfg.reg_idx = 132;
+        trans_cfg.offset = ctx->sclst_offset;
+        mpp_dev_ioctl(p_hal->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
+    } else {
+        regs->common_addr.reg132_scanlist_addr = 0;
+    }
+
+    hal_h264d_rcb_info_update(p_hal);
+    vdpu383_setup_rcb(&regs->common_addr, p_hal->dev, p_hal->fast_mode ?
+                      ctx->rcb_buf[task->dec.reg_index] : ctx->rcb_buf[0],
+                      ctx->rcb_info);
+    vdpu383_setup_statistic(&regs->ctrl_regs);
+    mpp_buffer_sync_end(ctx->bufs);
+
+__RETURN:
+    return ret = MPP_OK;
+}
+
+MPP_RET vdpu383_h264d_start(void *hal, HalTaskInfo *task)
+{
+    MPP_RET ret = MPP_ERR_UNKNOW;
+    H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
+    INP_CHECK(ret, NULL == p_hal);
+
+    if (task->dec.flags.parse_err ||
+        task->dec.flags.ref_err) {
+        goto __RETURN;
+    }
+
+    Vdpu383H264dRegCtx *reg_ctx = (Vdpu383H264dRegCtx *)p_hal->reg_ctx;
+    Vdpu383H264dRegSet *regs = p_hal->fast_mode ?
+                               reg_ctx->reg_buf[task->dec.reg_index].regs :
+                               reg_ctx->regs;
+    MppDev dev = p_hal->dev;
+
+    do {
+        MppDevRegWrCfg wr_cfg;
+        MppDevRegRdCfg rd_cfg;
+
+        wr_cfg.reg = &regs->ctrl_regs;
+        wr_cfg.size = sizeof(regs->ctrl_regs);
+        wr_cfg.offset = OFFSET_CTRL_REGS;
+        ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
+        if (ret) {
+            mpp_err_f("set register write failed %d\n", ret);
+            break;
+        }
+
+        wr_cfg.reg = &regs->common_addr;
+        wr_cfg.size = sizeof(regs->common_addr);
+        wr_cfg.offset = OFFSET_COMMON_ADDR_REGS;
+        ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
+        if (ret) {
+            mpp_err_f("set register write failed %d\n", ret);
+            break;
+        }
+
+        wr_cfg.reg = &regs->h264d_paras;
+        wr_cfg.size = sizeof(regs->h264d_paras);
+        wr_cfg.offset = OFFSET_CODEC_PARAS_REGS;
+        ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
+        if (ret) {
+            mpp_err_f("set register write failed %d\n", ret);
+            break;
+        }
+
+        wr_cfg.reg = &regs->h264d_addrs;
+        wr_cfg.size = sizeof(regs->h264d_addrs);
+        wr_cfg.offset = OFFSET_CODEC_ADDR_REGS;
+        ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
+        if (ret) {
+            mpp_err_f("set register write failed %d\n", ret);
+            break;
+        }
+
+        rd_cfg.reg = &regs->ctrl_regs.reg15;
+        rd_cfg.size = sizeof(regs->ctrl_regs.reg15);
+        rd_cfg.offset = OFFSET_INTERRUPT_REGS;
+        ret = mpp_dev_ioctl(dev, MPP_DEV_REG_RD, &rd_cfg);
+        if (ret) {
+            mpp_err_f("set register read failed %d\n", ret);
+            break;
+        }
+
+        /* rcb info for sram */
+        vdpu383_set_rcbinfo(dev, (Vdpu383RcbInfo*)reg_ctx->rcb_info);
+
+        /* send request to hardware */
+        ret = mpp_dev_ioctl(dev, MPP_DEV_CMD_SEND, NULL);
+        if (ret) {
+            mpp_err_f("send cmd failed %d\n", ret);
+            break;
+        }
+    } while (0);
+
+__RETURN:
+    return ret = MPP_OK;
+}
+
+MPP_RET vdpu383_h264d_wait(void *hal, HalTaskInfo *task)
+{
+    MPP_RET ret = MPP_ERR_UNKNOW;
+    H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
+
+    INP_CHECK(ret, NULL == p_hal);
+    Vdpu383H264dRegCtx *reg_ctx = (Vdpu383H264dRegCtx *)p_hal->reg_ctx;
+    Vdpu383H264dRegSet *p_regs = p_hal->fast_mode ?
+                                 reg_ctx->reg_buf[task->dec.reg_index].regs :
+                                 reg_ctx->regs;
+
+    if (task->dec.flags.parse_err ||
+        task->dec.flags.ref_err) {
+        goto __SKIP_HARD;
+    }
+
+    ret = mpp_dev_ioctl(p_hal->dev, MPP_DEV_CMD_POLL, NULL);
+    if (ret)
+        mpp_err_f("poll cmd failed %d\n", ret);
+
+__SKIP_HARD:
+    if (p_hal->dec_cb) {
+        DecCbHalDone param;
+
+        param.task = (void *)&task->dec;
+        param.regs = (RK_U32 *)p_regs;
+
+        if ((!p_regs->ctrl_regs.reg15.rkvdec_frame_rdy_sta) ||
+            p_regs->ctrl_regs.reg15.rkvdec_strm_error_sta ||
+            p_regs->ctrl_regs.reg15.rkvdec_core_timeout_sta ||
+            p_regs->ctrl_regs.reg15.rkvdec_ip_timeout_sta ||
+            p_regs->ctrl_regs.reg15.rkvdec_bus_error_sta ||
+            p_regs->ctrl_regs.reg15.rkvdec_buffer_empty_sta ||
+            p_regs->ctrl_regs.reg15.rkvdec_colmv_ref_error_sta)
+            param.hard_err = 1;
+        else
+            param.hard_err = 0;
+
+        mpp_callback(p_hal->dec_cb, &param);
+    }
+    memset(&p_regs->ctrl_regs.reg19, 0, sizeof(RK_U32));
+    if (p_hal->fast_mode) {
+        reg_ctx->reg_buf[task->dec.reg_index].valid = 0;
+    }
+
+    (void)task;
+__RETURN:
+    return ret = MPP_OK;
+}
+
+MPP_RET vdpu383_h264d_reset(void *hal)
+{
+    MPP_RET ret = MPP_ERR_UNKNOW;
+    H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
+
+    INP_CHECK(ret, NULL == p_hal);
+
+
+__RETURN:
+    return ret = MPP_OK;
+}
+
+MPP_RET vdpu383_h264d_flush(void *hal)
+{
+    MPP_RET ret = MPP_ERR_UNKNOW;
+    H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
+
+    INP_CHECK(ret, NULL == p_hal);
+
+__RETURN:
+    return ret = MPP_OK;
+}
+
+MPP_RET vdpu383_h264d_control(void *hal, MpiCmd cmd_type, void *param)
+{
+    MPP_RET ret = MPP_ERR_UNKNOW;
+    H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
+
+    INP_CHECK(ret, NULL == p_hal);
+
+    switch ((MpiCmd)cmd_type) {
+    case MPP_DEC_SET_FRAME_INFO: {
+        MppFrameFormat fmt = mpp_frame_get_fmt((MppFrame)param);
+        RK_U32 imgwidth = mpp_frame_get_width((MppFrame)param);
+        RK_U32 imgheight = mpp_frame_get_height((MppFrame)param);
+
+        mpp_log("control info: fmt %d, w %d, h %d\n", fmt, imgwidth, imgheight);
+        if (fmt == MPP_FMT_YUV422SP) {
+            mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, rkv_len_align_422);
+        }
+        if (MPP_FRAME_FMT_IS_FBC(fmt)) {
+            vdpu383_afbc_align_calc(p_hal->frame_slots, (MppFrame)param, 16);
+        } else if (imgwidth > 1920 || imgheight > 1088) {
+            mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, mpp_align_128_odd_plus_64);
+        }
+    } break;
+    case MPP_DEC_GET_THUMBNAIL_FRAME_INFO: {
+        vdpu383_update_thumbnail_frame_info((MppFrame)param);
+    } break;
+    case MPP_DEC_SET_OUTPUT_FORMAT: {
+    } break;
+    default : {
+    } break;
+    }
+
+__RETURN:
+    return ret = MPP_OK;
+}
+
+const MppHalApi hal_h264d_vdpu383 = {
+    .name     = "h264d_vdpu383",
+    .type     = MPP_CTX_DEC,
+    .coding   = MPP_VIDEO_CodingAVC,
+    .ctx_size = sizeof(Vdpu383H264dRegCtx),
+    .flag     = 0,
+    .init     = vdpu383_h264d_init,
+    .deinit   = vdpu383_h264d_deinit,
+    .reg_gen  = vdpu383_h264d_gen_regs,
+    .start    = vdpu383_h264d_start,
+    .wait     = vdpu383_h264d_wait,
+    .reset    = vdpu383_h264d_reset,
+    .flush    = vdpu383_h264d_flush,
+    .control  = vdpu383_h264d_control,
+};
diff --git a/mpp/hal/rkdec/h264d/hal_h264d_vdpu383.h b/mpp/hal/rkdec/h264d/hal_h264d_vdpu383.h
new file mode 100644
index 000000000..3b5ed51dd
--- /dev/null
+++ b/mpp/hal/rkdec/h264d/hal_h264d_vdpu383.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: Apache-2.0 OR MIT */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef __HAL_H264D_VDPU383_H__
+#define __HAL_H264D_VDPU383_H__
+
+#include "mpp_hal.h"
+#include "vdpu383.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern const MppHalApi hal_h264d_vdpu383;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HAL_H264D_VDPU34X_H__ */
\ No newline at end of file
diff --git a/mpp/hal/rkdec/h265d/CMakeLists.txt b/mpp/hal/rkdec/h265d/CMakeLists.txt
index 0e5d38ce5..dd5579f87 100644
--- a/mpp/hal/rkdec/h265d/CMakeLists.txt
+++ b/mpp/hal/rkdec/h265d/CMakeLists.txt
@@ -7,9 +7,10 @@ set(HAL_H265D_SRC
     hal_h265d_rkv.c
     hal_h265d_vdpu34x.c
     hal_h265d_vdpu382.c
+    hal_h265d_vdpu383.c
     )
 
 add_library(${HAL_H265D} STATIC ${HAL_H265D_SRC})
 
 set_target_properties(${HAL_H265D} PROPERTIES FOLDER "mpp/hal")
-target_link_libraries(${HAL_H265D} vdpu34x_com mpp_base)
+target_link_libraries(${HAL_H265D} vdpu34x_com vdpu383_com mpp_base)
diff --git a/mpp/hal/rkdec/h265d/hal_h265d_api.c b/mpp/hal/rkdec/h265d/hal_h265d_api.c
index 1ca0b0627..3a1ecf61f 100644
--- a/mpp/hal/rkdec/h265d/hal_h265d_api.c
+++ b/mpp/hal/rkdec/h265d/hal_h265d_api.c
@@ -28,6 +28,7 @@
 #include "hal_h265d_rkv.h"
 #include "hal_h265d_vdpu34x.h"
 #include "hal_h265d_vdpu382.h"
+#include "hal_h265d_vdpu383.h"
 
 RK_U32 hal_h265d_debug = 0;
 
@@ -37,6 +38,7 @@ MPP_RET hal_h265d_init(void *ctx, MppHalCfg *cfg)
     HalH265dCtx *p = (HalH265dCtx *)ctx;
     MppClientType client_type = VPU_CLIENT_BUTT;
     RK_U32 vcodec_type = mpp_get_vcodec_type();
+    RockchipSocType soc = mpp_get_soc_type();
     RK_U32 hw_id = 0;
 
     if (!(vcodec_type & (HAVE_RKVDEC | HAVE_HEVC_DEC))) {
@@ -52,17 +54,23 @@ MPP_RET hal_h265d_init(void *ctx, MppHalCfg *cfg)
         mpp_err("mpp_dev_init failed ret: %d\n", ret);
         return ret;
     }
+    cfg->hw_info = mpp_get_dec_hw_info_by_client_type(client_type);
+    p->hw_info = cfg->hw_info;
 
     hw_id = mpp_get_client_hw_id(client_type);
     p->dev = cfg->dev;
+    p->is_v341 = (soc == ROCKCHIP_SOC_RK3228H || (soc == ROCKCHIP_SOC_RK3328));
     p->is_v345 = (hw_id == HWID_VDPU345);
     p->is_v34x = (hw_id == HWID_VDPU34X || hw_id == HWID_VDPU38X);
+    p->is_v383 = (hw_id == HWID_VDPU383);
     p->client_type = client_type;
 
     if (hw_id == HWID_VDPU382_RK3528 || hw_id == HWID_VDPU382_RK3562)
         p->api = &hal_h265d_vdpu382;
     else if (p->is_v34x)
         p->api = &hal_h265d_vdpu34x;
+    else if (p->is_v383)
+        p->api = &hal_h265d_vdpu383;
     else
         p->api = &hal_h265d_rkv;
 
diff --git a/mpp/hal/rkdec/h265d/hal_h265d_com.h b/mpp/hal/rkdec/h265d/hal_h265d_com.h
index 84dd76fb5..2a1063088 100644
--- a/mpp/hal/rkdec/h265d/hal_h265d_com.h
+++ b/mpp/hal/rkdec/h265d/hal_h265d_com.h
@@ -19,6 +19,7 @@
 #define __HAL_H265D_COM_H__
 
 #include "rk_type.h"
+#include <limits.h>
 
 #define SCALING_LIST_SIZE       (81 * 1360)
 #define RPS_SIZE                (600 * 32)
diff --git a/mpp/hal/rkdec/h265d/hal_h265d_ctx.h b/mpp/hal/rkdec/h265d/hal_h265d_ctx.h
index f0217916a..346dbbc7d 100644
--- a/mpp/hal/rkdec/h265d/hal_h265d_ctx.h
+++ b/mpp/hal/rkdec/h265d/hal_h265d_ctx.h
@@ -1,17 +1,6 @@
+/* SPDX-License-Identifier: Apache-2.0 OR MIT */
 /*
- * Copyright 2020 Rockchip Electronics Co. LTD
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *      http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
  */
 
 #ifndef __HAL_H265D_CTX_H__
@@ -22,7 +11,8 @@
 #include "hal_bufs.h"
 
 #define MAX_GEN_REG 3
-#define H265D_RCB_BUF_COUNT 10
+/* before vdpu383 10 buf */
+#define H265D_RCB_BUF_COUNT 11
 
 typedef struct H265dRegBuf_t {
     RK_S32    use_flag;
@@ -32,7 +22,7 @@ typedef struct H265dRegBuf_t {
     void*     hw_regs;
 } H265dRegBuf;
 
-typedef struct h265d_rcb_info_t {
+typedef struct H265dRcbInfo_t {
     RK_S32              reg;
     RK_S32              size;
     RK_S32              offset;
@@ -74,14 +64,16 @@ typedef struct HalH265dCtx_t {
     RK_U32          mv_size;
     RK_S32          mv_count;
 
+    RK_U32          is_v341;
     RK_U32          is_v345;
     RK_U32          is_v34x;
+    RK_U32          is_v383;
     /* rcb info */
     RK_U32          chroma_fmt_idc;
     RK_U8           ctu_size;
     RK_U8           num_row_tiles;
     RK_U8           bit_depth;
-    RK_U8           error_index;
+    RK_U8           error_index[MAX_GEN_REG];
     /* for vdpu34x */
     MppBuffer       bufs;
     RK_S32          bufs_fd;
@@ -94,6 +86,9 @@ typedef struct HalH265dCtx_t {
     RK_U32          sclst_offset;
     void            *pps_buf;
     void            *sw_rps_buf;
+    HalBufs         origin_bufs;
+    MppBuffer       missing_ref_buf;
+    RK_U32          missing_ref_buf_size;
 
     const MppDecHwCap   *hw_info;
 } HalH265dCtx;
diff --git a/mpp/hal/rkdec/h265d/hal_h265d_rkv.c b/mpp/hal/rkdec/h265d/hal_h265d_rkv.c
index 1780c2b49..14fc1fabc 100644
--- a/mpp/hal/rkdec/h265d/hal_h265d_rkv.c
+++ b/mpp/hal/rkdec/h265d/hal_h265d_rkv.c
@@ -210,25 +210,6 @@ MPP_RET hal_h265d_rkv_init(void *hal, MppHalCfg *cfg)
         return ret;
     }
 
-
-    {
-        // report hw_info to parser
-        const MppSocInfo *info = mpp_get_soc_info();
-        const void *hw_info = NULL;
-        RK_U32 i = 0;
-
-        for (i = 0; i < MPP_ARRAY_ELEMS(info->dec_caps); i++) {
-            if (info->dec_caps[i] && ( info->dec_caps[i]->type == VPU_CLIENT_RKVDEC ||
-                                       info->dec_caps[i]->type == VPU_CLIENT_HEVC_DEC)) {
-                hw_info = info->dec_caps[i];
-                break;
-            }
-        }
-
-        mpp_assert(hw_info);
-        cfg->hw_info = hw_info;
-    }
-
 #ifdef dump
     fp = fopen("/data/hal.bin", "wb");
 #endif
@@ -786,6 +767,8 @@ MPP_RET hal_h265d_rkv_gen_regs(void *hal,  HalTaskInfo *syn)
             mpp_err("hevc rps buf all used");
             return MPP_ERR_NOMEM;
         }
+    } else {
+        syn->dec.reg_index = 0;
     }
     rps_ptr = mpp_buffer_get_ptr(reg_ctx->rps_data);
     if (NULL == rps_ptr) {
@@ -958,7 +941,8 @@ MPP_RET hal_h265d_rkv_start(void *hal, HalTaskInfo *task)
     do {
         MppDevRegWrCfg wr_cfg;
         MppDevRegRdCfg rd_cfg;
-        RK_U32 reg_size = (reg_ctx->is_v345) ? V345_HEVC_REGISTERS :
+
+        RK_U32 reg_size = (reg_ctx->is_v341 || reg_ctx->is_v345) ? V345_HEVC_REGISTERS :
                           (reg_ctx->client_type == VPU_CLIENT_RKVDEC) ?
                           RKVDEC_V1_REGISTERS : RKVDEC_HEVC_REGISTERS;
 
@@ -1007,18 +991,18 @@ MPP_RET hal_h265d_rkv_wait(void *hal, HalTaskInfo *task)
     H265d_REGS_t *hw_regs = NULL;
     RK_S32 i;
 
-    if (task->dec.flags.parse_err ||
-        task->dec.flags.ref_err) {
-        h265h_dbg(H265H_DBG_TASK_ERR, "%s found task error\n", __FUNCTION__);
-        goto ERR_PROC;
-    }
-
     if (reg_ctx->fast_mode) {
         hw_regs = ( H265d_REGS_t *)reg_ctx->g_buf[index].hw_regs;
     } else {
         hw_regs = ( H265d_REGS_t *)reg_ctx->hw_regs;
     }
 
+    if (task->dec.flags.parse_err ||
+        task->dec.flags.ref_err) {
+        h265h_dbg(H265H_DBG_TASK_ERR, "%s found task error\n", __FUNCTION__);
+        goto ERR_PROC;
+    }
+
     ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_CMD_POLL, NULL);
     if (ret)
         mpp_err_f("poll cmd failed %d\n", ret);
diff --git a/mpp/hal/rkdec/h265d/hal_h265d_vdpu34x.c b/mpp/hal/rkdec/h265d/hal_h265d_vdpu34x.c
index 4efd26f2f..6d05d6360 100644
--- a/mpp/hal/rkdec/h265d/hal_h265d_vdpu34x.c
+++ b/mpp/hal/rkdec/h265d/hal_h265d_vdpu34x.c
@@ -30,7 +30,6 @@
 #include "hal_h265d_com.h"
 #include "hal_h265d_vdpu34x.h"
 #include "vdpu34x_h265d.h"
-#include "rk_hdr_meta_com.h"
 
 /* #define dump */
 #ifdef dump
@@ -40,6 +39,8 @@ static FILE *fp = NULL;
 #define HW_RPS
 #define PPS_SIZE                (112 * 64)//(96x64)
 
+#define COLMV_COMPRESS_EN       1
+
 #define SET_REF_VALID(regs, index, value)\
     do{ \
         switch(index){\
@@ -160,23 +161,6 @@ static MPP_RET hal_h265d_vdpu34x_init(void *hal, MppHalCfg *cfg)
         return ret;
     }
 
-    {
-        // report hw_info to parser
-        const MppSocInfo *info = mpp_get_soc_info();
-        const void *hw_info = NULL;
-        RK_U32 i;
-
-        for (i = 0; i < MPP_ARRAY_ELEMS(info->dec_caps); i++) {
-            if (info->dec_caps[i] && info->dec_caps[i]->type == VPU_CLIENT_RKVDEC) {
-                hw_info = info->dec_caps[i];
-                break;
-            }
-        }
-
-        mpp_assert(hw_info);
-        cfg->hw_info = hw_info;
-    }
-
     if (cfg->hal_fbc_adj_cfg) {
         cfg->hal_fbc_adj_cfg->func = vdpu34x_afbc_align_calc;
         cfg->hal_fbc_adj_cfg->expand = 16;
@@ -208,6 +192,11 @@ static MPP_RET hal_h265d_vdpu34x_deinit(void *hal)
         }
     }
 
+    if (reg_ctx->missing_ref_buf) {
+        mpp_buffer_put(reg_ctx->missing_ref_buf);
+        reg_ctx->missing_ref_buf = NULL;
+    }
+
     if (reg_ctx->group) {
         mpp_buffer_group_put(reg_ctx->group);
         reg_ctx->group = NULL;
@@ -693,6 +682,7 @@ static void h265d_refine_rcb_size(Vdpu34xRcbInfo *rcb_info,
 
     width = MPP_ALIGN(width, ctu_size);
     height = MPP_ALIGN(height, ctu_size);
+
     /* RCB_STRMD_ROW */
     if (width > 8192) {
         RK_U32 factor = ctu_size / 16;
@@ -700,27 +690,33 @@ static void h265d_refine_rcb_size(Vdpu34xRcbInfo *rcb_info,
     } else
         rcb_bits = 0;
     rcb_info[RCB_STRMD_ROW].size = MPP_RCB_BYTES(rcb_bits);
+
     /* RCB_TRANSD_ROW */
     if (width > 8192)
         rcb_bits = (MPP_ALIGN(width - 8192, 4) << 1) + ext_align_size;
     else
         rcb_bits = 0;
     rcb_info[RCB_TRANSD_ROW].size = MPP_RCB_BYTES(rcb_bits);
+
     /* RCB_TRANSD_COL */
-    if (height > 8192)
-        rcb_bits = (MPP_ALIGN(height - 8192, 4) << 1) + ext_align_size;
+    if (height > 8192 && tile_col_cut_num)
+        rcb_bits = (MPP_ALIGN(height - 8192, 4) << 1);
     else
         rcb_bits = 0;
     rcb_info[RCB_TRANSD_COL].size = MPP_RCB_BYTES(rcb_bits);
+
     /* RCB_INTER_ROW */
     rcb_bits = width * 22 + ext_align_size;
     rcb_info[RCB_INTER_ROW].size = MPP_RCB_BYTES(rcb_bits);
+
     /* RCB_INTER_COL */
-    rcb_bits = height * 22 + ext_align_size;
+    rcb_bits = tile_col_cut_num ? height * 22 : 0;
     rcb_info[RCB_INTER_COL].size = MPP_RCB_BYTES(rcb_bits);
+
     /* RCB_INTRA_ROW */
     rcb_bits = width * 48 + ext_align_size;
     rcb_info[RCB_INTRA_ROW].size = MPP_RCB_BYTES(rcb_bits);
+
     /* RCB_DBLK_ROW */
     if (chroma_fmt_idc == 1 || chroma_fmt_idc == 2) {
         if (ctu_size == 32)
@@ -735,6 +731,7 @@ static void h265d_refine_rcb_size(Vdpu34xRcbInfo *rcb_info,
     }
     rcb_bits += (tile_col_cut_num * (bit_depth == 8 ? 256 : 192)) + ext_align_size;
     rcb_info[RCB_DBLK_ROW].size = MPP_RCB_BYTES(rcb_bits);
+
     /* RCB_SAO_ROW */
     if (chroma_fmt_idc == 1 || chroma_fmt_idc == 2) {
         rcb_bits = width * (128 / ctu_size + 2 * bit_depth);
@@ -743,6 +740,7 @@ static void h265d_refine_rcb_size(Vdpu34xRcbInfo *rcb_info,
     }
     rcb_bits += (tile_col_cut_num * (bit_depth == 8 ? 160 : 128)) + ext_align_size;
     rcb_info[RCB_SAO_ROW].size = MPP_RCB_BYTES(rcb_bits);
+
     /* RCB_FBC_ROW */
     if (hw_regs->common.reg012.fbc_e) {
         rcb_bits = width * (chroma_fmt_idc - 1) * 2 * bit_depth;
@@ -750,21 +748,25 @@ static void h265d_refine_rcb_size(Vdpu34xRcbInfo *rcb_info,
     } else
         rcb_bits = 0;
     rcb_info[RCB_FBC_ROW].size = MPP_RCB_BYTES(rcb_bits);
+
     /* RCB_FILT_COL */
-    if (hw_regs->common.reg012.fbc_e) {
-        RK_U32 ctu_idx = ctu_size >> 5;
-        RK_U32 a = filterd_fbc_on[chroma_fmt_idc][ctu_idx].a;
-        RK_U32 b = filterd_fbc_on[chroma_fmt_idc][ctu_idx].b;
+    if (tile_col_cut_num) {
+        if (hw_regs->common.reg012.fbc_e) {
+            RK_U32 ctu_idx = ctu_size >> 5;
+            RK_U32 a = filterd_fbc_on[ctu_idx][chroma_fmt_idc].a;
+            RK_U32 b = filterd_fbc_on[ctu_idx][chroma_fmt_idc].b;
 
-        rcb_bits = height * (a * bit_depth + b);
-    } else {
-        RK_U32 ctu_idx = ctu_size >> 5;
-        RK_U32 a = filterd_fbc_off[chroma_fmt_idc][ctu_idx].a;
-        RK_U32 b = filterd_fbc_off[chroma_fmt_idc][ctu_idx].b;
+            rcb_bits = height * (a * bit_depth + b);
+        } else {
+            RK_U32 ctu_idx = ctu_size >> 5;
+            RK_U32 a = filterd_fbc_off[ctu_idx][chroma_fmt_idc].a;
+            RK_U32 b = filterd_fbc_off[ctu_idx][chroma_fmt_idc].b;
+
+            rcb_bits = height * (a * bit_depth + b + (bit_depth == 10 ? 16 : 0));
+        }
+    } else
+        rcb_bits = 0;
 
-        rcb_bits = height * (a * bit_depth + b + (bit_depth == 10 ? 192 * ctu_size >> 4 : 0));
-    }
-    rcb_bits += ext_align_size;
     rcb_info[RCB_FILT_COL].size = MPP_RCB_BYTES(rcb_bits);
 }
 
@@ -835,7 +837,6 @@ static void hal_h265d_rcb_info_update(void *hal,  void *dxva,
     }while(0)
 
 #define pocdistance(a, b) (((a) > (b)) ? ((a) - (b)) : ((b) - (a)))
-#define MAX_INT           2147483647
 
 static MPP_RET hal_h265d_vdpu34x_gen_regs(void *hal,  HalTaskInfo *syn)
 {
@@ -852,12 +853,15 @@ static MPP_RET hal_h265d_vdpu34x_gen_regs(void *hal,  HalTaskInfo *syn)
     HalBuf *mv_buf = NULL;
     RK_S32 fd = -1;
     RK_U32 mv_size = 0;
-    RK_S32 distance = MAX_INT;
+    RK_S32 distance = INT_MAX;
     h265d_dxva2_picture_context_t *dxva_cxt =
         (h265d_dxva2_picture_context_t *)syn->dec.syntax.data;
     HalH265dCtx *reg_ctx = ( HalH265dCtx *)hal;
     void *rps_ptr = NULL;
     RK_U32 stream_buf_size = 0;
+    DXVA_PicParams_HEVC *pp = &dxva_cxt->pp;
+    RK_U8 ctu_size = 1 << (pp->log2_diff_max_min_luma_coding_block_size +
+                           pp->log2_min_luma_coding_block_size_minus3 + 3);
 
     if (syn->dec.flags.parse_err ||
         syn->dec.flags.ref_err) {
@@ -883,6 +887,8 @@ static MPP_RET hal_h265d_vdpu34x_gen_regs(void *hal,  HalTaskInfo *syn)
             mpp_err("hevc rps buf all used");
             return MPP_ERR_NOMEM;
         }
+    } else {
+        syn->dec.reg_index = 0;
     }
     rps_ptr = mpp_buffer_get_ptr(reg_ctx->bufs) + reg_ctx->rps_offset;
     if (NULL == rps_ptr) {
@@ -911,12 +917,11 @@ static MPP_RET hal_h265d_vdpu34x_gen_regs(void *hal,  HalTaskInfo *syn)
         return MPP_ERR_NULL_PTR;
     }
 
-
     log2_min_cb_size = dxva_cxt->pp.log2_min_luma_coding_block_size_minus3 + 3;
 
     width = (dxva_cxt->pp.PicWidthInMinCbsY << log2_min_cb_size);
     height = (dxva_cxt->pp.PicHeightInMinCbsY << log2_min_cb_size);
-    mv_size = (MPP_ALIGN(width, 64) * MPP_ALIGN(height, 64)) >> 3;
+    mv_size = vdpu34x_get_colmv_size(width, height, ctu_size, 16, 16, COLMV_COMPRESS_EN);
     if (reg_ctx->cmv_bufs == NULL || reg_ctx->mv_size < mv_size) {
         size_t size = mv_size;
 
@@ -972,9 +977,6 @@ static MPP_RET hal_h265d_vdpu34x_gen_regs(void *hal,  HalTaskInfo *syn)
             hw_regs->common.reg019.uv_hor_virstride = stride_uv >> 4;
             hw_regs->common.reg020_y_virstride.y_virstride = virstrid_y >> 4;
         }
-
-        if (MPP_FRAME_FMT_IS_HDR(mpp_frame_get_fmt(mframe)) && reg_ctx->cfg->base.enable_hdr_meta)
-            fill_hdr_meta_to_frame(mframe, HDR_HEVC);
     }
     mpp_buf_slot_get_prop(reg_ctx->slots, dxva_cxt->pp.CurrPic.Index7Bits,
                           SLOT_BUFFER, &framebuf);
@@ -1034,7 +1036,7 @@ static MPP_RET hal_h265d_vdpu34x_gen_regs(void *hal,  HalTaskInfo *syn)
     hw_regs->common.reg011.dec_timeout_e        = 1;
     hw_regs->common.reg012.wr_ddr_align_en      = dxva_cxt->pp.tiles_enabled_flag
                                                   ? 0 : 1;
-    hw_regs->common.reg012.colmv_compress_en    = 1;
+    hw_regs->common.reg012.colmv_compress_en    = COLMV_COMPRESS_EN;
 
     if (mpp_get_soc_type() == ROCKCHIP_SOC_RK3588) {
         hw_regs->common.reg026.swreg_block_gating_e = 0xfffef;
@@ -1052,7 +1054,7 @@ static MPP_RET hal_h265d_vdpu34x_gen_regs(void *hal,  HalTaskInfo *syn)
     hw_regs->common.reg032_timeout_threshold = 0x3ffff;
 
     valid_ref = hw_regs->common_addr.reg130_decout_base;
-    reg_ctx->error_index = dxva_cxt->pp.CurrPic.Index7Bits;
+    reg_ctx->error_index[syn->dec.reg_index] = dxva_cxt->pp.CurrPic.Index7Bits;
     hw_regs->common_addr.reg132_error_ref_base = valid_ref;
 
     for (i = 0; i < (RK_S32)MPP_ARRAY_ELEMS(dxva_cxt->pp.RefPicList); i++) {
@@ -1060,68 +1062,77 @@ static MPP_RET hal_h265d_vdpu34x_gen_regs(void *hal,  HalTaskInfo *syn)
             dxva_cxt->pp.RefPicList[i].bPicEntry != 0x7f) {
 
             MppFrame mframe = NULL;
+            MppBuffer ref_buf = NULL;
             hw_regs->h265d_param.reg67_82_ref_poc[i] = dxva_cxt->pp.PicOrderCntValList[i];
             mpp_buf_slot_get_prop(reg_ctx->slots,
                                   dxva_cxt->pp.RefPicList[i].Index7Bits,
-                                  SLOT_BUFFER, &framebuf);
+                                  SLOT_BUFFER, &ref_buf);
             mpp_buf_slot_get_prop(reg_ctx->slots, dxva_cxt->pp.RefPicList[i].Index7Bits,
                                   SLOT_FRAME_PTR, &mframe);
-            if (framebuf != NULL) {
-                hw_regs->h265d_addr.reg164_179_ref_base[i] = mpp_buffer_get_fd(framebuf);
+            if (!ref_buf && mpp_get_soc_type() == ROCKCHIP_SOC_RK3588 &&
+                reg_ctx->cfg->base.disable_error) {
+                if (reg_ctx->missing_ref_buf && reg_ctx->missing_ref_buf_size < mpp_buffer_get_size(framebuf)) {
+                    mpp_buffer_put(reg_ctx->missing_ref_buf);
+                    reg_ctx->missing_ref_buf = NULL;
+                }
+
+                if (!reg_ctx->missing_ref_buf) {
+                    reg_ctx->missing_ref_buf_size = mpp_buffer_get_size(framebuf);
+                    mpp_buffer_get(reg_ctx->group, &reg_ctx->missing_ref_buf, reg_ctx->missing_ref_buf_size);
+                    if (!reg_ctx->missing_ref_buf) {
+                        syn->dec.flags.ref_err = 1;
+                        h265h_dbg(H265H_DBG_TASK_ERR, "Failed to generate missing ref buf\n");
+                        return MPP_ERR_NOMEM;
+                    }
+                }
+                ref_buf = reg_ctx->missing_ref_buf;
+            }
+            if (ref_buf) {
+                hw_regs->h265d_addr.reg164_179_ref_base[i] = mpp_buffer_get_fd(ref_buf);
                 valid_ref = hw_regs->h265d_addr.reg164_179_ref_base[i];
-                // mpp_log("cur poc %d, ref poc %d", dxva_cxt->pp.current_poc, dxva_cxt->pp.PicOrderCntValList[i]);
+                h265h_dbg(H265H_DBG_TASK_ERR, "cur poc %d, ref poc %d", dxva_cxt->pp.current_poc, dxva_cxt->pp.PicOrderCntValList[i]);
                 if ((pocdistance(dxva_cxt->pp.PicOrderCntValList[i], dxva_cxt->pp.current_poc) < distance)
                     && (!mpp_frame_get_errinfo(mframe))) {
                     distance = pocdistance(dxva_cxt->pp.PicOrderCntValList[i], dxva_cxt->pp.current_poc);
                     hw_regs->common_addr.reg132_error_ref_base = hw_regs->h265d_addr.reg164_179_ref_base[i];
-                    reg_ctx->error_index = dxva_cxt->pp.RefPicList[i].Index7Bits;
+                    reg_ctx->error_index[syn->dec.reg_index] = dxva_cxt->pp.RefPicList[i].Index7Bits;
                     hw_regs->common.reg021.error_intra_mode = 0;
+                    h265h_dbg(H265H_DBG_TASK_ERR, "update error ref to ref[%d] to poc %d, slot_idx %d, fd %d\n",
+                              i, dxva_cxt->pp.PicOrderCntValList[i],
+                              dxva_cxt->pp.RefPicList[i].Index7Bits,
+                              hw_regs->common_addr.reg132_error_ref_base);
                 }
             } else {
+                h265h_dbg(H265H_DBG_TASK_ERR, "ref[%d] buffer is empty, replace with fd %d\n", i, valid_ref);
                 hw_regs->h265d_addr.reg164_179_ref_base[i] = valid_ref;
             }
 
             mv_buf = hal_bufs_get_buf(reg_ctx->cmv_bufs, dxva_cxt->pp.RefPicList[i].Index7Bits);
-            hw_regs->h265d_addr.reg181_196_colmv_base[i] = mpp_buffer_get_fd(mv_buf->buf[0]);
 
             SET_REF_VALID(hw_regs->h265d_param, i, 1);
-        }
-    }
 
-    if ((reg_ctx->error_index == dxva_cxt->pp.CurrPic.Index7Bits) && !dxva_cxt->pp.IntraPicFlag) {
-        // mpp_err("current frm may be err, should skip process");
-        syn->dec.flags.ref_err = 1;
-        return MPP_OK;
-    }
+            if (hw_regs->common.reg013.h26x_error_mode &&
+                !hw_regs->common.reg021.error_intra_mode &&
+                (!ref_buf || mpp_frame_get_errinfo(mframe))) {
 
-    for (i = 0; i < (RK_S32)MPP_ARRAY_ELEMS(dxva_cxt->pp.RefPicList); i++) {
-
-        if (dxva_cxt->pp.RefPicList[i].bPicEntry != 0xff &&
-            dxva_cxt->pp.RefPicList[i].bPicEntry != 0x7f) {
-            if (!hw_regs->common.reg021.error_intra_mode) {
-                MppFrame mframe = NULL;
-
-                mpp_buf_slot_get_prop(reg_ctx->slots,
-                                      dxva_cxt->pp.RefPicList[i].Index7Bits,
-                                      SLOT_BUFFER, &framebuf);
-
-                mpp_buf_slot_get_prop(reg_ctx->slots, dxva_cxt->pp.RefPicList[i].Index7Bits,
-                                      SLOT_FRAME_PTR, &mframe);
-
-                if (framebuf == NULL || mpp_frame_get_errinfo(mframe)) {
-                    mv_buf = hal_bufs_get_buf(reg_ctx->cmv_bufs, reg_ctx->error_index);
-                    hw_regs->h265d_addr.reg164_179_ref_base[i] = hw_regs->common_addr.reg132_error_ref_base;
-                    hw_regs->h265d_addr.reg181_196_colmv_base[i] = mpp_buffer_get_fd(mv_buf->buf[0]);
-                }
+                mv_buf = hal_bufs_get_buf(reg_ctx->cmv_bufs, reg_ctx->error_index[syn->dec.reg_index]);
+                hw_regs->h265d_addr.reg164_179_ref_base[i] = hw_regs->common_addr.reg132_error_ref_base;
             }
         } else {
-            mv_buf = hal_bufs_get_buf(reg_ctx->cmv_bufs, reg_ctx->error_index);
+            mv_buf = hal_bufs_get_buf(reg_ctx->cmv_bufs, reg_ctx->error_index[syn->dec.reg_index]);
             hw_regs->h265d_addr.reg164_179_ref_base[i] = hw_regs->common_addr.reg132_error_ref_base;
-            hw_regs->h265d_addr.reg181_196_colmv_base[i] = mpp_buffer_get_fd(mv_buf->buf[0]);
             /* mark 3 to differ from current frame */
-            if (reg_ctx->error_index == dxva_cxt->pp.CurrPic.Index7Bits)
+            if (reg_ctx->error_index[syn->dec.reg_index] == dxva_cxt->pp.CurrPic.Index7Bits)
                 SET_POC_HIGNBIT_INFO(hw_regs->highpoc, i, poc_highbit, 3);
         }
+        hw_regs->h265d_addr.reg181_196_colmv_base[i] = mpp_buffer_get_fd(mv_buf->buf[0]);
+    }
+
+    if ((reg_ctx->error_index[syn->dec.reg_index] == dxva_cxt->pp.CurrPic.Index7Bits) &&
+        !dxva_cxt->pp.IntraPicFlag && !reg_ctx->cfg->base.disable_error) {
+        h265h_dbg(H265H_DBG_TASK_ERR, "current frm may be err, should skip process");
+        syn->dec.flags.ref_err = 1;
+        return MPP_OK;
     }
 
     trans_cfg.reg_idx = 161;
@@ -1281,12 +1292,6 @@ static MPP_RET hal_h265d_vdpu34x_wait(void *hal, HalTaskInfo *task)
     Vdpu34xH265dRegSet *hw_regs = NULL;
     RK_S32 i;
 
-    if (task->dec.flags.parse_err ||
-        task->dec.flags.ref_err) {
-        h265h_dbg(H265H_DBG_TASK_ERR, "%s found task error\n", __FUNCTION__);
-        goto ERR_PROC;
-    }
-
     if (reg_ctx->fast_mode) {
         hw_regs = ( Vdpu34xH265dRegSet *)reg_ctx->g_buf[index].hw_regs;
     } else {
@@ -1295,6 +1300,12 @@ static MPP_RET hal_h265d_vdpu34x_wait(void *hal, HalTaskInfo *task)
 
     p = (RK_U8*)hw_regs;
 
+    if (task->dec.flags.parse_err ||
+        task->dec.flags.ref_err) {
+        h265h_dbg(H265H_DBG_TASK_ERR, "%s found task error\n", __FUNCTION__);
+        goto ERR_PROC;
+    }
+
     ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_CMD_POLL, NULL);
     if (ret)
         mpp_err_f("poll cmd failed %d\n", ret);
diff --git a/mpp/hal/rkdec/h265d/hal_h265d_vdpu382.c b/mpp/hal/rkdec/h265d/hal_h265d_vdpu382.c
index f3e8b5b49..6530ee9c2 100644
--- a/mpp/hal/rkdec/h265d/hal_h265d_vdpu382.c
+++ b/mpp/hal/rkdec/h265d/hal_h265d_vdpu382.c
@@ -30,7 +30,6 @@
 #include "hal_h265d_com.h"
 #include "hal_h265d_vdpu382.h"
 #include "vdpu382_h265d.h"
-#include "rk_hdr_meta_com.h"
 
 /* #define dump */
 #ifdef dump
@@ -77,10 +76,10 @@ static const FilterdColBufRatio filterd_fbc_on[CTU][FMT] = {
 };
 
 static const FilterdColBufRatio filterd_fbc_off[CTU][FMT] = {
-    /* 400    420      422       444 */
-    {{0, 0}, {9, 31}, {12, 39}, {12, 39}}, //ctu 16
-    {{0, 0}, {9, 25}, {12, 33}, {12, 33}}, //ctu 32
-    {{0, 0}, {9, 21}, {12, 29}, {12, 29}}  //ctu 64
+    /* 400     420       422       444 */
+    {{0, 0}, {15, 5},  {20, 5},  {20, 5}},  //ctu 16
+    {{0, 0}, {15, 9},  {20, 9},  {20, 9}},  //ctu 32
+    {{0, 0}, {15, 16}, {20, 16}, {20, 16}}  //ctu 64
 };
 
 #define CABAC_TAB_ALIGEND_SIZE          (MPP_ALIGN(27456, SZ_4K))
@@ -160,26 +159,6 @@ static MPP_RET hal_h265d_vdpu382_init(void *hal, MppHalCfg *cfg)
         return ret;
     }
 
-    {
-        // report hw_info to parser
-        const MppSocInfo *info = mpp_get_soc_info();
-        const void *hw_info = NULL;
-        RK_U32 i;
-
-        for (i = 0; i < MPP_ARRAY_ELEMS(info->dec_caps); i++) {
-            if (info->dec_caps[i] && info->dec_caps[i]->type == VPU_CLIENT_RKVDEC) {
-                hw_info = info->dec_caps[i];
-                break;
-            }
-        }
-
-        mpp_assert(hw_info);
-        cfg->hw_info = hw_info;
-
-        //save hw_info to context
-        reg_ctx->hw_info = hw_info;
-    }
-
     if (cfg->hal_fbc_adj_cfg) {
         cfg->hal_fbc_adj_cfg->func = vdpu382_afbc_align_calc;
         cfg->hal_fbc_adj_cfg->expand = 16;
@@ -555,7 +534,7 @@ static void h265d_refine_rcb_size(Vdpu382RcbInfo *rcb_info,
             RK_U32 a = filterd_fbc_off[ctu_idx][chroma_fmt_idc].a;
             RK_U32 b = filterd_fbc_off[ctu_idx][chroma_fmt_idc].b;
 
-            rcb_bits = height * (a * bit_depth + b + (bit_depth == 10 ? 192 * ctu_size >> 4 : 0));
+            rcb_bits = height * (a * bit_depth + b);
         }
     } else
         rcb_bits = 0;
@@ -629,7 +608,45 @@ static void hal_h265d_rcb_info_update(void *hal,  void *dxva,
     }while(0)
 
 #define pocdistance(a, b) (((a) > (b)) ? ((a) - (b)) : ((b) - (a)))
-#define MAX_INT           2147483647
+
+static MPP_RET hal_h265d_vdpu382_setup_colmv_buf(void *hal, HalTaskInfo *syn)
+{
+    HalH265dCtx *reg_ctx = ( HalH265dCtx *)hal;
+    h265d_dxva2_picture_context_t *dxva_cxt = (h265d_dxva2_picture_context_t *)syn->dec.syntax.data;
+    DXVA_PicParams_HEVC *pp = &dxva_cxt->pp;
+    RK_U8 ctu_size = 1 << (pp->log2_diff_max_min_luma_coding_block_size +
+                           pp->log2_min_luma_coding_block_size_minus3 + 3);
+    RK_U32 log2_min_cb_size = dxva_cxt->pp.log2_min_luma_coding_block_size_minus3 + 3;
+
+    RK_U32 width = (dxva_cxt->pp.PicWidthInMinCbsY << log2_min_cb_size);
+    RK_U32 height = (dxva_cxt->pp.PicHeightInMinCbsY << log2_min_cb_size);
+    RK_U32 mv_size = 0, colmv_size = 16, colmv_byte = 16;
+    RK_U32 compress = reg_ctx->hw_info ? reg_ctx->hw_info->cap_colmv_compress : 1;
+
+
+    mv_size = vdpu382_get_colmv_size(width, height, ctu_size, colmv_byte, colmv_size, compress);
+
+    if (reg_ctx->cmv_bufs == NULL || reg_ctx->mv_size < mv_size) {
+        size_t size = mv_size;
+
+        if (reg_ctx->cmv_bufs) {
+            hal_bufs_deinit(reg_ctx->cmv_bufs);
+            reg_ctx->cmv_bufs = NULL;
+        }
+
+        hal_bufs_init(&reg_ctx->cmv_bufs);
+        if (reg_ctx->cmv_bufs == NULL) {
+            mpp_err_f("colmv bufs init fail");
+            return MPP_ERR_NOMEM;;
+        }
+
+        reg_ctx->mv_size = mv_size;
+        reg_ctx->mv_count = mpp_buf_slot_get_count(reg_ctx->slots);
+        hal_bufs_setup(reg_ctx->cmv_bufs, reg_ctx->mv_count, 1, &size);
+    }
+
+    return MPP_OK;
+}
 
 static MPP_RET hal_h265d_vdpu382_gen_regs(void *hal,  HalTaskInfo *syn)
 {
@@ -645,8 +662,7 @@ static MPP_RET hal_h265d_vdpu382_gen_regs(void *hal,  HalTaskInfo *syn)
     MppBuffer framebuf = NULL;
     HalBuf *mv_buf = NULL;
     RK_S32 fd = -1;
-    RK_U32 mv_size = 0;
-    RK_S32 distance = MAX_INT;
+    RK_S32 distance = INT_MAX;
     h265d_dxva2_picture_context_t *dxva_cxt =
         (h265d_dxva2_picture_context_t *)syn->dec.syntax.data;
     HalH265dCtx *reg_ctx = ( HalH265dCtx *)hal;
@@ -677,6 +693,8 @@ static MPP_RET hal_h265d_vdpu382_gen_regs(void *hal,  HalTaskInfo *syn)
             mpp_err("hevc rps buf all used");
             return MPP_ERR_NOMEM;
         }
+    } else {
+        syn->dec.reg_index = 0;
     }
     rps_ptr = mpp_buffer_get_ptr(reg_ctx->bufs) + reg_ctx->rps_offset;
     if (NULL == rps_ptr) {
@@ -706,25 +724,9 @@ static MPP_RET hal_h265d_vdpu382_gen_regs(void *hal,  HalTaskInfo *syn)
 
     width = (dxva_cxt->pp.PicWidthInMinCbsY << log2_min_cb_size);
     height = (dxva_cxt->pp.PicHeightInMinCbsY << log2_min_cb_size);
-    mv_size = (MPP_ALIGN(width, 64) * MPP_ALIGN(height, 64)) >> 3;
-    if (reg_ctx->cmv_bufs == NULL || reg_ctx->mv_size < mv_size) {
-        size_t size = mv_size;
-
-        if (reg_ctx->cmv_bufs) {
-            hal_bufs_deinit(reg_ctx->cmv_bufs);
-            reg_ctx->cmv_bufs = NULL;
-        }
-
-        hal_bufs_init(&reg_ctx->cmv_bufs);
-        if (reg_ctx->cmv_bufs == NULL) {
-            mpp_err_f("colmv bufs init fail");
-            return MPP_ERR_NULL_PTR;
-        }
-
-        reg_ctx->mv_size = mv_size;
-        reg_ctx->mv_count = mpp_buf_slot_get_count(reg_ctx->slots);
-        hal_bufs_setup(reg_ctx->cmv_bufs, reg_ctx->mv_count, 1, &size);
-    }
+    ret = hal_h265d_vdpu382_setup_colmv_buf(hal, syn);
+    if (ret)
+        return MPP_ERR_NOMEM;
 
     {
         MppFrame mframe = NULL;
@@ -760,9 +762,6 @@ static MPP_RET hal_h265d_vdpu382_gen_regs(void *hal,  HalTaskInfo *syn)
             hw_regs->common.reg019.uv_hor_virstride = stride_uv >> 4;
             hw_regs->common.reg020_y_virstride.y_virstride = virstrid_y >> 4;
         }
-
-        if (MPP_FRAME_FMT_IS_HDR(mpp_frame_get_fmt(mframe)) && reg_ctx->cfg->base.enable_hdr_meta)
-            fill_hdr_meta_to_frame(mframe, HDR_HEVC);
     }
     mpp_buf_slot_get_prop(reg_ctx->slots, dxva_cxt->pp.CurrPic.Index7Bits,
                           SLOT_BUFFER, &framebuf);
@@ -839,7 +838,7 @@ static MPP_RET hal_h265d_vdpu382_gen_regs(void *hal,  HalTaskInfo *syn)
     hw_regs->common.reg032_timeout_threshold = 0x3ffff;
 
     valid_ref = hw_regs->common_addr.reg130_decout_base;
-    reg_ctx->error_index = dxva_cxt->pp.CurrPic.Index7Bits;
+    reg_ctx->error_index[syn->dec.reg_index] = dxva_cxt->pp.CurrPic.Index7Bits;
     hw_regs->common_addr.reg132_error_ref_base = valid_ref;
 
     memset(&hw_regs->highpoc.reg205, 0, sizeof(RK_U32));
@@ -863,7 +862,7 @@ static MPP_RET hal_h265d_vdpu382_gen_regs(void *hal,  HalTaskInfo *syn)
                     && (!mpp_frame_get_errinfo(mframe))) {
                     distance = pocdistance(dxva_cxt->pp.PicOrderCntValList[i], dxva_cxt->pp.current_poc);
                     hw_regs->common_addr.reg132_error_ref_base = hw_regs->h265d_addr.reg164_179_ref_base[i];
-                    reg_ctx->error_index = dxva_cxt->pp.RefPicList[i].Index7Bits;
+                    reg_ctx->error_index[syn->dec.reg_index] = dxva_cxt->pp.RefPicList[i].Index7Bits;
                     hw_regs->common.reg021.error_intra_mode = 0;
 
                 }
@@ -878,8 +877,9 @@ static MPP_RET hal_h265d_vdpu382_gen_regs(void *hal,  HalTaskInfo *syn)
         }
     }
 
-    if ((reg_ctx->error_index == dxva_cxt->pp.CurrPic.Index7Bits) && !dxva_cxt->pp.IntraPicFlag) {
-        // mpp_err("current frm may be err, should skip process");
+    if ((reg_ctx->error_index[syn->dec.reg_index] == dxva_cxt->pp.CurrPic.Index7Bits) &&
+        !dxva_cxt->pp.IntraPicFlag && !reg_ctx->cfg->base.disable_error) {
+        h265h_dbg(H265H_DBG_TASK_ERR, "current frm may be err, should skip process");
         syn->dec.flags.ref_err = 1;
         return MPP_OK;
     }
@@ -898,16 +898,16 @@ static MPP_RET hal_h265d_vdpu382_gen_regs(void *hal,  HalTaskInfo *syn)
                                   SLOT_FRAME_PTR, &mframe);
 
             if (framebuf == NULL || mpp_frame_get_errinfo(mframe)) {
-                mv_buf = hal_bufs_get_buf(reg_ctx->cmv_bufs, reg_ctx->error_index);
+                mv_buf = hal_bufs_get_buf(reg_ctx->cmv_bufs, reg_ctx->error_index[syn->dec.reg_index]);
                 hw_regs->h265d_addr.reg164_179_ref_base[i] = hw_regs->common_addr.reg132_error_ref_base;
                 hw_regs->h265d_addr.reg181_196_colmv_base[i] = mpp_buffer_get_fd(mv_buf->buf[0]);
             }
         } else {
-            mv_buf = hal_bufs_get_buf(reg_ctx->cmv_bufs, reg_ctx->error_index);
+            mv_buf = hal_bufs_get_buf(reg_ctx->cmv_bufs, reg_ctx->error_index[syn->dec.reg_index]);
             hw_regs->h265d_addr.reg164_179_ref_base[i] = hw_regs->common_addr.reg132_error_ref_base;
             hw_regs->h265d_addr.reg181_196_colmv_base[i] = mpp_buffer_get_fd(mv_buf->buf[0]);
             /* mark 3 to differ from current frame */
-            if (reg_ctx->error_index == dxva_cxt->pp.CurrPic.Index7Bits)
+            if (reg_ctx->error_index[syn->dec.reg_index] == dxva_cxt->pp.CurrPic.Index7Bits)
                 SET_POC_HIGNBIT_INFO(hw_regs->highpoc, i, poc_highbit, 3);
         }
     }
@@ -1083,12 +1083,6 @@ static MPP_RET hal_h265d_vdpu382_wait(void *hal, HalTaskInfo *task)
     Vdpu382H265dRegSet *hw_regs = NULL;
     RK_S32 i;
 
-    if (task->dec.flags.parse_err ||
-        task->dec.flags.ref_err) {
-        h265h_dbg(H265H_DBG_TASK_ERR, "%s found task error\n", __FUNCTION__);
-        goto ERR_PROC;
-    }
-
     if (reg_ctx->fast_mode) {
         hw_regs = ( Vdpu382H265dRegSet *)reg_ctx->g_buf[index].hw_regs;
     } else {
@@ -1097,6 +1091,12 @@ static MPP_RET hal_h265d_vdpu382_wait(void *hal, HalTaskInfo *task)
 
     p = (RK_U8*)hw_regs;
 
+    if (task->dec.flags.parse_err ||
+        task->dec.flags.ref_err) {
+        h265h_dbg(H265H_DBG_TASK_ERR, "%s found task error\n", __FUNCTION__);
+        goto ERR_PROC;
+    }
+
     ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_CMD_POLL, NULL);
     if (ret)
         mpp_err_f("poll cmd failed %d\n", ret);
diff --git a/mpp/hal/rkdec/h265d/hal_h265d_vdpu383.c b/mpp/hal/rkdec/h265d/hal_h265d_vdpu383.c
new file mode 100644
index 000000000..ee18faaf9
--- /dev/null
+++ b/mpp/hal/rkdec/h265d/hal_h265d_vdpu383.c
@@ -0,0 +1,1492 @@
+/* SPDX-License-Identifier: Apache-2.0 OR MIT */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#define MODULE_TAG "hal_h265d_vdpu383"
+
+#include <stdio.h>
+#include <string.h>
+#include <unistd.h>
+#include <stdarg.h>
+#include <inttypes.h>
+#include <ctype.h>
+#include <sys/stat.h>
+#include <sys/types.h>
+
+#include "mpp_env.h"
+#include "mpp_mem.h"
+#include "mpp_bitread.h"
+#include "mpp_bitput.h"
+#include "mpp_buffer_impl.h"
+
+#include "h265d_syntax.h"
+#include "hal_h265d_debug.h"
+#include "hal_h265d_ctx.h"
+#include "hal_h265d_com.h"
+#include "hal_h265d_vdpu383.h"
+#include "vdpu383_h265d.h"
+#include "vdpu383_com.h"
+
+#define HW_RPS
+#define PPS_SIZE                (112 * 64)//(96x64)
+
+#define FMT 4
+#define CTU 3
+
+typedef struct {
+    RK_U32 a;
+    RK_U32 b;
+} FilterdColBufRatio;
+
+#if 0
+static const FilterdColBufRatio filterd_fbc_on[CTU][FMT] = {
+    /* 400    420      422       444 */
+    {{0, 0}, {27, 15}, {36, 15}, {52, 15}}, //ctu 16
+    {{0, 0}, {27, 8},  {36, 8},  {52, 8}}, //ctu 32
+    {{0, 0}, {27, 5},  {36, 5},  {52, 5}}  //ctu 64
+};
+
+static const FilterdColBufRatio filterd_fbc_off[CTU][FMT] = {
+    /* 400    420      422       444 */
+    {{0, 0}, {9, 31}, {12, 39}, {12, 39}}, //ctu 16
+    {{0, 0}, {9, 25}, {12, 33}, {12, 33}}, //ctu 32
+    {{0, 0}, {9, 21}, {12, 29}, {12, 29}}  //ctu 64
+};
+#endif
+
+#define CABAC_TAB_ALIGEND_SIZE          (MPP_ALIGN(27456, SZ_4K))
+#define SPSPPS_ALIGNED_SIZE             (MPP_ALIGN(176, SZ_4K))
+#define RPS_ALIGEND_SIZE                (MPP_ALIGN(400 * 8, SZ_4K))
+#define SCALIST_ALIGNED_SIZE            (MPP_ALIGN(81 * 1360, SZ_4K))
+#define INFO_BUFFER_SIZE                (SPSPPS_ALIGNED_SIZE + RPS_ALIGEND_SIZE + SCALIST_ALIGNED_SIZE)
+#define ALL_BUFFER_SIZE(cnt)            (CABAC_TAB_ALIGEND_SIZE + INFO_BUFFER_SIZE *cnt)
+
+#define CABAC_TAB_OFFSET                (0)
+#define SPSPPS_OFFSET(pos)              (CABAC_TAB_OFFSET + CABAC_TAB_ALIGEND_SIZE + (INFO_BUFFER_SIZE * pos))
+#define RPS_OFFSET(pos)                 (SPSPPS_OFFSET(pos) + SPSPPS_ALIGNED_SIZE)
+#define SCALIST_OFFSET(pos)             (RPS_OFFSET(pos) + RPS_ALIGEND_SIZE)
+
+#define pocdistance(a, b)               (((a) > (b)) ? ((a) - (b)) : ((b) - (a)))
+
+static RK_U32 rkv_len_align_422(RK_U32 val)
+{
+    return (2 * MPP_ALIGN(val, 16));
+}
+
+static RK_U32 rkv_len_align_444(RK_U32 val)
+{
+    return (3 * MPP_ALIGN(val, 16));
+}
+
+static MPP_RET vdpu383_setup_scale_origin_bufs(HalH265dCtx *ctx, MppFrame mframe)
+{
+    /* for 8K FrameBuf scale mode */
+    size_t origin_buf_size = 0;
+
+    origin_buf_size = mpp_frame_get_buf_size(mframe);
+
+    if (!origin_buf_size) {
+        mpp_err_f("origin_bufs get buf size failed\n");
+        return MPP_NOK;
+    }
+
+    if (ctx->origin_bufs) {
+        hal_bufs_deinit(ctx->origin_bufs);
+        ctx->origin_bufs = NULL;
+    }
+    hal_bufs_init(&ctx->origin_bufs);
+    if (!ctx->origin_bufs) {
+        mpp_err_f("origin_bufs init fail\n");
+        return MPP_ERR_NOMEM;
+    }
+
+    hal_bufs_setup(ctx->origin_bufs, 16, 1, &origin_buf_size);
+
+    return MPP_OK;
+}
+
+static MPP_RET hal_h265d_vdpu383_init(void *hal, MppHalCfg *cfg)
+{
+    RK_S32 ret = 0;
+    HalH265dCtx *reg_ctx = (HalH265dCtx *)hal;
+
+    mpp_slots_set_prop(reg_ctx->slots, SLOTS_HOR_ALIGN, mpp_align_128_odd_plus_64);
+    mpp_slots_set_prop(reg_ctx->slots, SLOTS_VER_ALIGN, hevc_ver_align);
+
+    reg_ctx->scaling_qm = mpp_calloc(DXVA_Qmatrix_HEVC, 1);
+    if (reg_ctx->scaling_qm == NULL) {
+        mpp_err("scaling_org alloc fail");
+        return MPP_ERR_MALLOC;
+    }
+
+    reg_ctx->scaling_rk = mpp_calloc(scalingFactor_t, 1);
+    reg_ctx->pps_buf = mpp_calloc(RK_U64, 24);
+    reg_ctx->sw_rps_buf = mpp_calloc(RK_U64, 400);
+
+    if (reg_ctx->scaling_rk == NULL) {
+        mpp_err("scaling_rk alloc fail");
+        return MPP_ERR_MALLOC;
+    }
+
+    if (reg_ctx->group == NULL) {
+        ret = mpp_buffer_group_get_internal(&reg_ctx->group, MPP_BUFFER_TYPE_ION);
+        if (ret) {
+            mpp_err("h265d mpp_buffer_group_get failed\n");
+            return ret;
+        }
+    }
+
+    {
+        RK_U32 i = 0;
+        RK_U32 max_cnt = reg_ctx->fast_mode ? MAX_GEN_REG : 1;
+
+        //!< malloc buffers
+        ret = mpp_buffer_get(reg_ctx->group, &reg_ctx->bufs, ALL_BUFFER_SIZE(max_cnt));
+        if (ret) {
+            mpp_err("h265d mpp_buffer_get failed\n");
+            return ret;
+        }
+
+        reg_ctx->bufs_fd = mpp_buffer_get_fd(reg_ctx->bufs);
+        reg_ctx->offset_cabac = CABAC_TAB_OFFSET;
+        for (i = 0; i < max_cnt; i++) {
+            reg_ctx->g_buf[i].hw_regs = mpp_calloc_size(void, sizeof(Vdpu383H265dRegSet));
+            reg_ctx->offset_spspps[i] = SPSPPS_OFFSET(i);
+            reg_ctx->offset_rps[i] = RPS_OFFSET(i);
+            reg_ctx->offset_sclst[i] = SCALIST_OFFSET(i);
+        }
+
+        mpp_buffer_attach_dev(reg_ctx->bufs, reg_ctx->dev);
+    }
+
+    if (!reg_ctx->fast_mode) {
+        reg_ctx->hw_regs = reg_ctx->g_buf[0].hw_regs;
+        reg_ctx->spspps_offset = reg_ctx->offset_spspps[0];
+        reg_ctx->rps_offset = reg_ctx->offset_rps[0];
+        reg_ctx->sclst_offset = reg_ctx->offset_sclst[0];
+    }
+
+    ret = mpp_buffer_write(reg_ctx->bufs, 0, (void*)cabac_table, sizeof(cabac_table));
+    if (ret) {
+        mpp_err("h265d write cabac_table data failed\n");
+        return ret;
+    }
+
+    (void) cfg;
+    return MPP_OK;
+}
+
+static MPP_RET hal_h265d_vdpu383_deinit(void *hal)
+{
+    HalH265dCtx *reg_ctx = (HalH265dCtx *)hal;
+    RK_U32 loop = reg_ctx->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->g_buf) : 1;
+    RK_U32 i;
+
+    if (reg_ctx->bufs) {
+        mpp_buffer_put(reg_ctx->bufs);
+        reg_ctx->bufs = NULL;
+    }
+
+    loop = reg_ctx->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->rcb_buf) : 1;
+    for (i = 0; i < loop; i++) {
+        if (reg_ctx->rcb_buf[i]) {
+            mpp_buffer_put(reg_ctx->rcb_buf[i]);
+            reg_ctx->rcb_buf[i] = NULL;
+        }
+    }
+
+    if (reg_ctx->group) {
+        mpp_buffer_group_put(reg_ctx->group);
+        reg_ctx->group = NULL;
+    }
+
+    for (i = 0; i < loop; i++)
+        MPP_FREE(reg_ctx->g_buf[i].hw_regs);
+
+    MPP_FREE(reg_ctx->scaling_qm);
+    MPP_FREE(reg_ctx->scaling_rk);
+    MPP_FREE(reg_ctx->pps_buf);
+    MPP_FREE(reg_ctx->sw_rps_buf);
+
+    if (reg_ctx->cmv_bufs) {
+        hal_bufs_deinit(reg_ctx->cmv_bufs);
+        reg_ctx->cmv_bufs = NULL;
+    }
+
+    if (reg_ctx->origin_bufs) {
+        hal_bufs_deinit(reg_ctx->origin_bufs);
+        reg_ctx->origin_bufs = NULL;
+    }
+
+    return MPP_OK;
+}
+
+#define SCALING_LIST_NUM 6
+
+void hal_vdpu383_record_scaling_list(scalingFactor_t *pScalingFactor_out, scalingList_t *pScalingList)
+{
+    RK_S32 i;
+    RK_U32 listId;
+    BitputCtx_t bp;
+
+    mpp_set_bitput_ctx(&bp, (RK_U64 *)pScalingFactor_out, 170); // 170*64bits
+
+    //-------- following make it by hardware needed --------
+    //sizeId == 0, block4x4
+    for (listId = 0; listId < SCALING_LIST_NUM; listId++) {
+        RK_U8 *p_data = pScalingList->sl[0][listId];
+        /* dump by block4x4, vectial direction */
+        for (i = 0; i < 4; i++) {
+            mpp_put_bits(&bp, p_data[i + 0], 8);
+            mpp_put_bits(&bp, p_data[i + 4], 8);
+            mpp_put_bits(&bp, p_data[i + 8], 8);
+            mpp_put_bits(&bp, p_data[i + 12], 8);
+        }
+    }
+    //sizeId == 1, block8x8
+    for (listId = 0; listId < SCALING_LIST_NUM; listId++) {
+        RK_S32 blk4_x = 0, blk4_y = 0;
+        RK_U8 *p_data = pScalingList->sl[1][listId];
+
+        /* dump by block4x4, vectial direction */
+        for (blk4_x = 0; blk4_x < 8; blk4_x += 4) {
+            for (blk4_y = 0; blk4_y < 8; blk4_y += 4) {
+                RK_S32 pos = blk4_y * 8 + blk4_x;
+
+                for (i = 0; i < 4; i++) {
+                    mpp_put_bits(&bp, p_data[pos + i + 0], 8);
+                    mpp_put_bits(&bp, p_data[pos + i + 8], 8);
+                    mpp_put_bits(&bp, p_data[pos + i + 16], 8);
+                    mpp_put_bits(&bp, p_data[pos + i + 24], 8);
+                }
+            }
+        }
+    }
+    //sizeId == 2, block16x16
+    for (listId = 0; listId < SCALING_LIST_NUM; listId++) {
+        RK_S32 blk4_x = 0, blk4_y = 0;
+        RK_U8 *p_data = pScalingList->sl[2][listId];
+
+        /* dump by block4x4, vectial direction */
+        for (blk4_x = 0; blk4_x < 8; blk4_x += 4) {
+            for (blk4_y = 0; blk4_y < 8; blk4_y += 4) {
+                RK_S32 pos = blk4_y * 8 + blk4_x;
+
+                for (i = 0; i < 4; i++) {
+                    mpp_put_bits(&bp, p_data[pos + i + 0], 8);
+                    mpp_put_bits(&bp, p_data[pos + i + 8], 8);
+                    mpp_put_bits(&bp, p_data[pos + i + 16], 8);
+                    mpp_put_bits(&bp, p_data[pos + i + 24], 8);
+                }
+            }
+        }
+    }
+    //sizeId == 3, blcok32x32
+    for (listId = 0; listId < 6; listId++) {
+        RK_S32 blk4_x = 0, blk4_y = 0;
+        RK_U8 *p_data = pScalingList->sl[3][listId];
+
+        /* dump by block4x4, vectial direction */
+        for (blk4_x = 0; blk4_x < 8; blk4_x += 4) {
+            for (blk4_y = 0; blk4_y < 8; blk4_y += 4) {
+                RK_S32 pos = blk4_y * 8 + blk4_x;
+
+                for (i = 0; i < 4; i++) {
+                    mpp_put_bits(&bp, p_data[pos + i + 0], 8);
+                    mpp_put_bits(&bp, p_data[pos + i + 8], 8);
+                    mpp_put_bits(&bp, p_data[pos + i + 16], 8);
+                    mpp_put_bits(&bp, p_data[pos + i + 24], 8);
+                }
+            }
+        }
+    }
+    //sizeId == 0, block4x4, horiztion direction */
+    for (listId = 0; listId < SCALING_LIST_NUM; listId++) {
+        RK_U8 *p_data = pScalingList->sl[0][listId];
+
+        for (i = 0; i < 16; i++)
+            mpp_put_bits(&bp, p_data[i], 8);
+    }
+
+    // dump dc value
+    for (i = 0; i < SCALING_LIST_NUM; i++)//sizeId = 2, 16x16
+        mpp_put_bits(&bp, pScalingList->sl_dc[0][i], 8);
+    for (i = 0; i < SCALING_LIST_NUM; i++) //sizeId = 3, 32x32
+        mpp_put_bits(&bp, pScalingList->sl_dc[1][i], 8);
+
+    mpp_put_align(&bp, 128, 0);
+}
+
+static MPP_RET hal_h265d_vdpu383_scalinglist_packet(void *hal, void *ptr, void *dxva)
+{
+    scalingList_t sl;
+    RK_U32 i, j, pos;
+    h265d_dxva2_picture_context_t *dxva_ctx = (h265d_dxva2_picture_context_t*)dxva;
+    HalH265dCtx *reg_ctx = ( HalH265dCtx *)hal;
+
+    if (!dxva_ctx->pp.scaling_list_enabled_flag) {
+        return MPP_OK;
+    }
+
+    if (memcmp((void*)&dxva_ctx->qm, reg_ctx->scaling_qm, sizeof(DXVA_Qmatrix_HEVC))) {
+        memset(&sl, 0, sizeof(scalingList_t));
+
+        for (i = 0; i < 6; i++) {
+            for (j = 0; j < 16; j++) {
+                pos = 4 * hal_hevc_diag_scan4x4_y[j] + hal_hevc_diag_scan4x4_x[j];
+                sl.sl[0][i][pos] = dxva_ctx->qm.ucScalingLists0[i][j];
+            }
+
+            for (j = 0; j < 64; j++) {
+                pos = 8 * hal_hevc_diag_scan8x8_y[j] + hal_hevc_diag_scan8x8_x[j];
+                sl.sl[1][i][pos] =  dxva_ctx->qm.ucScalingLists1[i][j];
+                sl.sl[2][i][pos] =  dxva_ctx->qm.ucScalingLists2[i][j];
+
+                if (i == 0)
+                    sl.sl[3][i][pos] =  dxva_ctx->qm.ucScalingLists3[0][j];
+                else if (i == 3)
+                    sl.sl[3][i][pos] =  dxva_ctx->qm.ucScalingLists3[1][j];
+                else
+                    sl.sl[3][i][pos] =  dxva_ctx->qm.ucScalingLists2[i][j];
+            }
+
+            sl.sl_dc[0][i] =  dxva_ctx->qm.ucScalingListDCCoefSizeID2[i];
+            if (i == 0)
+                sl.sl_dc[1][i] =  dxva_ctx->qm.ucScalingListDCCoefSizeID3[0];
+            else if (i == 3)
+                sl.sl_dc[1][i] =  dxva_ctx->qm.ucScalingListDCCoefSizeID3[1];
+            else
+                sl.sl_dc[1][i] =  dxva_ctx->qm.ucScalingListDCCoefSizeID2[i];
+        }
+        hal_vdpu383_record_scaling_list((scalingFactor_t *)reg_ctx->scaling_rk, &sl);
+    }
+
+    memcpy(ptr, reg_ctx->scaling_rk, sizeof(scalingFactor_t));
+
+    return MPP_OK;
+}
+
+static RK_S32 hal_h265d_v345_output_pps_packet(void *hal, void *dxva)
+{
+    RK_S32 i;
+    RK_U32 log2_min_cb_size;
+    RK_S32 width, height;
+    HalH265dCtx *reg_ctx = ( HalH265dCtx *)hal;
+    Vdpu383H265dRegSet *hw_reg = (Vdpu383H265dRegSet*)(reg_ctx->hw_regs);
+    h265d_dxva2_picture_context_t *dxva_ctx = (h265d_dxva2_picture_context_t*)dxva;
+    BitputCtx_t bp;
+
+    if (NULL == reg_ctx || dxva_ctx == NULL) {
+        mpp_err("%s:%s:%d reg_ctx or dxva_ctx is NULL",
+                __FILE__, __FUNCTION__, __LINE__);
+        return MPP_ERR_NULL_PTR;
+    }
+
+    // SPS
+    {
+        void *pps_ptr = mpp_buffer_get_ptr(reg_ctx->bufs) + reg_ctx->spspps_offset;
+        RK_U64 *pps_packet = reg_ctx->pps_buf;
+
+        if (NULL == pps_ptr) {
+            mpp_err("pps_data get ptr error");
+            return MPP_ERR_NOMEM;
+        }
+
+        log2_min_cb_size = dxva_ctx->pp.log2_min_luma_coding_block_size_minus3 + 3;
+        width = (dxva_ctx->pp.PicWidthInMinCbsY << log2_min_cb_size);
+        height = (dxva_ctx->pp.PicHeightInMinCbsY << log2_min_cb_size);
+
+        mpp_set_bitput_ctx(&bp, pps_packet, 22); // 22*64bits
+
+        if (dxva_ctx->pp.ps_update_flag) {
+            mpp_put_bits(&bp, dxva_ctx->pp.vps_id, 4);
+            mpp_put_bits(&bp, dxva_ctx->pp.sps_id, 4);
+            mpp_put_bits(&bp, dxva_ctx->pp.chroma_format_idc, 2);
+
+            mpp_put_bits(&bp, width, 16);
+            mpp_put_bits(&bp, height, 16);
+            mpp_put_bits(&bp, dxva_ctx->pp.bit_depth_luma_minus8, 3);
+            mpp_put_bits(&bp, dxva_ctx->pp.bit_depth_chroma_minus8, 3);
+            mpp_put_bits(&bp, dxva_ctx->pp.log2_max_pic_order_cnt_lsb_minus4 + 4, 5);
+            mpp_put_bits(&bp, dxva_ctx->pp.log2_diff_max_min_luma_coding_block_size, 2);
+            mpp_put_bits(&bp, dxva_ctx->pp.log2_min_luma_coding_block_size_minus3 + 3, 3);
+            mpp_put_bits(&bp, dxva_ctx->pp.log2_min_transform_block_size_minus2 + 2, 3);
+
+            mpp_put_bits(&bp, dxva_ctx->pp.log2_diff_max_min_transform_block_size, 2);
+            mpp_put_bits(&bp, dxva_ctx->pp.max_transform_hierarchy_depth_inter, 3);
+            mpp_put_bits(&bp, dxva_ctx->pp.max_transform_hierarchy_depth_intra, 3);
+            mpp_put_bits(&bp, dxva_ctx->pp.scaling_list_enabled_flag, 1);
+            mpp_put_bits(&bp, dxva_ctx->pp.amp_enabled_flag, 1);
+            mpp_put_bits(&bp, dxva_ctx->pp.sample_adaptive_offset_enabled_flag, 1);
+            ///<-zrh comment ^  68 bit above
+            mpp_put_bits(&bp, dxva_ctx->pp.pcm_enabled_flag, 1);
+            mpp_put_bits(&bp, dxva_ctx->pp.pcm_enabled_flag ? (dxva_ctx->pp.pcm_sample_bit_depth_luma_minus1 + 1) : 0, 4);
+            mpp_put_bits(&bp, dxva_ctx->pp.pcm_enabled_flag ? (dxva_ctx->pp.pcm_sample_bit_depth_chroma_minus1 + 1) : 0, 4);
+            mpp_put_bits(&bp, dxva_ctx->pp.pcm_loop_filter_disabled_flag, 1);
+            mpp_put_bits(&bp, dxva_ctx->pp.log2_diff_max_min_pcm_luma_coding_block_size, 3);
+            mpp_put_bits(&bp, dxva_ctx->pp.pcm_enabled_flag ? (dxva_ctx->pp.log2_min_pcm_luma_coding_block_size_minus3 + 3) : 0, 3);
+
+            mpp_put_bits(&bp, dxva_ctx->pp.num_short_term_ref_pic_sets, 7);
+            mpp_put_bits(&bp, dxva_ctx->pp.long_term_ref_pics_present_flag, 1);
+            mpp_put_bits(&bp, dxva_ctx->pp.num_long_term_ref_pics_sps, 6);
+            mpp_put_bits(&bp, dxva_ctx->pp.sps_temporal_mvp_enabled_flag, 1);
+            mpp_put_bits(&bp, dxva_ctx->pp.strong_intra_smoothing_enabled_flag, 1);
+            // SPS extenstion
+            mpp_put_bits(&bp, dxva_ctx->pp.transform_skip_rotation_enabled_flag, 1);
+            mpp_put_bits(&bp, dxva_ctx->pp.transform_skip_context_enabled_flag, 1);
+            mpp_put_bits(&bp, dxva_ctx->pp.strong_intra_smoothing_enabled_flag, 1);
+            mpp_put_bits(&bp, dxva_ctx->pp.implicit_rdpcm_enabled_flag, 1);
+            mpp_put_bits(&bp, dxva_ctx->pp.explicit_rdpcm_enabled_flag, 1);
+            mpp_put_bits(&bp, dxva_ctx->pp.extended_precision_processing_flag, 1);
+            mpp_put_bits(&bp, dxva_ctx->pp.intra_smoothing_disabled_flag, 1);
+            mpp_put_bits(&bp, dxva_ctx->pp.sps_max_dec_pic_buffering_minus1, 4);
+            mpp_put_bits(&bp, dxva_ctx->pp.separate_colour_plane_flag, 1);
+            mpp_put_bits(&bp, dxva_ctx->pp.high_precision_offsets_enabled_flag, 1);
+            mpp_put_bits(&bp, dxva_ctx->pp.persistent_rice_adaptation_enabled_flag, 1);
+
+            /* PPS */
+            mpp_put_bits(&bp, dxva_ctx->pp.pps_id, 6);
+            mpp_put_bits(&bp, dxva_ctx->pp.sps_id, 4);
+            mpp_put_bits(&bp, dxva_ctx->pp.dependent_slice_segments_enabled_flag, 1);
+            mpp_put_bits(&bp, dxva_ctx->pp.output_flag_present_flag, 1);
+            mpp_put_bits(&bp, dxva_ctx->pp.num_extra_slice_header_bits, 13);
+
+            mpp_put_bits(&bp, dxva_ctx->pp.sign_data_hiding_enabled_flag, 1);
+            mpp_put_bits(&bp, dxva_ctx->pp.cabac_init_present_flag, 1);
+            mpp_put_bits(&bp, dxva_ctx->pp.num_ref_idx_l0_default_active_minus1 + 1, 4);
+            mpp_put_bits(&bp, dxva_ctx->pp.num_ref_idx_l1_default_active_minus1 + 1, 4);
+            mpp_put_bits(&bp, dxva_ctx->pp.init_qp_minus26, 7);
+            mpp_put_bits(&bp, dxva_ctx->pp.constrained_intra_pred_flag, 1);
+            mpp_put_bits(&bp, dxva_ctx->pp.transform_skip_enabled_flag, 1);
+            mpp_put_bits(&bp, dxva_ctx->pp.cu_qp_delta_enabled_flag, 1);
+            mpp_put_bits(&bp, log2_min_cb_size + dxva_ctx->pp.log2_diff_max_min_luma_coding_block_size - dxva_ctx->pp.diff_cu_qp_delta_depth, 3);
+
+            mpp_put_bits(&bp, dxva_ctx->pp.pps_cb_qp_offset, 5);
+            mpp_put_bits(&bp, dxva_ctx->pp.pps_cr_qp_offset, 5);
+            mpp_put_bits(&bp, dxva_ctx->pp.pps_slice_chroma_qp_offsets_present_flag, 1);
+            mpp_put_bits(&bp, dxva_ctx->pp.weighted_pred_flag, 1);
+            mpp_put_bits(&bp, dxva_ctx->pp.weighted_bipred_flag, 1);
+            mpp_put_bits(&bp, dxva_ctx->pp.transquant_bypass_enabled_flag, 1);
+            mpp_put_bits(&bp, dxva_ctx->pp.tiles_enabled_flag, 1);
+            mpp_put_bits(&bp, dxva_ctx->pp.entropy_coding_sync_enabled_flag, 1);
+            mpp_put_bits(&bp, dxva_ctx->pp.pps_loop_filter_across_slices_enabled_flag, 1);
+
+            mpp_put_bits(&bp, dxva_ctx->pp.loop_filter_across_tiles_enabled_flag, 1);
+            mpp_put_bits(&bp, dxva_ctx->pp.deblocking_filter_override_enabled_flag, 1);
+            mpp_put_bits(&bp, dxva_ctx->pp.pps_deblocking_filter_disabled_flag, 1);
+            mpp_put_bits(&bp, dxva_ctx->pp.pps_beta_offset_div2, 4);
+            mpp_put_bits(&bp, dxva_ctx->pp.pps_tc_offset_div2, 4);
+            mpp_put_bits(&bp, dxva_ctx->pp.lists_modification_present_flag, 1);
+            mpp_put_bits(&bp, dxva_ctx->pp.log2_parallel_merge_level_minus2 + 2, 3);
+            mpp_put_bits(&bp, dxva_ctx->pp.slice_segment_header_extension_present_flag, 1);
+            mpp_put_bits(&bp, 0, 3);
+
+            // PPS externsion
+            if (dxva_ctx->pp.log2_max_transform_skip_block_size > 2) {
+                mpp_put_bits(&bp, dxva_ctx->pp.log2_max_transform_skip_block_size - 2, 2);
+            } else {
+                mpp_put_bits(&bp, 0, 2);
+            }
+            mpp_put_bits(&bp, dxva_ctx->pp.cross_component_prediction_enabled_flag, 1);
+            mpp_put_bits(&bp, dxva_ctx->pp.chroma_qp_offset_list_enabled_flag, 1);
+
+            RK_S32 log2_min_cu_chroma_qp_delta_size = log2_min_cb_size +
+                                                      dxva_ctx->pp.log2_diff_max_min_luma_coding_block_size -
+                                                      dxva_ctx->pp.diff_cu_chroma_qp_offset_depth;
+            mpp_put_bits(&bp, log2_min_cu_chroma_qp_delta_size, 3);
+            for (i = 0; i < 6; i++)
+                mpp_put_bits(&bp, dxva_ctx->pp.cb_qp_offset_list[i], 5);
+            for (i = 0; i < 6; i++)
+                mpp_put_bits(&bp, dxva_ctx->pp.cr_qp_offset_list[i], 5);
+            mpp_put_bits(&bp, dxva_ctx->pp.chroma_qp_offset_list_len_minus1, 3);
+
+            /* mvc0 && mvc1 */
+            mpp_put_bits(&bp, 0xffff, 16);
+            mpp_put_bits(&bp, 0, 1);
+            mpp_put_bits(&bp, 0, 6);
+            mpp_put_bits(&bp, 0, 1);
+            mpp_put_bits(&bp, 0, 1);
+        } else {
+            bp.index = 4;
+            bp.bitpos = 41;
+            bp.bvalue = bp.pbuf[bp.index] & MPP_GENMASK(bp.bitpos - 1, 0);
+        }
+        /* poc info */
+        {
+            RK_S32 dpb_valid[15] = {0}, refpic_poc[15] = {0};
+
+            for (i = 0; i < (RK_S32)MPP_ARRAY_ELEMS(dxva_ctx->pp.RefPicList); i++) {
+                if (dxva_ctx->pp.RefPicList[i].bPicEntry != 0xff &&
+                    dxva_ctx->pp.RefPicList[i].bPicEntry != 0x7f) {
+                    dpb_valid[i] = 1;
+                    refpic_poc[i] = dxva_ctx->pp.PicOrderCntValList[i];
+                }
+            }
+
+            mpp_put_bits(&bp, 0, 1);
+            mpp_put_bits(&bp, 0, 1);
+            mpp_put_bits(&bp, 0, 1);
+            mpp_put_bits(&bp, dxva_ctx->pp.current_poc, 32);
+
+            for (i = 0; i < 15; i++)
+                mpp_put_bits(&bp, refpic_poc[i], 32);
+            mpp_put_bits(&bp, 0, 32);
+            for (i = 0; i < 15; i++)
+                mpp_put_bits(&bp, dpb_valid[i], 1);
+            mpp_put_bits(&bp, 0, 1);
+        }
+
+        /* tile info */
+        mpp_put_bits(&bp, dxva_ctx->pp.tiles_enabled_flag ? (dxva_ctx->pp.num_tile_columns_minus1 + 1) : 1, 5);
+        mpp_put_bits(&bp, dxva_ctx->pp.tiles_enabled_flag ? (dxva_ctx->pp.num_tile_rows_minus1 + 1) : 1, 5);
+        {
+            /// tiles info begin
+            RK_U16 column_width[20];
+            RK_U16 row_height[22];
+
+            memset(column_width, 0, sizeof(column_width));
+            memset(row_height, 0, sizeof(row_height));
+
+            if (dxva_ctx->pp.tiles_enabled_flag) {
+                if (dxva_ctx->pp.uniform_spacing_flag == 0) {
+                    RK_S32 maxcuwidth = dxva_ctx->pp.log2_diff_max_min_luma_coding_block_size + log2_min_cb_size;
+                    RK_S32 ctu_width_in_pic = (width +
+                                               (1 << maxcuwidth) - 1) / (1 << maxcuwidth) ;
+                    RK_S32 ctu_height_in_pic = (height +
+                                                (1 << maxcuwidth) - 1) / (1 << maxcuwidth) ;
+                    RK_S32 sum = 0;
+                    for (i = 0; i < dxva_ctx->pp.num_tile_columns_minus1; i++) {
+                        column_width[i] = dxva_ctx->pp.column_width_minus1[i] + 1;
+                        sum += column_width[i]  ;
+                    }
+                    column_width[i] = ctu_width_in_pic - sum;
+
+                    sum = 0;
+                    for (i = 0; i < dxva_ctx->pp.num_tile_rows_minus1; i++) {
+                        row_height[i] = dxva_ctx->pp.row_height_minus1[i] + 1;
+                        sum += row_height[i];
+                    }
+                    row_height[i] = ctu_height_in_pic - sum;
+                }  else {
+                    RK_S32    pic_in_cts_width = (width +
+                                                  (1 << (log2_min_cb_size +
+                                                         dxva_ctx->pp.log2_diff_max_min_luma_coding_block_size)) - 1)
+                                                 / (1 << (log2_min_cb_size +
+                                                          dxva_ctx->pp.log2_diff_max_min_luma_coding_block_size));
+                    RK_S32 pic_in_cts_height = (height +
+                                                (1 << (log2_min_cb_size +
+                                                       dxva_ctx->pp.log2_diff_max_min_luma_coding_block_size)) - 1)
+                                               / (1 << (log2_min_cb_size +
+                                                        dxva_ctx->pp.log2_diff_max_min_luma_coding_block_size));
+
+                    for (i = 0; i < dxva_ctx->pp.num_tile_columns_minus1 + 1; i++)
+                        column_width[i] = ((i + 1) * pic_in_cts_width) / (dxva_ctx->pp.num_tile_columns_minus1 + 1) -
+                                          (i * pic_in_cts_width) / (dxva_ctx->pp.num_tile_columns_minus1 + 1);
+
+                    for (i = 0; i < dxva_ctx->pp.num_tile_rows_minus1 + 1; i++)
+                        row_height[i] = ((i + 1) * pic_in_cts_height) / (dxva_ctx->pp.num_tile_rows_minus1 + 1) -
+                                        (i * pic_in_cts_height) / (dxva_ctx->pp.num_tile_rows_minus1 + 1);
+                }
+            } else {
+                RK_S32 MaxCUWidth = (1 << (dxva_ctx->pp.log2_diff_max_min_luma_coding_block_size + log2_min_cb_size));
+                column_width[0] = (width  + MaxCUWidth - 1) / MaxCUWidth;
+                row_height[0]   = (height + MaxCUWidth - 1) / MaxCUWidth;
+            }
+
+            for (i = 0; i < 20; i++)
+                mpp_put_bits(&bp, column_width[i], 12);
+
+            for (i = 0; i < 22; i++)
+                mpp_put_bits(&bp, row_height[i], 12);
+        }
+        mpp_put_align(&bp, 64, 0);//128
+        memcpy(pps_ptr, reg_ctx->pps_buf, 176);
+    } /* --- end spspps data ------*/
+
+    if (dxva_ctx->pp.scaling_list_enabled_flag) {
+        RK_U32 addr;
+        RK_U8 *ptr_scaling = (RK_U8 *)mpp_buffer_get_ptr(reg_ctx->bufs) + reg_ctx->sclst_offset;
+
+        if (dxva_ctx->pp.scaling_list_data_present_flag) {
+            addr = (dxva_ctx->pp.pps_id + 16) * 1360;
+        } else if (dxva_ctx->pp.scaling_list_enabled_flag) {
+            addr = dxva_ctx->pp.sps_id * 1360;
+        } else {
+            addr = 80 * 1360;
+        }
+
+        hal_h265d_vdpu383_scalinglist_packet(hal, ptr_scaling + addr, dxva);
+
+        hw_reg->common_addr.reg132_scanlist_addr = reg_ctx->bufs_fd;
+        mpp_dev_set_reg_offset(reg_ctx->dev, 132, addr + reg_ctx->sclst_offset);
+    }
+
+#ifdef dump
+    fwrite(pps_ptr, 1, 80 * 64, fp);
+    RK_U32 *tmp = (RK_U32 *)pps_ptr;
+    for (i = 0; i < 112 / 4; i++) {
+        mpp_log("pps[%3d] = 0x%08x\n", i, tmp[i]);
+    }
+#endif
+#ifdef DUMP_VDPU383_DATAS
+    {
+        char *cur_fname = "global_cfg.dat";
+        memset(dump_cur_fname_path, 0, sizeof(dump_cur_fname_path));
+        sprintf(dump_cur_fname_path, "%s/%s", dump_cur_dir, cur_fname);
+        dump_data_to_file(dump_cur_fname_path, (void *)bp.pbuf, 64 * bp.index + bp.bitpos, 128, 0);
+    }
+#endif
+
+    return 0;
+}
+
+static void h265d_refine_rcb_size(Vdpu383RcbInfo *rcb_info,
+                                  RK_S32 width, RK_S32 height, void *dxva)
+{
+    RK_U32 rcb_bits = 0;
+    h265d_dxva2_picture_context_t *dxva_ctx = (h265d_dxva2_picture_context_t*)dxva;
+    DXVA_PicParams_HEVC *pp = &dxva_ctx->pp;
+    RK_U32 chroma_fmt_idc = pp->chroma_format_idc;//0 400,1 4202 ,422,3 444
+    RK_U8 bit_depth = MPP_MAX(pp->bit_depth_luma_minus8, pp->bit_depth_chroma_minus8) + 8;
+    RK_U8 ctu_size = 1 << (pp->log2_diff_max_min_luma_coding_block_size + pp->log2_min_luma_coding_block_size_minus3 + 3);
+    RK_U32 tile_row_cut_num = pp->num_tile_rows_minus1;
+    RK_U32 tile_col_cut_num = pp->num_tile_columns_minus1;
+    RK_U32 ext_row_align_size = tile_row_cut_num * 64 * 8;
+    RK_U32 ext_col_align_size = tile_col_cut_num * 64 * 8;
+    RK_U32 filterd_row_append = 8192;
+    RK_U32 row_uv_para = 0;
+    RK_U32 col_uv_para = 0;
+
+    if (chroma_fmt_idc == 1) {
+        row_uv_para = 1;
+        col_uv_para = 1;
+    } else if (chroma_fmt_idc == 2) {
+        row_uv_para = 1;
+        col_uv_para = 3;
+    } else if (chroma_fmt_idc == 3) {
+        row_uv_para = 3;
+        col_uv_para = 3;
+    }
+
+    width = MPP_ALIGN(width, ctu_size);
+    height = MPP_ALIGN(height, ctu_size);
+    /* RCB_STRMD_ROW && RCB_STRMD_TILE_ROW*/
+    rcb_info[RCB_STRMD_ROW].size = 0;
+    rcb_info[RCB_STRMD_TILE_ROW].size = 0;
+
+    /* RCB_INTER_ROW && RCB_INTER_TILE_ROW*/
+    rcb_bits = ((width + 7) / 8) * 174;
+    rcb_info[RCB_INTER_ROW].size = MPP_RCB_BYTES(rcb_bits);
+    rcb_bits += ext_row_align_size;
+    if (tile_row_cut_num)
+        rcb_info[RCB_INTER_TILE_ROW].size = MPP_RCB_BYTES(rcb_bits);
+    else
+        rcb_info[RCB_INTER_TILE_ROW].size = 0;
+
+    /* RCB_INTRA_ROW && RCB_INTRA_TILE_ROW*/
+    rcb_bits = MPP_ALIGN(width, 512) * (bit_depth + 2);
+    rcb_bits = rcb_bits * 4; //TODO:
+    rcb_info[RCB_INTRA_ROW].size = MPP_RCB_BYTES(rcb_bits);
+    rcb_bits += ext_row_align_size;
+    if (tile_row_cut_num)
+        rcb_info[RCB_INTRA_TILE_ROW].size = MPP_RCB_BYTES(rcb_bits);
+    else
+        rcb_info[RCB_INTRA_TILE_ROW].size = 0;
+
+    /* RCB_FILTERD_ROW && RCB_FILTERD_TILE_ROW*/
+    rcb_bits = (MPP_ALIGN(width, 64) * (1.6 * bit_depth + 0.5) * (8 + 5 * row_uv_para));
+    // save space mode : half for RCB_FILTERD_ROW, half for RCB_FILTERD_PROTECT_ROW
+    if (width > 4096)
+        filterd_row_append = 27648;
+    rcb_info[RCB_FILTERD_ROW].size = MPP_RCB_BYTES(rcb_bits / 2);
+    rcb_info[RCB_FILTERD_PROTECT_ROW].size = MPP_RCB_BYTES(rcb_bits / 2) + filterd_row_append;
+    rcb_bits += ext_row_align_size;
+    if (tile_row_cut_num)
+        rcb_info[RCB_FILTERD_TILE_ROW].size = MPP_RCB_BYTES(rcb_bits);
+    else
+        rcb_info[RCB_FILTERD_TILE_ROW].size = 0;
+
+    /* RCB_FILTERD_TILE_COL */
+    if (tile_col_cut_num) {
+        rcb_bits = (MPP_ALIGN(height, 64) * (1.6 * bit_depth + 0.5) * (16.5 + 5 * col_uv_para)) + ext_col_align_size;
+        rcb_info[RCB_FILTERD_TILE_COL].size = MPP_RCB_BYTES(rcb_bits);
+    } else {
+        rcb_info[RCB_FILTERD_TILE_COL].size = 0;
+    }
+
+}
+
+static void hal_h265d_rcb_info_update(void *hal,  void *dxva,
+                                      Vdpu383H265dRegSet *hw_regs,
+                                      RK_S32 width, RK_S32 height)
+{
+    HalH265dCtx *reg_ctx = ( HalH265dCtx *)hal;
+    h265d_dxva2_picture_context_t *dxva_ctx = (h265d_dxva2_picture_context_t*)dxva;
+    DXVA_PicParams_HEVC *pp = &dxva_ctx->pp;
+    RK_U32 chroma_fmt_idc = pp->chroma_format_idc;//0 400,1 4202 ,422,3 444
+    RK_U8 bit_depth = MPP_MAX(pp->bit_depth_luma_minus8, pp->bit_depth_chroma_minus8) + 8;
+    RK_U8 ctu_size = 1 << (pp->log2_diff_max_min_luma_coding_block_size + pp->log2_min_luma_coding_block_size_minus3 + 3);
+    RK_U32 num_tiles = pp->num_tile_rows_minus1 + 1;
+    (void)hw_regs;
+
+    if (reg_ctx->num_row_tiles != num_tiles ||
+        reg_ctx->bit_depth != bit_depth ||
+        reg_ctx->chroma_fmt_idc != chroma_fmt_idc ||
+        reg_ctx->ctu_size !=  ctu_size ||
+        reg_ctx->width != width ||
+        reg_ctx->height != height) {
+        RK_U32 i = 0;
+        RK_U32 loop = reg_ctx->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->g_buf) : 1;
+
+        reg_ctx->rcb_buf_size = vdpu383_get_rcb_buf_size((Vdpu383RcbInfo *)reg_ctx->rcb_info, width, height);
+        h265d_refine_rcb_size((Vdpu383RcbInfo *)reg_ctx->rcb_info, width, height, dxva_ctx);
+
+        for (i = 0; i < loop; i++) {
+            MppBuffer rcb_buf;
+
+            if (reg_ctx->rcb_buf[i]) {
+                mpp_buffer_put(reg_ctx->rcb_buf[i]);
+                reg_ctx->rcb_buf[i] = NULL;
+            }
+            mpp_buffer_get(reg_ctx->group, &rcb_buf, reg_ctx->rcb_buf_size);
+            reg_ctx->rcb_buf[i] = rcb_buf;
+        }
+
+        reg_ctx->num_row_tiles  = num_tiles;
+        reg_ctx->bit_depth      = bit_depth;
+        reg_ctx->chroma_fmt_idc = chroma_fmt_idc;
+        reg_ctx->ctu_size       = ctu_size;
+        reg_ctx->width          = width;
+        reg_ctx->height         = height;
+    }
+}
+
+static RK_S32 hal_h265d_vdpu383_rps(void *dxva, void *rps_buf, void* sw_rps_buf, RK_U32 fast_mode)
+{
+    BitputCtx_t bp;
+    RK_S32 fifo_len = 400;
+    RK_S32 i = 0, j = 0;
+    h265d_dxva2_picture_context_t *dxva_ctx = (h265d_dxva2_picture_context_t*)dxva;
+
+    if (!dxva_ctx->pp.ps_update_flag) {
+        if (fast_mode) {
+            memcpy(rps_buf, sw_rps_buf, fifo_len * sizeof(RK_U64));
+        }
+        return 0;
+    }
+
+    mpp_set_bitput_ctx(&bp, (RK_U64*)sw_rps_buf, fifo_len);
+
+    for (i = 0; i < 32; i ++) {
+        mpp_put_bits(&bp, dxva_ctx->pp.sps_lt_rps[i].lt_ref_pic_poc_lsb, 16);
+        mpp_put_bits(&bp, dxva_ctx->pp.sps_lt_rps[i].used_by_curr_pic_lt_flag, 1);
+        mpp_put_bits(&bp, 0,     15);
+    }
+
+    for (i = 0; i < 64; i++) {
+        if (i < dxva_ctx->pp.num_short_term_ref_pic_sets) {
+
+            mpp_put_bits(&bp, dxva_ctx->pp.sps_st_rps[i].num_negative_pics, 4);
+            mpp_put_bits(&bp, dxva_ctx->pp.sps_st_rps[i].num_positive_pics, 4);
+            for ( j = 0; j <  dxva_ctx->pp.sps_st_rps[i].num_negative_pics; j++) {
+
+                mpp_put_bits(&bp, dxva_ctx->pp.sps_st_rps[i].delta_poc_s0[j], 16);
+                mpp_put_bits(&bp, dxva_ctx->pp.sps_st_rps[i].s0_used_flag[j], 1);
+            }
+
+            for (j = 0; j <  dxva_ctx->pp.sps_st_rps[i].num_positive_pics; j++) {
+                mpp_put_bits(&bp, dxva_ctx->pp.sps_st_rps[i].delta_poc_s1[j], 16);
+                mpp_put_bits(&bp, dxva_ctx->pp.sps_st_rps[i].s1_used_flag[j], 1);
+
+            }
+
+            for ( j = dxva_ctx->pp.sps_st_rps[i].num_negative_pics + dxva_ctx->pp.sps_st_rps[i].num_positive_pics; j < 15; j++) {
+                mpp_put_bits(&bp, 0, 16);
+                mpp_put_bits(&bp, 0, 1);
+            }
+
+        } else {
+            mpp_put_bits(&bp, 0, 4);
+            mpp_put_bits(&bp, 0, 4);
+            for ( j = 0; j < 15; j++) {
+                mpp_put_bits(&bp, 0, 16);
+                mpp_put_bits(&bp, 0, 1);
+            }
+        }
+        mpp_put_align(&bp, 64, 0);
+        mpp_put_bits(&bp,  0, 128);
+    }
+
+#ifdef DUMP_VDPU383_DATAS
+    {
+        char *cur_fname = "rps_128bit.dat";
+        memset(dump_cur_fname_path, 0, sizeof(dump_cur_fname_path));
+        sprintf(dump_cur_fname_path, "%s/%s", dump_cur_dir, cur_fname);
+        dump_data_to_file(dump_cur_fname_path, (void *)bp.pbuf, 64 * bp.index + bp.bitpos, 128, 0);
+    }
+#endif
+
+    RK_U32 *tmp = (RK_U32 *)sw_rps_buf;
+    memcpy(rps_buf, sw_rps_buf, fifo_len * sizeof(RK_U64));
+
+    if (hal_h265d_debug & H265H_DBG_RPS) {
+        for (i = 0; i < 400 * 8 / 4; i++) {
+            mpp_log("rps[%3d] = 0x%08x\n", i, tmp[i]);
+        }
+    }
+    return 0;
+}
+
+static RK_S32 calc_mv_size(RK_S32 pic_w, RK_S32 pic_h, RK_S32 ctu_w)
+{
+    RK_S32 seg_w = 64 * 16 * 16 / ctu_w; // colmv_block_size = 16, colmv_per_bytes = 16
+    RK_S32 seg_cnt_w = MPP_ALIGN(pic_w, seg_w) / seg_w;
+    RK_S32 seg_cnt_h = MPP_ALIGN(pic_h, ctu_w) / ctu_w;
+    RK_S32 mv_size   = seg_cnt_w * seg_cnt_h * 64 * 16;
+
+    return mv_size;
+}
+
+static MPP_RET hal_h265d_vdpu383_gen_regs(void *hal,  HalTaskInfo *syn)
+{
+    RK_S32 i = 0;
+    RK_S32 log2_min_cb_size;
+    RK_S32 width, height;
+    RK_S32 stride_y, stride_uv, virstrid_y;
+    Vdpu383H265dRegSet *hw_regs;
+    RK_S32 ret = MPP_SUCCESS;
+    MppBuffer streambuf = NULL;
+    RK_S32 aglin_offset = 0;
+    RK_S32 valid_ref = -1;
+    MppBuffer framebuf = NULL;
+    HalBuf *mv_buf = NULL;
+    RK_S32 fd = -1;
+    RK_U32 mv_size = 0;
+    RK_S32 distance = INT_MAX;
+
+    (void) fd;
+    if (syn->dec.flags.parse_err ||
+        syn->dec.flags.ref_err) {
+        h265h_dbg(H265H_DBG_TASK_ERR, "%s found task error\n", __FUNCTION__);
+        return MPP_OK;
+    }
+
+    h265d_dxva2_picture_context_t *dxva_ctx = (h265d_dxva2_picture_context_t *)syn->dec.syntax.data;
+    HalH265dCtx *reg_ctx = (HalH265dCtx *)hal;
+    HalBuf *origin_buf = NULL;
+
+    void *rps_ptr = NULL;
+    if (reg_ctx ->fast_mode) {
+        for (i = 0; i < MAX_GEN_REG; i++) {
+            if (!reg_ctx->g_buf[i].use_flag) {
+                syn->dec.reg_index = i;
+
+                reg_ctx->spspps_offset = reg_ctx->offset_spspps[i];
+                reg_ctx->rps_offset = reg_ctx->offset_rps[i];
+                reg_ctx->sclst_offset = reg_ctx->offset_sclst[i];
+
+                reg_ctx->hw_regs = reg_ctx->g_buf[i].hw_regs;
+                reg_ctx->g_buf[i].use_flag = 1;
+                break;
+            }
+        }
+        if (i == MAX_GEN_REG) {
+            mpp_err("hevc rps buf all used");
+            return MPP_ERR_NOMEM;
+        }
+    }
+    rps_ptr = mpp_buffer_get_ptr(reg_ctx->bufs) + reg_ctx->rps_offset;
+    if (NULL == rps_ptr) {
+
+        mpp_err("rps_data get ptr error");
+        return MPP_ERR_NOMEM;
+    }
+
+
+    if (syn->dec.syntax.data == NULL) {
+        mpp_err("%s:%s:%d dxva is NULL", __FILE__, __FUNCTION__, __LINE__);
+        return MPP_ERR_NULL_PTR;
+    }
+
+#ifdef DUMP_VDPU383_DATAS
+    {
+        memset(dump_cur_dir, 0, sizeof(dump_cur_dir));
+        sprintf(dump_cur_dir, "hevc/Frame%04d", dump_cur_frame);
+        if (access(dump_cur_dir, 0)) {
+            if (mkdir(dump_cur_dir))
+                mpp_err_f("error: mkdir %s\n", dump_cur_dir);
+        }
+        dump_cur_frame++;
+    }
+#endif
+
+    /* output pps */
+    hw_regs = (Vdpu383H265dRegSet*)reg_ctx->hw_regs;
+    memset(hw_regs, 0, sizeof(Vdpu383H265dRegSet));
+
+    hal_h265d_v345_output_pps_packet(hal, syn->dec.syntax.data);
+
+    if (NULL == reg_ctx->hw_regs) {
+        return MPP_ERR_NULL_PTR;
+    }
+
+
+    log2_min_cb_size = dxva_ctx->pp.log2_min_luma_coding_block_size_minus3 + 3;
+    width = (dxva_ctx->pp.PicWidthInMinCbsY << log2_min_cb_size);
+    height = (dxva_ctx->pp.PicHeightInMinCbsY << log2_min_cb_size);
+    mv_size = calc_mv_size(width, height, 1 << log2_min_cb_size) * 2;
+
+    if (reg_ctx->cmv_bufs == NULL || reg_ctx->mv_size < mv_size) {
+        size_t size = mv_size;
+
+        if (reg_ctx->cmv_bufs) {
+            hal_bufs_deinit(reg_ctx->cmv_bufs);
+            reg_ctx->cmv_bufs = NULL;
+        }
+
+        hal_bufs_init(&reg_ctx->cmv_bufs);
+        if (reg_ctx->cmv_bufs == NULL) {
+            mpp_err_f("colmv bufs init fail");
+            return MPP_ERR_NULL_PTR;
+        }
+
+        reg_ctx->mv_size = mv_size;
+        reg_ctx->mv_count = mpp_buf_slot_get_count(reg_ctx->slots);
+        hal_bufs_setup(reg_ctx->cmv_bufs, reg_ctx->mv_count, 1, &size);
+    }
+
+    {
+        MppFrame mframe = NULL;
+        RK_U32 ver_virstride;
+        RK_U32 virstrid_uv;
+        MppFrameFormat fmt;
+        RK_U32 chroma_fmt_idc = dxva_ctx->pp.chroma_format_idc;
+
+        mpp_buf_slot_get_prop(reg_ctx->slots, dxva_ctx->pp.CurrPic.Index7Bits,
+                              SLOT_FRAME_PTR, &mframe);
+        /* for 8K downscale mode*/
+        if (mpp_frame_get_thumbnail_en(mframe) == MPP_FRAME_THUMBNAIL_ONLY &&
+            reg_ctx->origin_bufs == NULL) {
+            vdpu383_setup_scale_origin_bufs(reg_ctx, mframe);
+        }
+
+        fmt = mpp_frame_get_fmt(mframe);
+
+        stride_y = mpp_frame_get_hor_stride(mframe);
+        ver_virstride = mpp_frame_get_ver_stride(mframe);
+        stride_uv = stride_y;
+        virstrid_y = ver_virstride * stride_y;
+        if (chroma_fmt_idc == 3)
+            stride_uv *= 2;
+        if (chroma_fmt_idc == 3 || chroma_fmt_idc == 2) {
+            virstrid_uv = stride_uv * ver_virstride;
+        } else {
+            virstrid_uv = stride_uv * ver_virstride / 2;
+        }
+        if (MPP_FRAME_FMT_IS_FBC(fmt)) {
+            RK_U32 pixel_width = MPP_ALIGN(mpp_frame_get_width(mframe), 64);
+            RK_U32 fbd_offset;
+
+            hw_regs->ctrl_regs.reg9.fbc_e = 1;
+            hw_regs->h265d_paras.reg68_hor_virstride = pixel_width / 64;
+            fbd_offset = pixel_width * MPP_ALIGN(ver_virstride, 64) / 16;
+            hw_regs->h265d_addrs.reg193_fbc_payload_offset = fbd_offset;
+        } else if (MPP_FRAME_FMT_IS_TILE(fmt)) {
+            hw_regs->ctrl_regs.reg9.tile_e = 1;
+            if (chroma_fmt_idc == 0) { //yuv400
+                hw_regs->h265d_paras.reg68_hor_virstride = stride_y * 4 / 16;
+            } else if (chroma_fmt_idc == 2) { //yuv422
+                hw_regs->h265d_paras.reg68_hor_virstride = stride_y * 8 / 16;
+            } else if (chroma_fmt_idc == 3) { //yuv444
+                hw_regs->h265d_paras.reg68_hor_virstride = stride_y * 12 / 16;
+            } else { //yuv420
+                hw_regs->h265d_paras.reg68_hor_virstride = stride_y * 6 / 16;
+            }
+            hw_regs->h265d_paras.reg70_y_virstride = (virstrid_y + virstrid_uv) / 16;
+        } else {
+            hw_regs->ctrl_regs.reg9.fbc_e = 0;
+            hw_regs->h265d_paras.reg68_hor_virstride = stride_y >> 4;
+            hw_regs->h265d_paras.reg69_raster_uv_hor_virstride = stride_uv >> 4;
+            hw_regs->h265d_paras.reg70_y_virstride = virstrid_y >> 4;
+        }
+        hw_regs->h265d_paras.reg80_error_ref_hor_virstride = hw_regs->h265d_paras.reg68_hor_virstride;
+        hw_regs->h265d_paras.reg81_error_ref_raster_uv_hor_virstride = hw_regs->h265d_paras.reg69_raster_uv_hor_virstride;
+        hw_regs->h265d_paras.reg82_error_ref_virstride = hw_regs->h265d_paras.reg70_y_virstride;
+    }
+    mpp_buf_slot_get_prop(reg_ctx->slots, dxva_ctx->pp.CurrPic.Index7Bits,
+                          SLOT_BUFFER, &framebuf);
+
+    if (reg_ctx->origin_bufs) {
+        origin_buf = hal_bufs_get_buf(reg_ctx->origin_bufs,
+                                      dxva_ctx->pp.CurrPic.Index7Bits);
+        framebuf = origin_buf->buf[0];
+    }
+
+    hw_regs->h265d_addrs.reg168_decout_base = mpp_buffer_get_fd(framebuf); //just index need map
+    hw_regs->h265d_addrs.reg169_error_ref_base = mpp_buffer_get_fd(framebuf);
+    /*if out_base is equal to zero it means this frame may error
+    we return directly add by csy*/
+
+    if (hw_regs->h265d_addrs.reg168_decout_base == 0) {
+        return 0;
+    }
+
+    fd =  mpp_buffer_get_fd(framebuf);
+    hw_regs->h265d_addrs.reg168_decout_base = fd;
+    hw_regs->h265d_addrs.reg192_payload_st_cur_base = fd;
+    mv_buf = hal_bufs_get_buf(reg_ctx->cmv_bufs, dxva_ctx->pp.CurrPic.Index7Bits);
+
+    hw_regs->h265d_addrs.reg216_colmv_cur_base = mpp_buffer_get_fd(mv_buf->buf[0]);
+#ifdef DUMP_VDPU383_DATAS
+    {
+        char *cur_fname = "colmv_cur_frame.dat";
+        memset(dump_cur_fname_path, 0, sizeof(dump_cur_fname_path));
+        sprintf(dump_cur_fname_path, "%s/%s", dump_cur_dir, cur_fname);
+        dump_data_to_file(dump_cur_fname_path, (void *)mpp_buffer_get_ptr(mv_buf->buf[0]),
+                          mpp_buffer_get_size(mv_buf->buf[0]), 64, 0);
+    }
+#endif
+
+    mpp_buf_slot_get_prop(reg_ctx->packet_slots, syn->dec.input, SLOT_BUFFER,
+                          &streambuf);
+    if ( dxva_ctx->bitstream == NULL) {
+        dxva_ctx->bitstream = mpp_buffer_get_ptr(streambuf);
+    }
+
+#ifdef DUMP_VDPU383_DATAS
+    {
+        char *cur_fname = "stream_in_128bit.dat";
+        memset(dump_cur_fname_path, 0, sizeof(dump_cur_fname_path));
+        sprintf(dump_cur_fname_path, "%s/%s", dump_cur_dir, cur_fname);
+        dump_data_to_file(dump_cur_fname_path, (void *)mpp_buffer_get_ptr(streambuf),
+                          mpp_buffer_get_size(streambuf), 128, 0);
+    }
+#endif
+
+    hal_h265d_vdpu383_rps(syn->dec.syntax.data, rps_ptr, reg_ctx->sw_rps_buf, reg_ctx->fast_mode);
+
+    MppDevRegOffsetCfg trans_cfg;
+
+    /* pps */
+    hw_regs->common_addr.reg131_gbl_base = reg_ctx->bufs_fd;
+    hw_regs->h265d_paras.reg67_global_len = 0xc; //22 * 8;
+
+    trans_cfg.reg_idx = 131;
+    trans_cfg.offset = reg_ctx->spspps_offset;
+    mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
+
+    /* rps */
+    hw_regs->common_addr.reg129_rps_base = reg_ctx->bufs_fd;
+    trans_cfg.reg_idx = 129;
+    trans_cfg.offset = reg_ctx->rps_offset;
+    mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_OFFSET, &trans_cfg);
+
+    hw_regs->common_addr.reg128_strm_base = mpp_buffer_get_fd(streambuf);
+    hw_regs->h265d_paras.reg66_stream_len = ((dxva_ctx->bitstream_size + 15) & (~15)) + 64;
+    aglin_offset =  hw_regs->h265d_paras.reg66_stream_len - dxva_ctx->bitstream_size;
+    if (aglin_offset > 0)
+        memset((void *)(dxva_ctx->bitstream + dxva_ctx->bitstream_size), 0, aglin_offset);
+
+    /* common setting */
+    hw_regs->ctrl_regs.reg8_dec_mode = 0; // hevc
+    hw_regs->ctrl_regs.reg9.buf_empty_en = 0;
+
+    hw_regs->ctrl_regs.reg10.strmd_auto_gating_e      = 1;
+    hw_regs->ctrl_regs.reg10.inter_auto_gating_e      = 1;
+    hw_regs->ctrl_regs.reg10.intra_auto_gating_e      = 1;
+    hw_regs->ctrl_regs.reg10.transd_auto_gating_e     = 1;
+    hw_regs->ctrl_regs.reg10.recon_auto_gating_e      = 1;
+    hw_regs->ctrl_regs.reg10.filterd_auto_gating_e    = 1;
+    hw_regs->ctrl_regs.reg10.bus_auto_gating_e        = 1;
+    hw_regs->ctrl_regs.reg10.ctrl_auto_gating_e       = 1;
+    hw_regs->ctrl_regs.reg10.rcb_auto_gating_e        = 1;
+    hw_regs->ctrl_regs.reg10.err_prc_auto_gating_e    = 1;
+
+    // hw_regs->ctrl_regs.reg11.dec_timeout_dis = 1;
+
+    hw_regs->ctrl_regs.reg16.error_proc_disable = 1;
+    hw_regs->ctrl_regs.reg16.error_spread_disable = 0;
+    hw_regs->ctrl_regs.reg16.roi_error_ctu_cal_en = 0;
+
+    hw_regs->ctrl_regs.reg20_cabac_error_en_lowbits = 0xffffffff;
+    hw_regs->ctrl_regs.reg21_cabac_error_en_highbits = 0x3ff3ffff;
+
+    hw_regs->ctrl_regs.reg13_core_timeout_threshold = 0xffff;
+
+
+    valid_ref = hw_regs->h265d_addrs.reg168_decout_base;
+    reg_ctx->error_index[syn->dec.reg_index] = dxva_ctx->pp.CurrPic.Index7Bits;
+
+    hw_regs->h265d_addrs.reg169_error_ref_base = valid_ref;
+    for (i = 0; i < (RK_S32)MPP_ARRAY_ELEMS(dxva_ctx->pp.RefPicList); i++) {
+        if (dxva_ctx->pp.RefPicList[i].bPicEntry != 0xff &&
+            dxva_ctx->pp.RefPicList[i].bPicEntry != 0x7f) {
+
+            MppFrame mframe = NULL;
+            mpp_buf_slot_get_prop(reg_ctx->slots,
+                                  dxva_ctx->pp.RefPicList[i].Index7Bits,
+                                  SLOT_BUFFER, &framebuf);
+            mpp_buf_slot_get_prop(reg_ctx->slots, dxva_ctx->pp.RefPicList[i].Index7Bits,
+                                  SLOT_FRAME_PTR, &mframe);
+            if (mpp_frame_get_thumbnail_en(mframe) == MPP_FRAME_THUMBNAIL_ONLY) {
+                origin_buf = hal_bufs_get_buf(reg_ctx->origin_bufs,
+                                              dxva_ctx->pp.RefPicList[i].Index7Bits);
+                framebuf = origin_buf->buf[0];
+            }
+            if (framebuf != NULL) {
+                hw_regs->h265d_addrs.reg170_185_ref_base[i] = mpp_buffer_get_fd(framebuf);
+                hw_regs->h265d_addrs.reg195_210_payload_st_ref_base[i] = mpp_buffer_get_fd(framebuf);
+                valid_ref = hw_regs->h265d_addrs.reg170_185_ref_base[i];
+                if ((pocdistance(dxva_ctx->pp.PicOrderCntValList[i], dxva_ctx->pp.current_poc) < distance)
+                    && (!mpp_frame_get_errinfo(mframe))) {
+
+                    distance = pocdistance(dxva_ctx->pp.PicOrderCntValList[i], dxva_ctx->pp.current_poc);
+                    hw_regs->h265d_addrs.reg169_error_ref_base = hw_regs->h265d_addrs.reg170_185_ref_base[i];
+                    reg_ctx->error_index[syn->dec.reg_index] = dxva_ctx->pp.RefPicList[i].Index7Bits;
+                    hw_regs->ctrl_regs.reg16.error_proc_disable = 1;
+                }
+            } else {
+                hw_regs->h265d_addrs.reg170_185_ref_base[i] = valid_ref;
+                hw_regs->h265d_addrs.reg195_210_payload_st_ref_base[i] = valid_ref;
+            }
+
+            mv_buf = hal_bufs_get_buf(reg_ctx->cmv_bufs, dxva_ctx->pp.RefPicList[i].Index7Bits);
+            hw_regs->h265d_addrs.reg217_232_colmv_ref_base[i] = mpp_buffer_get_fd(mv_buf->buf[0]);
+        }
+    }
+
+    if ((reg_ctx->error_index[syn->dec.reg_index] == dxva_ctx->pp.CurrPic.Index7Bits) &&
+        !dxva_ctx->pp.IntraPicFlag && !reg_ctx->cfg->base.disable_error) {
+        h265h_dbg(H265H_DBG_TASK_ERR, "current frm may be err, should skip process");
+        syn->dec.flags.ref_err = 1;
+        return MPP_OK;
+    }
+
+    for (i = 0; i < (RK_S32)MPP_ARRAY_ELEMS(dxva_ctx->pp.RefPicList); i++) {
+
+        if (dxva_ctx->pp.RefPicList[i].bPicEntry != 0xff &&
+            dxva_ctx->pp.RefPicList[i].bPicEntry != 0x7f) {
+            MppFrame mframe = NULL;
+
+            mpp_buf_slot_get_prop(reg_ctx->slots,
+                                  dxva_ctx->pp.RefPicList[i].Index7Bits,
+                                  SLOT_BUFFER, &framebuf);
+
+            mpp_buf_slot_get_prop(reg_ctx->slots, dxva_ctx->pp.RefPicList[i].Index7Bits,
+                                  SLOT_FRAME_PTR, &mframe);
+
+            if (framebuf == NULL || mpp_frame_get_errinfo(mframe)) {
+                mv_buf = hal_bufs_get_buf(reg_ctx->cmv_bufs, reg_ctx->error_index[syn->dec.reg_index]);
+                hw_regs->h265d_addrs.reg170_185_ref_base[i] = hw_regs->h265d_addrs.reg169_error_ref_base;
+                hw_regs->h265d_addrs.reg195_210_payload_st_ref_base[i] = hw_regs->h265d_addrs.reg169_error_ref_base;
+                hw_regs->h265d_addrs.reg217_232_colmv_ref_base[i] = mpp_buffer_get_fd(mv_buf->buf[0]);
+            }
+        } else {
+            mv_buf = hal_bufs_get_buf(reg_ctx->cmv_bufs, reg_ctx->error_index[syn->dec.reg_index]);
+            hw_regs->h265d_addrs.reg170_185_ref_base[i] = hw_regs->h265d_addrs.reg169_error_ref_base;
+            hw_regs->h265d_addrs.reg195_210_payload_st_ref_base[i] = hw_regs->h265d_addrs.reg169_error_ref_base;
+            hw_regs->h265d_addrs.reg217_232_colmv_ref_base[i] = mpp_buffer_get_fd(mv_buf->buf[0]);
+        }
+    }
+
+    hal_h265d_rcb_info_update(hal, dxva_ctx, hw_regs, width, height);
+    vdpu383_setup_rcb(&hw_regs->common_addr, reg_ctx->dev, reg_ctx->fast_mode ?
+                      reg_ctx->rcb_buf[syn->dec.reg_index] : reg_ctx->rcb_buf[0],
+                      (Vdpu383RcbInfo *)reg_ctx->rcb_info);
+    vdpu383_setup_statistic(&hw_regs->ctrl_regs);
+    mpp_buffer_sync_end(reg_ctx->bufs);
+
+    {
+        //scale down config
+        MppFrame mframe = NULL;
+        MppBuffer mbuffer = NULL;
+        MppFrameThumbnailMode thumbnail_mode;
+
+        mpp_buf_slot_get_prop(reg_ctx->slots, dxva_ctx->pp.CurrPic.Index7Bits,
+                              SLOT_BUFFER, &mbuffer);
+        mpp_buf_slot_get_prop(reg_ctx->slots, dxva_ctx->pp.CurrPic.Index7Bits,
+                              SLOT_FRAME_PTR, &mframe);
+        thumbnail_mode = mpp_frame_get_thumbnail_en(mframe);
+        switch (thumbnail_mode) {
+        case MPP_FRAME_THUMBNAIL_ONLY:
+            hw_regs->common_addr.reg133_scale_down_base = mpp_buffer_get_fd(mbuffer);
+            origin_buf = hal_bufs_get_buf(reg_ctx->origin_bufs, dxva_ctx->pp.CurrPic.Index7Bits);
+            fd = mpp_buffer_get_fd(origin_buf->buf[0]);
+            hw_regs->h265d_addrs.reg168_decout_base = fd;
+            hw_regs->h265d_addrs.reg192_payload_st_cur_base = fd;
+            hw_regs->h265d_addrs.reg169_error_ref_base = fd;
+            vdpu383_setup_down_scale(mframe, reg_ctx->dev, &hw_regs->ctrl_regs, (void*)&hw_regs->h265d_paras);
+            break;
+        case MPP_FRAME_THUMBNAIL_MIXED:
+            hw_regs->common_addr.reg133_scale_down_base = mpp_buffer_get_fd(mbuffer);
+            vdpu383_setup_down_scale(mframe, reg_ctx->dev, &hw_regs->ctrl_regs, (void*)&hw_regs->h265d_paras);
+            break;
+        case MPP_FRAME_THUMBNAIL_NONE:
+        default:
+            hw_regs->ctrl_regs.reg9.scale_down_en = 0;
+            break;
+        }
+    }
+
+    return ret;
+}
+
+static MPP_RET hal_h265d_vdpu383_start(void *hal, HalTaskInfo *task)
+{
+    MPP_RET ret = MPP_OK;
+    RK_U8* p = NULL;
+    Vdpu383H265dRegSet *hw_regs = NULL;
+    HalH265dCtx *reg_ctx = (HalH265dCtx *)hal;
+    RK_S32 index =  task->dec.reg_index;
+
+    RK_U32 i;
+
+    if (task->dec.flags.parse_err ||
+        task->dec.flags.ref_err) {
+        h265h_dbg(H265H_DBG_TASK_ERR, "%s found task error\n", __FUNCTION__);
+        return MPP_OK;
+    }
+
+    if (reg_ctx->fast_mode) {
+        p = (RK_U8*)reg_ctx->g_buf[index].hw_regs;
+        hw_regs = ( Vdpu383H265dRegSet *)reg_ctx->g_buf[index].hw_regs;
+    } else {
+        p = (RK_U8*)reg_ctx->hw_regs;
+        hw_regs = ( Vdpu383H265dRegSet *)reg_ctx->hw_regs;
+    }
+
+    if (hw_regs == NULL) {
+        mpp_err("hal_h265d_start hw_regs is NULL");
+        return MPP_ERR_NULL_PTR;
+    }
+    for (i = 0; i < 68; i++) {
+        h265h_dbg(H265H_DBG_REG, "RK_HEVC_DEC: regs[%02d]=%08X\n",
+                  i, *((RK_U32*)p));
+        //mpp_log("RK_HEVC_DEC: regs[%02d]=%08X\n", i, *((RK_U32*)p));
+        p += 4;
+    }
+
+    do {
+        MppDevRegWrCfg wr_cfg;
+        MppDevRegRdCfg rd_cfg;
+
+        wr_cfg.reg = &hw_regs->ctrl_regs;
+        wr_cfg.size = sizeof(hw_regs->ctrl_regs);
+        wr_cfg.offset = OFFSET_CTRL_REGS;
+        ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg);
+        if (ret) {
+            mpp_err_f("set register read failed %d\n", ret);
+            break;
+        }
+
+        wr_cfg.reg = &hw_regs->common_addr;
+        wr_cfg.size = sizeof(hw_regs->common_addr);
+        wr_cfg.offset = OFFSET_COMMON_ADDR_REGS;
+        ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg);
+        if (ret) {
+            mpp_err_f("set register write failed %d\n", ret);
+            break;
+        }
+
+        wr_cfg.reg = &hw_regs->h265d_paras;
+        wr_cfg.size = sizeof(hw_regs->h265d_paras);
+        wr_cfg.offset = OFFSET_CODEC_PARAS_REGS;
+        ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg);
+        if (ret) {
+            mpp_err_f("set register write failed %d\n", ret);
+            break;
+        }
+
+        wr_cfg.reg = &hw_regs->h265d_addrs;
+        wr_cfg.size = sizeof(hw_regs->h265d_addrs);
+        wr_cfg.offset = OFFSET_CODEC_ADDR_REGS;
+        ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_WR, &wr_cfg);
+        if (ret) {
+            mpp_err_f("set register write failed %d\n", ret);
+            break;
+        }
+
+        rd_cfg.reg = &hw_regs->ctrl_regs.reg15;
+        rd_cfg.size = sizeof(hw_regs->ctrl_regs.reg15);
+        rd_cfg.offset = OFFSET_INTERRUPT_REGS;
+        ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_REG_RD, &rd_cfg);
+        if (ret) {
+            mpp_err_f("set register read failed %d\n", ret);
+            break;
+        }
+
+        /* rcb info for sram */
+        vdpu383_set_rcbinfo(reg_ctx->dev, (Vdpu383RcbInfo*)reg_ctx->rcb_info);
+
+        ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_CMD_SEND, NULL);
+        if (ret) {
+            mpp_err_f("send cmd failed %d\n", ret);
+            break;
+        }
+    } while (0);
+
+    return ret;
+}
+
+
+static MPP_RET hal_h265d_vdpu383_wait(void *hal, HalTaskInfo *task)
+{
+    MPP_RET ret = MPP_OK;
+    RK_S32 index =  task->dec.reg_index;
+    HalH265dCtx *reg_ctx = (HalH265dCtx *)hal;
+    RK_U8* p = NULL;
+    Vdpu383H265dRegSet *hw_regs = NULL;
+    RK_S32 i;
+
+    if (reg_ctx->fast_mode) {
+        hw_regs = ( Vdpu383H265dRegSet *)reg_ctx->g_buf[index].hw_regs;
+    } else {
+        hw_regs = ( Vdpu383H265dRegSet *)reg_ctx->hw_regs;
+    }
+
+    p = (RK_U8*)hw_regs;
+
+    if (task->dec.flags.parse_err ||
+        task->dec.flags.ref_err) {
+        h265h_dbg(H265H_DBG_TASK_ERR, "%s found task error\n", __FUNCTION__);
+        goto ERR_PROC;
+    }
+
+    ret = mpp_dev_ioctl(reg_ctx->dev, MPP_DEV_CMD_POLL, NULL);
+    if (ret)
+        mpp_err_f("poll cmd failed %d\n", ret);
+
+ERR_PROC:
+    if (task->dec.flags.parse_err ||
+        task->dec.flags.ref_err ||
+        (!hw_regs->ctrl_regs.reg15.rkvdec_frame_rdy_sta) ||
+        hw_regs->ctrl_regs.reg15.rkvdec_strm_error_sta ||
+        hw_regs->ctrl_regs.reg15.rkvdec_core_timeout_sta ||
+        hw_regs->ctrl_regs.reg15.rkvdec_ip_timeout_sta ||
+        hw_regs->ctrl_regs.reg15.rkvdec_bus_error_sta ||
+        hw_regs->ctrl_regs.reg15.rkvdec_buffer_empty_sta ||
+        hw_regs->ctrl_regs.reg15.rkvdec_colmv_ref_error_sta) {
+        if (!reg_ctx->fast_mode) {
+            if (reg_ctx->dec_cb)
+                mpp_callback(reg_ctx->dec_cb, &task->dec);
+        } else {
+            MppFrame mframe = NULL;
+            mpp_buf_slot_get_prop(reg_ctx->slots, task->dec.output,
+                                  SLOT_FRAME_PTR, &mframe);
+            if (mframe) {
+                reg_ctx->fast_mode_err_found = 1;
+                mpp_frame_set_errinfo(mframe, 1);
+            }
+        }
+    } else {
+        if (reg_ctx->fast_mode && reg_ctx->fast_mode_err_found) {
+            for (i = 0; i < (RK_S32)MPP_ARRAY_ELEMS(task->dec.refer); i++) {
+                if (task->dec.refer[i] >= 0) {
+                    MppFrame frame_ref = NULL;
+
+                    mpp_buf_slot_get_prop(reg_ctx->slots, task->dec.refer[i],
+                                          SLOT_FRAME_PTR, &frame_ref);
+                    h265h_dbg(H265H_DBG_FAST_ERR, "refer[%d] %d frame %p\n",
+                              i, task->dec.refer[i], frame_ref);
+                    if (frame_ref && mpp_frame_get_errinfo(frame_ref)) {
+                        MppFrame frame_out = NULL;
+                        mpp_buf_slot_get_prop(reg_ctx->slots, task->dec.output,
+                                              SLOT_FRAME_PTR, &frame_out);
+                        mpp_frame_set_errinfo(frame_out, 1);
+                        break;
+                    }
+                }
+            }
+        }
+    }
+
+    for (i = 0; i < 68; i++) {
+        if (i == 1) {
+            h265h_dbg(H265H_DBG_REG, "RK_HEVC_DEC: regs[%02d]=%08X\n",
+                      i, *((RK_U32*)p));
+        }
+
+        if (i == 45) {
+            h265h_dbg(H265H_DBG_REG, "RK_HEVC_DEC: regs[%02d]=%08X\n",
+                      i, *((RK_U32*)p));
+        }
+        p += 4;
+    }
+
+    if (reg_ctx->fast_mode) {
+        reg_ctx->g_buf[index].use_flag = 0;
+    }
+
+    return ret;
+}
+
+static MPP_RET hal_h265d_vdpu383_reset(void *hal)
+{
+    MPP_RET ret = MPP_OK;
+    HalH265dCtx *p_hal = (HalH265dCtx *)hal;
+    p_hal->fast_mode_err_found = 0;
+    (void)hal;
+    return ret;
+}
+
+static MPP_RET hal_h265d_vdpu383_flush(void *hal)
+{
+    MPP_RET ret = MPP_OK;
+
+    (void)hal;
+    return ret;
+}
+
+static MPP_RET hal_h265d_vdpu383_control(void *hal, MpiCmd cmd_type, void *param)
+{
+    MPP_RET ret = MPP_OK;
+    HalH265dCtx *p_hal = (HalH265dCtx *)hal;
+
+    (void)hal;
+    (void)param;
+    switch ((MpiCmd)cmd_type) {
+    case MPP_DEC_SET_FRAME_INFO: {
+        MppFrame frame = (MppFrame)param;
+        MppFrameFormat fmt = mpp_frame_get_fmt(frame);
+        RK_U32 imgwidth = mpp_frame_get_width((MppFrame)param);
+        RK_U32 imgheight = mpp_frame_get_height((MppFrame)param);
+
+        if (fmt == MPP_FMT_YUV422SP) {
+            mpp_slots_set_prop(p_hal->slots, SLOTS_LEN_ALIGN, rkv_len_align_422);
+        } else if (fmt == MPP_FMT_YUV444SP) {
+            mpp_slots_set_prop(p_hal->slots, SLOTS_LEN_ALIGN, rkv_len_align_444);
+        }
+        if (MPP_FRAME_FMT_IS_FBC(fmt)) {
+            vdpu383_afbc_align_calc(p_hal->slots, frame, 16);
+        } else if (imgwidth > 1920 || imgheight > 1088) {
+            mpp_slots_set_prop(p_hal->slots, SLOTS_HOR_ALIGN, mpp_align_128_odd_plus_64);
+        }
+        break;
+    }
+    case MPP_DEC_GET_THUMBNAIL_FRAME_INFO: {
+        vdpu383_update_thumbnail_frame_info((MppFrame)param);
+    } break;
+    case MPP_DEC_SET_OUTPUT_FORMAT: {
+    } break;
+    default: {
+    } break;
+    }
+    return  ret;
+}
+
+const MppHalApi hal_h265d_vdpu383 = {
+    .name = "h265d_vdpu383",
+    .type = MPP_CTX_DEC,
+    .coding = MPP_VIDEO_CodingHEVC,
+    .ctx_size = sizeof(HalH265dCtx),
+    .flag = 0,
+    .init = hal_h265d_vdpu383_init,
+    .deinit = hal_h265d_vdpu383_deinit,
+    .reg_gen = hal_h265d_vdpu383_gen_regs,
+    .start = hal_h265d_vdpu383_start,
+    .wait = hal_h265d_vdpu383_wait,
+    .reset = hal_h265d_vdpu383_reset,
+    .flush = hal_h265d_vdpu383_flush,
+    .control = hal_h265d_vdpu383_control,
+};
diff --git a/mpp/hal/rkdec/h265d/hal_h265d_vdpu383.h b/mpp/hal/rkdec/h265d/hal_h265d_vdpu383.h
new file mode 100644
index 000000000..910729a1a
--- /dev/null
+++ b/mpp/hal/rkdec/h265d/hal_h265d_vdpu383.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: Apache-2.0 OR MIT */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef __HAL_H265D_VDPU383_H__
+#define __HAL_H265D_VDPU383_H__
+
+#include "mpp_hal.h"
+#include "vdpu383.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern const MppHalApi hal_h265d_vdpu383;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HAL_H265D_VDPU383_H__ */
diff --git a/mpp/hal/rkdec/inc/vdpu34x_com.h b/mpp/hal/rkdec/inc/vdpu34x_com.h
index f8768de8c..38fbc9679 100644
--- a/mpp/hal/rkdec/inc/vdpu34x_com.h
+++ b/mpp/hal/rkdec/inc/vdpu34x_com.h
@@ -501,6 +501,8 @@ void vdpu34x_setup_rcb(Vdpu34xRegCommonAddr *reg, MppDev dev, MppBuffer buf, Vdp
 void vdpu34x_setup_statistic(Vdpu34xRegCommon *com, Vdpu34xRegStatistic *sta);
 void vdpu34x_afbc_align_calc(MppBufSlots slots, MppFrame frame, RK_U32 expand);
 RK_S32 vdpu34x_set_rcbinfo(MppDev dev, Vdpu34xRcbInfo *rcb_info);
+RK_U32 vdpu34x_get_colmv_size(RK_U32 width, RK_U32 height, RK_U32 ctu_size,
+                              RK_U32 colmv_bytes, RK_U32 colmv_size, RK_U32 compress);
 
 #ifdef  __cplusplus
 }
diff --git a/mpp/hal/rkdec/inc/vdpu382_com.h b/mpp/hal/rkdec/inc/vdpu382_com.h
index 017d6c3b6..732a5daf5 100644
--- a/mpp/hal/rkdec/inc/vdpu382_com.h
+++ b/mpp/hal/rkdec/inc/vdpu382_com.h
@@ -568,6 +568,8 @@ RK_S32 vdpu382_set_rcbinfo(MppDev dev, Vdpu382RcbInfo *rcb_info);
 void vdpu382_setup_statistic(Vdpu382RegCommon *com, Vdpu382RegStatistic *sta);
 void vdpu382_afbc_align_calc(MppBufSlots slots, MppFrame frame, RK_U32 expand);
 void vdpu382_setup_down_scale(MppFrame frame, MppDev dev, Vdpu382RegCommon *com);
+RK_U32 vdpu382_get_colmv_size(RK_U32 width, RK_U32 height, RK_U32 ctu_size,
+                              RK_U32 colmv_bytes, RK_U32 colmv_size, RK_U32 compress);
 
 #ifdef  __cplusplus
 }
diff --git a/mpp/hal/rkdec/inc/vdpu383.h b/mpp/hal/rkdec/inc/vdpu383.h
new file mode 100644
index 000000000..3b7f6c15e
--- /dev/null
+++ b/mpp/hal/rkdec/inc/vdpu383.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: Apache-2.0 OR MIT */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef __VDPU383_H__
+#define __VDPU383_H__
+
+#define HWID_VDPU383                (0x38321746)
+
+#endif /* __VDPU383_H__ */
diff --git a/mpp/hal/rkdec/inc/vdpu383_avs2d.h b/mpp/hal/rkdec/inc/vdpu383_avs2d.h
new file mode 100644
index 000000000..459bef2b7
--- /dev/null
+++ b/mpp/hal/rkdec/inc/vdpu383_avs2d.h
@@ -0,0 +1,174 @@
+/* SPDX-License-Identifier: Apache-2.0 OR MIT */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef __VDPU383_AVS2D_H__
+#define __VDPU383_AVS2D_H__
+
+#include "vdpu383_com.h"
+
+#define AVS2D_REGISTERS     (278)
+
+typedef struct Vdpu383RegAvs2dParas_t {
+    /* SWREG64_H26X_PARA */
+    RK_U32 reg64_unused_bits;
+
+    /* SWREG65_STREAM_PARAM_SET */
+    RK_U32 reg65_strm_start_bit;
+
+    /* SWREG66_STREAM_LEN */
+    RK_U32 reg66_stream_len;
+
+    /* SWREG67_GLOBAL_LEN */
+    RK_U32 reg67_global_len;
+
+    /* SWREG68_HOR_STRIDE */
+    RK_U32 reg68_hor_virstride;
+
+    /* SWREG69_RASTER_UV_HOR_STRIDE */
+    RK_U32 reg69_raster_uv_hor_virstride;
+
+    /* SWREG70_Y_STRIDE */
+    RK_U32 reg70_y_virstride;
+
+    /* SWREG71_SCL_Y_HOR_VIRSTRIDE */
+    RK_U32 reg71_scl_ref_hor_virstride;
+
+    /* SWREG72_SCL_UV_HOR_VIRSTRIDE */
+    RK_U32 reg72_scl_ref_raster_uv_hor_virstride;
+
+    /* SWREG73_SCL_Y_VIRSTRIDE */
+    RK_U32 reg73_scl_ref_virstride;
+
+    /* SWREG74_FGS_Y_HOR_VIRSTRIDE */
+    RK_U32 reg74_fgs_ref_hor_virstride;
+
+    RK_U32 reserve_reg75_79[5];
+
+    /* SWREG80_ERROR_REF_Y_HOR_VIRSTRIDE */
+    RK_U32 reg80_error_ref_hor_virstride;
+
+    /* SWREG81_ERROR_REF_UV_HOR_VIRSTRIDE */
+    RK_U32 reg81_error_ref_raster_uv_hor_virstride;
+
+    /* SWREG82_ERROR_REF_Y_VIRSTRIDE */
+    RK_U32 reg82_error_ref_virstride;
+
+    /* SWREG83_REF0_Y_HOR_VIRSTRIDE */
+    RK_U32 reg83_ref0_hor_virstride;
+
+    /* SWREG84_REF0_UV_HOR_VIRSTRIDE */
+    RK_U32 reg84_ref0_raster_uv_hor_virstride;
+
+    /* SWREG85_REF0_Y_VIRSTRIDE */
+    RK_U32 reg85_ref0_virstride;
+
+    /* SWREG86_REF1_Y_HOR_VIRSTRIDE */
+    RK_U32 reg86_ref1_hor_virstride;
+
+    /* SWREG87_REF1_UV_HOR_VIRSTRIDE */
+    RK_U32 reg87_ref1_raster_uv_hor_virstride;
+
+    /* SWREG88_REF1_Y_VIRSTRIDE */
+    RK_U32 reg88_ref1_virstride;
+
+    /* SWREG89_REF2_Y_HOR_VIRSTRIDE */
+    RK_U32 reg89_ref2_hor_virstride;
+
+    /* SWREG90_REF2_UV_HOR_VIRSTRIDE */
+    RK_U32 reg90_ref2_raster_uv_hor_virstride;
+
+    /* SWREG91_REF2_Y_VIRSTRIDE */
+    RK_U32 reg91_ref2_virstride;
+
+    /* SWREG92_REF3_Y_HOR_VIRSTRIDE */
+    RK_U32 reg92_ref3_hor_virstride;
+
+    /* SWREG93_REF3_UV_HOR_VIRSTRIDE */
+    RK_U32 reg93_ref3_raster_uv_hor_virstride;
+
+    /* SWREG94_REF3_Y_VIRSTRIDE */
+    RK_U32 reg94_ref3_virstride;
+
+    /* SWREG95_REF4_Y_HOR_VIRSTRIDE */
+    RK_U32 reg95_ref4_hor_virstride;
+
+    /* SWREG96_REF4_UV_HOR_VIRSTRIDE */
+    RK_U32 reg96_ref4_raster_uv_hor_virstride;
+
+    /* SWREG97_REF4_Y_VIRSTRIDE */
+    RK_U32 reg97_ref4_virstride;
+
+    /* SWREG98_REF5_Y_HOR_VIRSTRIDE */
+    RK_U32 reg98_ref5_hor_virstride;
+
+    /* SWREG99_REF5_UV_HOR_VIRSTRIDE */
+    RK_U32 reg99_ref5_raster_uv_hor_virstride;
+
+    /* SWREG100_REF5_Y_VIRSTRIDE */
+    RK_U32 reg100_ref5_virstride;
+
+    /* SWREG101_REF6_Y_HOR_VIRSTRIDE */
+    RK_U32 reg101_ref6_hor_virstride;
+
+    /* SWREG102_REF6_UV_HOR_VIRSTRIDE */
+    RK_U32 reg102_ref6_raster_uv_hor_virstride;
+
+    /* SWREG103_REF6_Y_VIRSTRIDE */
+    RK_U32 reg103_ref6_virstride;
+
+    /* SWREG104_REF7_Y_HOR_VIRSTRIDE */
+    RK_U32 reg104_ref7_hor_virstride;
+
+    /* SWREG105_REF7_UV_HOR_VIRSTRIDE */
+    RK_U32 reg105_ref7_raster_uv_hor_virstride;
+
+    /* SWREG106_REF7_Y_VIRSTRIDE */
+    RK_U32 reg106_ref7_virstride;
+
+} Vdpu383RegAvs2dParas;
+
+typedef struct Vdpu383RegAvs2dAddr_t {
+    /* SWREG168_DECOUT_BASE */
+    RK_U32 reg168_decout_base;
+
+    /* SWREG169_ERROR_REF_BASE */
+    RK_U32 reg169_error_ref_base;
+
+    /* SWREG170_185_REF0_BASE */
+    RK_U32 reg170_185_ref_base[16];
+
+    RK_U32 reserve_reg186_191[6];
+
+    /* SWREG192_PAYLOAD_ST_CUR_BASE */
+    RK_U32 reg192_payload_st_cur_base;
+
+    /* SWREG193_FBC_PAYLOAD_OFFSET */
+    RK_U32 reg193_fbc_payload_offset;
+
+    /* SWREG194_PAYLOAD_ST_ERROR_REF_BASE */
+    RK_U32 reg194_payload_st_error_ref_base;
+
+    /* SWREG195_210_PAYLOAD_ST_REF0_BASE */
+    RK_U32 reg195_210_payload_st_ref_base[16];
+
+    RK_U32 reserve_reg211_215[5];
+
+    /* SWREG216_COLMV_CUR_BASE */
+    RK_U32 reg216_colmv_cur_base;
+
+    /* SWREG217_232_COLMV_REF0_BASE */
+    RK_U32 reg217_232_colmv_ref_base[16];
+
+} Vdpu383RegAvs2dAddr;
+
+typedef struct Vdpu383Avs2dRegSet_t {
+    Vdpu383RegVersion       reg_version;        /* 0 */
+    Vdpu383CtrlReg          ctrl_regs;          /* 8-30 */
+    Vdpu383RegCommonAddr    common_addr;        /* 128-134, 140-161 */
+    Vdpu383RegAvs2dParas    avs2d_paras;        /* 64-74, 80-106 */
+    Vdpu383RegAvs2dAddr     avs2d_addrs;        /* 168-185, 192-210, 216-232 */
+} Vdpu383Avs2dRegSet;
+
+#endif /* __VDPU34X_H264D_H__ */
diff --git a/mpp/hal/rkdec/inc/vdpu383_com.h b/mpp/hal/rkdec/inc/vdpu383_com.h
new file mode 100644
index 000000000..b9754d96b
--- /dev/null
+++ b/mpp/hal/rkdec/inc/vdpu383_com.h
@@ -0,0 +1,668 @@
+/* SPDX-License-Identifier: Apache-2.0 OR MIT */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef __VDPU383_COM_H__
+#define __VDPU383_COM_H__
+
+#include "mpp_device.h"
+#include "mpp_buf_slot.h"
+
+#define OFFSET_CTRL_REGS            (8 * sizeof(RK_U32))
+#define OFFSET_COMMON_ADDR_REGS     (128 * sizeof(RK_U32))
+#define OFFSET_COM_NEW_REGS         (320 * sizeof(RK_U32))
+#define OFFSET_CODEC_PARAS_REGS     (64 * sizeof(RK_U32))
+#define OFFSET_CODEC_ADDR_REGS      (168 * sizeof(RK_U32))
+#define OFFSET_INTERRUPT_REGS       (15 * sizeof(RK_U32))
+
+#define RCB_ALLINE_SIZE             (64)
+
+#define MPP_RCB_BYTES(bits)  MPP_ALIGN((bits + 7) / 8, RCB_ALLINE_SIZE)
+
+// #define DUMP_VDPU383_DATAS
+
+typedef enum Vdpu383RcbType_e {
+    RCB_STRMD_ROW,
+    RCB_STRMD_TILE_ROW,
+    RCB_INTER_ROW,
+    RCB_INTER_TILE_ROW,
+    RCB_INTRA_ROW,
+    RCB_INTRA_TILE_ROW,
+    RCB_FILTERD_ROW,
+    RCB_FILTERD_PROTECT_ROW,
+    RCB_FILTERD_TILE_ROW,
+    RCB_FILTERD_TILE_COL,
+    RCB_FILTERD_AV1_UP_TILE_COL,
+
+    RCB_BUF_COUNT,
+} Vdpu383RcbType;
+
+typedef enum Vdpu383_RCB_SET_MODE_E {
+    RCB_SET_BY_SIZE_SORT_MODE,
+    RCB_SET_BY_PRIORITY_MODE,
+} Vdpu383RcbSetMode_e;
+
+typedef struct Vdpu383RegVersion_t {
+    struct SWREG0_ID {
+        RK_U32 minor_ver                      : 8;
+        RK_U32 major_ver                      : 8;
+        RK_U32 prod_num                       : 16;
+    } reg0;
+
+} Vdpu383RegVersion;
+
+typedef struct Vdpu383CtrlReg_t {
+    /* SWREG8_DEC_MODE */
+    RK_U32 reg8_dec_mode;
+
+    struct SWREG9_IMPORTANT_EN {
+        RK_U32 fbc_e                          : 1;
+        RK_U32 tile_e                         : 1;
+        RK_U32 reserve0                       : 2;
+        RK_U32 buf_empty_en                   : 1;
+        RK_U32 scale_down_en                  : 1;
+        RK_U32 reserve1                       : 1;
+        RK_U32 pix_range_det_e                : 1;
+        RK_U32 av1_fgs_en                     : 1;
+        RK_U32 reserve2                       : 7;
+        RK_U32 line_irq_en                    : 1;
+        RK_U32 out_cbcr_swap                  : 1;
+        RK_U32 fbc_force_uncompress           : 1;
+        RK_U32 fbc_sparse_mode                : 1;
+        RK_U32 reserve3                       : 12;
+    } reg9;
+
+    struct SWREG10_BLOCK_GATING_EN {
+        RK_U32 strmd_auto_gating_e            : 1;
+        RK_U32 inter_auto_gating_e            : 1;
+        RK_U32 intra_auto_gating_e            : 1;
+        RK_U32 transd_auto_gating_e           : 1;
+        RK_U32 recon_auto_gating_e            : 1;
+        RK_U32 filterd_auto_gating_e          : 1;
+        RK_U32 bus_auto_gating_e              : 1;
+        RK_U32 ctrl_auto_gating_e             : 1;
+        RK_U32 rcb_auto_gating_e              : 1;
+        RK_U32 err_prc_auto_gating_e          : 1;
+        RK_U32 reserve0                       : 22;
+    } reg10;
+
+    struct SWREG11_CFG_PARA {
+        RK_U32 reserve0                       : 9;
+        RK_U32 dec_timeout_dis                : 1;
+        RK_U32 reserve1                       : 22;
+    } reg11;
+
+    struct SWREG12_CACHE_HASH_MASK {
+        RK_U32 reserve0                       : 7;
+        RK_U32 cache_hash_mask                : 25;
+    } reg12;
+
+    /* SWREG13_CORE_TIMEOUT_THRESHOLD */
+    RK_U32 reg13_core_timeout_threshold;
+
+    struct SWREG14_LINE_IRQ_CTRL {
+        RK_U32 dec_line_irq_step              : 16;
+        RK_U32 dec_line_offset_y_st           : 16;
+    } reg14;
+
+    /* copy from llp, media group add */
+    struct SWREG15_IRQ_STA {
+        RK_U32 rkvdec_frame_rdy_sta           : 1;
+        RK_U32 rkvdec_strm_error_sta          : 1;
+        RK_U32 rkvdec_core_timeout_sta        : 1;
+        RK_U32 rkvdec_ip_timeout_sta          : 1;
+        RK_U32 rkvdec_bus_error_sta           : 1;
+        RK_U32 rkvdec_buffer_empty_sta        : 1;
+        RK_U32 rkvdec_colmv_ref_error_sta     : 1;
+        RK_U32 rkvdec_error_spread_sta        : 1;
+        RK_U32 create_core_timeout_sta        : 1;
+        RK_U32 wlast_miss_match_sta           : 1;
+        RK_U32 rkvdec_core_rst_rdy_sta        : 1;
+        RK_U32 rkvdec_ip_rst_rdy_sta          : 1;
+        RK_U32 force_busidle_rdy_sta          : 1;
+        RK_U32 ltb_pause_rdy_sta              : 1;
+        RK_U32 ltb_end_flag                   : 1;
+        RK_U32 unsupport_decmode_error_sta    : 1;
+        RK_U32 wmask_bits                     : 15;
+        RK_U32 reserve0                       : 1;
+    } reg15;
+
+    struct SWREG16_ERROR_CTRL_SET {
+        RK_U32 error_proc_disable             : 1;
+        RK_U32 reserve0                       : 7;
+        RK_U32 error_spread_disable           : 1;
+        RK_U32 reserve1                       : 15;
+        RK_U32 roi_error_ctu_cal_en           : 1;
+        RK_U32 reserve2                       : 7;
+    } reg16;
+
+    struct SWREG17_ERR_ROI_CTU_OFFSET_START {
+        RK_U32 roi_x_ctu_offset_st            : 12;
+        RK_U32 reserve0                       : 4;
+        RK_U32 roi_y_ctu_offset_st            : 12;
+        RK_U32 reserve1                       : 4;
+    } reg17;
+
+    struct SWREG18_ERR_ROI_CTU_OFFSET_END {
+        RK_U32 roi_x_ctu_offset_end           : 12;
+        RK_U32 reserve0                       : 4;
+        RK_U32 roi_y_ctu_offset_end           : 12;
+        RK_U32 reserve1                       : 4;
+    } reg18;
+
+    struct SWREG19_ERROR_REF_INFO {
+        RK_U32 avs2_ref_error_field           : 1;
+        RK_U32 avs2_ref_error_topfield        : 1;
+        RK_U32 ref_error_topfield_used        : 1;
+        RK_U32 ref_error_botfield_used        : 1;
+        RK_U32 reserve0                       : 28;
+    } reg19;
+
+    /* SWREG20_CABAC_ERROR_EN_LOWBITS */
+    RK_U32 reg20_cabac_error_en_lowbits;
+
+    /* SWREG21_CABAC_ERROR_EN_HIGHBITS */
+    RK_U32 reg21_cabac_error_en_highbits;
+
+    RK_U32 reserve_reg22;
+
+    struct SWREG23_INVALID_PIXEL_FILL {
+        RK_U32 fill_y                         : 10;
+        RK_U32 fill_u                         : 10;
+        RK_U32 fill_v                         : 10;
+        RK_U32 reserve0                       : 2;
+    } reg23;
+
+    RK_U32 reserve_reg24_26[3];
+
+    struct SWREG27_ALIGN_EN {
+        RK_U32 reserve0                       : 4;
+        RK_U32 ctu_align_wr_en                : 1;
+        RK_U32 reserve1                       : 27;
+    } reg27;
+
+    struct SWREG28_DEBUG_PERF_LATENCY_CTRL0 {
+        RK_U32 axi_perf_work_e                : 1;
+        RK_U32 reserve0                       : 2;
+        RK_U32 axi_cnt_type                   : 1;
+        RK_U32 rd_latency_id                  : 8;
+        RK_U32 reserve1                       : 4;
+        RK_U32 rd_latency_thr                 : 12;
+        RK_U32 reserve2                       : 4;
+    } reg28;
+
+    struct SWREG29_DEBUG_PERF_LATENCY_CTRL1 {
+        RK_U32 addr_align_type                : 2;
+        RK_U32 ar_cnt_id_type                 : 1;
+        RK_U32 aw_cnt_id_type                 : 1;
+        RK_U32 ar_count_id                    : 8;
+        RK_U32 reserve0                       : 4;
+        RK_U32 aw_count_id                    : 8;
+        RK_U32 rd_band_width_mode             : 1;
+        RK_U32 reserve1                       : 7;
+    } reg29;
+
+    struct SWREG30_QOS_CTRL {
+        RK_U32 axi_wr_qos_level               : 4;
+        RK_U32 reserve0                       : 4;
+        RK_U32 axi_wr_qos                     : 4;
+        RK_U32 reserve1                       : 4;
+        RK_U32 axi_rd_qos_level               : 4;
+        RK_U32 reserve2                       : 4;
+        RK_U32 axi_rd_qos                     : 4;
+        RK_U32 reserve3                       : 4;
+    } reg30;
+} Vdpu383CtrlReg;
+
+typedef struct Vdpu383RegCommonAddr_t {
+    /* SWREG128_STRM_BASE */
+    RK_U32 reg128_strm_base;
+
+    /* SWREG129_RPS_BASE */
+    RK_U32 reg129_rps_base;
+
+    /* SWREG130_CABACTBL_BASE */
+    RK_U32 reg130_cabactbl_base;
+
+    /* SWREG131_GBL_BASE */
+    RK_U32 reg131_gbl_base;
+
+    /* SWREG132_SCANLIST_ADDR */
+    RK_U32 reg132_scanlist_addr;
+
+    /* SWREG133_SCL_BASE */
+    RK_U32 reg133_scale_down_base;
+
+    /* SWREG134_FGS_BASE */
+    RK_U32 reg134_fgs_base;
+
+    RK_U32 reserve_reg135_139[5];
+
+    /* SWREG140_RCB_STRMD_ROW_OFFSET */
+    RK_U32 reg140_rcb_strmd_row_offset;
+
+    /* SWREG141_RCB_STRMD_ROW_LEN */
+    RK_U32 reg141_rcb_strmd_row_len;
+
+    /* SWREG142_RCB_STRMD_TILE_ROW_OFFSET */
+    RK_U32 reg142_rcb_strmd_tile_row_offset;
+
+    /* SWREG143_RCB_STRMD_TILE_ROW_LEN */
+    RK_U32 reg143_rcb_strmd_tile_row_len;
+
+    /* SWREG144_RCB_INTER_ROW_OFFSET */
+    RK_U32 reg144_rcb_inter_row_offset;
+
+    /* SWREG145_RCB_INTER_ROW_LEN */
+    RK_U32 reg145_rcb_inter_row_len;
+
+    /* SWREG146_RCB_INTER_TILE_ROW_OFFSET */
+    RK_U32 reg146_rcb_inter_tile_row_offset;
+
+    /* SWREG147_RCB_INTER_TILE_ROW_LEN */
+    RK_U32 reg147_rcb_inter_tile_row_len;
+
+    /* SWREG148_RCB_INTRA_ROW_OFFSET */
+    RK_U32 reg148_rcb_intra_row_offset;
+
+    /* SWREG149_RCB_INTRA_ROW_LEN */
+    RK_U32 reg149_rcb_intra_row_len;
+
+    /* SWREG150_RCB_INTRA_TILE_ROW_OFFSET */
+    RK_U32 reg150_rcb_intra_tile_row_offset;
+
+    /* SWREG151_RCB_INTRA_TILE_ROW_LEN */
+    RK_U32 reg151_rcb_intra_tile_row_len;
+
+    /* SWREG152_RCB_FILTERD_ROW_OFFSET */
+    RK_U32 reg152_rcb_filterd_row_offset;
+
+    /* SWREG153_RCB_FILTERD_ROW_LEN */
+    RK_U32 reg153_rcb_filterd_row_len;
+
+    /* SWREG154_RCB_FILTERD_PROTECT_ROW_OFFSET */
+    RK_U32 reg154_rcb_filterd_protect_row_offset;
+
+    /* SWREG155_RCB_FILTERD_PROTECT_ROW_LEN */
+    RK_U32 reg155_rcb_filterd_protect_row_len;
+
+    /* SWREG156_RCB_FILTERD_TILE_ROW_OFFSET */
+    RK_U32 reg156_rcb_filterd_tile_row_offset;
+
+    /* SWREG157_RCB_FILTERD_TILE_ROW_LEN */
+    RK_U32 reg157_rcb_filterd_tile_row_len;
+
+    /* SWREG158_RCB_FILTERD_TILE_COL_OFFSET */
+    RK_U32 reg158_rcb_filterd_tile_col_offset;
+
+    /* SWREG159_RCB_FILTERD_TILE_COL_LEN */
+    RK_U32 reg159_rcb_filterd_tile_col_len;
+
+    /* SWREG160_RCB_FILTERD_AV1_UPSCALE_TILE_COL_OFFSET */
+    RK_U32 reg160_rcb_filterd_av1_upscale_tile_col_offset;
+
+    /* SWREG161_RCB_FILTERD_AV1_UPSCALE_TILE_COL_LEN */
+    RK_U32 reg161_rcb_filterd_av1_upscale_tile_col_len;
+
+} Vdpu383RegCommonAddr;
+
+typedef struct Vdpu383RegCommParas_t {
+    /* SWREG64_H26X_PARA */
+    RK_U32 reg64_unused_bits;
+
+    /* SWREG65_STREAM_PARAM_SET */
+    RK_U32 reg65_strm_start_bit;
+
+    /* SWREG66_STREAM_LEN */
+    RK_U32 reg66_stream_len;
+
+    /* SWREG67_GLOBAL_LEN */
+    RK_U32 reg67_global_len;
+
+    /* SWREG68_HOR_STRIDE */
+    RK_U32 reg68_hor_virstride;
+
+    /* SWREG69_RASTER_UV_HOR_STRIDE */
+    RK_U32 reg69_raster_uv_hor_virstride;
+
+    /* SWREG70_Y_STRIDE */
+    RK_U32 reg70_y_virstride;
+
+    /* SWREG71_SCL_Y_HOR_VIRSTRIDE */
+    RK_U32 reg71_scl_ref_hor_virstride;
+
+    /* SWREG72_SCL_UV_HOR_VIRSTRIDE */
+    RK_U32 reg72_scl_ref_raster_uv_hor_virstride;
+
+    /* SWREG73_SCL_Y_VIRSTRIDE */
+    RK_U32 reg73_scl_ref_virstride;
+
+    /* SWREG74_FGS_Y_HOR_VIRSTRIDE */
+    RK_U32 reg74_fgs_ref_hor_virstride;
+
+    RK_U32 reserve_reg75_79[5];
+
+    /* SWREG80_ERROR_REF_Y_HOR_VIRSTRIDE */
+    RK_U32 reg80_error_ref_hor_virstride;
+
+    /* SWREG81_ERROR_REF_UV_HOR_VIRSTRIDE */
+    RK_U32 reg81_error_ref_raster_uv_hor_virstride;
+
+    /* SWREG82_ERROR_REF_Y_VIRSTRIDE */
+    RK_U32 reg82_error_ref_virstride;
+
+    /* SWREG83_REF0_Y_HOR_VIRSTRIDE */
+    RK_U32 reg83_ref0_hor_virstride;
+
+    /* SWREG84_REF0_UV_HOR_VIRSTRIDE */
+    RK_U32 reg84_ref0_raster_uv_hor_virstride;
+
+    /* SWREG85_REF0_Y_VIRSTRIDE */
+    RK_U32 reg85_ref0_virstride;
+
+    /* SWREG86_REF1_Y_HOR_VIRSTRIDE */
+    RK_U32 reg86_ref1_hor_virstride;
+
+    /* SWREG87_REF1_UV_HOR_VIRSTRIDE */
+    RK_U32 reg87_ref1_raster_uv_hor_virstride;
+
+    /* SWREG88_REF1_Y_VIRSTRIDE */
+    RK_U32 reg88_ref1_virstride;
+
+    /* SWREG89_REF2_Y_HOR_VIRSTRIDE */
+    RK_U32 reg89_ref2_hor_virstride;
+
+    /* SWREG90_REF2_UV_HOR_VIRSTRIDE */
+    RK_U32 reg90_ref2_raster_uv_hor_virstride;
+
+    /* SWREG91_REF2_Y_VIRSTRIDE */
+    RK_U32 reg91_ref2_virstride;
+
+    /* SWREG92_REF3_Y_HOR_VIRSTRIDE */
+    RK_U32 reg92_ref3_hor_virstride;
+
+    /* SWREG93_REF3_UV_HOR_VIRSTRIDE */
+    RK_U32 reg93_ref3_raster_uv_hor_virstride;
+
+    /* SWREG94_REF3_Y_VIRSTRIDE */
+    RK_U32 reg94_ref3_virstride;
+
+    /* SWREG95_REF4_Y_HOR_VIRSTRIDE */
+    RK_U32 reg95_ref4_hor_virstride;
+
+    /* SWREG96_REF4_UV_HOR_VIRSTRIDE */
+    RK_U32 reg96_ref4_raster_uv_hor_virstride;
+
+    /* SWREG97_REF4_Y_VIRSTRIDE */
+    RK_U32 reg97_ref4_virstride;
+
+    /* SWREG98_REF5_Y_HOR_VIRSTRIDE */
+    RK_U32 reg98_ref5_hor_virstride;
+
+    /* SWREG99_REF5_UV_HOR_VIRSTRIDE */
+    RK_U32 reg99_ref5_raster_uv_hor_virstride;
+
+    /* SWREG100_REF5_Y_VIRSTRIDE */
+    RK_U32 reg100_ref5_virstride;
+
+    /* SWREG101_REF6_Y_HOR_VIRSTRIDE */
+    RK_U32 reg101_ref6_hor_virstride;
+
+    /* SWREG102_REF6_UV_HOR_VIRSTRIDE */
+    RK_U32 reg102_ref6_raster_uv_hor_virstride;
+
+    /* SWREG103_REF6_Y_VIRSTRIDE */
+    RK_U32 reg103_ref6_virstride;
+
+    /* SWREG104_REF7_Y_HOR_VIRSTRIDE */
+    RK_U32 reg104_ref7_hor_virstride;
+
+    /* SWREG105_REF7_UV_HOR_VIRSTRIDE */
+    RK_U32 reg105_ref7_raster_uv_hor_virstride;
+
+    /* SWREG106_REF7_Y_VIRSTRIDE */
+    RK_U32 reg106_ref7_virstride;
+
+} Vdpu383RegCommParas;
+
+typedef struct Vdpu383RegNew_t {
+    struct SWREG320_IDLE_FLAG {
+        RK_U32 reserve0                       : 24;
+        RK_U32 rkvdec_bus_idle_flag           : 1;
+        RK_U32 reserve1                       : 7;
+    } reg320;
+
+    RK_U32 reserve_reg321;
+
+    /* SWREG322_PERF_MONITOR */
+    RK_U32 reg322_perf_rd_max_latency_num;
+
+    /* SWREG323_PERF_MONITOR */
+    RK_U32 reg323_perf_rd_latency_samp_num;
+
+    /* SWREG324_PERF_MONITOR */
+    RK_U32 reg324_perf_rd_latency_acc_sum;
+
+    /* SWREG325_PERF_MONITOR */
+    RK_U32 reg325_perf_rd_axi_total_byte;
+
+    /* SWREG326_PERF_MONITOR */
+    RK_U32 reg326_perf_wr_axi_total_bytes;
+
+    /* SWREG327_PERF_MONITOR */
+    RK_U32 reg327_perf_working_cnt;
+
+    RK_U32 reserve_reg328_336[9];
+
+    /* SWREG337_REFLIST_IDX_USED */
+    RK_U32 reg337_inter_sw_reflst_idx_use;
+
+    RK_U32 reserve_reg338_348[11];
+
+    /* SWREG349_PAYLOAD_CNT */
+    RK_U32 reg349_filterd_payload_total_cnt;
+
+    struct SWREG350_WR_OFFSET {
+        RK_U32 filterd_report_offsety         : 16;
+        RK_U32 filterd_report_offsetx         : 16;
+    } reg350;
+
+    struct SWREG351_MAX_PIX {
+        RK_U32 filterd_max_y                  : 10;
+        RK_U32 filterd_max_u                  : 10;
+        RK_U32 filterd_max_v                  : 10;
+        RK_U32 reserve0                       : 2;
+    } reg351;
+
+    struct SWREG352_MIN_PIX {
+        RK_U32 filterd_min_y                  : 10;
+        RK_U32 filterd_min_u                  : 10;
+        RK_U32 filterd_min_v                  : 10;
+        RK_U32 reserve0                       : 2;
+    } reg352;
+
+    /* SWREG353_WR_LINE_NUM */
+    RK_U32 reg353_filterd_line_irq_offsety;
+
+    RK_U32 reserve_reg354_355[2];
+
+    struct SWREG356_RCB_RW_SUM {
+        RK_U32 rcb_rd_sum_chk                 : 8;
+        RK_U32 rcb_wr_sum_chk                 : 8;
+        RK_U32 reserve0                       : 16;
+    } reg356;
+
+    RK_U32 reserve_reg357;
+
+    struct SWREG358_ERR_CTU_NUM0 {
+        RK_U32 error_ctu_num                  : 24;
+        RK_U32 roi_error_ctu_num_lowbit       : 8;
+    } reg358;
+
+    /* SWREG359_ERR_CTU_NUM1 */
+    RK_U32 reg359_roi_error_ctu_num_highbit;
+
+} Vdpu383RegNew;
+
+typedef struct Vdpu383RegLlp_t {
+    struct SWREG0_LINK_MODE {
+        RK_U32 llp_mmu_zap_cache_dis          : 1;
+        RK_U32 reserve0                       : 15;
+        RK_U32 core_work_mode                 : 1;
+        RK_U32 ccu_core_work_mode             : 1;
+        RK_U32 reserve1                       : 3;
+        RK_U32 ltb_pause_flag                 : 1;
+        RK_U32 reserve2                       : 10;
+    } reg0;
+
+    struct SWREG1_CFG_START_ADDR {
+        RK_U32 reserve0                       : 4;
+        RK_U32 reg_cfg_addr                   : 28;
+    } reg1;
+
+    struct SWREG2_LINK_MODE {
+        RK_U32 pre_frame_num                  : 30;
+        RK_U32 reserve0                       : 1;
+        RK_U32 link_mode                      : 1;
+    } reg2;
+
+    /* SWREG3_CONFIG_DONE */
+    RK_U32 reg3_done;
+
+    /* SWREG4_DECODERED_NUM */
+    RK_U32 reg4_num;
+
+    /* SWREG5_DEC_TOTAL_NUM */
+    RK_U32 reg5_total_num;
+
+    /* SWREG6_LINK_MODE_EN */
+    RK_U32 reg6_mode_en;
+
+    /* SWREG7_SKIP_NUM */
+    RK_U32 reg7_num;
+
+    /* SWREG8_CUR_LTB_IDX */
+    RK_U32 reg8_ltb_idx;
+
+    RK_U32 reserve_reg9_15[7];
+
+    /* SWREG16_DEC_E */
+    RK_U32 reg16_dec_e;
+
+    /* SWREG17_SOFT_RST */
+    RK_U32 reg17_rkvdec_ip_rst_p;
+
+    struct SWREG18_IRQ {
+        RK_U32 rkvdec_irq                     : 1;
+        RK_U32 rkvdec_line_irq                : 1;
+        RK_U32 reserve0                       : 14;
+        RK_U32 wmask                          : 2;
+        RK_U32 reserve1                       : 14;
+    } reg18;
+
+    struct SWREG19_STA {
+        RK_U32 rkvdec_frame_rdy_sta           : 1;
+        RK_U32 rkvdec_strm_error_sta          : 1;
+        RK_U32 rkvdec_core_timeout_sta        : 1;
+        RK_U32 rkvdec_ip_timeout_sta          : 1;
+        RK_U32 rkvdec_bus_error_sta           : 1;
+        RK_U32 rkvdec_buffer_empty_sta        : 1;
+        RK_U32 rkvdec_colmv_ref_error_sta     : 1;
+        RK_U32 rkvdec_error_spread_sta        : 1;
+        RK_U32 create_core_timeout_sta        : 1;
+        RK_U32 wlast_miss_match_sta           : 1;
+        RK_U32 rkvdec_core_rst_rdy_sta        : 1;
+        RK_U32 rkvdec_ip_rst_rdy_sta          : 1;
+        RK_U32 force_busidle_rdy_sta          : 1;
+        RK_U32 ltb_pause_rdy_sta              : 1;
+        RK_U32 ltb_end_flag                   : 1;
+        RK_U32 unsupport_decmode_error_sta    : 1;
+        RK_U32 wmask_bits                     : 15;
+        RK_U32 reserve0                       : 1;
+    } reg19;
+
+    RK_U32 reserve_reg20;
+
+    /* SWREG21_IP_TIMEOUT_THRESHOD */
+    RK_U32 reg21_ip_timeout_threshold;
+
+    struct SWREG22_IP_EN {
+        RK_U32 ip_timeout_pause_flag          : 1;
+        RK_U32 reserve0                       : 3;
+        RK_U32 auto_reset_dis                 : 1;
+        RK_U32 reserve1                       : 3;
+        RK_U32 force_busidle_req_flag         : 1;
+        RK_U32 reserve2                       : 3;
+        RK_U32 bus_clkgate_dis                : 1;
+        RK_U32 ctrl_clkgate_dis               : 1;
+        RK_U32 reserve3                       : 1;
+        RK_U32 irq_dis                        : 1;
+        RK_U32 wid_reorder_dis                : 1;
+        RK_U32 reserve4                       : 7;
+        RK_U32 clk_cru_mode                   : 2;
+        RK_U32 reserve5                       : 5;
+        RK_U32 mmu_sel                        : 1;
+    } reg22;
+
+    struct SWREG23_IN_OUT {
+        RK_U32 endian                         : 1;
+        RK_U32 swap32_e                       : 1;
+        RK_U32 swap64_e                       : 1;
+        RK_U32 str_endian                     : 1;
+        RK_U32 str_swap32_e                   : 1;
+        RK_U32 str_swap64_e                   : 1;
+        RK_U32 reserve0                       : 26;
+    } reg23;
+
+    /* SWREG24_EXTRA_STRM_BASE */
+    RK_U32 reg24_extra_stream_base;
+
+    /* SWREG25_EXTRA_STRM_LEN */
+    RK_U32 reg25_extra_stream_len;
+
+    /* SWREG26_EXTRA_STRM_PARA_SET */
+    RK_U32 reg26_extra_strm_start_bit;
+
+    /* SWREG27_BUF_EMPTY_RESTART */
+    RK_U32 reg27_buf_emtpy_restart_p;
+
+    /* SWREG28_RCB_BASE */
+    RK_U32 reg28_rcb_base;
+
+} Vdpu383RegLlp;
+
+typedef struct Vdpu383RcbInfo_t {
+    RK_U32              reg_idx;
+    RK_S32              size;
+    RK_S32              offset;
+} Vdpu383RcbInfo;
+
+#ifdef  __cplusplus
+extern "C" {
+#endif
+
+RK_S32 vdpu383_get_rcb_buf_size(Vdpu383RcbInfo *info, RK_S32 width, RK_S32 height);
+void vdpu383_setup_rcb(Vdpu383RegCommonAddr *reg, MppDev dev, MppBuffer buf, Vdpu383RcbInfo *info);
+RK_S32 vdpu383_compare_rcb_size(const void *a, const void *b);
+void vdpu383_setup_statistic(Vdpu383CtrlReg *com);
+void vdpu383_afbc_align_calc(MppBufSlots slots, MppFrame frame, RK_U32 expand);
+RK_S32 vdpu383_set_rcbinfo(MppDev dev, Vdpu383RcbInfo *rcb_info);
+void vdpu383_setup_down_scale(MppFrame frame, MppDev dev, Vdpu383CtrlReg *com, void* comParas);
+void vdpu383_update_thumbnail_frame_info(MppFrame frame);
+
+#ifdef DUMP_VDPU383_DATAS
+extern RK_U32 dump_cur_frame;
+extern char dump_cur_dir[128];
+extern char dump_cur_fname_path[512];
+
+MPP_RET flip_string(char *str);
+MPP_RET dump_data_to_file(char *fname_path, void *data, RK_U32 data_bit_size,
+                          RK_U32 line_bits, RK_U32 big_end);
+#endif
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif /* __VDPU383_COM_H__ */
diff --git a/mpp/hal/rkdec/inc/vdpu383_h264d.h b/mpp/hal/rkdec/inc/vdpu383_h264d.h
new file mode 100644
index 000000000..f95c3852a
--- /dev/null
+++ b/mpp/hal/rkdec/inc/vdpu383_h264d.h
@@ -0,0 +1,175 @@
+/* SPDX-License-Identifier: Apache-2.0 OR MIT */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef __VDPU383_H264D_H__
+#define __VDPU383_H264D_H__
+
+#include "vdpu383_com.h"
+
+typedef struct Vdpu383RegH264dParas_t {
+    /* SWREG64_H26X_PARA */
+    RK_U32 reg64_unused_bits;
+
+    /* SWREG65_STREAM_PARAM_SET */
+    RK_U32 reg65_strm_start_bit;
+
+    /* SWREG66_STREAM_LEN */
+    RK_U32 reg66_stream_len;
+
+    /* SWREG67_GLOBAL_LEN */
+    RK_U32 reg67_global_len;
+
+    /* SWREG68_HOR_STRIDE */
+    RK_U32 reg68_hor_virstride;
+
+    /* SWREG69_RASTER_UV_HOR_STRIDE */
+    RK_U32 reg69_raster_uv_hor_virstride;
+
+    /* SWREG70_Y_STRIDE */
+    RK_U32 reg70_y_virstride;
+
+    /* SWREG71_SCL_Y_HOR_VIRSTRIDE */
+    RK_U32 reg71_scl_ref_hor_virstride;
+
+    /* SWREG72_SCL_UV_HOR_VIRSTRIDE */
+    RK_U32 reg72_scl_ref_raster_uv_hor_virstride;
+
+    /* SWREG73_SCL_Y_VIRSTRIDE */
+    RK_U32 reg73_scl_ref_virstride;
+
+    /* SWREG74_FGS_Y_HOR_VIRSTRIDE */
+    RK_U32 reg74_fgs_ref_hor_virstride;
+
+    RK_U32 reserve_reg75_79[5];
+
+    /* SWREG80_ERROR_REF_Y_HOR_VIRSTRIDE */
+    RK_U32 reg80_error_ref_hor_virstride;
+
+    /* SWREG81_ERROR_REF_UV_HOR_VIRSTRIDE */
+    RK_U32 reg81_error_ref_raster_uv_hor_virstride;
+
+    /* SWREG82_ERROR_REF_Y_VIRSTRIDE */
+    RK_U32 reg82_error_ref_virstride;
+
+    /* SWREG83_REF0_Y_HOR_VIRSTRIDE */
+    RK_U32 reg83_ref0_hor_virstride;
+
+    /* SWREG84_REF0_UV_HOR_VIRSTRIDE */
+    RK_U32 reg84_ref0_raster_uv_hor_virstride;
+
+    /* SWREG85_REF0_Y_VIRSTRIDE */
+    RK_U32 reg85_ref0_virstride;
+
+    /* SWREG86_REF1_Y_HOR_VIRSTRIDE */
+    RK_U32 reg86_ref1_hor_virstride;
+
+    /* SWREG87_REF1_UV_HOR_VIRSTRIDE */
+    RK_U32 reg87_ref1_raster_uv_hor_virstride;
+
+    /* SWREG88_REF1_Y_VIRSTRIDE */
+    RK_U32 reg88_ref1_virstride;
+
+    /* SWREG89_REF2_Y_HOR_VIRSTRIDE */
+    RK_U32 reg89_ref2_hor_virstride;
+
+    /* SWREG90_REF2_UV_HOR_VIRSTRIDE */
+    RK_U32 reg90_ref2_raster_uv_hor_virstride;
+
+    /* SWREG91_REF2_Y_VIRSTRIDE */
+    RK_U32 reg91_ref2_virstride;
+
+    /* SWREG92_REF3_Y_HOR_VIRSTRIDE */
+    RK_U32 reg92_ref3_hor_virstride;
+
+    /* SWREG93_REF3_UV_HOR_VIRSTRIDE */
+    RK_U32 reg93_ref3_raster_uv_hor_virstride;
+
+    /* SWREG94_REF3_Y_VIRSTRIDE */
+    RK_U32 reg94_ref3_virstride;
+
+    /* SWREG95_REF4_Y_HOR_VIRSTRIDE */
+    RK_U32 reg95_ref4_hor_virstride;
+
+    /* SWREG96_REF4_UV_HOR_VIRSTRIDE */
+    RK_U32 reg96_ref4_raster_uv_hor_virstride;
+
+    /* SWREG97_REF4_Y_VIRSTRIDE */
+    RK_U32 reg97_ref4_virstride;
+
+    /* SWREG98_REF5_Y_HOR_VIRSTRIDE */
+    RK_U32 reg98_ref5_hor_virstride;
+
+    /* SWREG99_REF5_UV_HOR_VIRSTRIDE */
+    RK_U32 reg99_ref5_raster_uv_hor_virstride;
+
+    /* SWREG100_REF5_Y_VIRSTRIDE */
+    RK_U32 reg100_ref5_virstride;
+
+    /* SWREG101_REF6_Y_HOR_VIRSTRIDE */
+    RK_U32 reg101_ref6_hor_virstride;
+
+    /* SWREG102_REF6_UV_HOR_VIRSTRIDE */
+    RK_U32 reg102_ref6_raster_uv_hor_virstride;
+
+    /* SWREG103_REF6_Y_VIRSTRIDE */
+    RK_U32 reg103_ref6_virstride;
+
+    /* SWREG104_REF7_Y_HOR_VIRSTRIDE */
+    RK_U32 reg104_ref7_hor_virstride;
+
+    /* SWREG105_REF7_UV_HOR_VIRSTRIDE */
+    RK_U32 reg105_ref7_raster_uv_hor_virstride;
+
+    /* SWREG106_REF7_Y_VIRSTRIDE */
+    RK_U32 reg106_ref7_virstride;
+
+} Vdpu383RegH264dParam;
+
+typedef struct Vdpu383RegH264dAddr_t {
+    /* SWREG168_DECOUT_BASE */
+    RK_U32 reg168_decout_base;
+
+    /* SWREG169_ERROR_REF_BASE */
+    RK_U32 reg169_error_ref_base;
+
+    /* SWREG170_185_REF0_BASE */
+    RK_U32 reg170_185_ref_base[16];
+
+    RK_U32 reserve_reg186_191[6];
+
+    /* SWREG192_PAYLOAD_ST_CUR_BASE */
+    RK_U32 reg192_payload_st_cur_base;
+
+    /* SWREG193_FBC_PAYLOAD_OFFSET */
+    RK_U32 reg193_fbc_payload_offset;
+
+    /* SWREG194_PAYLOAD_ST_ERROR_REF_BASE */
+    RK_U32 reg194_payload_st_error_ref_base;
+
+    /* SWREG195_PAYLOAD_ST_REF0_BASE */
+    RK_U32 reg195_210_payload_st_ref_base[16];
+
+    RK_U32 reserve_reg211_215[5];
+
+    /* SWREG216_COLMV_CUR_BASE */
+    RK_U32 reg216_colmv_cur_base;
+
+    /* SWREG217_232_COLMV_REF0_BASE */
+    RK_U32 reg217_232_colmv_ref_base[16];
+
+} Vdpu383RegH264dAddr;
+
+
+typedef struct Vdpu383H264dRegSet_t {
+    Vdpu383RegVersion     reg_version;       /* 0 */
+    Vdpu383CtrlReg        ctrl_regs;         /* 8-30 */
+    Vdpu383RegCommonAddr  common_addr;       /* 128-134, 140-161 */
+    // Vdpu383RegNew         new_add;           /* 320-359 */
+
+    Vdpu383RegH264dParam  h264d_paras;       /* 64-74, 80-106 */
+    Vdpu383RegH264dAddr   h264d_addrs;       /* 168-185, 192-210, 216-232 */
+} Vdpu383H264dRegSet;
+
+#endif /* __VDPU383_H264D_H__ */
diff --git a/mpp/hal/rkdec/inc/vdpu383_h265d.h b/mpp/hal/rkdec/inc/vdpu383_h265d.h
new file mode 100644
index 000000000..b8d8ebbef
--- /dev/null
+++ b/mpp/hal/rkdec/inc/vdpu383_h265d.h
@@ -0,0 +1,172 @@
+/* SPDX-License-Identifier: Apache-2.0 OR MIT */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef __VDPU383_H265D_H__
+#define __VDPU383_H265D_H__
+
+#include "vdpu383_com.h"
+
+typedef struct Vdpu383RegH265dParas_t {
+    /* SWREG64_H26X_PARA */
+    RK_U32 reg64_unused_bits;
+
+    /* SWREG65_STREAM_PARAM_SET */
+    RK_U32 reg65_strm_start_bit;
+
+    /* SWREG66_STREAM_LEN */
+    RK_U32 reg66_stream_len;
+
+    /* SWREG67_GLOBAL_LEN */
+    RK_U32 reg67_global_len;
+
+    /* SWREG68_HOR_STRIDE */
+    RK_U32 reg68_hor_virstride;
+
+    /* SWREG69_RASTER_UV_HOR_STRIDE */
+    RK_U32 reg69_raster_uv_hor_virstride;
+
+    /* SWREG70_Y_STRIDE */
+    RK_U32 reg70_y_virstride;
+
+    /* SWREG71_SCL_Y_HOR_VIRSTRIDE */
+    RK_U32 reg71_scl_ref_hor_virstride;
+
+    /* SWREG72_SCL_UV_HOR_VIRSTRIDE */
+    RK_U32 reg72_scl_ref_raster_uv_hor_virstride;
+
+    /* SWREG73_SCL_Y_VIRSTRIDE */
+    RK_U32 reg73_scl_ref_virstride;
+
+    /* SWREG74_FGS_Y_HOR_VIRSTRIDE */
+    RK_U32 reg74_fgs_ref_hor_virstride;
+
+    RK_U32 reserve_reg75_79[5];
+
+    /* SWREG80_ERROR_REF_Y_HOR_VIRSTRIDE */
+    RK_U32 reg80_error_ref_hor_virstride;
+
+    /* SWREG81_ERROR_REF_UV_HOR_VIRSTRIDE */
+    RK_U32 reg81_error_ref_raster_uv_hor_virstride;
+
+    /* SWREG82_ERROR_REF_Y_VIRSTRIDE */
+    RK_U32 reg82_error_ref_virstride;
+
+    /* SWREG83_REF0_Y_HOR_VIRSTRIDE */
+    RK_U32 reg83_ref0_hor_virstride;
+
+    /* SWREG84_REF0_UV_HOR_VIRSTRIDE */
+    RK_U32 reg84_ref0_raster_uv_hor_virstride;
+
+    /* SWREG85_REF0_Y_VIRSTRIDE */
+    RK_U32 reg85_ref0_virstride;
+
+    /* SWREG86_REF1_Y_HOR_VIRSTRIDE */
+    RK_U32 reg86_ref1_hor_virstride;
+
+    /* SWREG87_REF1_UV_HOR_VIRSTRIDE */
+    RK_U32 reg87_ref1_raster_uv_hor_virstride;
+
+    /* SWREG88_REF1_Y_VIRSTRIDE */
+    RK_U32 reg88_ref1_virstride;
+
+    /* SWREG89_REF2_Y_HOR_VIRSTRIDE */
+    RK_U32 reg89_ref2_hor_virstride;
+
+    /* SWREG90_REF2_UV_HOR_VIRSTRIDE */
+    RK_U32 reg90_ref2_raster_uv_hor_virstride;
+
+    /* SWREG91_REF2_Y_VIRSTRIDE */
+    RK_U32 reg91_ref2_virstride;
+
+    /* SWREG92_REF3_Y_HOR_VIRSTRIDE */
+    RK_U32 reg92_ref3_hor_virstride;
+
+    /* SWREG93_REF3_UV_HOR_VIRSTRIDE */
+    RK_U32 reg93_ref3_raster_uv_hor_virstride;
+
+    /* SWREG94_REF3_Y_VIRSTRIDE */
+    RK_U32 reg94_ref3_virstride;
+
+    /* SWREG95_REF4_Y_HOR_VIRSTRIDE */
+    RK_U32 reg95_ref4_hor_virstride;
+
+    /* SWREG96_REF4_UV_HOR_VIRSTRIDE */
+    RK_U32 reg96_ref4_raster_uv_hor_virstride;
+
+    /* SWREG97_REF4_Y_VIRSTRIDE */
+    RK_U32 reg97_ref4_virstride;
+
+    /* SWREG98_REF5_Y_HOR_VIRSTRIDE */
+    RK_U32 reg98_ref5_hor_virstride;
+
+    /* SWREG99_REF5_UV_HOR_VIRSTRIDE */
+    RK_U32 reg99_ref5_raster_uv_hor_virstride;
+
+    /* SWREG100_REF5_Y_VIRSTRIDE */
+    RK_U32 reg100_ref5_virstride;
+
+    /* SWREG101_REF6_Y_HOR_VIRSTRIDE */
+    RK_U32 reg101_ref6_hor_virstride;
+
+    /* SWREG102_REF6_UV_HOR_VIRSTRIDE */
+    RK_U32 reg102_ref6_raster_uv_hor_virstride;
+
+    /* SWREG103_REF6_Y_VIRSTRIDE */
+    RK_U32 reg103_ref6_virstride;
+
+    /* SWREG104_REF7_Y_HOR_VIRSTRIDE */
+    RK_U32 reg104_ref7_hor_virstride;
+
+    /* SWREG105_REF7_UV_HOR_VIRSTRIDE */
+    RK_U32 reg105_ref7_raster_uv_hor_virstride;
+
+    /* SWREG106_REF7_Y_VIRSTRIDE */
+    RK_U32 reg106_ref7_virstride;
+
+} Vdpu383RegH265dParas;
+
+typedef struct Vdpu383RegH265dAddr_t {
+    /* SWREG168_DECOUT_BASE */
+    RK_U32 reg168_decout_base;
+
+    /* SWREG169_ERROR_REF_BASE */
+    RK_U32 reg169_error_ref_base;
+
+    /* SWREG170_185_REF0_BASE */
+    RK_U32 reg170_185_ref_base[16];
+
+    RK_U32 reserve_reg186_191[6];
+
+    /* SWREG192_PAYLOAD_ST_CUR_BASE */
+    RK_U32 reg192_payload_st_cur_base;
+
+    /* SWREG193_FBC_PAYLOAD_OFFSET */
+    RK_U32 reg193_fbc_payload_offset;
+
+    /* SWREG194_PAYLOAD_ST_ERROR_REF_BASE */
+    RK_U32 reg194_payload_st_error_ref_base;
+
+    /* SWREG195_210_PAYLOAD_ST_REF0_BASE */
+    RK_U32 reg195_210_payload_st_ref_base[16];
+
+    RK_U32 reserve_reg211_215[5];
+
+    /* SWREG216_COLMV_CUR_BASE */
+    RK_U32 reg216_colmv_cur_base;
+
+    /* SWREG217_232_COLMV_REF0_BASE */
+    RK_U32 reg217_232_colmv_ref_base[16];
+
+} Vdpu383RegH265dAddr;
+
+typedef struct Vdpu383H265dRegSet_t {
+    Vdpu383RegVersion       reg_version;        /* 0 */
+    Vdpu383CtrlReg          ctrl_regs;          /* 8-30 */
+    Vdpu383RegCommonAddr    common_addr;        /* 128-134, 140-161 */
+    Vdpu383RegH265dParas    h265d_paras;        /* 64-74, 80-106 */
+    Vdpu383RegH265dAddr     h265d_addrs;        /* 168-185, 192-210, 216-232 */
+} Vdpu383H265dRegSet;
+
+#endif /* __VDPU383_H265D_H__ */
diff --git a/mpp/hal/rkdec/inc/vdpu383_vp9d.h b/mpp/hal/rkdec/inc/vdpu383_vp9d.h
new file mode 100644
index 000000000..bd032e896
--- /dev/null
+++ b/mpp/hal/rkdec/inc/vdpu383_vp9d.h
@@ -0,0 +1,184 @@
+/* SPDX-License-Identifier: Apache-2.0 OR MIT */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef __HAL_VDPU383_VP9D_H__
+#define __HAL_VDPU383_VP9D_H__
+
+#include "rk_type.h"
+#include "vdpu383_com.h"
+
+typedef struct Vdpu383RegVp9dParas_t {
+    /* SWREG64_H26X_PARA */
+    RK_U32 reg64_unused_bits;
+
+    /* SWREG65_STREAM_PARAM_SET */
+    RK_U32 reg65_strm_start_bit;
+
+    /* SWREG66_STREAM_LEN */
+    RK_U32 reg66_stream_len;
+
+    /* SWREG67_GLOBAL_LEN */
+    RK_U32 reg67_global_len;
+
+    /* SWREG68_HOR_STRIDE */
+    RK_U32 reg68_hor_virstride;
+
+    /* SWREG69_RASTER_UV_HOR_STRIDE */
+    RK_U32 reg69_raster_uv_hor_virstride;
+
+    /* SWREG70_Y_STRIDE */
+    RK_U32 reg70_y_virstride;
+
+    /* SWREG71_SCL_Y_HOR_VIRSTRIDE */
+    RK_U32 reg71_scl_ref_hor_virstride;
+
+    /* SWREG72_SCL_UV_HOR_VIRSTRIDE */
+    RK_U32 reg72_scl_ref_raster_uv_hor_virstride;
+
+    /* SWREG73_SCL_Y_VIRSTRIDE */
+    RK_U32 reg73_scl_ref_virstride;
+
+    /* SWREG74_FGS_Y_HOR_VIRSTRIDE */
+    RK_U32 reg74_fgs_ref_hor_virstride;
+
+    RK_U32 reserve_reg75_79[5];
+
+    /* SWREG80_ERROR_REF_Y_HOR_VIRSTRIDE */
+    RK_U32 reg80_error_ref_hor_virstride;
+
+    /* SWREG81_ERROR_REF_UV_HOR_VIRSTRIDE */
+    RK_U32 reg81_error_ref_raster_uv_hor_virstride;
+
+    /* SWREG82_ERROR_REF_Y_VIRSTRIDE */
+    RK_U32 reg82_error_ref_virstride;
+
+    /* SWREG83_REF0_Y_HOR_VIRSTRIDE */
+    RK_U32 reg83_ref0_hor_virstride;
+
+    /* SWREG84_REF0_UV_HOR_VIRSTRIDE */
+    RK_U32 reg84_ref0_raster_uv_hor_virstride;
+
+    /* SWREG85_REF0_Y_VIRSTRIDE */
+    RK_U32 reg85_ref0_virstride;
+
+    /* SWREG86_REF1_Y_HOR_VIRSTRIDE */
+    RK_U32 reg86_ref1_hor_virstride;
+
+    /* SWREG87_REF1_UV_HOR_VIRSTRIDE */
+    RK_U32 reg87_ref1_raster_uv_hor_virstride;
+
+    /* SWREG88_REF1_Y_VIRSTRIDE */
+    RK_U32 reg88_ref1_virstride;
+
+    /* SWREG89_REF2_Y_HOR_VIRSTRIDE */
+    RK_U32 reg89_ref2_hor_virstride;
+
+    /* SWREG90_REF2_UV_HOR_VIRSTRIDE */
+    RK_U32 reg90_ref2_raster_uv_hor_virstride;
+
+    /* SWREG91_REF2_Y_VIRSTRIDE */
+    RK_U32 reg91_ref2_virstride;
+
+    /* SWREG92_REF3_Y_HOR_VIRSTRIDE */
+    RK_U32 reg92_ref3_hor_virstride;
+
+    /* SWREG93_REF3_UV_HOR_VIRSTRIDE */
+    RK_U32 reg93_ref3_raster_uv_hor_virstride;
+
+    /* SWREG94_REF3_Y_VIRSTRIDE */
+    RK_U32 reg94_ref3_virstride;
+
+    /* SWREG95_REF4_Y_HOR_VIRSTRIDE */
+    RK_U32 reg95_ref4_hor_virstride;
+
+    /* SWREG96_REF4_UV_HOR_VIRSTRIDE */
+    RK_U32 reg96_ref4_raster_uv_hor_virstride;
+
+    /* SWREG97_REF4_Y_VIRSTRIDE */
+    RK_U32 reg97_ref4_virstride;
+
+    /* SWREG98_REF5_Y_HOR_VIRSTRIDE */
+    RK_U32 reg98_ref5_hor_virstride;
+
+    /* SWREG99_REF5_UV_HOR_VIRSTRIDE */
+    RK_U32 reg99_ref5_raster_uv_hor_virstride;
+
+    /* SWREG100_REF5_Y_VIRSTRIDE */
+    RK_U32 reg100_ref5_virstride;
+
+    /* SWREG101_REF6_Y_HOR_VIRSTRIDE */
+    RK_U32 reg101_ref6_hor_virstride;
+
+    /* SWREG102_REF6_UV_HOR_VIRSTRIDE */
+    RK_U32 reg102_ref6_raster_uv_hor_virstride;
+
+    /* SWREG103_REF6_Y_VIRSTRIDE */
+    RK_U32 reg103_ref6_virstride;
+
+    /* SWREG104_REF7_Y_HOR_VIRSTRIDE */
+    RK_U32 reg104_ref7_hor_virstride;
+
+    /* SWREG105_REF7_UV_HOR_VIRSTRIDE */
+    RK_U32 reg105_ref7_raster_uv_hor_virstride;
+
+    /* SWREG106_REF7_Y_VIRSTRIDE */
+    RK_U32 reg106_ref7_virstride;
+
+} Vdpu383RegVp9dParas;
+
+
+typedef struct Vdpu383RegVp9dAddr_t {
+    /* SWREG168_DECOUT_BASE */
+    RK_U32 reg168_decout_base;
+
+    /* SWREG169_ERROR_REF_BASE */
+    RK_U32 reg169_error_ref_base;
+
+    /* SWREG170_185_REF0_BASE */
+    union {
+        RK_U32 reg170_185_ref_base[16];
+        struct {
+            RK_U32 reg170_180[11];
+            RK_U32 reg181_segidlast_base;
+            RK_U32 reg182_segidcur_base;
+            RK_U32 reg183_kfprob_base;
+            RK_U32 reg184_lastprob_base;
+            RK_U32 reg185_updateprob_base;
+        };
+    };
+
+    RK_U32 reserve_reg186_191[6];
+
+    /* SWREG192_PAYLOAD_ST_CUR_BASE */
+    RK_U32 reg192_payload_st_cur_base;
+
+    /* SWREG193_FBC_PAYLOAD_OFFSET */
+    RK_U32 reg193_fbc_payload_offset;
+
+    /* SWREG194_PAYLOAD_ST_ERROR_REF_BASE */
+    RK_U32 reg194_payload_st_error_ref_base;
+
+    /* SWREG195_210_PAYLOAD_ST_REF0_BASE */
+    RK_U32 reg195_210_payload_st_ref_base[16];
+
+    RK_U32 reserve_reg211_215[5];
+
+    /* SWREG216_COLMV_CUR_BASE */
+    RK_U32 reg216_colmv_cur_base;
+
+    /* SWREG217_232_COLMV_REF0_BASE */
+    RK_U32 reg217_232_colmv_ref_base[16];
+
+} Vdpu383RegVp9dAddr;
+
+typedef struct Vdpu383Vp9dRegSet_t {
+    Vdpu383RegVersion       reg_version;        /* 0 */
+    Vdpu383CtrlReg          ctrl_regs;          /* 8-30 */
+    Vdpu383RegCommonAddr    common_addr;        /* 128-134, 140-161 */
+    Vdpu383RegVp9dParas     vp9d_paras;         /* 64-74, 80-106 */
+    Vdpu383RegVp9dAddr      vp9d_addrs;         /* 168-185, 192-210, 216-232 */
+} Vdpu383Vp9dRegSet;
+
+#endif /* __HAL_VDPU383_VP9D_H__ */
\ No newline at end of file
diff --git a/mpp/hal/rkdec/vdpu34x_com.c b/mpp/hal/rkdec/vdpu34x_com.c
index f0e524154..19faddb10 100644
--- a/mpp/hal/rkdec/vdpu34x_com.c
+++ b/mpp/hal/rkdec/vdpu34x_com.c
@@ -266,3 +266,27 @@ void vdpu34x_afbc_align_calc(MppBufSlots slots, MppFrame frame, RK_U32 expand)
     }
     mpp_frame_set_ver_stride(frame, ver_stride);
 }
+
+RK_U32 vdpu34x_get_colmv_size(RK_U32 width, RK_U32 height, RK_U32 ctu_size,
+                              RK_U32 colmv_bytes, RK_U32 colmv_size, RK_U32 compress)
+{
+    RK_U32 colmv_total_size;
+
+    if (compress) {
+        RK_U32 segment_w = (64 * colmv_size * colmv_size) / ctu_size;
+        RK_U32 segment_h = ctu_size;
+        RK_U32 seg_cnt_w = MPP_ALIGN(width, segment_w) / segment_w;
+        RK_U32 seg_cnt_h = MPP_ALIGN(height, segment_h) / segment_h;
+        RK_U32 seg_head_size = MPP_ALIGN(seg_cnt_w, 16) * seg_cnt_h;
+        RK_U32 seg_payload_size = seg_cnt_w * seg_cnt_h * 64 * colmv_bytes;
+
+        colmv_total_size = seg_head_size + seg_payload_size;
+    } else {
+        RK_U32 colmv_block_size_w = MPP_ALIGN(width, 64) / colmv_size;
+        RK_U32 colmv_block_size_h = MPP_ALIGN(height, 64) / colmv_size;
+
+        colmv_total_size = colmv_block_size_w * colmv_block_size_h * colmv_bytes;
+    }
+
+    return MPP_ALIGN(colmv_total_size, 128);
+}
diff --git a/mpp/hal/rkdec/vdpu382_com.c b/mpp/hal/rkdec/vdpu382_com.c
index 4b8183439..4e32ab5ea 100644
--- a/mpp/hal/rkdec/vdpu382_com.c
+++ b/mpp/hal/rkdec/vdpu382_com.c
@@ -294,3 +294,27 @@ void vdpu382_setup_down_scale(MppFrame frame, MppDev dev, Vdpu382RegCommon *com)
     mpp_dev_set_reg_offset(dev, 199, down_scale_uv_offset);
     mpp_meta_set_s32(meta, KEY_DEC_TBN_UV_OFFSET, down_scale_uv_offset);
 }
+
+RK_U32 vdpu382_get_colmv_size(RK_U32 width, RK_U32 height, RK_U32 ctu_size,
+                              RK_U32 colmv_bytes, RK_U32 colmv_size, RK_U32 compress)
+{
+    RK_U32 colmv_total_size;
+
+    if (compress) {
+        RK_U32 segment_w = (64 * colmv_size * colmv_size) / ctu_size;
+        RK_U32 segment_h = ctu_size;
+        RK_U32 seg_cnt_w = MPP_ALIGN(width, segment_w) / segment_w;
+        RK_U32 seg_cnt_h = MPP_ALIGN(height, segment_h) / segment_h;
+        RK_U32 seg_head_size = MPP_ALIGN(seg_cnt_w, 16) * seg_cnt_h;
+        RK_U32 seg_payload_size = seg_cnt_w * seg_cnt_h * 64 * colmv_bytes;
+
+        colmv_total_size = seg_head_size + seg_payload_size;
+    } else {
+        RK_U32 colmv_block_size_w = MPP_ALIGN(width, 64) / colmv_size;
+        RK_U32 colmv_block_size_h = MPP_ALIGN(height, 64) / colmv_size;
+
+        colmv_total_size = colmv_block_size_w * colmv_block_size_h * colmv_bytes;
+    }
+
+    return MPP_ALIGN(colmv_total_size, 128);
+}
diff --git a/mpp/hal/rkdec/vdpu383_com.c b/mpp/hal/rkdec/vdpu383_com.c
new file mode 100644
index 000000000..c131ecd94
--- /dev/null
+++ b/mpp/hal/rkdec/vdpu383_com.c
@@ -0,0 +1,395 @@
+/* SPDX-License-Identifier: Apache-2.0 OR MIT */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#define MODULE_TAG "vdpu383_com"
+
+#include <string.h>
+
+#include "mpp_log.h"
+#include "mpp_buffer.h"
+#include "mpp_common.h"
+#include "mpp_compat_impl.h"
+#include "mpp_frame_impl.h"
+
+#include "vdpu383_com.h"
+
+static RK_U32 rcb_coeff[RCB_BUF_COUNT] = {
+    [RCB_STRMD_ROW]                 = 3,
+    [RCB_STRMD_TILE_ROW]            = 3,
+    [RCB_INTER_ROW]                 = 6,
+    [RCB_INTER_TILE_ROW]            = 6,
+    [RCB_INTRA_ROW]                 = 5,
+    [RCB_INTRA_TILE_ROW]            = 5,
+    [RCB_FILTERD_ROW]               = 60,
+    [RCB_FILTERD_PROTECT_ROW]       = 60,
+    [RCB_FILTERD_TILE_ROW]          = 60,
+    [RCB_FILTERD_TILE_COL]          = 90,
+    [RCB_FILTERD_AV1_UP_TILE_COL]   = 0,
+};
+
+static RK_S32 update_size_offset(Vdpu383RcbInfo *info, RK_U32 reg_idx,
+                                 RK_S32 offset, RK_S32 len, RK_S32 idx)
+{
+    RK_S32 buf_size = 0;
+
+    buf_size = 2 * MPP_ALIGN(len * rcb_coeff[idx], RCB_ALLINE_SIZE);
+    info[idx].reg_idx = reg_idx;
+    info[idx].offset = offset;
+    info[idx].size = buf_size;
+
+    return buf_size;
+}
+
+RK_S32 vdpu383_get_rcb_buf_size(Vdpu383RcbInfo *info, RK_S32 width, RK_S32 height)
+{
+    RK_S32 offset = 0;
+
+    offset += update_size_offset(info, 140, offset, width, RCB_STRMD_ROW);
+    offset += update_size_offset(info, 142, offset, width, RCB_STRMD_TILE_ROW);
+    offset += update_size_offset(info, 144, offset, width, RCB_INTER_ROW);
+    offset += update_size_offset(info, 146, offset, width, RCB_INTER_TILE_ROW);
+    offset += update_size_offset(info, 148, offset, width, RCB_INTRA_ROW);
+    offset += update_size_offset(info, 150, offset, width, RCB_INTRA_TILE_ROW);
+    offset += update_size_offset(info, 152, offset, width, RCB_FILTERD_ROW);
+    offset += update_size_offset(info, 154, offset, width, RCB_FILTERD_PROTECT_ROW);
+    offset += update_size_offset(info, 156, offset, width, RCB_FILTERD_TILE_ROW);
+    offset += update_size_offset(info, 158, offset, height, RCB_FILTERD_TILE_COL);
+    offset += update_size_offset(info, 160, offset, height, RCB_FILTERD_AV1_UP_TILE_COL);
+
+    return offset;
+}
+
+void vdpu383_setup_rcb(Vdpu383RegCommonAddr *reg, MppDev dev,
+                       MppBuffer buf, Vdpu383RcbInfo *info)
+{
+    MppDevRegOffsetCfg trans_cfg;
+    RK_U32 i;
+
+    reg->reg140_rcb_strmd_row_offset           = mpp_buffer_get_fd(buf);
+    reg->reg142_rcb_strmd_tile_row_offset      = mpp_buffer_get_fd(buf);
+    reg->reg144_rcb_inter_row_offset           = mpp_buffer_get_fd(buf);
+    reg->reg146_rcb_inter_tile_row_offset      = mpp_buffer_get_fd(buf);
+    reg->reg148_rcb_intra_row_offset           = mpp_buffer_get_fd(buf);
+    reg->reg150_rcb_intra_tile_row_offset      = mpp_buffer_get_fd(buf);
+    reg->reg152_rcb_filterd_row_offset         = mpp_buffer_get_fd(buf);
+    reg->reg154_rcb_filterd_protect_row_offset = mpp_buffer_get_fd(buf);
+    reg->reg156_rcb_filterd_tile_row_offset    = mpp_buffer_get_fd(buf);
+    reg->reg158_rcb_filterd_tile_col_offset    = mpp_buffer_get_fd(buf);
+    reg->reg160_rcb_filterd_av1_upscale_tile_col_offset = mpp_buffer_get_fd(buf);
+
+    reg->reg141_rcb_strmd_row_len            =  info[RCB_STRMD_ROW].size          ;
+    reg->reg143_rcb_strmd_tile_row_len       =  info[RCB_STRMD_TILE_ROW].size     ;
+    reg->reg145_rcb_inter_row_len            =  info[RCB_INTER_ROW].size          ;
+    reg->reg147_rcb_inter_tile_row_len       =  info[RCB_INTER_TILE_ROW].size     ;
+    reg->reg149_rcb_intra_row_len            =  info[RCB_INTRA_ROW].size          ;
+    reg->reg151_rcb_intra_tile_row_len       =  info[RCB_INTRA_TILE_ROW].size     ;
+    reg->reg153_rcb_filterd_row_len          =  info[RCB_FILTERD_ROW].size        ;
+    reg->reg155_rcb_filterd_protect_row_len  =  info[RCB_FILTERD_PROTECT_ROW].size;
+    reg->reg157_rcb_filterd_tile_row_len     =  info[RCB_FILTERD_TILE_ROW].size   ;
+    reg->reg159_rcb_filterd_tile_col_len     =  info[RCB_FILTERD_TILE_COL].size   ;
+    reg->reg161_rcb_filterd_av1_upscale_tile_col_len = info[RCB_FILTERD_AV1_UP_TILE_COL].size;
+
+    for (i = 0; i < RCB_BUF_COUNT; i++) {
+        if (info[i].offset) {
+            trans_cfg.reg_idx = info[i].reg_idx;
+            trans_cfg.offset = info[i].offset;
+            mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
+        }
+    }
+}
+
+RK_S32 vdpu383_compare_rcb_size(const void *a, const void *b)
+{
+    RK_S32 val = 0;
+    Vdpu383RcbInfo *p0 = (Vdpu383RcbInfo *)a;
+    Vdpu383RcbInfo *p1 = (Vdpu383RcbInfo *)b;
+
+    val = (p0->size > p1->size) ? -1 : 1;
+
+    return val;
+}
+
+void vdpu383_setup_statistic(Vdpu383CtrlReg *ctrl_regs)
+{
+    ctrl_regs->reg28.axi_perf_work_e = 1;
+    ctrl_regs->reg28.axi_cnt_type = 1;
+    ctrl_regs->reg28.rd_latency_id = 11;
+
+    ctrl_regs->reg29.addr_align_type     = 1;
+    ctrl_regs->reg29.ar_cnt_id_type      = 0;
+    ctrl_regs->reg29.aw_cnt_id_type      = 1;
+    ctrl_regs->reg29.ar_count_id         = 17;
+    ctrl_regs->reg29.aw_count_id         = 0;
+    ctrl_regs->reg29.rd_band_width_mode  = 0;
+
+    /* set hurry */
+    ctrl_regs->reg30.axi_wr_qos = 0;
+    ctrl_regs->reg30.axi_rd_qos = 0;
+}
+
+void vdpu383_afbc_align_calc(MppBufSlots slots, MppFrame frame, RK_U32 expand)
+{
+    RK_U32 ver_stride = 0;
+    RK_U32 img_height = mpp_frame_get_height(frame);
+    RK_U32 img_width = mpp_frame_get_width(frame);
+    RK_U32 hdr_stride = (*compat_ext_fbc_hdr_256_odd) ?
+                        (MPP_ALIGN(img_width, 256) | 256) :
+                        (MPP_ALIGN(img_width, 64));
+
+    mpp_slots_set_prop(slots, SLOTS_HOR_ALIGN, mpp_align_64);
+    mpp_slots_set_prop(slots, SLOTS_VER_ALIGN, mpp_align_16);
+
+    mpp_frame_set_fbc_hdr_stride(frame, hdr_stride);
+
+    ver_stride = mpp_align_16(img_height);
+    if (*compat_ext_fbc_buf_size) {
+        ver_stride += expand;
+    }
+    mpp_frame_set_ver_stride(frame, ver_stride);
+}
+
+RK_S32 vdpu383_set_rcbinfo(MppDev dev, Vdpu383RcbInfo *rcb_info)
+{
+    MppDevRcbInfoCfg rcb_cfg;
+    RK_U32 i;
+
+    Vdpu383RcbSetMode_e set_rcb_mode = RCB_SET_BY_PRIORITY_MODE;
+
+    RK_U32 rcb_priority[RCB_BUF_COUNT] = {
+        RCB_FILTERD_ROW,
+        RCB_INTER_ROW,
+        RCB_INTRA_ROW,
+        RCB_STRMD_ROW,
+        RCB_INTER_TILE_ROW,
+        RCB_INTRA_TILE_ROW,
+        RCB_STRMD_TILE_ROW,
+        RCB_FILTERD_TILE_ROW,
+        RCB_FILTERD_TILE_COL,
+        RCB_FILTERD_AV1_UP_TILE_COL,
+        RCB_FILTERD_PROTECT_ROW,
+    };
+    /*
+     * RCB_SET_BY_SIZE_SORT_MODE: by size sort
+     * RCB_SET_BY_PRIORITY_MODE: by priority
+     */
+
+    switch (set_rcb_mode) {
+    case RCB_SET_BY_SIZE_SORT_MODE : {
+        Vdpu383RcbInfo info[RCB_BUF_COUNT];
+
+        memcpy(info, rcb_info, sizeof(info));
+        qsort(info, MPP_ARRAY_ELEMS(info),
+              sizeof(info[0]), vdpu383_compare_rcb_size);
+
+        for (i = 0; i < MPP_ARRAY_ELEMS(info); i++) {
+            rcb_cfg.reg_idx = info[i].reg_idx;
+            rcb_cfg.size = info[i].size;
+            if (rcb_cfg.size > 0) {
+                mpp_dev_ioctl(dev, MPP_DEV_RCB_INFO, &rcb_cfg);
+            } else
+                break;
+        }
+    } break;
+    case RCB_SET_BY_PRIORITY_MODE : {
+        Vdpu383RcbInfo *info = rcb_info;
+        RK_U32 index = 0;
+
+        for (i = 0; i < MPP_ARRAY_ELEMS(rcb_priority); i ++) {
+            index = rcb_priority[i];
+
+            rcb_cfg.reg_idx = info[index].reg_idx;
+            rcb_cfg.size = info[index].size;
+            if (rcb_cfg.size > 0) {
+                mpp_dev_ioctl(dev, MPP_DEV_RCB_INFO, &rcb_cfg);
+            }
+        }
+    } break;
+    default:
+        break;
+    }
+
+    return 0;
+}
+
+void vdpu383_update_thumbnail_frame_info(MppFrame frame)
+{
+    RK_U32 down_scale_height = mpp_frame_get_height(frame) >> 1;
+    RK_U32 down_scale_width = mpp_frame_get_width(frame) >> 1;
+    RK_U32 down_scale_ver = MPP_ALIGN(down_scale_height, 16);
+    RK_U32 down_scale_hor = MPP_ALIGN(down_scale_width, 16);
+    RK_U32 down_scale_buf_size = 0;
+
+    if (!MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(frame))) {
+        down_scale_hor = mpp_align_128_odd_plus_64(down_scale_hor);
+        down_scale_ver = mpp_frame_get_ver_stride(frame) >> 1;
+    }
+
+    down_scale_buf_size = down_scale_hor * down_scale_ver *  3 / 2;
+    /*
+     *  no matter what format, scale down image will output as 8bit raster format;
+     */
+    mpp_frame_set_fmt(frame, MPP_FMT_YUV420SP);
+    mpp_frame_set_width(frame, down_scale_width);
+    mpp_frame_set_height(frame, down_scale_height);
+    mpp_frame_set_hor_stride(frame, down_scale_hor);
+    mpp_frame_set_ver_stride(frame, down_scale_ver);
+    mpp_frame_set_buf_size(frame, down_scale_buf_size);
+}
+
+void vdpu383_setup_down_scale(MppFrame frame, MppDev dev, Vdpu383CtrlReg *com, void* comParas)
+{
+    RK_U32 down_scale_height = mpp_frame_get_height(frame) >> 1;
+    RK_U32 down_scale_width = mpp_frame_get_width(frame) >> 1;
+    RK_U32 down_scale_ver = MPP_ALIGN(down_scale_height, 16);
+    RK_U32 down_scale_hor = MPP_ALIGN(down_scale_width, 16);
+
+    Vdpu383RegCommParas* paras = (Vdpu383RegCommParas*)comParas;
+    MppFrameFormat fmt = mpp_frame_get_fmt(frame);
+    MppMeta meta = mpp_frame_get_meta(frame);
+    RK_U32 down_scale_y_offset = 0;
+    RK_U32 down_scale_uv_offset = 0;
+    RK_U32 down_scale_y_virstride = down_scale_ver * down_scale_hor;
+    RK_U32 downscale_buf_size;
+
+    if (!MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(frame))) {
+        down_scale_hor = mpp_align_128_odd_plus_64(down_scale_hor);
+        down_scale_ver = mpp_frame_get_ver_stride(frame) >> 1;
+        down_scale_y_virstride = down_scale_ver * down_scale_hor;
+    }
+    /*
+     *  no matter what format, scale down image will output as 8bit raster format;
+     *  down_scale image buffer size was already added to the buf_size of mpp_frame,
+     *  which was calculated in mpp_buf_slot.cpp: (size = original_size + scaledown_size)
+     */
+    switch ((fmt & MPP_FRAME_FMT_MASK)) {
+    case MPP_FMT_YUV400 : {
+        downscale_buf_size = down_scale_y_virstride;
+    } break;
+    case MPP_FMT_YUV420SP_10BIT :
+    case MPP_FMT_YUV420SP : {
+        downscale_buf_size = down_scale_y_virstride * 3 / 2;
+    } break;
+    case MPP_FMT_YUV422SP_10BIT :
+    case MPP_FMT_YUV422SP : {
+        downscale_buf_size = down_scale_y_virstride * 2;
+    } break;
+    case MPP_FMT_YUV444SP : {
+        downscale_buf_size = down_scale_y_virstride * 3;
+    } break;
+    default : {
+        downscale_buf_size = down_scale_y_virstride * 3 / 2;
+    } break;
+    }
+    downscale_buf_size = MPP_ALIGN(downscale_buf_size, 16);
+
+    down_scale_y_offset = MPP_ALIGN((mpp_frame_get_buf_size(frame) - downscale_buf_size), 16);
+    down_scale_uv_offset = down_scale_y_offset + down_scale_y_virstride;
+
+    com->reg9.scale_down_en = 1;
+    com->reg9.av1_fgs_en = 0;
+    paras->reg71_scl_ref_hor_virstride = down_scale_hor >> 4;
+    paras->reg72_scl_ref_raster_uv_hor_virstride = down_scale_hor >> 4;
+    if ((fmt & MPP_FRAME_FMT_MASK) == MPP_FMT_YUV444SP)
+        paras->reg72_scl_ref_raster_uv_hor_virstride = down_scale_hor >> 3;
+    paras->reg73_scl_ref_virstride = down_scale_y_virstride >> 4;
+    if (mpp_frame_get_thumbnail_en(frame) == MPP_FRAME_THUMBNAIL_MIXED) {
+        mpp_dev_set_reg_offset(dev, 133, down_scale_y_offset);
+        mpp_meta_set_s32(meta, KEY_DEC_TBN_Y_OFFSET, down_scale_y_offset);
+        mpp_meta_set_s32(meta, KEY_DEC_TBN_UV_OFFSET, down_scale_uv_offset);
+    }
+}
+
+#ifdef DUMP_VDPU383_DATAS
+RK_U32 dump_cur_frame = 0;
+char dump_cur_dir[128];
+char dump_cur_fname_path[512];
+
+MPP_RET flip_string(char *str)
+{
+    RK_U32 len = strlen(str);
+    RK_U32 i, j;
+
+    for (i = 0, j = len - 1; i <= j; i++, j--) {
+        // swapping characters
+        char c = str[i];
+        str[i] = str[j];
+        str[j] = c;
+    }
+
+    return MPP_OK;
+}
+
+MPP_RET dump_data_to_file(char *fname_path, void *data, RK_U32 data_bit_size,
+                          RK_U32 line_bits, RK_U32 big_end)
+{
+    RK_U8 *buf_p = (RK_U8 *)data;
+    RK_U8 cur_data;
+    RK_U32 i;
+    RK_U32 loop_cnt;
+    FILE *dump_fp = NULL;
+    char line_tmp[256];
+    RK_U32 str_idx = 0;
+
+    dump_fp = fopen(fname_path, "w+");
+    if (!dump_fp) {
+        mpp_err_f("open file: %s error!\n", fname_path);
+        return MPP_NOK;
+    }
+
+    if ((data_bit_size % 4 != 0) || (line_bits % 8 != 0)) {
+        mpp_err_f("line bits not align to 4!\n");
+        return MPP_NOK;
+    }
+
+    loop_cnt = data_bit_size / 8;
+    for (i = 0; i < loop_cnt; i++) {
+        cur_data = buf_p[i];
+
+        sprintf(&line_tmp[str_idx++], "%0x", cur_data & 0xf);
+        if ((i * 8 + 4) % line_bits == 0) {
+            line_tmp[str_idx++] = '\0';
+            str_idx = 0;
+            if (!big_end)
+                flip_string(line_tmp);
+            fprintf(dump_fp, "%s\n", line_tmp);
+        }
+        sprintf(&line_tmp[str_idx++], "%0x", (cur_data >> 4) & 0xf);
+        if ((i * 8 + 8) % line_bits == 0) {
+            line_tmp[str_idx++] = '\0';
+            str_idx = 0;
+            if (!big_end)
+                flip_string(line_tmp);
+            fprintf(dump_fp, "%s\n", line_tmp);
+        }
+    }
+
+    // last line
+    if (data_bit_size % 4) {
+        cur_data = buf_p[i];
+        sprintf(&line_tmp[str_idx++], "%0x", cur_data & 0xf);
+        if ((i * 8 + 8) % line_bits == 0) {
+            line_tmp[str_idx++] = '\0';
+            str_idx = 0;
+            if (!big_end)
+                flip_string(line_tmp);
+            fprintf(dump_fp, "%s\n", line_tmp);
+        }
+    }
+    if (data_bit_size % line_bits) {
+        loop_cnt = (line_bits - (data_bit_size % line_bits)) / 4;
+        for (i = 0; i < loop_cnt; i++)
+            sprintf(&line_tmp[str_idx++], "%0x", 0);
+        line_tmp[str_idx++] = '\0';
+        str_idx = 0;
+        if (!big_end)
+            flip_string(line_tmp);
+        fprintf(dump_fp, "%s\n", line_tmp);
+    }
+
+    fclose(dump_fp);
+
+    return MPP_OK;
+}
+#endif
\ No newline at end of file
diff --git a/mpp/hal/rkdec/vp9d/CMakeLists.txt b/mpp/hal/rkdec/vp9d/CMakeLists.txt
index 5f6e66d13..78a7699be 100644
--- a/mpp/hal/rkdec/vp9d/CMakeLists.txt
+++ b/mpp/hal/rkdec/vp9d/CMakeLists.txt
@@ -7,10 +7,11 @@ set(HAL_VP9D_SRC
     hal_vp9d_rkv.c
     hal_vp9d_vdpu34x.c
     hal_vp9d_vdpu382.c
+    hal_vp9d_vdpu383.c
     )
 
 add_library(hal_vp9d STATIC ${HAL_VP9D_SRC})
 
-target_link_libraries(hal_vp9d mpp_base)
+target_link_libraries(hal_vp9d mpp_base vdpu383_com)
 set_target_properties(hal_vp9d PROPERTIES FOLDER "mpp/hal")
 
diff --git a/mpp/hal/rkdec/vp9d/hal_vp9d_api.c b/mpp/hal/rkdec/vp9d/hal_vp9d_api.c
index ab0b0971d..e02039d78 100644
--- a/mpp/hal/rkdec/vp9d/hal_vp9d_api.c
+++ b/mpp/hal/rkdec/vp9d/hal_vp9d_api.c
@@ -26,6 +26,7 @@
 #include "hal_vp9d_rkv.h"
 #include "hal_vp9d_vdpu34x.h"
 #include "hal_vp9d_vdpu382.h"
+#include "hal_vp9d_vdpu383.h"
 
 RK_U32 hal_vp9d_debug = 0;
 
@@ -41,12 +42,17 @@ MPP_RET hal_vp9d_init(void *ctx, MppHalCfg *cfg)
         mpp_err("mpp_dev_init failed ret: %d\n", ret);
         return ret;
     }
+    cfg->hw_info = mpp_get_dec_hw_info_by_client_type(client_type);
+    p->hw_info = cfg->hw_info;
 
     hw_id = mpp_get_client_hw_id(client_type);
     p->dev = cfg->dev;
     p->hw_id = hw_id;
     p->client_type = client_type;
-    if (hw_id == HWID_VDPU382_RK3528 || hw_id == HWID_VDPU382_RK3562) {
+    if (hw_id == HWID_VDPU383) {
+        p->api = &hal_vp9d_vdpu383;
+        cfg->support_fast_mode = 1;
+    } else if (hw_id == HWID_VDPU382_RK3528 || hw_id == HWID_VDPU382_RK3562) {
         p->api = &hal_vp9d_vdpu382;
         cfg->support_fast_mode = 1;
     } else if (hw_id == HWID_VDPU34X || hw_id == HWID_VDPU38X) {
diff --git a/mpp/hal/rkdec/vp9d/hal_vp9d_com.c b/mpp/hal/rkdec/vp9d/hal_vp9d_com.c
index 571cccb97..96eabaf80 100644
--- a/mpp/hal/rkdec/vp9d/hal_vp9d_com.c
+++ b/mpp/hal/rkdec/vp9d/hal_vp9d_com.c
@@ -1449,7 +1449,6 @@ MPP_RET hal_vp9d_prob_flag_delta(void *buf, void *dxva)
 {
     RK_S32 i, j, k, m, n;
     RK_S32 fifo_len = PROB_SIZE >> 3;
-    RK_U64 *probe_packet = NULL;
     BitputCtx_t bp;
     DXVA_PicParams_VP9 *pic_param = (DXVA_PicParams_VP9*)dxva;
     RK_S32 intraFlag = (!pic_param->frame_type || pic_param->intra_only);
@@ -1468,9 +1467,7 @@ MPP_RET hal_vp9d_prob_flag_delta(void *buf, void *dxva)
         memcpy(partition_delta, prob_delta->partition, sizeof(partition_delta));
     }
 
-    probe_packet = mpp_calloc(RK_U64, fifo_len);
-    memset(probe_packet, 0, fifo_len);
-    mpp_set_bitput_ctx(&bp, probe_packet, fifo_len);
+    mpp_set_bitput_ctx(&bp, buf, fifo_len);
 
     if (intraFlag) { //intra probs
         //sb info  5 x 128 bit
@@ -1902,8 +1899,6 @@ MPP_RET hal_vp9d_prob_flag_delta(void *buf, void *dxva)
     }
     mpp_put_align(&bp, 128, 0);
 
-    memcpy(buf, probe_packet, fifo_len << 3);
-
 #if VP9_DUMP
     static RK_U32 file_cnt = 0;
     char file_name[128];
@@ -1917,11 +1912,56 @@ MPP_RET hal_vp9d_prob_flag_delta(void *buf, void *dxva)
     fflush(vp9_fp);
     fclose(vp9_fp);
 #endif
-    MPP_FREE(probe_packet);
 
     return 0;
 }
 
+MPP_RET hal_vp9d_prob_kf(void *buf)
+{
+    RK_S32 i, j, k, m;
+    RK_S32 fifo_len = PROB_KF_SIZE >> 3;
+    BitputCtx_t bp;
+
+    memset(buf, 0, PROB_KF_SIZE);
+    mpp_set_bitput_ctx(&bp, buf, fifo_len);
+
+    for (i = 0; i < 16; i++)//kf_partition_prob
+        for (j = 0; j < 3; j++)
+            mpp_put_bits(&bp, vp9_kf_partition_probs[i][j], 8);
+
+    //intra mode prob  80 x 128 bit, 10x 8x 128bit
+    for (i = 0; i < 10; i++) {
+        RK_S32 byte_count = 0;// 4x128 bit
+        RK_U8 val = 0;
+        for (j = 0; j < 10; j++)
+            for (k = 0; k < 9; k++) {
+                mpp_put_bits(&bp, vp9_kf_y_mode_prob[i][j][k], 8);
+                byte_count++;
+                if (byte_count == 27) {
+                    byte_count = 0;
+                    mpp_put_align(&bp, 128, 0);
+                }
+            }
+        // 6x128 bit, 23x4 bytes
+        if (i < 4) {
+            for (m = 0; m < (i < 3 ? 23 : 21); m++) {
+                val = ((RK_U8 *)(&vp9_kf_uv_mode_prob[0][0]))[i * 23 + m];
+                mpp_put_bits(&bp, val, 8);
+            }
+            for (; m < 23; m++)
+                mpp_put_bits(&bp, 0, 8);
+        } else {
+            for (m = 0; m < 23; m++)
+                mpp_put_bits(&bp, 0, 8);
+        }
+        mpp_put_align(&bp, 128, 0);
+    }
+
+    mpp_put_align(&bp, 128, 0);
+
+    return MPP_OK;
+}
+
 void hal_vp9d_update_counts(void *buf, void *dxva)
 {
     DXVA_PicParams_VP9 *s = (DXVA_PicParams_VP9*)dxva;
diff --git a/mpp/hal/rkdec/vp9d/hal_vp9d_com.h b/mpp/hal/rkdec/vp9d/hal_vp9d_com.h
index bfcd24109..8dee8e569 100644
--- a/mpp/hal/rkdec/vp9d/hal_vp9d_com.h
+++ b/mpp/hal/rkdec/vp9d/hal_vp9d_com.h
@@ -53,6 +53,7 @@ typedef RK_U8 vp9_prob;
 #define MV_FP_SIZE                      4
 
 #define PROB_SIZE                       4864
+#define PROB_KF_SIZE                    (82 * 16)
 #define COUNT_SIZE                      13208
 
 /*
@@ -91,6 +92,7 @@ MPP_RET hal_vp9d_output_probe(void *buf, void *dxva);
 MPP_RET hal_vp9d_prob_flag_delta(void *buf, void *dxva);
 void hal_vp9d_update_counts(void *buf, void *dxva);
 MPP_RET hal_vp9d_prob_default(void *buf, void *dxva);
+MPP_RET hal_vp9d_prob_kf(void *buf);
 
 #ifdef __cplusplus
 }
diff --git a/mpp/hal/rkdec/vp9d/hal_vp9d_ctx.h b/mpp/hal/rkdec/vp9d/hal_vp9d_ctx.h
index 7532dfcc3..a64dd8f42 100644
--- a/mpp/hal/rkdec/vp9d/hal_vp9d_ctx.h
+++ b/mpp/hal/rkdec/vp9d/hal_vp9d_ctx.h
@@ -34,10 +34,13 @@ typedef struct Vp9dLastInfo_t {
     RK_U32      last_height;
     RK_S16      feature_data[8][4];
     RK_U8       feature_mask[8];
+    RK_U8       color_space_last;
+    RK_U8       last_frame_type;
 } Vp9dLastInfo;
 
 typedef struct Vp9dRegBuf_t {
     RK_S32      use_flag;
+    MppBuffer   global_base;
     MppBuffer   probe_base;
     MppBuffer   count_base;
     MppBuffer   segid_cur_base;
diff --git a/mpp/hal/rkdec/vp9d/hal_vp9d_vdpu34x.c b/mpp/hal/rkdec/vp9d/hal_vp9d_vdpu34x.c
index ce0ea0d17..a0245d1cc 100644
--- a/mpp/hal/rkdec/vp9d/hal_vp9d_vdpu34x.c
+++ b/mpp/hal/rkdec/vp9d/hal_vp9d_vdpu34x.c
@@ -258,22 +258,6 @@ static MPP_RET hal_vp9d_vdpu34x_init(void *hal, MppHalCfg *cfg)
     }
 
     hw_ctx->last_segid_flag = 1;
-    {
-        // report hw_info to parser
-        const MppSocInfo *info = mpp_get_soc_info();
-        const void *hw_info = NULL;
-        RK_U32 i;
-
-        for (i = 0; i < MPP_ARRAY_ELEMS(info->dec_caps); i++) {
-            if (info->dec_caps[i] && info->dec_caps[i]->type == VPU_CLIENT_RKVDEC) {
-                hw_info = info->dec_caps[i];
-                break;
-            }
-        }
-
-        mpp_assert(hw_info);
-        cfg->hw_info = hw_info;
-    }
 
     if (cfg->hal_fbc_adj_cfg) {
         cfg->hal_fbc_adj_cfg->func = vdpu34x_afbc_align_calc;
@@ -393,6 +377,38 @@ static void hal_vp9d_rcb_info_update(void *hal,  Vdpu34xVp9dRegSet *hw_regs, voi
     }
 }
 
+static MPP_RET hal_vp9d_vdpu34x_setup_colmv_buf(void *hal, HalTaskInfo *task)
+{
+    HalVp9dCtx *p_hal = (HalVp9dCtx*)hal;
+    Vdpu34xVp9dCtx *hw_ctx = (Vdpu34xVp9dCtx*)p_hal->hw_ctx;
+    DXVA_PicParams_VP9 *pic_param = (DXVA_PicParams_VP9*)task->dec.syntax.data;
+    RK_U32 width = pic_param->width;
+    RK_U32 height = pic_param->height;
+    RK_S32 mv_size = 0, colmv_size = 8, colmv_byte = 16;
+    RK_U32 compress = p_hal->hw_info ? p_hal->hw_info->cap_colmv_compress : 1;
+
+    mv_size = vdpu34x_get_colmv_size(width, height, VP9_CTU_SIZE, colmv_byte, colmv_size, compress);
+    if (hw_ctx->cmv_bufs == NULL || hw_ctx->mv_size < mv_size) {
+        size_t size = mv_size;
+
+        if (hw_ctx->cmv_bufs) {
+            hal_bufs_deinit(hw_ctx->cmv_bufs);
+            hw_ctx->cmv_bufs = NULL;
+        }
+
+        hal_bufs_init(&hw_ctx->cmv_bufs);
+        if (hw_ctx->cmv_bufs == NULL) {
+            mpp_err_f("colmv bufs init fail");
+            return MPP_ERR_NOMEM;
+        }
+        hw_ctx->mv_size = mv_size;
+        hw_ctx->mv_count = mpp_buf_slot_get_count(p_hal ->slots);
+        hal_bufs_setup(hw_ctx->cmv_bufs, hw_ctx->mv_count, 1, &size);
+    }
+
+    return MPP_OK;
+}
+
 static MPP_RET hal_vp9d_vdpu34x_gen_regs(void *hal, HalTaskInfo *task)
 {
     RK_S32   i;
@@ -418,7 +434,6 @@ static MPP_RET hal_vp9d_vdpu34x_gen_regs(void *hal, HalTaskInfo *task)
     HalVp9dCtx *p_hal = (HalVp9dCtx*)hal;
     Vdpu34xVp9dCtx *hw_ctx = (Vdpu34xVp9dCtx*)p_hal->hw_ctx;
     DXVA_PicParams_VP9 *pic_param = (DXVA_PicParams_VP9*)task->dec.syntax.data;
-    RK_S32 mv_size = pic_param->width * pic_param->height / 2;
     RK_U32 frame_ctx_id = pic_param->frame_context_idx;
 
     if (p_hal->fast_mode) {
@@ -438,23 +453,8 @@ static MPP_RET hal_vp9d_vdpu34x_gen_regs(void *hal, HalTaskInfo *task)
         }
     }
 
-    if (hw_ctx->cmv_bufs == NULL || hw_ctx->mv_size < mv_size) {
-        size_t size = mv_size;
-
-        if (hw_ctx->cmv_bufs) {
-            hal_bufs_deinit(hw_ctx->cmv_bufs);
-            hw_ctx->cmv_bufs = NULL;
-        }
-
-        hal_bufs_init(&hw_ctx->cmv_bufs);
-        if (hw_ctx->cmv_bufs == NULL) {
-            mpp_err_f("colmv bufs init fail");
-            return MPP_NOK;
-        }
-        hw_ctx->mv_size = mv_size;
-        hw_ctx->mv_count = mpp_buf_slot_get_count(p_hal ->slots);
-        hal_bufs_setup(hw_ctx->cmv_bufs, hw_ctx->mv_count, 1, &size);
-    }
+    if (hal_vp9d_vdpu34x_setup_colmv_buf(hal, task))
+        return MPP_ERR_NOMEM;
 
     Vdpu34xVp9dRegSet *vp9_hw_regs = (Vdpu34xVp9dRegSet*)hw_ctx->hw_regs;
     intraFlag = (!pic_param->frame_type || pic_param->intra_only);
@@ -607,6 +607,7 @@ static MPP_RET hal_vp9d_vdpu34x_gen_regs(void *hal, HalTaskInfo *task)
     hal_vp9d_output_probe(mpp_buffer_get_ptr(hw_ctx->probe_base), task->dec.syntax.data);
     mpp_buffer_sync_end(hw_ctx->probe_base);
 #endif
+    vp9_hw_regs->common.reg012.colmv_compress_en = p_hal->hw_info ? p_hal->hw_info->cap_colmv_compress : 1;
     vp9_hw_regs->common.reg013.cur_pic_is_idr = !pic_param->frame_type;
     vp9_hw_regs->common.reg009.dec_mode = 2; //set as vp9 dec
     vp9_hw_regs->common.reg016_str_len = ((stream_len + 15) & (~15)) + 0x80;
@@ -1065,16 +1066,12 @@ static MPP_RET hal_vp9d_vdpu34x_control(void *hal, MpiCmd cmd_type, void *param)
 
     switch ((MpiCmd)cmd_type) {
     case MPP_DEC_SET_FRAME_INFO : {
-        /* commit buffer stride */
-        RK_U32 width = mpp_frame_get_width((MppFrame)param);
-        RK_U32 height = mpp_frame_get_height((MppFrame)param);
         MppFrameFormat fmt = mpp_frame_get_fmt((MppFrame)param);
 
         if (MPP_FRAME_FMT_IS_FBC(fmt)) {
             vdpu34x_afbc_align_calc(p_hal->slots, (MppFrame)param, 0);
         } else {
-            mpp_frame_set_hor_stride((MppFrame)param, vp9_hor_align(width));
-            mpp_frame_set_ver_stride((MppFrame)param, vp9_ver_align(height));
+            mpp_slots_set_prop(p_hal->slots, SLOTS_HOR_ALIGN, vp9_hor_align);
         }
     } break;
     default : {
diff --git a/mpp/hal/rkdec/vp9d/hal_vp9d_vdpu382.c b/mpp/hal/rkdec/vp9d/hal_vp9d_vdpu382.c
index b082a2f5e..da3ba195a 100644
--- a/mpp/hal/rkdec/vp9d/hal_vp9d_vdpu382.c
+++ b/mpp/hal/rkdec/vp9d/hal_vp9d_vdpu382.c
@@ -259,23 +259,6 @@ static MPP_RET hal_vp9d_vdpu382_init(void *hal, MppHalCfg *cfg)
     }
 
     hw_ctx->last_segid_flag = 1;
-    {
-        // report hw_info to parser
-        const MppSocInfo *info = mpp_get_soc_info();
-        const void *hw_info = NULL;
-        RK_U32 i;
-
-        for (i = 0; i < MPP_ARRAY_ELEMS(info->dec_caps); i++) {
-            if (info->dec_caps[i] && info->dec_caps[i]->type == VPU_CLIENT_RKVDEC) {
-                hw_info = info->dec_caps[i];
-                break;
-            }
-        }
-
-        mpp_assert(hw_info);
-        cfg->hw_info = hw_info;
-        p_hal->hw_info = hw_info;
-    }
 
     if (cfg->hal_fbc_adj_cfg) {
         cfg->hal_fbc_adj_cfg->func = vdpu382_afbc_align_calc;
@@ -406,6 +389,39 @@ static void hal_vp9d_rcb_info_update(void *hal,  Vdpu382Vp9dRegSet *hw_regs, voi
     }
 }
 
+
+static MPP_RET hal_vp9d_vdpu382_setup_colmv_buf(void *hal, HalTaskInfo *task)
+{
+    HalVp9dCtx *p_hal = (HalVp9dCtx*)hal;
+    Vdpu382Vp9dCtx *hw_ctx = (Vdpu382Vp9dCtx*)p_hal->hw_ctx;
+    DXVA_PicParams_VP9 *pic_param = (DXVA_PicParams_VP9*)task->dec.syntax.data;
+    RK_U32 width = pic_param->width;
+    RK_U32 height = pic_param->height;
+    RK_S32 mv_size = 0, colmv_size = 8, colmv_byte = 16;
+    RK_U32 compress = p_hal->hw_info ? p_hal->hw_info->cap_colmv_compress : 1;
+
+    mv_size = vdpu382_get_colmv_size(width, height, VP9_CTU_SIZE, colmv_byte, colmv_size, compress);
+    if (hw_ctx->cmv_bufs == NULL || hw_ctx->mv_size < mv_size) {
+        size_t size = mv_size;
+
+        if (hw_ctx->cmv_bufs) {
+            hal_bufs_deinit(hw_ctx->cmv_bufs);
+            hw_ctx->cmv_bufs = NULL;
+        }
+
+        hal_bufs_init(&hw_ctx->cmv_bufs);
+        if (hw_ctx->cmv_bufs == NULL) {
+            mpp_err_f("colmv bufs init fail");
+            return MPP_ERR_NOMEM;
+        }
+        hw_ctx->mv_size = mv_size;
+        hw_ctx->mv_count = mpp_buf_slot_get_count(p_hal ->slots);
+        hal_bufs_setup(hw_ctx->cmv_bufs, hw_ctx->mv_count, 1, &size);
+    }
+
+    return MPP_OK;
+}
+
 static MPP_RET hal_vp9d_vdpu382_gen_regs(void *hal, HalTaskInfo *task)
 {
     RK_S32   i;
@@ -431,7 +447,6 @@ static MPP_RET hal_vp9d_vdpu382_gen_regs(void *hal, HalTaskInfo *task)
     HalVp9dCtx *p_hal = (HalVp9dCtx*)hal;
     Vdpu382Vp9dCtx *hw_ctx = (Vdpu382Vp9dCtx*)p_hal->hw_ctx;
     DXVA_PicParams_VP9 *pic_param = (DXVA_PicParams_VP9*)task->dec.syntax.data;
-    RK_S32 mv_size = pic_param->width * pic_param->height / 2;
     RK_U32 frame_ctx_id = pic_param->frame_context_idx;
 
     if (p_hal->fast_mode) {
@@ -451,23 +466,8 @@ static MPP_RET hal_vp9d_vdpu382_gen_regs(void *hal, HalTaskInfo *task)
         }
     }
 
-    if (hw_ctx->cmv_bufs == NULL || hw_ctx->mv_size < mv_size) {
-        size_t size = mv_size;
-
-        if (hw_ctx->cmv_bufs) {
-            hal_bufs_deinit(hw_ctx->cmv_bufs);
-            hw_ctx->cmv_bufs = NULL;
-        }
-
-        hal_bufs_init(&hw_ctx->cmv_bufs);
-        if (hw_ctx->cmv_bufs == NULL) {
-            mpp_err_f("colmv bufs init fail");
-            return MPP_NOK;
-        }
-        hw_ctx->mv_size = mv_size;
-        hw_ctx->mv_count = mpp_buf_slot_get_count(p_hal ->slots);
-        hal_bufs_setup(hw_ctx->cmv_bufs, hw_ctx->mv_count, 1, &size);
-    }
+    if (hal_vp9d_vdpu382_setup_colmv_buf(hal, task))
+        return MPP_ERR_NOMEM;
 
     Vdpu382Vp9dRegSet *vp9_hw_regs = (Vdpu382Vp9dRegSet*)hw_ctx->hw_regs;
     intraFlag = (!pic_param->frame_type || pic_param->intra_only);
@@ -617,6 +617,7 @@ static MPP_RET hal_vp9d_vdpu382_gen_regs(void *hal, HalTaskInfo *task)
     hal_vp9d_output_probe(mpp_buffer_get_ptr(hw_ctx->probe_base), task->dec.syntax.data);
     mpp_buffer_sync_end(hw_ctx->probe_base);
 #endif
+    vp9_hw_regs->common.reg012.colmv_compress_en = p_hal->hw_info ? p_hal->hw_info->cap_colmv_compress : 1;
     vp9_hw_regs->common.reg013.cur_pic_is_idr = !pic_param->frame_type;
     vp9_hw_regs->common.reg009.dec_mode = 2; //set as vp9 dec
     vp9_hw_regs->common.reg016_str_len = ((stream_len + 15) & (~15)) + 0x80;
@@ -1097,16 +1098,12 @@ static MPP_RET hal_vp9d_vdpu382_control(void *hal, MpiCmd cmd_type, void *param)
 
     switch ((MpiCmd)cmd_type) {
     case MPP_DEC_SET_FRAME_INFO : {
-        /* commit buffer stride */
-        RK_U32 width = mpp_frame_get_width((MppFrame)param);
-        RK_U32 height = mpp_frame_get_height((MppFrame)param);
         MppFrameFormat fmt = mpp_frame_get_fmt((MppFrame)param);
 
         if (MPP_FRAME_FMT_IS_FBC(fmt)) {
             vdpu382_afbc_align_calc(p_hal->slots, (MppFrame)param, 0);
         } else {
-            mpp_frame_set_hor_stride((MppFrame)param, vp9_hor_align(width));
-            mpp_frame_set_ver_stride((MppFrame)param, vp9_ver_align(height));
+            mpp_slots_set_prop(p_hal->slots, SLOTS_HOR_ALIGN, vp9_hor_align);
         }
     } break;
     default : {
diff --git a/mpp/hal/rkdec/vp9d/hal_vp9d_vdpu383.c b/mpp/hal/rkdec/vp9d/hal_vp9d_vdpu383.c
new file mode 100644
index 000000000..b400e59e1
--- /dev/null
+++ b/mpp/hal/rkdec/vp9d/hal_vp9d_vdpu383.c
@@ -0,0 +1,1355 @@
+/* SPDX-License-Identifier: Apache-2.0 OR MIT */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#define MODULE_TAG "hal_vp9d_vdpu383"
+
+#include <string.h>
+
+#include "mpp_debug.h"
+#include "mpp_env.h"
+#include "mpp_mem.h"
+#include "mpp_common.h"
+#include "mpp_buffer_impl.h"
+#include "mpp_bitput.h"
+
+#include "hal_vp9d_debug.h"
+#include "hal_vp9d_com.h"
+#include "hal_vp9d_vdpu383.h"
+#include "hal_vp9d_ctx.h"
+#include "vdpu383_vp9d.h"
+#include "vp9d_syntax.h"
+
+#define HW_PROB         1
+#define VP9_CONTEXT     4
+#define VP9_CTU_SIZE    64
+
+#define GBL_SIZE        2 * (MPP_ALIGN(1299, 128) / 8)
+
+#define EIGHTTAP        0
+#define EIGHTTAP_SMOOTH 1
+#define EIGHTTAP_SHARP  2
+#define BILINEAR        3
+
+const RK_U8 literal_to_filter[] = { EIGHTTAP_SMOOTH, EIGHTTAP,
+                                    EIGHTTAP_SHARP, BILINEAR
+                                  };
+
+typedef struct Vdpu383Vp9dCtx_t {
+    Vp9dRegBuf      g_buf[MAX_GEN_REG];
+    MppBuffer       global_base;
+    MppBuffer       probe_base;
+    MppBuffer       count_base;
+    MppBuffer       segid_cur_base;
+    MppBuffer       segid_last_base;
+    MppBuffer       prob_default_base;
+    void*           hw_regs;
+    RK_S32          mv_base_addr;
+    RK_S32          pre_mv_base_addr;
+    Vp9dLastInfo    ls_info;
+    /*
+     * swap between segid_cur_base & segid_last_base
+     * 0  used segid_cur_base as last
+     * 1  used segid_last_base as
+     */
+    RK_U32          last_segid_flag;
+    RK_S32          width;
+    RK_S32          height;
+    /* rcb buffers info */
+    RK_S32          rcb_buf_size;
+    Vdpu383RcbInfo  rcb_info[RCB_BUF_COUNT];
+    MppBuffer       rcb_buf;
+    RK_U32          num_row_tiles;
+    RK_U32          bit_depth;
+    /* colmv buffers info */
+    HalBufs         cmv_bufs;
+    RK_S32          mv_size;
+    RK_S32          mv_count;
+    HalBufs         origin_bufs;
+    RK_U32          prob_ctx_valid[VP9_CONTEXT];
+    MppBuffer       prob_loop_base[VP9_CONTEXT];
+    /* uncompress header data */
+    RK_U8           header_data[168];
+} Vdpu383Vp9dCtx;
+
+#ifdef DUMP_VDPU383_DATAS
+static RK_U32 cur_last_segid_flag;
+static MppBuffer cur_last_prob_base;
+#endif
+
+static MPP_RET vdpu383_setup_scale_origin_bufs(Vdpu383Vp9dCtx *ctx, MppFrame mframe)
+{
+    /* for 8K FrameBuf scale mode */
+    size_t origin_buf_size = 0;
+
+    origin_buf_size = mpp_frame_get_buf_size(mframe);
+
+    if (!origin_buf_size) {
+        mpp_err_f("origin_bufs get buf size failed\n");
+        return MPP_NOK;
+    }
+    if (ctx->origin_bufs) {
+        hal_bufs_deinit(ctx->origin_bufs);
+        ctx->origin_bufs = NULL;
+    }
+    hal_bufs_init(&ctx->origin_bufs);
+    if (!ctx->origin_bufs) {
+        mpp_err_f("origin_bufs thumb init fail\n");
+        return MPP_ERR_NOMEM;
+    }
+    hal_bufs_setup(ctx->origin_bufs, 16, 1, &origin_buf_size);
+
+    return MPP_OK;
+}
+static MPP_RET hal_vp9d_alloc_res(HalVp9dCtx *hal)
+{
+    HalVp9dCtx *p_hal = (HalVp9dCtx*)hal;
+    Vdpu383Vp9dCtx *hw_ctx = (Vdpu383Vp9dCtx*)p_hal->hw_ctx;
+    RK_S32 ret = 0;
+    RK_S32 i = 0;
+
+    /* alloc common buffer */
+    for (i = 0; i < VP9_CONTEXT; i++) {
+        ret = mpp_buffer_get(p_hal->group, &hw_ctx->prob_loop_base[i], PROB_SIZE);
+        if (ret) {
+            mpp_err("vp9 probe_loop_base get buffer failed\n");
+            return ret;
+        }
+        mpp_buffer_attach_dev(hw_ctx->prob_loop_base[i], p_hal->dev);
+    }
+    ret = mpp_buffer_get(p_hal->group, &hw_ctx->prob_default_base, PROB_SIZE);
+    if (ret) {
+        mpp_err("vp9 probe_default_base get buffer failed\n");
+        return ret;
+    }
+    mpp_buffer_attach_dev(hw_ctx->prob_default_base, p_hal->dev);
+
+    ret = mpp_buffer_get(p_hal->group, &hw_ctx->segid_cur_base, MAX_SEGMAP_SIZE);
+    if (ret) {
+        mpp_err("vp9 segid_cur_base get buffer failed\n");
+        return ret;
+    }
+    mpp_buffer_attach_dev(hw_ctx->segid_cur_base, p_hal->dev);
+    ret = mpp_buffer_get(p_hal->group, &hw_ctx->segid_last_base, MAX_SEGMAP_SIZE);
+    if (ret) {
+        mpp_err("vp9 segid_last_base get buffer failed\n");
+        return ret;
+    }
+    mpp_buffer_attach_dev(hw_ctx->segid_last_base, p_hal->dev);
+
+    /* alloc buffer for fast mode or normal */
+    if (p_hal->fast_mode) {
+        for (i = 0; i < MAX_GEN_REG; i++) {
+            hw_ctx->g_buf[i].hw_regs = mpp_calloc_size(void, sizeof(Vdpu383Vp9dRegSet));
+            ret = mpp_buffer_get(p_hal->group,
+                                 &hw_ctx->g_buf[i].global_base, GBL_SIZE);
+            mpp_buffer_attach_dev(hw_ctx->g_buf[i].global_base, p_hal->dev);
+            if (ret) {
+                mpp_err("vp9 global_base get buffer failed\n");
+                return ret;
+            }
+            ret = mpp_buffer_get(p_hal->group,
+                                 &hw_ctx->g_buf[i].probe_base, PROB_KF_SIZE);
+            if (ret) {
+                mpp_err("vp9 probe_base get buffer failed\n");
+                return ret;
+            }
+            mpp_buffer_attach_dev(hw_ctx->g_buf[i].probe_base, p_hal->dev);
+            ret = mpp_buffer_get(p_hal->group,
+                                 &hw_ctx->g_buf[i].count_base, COUNT_SIZE);
+            if (ret) {
+                mpp_err("vp9 count_base get buffer failed\n");
+                return ret;
+            }
+            mpp_buffer_attach_dev(hw_ctx->g_buf[i].count_base, p_hal->dev);
+        }
+    } else {
+        hw_ctx->hw_regs = mpp_calloc_size(void, sizeof(Vdpu383Vp9dRegSet));
+        ret = mpp_buffer_get(p_hal->group, &hw_ctx->global_base, PROB_SIZE);
+        if (ret) {
+            mpp_err("vp9 global_base get buffer failed\n");
+            return ret;
+        }
+        mpp_buffer_attach_dev(hw_ctx->global_base, p_hal->dev);
+
+        ret = mpp_buffer_get(p_hal->group, &hw_ctx->probe_base, PROB_KF_SIZE);
+        if (ret) {
+            mpp_err("vp9 probe_base get buffer failed\n");
+            return ret;
+        }
+        mpp_buffer_attach_dev(hw_ctx->probe_base, p_hal->dev);
+
+        ret = mpp_buffer_get(p_hal->group, &hw_ctx->count_base, COUNT_SIZE);
+        if (ret) {
+            mpp_err("vp9 count_base get buffer failed\n");
+            return ret;
+        }
+        mpp_buffer_attach_dev(hw_ctx->count_base, p_hal->dev);
+    }
+    return MPP_OK;
+}
+
+static MPP_RET hal_vp9d_release_res(HalVp9dCtx *hal)
+{
+    HalVp9dCtx *p_hal = (HalVp9dCtx*)hal;
+    Vdpu383Vp9dCtx *hw_ctx = (Vdpu383Vp9dCtx*)p_hal->hw_ctx;
+    RK_S32 ret = 0;
+    RK_S32 i = 0;
+
+    if (hw_ctx->prob_default_base) {
+        ret = mpp_buffer_put(hw_ctx->prob_default_base);
+        if (ret) {
+            mpp_err("vp9 probe_wr_base get buffer failed\n");
+            return ret;
+        }
+    }
+    if (hw_ctx->segid_cur_base) {
+        ret = mpp_buffer_put(hw_ctx->segid_cur_base);
+        if (ret) {
+            mpp_err("vp9 segid_cur_base put buffer failed\n");
+            return ret;
+        }
+    }
+    if (hw_ctx->segid_last_base) {
+        ret = mpp_buffer_put(hw_ctx->segid_last_base);
+        if (ret) {
+            mpp_err("vp9 segid_last_base put buffer failed\n");
+            return ret;
+        }
+    }
+    for (i = 0; i < VP9_CONTEXT; i++) {
+        if (hw_ctx->prob_loop_base[i]) {
+            ret = mpp_buffer_put(hw_ctx->prob_loop_base[i]);
+            if (ret) {
+                mpp_err("vp9 prob_loop_base put buffer failed\n");
+                return ret;
+            }
+        }
+    }
+    if (p_hal->fast_mode) {
+        for (i = 0; i < MAX_GEN_REG; i++) {
+            if (hw_ctx->g_buf[i].global_base) {
+                ret = mpp_buffer_put(hw_ctx->g_buf[i].global_base);
+                if (ret) {
+                    mpp_err("vp9 global_base put buffer failed\n");
+                    return ret;
+                }
+            }
+            if (hw_ctx->g_buf[i].probe_base) {
+                ret = mpp_buffer_put(hw_ctx->g_buf[i].probe_base);
+                if (ret) {
+                    mpp_err("vp9 probe_base put buffer failed\n");
+                    return ret;
+                }
+            }
+            if (hw_ctx->g_buf[i].count_base) {
+                ret = mpp_buffer_put(hw_ctx->g_buf[i].count_base);
+                if (ret) {
+                    mpp_err("vp9 count_base put buffer failed\n");
+                    return ret;
+                }
+            }
+            if (hw_ctx->g_buf[i].hw_regs) {
+                mpp_free(hw_ctx->g_buf[i].hw_regs);
+                hw_ctx->g_buf[i].hw_regs = NULL;
+            }
+            if (hw_ctx->g_buf[i].rcb_buf) {
+                ret = mpp_buffer_put(hw_ctx->g_buf[i].rcb_buf);
+                if (ret) {
+                    mpp_err("vp9 rcb_buf[%d] put buffer failed\n", i);
+                    return ret;
+                }
+            }
+        }
+    } else {
+        if (hw_ctx->global_base) {
+            ret = mpp_buffer_put(hw_ctx->global_base);
+            if (ret) {
+                mpp_err("vp9 global_base get buffer failed\n");
+                return ret;
+            }
+        }
+        if (hw_ctx->probe_base) {
+            ret = mpp_buffer_put(hw_ctx->probe_base);
+            if (ret) {
+                mpp_err("vp9 probe_base get buffer failed\n");
+                return ret;
+            }
+        }
+        if (hw_ctx->count_base) {
+            ret = mpp_buffer_put(hw_ctx->count_base);
+            if (ret) {
+                mpp_err("vp9 count_base put buffer failed\n");
+                return ret;
+            }
+        }
+        if (hw_ctx->hw_regs) {
+            mpp_free(hw_ctx->hw_regs);
+            hw_ctx->hw_regs = NULL;
+        }
+        if (hw_ctx->rcb_buf) {
+            ret = mpp_buffer_put(hw_ctx->rcb_buf);
+            if (ret) {
+                mpp_err("vp9 rcb_buf put buffer failed\n");
+                return ret;
+            }
+        }
+    }
+
+    if (hw_ctx->cmv_bufs) {
+        ret = hal_bufs_deinit(hw_ctx->cmv_bufs);
+        if (ret) {
+            mpp_err("vp9 cmv bufs deinit buffer failed\n");
+            return ret;
+        }
+    }
+    if (hw_ctx->origin_bufs) {
+        ret = hal_bufs_deinit(hw_ctx->origin_bufs);
+        if (ret) {
+            mpp_err("thumb vp9 origin_bufs deinit buffer failed\n");
+            return ret;
+        }
+        hw_ctx->origin_bufs = NULL;
+    }
+
+    return MPP_OK;
+}
+
+static MPP_RET hal_vp9d_vdpu383_deinit(void *hal)
+{
+    HalVp9dCtx *p_hal = (HalVp9dCtx *)hal;
+    MPP_RET ret = MPP_OK;
+
+    hal_vp9d_release_res(p_hal);
+
+    if (p_hal->group) {
+        ret = mpp_buffer_group_put(p_hal->group);
+        if (ret) {
+            mpp_err("vp9d group free buffer failed\n");
+            return ret;
+        }
+    }
+    MPP_FREE(p_hal->hw_ctx);
+
+    return ret;
+}
+
+static MPP_RET hal_vp9d_vdpu383_init(void *hal, MppHalCfg *cfg)
+{
+    MPP_RET ret = MPP_OK;
+    HalVp9dCtx *p_hal = (HalVp9dCtx*)hal;
+    MEM_CHECK(ret, p_hal->hw_ctx = mpp_calloc_size(void, sizeof(Vdpu383Vp9dCtx)));
+    Vdpu383Vp9dCtx *hw_ctx = (Vdpu383Vp9dCtx*)p_hal->hw_ctx;
+    (void) cfg;
+
+    hw_ctx->mv_base_addr = -1;
+    hw_ctx->pre_mv_base_addr = -1;
+    mpp_slots_set_prop(p_hal->slots, SLOTS_HOR_ALIGN, mpp_align_128_odd_plus_64);
+    mpp_slots_set_prop(p_hal->slots, SLOTS_VER_ALIGN, vp9_ver_align);
+
+    if (p_hal->group == NULL) {
+        ret = mpp_buffer_group_get_internal(&p_hal->group, MPP_BUFFER_TYPE_ION);
+        if (ret) {
+            mpp_err("vp9 mpp_buffer_group_get failed\n");
+            goto __FAILED;
+        }
+    }
+
+    ret = hal_vp9d_alloc_res(p_hal);
+    if (ret) {
+        mpp_err("hal_vp9d_alloc_res failed\n");
+        goto __FAILED;
+    }
+
+    hw_ctx->last_segid_flag = 1;
+
+    return ret;
+__FAILED:
+    hal_vp9d_vdpu383_deinit(hal);
+    return ret;
+}
+
+static void vp9d_refine_rcb_size(Vdpu383RcbInfo *rcb_info,
+                                 RK_S32 width, RK_S32 height, void* data)
+{
+    RK_U32 rcb_bits = 0;
+    DXVA_PicParams_VP9 *pic_param = (DXVA_PicParams_VP9*)data;
+    RK_U32 tile_row_num = 1 << pic_param->log2_tile_rows;
+    RK_U32 tile_col_num = 1 << pic_param->log2_tile_cols;
+    RK_U32 bit_depth = pic_param->BitDepthMinus8Luma + 8;
+    RK_U32 ext_row_align_size = tile_row_num * 64 * 8;
+    RK_U32 ext_col_align_size = tile_col_num * 64 * 8;
+    RK_U32 filterd_row_append = 8192;
+
+    width = MPP_ALIGN(width, VP9_CTU_SIZE);
+    height = MPP_ALIGN(height, VP9_CTU_SIZE);
+    /* RCB_STRMD_ROW && RCB_STRMD_TILE_ROW*/
+    if (width > 4096)
+        rcb_bits = ((width + 63) / 64) * 250;
+    else
+        rcb_bits = 0;
+    rcb_info[RCB_STRMD_ROW].size = 0;
+    rcb_info[RCB_STRMD_TILE_ROW].size = MPP_RCB_BYTES(rcb_bits);
+
+    /* RCB_INTER_ROW && RCB_INTER_TILE_ROW*/
+    rcb_bits = ((width + 63) / 64) * 2368;
+    rcb_info[RCB_INTER_ROW].size = MPP_RCB_BYTES(rcb_bits);
+    rcb_bits += ext_row_align_size;
+    if (tile_row_num > 1)
+        rcb_info[RCB_INTER_TILE_ROW].size = MPP_RCB_BYTES(rcb_bits);
+    else
+        rcb_info[RCB_INTER_TILE_ROW].size = 0;
+
+    /* RCB_INTRA_ROW && RCB_INTRA_TILE_ROW*/
+    rcb_bits = MPP_ALIGN(width, 512) * (bit_depth + 2);
+    rcb_bits = rcb_bits * 3; //TODO:
+    rcb_info[RCB_INTRA_ROW].size = MPP_RCB_BYTES(rcb_bits);
+    rcb_bits += ext_row_align_size;
+    if (tile_row_num > 1)
+        rcb_info[RCB_INTRA_TILE_ROW].size = MPP_RCB_BYTES(rcb_bits);
+    else
+        rcb_info[RCB_INTRA_TILE_ROW].size = 0;
+
+    /* RCB_FILTERD_ROW && RCB_FILTERD_TILE_ROW*/
+    // save space mode : half for RCB_FILTERD_ROW, half for RCB_FILTERD_PROTECT_ROW
+    if (width > 4096)
+        filterd_row_append = 27648;
+    rcb_bits = (RK_U32)(MPP_ALIGN(width, 64) * (41 * bit_depth + 13));
+    rcb_info[RCB_FILTERD_ROW].size = MPP_RCB_BYTES(rcb_bits / 2);
+    rcb_info[RCB_FILTERD_PROTECT_ROW].size = filterd_row_append + MPP_RCB_BYTES(rcb_bits / 2);
+    rcb_bits += ext_row_align_size;
+    if (tile_row_num > 1)
+        rcb_info[RCB_FILTERD_TILE_ROW].size = MPP_RCB_BYTES(rcb_bits);
+    else
+        rcb_info[RCB_FILTERD_TILE_ROW].size = 0;
+
+    /* RCB_FILTERD_TILE_COL */
+    if (tile_col_num > 1) {
+        rcb_bits = (RK_U32)(MPP_ALIGN(height, 64) * (42 * bit_depth + 13)) + ext_col_align_size;
+        rcb_info[RCB_FILTERD_TILE_COL].size = MPP_RCB_BYTES(rcb_bits);
+    } else {
+        rcb_info[RCB_FILTERD_TILE_COL].size = 0;
+    }
+
+}
+
+static void hal_vp9d_rcb_info_update(void *hal, Vdpu383Vp9dRegSet *hw_regs, void *data)
+{
+    HalVp9dCtx *p_hal = (HalVp9dCtx*)hal;
+    Vdpu383Vp9dCtx *hw_ctx = (Vdpu383Vp9dCtx*)p_hal->hw_ctx;
+    DXVA_PicParams_VP9 *pic_param = (DXVA_PicParams_VP9*)data;
+    RK_U32 num_tiles = pic_param->log2_tile_rows;
+    RK_U32 bit_depth = pic_param->BitDepthMinus8Luma + 8;
+    RK_S32 height = vp9_ver_align(pic_param->height);
+    RK_S32 width  = vp9_ver_align(pic_param->width);
+    (void) hw_regs;
+
+    if (hw_ctx->num_row_tiles != num_tiles ||
+        hw_ctx->bit_depth != bit_depth ||
+        hw_ctx->width != width ||
+        hw_ctx->height != height) {
+
+        hw_ctx->rcb_buf_size = vdpu383_get_rcb_buf_size(hw_ctx->rcb_info, width, height);
+        // TODO: refine rcb buffer size
+        vp9d_refine_rcb_size(hw_ctx->rcb_info, width, height, pic_param);
+
+        if (p_hal->fast_mode) {
+            RK_U32 i;
+
+            for (i = 0; i < MPP_ARRAY_ELEMS(hw_ctx->g_buf); i++) {
+                MppBuffer rcb_buf = hw_ctx->g_buf[i].rcb_buf;
+
+                if (rcb_buf) {
+                    mpp_buffer_put(rcb_buf);
+                    hw_ctx->g_buf[i].rcb_buf = NULL;
+                }
+                mpp_buffer_get(p_hal->group, &rcb_buf, hw_ctx->rcb_buf_size);
+                hw_ctx->g_buf[i].rcb_buf = rcb_buf;
+            }
+        } else {
+            MppBuffer rcb_buf = hw_ctx->rcb_buf;
+
+            if (rcb_buf) {
+                mpp_buffer_put(rcb_buf);
+                rcb_buf = NULL;
+            }
+            mpp_buffer_get(p_hal->group, &rcb_buf, hw_ctx->rcb_buf_size);
+            hw_ctx->rcb_buf = rcb_buf;
+        }
+
+        hw_ctx->num_row_tiles  = num_tiles;
+        hw_ctx->bit_depth      = bit_depth;
+        hw_ctx->width          = width;
+        hw_ctx->height         = height;
+    }
+}
+
+static void
+set_tile_offset(RK_S32 *start, RK_S32 *end, RK_S32 idx, RK_S32 log2_n, RK_S32 n)
+{
+    RK_S32 sb_start = ( idx      * n) >> log2_n;
+    RK_S32 sb_end   = ((idx + 1) * n) >> log2_n;
+
+    *start = MPP_MIN(sb_start, n) << 3;
+    *end   = MPP_MIN(sb_end,   n) << 3;
+}
+
+static MPP_RET prepare_uncompress_header(HalVp9dCtx *p_hal, DXVA_PicParams_VP9 *pp,
+                                         RK_U64 *data, RK_U32 len)
+{
+    Vdpu383Vp9dCtx *hw_ctx = (Vdpu383Vp9dCtx*)p_hal->hw_ctx;
+    BitputCtx_t bp;
+    RK_S32 i, j;
+
+    mpp_set_bitput_ctx(&bp, data, len);
+
+    mpp_put_bits(&bp, pp->frame_type, 1);
+    mpp_put_bits(&bp, pp->error_resilient_mode, 1);
+    mpp_put_bits(&bp, pp->BitDepthMinus8Luma, 3);
+    mpp_put_bits(&bp, 1, 2); // yuv420
+    mpp_put_bits(&bp, pp->width, 16);
+    mpp_put_bits(&bp, pp->height, 16);
+
+    mpp_put_bits(&bp, (!pp->frame_type || pp->intra_only), 1);
+    mpp_put_bits(&bp, pp->ref_frame_sign_bias[1], 1);
+    mpp_put_bits(&bp, pp->ref_frame_sign_bias[2], 1);
+    mpp_put_bits(&bp, pp->ref_frame_sign_bias[3], 1);
+
+    mpp_put_bits(&bp, pp->allow_high_precision_mv, 1);
+    /* sync with cmodel */
+    if (!pp->frame_type || pp->intra_only)
+        mpp_put_bits(&bp, 0, 3);
+    else {
+        if (pp->interp_filter == 4) /* FILTER_SWITCHABLE */
+            mpp_put_bits(&bp, pp->interp_filter, 3);
+        else
+            mpp_put_bits(&bp, literal_to_filter[pp->interp_filter], 3);
+    }
+    mpp_put_bits(&bp, pp->parallelmode, 1);
+    mpp_put_bits(&bp, pp->refresh_frame_context, 1);
+
+    /* loop filter */
+    mpp_put_bits(&bp, pp->filter_level, 6);
+    mpp_put_bits(&bp, pp->sharpness_level, 3);
+    mpp_put_bits(&bp, pp->mode_ref_delta_enabled, 1);
+    mpp_put_bits(&bp, pp->mode_ref_delta_update, 1);
+
+    mpp_put_bits(&bp, pp->ref_deltas[0], 7);
+    mpp_put_bits(&bp, pp->ref_deltas[1], 7);
+    mpp_put_bits(&bp, pp->ref_deltas[2], 7);
+    mpp_put_bits(&bp, pp->ref_deltas[3], 7);
+    mpp_put_bits(&bp, pp->mode_deltas[0], 7);
+    mpp_put_bits(&bp, pp->mode_deltas[1], 7);
+
+    mpp_put_bits(&bp, pp->base_qindex, 8);
+    mpp_put_bits(&bp, pp->y_dc_delta_q, 5);
+    mpp_put_bits(&bp, pp->uv_dc_delta_q, 5);
+    mpp_put_bits(&bp, pp->uv_ac_delta_q, 5);
+    mpp_put_bits(&bp, (!pp->base_qindex && !pp->y_dc_delta_q && !pp->uv_dc_delta_q && !pp->uv_ac_delta_q), 1);
+
+    for (i = 0; i < 3; i++) {
+        mpp_put_bits(&bp, pp->stVP9Segments.pred_probs[i], 8);
+    }
+    for (i = 0; i < 7; i++) {
+        mpp_put_bits(&bp, pp->stVP9Segments.tree_probs[i], 8);
+    }
+    mpp_put_bits(&bp, pp->stVP9Segments.enabled, 1);
+    mpp_put_bits(&bp, pp->stVP9Segments.update_map, 1);
+    mpp_put_bits(&bp, pp->stVP9Segments.temporal_update, 1);
+    mpp_put_bits(&bp, pp->stVP9Segments.abs_delta, 1);
+
+    {
+        RK_U32 use_prev_frame_mvs = !pp->error_resilient_mode &&
+                                    pp->width == hw_ctx->ls_info.last_width &&
+                                    pp->height == hw_ctx->ls_info.last_height &&
+                                    !hw_ctx->ls_info.last_intra_only &&
+                                    hw_ctx->ls_info.last_show_frame;
+        mpp_put_bits(&bp, use_prev_frame_mvs, 1);
+    }
+
+    for ( i = 0; i < 8; i++ )
+        for ( j = 0; j < 4; j++ )
+            mpp_put_bits(&bp, (pp->stVP9Segments.feature_mask[i] >> j) & 0x1, 1);
+
+    for ( i = 0; i < 8; i++ ) {
+        mpp_put_bits(&bp, pp->stVP9Segments.feature_data[i][0], 9);
+        mpp_put_bits(&bp, pp->stVP9Segments.feature_data[i][1], 7);
+        mpp_put_bits(&bp, pp->stVP9Segments.feature_data[i][2], 2);
+    }
+
+    mpp_put_bits(&bp, pp->first_partition_size, 16);
+
+    /* refer frame width and height */
+    {
+        RK_S32 ref_idx = pp->frame_refs[0].Index7Bits;
+        mpp_put_bits(&bp, pp->ref_frame_coded_width[ref_idx], 16);
+        mpp_put_bits(&bp, pp->ref_frame_coded_height[ref_idx], 16);
+        ref_idx = pp->frame_refs[1].Index7Bits;
+        mpp_put_bits(&bp, pp->ref_frame_coded_width[ref_idx], 16);
+        mpp_put_bits(&bp, pp->ref_frame_coded_height[ref_idx], 16);
+        ref_idx = pp->frame_refs[2].Index7Bits;
+        mpp_put_bits(&bp, pp->ref_frame_coded_width[ref_idx], 16);
+        mpp_put_bits(&bp, pp->ref_frame_coded_height[ref_idx], 16);
+    }
+
+    /* last frame info */
+    mpp_put_bits(&bp, hw_ctx->ls_info.last_mode_deltas[0], 7);
+    mpp_put_bits(&bp, hw_ctx->ls_info.last_mode_deltas[1], 7);
+    mpp_put_bits(&bp, hw_ctx->ls_info.last_ref_deltas[0], 7);
+    mpp_put_bits(&bp, hw_ctx->ls_info.last_ref_deltas[1], 7);
+    mpp_put_bits(&bp, hw_ctx->ls_info.last_ref_deltas[2], 7);
+    mpp_put_bits(&bp, hw_ctx->ls_info.last_ref_deltas[3], 7);
+    mpp_put_bits(&bp, hw_ctx->ls_info.segmentation_enable_flag_last, 1);
+
+    mpp_put_bits(&bp, hw_ctx->ls_info.last_show_frame, 1);
+    mpp_put_bits(&bp, pp->intra_only, 1);
+    {
+        RK_U32 last_widthheight_eqcur = pp->width == hw_ctx->ls_info.last_width &&
+                                        pp->height == hw_ctx->ls_info.last_height;
+
+        mpp_put_bits(&bp, last_widthheight_eqcur, 1);
+    }
+    mpp_put_bits(&bp, hw_ctx->ls_info.color_space_last, 3);
+
+    mpp_put_bits(&bp, !hw_ctx->ls_info.last_frame_type, 1);
+    mpp_put_bits(&bp, 0, 1);
+    mpp_put_bits(&bp, 1, 1);
+    mpp_put_bits(&bp, 1, 1);
+    mpp_put_bits(&bp, 1, 1);
+
+    mpp_put_bits(&bp, pp->mvscale[0][0], 16);
+    mpp_put_bits(&bp, pp->mvscale[0][1], 16);
+    mpp_put_bits(&bp, pp->mvscale[1][0], 16);
+    mpp_put_bits(&bp, pp->mvscale[1][1], 16);
+    mpp_put_bits(&bp, pp->mvscale[2][0], 16);
+    mpp_put_bits(&bp, pp->mvscale[2][1], 16);
+
+    /* tile cols and rows */
+    {
+        RK_S32 tile_width[64] = {0};
+        RK_S32 tile_height[4] = {0};
+        RK_S32 tile_cols = 1 << pp->log2_tile_cols;
+        RK_S32 tile_rows = 1 << pp->log2_tile_rows;
+
+        mpp_put_bits(&bp, tile_cols, 7);
+        mpp_put_bits(&bp, tile_rows, 3);
+
+        for (i = 0; i < tile_cols; ++i) { // tile_col
+            RK_S32 tile_col_start = 0;
+            RK_S32 tile_col_end = 0;
+
+            set_tile_offset(&tile_col_start, &tile_col_end,
+                            i, pp->log2_tile_cols, MPP_ALIGN(pp->width, 64) / 64);
+            tile_width[i] = (tile_col_end - tile_col_start + 7) / 8;
+        }
+
+        for (j = 0; j < tile_rows; ++j) { // tile_row
+            RK_S32 tile_row_start = 0;
+            RK_S32 tile_row_end = 0;
+
+            set_tile_offset(&tile_row_start, &tile_row_end,
+                            j, pp->log2_tile_rows, MPP_ALIGN(pp->height, 64) / 64);
+            tile_height[j] = (tile_row_end - tile_row_start + 7) / 8;
+        }
+
+        for (i = 0; i < 64; i++)
+            mpp_put_bits(&bp, tile_width[i], 10);
+
+        for (j = 0; j < 4; j++)
+            mpp_put_bits(&bp, tile_height[j], 10);
+    }
+
+    mpp_put_align(&bp, 64, 0);//128
+
+#ifdef DUMP_VDPU383_DATAS
+    {
+        char *cur_fname = "global_cfg.dat";
+        memset(dump_cur_fname_path, 0, sizeof(dump_cur_fname_path));
+        sprintf(dump_cur_fname_path, "%s/%s", dump_cur_dir, cur_fname);
+        dump_data_to_file(dump_cur_fname_path, (void *)bp.pbuf, 64 * (bp.index - 1) + bp.bitpos, 64, 0);
+    }
+#endif
+
+    return MPP_OK;
+}
+
+static MPP_RET hal_vp9d_vdpu383_gen_regs(void *hal, HalTaskInfo *task)
+{
+    RK_S32 i;
+    RK_U8  bit_depth = 0;
+    RK_U32 pic_h[3] = { 0 };
+    RK_U32 ref_frame_width_y;
+    RK_U32 ref_frame_height_y;
+    RK_S32 stream_len = 0, aglin_offset = 0;
+    RK_U32 y_hor_virstride, uv_hor_virstride, y_virstride;
+    RK_U8  *bitstream = NULL;
+    MppBuffer streambuf = NULL;
+    RK_U32 sw_y_hor_virstride;
+    RK_U32 sw_uv_hor_virstride;
+    RK_U32 sw_y_virstride;
+    RK_U32 sw_uv_virstride;
+    RK_U8  ref_idx = 0;
+    RK_U32 *reg_ref_base = NULL;
+    RK_U32 *reg_payload_ref_base = NULL;
+    RK_S32 intraFlag = 0;
+    MppBuffer framebuf = NULL;
+    HalBuf *mv_buf = NULL;
+    RK_U32 fbc_en = 0;
+    HalBuf *origin_buf = NULL;
+
+    HalVp9dCtx *p_hal = (HalVp9dCtx*)hal;
+    Vdpu383Vp9dCtx *hw_ctx = (Vdpu383Vp9dCtx*)p_hal->hw_ctx;
+    DXVA_PicParams_VP9 *pic_param = (DXVA_PicParams_VP9*)task->dec.syntax.data;
+    Vdpu383Vp9dRegSet *vp9_hw_regs = NULL;
+    RK_S32 mv_size = pic_param->width * pic_param->height / 2;
+    RK_U32 frame_ctx_id = pic_param->frame_context_idx;
+    MppFrame mframe;
+
+    if (p_hal->fast_mode) {
+        for (i = 0; i < MAX_GEN_REG; i++) {
+            if (!hw_ctx->g_buf[i].use_flag) {
+                task->dec.reg_index = i;
+                hw_ctx->global_base = hw_ctx->g_buf[i].global_base;
+                hw_ctx->probe_base = hw_ctx->g_buf[i].probe_base;
+                hw_ctx->count_base = hw_ctx->g_buf[i].count_base;
+                hw_ctx->hw_regs = hw_ctx->g_buf[i].hw_regs;
+                hw_ctx->g_buf[i].use_flag = 1;
+                break;
+            }
+        }
+        if (i == MAX_GEN_REG) {
+            mpp_err("vp9 fast mode buf all used\n");
+            return MPP_ERR_NOMEM;
+        }
+    }
+    vp9_hw_regs = (Vdpu383Vp9dRegSet*)hw_ctx->hw_regs;
+    memset(vp9_hw_regs, 0, sizeof(Vdpu383Vp9dRegSet));
+
+#ifdef DUMP_VDPU383_DATAS
+    {
+        memset(dump_cur_dir, 0, sizeof(dump_cur_dir));
+        sprintf(dump_cur_dir, "vp9/Frame%04d", dump_cur_frame);
+        if (access(dump_cur_dir, 0)) {
+            if (mkdir(dump_cur_dir))
+                mpp_err_f("error: mkdir %s\n", dump_cur_dir);
+        }
+        dump_cur_frame++;
+    }
+#endif
+
+    /* uncompress header data */
+    prepare_uncompress_header(p_hal, pic_param, (RK_U64 *)hw_ctx->header_data, sizeof(hw_ctx->header_data) / 8);
+    memcpy(mpp_buffer_get_ptr(hw_ctx->global_base), hw_ctx->header_data, sizeof(hw_ctx->header_data));
+    mpp_buffer_sync_end(hw_ctx->global_base);
+    vp9_hw_regs->vp9d_paras.reg67_global_len = GBL_SIZE / 16;
+    vp9_hw_regs->common_addr.reg131_gbl_base = mpp_buffer_get_fd(hw_ctx->global_base);
+
+    if (hw_ctx->cmv_bufs == NULL || hw_ctx->mv_size < mv_size) {
+        size_t size = mv_size;
+
+        if (hw_ctx->cmv_bufs) {
+            hal_bufs_deinit(hw_ctx->cmv_bufs);
+            hw_ctx->cmv_bufs = NULL;
+        }
+
+        hal_bufs_init(&hw_ctx->cmv_bufs);
+        if (hw_ctx->cmv_bufs == NULL) {
+            mpp_err_f("colmv bufs init fail");
+            return MPP_NOK;
+        }
+        hw_ctx->mv_size = mv_size;
+        hw_ctx->mv_count = mpp_buf_slot_get_count(p_hal ->slots);
+        hal_bufs_setup(hw_ctx->cmv_bufs, hw_ctx->mv_count, 1, &size);
+    }
+
+    mpp_buf_slot_get_prop(p_hal->slots, task->dec.output, SLOT_FRAME_PTR, &mframe);
+    if (mpp_frame_get_thumbnail_en(mframe) == MPP_FRAME_THUMBNAIL_ONLY &&
+        hw_ctx->origin_bufs == NULL) {
+        vdpu383_setup_scale_origin_bufs(hw_ctx, mframe);
+    }
+
+    stream_len = (RK_S32)mpp_packet_get_length(task->dec.input_packet);
+
+    intraFlag = (!pic_param->frame_type || pic_param->intra_only);
+#if HW_PROB
+    // hal_vp9d_prob_flag_delta(mpp_buffer_get_ptr(hw_ctx->probe_base), task->dec.syntax.data);
+    /* init kf_probe */
+    hal_vp9d_prob_kf(mpp_buffer_get_ptr(hw_ctx->probe_base));
+    mpp_buffer_sync_end(hw_ctx->probe_base);
+    if (intraFlag) {
+        hal_vp9d_prob_default(mpp_buffer_get_ptr(hw_ctx->prob_default_base), task->dec.syntax.data);
+        mpp_buffer_sync_end(hw_ctx->prob_default_base);
+    }
+
+    /* config last prob base and update write base */
+    {
+        if (intraFlag || pic_param->error_resilient_mode) {
+            if (intraFlag
+                || pic_param->error_resilient_mode
+                || (pic_param->reset_frame_context == 3)) {
+                memset(hw_ctx->prob_ctx_valid, 0, sizeof(hw_ctx->prob_ctx_valid));
+            } else if (pic_param->reset_frame_context == 2) {
+                hw_ctx->prob_ctx_valid[frame_ctx_id] = 0;
+            }
+        }
+
+        if (hw_ctx->prob_ctx_valid[frame_ctx_id]) {
+            vp9_hw_regs->vp9d_addrs.reg184_lastprob_base =
+                mpp_buffer_get_fd(hw_ctx->prob_loop_base[frame_ctx_id]);
+#ifdef DUMP_VDPU383_DATAS
+            { cur_last_prob_base = hw_ctx->prob_loop_base[frame_ctx_id]; }
+#endif
+        } else {
+            vp9_hw_regs->vp9d_addrs.reg184_lastprob_base = mpp_buffer_get_fd(hw_ctx->prob_default_base);
+            hw_ctx->prob_ctx_valid[frame_ctx_id] |= pic_param->refresh_frame_context;
+#ifdef DUMP_VDPU383_DATAS
+            { cur_last_prob_base = hw_ctx->prob_default_base; }
+#endif
+        }
+        vp9_hw_regs->vp9d_addrs.reg185_updateprob_base =
+            mpp_buffer_get_fd(hw_ctx->prob_loop_base[frame_ctx_id]);
+    }
+    vp9_hw_regs->vp9d_addrs.reg183_kfprob_base = mpp_buffer_get_fd(hw_ctx->probe_base);
+#ifdef DUMP_VDPU383_DATAS
+    {
+        char *cur_fname = "cabac_last_probe.dat";
+        memset(dump_cur_fname_path, 0, sizeof(dump_cur_fname_path));
+        sprintf(dump_cur_fname_path, "%s/%s", dump_cur_dir, cur_fname);
+        dump_data_to_file(dump_cur_fname_path, (void *)mpp_buffer_get_ptr(cur_last_prob_base),
+                          8 * 152 * 16, 128, 0);
+    }
+    {
+        char *cur_fname = "cabac_kf_probe.dat";
+        memset(dump_cur_fname_path, 0, sizeof(dump_cur_fname_path));
+        sprintf(dump_cur_fname_path, "%s/%s", dump_cur_dir, cur_fname);
+        dump_data_to_file(dump_cur_fname_path, (void *)mpp_buffer_get_ptr(hw_ctx->probe_base),
+                          8 * PROB_KF_SIZE, 128, 0);
+    }
+#endif
+#else
+#endif
+
+    vp9_hw_regs->vp9d_paras.reg66_stream_len = ((stream_len + 15) & (~15)) + 0x80;
+
+    mpp_buf_slot_get_prop(p_hal->packet_slots, task->dec.input, SLOT_BUFFER, &streambuf);
+    bitstream = mpp_buffer_get_ptr(streambuf);
+    aglin_offset = vp9_hw_regs->vp9d_paras.reg66_stream_len - stream_len;
+    if (aglin_offset > 0) {
+        memset((void *)(bitstream + stream_len), 0, aglin_offset);
+    }
+
+    //--- caculate the yuv_frame_size and mv_size
+    bit_depth = pic_param->BitDepthMinus8Luma + 8;
+    pic_h[0] = vp9_ver_align(pic_param->height);
+    pic_h[1] = vp9_ver_align(pic_param->height) / 2;
+    pic_h[2] = pic_h[1];
+
+    {
+        mpp_buf_slot_get_prop(p_hal->slots, task->dec.output, SLOT_FRAME_PTR, &mframe);
+        fbc_en = MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(mframe));
+
+        if (fbc_en) {
+            RK_U32 w = MPP_ALIGN(mpp_frame_get_width(mframe), 64);
+            RK_U32 h = MPP_ALIGN(mpp_frame_get_height(mframe), 8);
+            RK_U32 fbd_offset;
+
+            vp9_hw_regs->ctrl_regs.reg9.fbc_e = 1;
+            vp9_hw_regs->vp9d_paras.reg68_hor_virstride = w / 64;
+            fbd_offset = vp9_hw_regs->vp9d_paras.reg68_hor_virstride * h * 4;
+            vp9_hw_regs->vp9d_addrs.reg193_fbc_payload_offset = fbd_offset;
+            /* error stride */
+            vp9_hw_regs->vp9d_paras.reg80_error_ref_hor_virstride = w / 64;
+        } else {
+            sw_y_hor_virstride = (mpp_align_128_odd_plus_64((pic_param->width * bit_depth) >> 3) >> 4);
+            sw_uv_hor_virstride = (mpp_align_128_odd_plus_64((pic_param->width * bit_depth) >> 3) >> 4);
+            sw_y_virstride = pic_h[0] * sw_y_hor_virstride;
+            sw_uv_virstride = sw_y_virstride / 2;
+
+            vp9_hw_regs->ctrl_regs.reg9.fbc_e = 0;
+            if (MPP_FRAME_FMT_IS_TILE(mpp_frame_get_fmt(mframe))) {
+                vp9_hw_regs->ctrl_regs.reg9.tile_e = 1;
+                vp9_hw_regs->vp9d_paras.reg68_hor_virstride = sw_y_hor_virstride * 6;
+                vp9_hw_regs->vp9d_paras.reg70_y_virstride = sw_y_virstride + sw_uv_virstride;
+            } else {
+                vp9_hw_regs->ctrl_regs.reg9.tile_e = 0;
+                vp9_hw_regs->vp9d_paras.reg68_hor_virstride = sw_y_hor_virstride;
+                vp9_hw_regs->vp9d_paras.reg69_raster_uv_hor_virstride = sw_uv_hor_virstride;
+                vp9_hw_regs->vp9d_paras.reg70_y_virstride = sw_y_virstride;
+            }
+            /* error stride */
+            vp9_hw_regs->vp9d_paras.reg80_error_ref_hor_virstride = sw_y_hor_virstride;
+            vp9_hw_regs->vp9d_paras.reg81_error_ref_raster_uv_hor_virstride = sw_uv_hor_virstride;
+            vp9_hw_regs->vp9d_paras.reg82_error_ref_virstride = sw_y_virstride;
+        }
+    }
+    if (!pic_param->intra_only && pic_param->frame_type &&
+        !pic_param->error_resilient_mode && hw_ctx->ls_info.last_show_frame) {
+        hw_ctx->pre_mv_base_addr = hw_ctx->mv_base_addr;
+    }
+
+    mpp_buf_slot_get_prop(p_hal->slots, task->dec.output, SLOT_FRAME_PTR, &mframe);
+    mpp_buf_slot_get_prop(p_hal ->slots, task->dec.output, SLOT_BUFFER, &framebuf);
+    if (mpp_frame_get_thumbnail_en(mframe) == MPP_FRAME_THUMBNAIL_ONLY) {
+        origin_buf = hal_bufs_get_buf(hw_ctx->origin_bufs, task->dec.output);
+        framebuf = origin_buf->buf[0];
+    }
+    vp9_hw_regs->vp9d_addrs.reg168_decout_base = mpp_buffer_get_fd(framebuf);
+    vp9_hw_regs->vp9d_addrs.reg169_error_ref_base = mpp_buffer_get_fd(framebuf);
+    vp9_hw_regs->vp9d_addrs.reg192_payload_st_cur_base = mpp_buffer_get_fd(framebuf);
+    vp9_hw_regs->vp9d_addrs.reg194_payload_st_error_ref_base = mpp_buffer_get_fd(framebuf);
+    vp9_hw_regs->common_addr.reg128_strm_base = mpp_buffer_get_fd(streambuf);
+
+    {
+        RK_U32 strm_offset = pic_param->uncompressed_header_size_byte_aligned;
+
+        vp9_hw_regs->vp9d_paras.reg65_strm_start_bit = 8 * (strm_offset & 0xf);
+        mpp_dev_set_reg_offset(p_hal->dev, 128, strm_offset & 0xfffffff0);
+    }
+
+    if (hw_ctx->last_segid_flag) {
+        vp9_hw_regs->vp9d_addrs.reg181_segidlast_base = mpp_buffer_get_fd(hw_ctx->segid_last_base);
+        vp9_hw_regs->vp9d_addrs.reg182_segidcur_base = mpp_buffer_get_fd(hw_ctx->segid_cur_base);
+    } else {
+        vp9_hw_regs->vp9d_addrs.reg181_segidlast_base = mpp_buffer_get_fd(hw_ctx->segid_cur_base);
+        vp9_hw_regs->vp9d_addrs.reg182_segidcur_base = mpp_buffer_get_fd(hw_ctx->segid_last_base);
+    }
+#ifdef DUMP_VDPU383_DATAS
+    cur_last_segid_flag = hw_ctx->last_segid_flag;
+    {
+        char *cur_fname = "stream_in.dat";
+        memset(dump_cur_fname_path, 0, sizeof(dump_cur_fname_path));
+        sprintf(dump_cur_fname_path, "%s/%s", dump_cur_dir, cur_fname);
+        dump_data_to_file(dump_cur_fname_path, (void *)mpp_buffer_get_ptr(streambuf)
+                          + pic_param->uncompressed_header_size_byte_aligned,
+                          8 * (((stream_len + 15) & (~15)) + 0x80), 128, 0);
+    }
+#endif
+    /* set last segid flag */
+    if ((pic_param->stVP9Segments.enabled && pic_param->stVP9Segments.update_map) ||
+        (pic_param->width != hw_ctx->ls_info.last_width || pic_param->height != hw_ctx->ls_info.last_height) ||
+        intraFlag || pic_param->error_resilient_mode) {
+        hw_ctx->last_segid_flag = !hw_ctx->last_segid_flag;
+    }
+    //set cur colmv base
+    mv_buf = hal_bufs_get_buf(hw_ctx->cmv_bufs, task->dec.output);
+
+    vp9_hw_regs->vp9d_addrs.reg216_colmv_cur_base = mpp_buffer_get_fd(mv_buf->buf[0]);
+
+    hw_ctx->mv_base_addr = vp9_hw_regs->vp9d_addrs.reg216_colmv_cur_base;
+    if (hw_ctx->pre_mv_base_addr < 0)
+        hw_ctx->pre_mv_base_addr = hw_ctx->mv_base_addr;
+
+    // vp9 only one colmv
+    vp9_hw_regs->vp9d_addrs.reg217_232_colmv_ref_base[0] = hw_ctx->pre_mv_base_addr;
+
+    reg_ref_base = vp9_hw_regs->vp9d_addrs.reg170_185_ref_base;
+    reg_payload_ref_base = vp9_hw_regs->vp9d_addrs.reg195_210_payload_st_ref_base;
+    for (i = 0; i < 3; i++) {
+        ref_idx = pic_param->frame_refs[i].Index7Bits;
+        ref_frame_width_y = pic_param->ref_frame_coded_width[ref_idx];
+        ref_frame_height_y = pic_param->ref_frame_coded_height[ref_idx];
+        pic_h[0] = vp9_ver_align(ref_frame_height_y);
+        pic_h[1] = vp9_ver_align(ref_frame_height_y) / 2;
+        if (fbc_en) {
+            y_hor_virstride = uv_hor_virstride = MPP_ALIGN(ref_frame_width_y, 64) / 64;
+        } else {
+            y_hor_virstride = uv_hor_virstride = (mpp_align_128_odd_plus_64((ref_frame_width_y * bit_depth) >> 3) >> 4);
+        }
+        y_virstride = y_hor_virstride * pic_h[0];
+
+        if (pic_param->ref_frame_map[ref_idx].Index7Bits < 0x7f) {
+            mpp_buf_slot_get_prop(p_hal ->slots, pic_param->ref_frame_map[ref_idx].Index7Bits, SLOT_BUFFER, &framebuf);
+            if (hw_ctx->origin_bufs && mpp_frame_get_thumbnail_en(mframe) == MPP_FRAME_THUMBNAIL_ONLY) {
+                origin_buf = hal_bufs_get_buf(hw_ctx->origin_bufs, pic_param->ref_frame_map[ref_idx].Index7Bits);
+                framebuf = origin_buf->buf[0];
+            }
+
+            switch (i) {
+            case 0: {
+                vp9_hw_regs->vp9d_paras.reg83_ref0_hor_virstride = y_hor_virstride;
+                vp9_hw_regs->vp9d_paras.reg84_ref0_raster_uv_hor_virstride = uv_hor_virstride;
+                vp9_hw_regs->vp9d_paras.reg85_ref0_virstride = y_virstride;
+            } break;
+            case 1: {
+                vp9_hw_regs->vp9d_paras.reg86_ref1_hor_virstride = y_hor_virstride;
+                vp9_hw_regs->vp9d_paras.reg87_ref1_raster_uv_hor_virstride = uv_hor_virstride;
+                vp9_hw_regs->vp9d_paras.reg88_ref1_virstride = y_virstride;
+            } break;
+            case 2: {
+                vp9_hw_regs->vp9d_paras.reg89_ref2_hor_virstride = y_hor_virstride;
+                vp9_hw_regs->vp9d_paras.reg90_ref2_raster_uv_hor_virstride = uv_hor_virstride;
+                vp9_hw_regs->vp9d_paras.reg91_ref2_virstride = y_virstride;
+            } break;
+            default:
+                break;
+            }
+
+            /*0 map to 11*/
+            /*1 map to 12*/
+            /*2 map to 13*/
+            if (framebuf != NULL) {
+                reg_ref_base[i] = mpp_buffer_get_fd(framebuf);
+                reg_payload_ref_base[i] = mpp_buffer_get_fd(framebuf);
+            } else {
+                mpp_log("ref buff address is no valid used out as base slot index 0x%x", pic_param->ref_frame_map[ref_idx].Index7Bits);
+                reg_ref_base[i] = vp9_hw_regs->vp9d_addrs.reg168_decout_base;
+                reg_payload_ref_base[i] = vp9_hw_regs->vp9d_addrs.reg168_decout_base;
+            }
+            mv_buf = hal_bufs_get_buf(hw_ctx->cmv_bufs, pic_param->ref_frame_map[ref_idx].Index7Bits);
+        } else {
+            reg_ref_base[i] = vp9_hw_regs->vp9d_addrs.reg168_decout_base;
+            reg_payload_ref_base[i] = vp9_hw_regs->vp9d_addrs.reg168_decout_base;
+        }
+    }
+
+    /* common register setting */
+    vp9_hw_regs->ctrl_regs.reg8_dec_mode = 2; //set as vp9 dec
+    vp9_hw_regs->ctrl_regs.reg9.buf_empty_en = 0;
+
+    vp9_hw_regs->ctrl_regs.reg10.strmd_auto_gating_e      = 1;
+    vp9_hw_regs->ctrl_regs.reg10.inter_auto_gating_e      = 1;
+    vp9_hw_regs->ctrl_regs.reg10.intra_auto_gating_e      = 1;
+    vp9_hw_regs->ctrl_regs.reg10.transd_auto_gating_e     = 1;
+    vp9_hw_regs->ctrl_regs.reg10.recon_auto_gating_e      = 1;
+    vp9_hw_regs->ctrl_regs.reg10.filterd_auto_gating_e    = 1;
+    vp9_hw_regs->ctrl_regs.reg10.bus_auto_gating_e        = 1;
+    vp9_hw_regs->ctrl_regs.reg10.ctrl_auto_gating_e       = 1;
+    vp9_hw_regs->ctrl_regs.reg10.rcb_auto_gating_e        = 1;
+    vp9_hw_regs->ctrl_regs.reg10.err_prc_auto_gating_e    = 1;
+
+    vp9_hw_regs->ctrl_regs.reg16.error_proc_disable = 1;
+    vp9_hw_regs->ctrl_regs.reg16.error_spread_disable = 0;
+    vp9_hw_regs->ctrl_regs.reg16.roi_error_ctu_cal_en = 0;
+
+    vp9_hw_regs->ctrl_regs.reg20_cabac_error_en_lowbits = 0xffffffdf;
+    vp9_hw_regs->ctrl_regs.reg21_cabac_error_en_highbits = 0x3fffffff;
+
+    vp9_hw_regs->ctrl_regs.reg13_core_timeout_threshold = 0x3ffff;
+
+    //last info update
+    hw_ctx->ls_info.abs_delta_last = pic_param->stVP9Segments.abs_delta;
+    for (i = 0 ; i < 4; i ++) {
+        hw_ctx->ls_info.last_ref_deltas[i] = pic_param->ref_deltas[i];
+    }
+
+    for (i = 0 ; i < 2; i ++) {
+        hw_ctx->ls_info.last_mode_deltas[i] = pic_param->mode_deltas[i];
+    }
+
+    for (i = 0; i < 8; i++) {
+        hw_ctx->ls_info.feature_data[i][0] = pic_param->stVP9Segments.feature_data[i][0];
+        hw_ctx->ls_info.feature_data[i][1] = pic_param->stVP9Segments.feature_data[i][1];
+        hw_ctx->ls_info.feature_data[i][2] = pic_param->stVP9Segments.feature_data[i][2];
+        hw_ctx->ls_info.feature_data[i][3] = pic_param->stVP9Segments.feature_data[i][3];
+        hw_ctx->ls_info.feature_mask[i] = pic_param->stVP9Segments.feature_mask[i];
+    }
+    if (!hw_ctx->ls_info.segmentation_enable_flag_last)
+        hw_ctx->ls_info.segmentation_enable_flag_last = pic_param->stVP9Segments.enabled;
+
+    hw_ctx->ls_info.last_show_frame = pic_param->show_frame;
+    hw_ctx->ls_info.last_width = pic_param->width;
+    hw_ctx->ls_info.last_height = pic_param->height;
+    hw_ctx->ls_info.last_frame_type = pic_param->frame_type;
+
+    if (intraFlag)
+        hw_ctx->ls_info.last_intra_only = 1;
+
+    hw_ctx->ls_info.last_intra_only = (!pic_param->frame_type || pic_param->intra_only);
+    hal_vp9d_dbg_par("stVP9Segments.enabled %d show_frame %d width %d height %d last_intra_only %d",
+                     pic_param->stVP9Segments.enabled, pic_param->show_frame,
+                     pic_param->width, pic_param->height,
+                     hw_ctx->ls_info.last_intra_only);
+
+    hal_vp9d_rcb_info_update(hal, vp9_hw_regs, pic_param);
+    {
+        MppBuffer rcb_buf = NULL;
+
+        rcb_buf = p_hal->fast_mode ? hw_ctx->g_buf[task->dec.reg_index].rcb_buf : hw_ctx->rcb_buf;
+        vdpu383_setup_rcb(&vp9_hw_regs->common_addr, p_hal->dev, rcb_buf, hw_ctx->rcb_info);
+    }
+    vdpu383_setup_statistic(&vp9_hw_regs->ctrl_regs);
+    // whether need update counts
+    if (pic_param->refresh_frame_context && !pic_param->parallelmode) {
+        task->dec.flags.wait_done = 1;
+    }
+
+    {
+        //scale down config
+        MppBuffer mbuffer = NULL;
+        RK_S32 fd = -1;
+        MppFrameThumbnailMode thumbnail_mode;
+
+        mpp_buf_slot_get_prop(p_hal->slots, task->dec.output,
+                              SLOT_BUFFER, &mbuffer);
+        mpp_buf_slot_get_prop(p_hal->slots, task->dec.output,
+                              SLOT_FRAME_PTR, &mframe);
+        thumbnail_mode = mpp_frame_get_thumbnail_en(mframe);
+        switch (thumbnail_mode) {
+        case MPP_FRAME_THUMBNAIL_ONLY:
+            vp9_hw_regs->common_addr.reg133_scale_down_base = mpp_buffer_get_fd(mbuffer);
+            origin_buf = hal_bufs_get_buf(hw_ctx->origin_bufs, task->dec.output);
+            fd = mpp_buffer_get_fd(origin_buf->buf[0]);
+            vp9_hw_regs->vp9d_addrs.reg168_decout_base = fd;
+            vp9_hw_regs->vp9d_addrs.reg169_error_ref_base = fd;
+            vp9_hw_regs->vp9d_addrs.reg192_payload_st_cur_base = fd;
+            vp9_hw_regs->vp9d_addrs.reg194_payload_st_error_ref_base = fd;
+            vdpu383_setup_down_scale(mframe, p_hal->dev, &vp9_hw_regs->ctrl_regs,
+                                     (void *)&vp9_hw_regs->vp9d_paras);
+            break;
+        case MPP_FRAME_THUMBNAIL_MIXED:
+            vp9_hw_regs->common_addr.reg133_scale_down_base = mpp_buffer_get_fd(mbuffer);
+            vdpu383_setup_down_scale(mframe, p_hal->dev, &vp9_hw_regs->ctrl_regs,
+                                     (void *)&vp9_hw_regs->vp9d_paras);
+            break;
+        case MPP_FRAME_THUMBNAIL_NONE:
+        default:
+            vp9_hw_regs->ctrl_regs.reg9.scale_down_en = 0;
+            break;
+        }
+    }
+
+    return MPP_OK;
+}
+
+static MPP_RET hal_vp9d_vdpu383_start(void *hal, HalTaskInfo *task)
+{
+    MPP_RET ret = MPP_OK;
+    HalVp9dCtx *p_hal = (HalVp9dCtx*)hal;
+    Vdpu383Vp9dCtx *hw_ctx = (Vdpu383Vp9dCtx*)p_hal->hw_ctx;
+    Vdpu383Vp9dRegSet *hw_regs = (Vdpu383Vp9dRegSet *)hw_ctx->hw_regs;
+    MppDev dev = p_hal->dev;
+
+    if (p_hal->fast_mode) {
+        RK_S32 index = task->dec.reg_index;
+
+        hw_regs = (Vdpu383Vp9dRegSet *)hw_ctx->g_buf[index].hw_regs;
+    }
+
+    mpp_assert(hw_regs);
+
+    do {
+        MppDevRegWrCfg wr_cfg;
+        MppDevRegRdCfg rd_cfg;
+
+        wr_cfg.reg = &hw_regs->ctrl_regs;
+        wr_cfg.size = sizeof(hw_regs->ctrl_regs);
+        wr_cfg.offset = OFFSET_CTRL_REGS;
+        ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
+        if (ret) {
+            mpp_err_f("set register write failed %d\n", ret);
+            break;
+        }
+
+        wr_cfg.reg = &hw_regs->common_addr;
+        wr_cfg.size = sizeof(hw_regs->common_addr);
+        wr_cfg.offset = OFFSET_COMMON_ADDR_REGS;
+        ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
+        if (ret) {
+            mpp_err_f("set register write failed %d\n", ret);
+            break;
+        }
+
+        wr_cfg.reg = &hw_regs->vp9d_paras;
+        wr_cfg.size = sizeof(hw_regs->vp9d_paras);
+        wr_cfg.offset = OFFSET_CODEC_PARAS_REGS;
+        ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
+        if (ret) {
+            mpp_err_f("set register write failed %d\n", ret);
+            break;
+        }
+
+        wr_cfg.reg = &hw_regs->vp9d_addrs;
+        wr_cfg.size = sizeof(hw_regs->vp9d_addrs);
+        wr_cfg.offset = OFFSET_CODEC_ADDR_REGS;
+        ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
+        if (ret) {
+            mpp_err_f("set register write failed %d\n", ret);
+            break;
+        }
+
+        rd_cfg.reg = &hw_regs->ctrl_regs.reg15;
+        rd_cfg.size = sizeof(hw_regs->ctrl_regs.reg15);
+        rd_cfg.offset = OFFSET_INTERRUPT_REGS;
+        ret = mpp_dev_ioctl(dev, MPP_DEV_REG_RD, &rd_cfg);
+        if (ret) {
+            mpp_err_f("set register read failed %d\n", ret);
+            break;
+        }
+
+        // rcb info for sram
+        vdpu383_set_rcbinfo(dev, hw_ctx->rcb_info);
+
+        ret = mpp_dev_ioctl(dev, MPP_DEV_CMD_SEND, NULL);
+        if (ret) {
+            mpp_err_f("send cmd failed %d\n", ret);
+            break;
+        }
+    } while (0);
+
+    return ret;
+}
+
+static MPP_RET hal_vp9d_vdpu383_wait(void *hal, HalTaskInfo *task)
+{
+    MPP_RET ret = MPP_OK;
+    HalVp9dCtx *p_hal = (HalVp9dCtx*)hal;
+    Vdpu383Vp9dCtx *hw_ctx = (Vdpu383Vp9dCtx*)p_hal->hw_ctx;
+    Vdpu383Vp9dRegSet *hw_regs = (Vdpu383Vp9dRegSet *)hw_ctx->hw_regs;
+
+    if (p_hal->fast_mode)
+        hw_regs = (Vdpu383Vp9dRegSet *)hw_ctx->g_buf[task->dec.reg_index].hw_regs;
+
+    mpp_assert(hw_regs);
+
+    ret = mpp_dev_ioctl(p_hal->dev, MPP_DEV_CMD_POLL, NULL);
+    if (ret)
+        mpp_err_f("poll cmd failed %d\n", ret);
+#ifdef DUMP_VDPU383_DATAS
+    {
+        char *cur_fname = "cabac_update_probe.dat";
+        DXVA_PicParams_VP9 *pic_param = (DXVA_PicParams_VP9*)task->dec.syntax.data;
+        RK_U32 frame_ctx_id = pic_param->frame_context_idx;
+        memset(dump_cur_fname_path, 0, sizeof(dump_cur_fname_path));
+        sprintf(dump_cur_fname_path, "%s/%s", dump_cur_dir, cur_fname);
+        dump_data_to_file(dump_cur_fname_path,
+                          (void *)mpp_buffer_get_ptr(hw_ctx->prob_loop_base[frame_ctx_id]),
+                          8 * 152 * 16, 128, 0);
+    }
+    {
+        char *cur_fname = "segid_last.dat";
+        memset(dump_cur_fname_path, 0, sizeof(dump_cur_fname_path));
+        sprintf(dump_cur_fname_path, "%s/%s", dump_cur_dir, cur_fname);
+        if (!cur_last_segid_flag)
+            dump_data_to_file(dump_cur_fname_path,
+                              (void *)mpp_buffer_get_ptr(hw_ctx->segid_cur_base),
+                              8 * 1559 * 8, 64, 0);
+        else
+            dump_data_to_file(dump_cur_fname_path,
+                              (void *)mpp_buffer_get_ptr(hw_ctx->segid_last_base),
+                              8 * 1559 * 8, 64, 0);
+    }
+    {
+        char *cur_fname = "segid_cur.dat";
+        memset(dump_cur_fname_path, 0, sizeof(dump_cur_fname_path));
+        sprintf(dump_cur_fname_path, "%s/%s", dump_cur_dir, cur_fname);
+        if (cur_last_segid_flag)
+            dump_data_to_file(dump_cur_fname_path,
+                              (void *)mpp_buffer_get_ptr(hw_ctx->segid_cur_base),
+                              8 * 1559 * 8, 64, 0);
+        else
+            dump_data_to_file(dump_cur_fname_path,
+                              (void *)mpp_buffer_get_ptr(hw_ctx->segid_last_base),
+                              8 * 1559 * 8, 64, 0);
+    }
+#endif
+
+    if (hal_vp9d_debug & HAL_VP9D_DBG_REG) {
+        RK_U32 *p = (RK_U32 *)hw_regs;
+        RK_U32 i = 0;
+
+        for (i = 0; i < sizeof(Vdpu383Vp9dRegSet) / 4; i++)
+            mpp_log("get regs[%02d]: %08X\n", i, *p++);
+    }
+
+    if (task->dec.flags.parse_err ||
+        task->dec.flags.ref_err ||
+        (!hw_regs->ctrl_regs.reg15.rkvdec_frame_rdy_sta) ||
+        hw_regs->ctrl_regs.reg15.rkvdec_strm_error_sta ||
+        hw_regs->ctrl_regs.reg15.rkvdec_core_timeout_sta ||
+        hw_regs->ctrl_regs.reg15.rkvdec_ip_timeout_sta ||
+        hw_regs->ctrl_regs.reg15.rkvdec_bus_error_sta ||
+        hw_regs->ctrl_regs.reg15.rkvdec_buffer_empty_sta ||
+        hw_regs->ctrl_regs.reg15.rkvdec_colmv_ref_error_sta) {
+        MppFrame mframe = NULL;
+
+        mpp_buf_slot_get_prop(p_hal->slots, task->dec.output, SLOT_FRAME_PTR, &mframe);
+        mpp_frame_set_errinfo(mframe, 1);
+    }
+
+#if !HW_PROB
+    if (p_hal->dec_cb && task->dec.flags.wait_done) {
+        DXVA_PicParams_VP9 *pic_param = (DXVA_PicParams_VP9*)task->dec.syntax.data;
+        hal_vp9d_update_counts(mpp_buffer_get_ptr(hw_ctx->count_base), task->dec.syntax.data);
+        mpp_callback(p_hal->dec_cb, &pic_param->counts);
+    }
+#endif
+    if (p_hal->fast_mode) {
+        hw_ctx->g_buf[task->dec.reg_index].use_flag = 0;
+    }
+
+    (void)task;
+    return ret;
+}
+
+static MPP_RET hal_vp9d_vdpu383_reset(void *hal)
+{
+    HalVp9dCtx *p_hal = (HalVp9dCtx*)hal;
+    Vdpu383Vp9dCtx *hw_ctx = (Vdpu383Vp9dCtx*)p_hal->hw_ctx;
+
+    hal_vp9d_enter();
+
+    memset(&hw_ctx->ls_info, 0, sizeof(hw_ctx->ls_info));
+    hw_ctx->mv_base_addr = -1;
+    hw_ctx->pre_mv_base_addr = -1;
+    hw_ctx->last_segid_flag = 1;
+
+    hal_vp9d_leave();
+
+    return MPP_OK;
+}
+
+static MPP_RET hal_vp9d_vdpu383_flush(void *hal)
+{
+    HalVp9dCtx *p_hal = (HalVp9dCtx*)hal;
+    Vdpu383Vp9dCtx *hw_ctx = (Vdpu383Vp9dCtx*)p_hal->hw_ctx;
+
+    hal_vp9d_enter();
+
+    hw_ctx->mv_base_addr = -1;
+    hw_ctx->pre_mv_base_addr = -1;
+
+    hal_vp9d_leave();
+
+    return MPP_OK;
+}
+
+static MPP_RET hal_vp9d_vdpu383_control(void *hal, MpiCmd cmd_type, void *param)
+{
+    HalVp9dCtx *p_hal = (HalVp9dCtx*)hal;
+
+    switch ((MpiCmd)cmd_type) {
+    case MPP_DEC_SET_FRAME_INFO : {
+        MppFrameFormat fmt = mpp_frame_get_fmt((MppFrame)param);
+
+        if (MPP_FRAME_FMT_IS_FBC(fmt)) {
+            vdpu383_afbc_align_calc(p_hal->slots, (MppFrame)param, 0);
+        } else {
+            mpp_slots_set_prop(p_hal->slots, SLOTS_HOR_ALIGN, mpp_align_128_odd_plus_64);
+        }
+    } break;
+    case MPP_DEC_GET_THUMBNAIL_FRAME_INFO: {
+        vdpu383_update_thumbnail_frame_info((MppFrame)param);
+    } break;
+    default : {
+    } break;
+    }
+
+    return MPP_OK;
+}
+
+const MppHalApi hal_vp9d_vdpu383 = {
+    .name = "vp9d_vdpu383",
+    .type = MPP_CTX_DEC,
+    .coding = MPP_VIDEO_CodingVP9,
+    .ctx_size = sizeof(Vdpu383Vp9dCtx),
+    .flag = 0,
+    .init = hal_vp9d_vdpu383_init,
+    .deinit = hal_vp9d_vdpu383_deinit,
+    .reg_gen = hal_vp9d_vdpu383_gen_regs,
+    .start = hal_vp9d_vdpu383_start,
+    .wait = hal_vp9d_vdpu383_wait,
+    .reset = hal_vp9d_vdpu383_reset,
+    .flush = hal_vp9d_vdpu383_flush,
+    .control = hal_vp9d_vdpu383_control,
+};
diff --git a/mpp/hal/rkdec/vp9d/hal_vp9d_vdpu383.h b/mpp/hal/rkdec/vp9d/hal_vp9d_vdpu383.h
new file mode 100644
index 000000000..aec2706a1
--- /dev/null
+++ b/mpp/hal/rkdec/vp9d/hal_vp9d_vdpu383.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: Apache-2.0 OR MIT */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef __HAL_VP9D_VDPU383_H__
+#define __HAL_VP9D_VDPU383_H__
+
+#include "mpp_hal.h"
+#include "vdpu383.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern const MppHalApi hal_vp9d_vdpu383;
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __HAL_VP9D_VDPU34X_H__ */
diff --git a/mpp/hal/rkenc/common/CMakeLists.txt b/mpp/hal/rkenc/common/CMakeLists.txt
index f3d76cf5c..65e8ebb22 100644
--- a/mpp/hal/rkenc/common/CMakeLists.txt
+++ b/mpp/hal/rkenc/common/CMakeLists.txt
@@ -7,6 +7,7 @@ add_library(hal_vepu541_common STATIC
             vepu5xx_common.c
             vepu540c_common.c
             vepu580_tune.c
+            vepu510_common.c
             )
 
 target_link_libraries(hal_vepu541_common mpp_base)
diff --git a/mpp/hal/rkenc/common/vepu510_common.c b/mpp/hal/rkenc/common/vepu510_common.c
new file mode 100644
index 000000000..942ba7699
--- /dev/null
+++ b/mpp/hal/rkenc/common/vepu510_common.c
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#define MODULE_TAG  "vepu510_common"
+
+#include <string.h>
+#include "mpp_log.h"
+#include "mpp_common.h"
+#include "vepu510_common.h"
+
+MPP_RET vepu510_set_roi(void *roi_reg_base, MppEncROICfg * roi,
+                        RK_S32 w, RK_S32 h)
+{
+    MppEncROIRegion *region = roi->regions;
+    Vepu510RoiCfg  *roi_cfg = (Vepu510RoiCfg *)roi_reg_base;
+    Vepu510RoiRegion *reg_regions = &roi_cfg->regions[0];
+    MPP_RET ret = MPP_NOK;
+    RK_S32 i = 0;
+
+    if (NULL == reg_regions) {
+        mpp_err_f("invalid reg_regions %p\n", reg_regions);
+        goto DONE;
+    }
+    memset(reg_regions, 0, sizeof(Vepu510RoiRegion) * 8);
+
+    if (NULL == roi_cfg || NULL == roi) {
+        mpp_err_f("invalid buf %p roi %p\n", roi_cfg, roi);
+        goto DONE;
+    }
+
+    if (roi->number > VEPU510_MAX_ROI_NUM) {
+        mpp_err_f("invalid region number %d\n", roi->number);
+        goto DONE;
+    }
+
+    /* check region config */
+    ret = MPP_OK;
+    for (i = 0; i < (RK_S32) roi->number; i++, region++) {
+        if (region->x + region->w > w || region->y + region->h > h)
+            ret = MPP_NOK;
+
+        if (region->intra > 1
+            || region->qp_area_idx >= VEPU510_MAX_ROI_NUM
+            || region->area_map_en > 1 || region->abs_qp_en > 1)
+            ret = MPP_NOK;
+
+        if ((region->abs_qp_en && region->quality > 51) ||
+            (!region->abs_qp_en
+             && (region->quality > 51 || region->quality < -51)))
+            ret = MPP_NOK;
+
+        if (ret) {
+            mpp_err_f("region %d invalid param:\n", i);
+            mpp_err_f("position [%d:%d:%d:%d] vs [%d:%d]\n",
+                      region->x, region->y, region->w, region->h, w,
+                      h);
+            mpp_err_f("force intra %d qp area index %d\n",
+                      region->intra, region->qp_area_idx);
+            mpp_err_f("abs qp mode %d value %d\n",
+                      region->abs_qp_en, region->quality);
+            goto DONE;
+        }
+        reg_regions->roi_pos_lt.roi_lt_x = MPP_ALIGN(region->x, 16) >> 4;
+        reg_regions->roi_pos_lt.roi_lt_y = MPP_ALIGN(region->y, 16) >> 4;
+        reg_regions->roi_pos_rb.roi_rb_x = MPP_ALIGN(region->x + region->w, 16) >> 4;
+        reg_regions->roi_pos_rb.roi_rb_y = MPP_ALIGN(region->y + region->h, 16) >> 4;
+        reg_regions->roi_base.roi_qp_value = region->quality;
+        reg_regions->roi_base.roi_qp_adj_mode = region->abs_qp_en;
+        reg_regions->roi_base.roi_en = 1;
+        reg_regions->roi_base.roi_pri = 0x1f;
+        if (region->intra) {
+            reg_regions->roi_mdc.roi_mdc_intra16 = 1;
+            reg_regions->roi_mdc.roi0_mdc_intra32_hevc = 1;
+        }
+        reg_regions++;
+    }
+
+DONE:
+    return ret;
+}
+
diff --git a/mpp/hal/rkenc/common/vepu510_common.h b/mpp/hal/rkenc/common/vepu510_common.h
new file mode 100644
index 000000000..330abe19f
--- /dev/null
+++ b/mpp/hal/rkenc/common/vepu510_common.h
@@ -0,0 +1,2248 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef __VEPU510_COMMON_H__
+#define __VEPU510_COMMON_H__
+
+#include "rk_venc_cmd.h"
+
+#define VEPU510_CTL_OFFSET           (0 * sizeof(RK_U32))       /* 0x00000000 reg0    - 0x00000120 reg72 */
+#define VEPU510_FRAME_OFFSET         (156 * sizeof(RK_U32))     /* 0x00000270 reg156  - 0x000003f4 reg253 */
+#define VEPU510_RC_ROI_OFFSET        (1024 * sizeof(RK_U32))    /* 0x00001000 reg1024 - 0x0000110c reg1091 */
+#define VEPU510_PARAM_OFFSET         (1472 * sizeof(RK_U32))    /* 0x00001700 reg1472 - 0x000019cc reg1651 */
+#define VEPU510_SQI_OFFSET           (2048 * sizeof(RK_U32))    /* 0x00002000 reg2048 - 0x0000212c reg2123 */
+#define VEPU510_SCL_OFFSET           (2176 * sizeof(RK_U32))    /* 0x00002200 reg2176 - 0x00002584 reg2401 */
+#define VEPU510_STATUS_OFFSET        (4096 * sizeof(RK_U32))    /* 0x00004000 reg4096 - 0x0000424c reg4243 */
+#define VEPU510_DBG_OFFSET           (5120 * sizeof(RK_U32))    /* 0x00005000 reg5120 - 0x00005230 reg5260 */
+#define VEPU510_REG_BASE_HW_STATUS   (0x2c)
+#define VEPU510_MAX_ROI_NUM          8
+#define VEPU510_SLICE_FIFO_LEN       8
+
+typedef struct Vepu510Online_t {
+    /* 0x00000270 reg156 */
+    struct {
+        RK_U32 reserved     : 4;
+        RK_U32 adr_vsy_t    : 28;
+    } adr_vsy_t;
+
+    /* 0x00000274 reg157 */
+    struct {
+        RK_U32 reserved     : 4;
+        RK_U32 adr_vsc_t    : 28;
+    } adr_vsc_t;
+
+    /* 0x00000278 reg158 */
+    struct {
+        RK_U32 reserved     : 4;
+        RK_U32 adr_vsy_b    : 28;
+    } adr_vsy_b;
+
+    /* 0x0000027c reg159 */
+    struct {
+        RK_U32 reserved     : 4;
+        RK_U32 adr_vsc_b    : 28;
+    } adr_vsc_b;
+} vepu510_online;
+
+typedef struct RdoSkipPar_t {
+    struct {
+        RK_U32 madp_thd0    : 12;
+        RK_U32 reserved     : 4;
+        RK_U32 madp_thd1    : 12;
+        RK_U32 reserved1    : 4;
+    } atf_thd0;
+
+    /* 0x00002064 reg2073 */
+    struct {
+        RK_U32 madp_thd2    : 12;
+        RK_U32 reserved     : 4;
+        RK_U32 madp_thd3    : 12;
+        RK_U32 reserved1    : 4;
+    } atf_thd1;
+
+    /* 0x00002068 reg2074 */
+    struct {
+        RK_U32 wgt0    : 8;
+        RK_U32 wgt1    : 8;
+        RK_U32 wgt2    : 8;
+        RK_U32 wgt3    : 8;
+    } atf_wgt0;
+
+    /* 0x0000206c reg2075 */
+    struct {
+        RK_U32 wgt4         : 8;
+        RK_U32 reserved     : 24;
+    } atf_wgt1;
+} rdo_skip_par;
+
+typedef struct RdoNoSkipPar_t {
+    /* 0x00002080 reg2080 */
+    struct {
+        RK_U32 madp_thd0    : 12;
+        RK_U32 reserved     : 4;
+        RK_U32 madp_thd1    : 12;
+        RK_U32 reserved1    : 4;
+    } ratf_thd0;
+
+    /* 0x00002084 reg2081 */
+    struct {
+        RK_U32 madp_thd2             : 12;
+        RK_U32 reserved              : 4;
+        RK_U32 atf_bypass_pri_flag   : 1;
+        RK_U32 reserved1             : 15;
+    } ratf_thd1;
+
+    /* 0x00002088 reg2082 */
+    struct {
+        RK_U32 wgt0    : 8;
+        RK_U32 wgt1    : 8;
+        RK_U32 wgt2    : 8;
+        RK_U32 wgt3    : 8;
+    } atf_wgt;
+} rdo_noskip_par;
+
+typedef struct Vepu510RoiRegion_t {
+    struct {
+        RK_U32 roi_lt_x    : 10;
+        RK_U32 reserved     : 6;
+        RK_U32 roi_lt_y    : 10;
+        RK_U32 reserved1    : 6;
+    } roi_pos_lt;
+
+    struct {
+        RK_U32 roi_rb_x    : 10;
+        RK_U32 reserved     : 6;
+        RK_U32 roi_rb_y    : 10;
+        RK_U32 reserved1    : 6;
+    } roi_pos_rb;
+
+    struct {
+        RK_U32 roi_qp_value       : 7;
+        RK_U32 roi_qp_adj_mode    : 1;
+        RK_U32 roi_pri            : 5;
+        RK_U32 roi_en             : 1;
+        RK_U32 reserved           : 18;
+    } roi_base;
+
+    struct {
+        RK_U32 roi_mdc_inter16         : 4;
+        RK_U32 roi_mdc_skip16          : 4;
+        RK_U32 roi_mdc_intra16         : 4;
+        RK_U32 roi0_mdc_inter32_hevc   : 4;
+        RK_U32 roi0_mdc_skip32_hevc    : 4;
+        RK_U32 roi0_mdc_intra32_hevc   : 4;
+        RK_U32 roi0_mdc_dpth_hevc      : 1;
+        RK_U32 reserved                : 7;
+    } roi_mdc;
+} Vepu510RoiRegion;
+
+typedef struct Vepu510RoiCfg_t {
+    /* 0x00001080 reg1056 */
+    struct {
+        RK_U32 fmdc_adju_inter16         : 4;
+        RK_U32 fmdc_adju_skip16          : 4;
+        RK_U32 fmdc_adju_intra16         : 4;
+        RK_U32 fmdc_adju_inter32         : 4;
+        RK_U32 fmdc_adju_skip32          : 4;
+        RK_U32 fmdc_adju_intra32         : 4;
+        RK_U32 fmdc_adj_pri              : 5;
+        RK_U32 reserved                  : 3;
+    } fmdc_adj0;
+
+    /* 0x00001084 reg1057 */
+    struct {
+        RK_U32 fmdc_adju_inter8         : 4;
+        RK_U32 fmdc_adju_skip8          : 4;
+        RK_U32 fmdc_adju_intra8         : 4;
+        RK_U32 reserved                 : 20;
+    } fmdc_adj1;
+
+    RK_U32 reserved_1058;
+
+    /* 0x0000108c reg1059 */
+    struct {
+        RK_U32 bmap_en               : 1;
+        RK_U32 bmap_pri              : 5;
+        RK_U32 bmap_qpmin            : 6;
+        RK_U32 bmap_qpmax            : 6;
+        RK_U32 bmap_mdc_dpth         : 1;
+        RK_U32 reserved              : 13;
+    } bmap_cfg;
+
+    /* 0x00001090 reg1060 - 0x0000110c reg1091 */
+    Vepu510RoiRegion regions[8];
+} Vepu510RoiCfg;
+
+/* class: control/link */
+/* 0x00000000 reg0 - 0x00000120 reg72 */
+typedef struct Vepu510ControlCfg_t {
+    /* 0x00000000 reg0 */
+    struct {
+        RK_U32 sub_ver      : 8;
+        RK_U32 h264_cap     : 1;
+        RK_U32 hevc_cap     : 1;
+        RK_U32 reserved     : 2;
+        RK_U32 res_cap      : 4;
+        RK_U32 osd_cap      : 2;
+        RK_U32 filtr_cap    : 2;
+        RK_U32 bfrm_cap     : 1;
+        RK_U32 fbc_cap      : 2;
+        RK_U32 reserved1    : 1;
+        RK_U32 ip_id        : 8;
+    } version;
+
+    /* 0x00000004 - 0x0000000c */
+    RK_U32 reserved1_3[3];
+
+    /* 0x00000010 reg4 */
+    struct {
+        RK_U32 lkt_num     : 8;
+        RK_U32 vepu_cmd    : 3;
+        RK_U32 reserved    : 21;
+    } enc_strt;
+
+    /* 0x00000014 reg5 */
+    struct {
+        RK_U32 safe_clr     : 1;
+        RK_U32 force_clr    : 1;
+        RK_U32 reserved     : 30;
+    } enc_clr;
+
+    /* 0x00000018 reg6 */
+    struct {
+        RK_U32 vswm_lcnt_soft    : 14;
+        RK_U32 vswm_fcnt_soft    : 8;
+        RK_U32 reserved          : 2;
+        RK_U32 dvbm_ack_soft     : 1;
+        RK_U32 dvbm_ack_sel      : 1;
+        RK_U32 dvbm_inf_sel      : 1;
+        RK_U32 reserved1         : 5;
+    } vs_ldly;
+
+    /* 0x0000001c */
+    RK_U32 reserved_7;
+
+    /* 0x00000020 reg8 */
+    struct {
+        RK_U32 enc_done_en          : 1;
+        RK_U32 lkt_node_done_en     : 1;
+        RK_U32 sclr_done_en         : 1;
+        RK_U32 vslc_done_en         : 1;
+        RK_U32 vbsf_oflw_en         : 1;
+        RK_U32 vbuf_lens_en         : 1;
+        RK_U32 enc_err_en           : 1;
+        RK_U32 vsrc_err_en          : 1;
+        RK_U32 wdg_en               : 1;
+        RK_U32 lkt_err_int_en       : 1;
+        RK_U32 lkt_err_stop_en      : 1;
+        RK_U32 lkt_force_stop_en    : 1;
+        RK_U32 jslc_done_en         : 1;
+        RK_U32 jbsf_oflw_en         : 1;
+        RK_U32 jbuf_lens_en         : 1;
+        RK_U32 dvbm_err_en          : 1;
+        RK_U32 reserved             : 16;
+    } int_en;
+
+    /* 0x00000024 reg9 */
+    struct {
+        RK_U32 enc_done_msk          : 1;
+        RK_U32 lkt_node_done_msk     : 1;
+        RK_U32 sclr_done_msk         : 1;
+        RK_U32 vslc_done_msk         : 1;
+        RK_U32 vbsf_oflw_msk         : 1;
+        RK_U32 vbuf_lens_msk         : 1;
+        RK_U32 enc_err_msk           : 1;
+        RK_U32 vsrc_err_msk          : 1;
+        RK_U32 wdg_msk               : 1;
+        RK_U32 lkt_err_int_msk       : 1;
+        RK_U32 lkt_err_stop_msk      : 1;
+        RK_U32 lkt_force_stop_msk    : 1;
+        RK_U32 jslc_done_msk         : 1;
+        RK_U32 jbsf_oflw_msk         : 1;
+        RK_U32 jbuf_lens_msk         : 1;
+        RK_U32 dvbm_err_msk          : 1;
+        RK_U32 reserved              : 16;
+    } int_msk;
+
+    /* 0x00000028 reg10 */
+    struct {
+        RK_U32 enc_done_clr          : 1;
+        RK_U32 lkt_node_done_clr     : 1;
+        RK_U32 sclr_done_clr         : 1;
+        RK_U32 vslc_done_clr         : 1;
+        RK_U32 vbsf_oflw_clr         : 1;
+        RK_U32 vbuf_lens_clr         : 1;
+        RK_U32 enc_err_clr           : 1;
+        RK_U32 vsrc_err_clr          : 1;
+        RK_U32 wdg_clr               : 1;
+        RK_U32 lkt_err_int_clr       : 1;
+        RK_U32 lkt_err_stop_clr      : 1;
+        RK_U32 lkt_force_stop_clr    : 1;
+        RK_U32 jslc_done_clr         : 1;
+        RK_U32 jbsf_oflw_clr         : 1;
+        RK_U32 jbuf_lens_clr         : 1;
+        RK_U32 dvbm_err_clr          : 1;
+        RK_U32 reserved              : 16;
+    } int_clr;
+
+    /* 0x0000002c reg11 */
+    struct {
+        RK_U32 enc_done_sta          : 1;
+        RK_U32 lkt_node_done_sta     : 1;
+        RK_U32 sclr_done_sta         : 1;
+        RK_U32 vslc_done_sta         : 1;
+        RK_U32 vbsf_oflw_sta         : 1;
+        RK_U32 vbuf_lens_sta         : 1;
+        RK_U32 enc_err_sta           : 1;
+        RK_U32 vsrc_err_sta          : 1;
+        RK_U32 wdg_sta               : 1;
+        RK_U32 lkt_err_int_sta       : 1;
+        RK_U32 lkt_err_stop_sta      : 1;
+        RK_U32 lkt_force_stop_sta    : 1;
+        RK_U32 jslc_done_sta         : 1;
+        RK_U32 jbsf_oflw_sta         : 1;
+        RK_U32 jbuf_lens_sta         : 1;
+        RK_U32 dvbm_err_sta          : 1;
+        RK_U32 reserved              : 16;
+    } int_sta;
+
+    /* 0x00000030 reg12 */
+    struct {
+        RK_U32 jpeg_bus_edin        : 4;
+        RK_U32 src_bus_edin         : 4;
+        RK_U32 meiw_bus_edin        : 4;
+        RK_U32 bsw_bus_edin         : 4;
+        RK_U32 reserved             : 8;
+        RK_U32 lktw_bus_edin        : 4;
+        RK_U32 rec_nfbc_bus_edin    : 4;
+    } dtrns_map;
+
+    /* 0x00000034 reg13 */
+    struct {
+        RK_U32 reserved        : 16;
+        RK_U32 axi_brsp_cke    : 10;
+        RK_U32 reserved1       : 6;
+    } dtrns_cfg;
+
+    /* 0x00000038 reg14 */
+    struct {
+        RK_U32 vs_load_thd    : 24;
+        RK_U32 reserved       : 8;
+    } enc_wdg;
+
+    /* 0x0000003c - 0x0000004c */
+    RK_U32 reserved15_19[5];
+
+    /* 0x00000050 reg20 */
+    struct {
+        RK_U32 idle_en_core    : 1;
+        RK_U32 idle_en_axi     : 1;
+        RK_U32 idle_en_ahb     : 1;
+        RK_U32 reserved        : 29;
+    } enc_idle_en;
+
+    /* 0x00000054 reg21 */
+    struct {
+        RK_U32 cke              : 1;
+        RK_U32 resetn_hw_en     : 1;
+        RK_U32 rfpr_err_e       : 1;
+        RK_U32 sram_ckg_en      : 1;
+        RK_U32 link_err_stop    : 1;
+        RK_U32 reserved         : 27;
+    } opt_strg;
+
+    /* 0x00000058 reg22 */
+    union {
+        struct {
+            RK_U32 tq8_ckg           : 1;
+            RK_U32 tq4_ckg           : 1;
+            RK_U32 bits_ckg_8x8      : 1;
+            RK_U32 bits_ckg_4x4_1    : 1;
+            RK_U32 bits_ckg_4x4_0    : 1;
+            RK_U32 inter_mode_ckg    : 1;
+            RK_U32 inter_ctrl_ckg    : 1;
+            RK_U32 inter_pred_ckg    : 1;
+            RK_U32 intra8_ckg        : 1;
+            RK_U32 intra4_ckg        : 1;
+            RK_U32 reserved          : 22;
+        } h264;
+        struct {
+            RK_U32 recon32_ckg       : 1;
+            RK_U32 iqit32_ckg        : 1;
+            RK_U32 q32_ckg           : 1;
+            RK_U32 t32_ckg           : 1;
+            RK_U32 cabac32_ckg       : 1;
+            RK_U32 recon16_ckg       : 1;
+            RK_U32 iqit16_ckg        : 1;
+            RK_U32 q16_ckg           : 1;
+            RK_U32 t16_ckg           : 1;
+            RK_U32 cabac16_ckg       : 1;
+            RK_U32 recon8_ckg        : 1;
+            RK_U32 iqit8_ckg         : 1;
+            RK_U32 q8_ckg            : 1;
+            RK_U32 t8_ckg            : 1;
+            RK_U32 cabac8_ckg        : 1;
+            RK_U32 recon4_ckg        : 1;
+            RK_U32 iqit4_ckg         : 1;
+            RK_U32 q4_ckg            : 1;
+            RK_U32 t4_ckg            : 1;
+            RK_U32 cabac4_ckg        : 1;
+            RK_U32 intra32_ckg       : 1;
+            RK_U32 intra16_ckg       : 1;
+            RK_U32 intra8_ckg        : 1;
+            RK_U32 intra4_ckg        : 1;
+            RK_U32 inter_pred_ckg    : 1;
+            RK_U32 reserved          : 7;
+        } hevc;
+    } rdo_ckg;
+
+    /* 0x0000005c reg23 */
+    struct {
+        RK_U32 core_id     : 2;
+        RK_U32 reserved    : 30;
+    } core_id;
+} Vepu510ControlCfg;
+
+/* 0x00000270 reg156  - 0x0000039c reg231 */
+typedef struct Vepu510FrmCommon_t {
+    /* 0x00000270 reg156 - 0x0000027c reg159 */
+    vepu510_online online_addr;
+
+    /* 0x00000280 reg160 */
+    RK_U32 adr_src0;
+
+    /* 0x00000284 reg161 */
+    RK_U32 adr_src1;
+
+    /* 0x00000288 reg162 */
+    RK_U32 adr_src2;
+
+    /* 0x0000028c reg163 */
+    RK_U32 rfpw_h_addr;
+
+    /* 0x00000290 reg164 */
+    RK_U32 rfpw_b_addr;
+
+    /* 0x00000294 reg165 */
+    RK_U32 rfpr_h_addr;
+
+    /* 0x00000298 reg166 */
+    RK_U32 rfpr_b_addr;
+
+    /* 0x0000029c reg167 */
+    RK_U32 colmvw_addr;
+
+    /* 0x000002a0 reg168 */
+    RK_U32 colmvr_addr;
+
+    /* 0x000002a4 reg169 */
+    RK_U32 dspw_addr;
+
+    /* 0x000002a8 reg170 */
+    RK_U32 dspr_addr;
+
+    /* 0x000002ac reg171 */
+    RK_U32 meiw_addr;
+
+    /* 0x000002b0 reg172 */
+    RK_U32 bsbt_addr;
+
+    /* 0x000002b4 reg173 */
+    RK_U32 bsbb_addr;
+
+    /* 0x000002b8 reg174 */
+    RK_U32 adr_bsbs;
+
+    /* 0x000002bc reg175 */
+    RK_U32 bsbr_addr;
+
+    /* 0x000002c0 reg176 */
+    RK_U32 lpfw_addr;
+
+    /* 0x000002c4 reg177 */
+    RK_U32 lpfr_addr;
+
+    /* 0x000002c8 reg178 */
+    RK_U32 ebuft_addr;
+
+    /* 0x000002cc reg179 */
+    RK_U32 ebufb_addr;
+
+    /* 0x000002d0 reg180 */
+    RK_U32 rfpt_h_addr;
+
+    /* 0x000002d4 reg181 */
+    RK_U32 rfpb_h_addr;
+
+    /* 0x000002d8 reg182 */
+    RK_U32 rfpt_b_addr;
+
+    /* 0x000002dc reg183 */
+    RK_U32 adr_rfpb_b;
+
+    /* 0x000002e0 reg184 */
+    RK_U32 adr_smear_rd;
+
+    /* 0x000002e4 reg185 */
+    RK_U32 adr_smear_wr;
+
+    /* 0x000002e8 reg186 */
+    RK_U32 adr_roir;
+
+    /* 0x2ec - 0x2fc */
+    RK_U32 reserved187_191[5];
+
+    /* 0x00000300 reg192 */
+    struct {
+        RK_U32 enc_stnd                : 2;
+        RK_U32 cur_frm_ref             : 1;
+        RK_U32 mei_stor                : 1;
+        RK_U32 bs_scp                  : 1;
+        RK_U32 reserved                : 3;
+        RK_U32 pic_qp                  : 6;
+        RK_U32 num_pic_tot_cur_hevc    : 5;
+        RK_U32 log2_ctu_num_hevc       : 5;
+        RK_U32 reserved1               : 6;
+        RK_U32 slen_fifo               : 1;
+        RK_U32 rec_fbc_dis             : 1;
+    } enc_pic;
+
+    /* 0x00000304 reg193 */
+    struct {
+        RK_U32 dchs_txid    : 2;
+        RK_U32 dchs_rxid    : 2;
+        RK_U32 dchs_txe     : 1;
+        RK_U32 dchs_rxe     : 1;
+        RK_U32 reserved     : 2;
+        RK_U32 dchs_dly     : 8;
+        RK_U32 dchs_ofst    : 10;
+        RK_U32 reserved1    : 6;
+    } dual_core;
+
+    /* 0x00000308 reg194 */
+    struct {
+        RK_U32 frame_id        : 8;
+        RK_U32 frm_id_match    : 1;
+        RK_U32 reserved        : 7;
+        RK_U32 ch_id           : 2;
+        RK_U32 vrsp_rtn_en     : 1;
+        RK_U32 vinf_req_en     : 1;
+        RK_U32 reserved1       : 12;
+    } enc_id;
+
+    /* 0x0000030c reg195 */
+    RK_U32 bsp_size;
+
+    /* 0x00000310 reg196 */
+    struct {
+        RK_U32 pic_wd8_m1    : 11;
+        RK_U32 reserved      : 5;
+        RK_U32 pic_hd8_m1    : 11;
+        RK_U32 reserved1     : 5;
+    } enc_rsl;
+
+    /* 0x00000314 reg197 */
+    struct {
+        RK_U32 pic_wfill    : 6;
+        RK_U32 reserved     : 10;
+        RK_U32 pic_hfill    : 6;
+        RK_U32 reserved1    : 10;
+    } src_fill;
+
+    /* 0x00000318 reg198 */
+    struct {
+        RK_U32 alpha_swap            : 1;
+        RK_U32 rbuv_swap             : 1;
+        RK_U32 src_cfmt              : 4;
+        RK_U32 src_rcne              : 1;
+        RK_U32 out_fmt               : 1;
+        RK_U32 src_range_trns_en     : 1;
+        RK_U32 src_range_trns_sel    : 1;
+        RK_U32 chroma_ds_mode        : 1;
+        RK_U32 reserved              : 21;
+    } src_fmt;
+
+    /* 0x0000031c reg199 */
+    struct {
+        RK_U32 csc_wgt_b2y    : 9;
+        RK_U32 csc_wgt_g2y    : 9;
+        RK_U32 csc_wgt_r2y    : 9;
+        RK_U32 reserved       : 5;
+    } src_udfy;
+
+    /* 0x00000320 reg200 */
+    struct {
+        RK_U32 csc_wgt_b2u    : 9;
+        RK_U32 csc_wgt_g2u    : 9;
+        RK_U32 csc_wgt_r2u    : 9;
+        RK_U32 reserved       : 5;
+    } src_udfu;
+
+    /* 0x00000324 reg201 */
+    struct {
+        RK_U32 csc_wgt_b2v    : 9;
+        RK_U32 csc_wgt_g2v    : 9;
+        RK_U32 csc_wgt_r2v    : 9;
+        RK_U32 reserved       : 5;
+    } src_udfv;
+
+    /* 0x00000328 reg202 */
+    struct {
+        RK_U32 csc_ofst_v    : 8;
+        RK_U32 csc_ofst_u    : 8;
+        RK_U32 csc_ofst_y    : 5;
+        RK_U32 reserved      : 11;
+    } src_udfo;
+
+    /* 0x0000032c reg203 */
+    struct {
+        RK_U32 cr_force_value     : 8;
+        RK_U32 cb_force_value     : 8;
+        RK_U32 chroma_force_en    : 1;
+        RK_U32 reserved           : 9;
+        RK_U32 src_mirr           : 1;
+        RK_U32 src_rot            : 2;
+        RK_U32 tile4x4_en         : 1;
+        RK_U32 reserved1          : 2;
+    } src_proc;
+
+    /* 0x00000330 reg204 */
+    struct {
+        RK_U32 pic_ofst_x    : 14;
+        RK_U32 reserved      : 2;
+        RK_U32 pic_ofst_y    : 14;
+        RK_U32 reserved1     : 2;
+    } pic_ofst;
+
+    /* 0x00000334 reg205 */
+    struct {
+        RK_U32 src_strd0    : 21;
+        RK_U32 reserved     : 11;
+    } src_strd0;
+
+    /* 0x00000338 reg206 */
+    struct {
+        RK_U32 src_strd1    : 16;
+        RK_U32 reserved     : 16;
+    } src_strd1;
+
+    /* 0x33c - 0x34c */
+    RK_U32 reserved207_211[5];
+
+    /* 0x00000350 reg212 */
+    struct {
+        RK_U32 rc_en         : 1;
+        RK_U32 aq_en         : 1;
+        RK_U32 reserved      : 10;
+        RK_U32 rc_ctu_num    : 20;
+    } rc_cfg;
+
+    /* 0x00000354 reg213 */
+    struct {
+        RK_U32 reserved       : 16;
+        RK_U32 rc_qp_range    : 4;
+        RK_U32 rc_max_qp      : 6;
+        RK_U32 rc_min_qp      : 6;
+    } rc_qp;
+
+    /* 0x00000358 reg214 */
+    struct {
+        RK_U32 ctu_ebit    : 20;
+        RK_U32 reserved    : 12;
+    } rc_tgt;
+
+    /* 0x35c */
+    RK_U32 reserved_215;
+
+    /* 0x00000360 reg216 */
+    struct {
+        RK_U32 sli_splt          : 1;
+        RK_U32 sli_splt_mode     : 1;
+        RK_U32 sli_splt_cpst     : 1;
+        RK_U32 reserved          : 12;
+        RK_U32 sli_flsh          : 1;
+        RK_U32 sli_max_num_m1    : 15;
+        RK_U32 reserved1         : 1;
+    } sli_splt;
+
+    /* 0x00000364 reg217 */
+    struct {
+        RK_U32 sli_splt_byte    : 20;
+        RK_U32 reserved         : 12;
+    } sli_byte;
+
+    /* 0x00000368 reg218 */
+    struct {
+        RK_U32 sli_splt_cnum_m1    : 20;
+        RK_U32 reserved            : 12;
+    } sli_cnum;
+
+    /* 0x0000036c reg219 */
+    struct {
+        RK_U32 uvc_partition0_len    : 12;
+        RK_U32 uvc_partition_len     : 12;
+        RK_U32 uvc_skip_len          : 6;
+        RK_U32 reserved              : 2;
+    } vbs_pad;
+
+    /* 0x00000370 reg220 */
+    struct {
+        RK_U32 cime_srch_dwnh    : 4;
+        RK_U32 cime_srch_uph     : 4;
+        RK_U32 cime_srch_rgtw    : 4;
+        RK_U32 cime_srch_lftw    : 4;
+        RK_U32 dlt_frm_num       : 16;
+    } me_rnge;
+
+    /* 0x00000374 reg221 */
+    struct {
+        RK_U32 srgn_max_num      : 7;
+        RK_U32 cime_dist_thre    : 13;
+        RK_U32 rme_srch_h        : 2;
+        RK_U32 rme_srch_v        : 2;
+        RK_U32 rme_dis           : 3;
+        RK_U32 reserved          : 1;
+        RK_U32 fme_dis           : 3;
+        RK_U32 reserved1         : 1;
+    } me_cfg;
+
+    /* 0x00000378 reg222 */
+    struct {
+        RK_U32 cime_zero_thre     : 13;
+        RK_U32 reserved           : 15;
+        RK_U32 fme_prefsu_en      : 2;
+        RK_U32 colmv_stor_hevc    : 1;
+        RK_U32 colmv_load_hevc    : 1;
+    } me_cach;
+
+    /* 0x37c - 0x39c */
+    RK_U32 reserved223_231[9];
+} Vepu510FrmCommon;
+
+/* class: rc/roi/aq/klut */
+/* 0x00001000 reg1024 - 0x0000110c reg1091 */
+typedef struct Vepu510RcRoi_t {
+    /* 0x00001000 reg1024 */
+    struct {
+        RK_U32 qp_adj0     : 5;
+        RK_U32 qp_adj1     : 5;
+        RK_U32 qp_adj2     : 5;
+        RK_U32 qp_adj3     : 5;
+        RK_U32 qp_adj4     : 5;
+        RK_U32 reserved    : 7;
+    } rc_adj0;
+
+    /* 0x00001004 reg1025 */
+    struct {
+        RK_U32 qp_adj5     : 5;
+        RK_U32 qp_adj6     : 5;
+        RK_U32 qp_adj7     : 5;
+        RK_U32 qp_adj8     : 5;
+        RK_U32 reserved    : 12;
+    } rc_adj1;
+
+    /* 0x00001008 reg1026 - 0x00001028 reg1034 */
+    RK_U32 rc_dthd_0_8[9];
+
+    /* 0x102c */
+    RK_U32 reserved_1035;
+
+    /* 0x00001030 reg1036 */
+    struct {
+        RK_U32 qpmin_area0    : 6;
+        RK_U32 qpmax_area0    : 6;
+        RK_U32 qpmin_area1    : 6;
+        RK_U32 qpmax_area1    : 6;
+        RK_U32 qpmin_area2    : 6;
+        RK_U32 reserved       : 2;
+    } roi_qthd0;
+
+    /* 0x00001034 reg1037 */
+    struct {
+        RK_U32 qpmax_area2    : 6;
+        RK_U32 qpmin_area3    : 6;
+        RK_U32 qpmax_area3    : 6;
+        RK_U32 qpmin_area4    : 6;
+        RK_U32 qpmax_area4    : 6;
+        RK_U32 reserved       : 2;
+    } roi_qthd1;
+
+    /* 0x00001038 reg1038 */
+    struct {
+        RK_U32 qpmin_area5    : 6;
+        RK_U32 qpmax_area5    : 6;
+        RK_U32 qpmin_area6    : 6;
+        RK_U32 qpmax_area6    : 6;
+        RK_U32 qpmin_area7    : 6;
+        RK_U32 reserved       : 2;
+    } roi_qthd2;
+
+    /* 0x0000103c reg1039 */
+    struct {
+        RK_U32 qpmax_area7    : 6;
+        RK_U32 reserved       : 24;
+        RK_U32 qpmap_mode     : 2;
+    } roi_qthd3;
+
+    /* 0x00001040 reg1040 */
+    RK_U32 reserved_1040;
+
+    /* 0x00001044 reg1041 */
+    struct {
+        RK_U32 aq_tthd0    : 8;
+        RK_U32 aq_tthd1    : 8;
+        RK_U32 aq_tthd2    : 8;
+        RK_U32 aq_tthd3    : 8;
+    } aq_tthd0;
+
+    /* 0x00001048 reg1042 */
+    struct {
+        RK_U32 aq_tthd4    : 8;
+        RK_U32 aq_tthd5    : 8;
+        RK_U32 aq_tthd6    : 8;
+        RK_U32 aq_tthd7    : 8;
+    } aq_tthd1;
+
+    /* 0x0000104c reg1043 */
+    struct {
+        RK_U32 aq_tthd8     : 8;
+        RK_U32 aq_tthd9     : 8;
+        RK_U32 aq_tthd10    : 8;
+        RK_U32 aq_tthd11    : 8;
+    } aq_tthd2;
+
+    /* 0x00001050 reg1044 */
+    struct {
+        RK_U32 aq_tthd12    : 8;
+        RK_U32 aq_tthd13    : 8;
+        RK_U32 aq_tthd14    : 8;
+        RK_U32 aq_tthd15    : 8;
+    } aq_tthd3;
+
+    /* 0x00001054 reg1045 */
+    struct {
+        RK_S32 aq_stp_s0     : 5;
+        RK_S32 aq_stp_0t1    : 5;
+        RK_S32 aq_stp_1t2    : 5;
+        RK_S32 aq_stp_2t3    : 5;
+        RK_S32 aq_stp_3t4    : 5;
+        RK_S32 aq_stp_4t5    : 5;
+        RK_S32 reserved      : 2;
+    } aq_stp0;
+
+    /* 0x00001058 reg1046 */
+    struct {
+        RK_S32 aq_stp_5t6      : 5;
+        RK_S32 aq_stp_6t7      : 5;
+        RK_S32 aq_stp_7t8      : 5;
+        RK_S32 aq_stp_8t9      : 5;
+        RK_S32 aq_stp_9t10     : 5;
+        RK_S32 aq_stp_10t11    : 5;
+        RK_S32 reserved        : 2;
+    } aq_stp1;
+
+    /* 0x0000105c reg1047 */
+    struct {
+        RK_S32 aq_stp_11t12    : 5;
+        RK_S32 aq_stp_12t13    : 5;
+        RK_S32 aq_stp_13t14    : 5;
+        RK_S32 aq_stp_14t15    : 5;
+        RK_S32 aq_stp_b15      : 5;
+        RK_U32 reserved        : 7;
+    } aq_stp2;
+
+    /* 0x00001060 reg1048 */
+    struct {
+        RK_U32 aq16_rnge         : 4;
+        RK_U32 aq32_rnge         : 4;
+        RK_U32 aq8_rnge          : 5;
+        RK_U32 aq16_dif0         : 5;
+        RK_U32 aq16_dif1         : 5;
+        RK_U32 reserved          : 1;
+        RK_U32 aq_cme_en         : 1;
+        RK_U32 aq_subj_cme_en    : 1;
+        RK_U32 aq_rme_en         : 1;
+        RK_U32 aq_subj_rme_en    : 1;
+        RK_U32 reserved1         : 4;
+    } aq_clip;
+
+    /* 0x00001064 reg1049 */
+    struct {
+        RK_U32 madi_th0    : 8;
+        RK_U32 madi_th1    : 8;
+        RK_U32 madi_th2    : 8;
+        RK_U32 reserved    : 8;
+    } madi_st_thd;
+
+    /* 0x00001068 reg1050 */
+    struct {
+        RK_U32 madp_th0     : 12;
+        RK_U32 reserved     : 4;
+        RK_U32 madp_th1     : 12;
+        RK_U32 reserved1    : 4;
+    } madp_st_thd0;
+
+    /* 0x0000106c reg1051 */
+    struct {
+        RK_U32 madp_th2    : 12;
+        RK_U32 reserved    : 20;
+    } madp_st_thd1;
+
+    /* 0x1070 - 0x1078 */
+    RK_U32 reserved1052_1054[3];
+
+    /* 0x0000107c reg1055 */
+    struct {
+        RK_U32 chrm_klut_ofst                : 4;
+        RK_U32 reserved                      : 4;
+        RK_U32 inter_chrm_dist_multi         : 6;
+        RK_U32 reserved1                     : 18;
+    } klut_ofst;
+
+    /*0x00001080 reg1056 - 0x0000110c reg1091 */
+    Vepu510RoiCfg roi_cfg;
+} Vepu510RcRoi;
+
+/* class: scaling list  */
+/* 0x00002200 reg2176- 0x00002584 reg2401*/
+typedef struct Vepu510SclCfg_t {
+    /* 0x2200 - 0x221F, valid for h.264/h.h265, jpeg no use */
+    RK_U32 tu8_intra_y[16];
+    RK_U32 tu8_intra_u[16]; /* tu8_inter_y[16] for h.264 */
+
+    /* 0x2220 - 0x2584, valid for h.265 only */
+    RK_U32 tu8_intra_v[16];
+    RK_U32 tu8_inter_y[16];
+    RK_U32 tu8_inter_u[16];
+    RK_U32 tu8_inter_v[16];
+    RK_U32 tu16_intra_y_ac[16];
+    RK_U32 tu16_intra_u_ac[16];
+    RK_U32 tu16_intra_v_ac[16];
+    RK_U32 tu16_inter_y_ac[16];
+    RK_U32 tu16_inter_u_ac[16];
+    RK_U32 tu16_inter_v_ac[16];
+    RK_U32 tu32_intra_y_ac[16];
+    RK_U32 tu32_inter_y_ac[16];
+
+    /* 0x2580 */
+    struct {
+        RK_U32 tu16_intra_y_dc  : 8;
+        RK_U32 tu16_intra_u_dc  : 8;
+        RK_U32 tu16_intra_v_dc  : 8;
+        RK_U32 tu16_inter_y_dc  : 8;
+    } tu_dc0;
+
+    /* 0x2584 */
+    struct {
+        RK_U32 tu16_inter_u_dc  : 8;
+        RK_U32 tu16_inter_v_dc  : 8;
+        RK_U32 tu32_intra_y_dc  : 8;
+        RK_U32 tu32_inter_y_dc  : 8;
+    } tu_dc1;
+} Vepu510SclCfg;
+
+/* class: st */
+/* 0x00004000 reg4096 - 0x0000424c reg4243*/
+typedef struct Vepu510Status_t {
+    /* 0x00004000 reg4096 */
+    RK_U32 bs_lgth_l32;
+
+    /* 0x00004004 reg4097 */
+    struct {
+        RK_U32 bs_lgth_h8    : 8;
+        RK_U32 reserved      : 8;
+        RK_U32 sse_l16       : 16;
+    } st_sse_bsl;
+
+    /* 0x00004008 reg4098 */
+    RK_U32 sse_h32;
+
+    /* 0x0000400c reg4099 */
+    RK_U32 qp_sum;
+
+    /* 0x00004010 reg4100 */
+    struct {
+        RK_U32 sao_cnum    : 16;
+        RK_U32 sao_ynum    : 16;
+    } st_sao;
+
+    /* 0x00004014 reg4101 */
+    RK_U32 rdo_head_bits;
+
+    /* 0x00004018 reg4102 */
+    struct {
+        RK_U32 rdo_head_bits_h8    : 8;
+        RK_U32 reserved            : 8;
+        RK_U32 rdo_res_bits_l16    : 16;
+    } st_head_res_bl;
+
+    /* 0x0000401c reg4103 */
+    RK_U32 rdo_res_bits_h24;
+
+    /* 0x00004020 reg4104 */
+    struct {
+        RK_U32 st_enc             : 2;
+        RK_U32 st_sclr            : 1;
+        RK_U32 isp_src_oflw       : 1;
+        RK_U32 vepu_src_oflw      : 1;
+        RK_U32 vepu_fcnt_nmch     : 1;
+        RK_U32 vepu_fbd_err       : 5;
+        RK_U32 reserved           : 5;
+        RK_U32 dvbm_finf_wful     : 1;
+        RK_U32 dvbm_linf_wful     : 1;
+        RK_U32 dvbm_fcnt_late     : 1;
+        RK_U32 dvbm_fcnt_early    : 1;
+        RK_U32 dvbm_isp_oflw      : 1;
+        RK_U32 dvbm_vepu_oflw     : 1;
+        RK_U32 isp_time_out       : 1;
+        RK_U32 dvbm_vsrc_fcnt     : 1;
+        RK_U32 reserved1          : 8;
+    } st_enc;
+
+    /* 0x00004024 reg4105 */
+    struct {
+        RK_U32 fnum_cfg_done    : 8;
+        RK_U32 fnum_cfg         : 8;
+        RK_U32 fnum_int         : 8;
+        RK_U32 fnum_enc_done    : 8;
+    } st_lkt;
+
+    /* 0x00004028 reg4106 */
+    struct {
+        RK_U32 reserved     : 4;
+        RK_U32 node_addr    : 28;
+    } st_nadr;
+
+    /* 0x0000402c reg4107 */
+    struct {
+        RK_U32 bsbw_ovfl    : 1;
+        RK_U32 reserved     : 2;
+        RK_U32 bsbw_addr    : 28;
+        RK_U32 reserved1    : 1;
+    } st_bsb;
+
+    /* 0x00004030 reg4108 */
+    struct {
+        RK_U32 axib_idl     : 8;
+        RK_U32 axib_ovfl    : 8;
+        RK_U32 axib_err     : 8;
+        RK_U32 axir_err     : 8;
+    } st_bus;
+
+    /* 0x00004034 reg4109 */
+    struct {
+        RK_U32 sli_num_video     : 6;
+        RK_U32 sli_num_jpeg      : 6;
+        RK_U32 reserved          : 4;
+        RK_U32 bpkt_num_video    : 7;
+        RK_U32 bpkt_lst_video    : 1;
+        RK_U32 bpkt_num_jpeg     : 7;
+        RK_U32 bpkt_lst_jpeg     : 1;
+    } st_snum;
+
+    /* 0x00004038 reg4110 */
+    struct {
+        RK_U32 sli_len    : 31;
+        RK_U32 sli_lst    : 1;
+    } st_slen;
+
+    /* 0x403c - reg4111 */
+    struct {
+        RK_U32 task_id_proc     : 12;
+        RK_U32 task_id_done     : 12;
+        RK_U32 task_done        : 1;
+        RK_U32 task_lkt_err     : 3;
+        RK_U32 reserved         : 4;
+    } st_link_task;
+
+    /* 0x4040 - 0x405c */
+    RK_U32 reserved4111_4119[8];
+
+    /* 0x00004060 reg4120 */
+    struct {
+        RK_U32 sli_len_jpeg    : 31;
+        RK_U32 sli_lst_jpeg    : 1;
+    } st_slen_jpeg;
+
+    /* 0x00004064 reg4121 */
+    RK_U32 jpeg_head_bits_l32;
+
+    /* 0x00004068 reg4122 */
+    struct {
+        RK_U32 jpeg_head_bits_h8    : 1;
+        RK_U32 reserved             : 31;
+    } st_bsl_h8_jpeg;
+
+    /* 0x0000406c reg4123 */
+    struct {
+        RK_U32 jbsbw_ovfl    : 1;
+        RK_U32 reserved      : 2;
+        RK_U32 jbsbw_addr    : 28;
+        RK_U32 reserved1     : 1;
+    } st_jbsb;
+
+    /* 0x4070 - 0x407c */
+    RK_U32 reserved4124_4127[4];
+
+    /* 0x00004080 reg4128 */
+    struct {
+        RK_U32 pnum_p64    : 17;
+        RK_U32 reserved    : 15;
+    } st_pnum_p64;
+
+    /* 0x00004084 reg4129 */
+    struct {
+        RK_U32 pnum_p32    : 19;
+        RK_U32 reserved    : 13;
+    } st_pnum_p32;
+
+    /* 0x00004088 reg4130 */
+    struct {
+        RK_U32 pnum_p16    : 21;
+        RK_U32 reserved    : 11;
+    } st_pnum_p16;
+
+    /* 0x0000408c reg4131 */
+    struct {
+        RK_U32 pnum_p8     : 23;
+        RK_U32 reserved    : 9;
+    } st_pnum_p8;
+
+    /* 0x00004090 reg4132 */
+    struct {
+        RK_U32 pnum_i32    : 19;
+        RK_U32 reserved    : 13;
+    } st_pnum_i32;
+
+    /* 0x00004094 reg4133 */
+    struct {
+        RK_U32 pnum_i16    : 21;
+        RK_U32 reserved    : 11;
+    } st_pnum_i16;
+
+    /* 0x00004098 reg4134 */
+    struct {
+        RK_U32 pnum_i8     : 23;
+        RK_U32 reserved    : 9;
+    } st_pnum_i8;
+
+    /* 0x0000409c reg4135 */
+    struct {
+        RK_U32 pnum_i4     : 23;
+        RK_U32 reserved    : 9;
+    } st_pnum_i4;
+
+    /* 0x000040a0 reg4136 */
+    struct {
+        RK_U32 num_b16     : 23;
+        RK_U32 reserved    : 9;
+    } st_bnum_b16;
+
+    /* 0x000040a4 reg4137 */
+    struct {
+        RK_U32 rdo_smear_cnt0  : 8;
+        RK_U32 rdo_smear_cnt1  : 8;
+        RK_U32 rdo_smear_cnt2  : 8;
+        RK_U32 rdo_smear_cnt3  : 8;
+    } st_smear_cnt;
+
+    /* 0x000040a8 reg4138 */
+    RK_U32 madi16_sum;
+
+    /* 0x000040ac reg4139 */
+    RK_U32 madi32_sum;
+
+    /* 0x000040b0 reg4140 */
+    RK_U32 madp16_sum;
+
+    /* 0x40b4 - 0x40bc */
+    RK_U32 reserved4141_4143[3];
+
+    /* 0x000040c0 reg4144 */
+    struct {
+        RK_U32 madi_th_lt_cnt0    : 16;
+        RK_U32 madi_th_lt_cnt1    : 16;
+    } st_madi_lt_num0;
+
+    /* 0x000040c4 reg4145 */
+    struct {
+        RK_U32 madi_th_lt_cnt2    : 16;
+        RK_U32 madi_th_lt_cnt3    : 16;
+    } st_madi_lt_num1;
+
+    /* 0x000040c8 reg4146 */
+    struct {
+        RK_U32 madi_th_rt_cnt0    : 16;
+        RK_U32 madi_th_rt_cnt1    : 16;
+    } st_madi_rt_num0;
+
+    /* 0x000040cc reg4147 */
+    struct {
+        RK_U32 madi_th_rt_cnt2    : 16;
+        RK_U32 madi_th_rt_cnt3    : 16;
+    } st_madi_rt_num1;
+
+    /* 0x000040d0 reg4148 */
+    struct {
+        RK_U32 madi_th_lb_cnt0    : 16;
+        RK_U32 madi_th_lb_cnt1    : 16;
+    } st_madi_lb_num0;
+
+    /* 0x000040d4 reg4149 */
+    struct {
+        RK_U32 madi_th_lb_cnt2    : 16;
+        RK_U32 madi_th_lb_cnt3    : 16;
+    } st_madi_lb_num1;
+
+    /* 0x000040d8 reg4150 */
+    struct {
+        RK_U32 madi_th_rb_cnt0    : 16;
+        RK_U32 madi_th_rb_cnt1    : 16;
+    } st_madi_rb_num0;
+
+    /* 0x000040dc reg4151 */
+    struct {
+        RK_U32 madi_th_rb_cnt2    : 16;
+        RK_U32 madi_th_rb_cnt3    : 16;
+    } st_madi_rb_num1;
+
+    /* 0x000040e0 reg4152 */
+    struct {
+        RK_U32 madp_th_lt_cnt0    : 16;
+        RK_U32 madp_th_lt_cnt1    : 16;
+    } st_madp_lt_num0;
+
+    /* 0x000040e4 reg4153 */
+    struct {
+        RK_U32 madp_th_lt_cnt2    : 16;
+        RK_U32 madp_th_lt_cnt3    : 16;
+    } st_madp_lt_num1;
+
+    /* 0x000040e8 reg4154 */
+    struct {
+        RK_U32 madp_th_rt_cnt0    : 16;
+        RK_U32 madp_th_rt_cnt1    : 16;
+    } st_madp_rt_num0;
+
+    /* 0x000040ec reg4155 */
+    struct {
+        RK_U32 madp_th_rt_cnt2    : 16;
+        RK_U32 madp_th_rt_cnt3    : 16;
+    } st_madp_rt_num1;
+
+    /* 0x000040f0 reg4156 */
+    struct {
+        RK_U32 madp_th_lb_cnt0    : 16;
+        RK_U32 madp_th_lb_cnt1    : 16;
+    } st_madp_lb_num0;
+
+    /* 0x000040f4 reg4157 */
+    struct {
+        RK_U32 madp_th_lb_cnt2    : 16;
+        RK_U32 madp_th_lb_cnt3    : 16;
+    } st_madp_lb_num1;
+
+    /* 0x000040f8 reg4158 */
+    struct {
+        RK_U32 madp_th_rb_cnt0    : 16;
+        RK_U32 madp_th_rb_cnt1    : 16;
+    } st_madp_rb_num0;
+
+    /* 0x000040fc reg4159 */
+    struct {
+        RK_U32 madp_th_rb_cnt2    : 16;
+        RK_U32 madp_th_rb_cnt3    : 16;
+    } st_madp_rb_num1;
+
+    /* 0x00004100 reg4160 */
+    struct {
+        RK_U32 cmv_th_lt_cnt0    : 16;
+        RK_U32 cmv_th_lt_cnt1    : 16;
+    } st_cmv_lt_num0;
+
+    /* 0x00004104 reg4161 */
+    struct {
+        RK_U32 cmv_th_lt_cnt2    : 16;
+        RK_U32 cmv_th_lt_cnt3    : 16;
+    } st_cmv_lt_num1;
+
+    /* 0x00004108 reg4162 */
+    struct {
+        RK_U32 cmv_th_rt_cnt0    : 16;
+        RK_U32 cmv_th_rt_cnt1    : 16;
+    } st_cmv_rt_num0;
+
+    /* 0x0000410c reg4163 */
+    struct {
+        RK_U32 cmv_th_rt_cnt2    : 16;
+        RK_U32 cmv_th_rt_cnt3    : 16;
+    } st_cmv_rt_num1;
+
+    /* 0x00004110 reg4164 */
+    struct {
+        RK_U32 cmv_th_lb_cnt0    : 16;
+        RK_U32 cmv_th_lb_cnt1    : 16;
+    } st_cmv_lb_num0;
+
+    /* 0x00004114 reg4165 */
+    struct {
+        RK_U32 cmv_th_lb_cnt2    : 16;
+        RK_U32 cmv_th_lb_cnt3    : 16;
+    } st_cmv_lb_num1;
+
+    /* 0x00004118 reg4166 */
+    struct {
+        RK_U32 cmv_th_rb_cnt0    : 16;
+        RK_U32 cmv_th_rb_cnt1    : 16;
+    } st_cmv_rb_num0;
+
+    /* 0x0000411c reg4167 */
+    struct {
+        RK_U32 cmv_th_rb_cnt2    : 16;
+        RK_U32 cmv_th_rb_cnt3    : 16;
+    } st_cmv_rb_num1;
+
+    /* 0x00004120 reg4168 */
+    struct {
+        RK_U32 org_y_r_max_value    : 8;
+        RK_U32 org_y_r_min_value    : 8;
+        RK_U32 org_u_g_max_value    : 8;
+        RK_U32 org_u_g_min_value    : 8;
+    } st_vsp_org_value0;
+
+    /* 0x00004124 reg4169 */
+    struct {
+        RK_U32 org_v_b_max_value    : 8;
+        RK_U32 org_v_b_min_value    : 8;
+        RK_U32 reserved             : 16;
+    } st_vsp_org_value1;
+
+    /* 0x4128 - 0x412c */
+    RK_U32 reserved4170_4171[2];
+
+    /* 0x00004130 reg4172 */
+    RK_U32 dsp_y_sum;
+
+    /* 0x00004134 reg4173 */
+    RK_U32 acc_zero_mv;
+
+    /* 0x00004138 reg4174 */
+    RK_U32 acc_dist0;
+
+    /* 0x0000413c reg4175 */
+    RK_U32 acc_block_num;
+
+    /* 0x00004140 reg4176 */
+    struct {
+        RK_U32 num0_point_skin    : 15;
+        RK_U32 acc_cmplx_num      : 17;
+    } st_skin_sum0;
+
+    /* 0x00004144 reg4177 */
+    struct {
+        RK_U32 num1_point_skin    : 15;
+        RK_U32 acc_cover16_num    : 17;
+    } st_skin_sum1;
+
+    /* 0x00004148 reg4178 */
+    struct {
+        RK_U32 num2_point_skin    : 15;
+        RK_U32 acc_bndry16_num    : 17;
+    } st_skin_sum2;
+
+    /* 0x0000414c reg4179 */
+    RK_U32 num0_grdnt_point_dep0;
+
+    /* 0x00004150 reg4180 */
+    RK_U32 num1_grdnt_point_dep0;
+
+    /* 0x00004154 reg4181 */
+    RK_U32 num2_grdnt_point_dep0;
+
+    /* 0x4158 - 0x417c */
+    RK_U32 reserved4182_4191[10];
+
+    /* 0x00004180 reg4192 - 0x0000424c reg4243*/
+    RK_U32 st_b8_qp[52];
+} Vepu510Status;
+
+/* class: dbg/st/axipn */
+/* 0x00005000 reg5120 - 0x0000230 reg5260*/
+//TODO:
+typedef struct Vepu510Dbg_t {
+    /* 0x00005000 reg5120 */
+    struct {
+        RK_U32 vsp0_pos_x    : 16;
+        RK_U32 vsp0_pos_y    : 16;
+    } st_ppl_pos_vsp0;
+
+    /* 0x00005004 reg5121 */
+    struct {
+        RK_U32 vsp1_pos_x    : 16;
+        RK_U32 vsp1_pos_y    : 16;
+    } st_ppl_pos_vsp1;
+
+    /* 0x00005008 reg5122 */
+    struct {
+        RK_U32 cme_pos_x    : 16;
+        RK_U32 cme_pos_y    : 16;
+    } st_ppl_pos_cme;
+
+    /* 0x0000500c reg5123 */
+    struct {
+        RK_U32 swin_cmd_x    : 16;
+        RK_U32 swin_cmd_y    : 16;
+    } st_ppl_cmd_swin;
+
+    /* 0x00005010 reg5124 */
+    struct {
+        RK_U32 swin_pos_x    : 16;
+        RK_U32 swin_pos_y    : 16;
+    } st_ppl_pos_swin;
+
+    /* 0x00005014 reg5125 */
+    struct {
+        RK_U32 pren_pos_x    : 16;
+        RK_U32 pren_pos_y    : 16;
+    } st_ppl_pos_pren;
+
+    /* 0x00005018 reg5126 */
+    struct {
+        RK_U32 rfme_pos_x    : 16;
+        RK_U32 rfme_pos_y    : 16;
+    } st_ppl_pos_rfme;
+
+    /* 0x0000501c reg5127 */
+    struct {
+        RK_U32 rdo_pos_x    : 16;
+        RK_U32 rdo_pos_y    : 16;
+    } st_ppl_pos_rdo;
+
+    /* 0x00005020 reg5128 */
+    struct {
+        RK_U32 lpf_pos_x    : 16;
+        RK_U32 lpf_pos_y    : 16;
+    } st_ppl_pos_lpf;
+
+    /* 0x00005024 reg5129 */
+    struct {
+        RK_U32 etpy_pos_x    : 16;
+        RK_U32 etpy_pos_y    : 16;
+    } st_ppl_pos_etpy;
+
+    /* 0x00005028 reg5130 */
+    struct {
+        RK_U32 vsp0_pos_x    : 16;
+        RK_U32 vsp0_pos_y    : 16;
+    } st_ppl_pos_jsp0;
+
+    /* 0x0000502c reg5131 */
+    struct {
+        RK_U32 vsp1_pos_x    : 16;
+        RK_U32 vsp1_pos_y    : 16;
+    } st_ppl_pos_jsp1;
+
+    /* 0x00005030 reg5132 */
+    struct {
+        RK_U32 jpeg_pos_x    : 16;
+        RK_U32 jpeg_pos_y    : 16;
+    } st_ppl_pos_jpeg;
+
+    /* 0x5034 - 0x503c */
+    RK_U32 reserved5133_5135[3];
+    /* 0x00005040 reg5136 */
+    struct {
+        RK_U32 vsp0_org_err     : 1;
+        RK_U32 vsp0_vsld_err    : 1;
+        RK_U32 pp0_pp1_err      : 1;
+        RK_U32 vsp0_cmd_err     : 1;
+        RK_U32 reserved         : 24;
+        RK_U32 vsp0_wrk         : 1;
+        RK_U32 vsp0_tout        : 1;
+        RK_U32 reserved1        : 2;
+    } dbg_ctrl_vsp0;
+
+    /* 0x00005044 reg5137 */
+    struct {
+        RK_U32 vsp1_org_err    : 1;
+        RK_U32 vsp1_rdo_err    : 1;
+        RK_U32 reserved        : 26;
+        RK_U32 vsp1_wrk        : 1;
+        RK_U32 vsp1_tout       : 1;
+        RK_U32 reserved1       : 2;
+    } dbg_ctrl_vsp1;
+
+    /* 0x00005048 reg5138 */
+    struct {
+        RK_U32 cme_org_err     : 1;
+        RK_U32 cme_roi_err     : 1;
+        RK_U32 cme_win_err     : 1;
+        RK_U32 cme_cmmv_err    : 1;
+        RK_U32 cme_smvp_err    : 1;
+        RK_U32 cme_meiw_err    : 1;
+        RK_U32 cme_dist_err    : 1;
+        RK_U32 cme_rdo_err     : 1;
+        RK_U32 cme_madp_err    : 1;
+        RK_U32 cme_mv_err      : 1;
+        RK_U32 reserved        : 18;
+        RK_U32 cme_wrk         : 1;
+        RK_U32 cme_tout        : 1;
+        RK_U32 reserved1       : 2;
+    } dbg_ctrl_cme;
+
+    /* 0x0000504c reg5139 */
+    struct {
+        RK_U32 swin_org_err    : 1;
+        RK_U32 swin_ref_err    : 1;
+        RK_U32 swin_cmd_err    : 1;
+        RK_U32 reserved        : 25;
+        RK_U32 swin_wrk        : 1;
+        RK_U32 swin_tout       : 1;
+        RK_U32 reserved1       : 2;
+    } dbg_ctrl_swin;
+
+    /* 0x00005050 reg5140 */
+    struct {
+        RK_U32 swin_buff_ptr     : 2;
+        RK_U32 swin_buff_num0    : 2;
+        RK_U32 swin_buff_num1    : 2;
+        RK_U32 swin_buff_num2    : 2;
+        RK_U32 reserved          : 24;
+    } dbg_ppl_swin;
+
+    /* 0x00005054 reg5141 */
+    struct {
+        RK_U32 pnra_org_err     : 1;
+        RK_U32 pnra_dist_err    : 1;
+        RK_U32 pnra_olm_err     : 1;
+        RK_U32 reserved         : 25;
+        RK_U32 pnra_wrk         : 1;
+        RK_U32 pnra_tout        : 1;
+        RK_U32 reserved1        : 2;
+    } dbg_ctrl_pren;
+
+    /* 0x00005058 reg5142 */
+    struct {
+        RK_U32 rfme_org_err     : 1;
+        RK_U32 rfme_ref_err     : 1;
+        RK_U32 rfme_cmmv_err    : 1;
+        RK_U32 rfme_rfmv_err    : 1;
+        RK_U32 rfme_tmvp_err    : 1;
+        RK_U32 reserved         : 23;
+        RK_U32 rfme_wrk         : 1;
+        RK_U32 rfme_tout        : 1;
+        RK_U32 reserved1        : 2;
+    } dbg_ctrl_rfme;
+
+    /* 0x0000505c reg5143 */
+    struct {
+        RK_U32 rdo_org_err        : 1;
+        RK_U32 rdo_ref_err        : 1;
+        RK_U32 rdo_inf_err        : 1;
+        RK_U32 rdo_roi_err        : 1;
+        RK_U32 rdo_rfmv_err       : 1;
+        RK_U32 rdo_lbfr_err       : 1;
+        RK_U32 rdo_lbfw_err       : 1;
+        RK_U32 rdo_tmvp_rd_err    : 1;
+        RK_U32 rdo_tmvp_wr_err    : 1;
+        RK_U32 rdo_st_err         : 1;
+        RK_U32 rdo_pnra_err       : 1;
+        RK_U32 rdo_lpf_err        : 1;
+        RK_U32 rdo_ent_err        : 1;
+        RK_U32 reserved           : 15;
+        RK_U32 rdo_wrk            : 1;
+        RK_U32 rdo_tout           : 1;
+        RK_U32 reserved1          : 2;
+    } dbg_ctrl_rdo;
+
+    /* 0x00005060 reg5144 */
+    struct {
+        RK_U32 lpf_org_err     : 1;
+        RK_U32 lpf_lbfr_err    : 1;
+        RK_U32 lpf_lbfw_err    : 1;
+        RK_U32 lpf_rcol_err    : 1;
+        RK_U32 reserved        : 24;
+        RK_U32 lpf_wrk         : 1;
+        RK_U32 lpf_tout        : 1;
+        RK_U32 reserved1       : 2;
+    } dbg_ctrl_lpf;
+
+    /* 0x00005064 reg5145 */
+    struct {
+        RK_U32 etpy_bsw_err    : 1;
+        RK_U32 reserved        : 27;
+        RK_U32 etpy_wrk        : 1;
+        RK_U32 etpy_tout       : 1;
+        RK_U32 reserved1       : 2;
+    } dbg_ctrl_etpy;
+
+    /* 0x00005068 reg5146 */
+    struct {
+        RK_U32 jsp0_org_err     : 1;
+        RK_U32 jsp0_vsld_err    : 1;
+        RK_U32 pp0_pp1_err      : 1;
+        RK_U32 jsp0_cmd_err     : 1;
+        RK_U32 reserved         : 24;
+        RK_U32 jsp0_wrk         : 1;
+        RK_U32 jsp0_tout        : 1;
+        RK_U32 reserved1        : 2;
+    } dbg_ctrl_jsp0;
+
+    /* 0x0000506c reg5147 */
+    struct {
+        RK_U32 jsp1_org_err     : 1;
+        RK_U32 jsp1_madi_err    : 1;
+        RK_U32 reserved         : 26;
+        RK_U32 jsp1_wrk         : 1;
+        RK_U32 jsp1_tout        : 1;
+        RK_U32 reserved1        : 2;
+    } dbg_ctrl_jsp1;
+
+    /* 0x00005070 reg5148 */
+    struct {
+        RK_U32 jpeg_org_err    : 1;
+        RK_U32 reserved        : 27;
+        RK_U32 jpeg_wrk        : 1;
+        RK_U32 jpeg_tout       : 1;
+        RK_U32 reserved1       : 2;
+    } dbg_ctrl_jpeg;
+
+    /* 0x00005074 reg5149 */
+    struct {
+        RK_U32 dma_brsp_idle     : 1;
+        RK_U32 jpeg_frm_done     : 1;
+        RK_U32 rdo_frm_done      : 1;
+        RK_U32 lpf_frm_done      : 1;
+        RK_U32 ent_frm_done      : 1;
+        RK_U32 ppl_ctrl_done     : 1;
+        RK_U32 criw_frm_done     : 1;
+        RK_U32 meiw_frm_done     : 1;
+        RK_U32 smiw_frm_done     : 1;
+        RK_U32 strg_rsrc_done    : 1;
+        RK_U32 reserved          : 18;
+        RK_U32 frm_wrk           : 1;
+        RK_U32 frm_tout          : 1;
+        RK_U32 reserved1         : 2;
+    } dbg_tctrl0;
+
+    /* 0x00005078 reg5150 */
+    struct {
+        RK_U32 pp0_cmd_vld      : 1;
+        RK_U32 pp0_cmd_rdy      : 1;
+        RK_U32 pp0_cmd_eid      : 1;
+        RK_U32 cme_madp_vld     : 1;
+        RK_U32 cme_madp_rdy0    : 1;
+        RK_U32 cmd_madp_rdy1    : 1;
+        RK_U32 cme_mv16_vld     : 1;
+        RK_U32 cmd_mv16_rdy     : 1;
+        RK_U32 swin_cmd_vld     : 1;
+        RK_U32 swin_cmd_rdy     : 1;
+        RK_U32 pnra_olm_vld     : 1;
+        RK_U32 pnra_olm_rdy     : 1;
+        RK_U32 lpf_rcol_vld     : 1;
+        RK_U32 lpf_rcol_rdy     : 1;
+        RK_U32 bsw_dat_vld      : 1;
+        RK_U32 bsw_dat_rdy      : 1;
+        RK_U32 slc_fifo_full    : 1;
+        RK_U32 reserved         : 15;
+    } dbg_tctrl1;
+
+    /* 0x507c */
+    RK_U32 reserved_5151;
+
+    /* 0x00005080 reg5152 */
+    struct {
+        RK_U32 sli_num     : 15;
+        RK_U32 reserved    : 17;
+    } st_sli_num;
+
+    /* 0x5084 - 0x50fc */
+    RK_U32 reserved5153_5183[31];
+
+    /* 0x00005100 reg5184 */
+    struct {
+        RK_U32 empty_oafifo        : 1;
+        RK_U32 full_cmd_oafifo     : 1;
+        RK_U32 full_data_oafifo    : 1;
+        RK_U32 empty_iafifo        : 1;
+
+        RK_U32 full_cmd_iafifo     : 1;
+        RK_U32 full_info_iafifo    : 1;
+        RK_U32 fbd_brq_st          : 4;
+        RK_U32 fbd_hdr_vld         : 1;
+        RK_U32 fbd_bmng_end        : 1;
+
+        RK_U32 nfbd_req_st         : 4;
+        RK_U32 acc_axi_cmd         : 8;
+        RK_U32 reserved            : 8;
+    } dbg_pp_st;
+
+    /* 0x00005104 reg5185 */
+    struct {
+        RK_U32 r_ena_lambd        : 1;
+        RK_U32 r_fst_swinw_end    : 1;
+        RK_U32 r_swinw_end        : 1;
+        RK_U32 r_cnt_swinw        : 1;
+
+        RK_U32 r_dspw_end         : 1;
+        RK_U32 r_dspw_cnt         : 1;
+        RK_U32 i_sjgen_work       : 1;
+        RK_U32 r_end_rspgen       : 1;
+
+        RK_U32 r_cost_gate        : 1;
+        RK_U32 r_ds_gate          : 1;
+        RK_U32 r_mvp_gate         : 1;
+        RK_U32 i_smvp_arrdy       : 1;
+
+        RK_U32 i_smvp_arvld       : 1;
+        RK_U32 i_stptr_wrdy       : 1;
+        RK_U32 i_stptr_wvld       : 1;
+        RK_U32 i_rdy_atf          : 1;
+
+        RK_U32 i_vld_atf          : 1;
+        RK_U32 i_rdy_bmv16        : 1;
+        RK_U32 i_vld_bmv16        : 1;
+        RK_U32 i_wr_dsp           : 1;
+
+        RK_U32 i_rdy_dsp          : 1;
+        RK_U32 i_vld_dsp          : 1;
+        RK_U32 r_rdy_org          : 1;
+        RK_U32 i_vld_org          : 1;
+
+        RK_U32 i_rdy_state        : 1;
+        RK_U32 i_vld_state        : 1;
+        RK_U32 i_rdy_madp         : 1;
+        RK_U32 i_vld_madp         : 1;
+
+        RK_U32 i_rdy_diff         : 1;
+        RK_U32 i_vld_diff         : 1;
+        RK_U32 reserved           : 2;
+    } dbg_cime_st;
+
+    /* 0x00005108 reg5186 */
+    RK_U32 swin_dbg_inf;
+
+    /* 0x0000510c reg5187 */
+    struct {
+        RK_U32 bbrq_cmps_left_len2    : 1;
+        RK_U32 bbrq_cmps_left_len1    : 1;
+        RK_U32 cmps_left_len0         : 1;
+        RK_U32 bbrq_rdy2              : 1;
+        RK_U32 dcps_vld2              : 1;
+        RK_U32 bbrq_rdy1              : 1;
+        RK_U32 dcps_vld1              : 1;
+        RK_U32 bbrq_rdy0              : 1;
+        RK_U32 dcps_vld0              : 1;
+        RK_U32 hb_rdy2                : 1;
+        RK_U32 bbrq_vld2              : 1;
+        RK_U32 hb_rdy1                : 1;
+        RK_U32 bbrq_vld1              : 1;
+        RK_U32 hb_rdy0                : 1;
+        RK_U32 bbrq_vld0              : 1;
+        RK_U32 idle_msb2              : 1;
+        RK_U32 idle_msb1              : 1;
+        RK_U32 idle_msb0              : 1;
+        RK_U32 cur_state_dcps         : 1;
+        RK_U32 cur_state_bbrq         : 1;
+        RK_U32 cur_state_hb           : 1;
+        RK_U32 cke_bbrq_dcps          : 1;
+        RK_U32 cke_dcps               : 1;
+        RK_U32 cke_bbrq               : 1;
+        RK_U32 rdy_lwcd_rsp           : 1;
+        RK_U32 vld_lwcd_rsp           : 1;
+        RK_U32 rdy_lwcd_req           : 1;
+        RK_U32 vld_lwcd_req           : 1;
+        RK_U32 rdy_lwrsp              : 1;
+        RK_U32 vld_lwrsp              : 1;
+        RK_U32 rdy_lwreq              : 1;
+        RK_U32 vld_lwreq              : 1;
+    } dbg_fbd_hhit0;
+
+    /* 0x00005110 reg5188 */
+    RK_U32 rfme_dbg_inf;
+
+    /* 0x00005114 reg5189 */
+    struct {
+        RK_U32 mscnt_clr    : 1;
+        RK_U32 reserved     : 31;
+    } dbg_cach_clr;
+
+    /* 0x00005118 reg5190 */
+    RK_U32 l1_mis;
+
+    /* 0x0000511c reg5191 */
+    RK_U32 l2_mis;
+
+    /* 0x00005120 reg5192 */
+    RK_U32 rdo_dbg0;
+
+    /* 0x00005124 reg5193 */
+    RK_U32 rdo_dbg1;
+
+    /* 0x00005128 reg5194 */
+    struct {
+        RK_U32 h264_sh_st_cs    : 4;
+        RK_U32 rsd_st_cs        : 4;
+        RK_U32 h264_sd_st_cs    : 5;
+        RK_U32 etpy_rdy         : 1;
+        RK_U32 reserved         : 18;
+    } dbg_etpy;
+
+    /* 0x0000512c reg5195 */
+    struct {
+        RK_U32 chl_aw_vld        : 10;
+        RK_U32 chl_aw_rdy        : 10;
+        RK_U32 aw_vld_arb        : 1;
+        RK_U32 aw_rdy_arb        : 1;
+        RK_U32 aw_vld_crosclk    : 1;
+        RK_U32 aw_rdy_crosclk    : 1;
+        RK_U32 aw_rdy_mmu        : 1;
+        RK_U32 aw_vld_mmu        : 1;
+        RK_U32 aw_rdy_axi        : 1;
+        RK_U32 aw_vld_axi        : 1;
+        RK_U32 reserved          : 4;
+    } dbg_dma_aw;
+
+    /* 0x00005130 reg5196 */
+    struct {
+        RK_U32 chl_w_vld        : 10;
+        RK_U32 chl_w_rdy        : 10;
+        RK_U32 w_vld_arb        : 1;
+        RK_U32 w_rdy_arb        : 1;
+        RK_U32 w_vld_crosclk    : 1;
+        RK_U32 w_rdy_crosclk    : 1;
+        RK_U32 w_rdy_mmu        : 1;
+        RK_U32 w_vld_mmu        : 1;
+        RK_U32 w_rdy_axi        : 1;
+        RK_U32 w_vld_axi        : 1;
+        RK_U32 reserved         : 4;
+    } dbg_dma_w;
+
+    /* 0x00005134 reg5197 */
+    struct {
+        RK_U32 chl_ar_vld        : 9;
+        RK_U32 chl_ar_rdy        : 9;
+        RK_U32 reserved          : 2;
+        RK_U32 ar_vld_arb        : 1;
+        RK_U32 ar_rdy_arb        : 1;
+        RK_U32 ar_vld_crosclk    : 1;
+        RK_U32 ar_rdy_crosclk    : 1;
+        RK_U32 ar_rdy_mmu        : 1;
+        RK_U32 ar_vld_mmu        : 1;
+        RK_U32 ar_rdy_axi        : 1;
+        RK_U32 ar_vld_axi        : 1;
+        RK_U32 reserved1         : 4;
+    } dbg_dma_ar;
+
+    /* 0x00005138 reg5198 */
+    struct {
+        RK_U32 chl_r_vld        : 9;
+        RK_U32 chl_r_rdy        : 9;
+        RK_U32 reserved         : 2;
+        RK_U32 r_vld_arb        : 1;
+        RK_U32 r_rdy_arb        : 1;
+        RK_U32 r_vld_crosclk    : 1;
+        RK_U32 r_rdy_crosclk    : 1;
+        RK_U32 r_rdy_mmu        : 1;
+        RK_U32 r_vld_mmu        : 1;
+        RK_U32 r_rdy_axi        : 1;
+        RK_U32 r_vld_axi        : 1;
+        RK_U32 b_rdy_mmu        : 1;
+        RK_U32 b_vld_mmu        : 1;
+        RK_U32 b_rdy_axi        : 1;
+        RK_U32 b_vld_axi        : 1;
+    } dbg_dma_r;
+
+    /* 0x513c */
+    RK_U32 reserved_5199;
+
+    /* 0x00005140 reg5200 */
+    struct {
+        RK_U32 bsw_fsm_stus     : 4;
+        RK_U32 bsw_aw_full      : 1;
+        RK_U32 bsw_rdy_ent      : 1;
+        RK_U32 bsw_vld_ent      : 1;
+        RK_U32 jpg_bsw_stus     : 4;
+        RK_U32 jpg_aw_full      : 1;
+        RK_U32 jpg_bsw_rdy      : 1;
+        RK_U32 jpg_bsw_vld      : 1;
+        RK_U32 crpw_fsm_stus    : 3;
+        RK_U32 hdwr_rdy         : 1;
+        RK_U32 hdwr_vld         : 1;
+        RK_U32 bdwr_rdy         : 1;
+        RK_U32 bdwr_vld         : 1;
+        RK_U32 nfbc_rdy         : 1;
+        RK_U32 nfbc_vld         : 1;
+        RK_U32 dsp_fsm_stus     : 2;
+        RK_U32 dsp_wr_flg       : 1;
+        RK_U32 dsp_rsy          : 1;
+        RK_U32 dsp_vld          : 1;
+        RK_U32 lpfw_fsm_stus    : 3;
+        RK_U32 reserved         : 1;
+    } dbg_dma_dbg1;
+
+    /* 0x5144 */
+    RK_U32 reserved_5201;
+
+    /* 0x00005148 reg5202 */
+    struct {
+        RK_U32 rdo_st      : 20;
+        RK_U32 reserved    : 12;
+    } dbg_rdo_st;
+
+    /* 0x0000514c reg5203 */
+    struct {
+        RK_U32 lpf_work               : 1;
+        RK_U32 rdo_par_nrdy           : 1;
+        RK_U32 rdo_rcn_nrdy           : 1;
+        RK_U32 lpf_rcn_rdy            : 1;
+        RK_U32 dblk_work              : 1;
+        RK_U32 sao_work               : 1;
+        RK_U32 reserved               : 18;
+        RK_U32 tile_bdry_read         : 1;
+        RK_U32 tile_bdry_write        : 1;
+        RK_U32 tile_bdry_rrdy         : 1;
+        RK_U32 rdo_read_tile_bdry     : 1;
+        RK_U32 rdo_write_tile_bdry    : 1;
+        RK_U32 reserved1              : 3;
+    } dbg_lpf;
+
+    /* 0x5150 */
+    RK_U32 reserved_5204;
+
+    /* 0x00005154 reg5205 */
+    RK_U32 dbg0_cache;
+
+    /* 0x00005158 reg5206 */
+    RK_U32 dbg1_cache;
+
+    /* 0x0000515c reg5207 */
+    RK_U32 dbg2_cache;
+
+    /* 0x00005160 reg5208 */
+    struct {
+        RK_U32 ebuf_diff_cmd    : 8;
+        RK_U32 lbuf_lpf_ncnt    : 7;
+        RK_U32 lbuf_lpf_cien    : 1;
+        RK_U32 lbuf_rdo_ncnt    : 7;
+        RK_U32 lbuf_rdo_cien    : 1;
+        RK_U32 reserved         : 8;
+    } dbg_lbuf0;
+
+    /* 0x00005164 reg5209 */
+    struct {
+        RK_U32 rvld_ebfr          : 1;
+        RK_U32 rrdy_ebfr          : 1;
+        RK_U32 arvld_ebfr         : 1;
+        RK_U32 arrdy_ebfr         : 1;
+        RK_U32 wvld_ebfw          : 1;
+        RK_U32 wrdy_ebfw          : 1;
+        RK_U32 awvld_ebfw         : 1;
+        RK_U32 awrdy_ebfw         : 1;
+        RK_U32 lpf_lbuf_rvld      : 1;
+        RK_U32 lpf_lbuf_rrdy      : 1;
+        RK_U32 lpf_lbuf_wvld      : 1;
+        RK_U32 lpf_lbuf_wrdy      : 1;
+        RK_U32 rdo_lbuf_rvld      : 1;
+        RK_U32 rdo_lbuf_rrdy      : 1;
+        RK_U32 rdo_lbuf_wvld      : 1;
+        RK_U32 rdo_lbuf_wrdy      : 1;
+        RK_U32 fme_lbuf_rvld      : 1;
+        RK_U32 fme_lbuf_rrdy      : 1;
+        RK_U32 cme_lbuf_rvld      : 1;
+        RK_U32 cme_lbuf_rrdy      : 1;
+        RK_U32 smear_lbuf_rvld    : 1;
+        RK_U32 smear_lbuf_rrdy    : 1;
+        RK_U32 smear_lbuf_wvld    : 1;
+        RK_U32 smear_lbuf_wrdy    : 1;
+        RK_U32 rdo_lbufw_flag     : 1;
+        RK_U32 rdo_lbufr_flag     : 1;
+        RK_U32 cme_lbufr_flag     : 1;
+        RK_U32 reserved           : 5;
+    } dbg_lbuf1;
+
+    /* 0x00005168 reg5210 */
+    struct {
+        RK_U32 dbg_isp_fcnt    : 8;
+        RK_U32 dbg_isp_fcyc    : 24;
+    } dbg_dvbm_isp0;
+
+    /* 0x0000516c reg5211 */
+    struct {
+        RK_U32 dbg_isp_lcnt    : 14;
+        RK_U32 reserved        : 1;
+        RK_U32 dbg_isp_ltgl    : 1;
+        RK_U32 dbg_isp_fcnt    : 8;
+        RK_U32 dbg_isp_oflw    : 1;
+        RK_U32 dbg_isp_ftgl    : 1;
+        RK_U32 dbg_isp_full    : 1;
+        RK_U32 dbg_isp_work    : 1;
+        RK_U32 dbg_isp_lvld    : 1;
+        RK_U32 dbg_isp_lrdy    : 1;
+        RK_U32 dbg_isp_fvld    : 1;
+        RK_U32 dbg_isp_frdy    : 1;
+    } dbg_dvbm_isp1;
+
+    /* 0x00005170 reg5212 */
+    struct {
+        RK_U32 dbg_bf0_isp_lcnt    : 14;
+        RK_U32 dbg_bf0_isp_llst    : 1;
+        RK_U32 dbg_bf0_isp_sofw    : 1;
+        RK_U32 dbg_bf0_isp_fcnt    : 8;
+        RK_U32 dbg_bf0_isp_pnt     : 1;
+        RK_U32 reserved            : 3;
+        RK_U32 dbg_bf0_vpu_pnt     : 1;
+        RK_U32 reserved1           : 3;
+    } dbg_dvbm_buf0_inf0;
+
+    /* 0x00005174 reg5213 */
+    struct {
+        RK_U32 dbg_bf0_src_lcnt    : 14;
+        RK_U32 dbg_bf0_src_llst    : 1;
+        RK_U32 reserved            : 1;
+        RK_U32 dbg_bf0_vpu_lcnt    : 14;
+        RK_U32 dbg_bf0_vpu_llst    : 1;
+        RK_U32 dbg_bf0_vpu_vofw    : 1;
+    } dbg_dvbm_buf0_inf1;
+
+    /* 0x00005178 reg5214 */
+    struct {
+        RK_U32 dbg_bf1_isp_lcnt    : 14;
+        RK_U32 dbg_bf1_isp_llst    : 1;
+        RK_U32 dbg_bf1_isp_sofw    : 1;
+        RK_U32 dbg_bf1_isp_fcnt    : 1;
+        RK_U32 reserved            : 7;
+        RK_U32 dbg_bf1_isp_pnt     : 1;
+        RK_U32 reserved1           : 3;
+        RK_U32 dbg_bf1_vpu_pnt     : 1;
+        RK_U32 reserved2           : 3;
+    } dbg_dvbm_buf1_inf0;
+
+    /* 0x0000517c reg5215 */
+    struct {
+        RK_U32 dbg_bf1_src_lcnt    : 14;
+        RK_U32 dbg_bf1_src_llst    : 1;
+        RK_U32 reserved            : 1;
+        RK_U32 dbg_bf1_vpu_lcnt    : 14;
+        RK_U32 dbg_bf1_vpu_llst    : 1;
+        RK_U32 dbg_bf1_vpu_vofw    : 1;
+    } dbg_dvbm_buf1_inf1;
+
+    /* 0x00005180 reg5216 */
+    struct {
+        RK_U32 dbg_bf2_isp_lcnt    : 14;
+        RK_U32 dbg_bf2_isp_llst    : 1;
+        RK_U32 dbg_bf2_isp_sofw    : 1;
+        RK_U32 dbg_bf2_isp_fcnt    : 1;
+        RK_U32 reserved            : 7;
+        RK_U32 dbg_bf2_isp_pnt     : 1;
+        RK_U32 reserved1           : 3;
+        RK_U32 dbg_bf2_vpu_pnt     : 1;
+        RK_U32 reserved2           : 3;
+    } dbg_dvbm_buf2_inf0;
+
+    /* 0x00005184 reg5217 */
+    struct {
+        RK_U32 dbg_bf2_src_lcnt    : 14;
+        RK_U32 dbg_bf2_src_llst    : 1;
+        RK_U32 reserved            : 1;
+        RK_U32 dbg_bf2_vpu_lcnt    : 14;
+        RK_U32 dbg_bf2_vpu_llst    : 1;
+        RK_U32 dbg_bf2_vpu_vofw    : 1;
+    } dbg_dvbm_buf2_inf1;
+
+    /* 0x00005188 reg5218 */
+    struct {
+        RK_U32 dbg_bf3_isp_lcnt    : 14;
+        RK_U32 dbg_bf3_isp_llst    : 1;
+        RK_U32 dbg_bf3_isp_sofw    : 1;
+        RK_U32 dbg_bf3_isp_fcnt    : 1;
+        RK_U32 reserved            : 7;
+        RK_U32 dbg_bf3_isp_pnt     : 1;
+        RK_U32 reserved1           : 3;
+        RK_U32 dbg_bf3_vpu_pnt     : 1;
+        RK_U32 reserved2           : 3;
+    } dbg_dvbm_buf3_inf0;
+
+    /* 0x0000518c reg5219 */
+    struct {
+        RK_U32 dbg_bf3_src_lcnt    : 14;
+        RK_U32 dbg_bf3_src_llst    : 1;
+        RK_U32 reserved            : 1;
+        RK_U32 dbg_bf3_vpu_lcnt    : 14;
+        RK_U32 dbg_bf3_vpu_llst    : 1;
+        RK_U32 dbg_bf3_vpu_vofw    : 1;
+    } dbg_dvbm_buf3_inf1;
+
+    /* 0x00005190 reg5220 */
+    struct {
+        RK_U32 dbg_isp_fptr     : 3;
+        RK_U32 dbg_isp_full     : 1;
+        RK_U32 dbg_src_fptr     : 3;
+        RK_U32 reserved         : 1;
+        RK_U32 dbg_vpu_fptr     : 3;
+        RK_U32 dbg_vpu_empt     : 1;
+        RK_U32 dbg_vpu_lvld     : 1;
+        RK_U32 dbg_vpu_lrdy     : 1;
+        RK_U32 dbg_vpu_fvld     : 1;
+        RK_U32 dbg_vpu_frdy     : 1;
+        RK_U32 dbg_fcnt_misp    : 4;
+        RK_U32 dbg_fcnt_mvpu    : 4;
+        RK_U32 dbg_fcnt_sofw    : 4;
+        RK_U32 dbg_fcnt_vofw    : 4;
+    } dbg_dvbm_ctrl;
+
+    /* 0x5194 - 0x519c */
+    RK_U32 reserved5221_5223[3];
+
+    /* 0x000051a0 reg5224 */
+    RK_U32 dbg_dvbm_buf0_yadr;
+
+    /* 0x000051a4 reg5225 */
+    RK_U32 dbg_dvbm_buf0_cadr;
+
+    /* 0x000051a8 reg5226 */
+    RK_U32 dbg_dvbm_buf1_yadr;
+
+    /* 0x000051ac reg5227 */
+    RK_U32 dbg_dvbm_buf1_cadr;
+
+    /* 0x000051b0 reg5228 */
+    RK_U32 dbg_dvbm_buf2_yadr;
+
+    /* 0x000051b4 reg5229 */
+    RK_U32 dbg_dvbm_buf2_cadr;
+
+    /* 0x000051b8 reg5230 */
+    RK_U32 dbg_dvbm_buf3_yadr;
+
+    /* 0x000051bc reg5231 */
+    RK_U32 dbg_dvbm_buf3_cadr;
+
+    /* 0x000051c0 reg5232 */
+    struct {
+        RK_U32 dchs_rx_cnt    : 11;
+        RK_U32 dchs_rx_id     : 2;
+        RK_U32 dchs_rx_en     : 1;
+        RK_U32 dchs_rx_ack    : 1;
+        RK_U32 dchs_rx_req    : 1;
+        RK_U32 dchs_tx_cnt    : 11;
+        RK_U32 dchs_tx_id     : 2;
+        RK_U32 dchs_tx_en     : 1;
+        RK_U32 dchs_tx_ack    : 1;
+        RK_U32 dchs_tx_req    : 1;
+    } dbg_dchs_intfc;
+
+    /* 0x000051c4 reg5233 */
+    struct {
+        RK_U32 lpfw_tx_cnt       : 11;
+        RK_U32 lpfw_tx_en        : 1;
+        RK_U32 crpw_tx_cnt       : 11;
+        RK_U32 crpw_tx_en        : 1;
+        RK_U32 dual_err_updt     : 1;
+        RK_U32 dlyc_fifo_oflw    : 1;
+        RK_U32 dlyc_tx_vld       : 1;
+        RK_U32 dlyc_tx_rdy       : 1;
+        RK_U32 dlyc_tx_empty     : 1;
+        RK_U32 dchs_tx_idle      : 1;
+        RK_U32 dchs_tx_asy       : 1;
+        RK_U32 dchs_tx_syn       : 1;
+    } dbg_dchs_tx_inf0;
+
+    /* 0x000051c8 reg5234 */
+    struct {
+        RK_U32 criw_tx_cnt    : 11;
+        RK_U32 criw_tx_en     : 1;
+        RK_U32 smrw_tx_cnt    : 11;
+        RK_U32 smrw_tx_en     : 1;
+        RK_U32 reserved       : 8;
+    } dbg_dchs_tx_inf1;
+
+    /* 0x000051cc reg5235 */
+    struct {
+        RK_U32 dual_rx_cnt        : 11;
+        RK_U32 dual_rx_id         : 2;
+        RK_U32 dual_rx_en         : 1;
+        RK_U32 dual_rx_syn        : 1;
+        RK_U32 dual_rx_lock       : 1;
+        RK_U32 dual_lpfr_dule     : 1;
+        RK_U32 dual_cime_dule     : 1;
+        RK_U32 dual_clomv_dule    : 1;
+        RK_U32 dual_smear_dule    : 1;
+        RK_U32 reserved           : 12;
+    } dbg_dchs_rx_inf0;
+
+    /* 0x51d0 - 0x51fc */
+    RK_U32 reserved5236_5247[12];
+
+    /* 0x00005200 reg5248 */
+    RK_U32 frame_cyc;
+
+    /* 0x00005204 reg5249 */
+    RK_U32 vsp0_fcyc;
+
+    /* 0x00005208 reg5250 */
+    RK_U32 vsp1_fcyc;
+
+    /* 0x0000520c reg5251 */
+    RK_U32 cme_fcyc;
+
+    /* 0x00005210 reg5252 */
+    RK_U32 ldr_fcyc;
+
+    /* 0x00005214 reg5253 */
+    RK_U32 rfme_fcyc;
+
+    /* 0x00005218 reg5254 */
+    RK_U32 fme_fcyc;
+
+    /* 0x0000521c reg5255 */
+    RK_U32 rdo_fcyc;
+
+    /* 0x00005220 reg5256 */
+    RK_U32 lpf_fcyc;
+
+    /* 0x00005224 reg5257 */
+    RK_U32 etpy_fcyc;
+
+    /* 0x00005228 reg5258 */
+    RK_U32 jsp0_fcyc;
+
+    /* 0x0000522c reg5259 */
+    RK_U32 jsp1_fcyc;
+
+    /* 0x00005230 reg5260 */
+    RK_U32 jpeg_fcyc;
+} Vepu510Dbg;
+
+/* ROI block configuration */
+typedef struct Vepu510H264RoiBlkCfg {
+    RK_U32 qp_adju        : 8;
+    RK_U32 mdc_adju_inter : 4;
+    RK_U32 mdc_adju_skip  : 4;
+    RK_U32 mdc_adju_intra : 4;
+    RK_U32 reserved       : 12;
+} Vepu510H264RoiBlkCfg;
+
+typedef struct Vepu510H265RoiBlkCfg {
+    RK_U32 qp_adju        : 8;
+    RK_U32 reserved       : 12;
+    RK_U32 mdc_adju_inter : 4;
+    RK_U32 mdc_adju_skip  : 4;
+    RK_U32 mdc_adju_intra : 4;
+} Vepu510H265RoiBlkCfg;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+MPP_RET vepu510_set_roi(void *roi_reg_base, MppEncROICfg * roi, RK_S32 w,
+                        RK_S32 h);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __VEPU510_COMMON_H__ */
diff --git a/mpp/hal/rkenc/common/vepu540c_common.h b/mpp/hal/rkenc/common/vepu540c_common.h
index 778c3d41b..988300a16 100644
--- a/mpp/hal/rkenc/common/vepu540c_common.h
+++ b/mpp/hal/rkenc/common/vepu540c_common.h
@@ -34,6 +34,7 @@
 #define VEPU540C_REG_BASE_HW_STATUS  0x2c
 
 #define VEPU540C_MAX_ROI_NUM         8
+#define VEPU540C_SLICE_FIFO_LEN      8
 
 typedef struct Vepu540cOnline_t {
     /* 0x00000270 reg156 */
diff --git a/mpp/hal/rkenc/common/vepu5xx.h b/mpp/hal/rkenc/common/vepu5xx.h
index 75181b8ed..9317ca7f3 100644
--- a/mpp/hal/rkenc/common/vepu5xx.h
+++ b/mpp/hal/rkenc/common/vepu5xx.h
@@ -19,5 +19,6 @@
 
 #define HWID_VEPU58X                (0x50603312)
 #define HWID_VEPU540C               (0x50603313)
+#define HWID_VEPU510                (0x506f2314)
 
 #endif /* __VEPU5XX_H__ */
diff --git a/mpp/hal/rkenc/common/vepu5xx_common.c b/mpp/hal/rkenc/common/vepu5xx_common.c
index 4757fecf6..63b8d4618 100644
--- a/mpp/hal/rkenc/common/vepu5xx_common.c
+++ b/mpp/hal/rkenc/common/vepu5xx_common.c
@@ -14,9 +14,8 @@
  * limitations under the License.
  */
 
-#define MODULE_TAG "vepu5xx_common.c"
+#define MODULE_TAG "vepu5xx_common"
 
-#include "mpp_log.h"
 #include "mpp_common.h"
 #include "vepu5xx_common.h"
 
@@ -37,7 +36,6 @@ const VepuRgb2YuvCfg vepu_rgb2limit_yuv_cfg_set[] = {
     },
 };
 
-
 const VepuRgb2YuvCfg vepu_rgb2full_yuv_cfg_set[] = {
     /* MPP_BT601_FULL_RGB_TO_FULL_YUV */
     {
@@ -190,4 +188,14 @@ const RK_U32 lamd_modb_qp[52] = {
     0x0002c000, 0x00038000, 0x00044800, 0x00058000, 0x00070000, 0x00089000, 0x000b0000, 0x000e0000,
     0x00112000, 0x00160000, 0x001c0000, 0x00224000, 0x002c0000, 0x00380000, 0x00448000, 0x00580000,
     0x00700000, 0x00890000, 0x00b00000, 0x00e00000
+};
+
+const RK_U32 lamd_satd_qp_510[52] = {
+    0x00000243, 0x00000289, 0x000002DA, 0x00000333, 0x00000397, 0x00000408, 0x00000487, 0x00000514,
+    0x000005B5, 0x00000667, 0x000007C9, 0x000008BD, 0x00000B52, 0x00000CB5, 0x00000E44, 0x00001002,
+    0x000011F9, 0x0000142D, 0x00001523, 0x000017BA, 0x00001AA2, 0x0000199F, 0x00001CC2, 0x00002049,
+    0x0000243C, 0x000032D8, 0x00002DA8, 0x0000333F, 0x00003985, 0x00004092, 0x00004879, 0x000065B0,
+    0x000062EC, 0x000088AA, 0x00007CA2, 0x0000AC30, 0x00009D08, 0x0000B043, 0x0000C5D9, 0x0000EF29,
+    0x00010C74, 0x00012D54, 0x000121E9, 0x00014569, 0x00018BB4, 0x0001BC2A, 0x0001F28E, 0x00020490,
+    0x000243D3, 0x00028AD4, 0x0002DA89, 0x000333FF,
 };
\ No newline at end of file
diff --git a/mpp/hal/rkenc/common/vepu5xx_common.h b/mpp/hal/rkenc/common/vepu5xx_common.h
index 532d66a33..0bd6b70a7 100644
--- a/mpp/hal/rkenc/common/vepu5xx_common.h
+++ b/mpp/hal/rkenc/common/vepu5xx_common.h
@@ -52,5 +52,6 @@ extern const RK_U32 klut_weight[24];
 extern const RK_U32 lamd_satd_qp[52];
 extern const RK_U32 lamd_moda_qp[52];
 extern const RK_U32 lamd_modb_qp[52];
+extern const RK_U32 lamd_satd_qp_510[52];
 
 #endif /* __VEPU5XX_COMMON_H__ */
\ No newline at end of file
diff --git a/mpp/hal/rkenc/h264e/CMakeLists.txt b/mpp/hal/rkenc/h264e/CMakeLists.txt
index 76ea88615..91b88642a 100644
--- a/mpp/hal/rkenc/h264e/CMakeLists.txt
+++ b/mpp/hal/rkenc/h264e/CMakeLists.txt
@@ -15,6 +15,7 @@ set(HAL_H264E_SRC
     hal_h264e_vepu541.c
     hal_h264e_vepu580.c
     hal_h264e_vepu540c.c
+    hal_h264e_vepu510.c
     )
 
 add_library(hal_h264e_rkv STATIC
@@ -22,5 +23,5 @@ add_library(hal_h264e_rkv STATIC
             ${HAL_H264E_SRC}
             )
 
-target_link_libraries(hal_h264e_rkv hal_vepu541_common hal_h264e hal_common)
+target_link_libraries(hal_h264e_rkv hal_vepu541_common hal_h264e_com hal_common)
 set_target_properties(hal_h264e_rkv PROPERTIES FOLDER "mpp/hal")
diff --git a/mpp/hal/rkenc/h264e/hal_h264e_vepu510.c b/mpp/hal/rkenc/h264e/hal_h264e_vepu510.c
new file mode 100644
index 000000000..d3e9d7523
--- /dev/null
+++ b/mpp/hal/rkenc/h264e/hal_h264e_vepu510.c
@@ -0,0 +1,2560 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#define MODULE_TAG "hal_h264e_vepu510"
+
+#include <string.h>
+
+#include "mpp_env.h"
+#include "mpp_mem.h"
+#include "mpp_common.h"
+#include "mpp_frame_impl.h"
+#include "mpp_packet_impl.h"
+#include "mpp_enc_cb_param.h"
+
+#include "rkv_enc_def.h"
+#include "hal_h264e_debug.h"
+#include "hal_bufs.h"
+#include "hal_h264e_vepu510_reg.h"
+#include "hal_h264e_vepu510.h"
+#include "hal_h264e_stream_amend.h"
+#include "h264e_dpb.h"
+
+#include "vepu5xx.h"
+#include "vepu5xx_common.h"
+#include "vepu541_common.h"
+#include "vepu510_common.h"
+
+#define DUMP_REG                0
+#define MAX_TASK_CNT            2
+#define VEPU540C_MAX_ROI_NUM    8
+
+/* Custom Quant Matrices: Joint Video Team */
+static RK_U8 vepu510_h264_cqm_jvt8i[64] = {
+    6, 10, 13, 16, 18, 23, 25, 27,
+    10, 11, 16, 18, 23, 25, 27, 29,
+    13, 16, 18, 23, 25, 27, 29, 31,
+    16, 18, 23, 25, 27, 29, 31, 33,
+    18, 23, 25, 27, 29, 31, 33, 36,
+    23, 25, 27, 29, 31, 33, 36, 38,
+    25, 27, 29, 31, 33, 36, 38, 40,
+    27, 29, 31, 33, 36, 38, 40, 42
+};
+
+static RK_U8 vepu510_h264_cqm_jvt8p[64] = {
+    9, 13, 15, 17, 19, 21, 22, 24,
+    13, 13, 17, 19, 21, 22, 24, 25,
+    15, 17, 19, 21, 22, 24, 25, 27,
+    17, 19, 21, 22, 24, 25, 27, 28,
+    19, 21, 22, 24, 25, 27, 28, 30,
+    21, 22, 24, 25, 27, 28, 30, 32,
+    22, 24, 25, 27, 28, 30, 32, 33,
+    24, 25, 27, 28, 30, 32, 33, 35
+};
+
+typedef struct Vepu510RoiH264BsCfg_t {
+    RK_U64 force_inter   : 42;
+    RK_U64 mode_mask     : 9;
+    RK_U64 reserved      : 10;
+    RK_U64 force_intra   : 1;
+    RK_U64 qp_adj_en     : 1;
+    RK_U64 amv_en        : 1;
+} Vepu510RoiH264BsCfg;
+
+typedef struct Vepu510H264Fbk_t {
+    RK_U32 hw_status;       /* 0:corret, 1:error */
+    RK_U32 frame_type;
+    RK_U32 qp_sum;
+    RK_U32 out_strm_size;
+    RK_U32 out_hw_strm_size;
+    RK_S64 sse_sum;
+    RK_U32 st_lvl64_inter_num;
+    RK_U32 st_lvl32_inter_num;
+    RK_U32 st_lvl16_inter_num;
+    RK_U32 st_lvl8_inter_num;
+    RK_U32 st_lvl32_intra_num;
+    RK_U32 st_lvl16_intra_num;
+    RK_U32 st_lvl8_intra_num;
+    RK_U32 st_lvl4_intra_num;
+    RK_U32 st_cu_num_qp[52];
+    RK_U32 st_madp;
+    RK_U32 st_madi;
+    RK_U32 st_mb_num;
+    RK_U32 st_ctu_num;
+    RK_U32 st_smear_cnt[5];
+} Vepu510H264Fbk;
+
+typedef struct HalH264eVepu510Ctx_t {
+    MppEncCfgSet            *cfg;
+
+    MppDev                  dev;
+    RK_S32                  frame_cnt;
+    RK_U32                  task_cnt;
+
+    /* buffers management */
+    HalBufs                 hw_recn;
+    RK_S32                  pixel_buf_fbc_hdr_size;
+    RK_S32                  pixel_buf_fbc_bdy_size;
+    RK_S32                  pixel_buf_size;
+    RK_S32                  thumb_buf_size;
+    RK_S32                  max_buf_cnt;
+    MppDevRegOffCfgs        *offsets;
+
+    /* external line buffer over 4K */
+    MppBufferGroup          ext_line_buf_grp;
+    MppBuffer               ext_line_bufs[MAX_TASK_CNT];
+    RK_S32                  ext_line_buf_size;
+
+    /* syntax for input from enc_impl */
+    RK_U32                  updated;
+    H264eSps                *sps;
+    H264ePps                *pps;
+    H264eDpb                *dpb;
+    H264eFrmInfo            *frms;
+
+    /* async encode TSVC info */
+    H264eReorderInfo        *reorder;
+    H264eMarkingInfo        *marking;
+
+    /* syntax for output to enc_impl */
+    EncRcTaskInfo           hal_rc_cfg;
+
+    /* roi */
+    void                    *roi_data;
+    MppBufferGroup          roi_grp;
+    MppBuffer               roi_base_cfg_buf;
+    RK_S32                  roi_base_buf_size;
+
+    /* two-pass deflicker */
+    MppBuffer               buf_pass1;
+
+    /* register */
+    HalVepu510RegSet        *regs_sets;
+    HalH264eVepuStreamAmend *amend_sets;
+
+    H264ePrefixNal          *prefix_sets;
+    H264eSlice              *slice_sets;
+
+    /* frame parallel info */
+    RK_S32                  task_idx;
+    RK_S32                  curr_idx;
+    RK_S32                  prev_idx;
+    HalVepu510RegSet        *regs_set;
+    HalH264eVepuStreamAmend *amend;
+    H264ePrefixNal          *prefix;
+    H264eSlice              *slice;
+
+    MppBuffer               ext_line_buf;
+
+    /* slice low delay output callback */
+    MppCbCtx                *output_cb;
+    RK_S32                  poll_slice_max;
+    RK_S32                  poll_cfg_size;
+    MppDevPollCfg           *poll_cfgs;
+
+    Vepu510H264Fbk          feedback;
+    Vepu510H264Fbk          last_frame_fb;
+
+    void                    *tune;
+    RK_S32                  smart_en;
+    RK_S32                  qpmap_en;
+} HalH264eVepu510Ctx;
+
+#include "hal_h264e_vepu510_tune.c"
+
+static RK_S32 h264_aq_tthd_default[16] = {
+    0,  0,  0,  0,  3,  3,  5,  5,
+    8,  8,  8, 15, 15, 20, 25, 25
+};
+
+static RK_S32 h264_P_aq_step_default[16] = {
+    -8, -7, -6, -5, -4, -3, -2, -1,
+    0,  1,  2,  3,  4,  5,  7,  8
+};
+
+static RK_S32 h264_I_aq_step_default[16] = {
+    -8, -7, -6, -5, -4, -3, -2, -1,
+    0,  1,  2,  3,  4,  5,  7,  8
+};
+
+static void setup_ext_line_bufs(HalH264eVepu510Ctx *ctx)
+{
+    RK_U32 i;
+
+    for (i = 0; i < ctx->task_cnt; i++) {
+        if (ctx->ext_line_bufs[i])
+            continue;
+
+        mpp_buffer_get(ctx->ext_line_buf_grp, &ctx->ext_line_bufs[i],
+                       ctx->ext_line_buf_size);
+    }
+}
+
+static void clear_ext_line_bufs(HalH264eVepu510Ctx *ctx)
+{
+    RK_U32 i;
+
+    for (i = 0; i < ctx->task_cnt; i++) {
+        if (ctx->ext_line_bufs[i]) {
+            mpp_buffer_put(ctx->ext_line_bufs[i]);
+            ctx->ext_line_bufs[i] = NULL;
+        }
+    }
+}
+
+static MPP_RET hal_h264e_vepu510_deinit(void *hal)
+{
+    HalH264eVepu510Ctx *p = (HalH264eVepu510Ctx *)hal;
+    RK_U32 i;
+
+    hal_h264e_dbg_func("enter %p\n", p);
+
+    if (p->dev) {
+        mpp_dev_deinit(p->dev);
+        p->dev = NULL;
+    }
+
+    clear_ext_line_bufs(p);
+
+    if (p->amend_sets) {
+        for (i = 0; i < p->task_cnt; i++)
+            h264e_vepu_stream_amend_deinit(&p->amend_sets[i]);
+    }
+
+    MPP_FREE(p->regs_sets);
+    MPP_FREE(p->amend_sets);
+    MPP_FREE(p->prefix_sets);
+    MPP_FREE(p->slice_sets);
+    MPP_FREE(p->reorder);
+    MPP_FREE(p->marking);
+    MPP_FREE(p->poll_cfgs);
+
+    if (p->ext_line_buf_grp) {
+        mpp_buffer_group_put(p->ext_line_buf_grp);
+        p->ext_line_buf_grp = NULL;
+    }
+
+    if (p->hw_recn) {
+        hal_bufs_deinit(p->hw_recn);
+        p->hw_recn = NULL;
+    }
+
+    if (p->roi_base_cfg_buf) {
+        mpp_buffer_put(p->roi_base_cfg_buf);
+        p->roi_base_cfg_buf = NULL;
+        p->roi_base_buf_size = 0;
+    }
+
+    if (p->roi_grp) {
+        mpp_buffer_group_put(p->roi_grp);
+        p->roi_grp = NULL;
+    }
+
+    if (p->offsets) {
+        mpp_dev_multi_offset_deinit(p->offsets);
+        p->offsets = NULL;
+    }
+
+    if (p->buf_pass1) {
+        mpp_buffer_put(p->buf_pass1);
+        p->buf_pass1 = NULL;
+    }
+
+    if (p->tune) {
+        vepu510_h264e_tune_deinit(p->tune);
+        p->tune = NULL;
+    }
+
+    hal_h264e_dbg_func("leave %p\n", p);
+
+    return MPP_OK;
+}
+
+static MPP_RET hal_h264e_vepu510_init(void *hal, MppEncHalCfg *cfg)
+{
+    HalH264eVepu510Ctx *p = (HalH264eVepu510Ctx *)hal;
+    MPP_RET ret = MPP_OK;
+    RK_U32 i;
+
+    hal_h264e_dbg_func("enter %p\n", p);
+
+    p->cfg = cfg->cfg;
+
+    /* update output to MppEnc */
+    cfg->type = VPU_CLIENT_RKVENC;
+    ret = mpp_dev_init(&cfg->dev, cfg->type);
+    if (ret) {
+        mpp_err_f("mpp_dev_init failed. ret: %d\n", ret);
+        goto DONE;
+    }
+    p->dev = cfg->dev;
+    p->task_cnt = cfg->task_cnt;
+    mpp_assert(p->task_cnt && p->task_cnt <= MAX_TASK_CNT);
+
+    ret = hal_bufs_init(&p->hw_recn);
+    if (ret) {
+        mpp_err_f("init vepu buffer failed ret: %d\n", ret);
+        goto DONE;
+    }
+
+    p->regs_sets = mpp_malloc(HalVepu510RegSet, p->task_cnt);
+    if (NULL == p->regs_sets) {
+        ret = MPP_ERR_MALLOC;
+        mpp_err_f("init register buffer failed\n");
+        goto DONE;
+    }
+
+    p->amend_sets = mpp_malloc(HalH264eVepuStreamAmend, p->task_cnt);
+    if (NULL == p->amend_sets) {
+        ret = MPP_ERR_MALLOC;
+        mpp_err_f("init amend data failed\n");
+        goto DONE;
+    }
+
+    if (p->task_cnt > 1) {
+        p->prefix_sets = mpp_malloc(H264ePrefixNal, p->task_cnt);
+        if (NULL == p->prefix_sets) {
+            ret = MPP_ERR_MALLOC;
+            mpp_err_f("init amend data failed\n");
+            goto DONE;
+        }
+
+        p->slice_sets = mpp_malloc(H264eSlice, p->task_cnt);
+        if (NULL == p->slice_sets) {
+            ret = MPP_ERR_MALLOC;
+            mpp_err_f("init amend data failed\n");
+            goto DONE;
+        }
+
+        p->reorder = mpp_malloc(H264eReorderInfo, 1);
+        if (NULL == p->reorder) {
+            ret = MPP_ERR_MALLOC;
+            mpp_err_f("init amend data failed\n");
+            goto DONE;
+        }
+
+        p->marking = mpp_malloc(H264eMarkingInfo, 1);
+        if (NULL == p->marking) {
+            ret = MPP_ERR_MALLOC;
+            mpp_err_f("init amend data failed\n");
+            goto DONE;
+        }
+    }
+
+    p->poll_slice_max = 8;
+    p->poll_cfg_size = (sizeof(p->poll_cfgs) + sizeof(RK_S32) * p->poll_slice_max);
+    p->poll_cfgs = mpp_malloc_size(MppDevPollCfg, p->poll_cfg_size * p->task_cnt);
+    if (NULL == p->poll_cfgs) {
+        ret = MPP_ERR_MALLOC;
+        mpp_err_f("init poll cfg buffer failed\n");
+        goto DONE;
+    }
+
+    {   /* setup default hardware config */
+        MppEncHwCfg *hw = &cfg->cfg->hw;
+
+        hw->qp_delta_row_i  = 1;
+        hw->qp_delta_row    = 2;
+        hw->extra_buf       = 1;
+        hw->qbias_i         = 683;
+        hw->qbias_p         = 341;
+        hw->qbias_en        = 0;
+
+        memcpy(hw->aq_thrd_i, h264_aq_tthd_default, sizeof(hw->aq_thrd_i));
+        memcpy(hw->aq_thrd_p, h264_aq_tthd_default, sizeof(hw->aq_thrd_p));
+        memcpy(hw->aq_step_i, h264_I_aq_step_default, sizeof(hw->aq_step_i));
+        memcpy(hw->aq_step_p, h264_P_aq_step_default, sizeof(hw->aq_step_p));
+
+        for (i = 0; i < MPP_ARRAY_ELEMS(hw->mode_bias); i++)
+            hw->mode_bias[i] = 8;
+
+        hw->skip_sad  = 8;
+        hw->skip_bias = 8;
+    }
+
+    mpp_dev_multi_offset_init(&p->offsets, 24);
+    p->output_cb = cfg->output_cb;
+    cfg->cap_recn_out = 1;
+    for (i = 0; i < p->task_cnt; i++)
+        h264e_vepu_stream_amend_init(&p->amend_sets[i]);
+
+    p->tune = vepu510_h264e_tune_init(p);
+
+DONE:
+    if (ret)
+        hal_h264e_vepu510_deinit(hal);
+
+    hal_h264e_dbg_func("leave %p\n", p);
+    return ret;
+}
+
+/*
+ * NOTE: recon / refer buffer is FBC data buffer.
+ * And FBC data require extra 16 lines space for hardware io.
+ */
+static void setup_hal_bufs(HalH264eVepu510Ctx *ctx)
+{
+    MppEncCfgSet *cfg = ctx->cfg;
+    MppEncPrepCfg *prep = &cfg->prep;
+    RK_S32 alignment_w = 64;
+    RK_S32 alignment_h = 16;
+    RK_S32 aligned_w = MPP_ALIGN(prep->width,  alignment_w);
+    RK_S32 aligned_h = MPP_ALIGN(prep->height, alignment_h) + 16;
+    RK_S32 pixel_buf_fbc_hdr_size = MPP_ALIGN(aligned_w * aligned_h / 64, SZ_8K);
+    RK_S32 pixel_buf_fbc_bdy_size = aligned_w * aligned_h * 3 / 2;
+    RK_S32 pixel_buf_size = pixel_buf_fbc_hdr_size + pixel_buf_fbc_bdy_size;
+    RK_S32 thumb_buf_size = MPP_ALIGN(aligned_w / 64 * aligned_h / 64 * 256, SZ_8K);
+    RK_S32 old_max_cnt = ctx->max_buf_cnt;
+    RK_S32 new_max_cnt = 4;
+    MppEncRefCfg ref_cfg = cfg->ref_cfg;
+
+    if (ref_cfg) {
+        MppEncCpbInfo *info = mpp_enc_ref_cfg_get_cpb_info(ref_cfg);
+        if (new_max_cnt < MPP_MAX(new_max_cnt, info->dpb_size + 1))
+            new_max_cnt = MPP_MAX(new_max_cnt, info->dpb_size + 1);
+    }
+
+    if (aligned_w > SZ_4K) {
+        RK_S32 ctu_w = (aligned_w + 63) / 64;
+        RK_S32 ext_line_buf_size = ((ctu_w - 53) * 53 + 15) / 16 * 16 * 16;
+
+        if (NULL == ctx->ext_line_buf_grp)
+            mpp_buffer_group_get_internal(&ctx->ext_line_buf_grp, MPP_BUFFER_TYPE_ION);
+        else if (ext_line_buf_size != ctx->ext_line_buf_size) {
+            clear_ext_line_bufs(ctx);
+            mpp_buffer_group_clear(ctx->ext_line_buf_grp);
+        }
+
+        mpp_assert(ctx->ext_line_buf_grp);
+
+        ctx->ext_line_buf_size = ext_line_buf_size;
+        setup_ext_line_bufs(ctx);
+    } else {
+        clear_ext_line_bufs(ctx);
+        if (ctx->ext_line_buf_grp) {
+            mpp_buffer_group_clear(ctx->ext_line_buf_grp);
+            mpp_buffer_group_put(ctx->ext_line_buf_grp);
+            ctx->ext_line_buf_grp = NULL;
+        }
+        ctx->ext_line_buf_size = 0;
+    }
+
+    if ((ctx->pixel_buf_fbc_hdr_size != pixel_buf_fbc_hdr_size) ||
+        (ctx->pixel_buf_fbc_bdy_size != pixel_buf_fbc_bdy_size) ||
+        (ctx->pixel_buf_size != pixel_buf_size) ||
+        (ctx->thumb_buf_size != thumb_buf_size) ||
+        (new_max_cnt > old_max_cnt)) {
+        size_t sizes[3];
+
+        hal_h264e_dbg_detail("frame size %d -> %d max count %d -> %d\n",
+                             ctx->pixel_buf_size, pixel_buf_size,
+                             old_max_cnt, new_max_cnt);
+
+        /* pixel buffer */
+        sizes[0] = pixel_buf_size;
+        /* thumb buffer */
+        sizes[1] = thumb_buf_size;
+        /* smear buffer */
+        sizes[2] = MPP_ALIGN(aligned_w / 64, 16) * MPP_ALIGN(aligned_h / 16, 16);
+        new_max_cnt = MPP_MAX(new_max_cnt, old_max_cnt);
+
+        hal_bufs_setup(ctx->hw_recn, new_max_cnt, MPP_ARRAY_ELEMS(sizes), sizes);
+
+        ctx->pixel_buf_fbc_hdr_size = pixel_buf_fbc_hdr_size;
+        ctx->pixel_buf_fbc_bdy_size = pixel_buf_fbc_bdy_size;
+        ctx->pixel_buf_size = pixel_buf_size;
+        ctx->thumb_buf_size = thumb_buf_size;
+        ctx->max_buf_cnt = new_max_cnt;
+    }
+}
+
+static MPP_RET hal_h264e_vepu510_prepare(void *hal)
+{
+    HalH264eVepu510Ctx *ctx = (HalH264eVepu510Ctx *)hal;
+    MppEncPrepCfg *prep = &ctx->cfg->prep;
+
+    hal_h264e_dbg_func("enter %p\n", hal);
+
+    if (prep->change & (MPP_ENC_PREP_CFG_CHANGE_INPUT | MPP_ENC_PREP_CFG_CHANGE_FORMAT)) {
+        RK_S32 i;
+
+        // pre-alloc required buffers to reduce first frame delay
+        setup_hal_bufs(ctx);
+        for (i = 0; i < ctx->max_buf_cnt; i++)
+            hal_bufs_get_buf(ctx->hw_recn, i);
+
+        prep->change = 0;
+    }
+
+    hal_h264e_dbg_func("leave %p\n", hal);
+
+    return MPP_OK;
+}
+
+static RK_U32 update_vepu510_syntax(HalH264eVepu510Ctx *ctx, MppSyntax *syntax)
+{
+    H264eSyntaxDesc *desc = syntax->data;
+    RK_S32 syn_num = syntax->number;
+    RK_U32 updated = 0;
+    RK_S32 i;
+
+    for (i = 0; i < syn_num; i++, desc++) {
+        switch (desc->type) {
+        case H264E_SYN_CFG : {
+            hal_h264e_dbg_detail("update cfg");
+            ctx->cfg = desc->p;
+        } break;
+        case H264E_SYN_SPS : {
+            hal_h264e_dbg_detail("update sps");
+            ctx->sps = desc->p;
+        } break;
+        case H264E_SYN_PPS : {
+            hal_h264e_dbg_detail("update pps");
+            ctx->pps = desc->p;
+        } break;
+        case H264E_SYN_DPB : {
+            hal_h264e_dbg_detail("update dpb");
+            ctx->dpb = desc->p;
+        } break;
+        case H264E_SYN_SLICE : {
+            hal_h264e_dbg_detail("update slice");
+            ctx->slice = desc->p;
+        } break;
+        case H264E_SYN_FRAME : {
+            hal_h264e_dbg_detail("update frames");
+            ctx->frms = desc->p;
+        } break;
+        case H264E_SYN_PREFIX : {
+            hal_h264e_dbg_detail("update prefix nal");
+            ctx->prefix = desc->p;
+        } break;
+        default : {
+            mpp_log_f("invalid syntax type %d\n", desc->type);
+        } break;
+        }
+
+        updated |= SYN_TYPE_FLAG(desc->type);
+    }
+
+    return updated;
+}
+
+static MPP_RET hal_h264e_vepu510_get_task(void *hal, HalEncTask *task)
+{
+    HalH264eVepu510Ctx *ctx = (HalH264eVepu510Ctx *)hal;
+    MppEncCfgSet *cfg_set = ctx->cfg;
+    MppEncRefCfgImpl *ref = (MppEncRefCfgImpl *)cfg_set->ref_cfg;
+    MppEncH264HwCfg *hw_cfg = &cfg_set->codec.h264.hw_cfg;
+    RK_U32 updated = update_vepu510_syntax(ctx, &task->syntax);
+    EncFrmStatus *frm_status = &task->rc_task->frm;
+    H264eFrmInfo *frms = ctx->frms;
+
+    hal_h264e_dbg_func("enter %p\n", hal);
+
+    ctx->smart_en = (ctx->cfg->rc.rc_mode == MPP_ENC_RC_MODE_SMTRC);
+    ctx->qpmap_en = ctx->cfg->tune.deblur_en;
+
+    if (updated & SYN_TYPE_FLAG(H264E_SYN_CFG))
+        setup_hal_bufs(ctx);
+
+    if (!frm_status->reencode && mpp_frame_has_meta(task->frame)) {
+        MppMeta meta = mpp_frame_get_meta(task->frame);
+        mpp_meta_get_ptr(meta, KEY_ROI_DATA, (void **)&ctx->roi_data);
+    }
+
+    if (!frm_status->reencode)
+        ctx->last_frame_fb = ctx->feedback;
+
+    if (ctx->dpb) {
+        h264e_dpb_hal_start(ctx->dpb, frms->curr_idx);
+        h264e_dpb_hal_start(ctx->dpb, frms->refr_idx);
+    }
+
+    task->flags.reg_idx = ctx->task_idx;
+    task->flags.curr_idx = frms->curr_idx;
+    task->flags.refr_idx = frms->refr_idx;
+    task->part_first = 1;
+    task->part_last = 0;
+
+    ctx->ext_line_buf = ctx->ext_line_bufs[ctx->task_idx];
+    ctx->regs_set = &ctx->regs_sets[ctx->task_idx];
+    ctx->amend = &ctx->amend_sets[ctx->task_idx];
+
+    /* if not VEPU1/2, update log2_max_frame_num_minus4 in hw_cfg */
+    hw_cfg->hw_log2_max_frame_num_minus4 = ctx->sps->log2_max_frame_num_minus4;
+
+    if (ctx->task_cnt > 1 && (ref->lt_cfg_cnt || ref->st_cfg_cnt > 1)) {
+        H264ePrefixNal *prefix = &ctx->prefix_sets[ctx->task_idx];
+        H264eSlice *slice = &ctx->slice_sets[ctx->task_idx];
+
+        //store async encode TSVC info
+        if (ctx->prefix)
+            memcpy(prefix, ctx->prefix, sizeof(H264ePrefixNal));
+        else
+            prefix = NULL;
+
+        if (ctx->slice) {
+            memcpy(slice, ctx->slice, sizeof(H264eSlice));
+
+            /*
+             * Generally, reorder and marking are shared by dpb and slice.
+             * However, async encoding TSVC will change reorder and marking in each task.
+             * Therefore, malloc a special space for async encoding TSVC.
+             */
+            ctx->amend->reorder = ctx->reorder;
+            ctx->amend->marking = ctx->marking;
+        }
+
+        h264e_vepu_stream_amend_config(ctx->amend, task->packet, ctx->cfg,
+                                       slice, prefix);
+    } else {
+        h264e_vepu_stream_amend_config(ctx->amend, task->packet, ctx->cfg,
+                                       ctx->slice, ctx->prefix);
+    }
+
+    if (ctx->task_cnt > 1)
+        ctx->task_idx = !ctx->task_idx;
+
+    hal_h264e_dbg_func("leave %p\n", hal);
+
+    return MPP_OK;
+}
+
+static void setup_vepu510_normal(HalVepu510RegSet *regs)
+{
+    hal_h264e_dbg_func("enter\n");
+    /* reg000 VERSION is read only */
+
+    /* reg001 ENC_STRT */
+    regs->reg_ctl.enc_strt.lkt_num           = 0;
+    regs->reg_ctl.enc_strt.vepu_cmd          = 1;
+
+    regs->reg_ctl.opt_strg.cke                = 1;
+    regs->reg_ctl.opt_strg.resetn_hw_en       = 1;
+
+    /* reg002 ENC_CLR */
+    regs->reg_ctl.enc_clr.safe_clr           = 0;
+    regs->reg_ctl.enc_clr.force_clr          = 0;
+
+    /* reg004 INT_EN */
+    regs->reg_ctl.int_en.enc_done_en        = 1;
+    regs->reg_ctl.int_en.lkt_node_done_en   = 1;
+    regs->reg_ctl.int_en.sclr_done_en       = 1;
+    regs->reg_ctl.int_en.vslc_done_en       = 0;
+    regs->reg_ctl.int_en.vbsf_oflw_en       = 1;
+    regs->reg_ctl.int_en.vbuf_lens_en       = 1;
+    regs->reg_ctl.int_en.enc_err_en         = 1;
+
+    regs->reg_ctl.int_en.wdg_en             = 1;
+    regs->reg_ctl.int_en.vsrc_err_en        = 1;
+    regs->reg_ctl.int_en.wdg_en             = 1;
+    regs->reg_ctl.int_en.lkt_err_int_en     = 1;
+    regs->reg_ctl.int_en.lkt_err_stop_en    = 1;
+    regs->reg_ctl.int_en.lkt_force_stop_en  = 1;
+    regs->reg_ctl.int_en.jslc_done_en       = 1;
+    regs->reg_ctl.int_en.jbsf_oflw_en       = 1;
+    regs->reg_ctl.int_en.jbuf_lens_en       = 1;
+    regs->reg_ctl.int_en.dvbm_err_en        = 0;
+
+    /* reg005 INT_MSK */
+    regs->reg_ctl.int_msk.enc_done_msk        = 0;
+    regs->reg_ctl.int_msk.lkt_node_done_msk   = 0;
+    regs->reg_ctl.int_msk.sclr_done_msk       = 0;
+    regs->reg_ctl.int_msk.vslc_done_msk       = 0;
+    regs->reg_ctl.int_msk.vbsf_oflw_msk       = 0;
+    regs->reg_ctl.int_msk.vbuf_lens_msk       = 0;
+    regs->reg_ctl.int_msk.enc_err_msk         = 0;
+    regs->reg_ctl.int_msk.vsrc_err_msk        = 0;
+    regs->reg_ctl.int_msk.wdg_msk             = 0;
+    regs->reg_ctl.int_msk.lkt_err_int_msk     = 0;
+    regs->reg_ctl.int_msk.lkt_err_stop_msk    = 0;
+    regs->reg_ctl.int_msk.lkt_force_stop_msk  = 0;
+    regs->reg_ctl.int_msk.jslc_done_msk       = 0;
+    regs->reg_ctl.int_msk.jbsf_oflw_msk       = 0;
+    regs->reg_ctl.int_msk.jbuf_lens_msk       = 0;
+    regs->reg_ctl.int_msk.dvbm_err_msk        = 0;
+
+    /* reg006 INT_CLR is not set */
+    /* reg007 INT_STA is read only */
+    /* reg008 ~ reg0011 gap */
+    regs->reg_ctl.enc_wdg.vs_load_thd       = 0;
+
+    /* reg015 DTRNS_MAP */
+    regs->reg_ctl.dtrns_map.jpeg_bus_edin      = 0;
+    regs->reg_ctl.dtrns_map.src_bus_edin       = 0;
+    regs->reg_ctl.dtrns_map.meiw_bus_edin      = 0;
+    regs->reg_ctl.dtrns_map.bsw_bus_edin       = 7;
+    regs->reg_ctl.dtrns_map.lktw_bus_edin      = 0;
+    regs->reg_ctl.dtrns_map.rec_nfbc_bus_edin  = 0;
+
+    regs->reg_ctl.dtrns_cfg.axi_brsp_cke   = 0;
+
+    hal_h264e_dbg_func("leave\n");
+}
+
+static MPP_RET setup_vepu510_prep(HalVepu510RegSet *regs, MppEncPrepCfg *prep)
+{
+    H264eVepu510Frame *reg_frm = &regs->reg_frm;
+    VepuFmtCfg cfg;
+    MppFrameFormat fmt = prep->format;
+    MPP_RET ret = vepu541_set_fmt(&cfg, fmt);
+    RK_U32 hw_fmt = cfg.format;
+    RK_S32 y_stride;
+    RK_S32 c_stride;
+
+    hal_h264e_dbg_func("enter\n");
+
+    /* do nothing when color format is not supported */
+    if (ret)
+        return ret;
+
+    reg_frm->common.enc_rsl.pic_wd8_m1 = MPP_ALIGN(prep->width, 16) / 8 - 1;
+    reg_frm->common.src_fill.pic_wfill = MPP_ALIGN(prep->width, 16) - prep->width;
+    reg_frm->common.enc_rsl.pic_hd8_m1 = MPP_ALIGN(prep->height, 16) / 8 - 1;
+    reg_frm->common.src_fill.pic_hfill = MPP_ALIGN(prep->height, 16) - prep->height;
+
+    regs->reg_ctl.dtrns_map.src_bus_edin = cfg.src_endian;
+
+    reg_frm->common.src_fmt.src_cfmt   = hw_fmt;
+    reg_frm->common.src_fmt.alpha_swap = cfg.alpha_swap;
+    reg_frm->common.src_fmt.rbuv_swap  = cfg.rbuv_swap;
+    reg_frm->common.src_fmt.out_fmt = ((fmt & MPP_FRAME_FMT_MASK) == MPP_FMT_YUV400 ? 0 : 1);
+
+    if (MPP_FRAME_FMT_IS_FBC(fmt)) {
+        mpp_err("Unsupported FBC format input.\n");
+
+        return MPP_ERR_VALUE;
+    } else if (prep->hor_stride) {
+        if (MPP_FRAME_FMT_IS_TILE(fmt)) {
+            switch (fmt & MPP_FRAME_FMT_MASK) {
+            case MPP_FMT_YUV400:
+                y_stride = prep->hor_stride * 4;
+                break;
+            case MPP_FMT_YUV420P:
+            case MPP_FMT_YUV420SP:
+                y_stride = prep->hor_stride * 4 * 3 / 2;
+                break;
+            case MPP_FMT_YUV422P:
+            case MPP_FMT_YUV422SP:
+                y_stride = prep->hor_stride * 4 * 2;
+                break;
+            case MPP_FMT_YUV444P:
+            case MPP_FMT_YUV444SP:
+                y_stride = prep->hor_stride * 4 * 3;
+                break;
+            default:
+                mpp_err("Unsupported input format 0x%08x, with TILE mask.\n", fmt);
+                return MPP_ERR_VALUE;
+                break;
+            }
+        } else {
+            y_stride = prep->hor_stride;
+        }
+    } else {
+        if (hw_fmt == VEPU541_FMT_BGRA8888 )
+            y_stride = prep->width * 4;
+        else if (hw_fmt == VEPU541_FMT_BGR888 )
+            y_stride = prep->width * 3;
+        else if (hw_fmt == VEPU541_FMT_BGR565 ||
+                 hw_fmt == VEPU541_FMT_YUYV422 ||
+                 hw_fmt == VEPU541_FMT_UYVY422)
+            y_stride = prep->width * 2;
+        else
+            y_stride = prep->width;
+    }
+
+    switch (hw_fmt) {
+    case VEPU580_FMT_YUV444SP : {
+        c_stride = y_stride * 2;
+    } break;
+    case VEPU541_FMT_YUV422SP :
+    case VEPU541_FMT_YUV420SP :
+    case VEPU580_FMT_YUV444P : {
+        c_stride = y_stride;
+    } break;
+    default : {
+        c_stride = y_stride / 2;
+    } break;
+    }
+
+    if (hw_fmt < VEPU541_FMT_NONE) {
+        const VepuRgb2YuvCfg *cfg_coeffs = get_rgb2yuv_cfg(prep->range, prep->color);
+
+        hal_h264e_dbg_flow("input color range %d colorspace %d", prep->range, prep->color);
+
+        reg_frm->common.src_udfy.csc_wgt_b2y = cfg_coeffs->_2y.b_coeff;
+        reg_frm->common.src_udfy.csc_wgt_g2y = cfg_coeffs->_2y.g_coeff;
+        reg_frm->common.src_udfy.csc_wgt_r2y = cfg_coeffs->_2y.r_coeff;
+
+        reg_frm->common.src_udfu.csc_wgt_b2u = cfg_coeffs->_2u.b_coeff;
+        reg_frm->common.src_udfu.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff;
+        reg_frm->common.src_udfu.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff;
+
+        reg_frm->common.src_udfv.csc_wgt_b2v = cfg_coeffs->_2v.b_coeff;
+        reg_frm->common.src_udfv.csc_wgt_g2v = cfg_coeffs->_2v.g_coeff;
+        reg_frm->common.src_udfv.csc_wgt_r2v = cfg_coeffs->_2v.r_coeff;
+
+        reg_frm->common.src_udfo.csc_ofst_y  = cfg_coeffs->_2y.offset;
+        reg_frm->common.src_udfo.csc_ofst_u  = cfg_coeffs->_2u.offset;
+        reg_frm->common.src_udfo.csc_ofst_v  = cfg_coeffs->_2v.offset;
+
+        hal_h264e_dbg_flow("use color range %d colorspace %d", cfg_coeffs->dst_range, cfg_coeffs->color);
+    } else {
+        reg_frm->common.src_udfy.csc_wgt_b2y = cfg.weight[0];
+        reg_frm->common.src_udfy.csc_wgt_g2y = cfg.weight[1];
+        reg_frm->common.src_udfy.csc_wgt_r2y = cfg.weight[2];
+
+        reg_frm->common.src_udfu.csc_wgt_b2u = cfg.weight[3];
+        reg_frm->common.src_udfu.csc_wgt_g2u = cfg.weight[4];
+        reg_frm->common.src_udfu.csc_wgt_r2u = cfg.weight[5];
+
+        reg_frm->common.src_udfv.csc_wgt_b2v = cfg.weight[6];
+        reg_frm->common.src_udfv.csc_wgt_g2v = cfg.weight[7];
+        reg_frm->common.src_udfv.csc_wgt_r2v = cfg.weight[8];
+
+        reg_frm->common.src_udfo.csc_ofst_y  = cfg.offset[0];
+        reg_frm->common.src_udfo.csc_ofst_u  = cfg.offset[1];
+        reg_frm->common.src_udfo.csc_ofst_v  = cfg.offset[2];
+    }
+
+    reg_frm->common.src_strd0.src_strd0  = y_stride;
+    reg_frm->common.src_strd1.src_strd1  = c_stride;
+
+    reg_frm->common.src_proc.src_mirr    = prep->mirroring > 0;
+    reg_frm->common.src_proc.src_rot     = prep->rotation;
+
+    if (MPP_FRAME_FMT_IS_TILE(fmt))
+        reg_frm->common.src_proc.tile4x4_en = 1;
+    else
+        reg_frm->common.src_proc.tile4x4_en = 0;
+
+    reg_frm->sli_cfg.mv_v_lmt_thd = 0;
+    reg_frm->sli_cfg.mv_v_lmt_en  = 0;
+
+    reg_frm->common.pic_ofst.pic_ofst_y  = 0;
+    reg_frm->common.pic_ofst.pic_ofst_x  = 0;
+
+    hal_h264e_dbg_func("leave\n");
+
+    return ret;
+}
+
+static MPP_RET vepu510_h264e_save_pass1_patch(HalVepu510RegSet *regs, HalH264eVepu510Ctx *ctx)
+{
+    H264eVepu510Frame *reg_frm = &regs->reg_frm;
+    RK_S32 width_align = MPP_ALIGN(ctx->cfg->prep.width, 16);
+    RK_S32 height_align = MPP_ALIGN(ctx->cfg->prep.height, 16);
+
+    if (NULL == ctx->buf_pass1) {
+        mpp_buffer_get(NULL, &ctx->buf_pass1, width_align * height_align * 3 / 2);
+        if (!ctx->buf_pass1) {
+            mpp_err("buf_pass1 malloc fail, debreath invaild");
+            return MPP_NOK;
+        }
+    }
+
+    reg_frm->common.enc_pic.cur_frm_ref = 1;
+    reg_frm->common.rfpw_h_addr = mpp_buffer_get_fd(ctx->buf_pass1);
+    reg_frm->common.rfpw_b_addr = reg_frm->common.rfpw_h_addr;
+    reg_frm->common.enc_pic.rec_fbc_dis = 1;
+
+    mpp_dev_multi_offset_update(ctx->offsets, 164, 0);
+
+    /* NOTE: disable split to avoid lowdelay slice output */
+    reg_frm->common.sli_splt.sli_splt = 0;
+    reg_frm->common.enc_pic.slen_fifo = 0;
+
+    return MPP_OK;
+}
+
+static MPP_RET vepu510_h264e_use_pass1_patch(HalVepu510RegSet *regs, HalH264eVepu510Ctx *ctx)
+{
+    MppEncPrepCfg *prep = &ctx->cfg->prep;
+    H264eVepu510Frame *reg_frm = &regs->reg_frm;
+    RK_S32 fd_in = mpp_buffer_get_fd(ctx->buf_pass1);
+    RK_S32 y_stride;
+    RK_S32 c_stride;
+
+    hal_h264e_dbg_func("enter\n");
+
+    reg_frm->common.src_fmt.src_cfmt   = VEPU541_FMT_YUV420SP;
+    reg_frm->common.src_fmt.alpha_swap = 0;
+    reg_frm->common.src_fmt.rbuv_swap  = 0;
+    reg_frm->common.src_fmt.out_fmt    = 1;
+    reg_frm->common.src_fmt.src_rcne   = 1;
+    y_stride = MPP_ALIGN(prep->width, 16);
+    c_stride = y_stride;
+
+    reg_frm->common.src_strd0.src_strd0 = y_stride;
+    reg_frm->common.src_strd1.src_strd1 = 3 * c_stride;
+
+    reg_frm->common.src_proc.src_mirr   = 0;
+    reg_frm->common.src_proc.src_rot    = 0;
+
+    reg_frm->common.pic_ofst.pic_ofst_y = 0;
+    reg_frm->common.pic_ofst.pic_ofst_x = 0;
+
+
+    reg_frm->common.adr_src0   = fd_in;
+    reg_frm->common.adr_src1   = fd_in;
+    reg_frm->common.adr_src2   = fd_in;
+
+    mpp_dev_multi_offset_update(ctx->offsets, 161, 2 * y_stride);
+
+    hal_h264e_dbg_func("leave\n");
+    return MPP_OK;
+}
+
+static void setup_vepu510_codec(HalVepu510RegSet *regs, H264eSps *sps,
+                                H264ePps *pps, H264eSlice *slice)
+{
+    H264eVepu510Frame *reg_frm = &regs->reg_frm;
+
+    hal_h264e_dbg_func("enter\n");
+
+    reg_frm->common.enc_pic.enc_stnd       = 0;
+    reg_frm->common.enc_pic.cur_frm_ref    = slice->nal_reference_idc > 0;
+    reg_frm->common.enc_pic.bs_scp         = 1;
+
+    reg_frm->synt_nal.nal_ref_idc    = slice->nal_reference_idc;
+    reg_frm->synt_nal.nal_unit_type  = slice->nalu_type;
+
+    reg_frm->synt_sps.max_fnum       = sps->log2_max_frame_num_minus4;
+    reg_frm->synt_sps.drct_8x8       = sps->direct8x8_inference;
+    reg_frm->synt_sps.mpoc_lm4       = sps->log2_max_poc_lsb_minus4;
+
+    reg_frm->synt_pps.etpy_mode      = pps->entropy_coding_mode;
+    reg_frm->synt_pps.trns_8x8       = pps->transform_8x8_mode;
+    reg_frm->synt_pps.csip_flag      = pps->constrained_intra_pred;
+    reg_frm->synt_pps.num_ref0_idx   = pps->num_ref_idx_l0_default_active - 1;
+    reg_frm->synt_pps.num_ref1_idx   = pps->num_ref_idx_l1_default_active - 1;
+    reg_frm->synt_pps.pic_init_qp    = pps->pic_init_qp;
+    reg_frm->synt_pps.cb_ofst        = pps->chroma_qp_index_offset;
+    reg_frm->synt_pps.cr_ofst        = pps->second_chroma_qp_index_offset;
+    reg_frm->synt_pps.dbf_cp_flg     = pps->deblocking_filter_control;
+
+    reg_frm->synt_sli0.sli_type       = (slice->slice_type == H264_I_SLICE) ? (2) : (0);
+    reg_frm->synt_sli0.pps_id         = slice->pic_parameter_set_id;
+    reg_frm->synt_sli0.drct_smvp      = 0;
+    reg_frm->synt_sli0.num_ref_ovrd   = slice->num_ref_idx_override;
+    reg_frm->synt_sli0.cbc_init_idc   = slice->cabac_init_idc;
+    reg_frm->synt_sli0.frm_num        = slice->frame_num;
+
+    reg_frm->synt_sli1.idr_pid        = (slice->slice_type == H264_I_SLICE) ? slice->idr_pic_id : (RK_U32)(-1);
+    reg_frm->synt_sli1.poc_lsb        = slice->pic_order_cnt_lsb;
+
+
+    reg_frm->synt_sli2.dis_dblk_idc   = slice->disable_deblocking_filter_idc;
+    reg_frm->synt_sli2.sli_alph_ofst  = slice->slice_alpha_c0_offset_div2;
+
+    h264e_reorder_rd_rewind(slice->reorder);
+    {   /* reorder process */
+        H264eRplmo rplmo;
+        MPP_RET ret = h264e_reorder_rd_op(slice->reorder, &rplmo);
+
+        if (MPP_OK == ret) {
+            reg_frm->synt_sli2.ref_list0_rodr = 1;
+            reg_frm->synt_sli2.rodr_pic_idx   = rplmo.modification_of_pic_nums_idc;
+
+            switch (rplmo.modification_of_pic_nums_idc) {
+            case 0 :
+            case 1 : {
+                reg_frm->synt_sli2.rodr_pic_num   = rplmo.abs_diff_pic_num_minus1;
+            } break;
+            case 2 : {
+                reg_frm->synt_sli2.rodr_pic_num   = rplmo.long_term_pic_idx;
+            } break;
+            default : {
+                mpp_err_f("invalid modification_of_pic_nums_idc %d\n",
+                          rplmo.modification_of_pic_nums_idc);
+            } break;
+            }
+        } else {
+            // slice->ref_pic_list_modification_flag;
+            reg_frm->synt_sli2.ref_list0_rodr = 0;
+            reg_frm->synt_sli2.rodr_pic_idx   = 0;
+            reg_frm->synt_sli2.rodr_pic_num   = 0;
+        }
+    }
+
+    /* clear all mmco arg first */
+    reg_frm->synt_refm0.nopp_flg               = 0;
+    reg_frm->synt_refm0.ltrf_flg               = 0;
+    reg_frm->synt_refm0.arpm_flg               = 0;
+    reg_frm->synt_refm0.mmco4_pre              = 0;
+    reg_frm->synt_refm0.mmco_type0             = 0;
+    reg_frm->synt_refm0.mmco_parm0             = 0;
+    reg_frm->synt_refm0.mmco_type1             = 0;
+    reg_frm->synt_refm1.mmco_parm1             = 0;
+    reg_frm->synt_refm0.mmco_type2             = 0;
+    reg_frm->synt_refm1.mmco_parm2             = 0;
+    reg_frm->synt_refm2.long_term_frame_idx0   = 0;
+    reg_frm->synt_refm2.long_term_frame_idx1   = 0;
+    reg_frm->synt_refm2.long_term_frame_idx2   = 0;
+
+    h264e_marking_rd_rewind(slice->marking);
+
+    /* only update used parameter */
+    if (slice->slice_type == H264_I_SLICE) {
+        reg_frm->synt_refm0.nopp_flg       = slice->no_output_of_prior_pics;
+        reg_frm->synt_refm0.ltrf_flg       = slice->long_term_reference_flag;
+    } else {
+        if (!h264e_marking_is_empty(slice->marking)) {
+            H264eMmco mmco;
+
+            reg_frm->synt_refm0.arpm_flg       = 1;
+
+            /* max 3 mmco */
+            do {
+                RK_S32 type = 0;
+                RK_S32 param_0 = 0;
+                RK_S32 param_1 = 0;
+
+                h264e_marking_rd_op(slice->marking, &mmco);
+                type = mmco.mmco;
+                switch (type) {
+                case 1 : {
+                    param_0 = mmco.difference_of_pic_nums_minus1;
+                } break;
+                case 2 : {
+                    param_0 = mmco.long_term_pic_num;
+                } break;
+                case 3 : {
+                    param_0 = mmco.difference_of_pic_nums_minus1;
+                    param_1 = mmco.long_term_frame_idx;
+                } break;
+                case 4 : {
+                    param_0 = mmco.max_long_term_frame_idx_plus1;
+                } break;
+                case 5 : {
+                } break;
+                case 6 : {
+                    param_0 = mmco.long_term_frame_idx;
+                } break;
+                default : {
+                    mpp_err_f("unsupported mmco 0 %d\n", type);
+                    type = 0;
+                } break;
+                }
+
+                reg_frm->synt_refm0.mmco_type0 = type;
+                reg_frm->synt_refm0.mmco_parm0 = param_0;
+                reg_frm->synt_refm2.long_term_frame_idx0 = param_1;
+
+                if (h264e_marking_is_empty(slice->marking))
+                    break;
+
+                h264e_marking_rd_op(slice->marking, &mmco);
+                type = mmco.mmco;
+                param_0 = 0;
+                param_1 = 0;
+                switch (type) {
+                case 1 : {
+                    param_0 = mmco.difference_of_pic_nums_minus1;
+                } break;
+                case 2 : {
+                    param_0 = mmco.long_term_pic_num;
+                } break;
+                case 3 : {
+                    param_0 = mmco.difference_of_pic_nums_minus1;
+                    param_1 = mmco.long_term_frame_idx;
+                } break;
+                case 4 : {
+                    param_0 = mmco.max_long_term_frame_idx_plus1;
+                } break;
+                case 5 : {
+                } break;
+                case 6 : {
+                    param_0 = mmco.long_term_frame_idx;
+                } break;
+                default : {
+                    mpp_err_f("unsupported mmco 0 %d\n", type);
+                    type = 0;
+                } break;
+                }
+
+                reg_frm->synt_refm0.mmco_type1 = type;
+                reg_frm->synt_refm1.mmco_parm1 = param_0;
+                reg_frm->synt_refm2.long_term_frame_idx1 = param_1;
+
+                if (h264e_marking_is_empty(slice->marking))
+                    break;
+
+                h264e_marking_rd_op(slice->marking, &mmco);
+                type = mmco.mmco;
+                param_0 = 0;
+                param_1 = 0;
+                switch (type) {
+                case 1 : {
+                    param_0 = mmco.difference_of_pic_nums_minus1;
+                } break;
+                case 2 : {
+                    param_0 = mmco.long_term_pic_num;
+                } break;
+                case 3 : {
+                    param_0 = mmco.difference_of_pic_nums_minus1;
+                    param_1 = mmco.long_term_frame_idx;
+                } break;
+                case 4 : {
+                    param_0 = mmco.max_long_term_frame_idx_plus1;
+                } break;
+                case 5 : {
+                } break;
+                case 6 : {
+                    param_0 = mmco.long_term_frame_idx;
+                } break;
+                default : {
+                    mpp_err_f("unsupported mmco 0 %d\n", type);
+                    type = 0;
+                } break;
+                }
+
+                reg_frm->synt_refm0.mmco_type2 = type;
+                reg_frm->synt_refm1.mmco_parm2 = param_0;
+                reg_frm->synt_refm2.long_term_frame_idx2 = param_1;
+            } while (0);
+        }
+    }
+
+    hal_h264e_dbg_func("leave\n");
+}
+
+static void setup_vepu510_rdo_pred(HalH264eVepu510Ctx *ctx, H264eSps *sps,
+                                   H264ePps *pps, H264eSlice *slice)
+{
+    HalVepu510RegSet *regs = ctx->regs_set;
+    H264eVepu510Frame *reg_frm = &regs->reg_frm;
+    RK_U32 is_ipc_scene = (ctx->cfg->tune.scene_mode == MPP_ENC_SCENE_MODE_IPC);
+
+    hal_h264e_dbg_func("enter\n");
+
+    if (slice->slice_type == H264_I_SLICE) {
+        regs->reg_rc_roi.klut_ofst.chrm_klut_ofst = 6;
+    } else {
+        regs->reg_rc_roi.klut_ofst.chrm_klut_ofst = is_ipc_scene ? 9 : 6;
+    }
+
+    reg_frm->rdo_cfg.rect_size      = (sps->profile_idc == H264_PROFILE_BASELINE &&
+                                       sps->level_idc <= H264_LEVEL_3_0) ? 1 : 0;
+    reg_frm->rdo_cfg.vlc_lmt        = (sps->profile_idc < H264_PROFILE_MAIN) &&
+                                      !pps->entropy_coding_mode;
+    reg_frm->rdo_cfg.chrm_spcl      = 1;
+    reg_frm->rdo_cfg.ccwa_e         = 1;
+    reg_frm->rdo_cfg.scl_lst_sel    = pps->pic_scaling_matrix_present;
+    reg_frm->rdo_cfg.atf_e          = ctx->cfg->tune.anti_flicker_str > 0;
+    reg_frm->rdo_cfg.atr_e          = ctx->cfg->tune.atr_str_i > 0;
+    reg_frm->rdo_cfg.atr_mult_sel_e = 1;
+    reg_frm->iprd_csts.rdo_mark_mode = 0;
+
+    hal_h264e_dbg_func("leave\n");
+}
+
+static void setup_vepu510_rc_base(HalVepu510RegSet *regs, HalH264eVepu510Ctx *ctx, EncRcTask *rc_task)
+{
+    H264eSps *sps = ctx->sps;
+    H264eSlice *slice = ctx->slice;
+    MppEncCfgSet *cfg = ctx->cfg;
+    MppEncRcCfg *rc = &cfg->rc;
+    MppEncHwCfg *hw = &cfg->hw;
+    EncRcTaskInfo *rc_info = &rc_task->info;
+    H264eVepu510Frame *reg_frm = &regs->reg_frm;
+    RK_S32 mb_w = sps->pic_width_in_mbs;
+    RK_S32 mb_h = sps->pic_height_in_mbs;
+    RK_U32 qp_target = rc_info->quality_target;
+    RK_U32 qp_min = rc_info->quality_min;
+    RK_U32 qp_max = rc_info->quality_max;
+    RK_U32 qpmap_mode = 1;
+    RK_S32 mb_target_bits_mul_16 = (rc_info->bit_target << 4) / (mb_w * mb_h);
+    RK_S32 mb_target_bits;
+    RK_S32 negative_bits_thd;
+    RK_S32 positive_bits_thd;
+
+    hal_h264e_dbg_rc("bittarget %d qp [%d %d %d]\n", rc_info->bit_target,
+                     qp_min, qp_target, qp_max);
+
+    hal_h264e_dbg_func("enter\n");
+
+    regs->reg_rc_roi.roi_qthd0.qpmin_area0    = qp_min;
+    regs->reg_rc_roi.roi_qthd0.qpmax_area0    = qp_max;
+    regs->reg_rc_roi.roi_qthd0.qpmin_area1    = qp_min;
+    regs->reg_rc_roi.roi_qthd0.qpmax_area1    = qp_max;
+    regs->reg_rc_roi.roi_qthd0.qpmin_area2    = qp_min;
+
+    regs->reg_rc_roi.roi_qthd1.qpmax_area2    = qp_max;
+    regs->reg_rc_roi.roi_qthd1.qpmin_area3    = qp_min;
+    regs->reg_rc_roi.roi_qthd1.qpmax_area3    = qp_max;
+    regs->reg_rc_roi.roi_qthd1.qpmin_area4    = qp_min;
+    regs->reg_rc_roi.roi_qthd1.qpmax_area4    = qp_max;
+
+    regs->reg_rc_roi.roi_qthd2.qpmin_area5    = qp_min;
+    regs->reg_rc_roi.roi_qthd2.qpmax_area5    = qp_max;
+    regs->reg_rc_roi.roi_qthd2.qpmin_area6    = qp_min;
+    regs->reg_rc_roi.roi_qthd2.qpmax_area6    = qp_max;
+    regs->reg_rc_roi.roi_qthd2.qpmin_area7    = qp_min;
+
+    regs->reg_rc_roi.roi_qthd3.qpmax_area7    = qp_max;
+    regs->reg_rc_roi.roi_qthd3.qpmap_mode     = qpmap_mode;
+
+    if (rc->rc_mode == MPP_ENC_RC_MODE_FIXQP) {
+        reg_frm->common.enc_pic.pic_qp    = rc_info->quality_target;
+        reg_frm->common.rc_qp.rc_max_qp   = rc_info->quality_target;
+        reg_frm->common.rc_qp.rc_min_qp   = rc_info->quality_target;
+
+        return;
+    }
+
+    if (mb_target_bits_mul_16 >= 0x100000)
+        mb_target_bits_mul_16 = 0x50000;
+
+    mb_target_bits = (mb_target_bits_mul_16 * mb_w) >> 4;
+    negative_bits_thd = 0 - 5 * mb_target_bits / 16;
+    positive_bits_thd = 5 * mb_target_bits / 16;
+
+    reg_frm->common.enc_pic.pic_qp         = qp_target;
+
+    reg_frm->common.rc_cfg.rc_en          = 1;
+    reg_frm->common.rc_cfg.aq_en          = 1;
+    reg_frm->common.rc_cfg.rc_ctu_num     = mb_w;
+
+    reg_frm->common.rc_qp.rc_max_qp       = qp_max;
+    reg_frm->common.rc_qp.rc_min_qp       = qp_min;
+    reg_frm->common.rc_tgt.ctu_ebit       = mb_target_bits_mul_16;
+
+    if (rc->rc_mode == MPP_ENC_RC_MODE_SMTRC) {
+        reg_frm->common.rc_qp.rc_qp_range = 0;
+    } else {
+        reg_frm->common.rc_qp.rc_qp_range = (slice->slice_type == H264_I_SLICE) ?
+                                            hw->qp_delta_row_i : hw->qp_delta_row;
+    }
+
+    {
+        /* fixed frame level QP */
+        RK_S32 fqp_min, fqp_max;
+
+        if (slice->slice_type == H264_I_SLICE) {
+            fqp_min = rc->fqp_min_i;
+            fqp_max = rc->fqp_max_i;
+        } else {
+            fqp_min = rc->fqp_min_p;
+            fqp_max = rc->fqp_max_p;
+        }
+
+        if ((fqp_min == fqp_max) && (fqp_min >= 1) && (fqp_max <= 51)) {
+            reg_frm->common.enc_pic.pic_qp = fqp_min;
+            reg_frm->common.rc_qp.rc_qp_range = 0;
+        }
+    }
+
+    regs->reg_rc_roi.rc_adj0.qp_adj0        = -2;
+    regs->reg_rc_roi.rc_adj0.qp_adj1        = -1;
+    regs->reg_rc_roi.rc_adj0.qp_adj2        = 0;
+    regs->reg_rc_roi.rc_adj0.qp_adj3        = 1;
+    regs->reg_rc_roi.rc_adj0.qp_adj4        = 2;
+    regs->reg_rc_roi.rc_adj1.qp_adj5        = 0;
+    regs->reg_rc_roi.rc_adj1.qp_adj6        = 0;
+    regs->reg_rc_roi.rc_adj1.qp_adj7        = 0;
+    regs->reg_rc_roi.rc_adj1.qp_adj8        = 0;
+
+    regs->reg_rc_roi.rc_dthd_0_8[0] = 4 * negative_bits_thd;
+    regs->reg_rc_roi.rc_dthd_0_8[1] = negative_bits_thd;
+    regs->reg_rc_roi.rc_dthd_0_8[2] = positive_bits_thd;
+    regs->reg_rc_roi.rc_dthd_0_8[3] = 4 * positive_bits_thd;
+    regs->reg_rc_roi.rc_dthd_0_8[4] = 0x7FFFFFFF;
+    regs->reg_rc_roi.rc_dthd_0_8[5] = 0x7FFFFFFF;
+    regs->reg_rc_roi.rc_dthd_0_8[6] = 0x7FFFFFFF;
+    regs->reg_rc_roi.rc_dthd_0_8[7] = 0x7FFFFFFF;
+    regs->reg_rc_roi.rc_dthd_0_8[8] = 0x7FFFFFFF;
+
+    hal_h264e_dbg_func("leave\n");
+}
+
+static void setup_vepu510_io_buf(HalVepu510RegSet *regs, MppDevRegOffCfgs *offsets,
+                                 HalEncTask *task)
+{
+    MppFrame frm = task->frame;
+    MppPacket pkt = task->packet;
+    MppBuffer buf_in = mpp_frame_get_buffer(frm);
+    MppBuffer buf_out = task->output;
+    MppFrameFormat fmt = mpp_frame_get_fmt(frm);
+    H264eVepu510Frame *reg_frm = &regs->reg_frm;
+    RK_S32 hor_stride = mpp_frame_get_hor_stride(frm);
+    RK_S32 ver_stride = mpp_frame_get_ver_stride(frm);
+    RK_S32 fd_in = mpp_buffer_get_fd(buf_in);
+    RK_U32 off_in[2] = {0};
+    RK_U32 off_out = mpp_packet_get_length(pkt);
+    size_t siz_out = mpp_buffer_get_size(buf_out);
+    RK_S32 fd_out = mpp_buffer_get_fd(buf_out);
+
+    hal_h264e_dbg_func("enter\n");
+
+    reg_frm->common.adr_src0   = fd_in;
+    reg_frm->common.adr_src1   = fd_in;
+    reg_frm->common.adr_src2   = fd_in;
+
+    reg_frm->common.bsbt_addr  = fd_out;
+    reg_frm->common.bsbb_addr  = fd_out;
+    reg_frm->common.adr_bsbs   = fd_out;
+    reg_frm->common.bsbr_addr  = fd_out;
+
+    reg_frm->common.rfpt_h_addr = 0xffffffff;
+    reg_frm->common.rfpb_h_addr = 0;
+    reg_frm->common.rfpt_b_addr = 0xffffffff;
+    reg_frm->common.adr_rfpb_b  = 0;
+
+    if (MPP_FRAME_FMT_IS_YUV(fmt)) {
+        VepuFmtCfg cfg;
+
+        vepu541_set_fmt(&cfg, fmt);
+        switch (cfg.format) {
+        case VEPU541_FMT_BGRA8888 :
+        case VEPU541_FMT_BGR888 :
+        case VEPU541_FMT_BGR565 : {
+            off_in[0] = 0;
+            off_in[1] = 0;
+        } break;
+        case VEPU541_FMT_YUV420SP :
+        case VEPU541_FMT_YUV422SP : {
+            off_in[0] = hor_stride * ver_stride;
+            off_in[1] = hor_stride * ver_stride;
+        } break;
+        case VEPU541_FMT_YUV422P : {
+            off_in[0] = hor_stride * ver_stride;
+            off_in[1] = hor_stride * ver_stride * 3 / 2;
+        } break;
+        case VEPU541_FMT_YUV420P : {
+            off_in[0] = hor_stride * ver_stride;
+            off_in[1] = hor_stride * ver_stride * 5 / 4;
+        } break;
+        case VEPU540_FMT_YUV400 :
+        case VEPU541_FMT_YUYV422 :
+        case VEPU541_FMT_UYVY422 : {
+            off_in[0] = 0;
+            off_in[1] = 0;
+        } break;
+        case VEPU580_FMT_YUV444SP : {
+            off_in[0] = hor_stride * ver_stride;
+            off_in[1] = hor_stride * ver_stride;
+        } break;
+        case VEPU580_FMT_YUV444P : {
+            off_in[0] = hor_stride * ver_stride;
+            off_in[1] = hor_stride * ver_stride * 2;
+        } break;
+        case VEPU541_FMT_NONE :
+        default : {
+            off_in[0] = 0;
+            off_in[1] = 0;
+        } break;
+        }
+    }
+
+    mpp_dev_multi_offset_update(offsets, 161, off_in[0]);
+    mpp_dev_multi_offset_update(offsets, 162, off_in[1]);
+    mpp_dev_multi_offset_update(offsets, 172, siz_out);
+    mpp_dev_multi_offset_update(offsets, 174, off_out);
+
+    hal_h264e_dbg_func("leave\n");
+}
+
+static MPP_RET vepu510_h264_set_one_roi(void *buf, MppEncROIRegion *region, RK_S32 w, RK_S32 h)
+{
+    Vepu510RoiH264BsCfg *ptr = (Vepu510RoiH264BsCfg *)buf;
+    RK_S32 mb_w = MPP_ALIGN(w, 16) / 16;
+    RK_S32 mb_h = MPP_ALIGN(h, 16) / 16;
+    RK_S32 stride_h = MPP_ALIGN(mb_w, 4);
+    Vepu510RoiH264BsCfg cfg;
+    MPP_RET ret = MPP_NOK;
+
+    if (NULL == buf || NULL == region) {
+        mpp_err_f("invalid buf %p roi %p\n", buf, region);
+        goto DONE;
+    }
+
+    RK_S32 roi_width  = (region->w + 15) / 16;
+    RK_S32 roi_height = (region->h + 15) / 16;
+    RK_S32 pos_x_init = region->x / 16;
+    RK_S32 pos_y_init = region->y / 16;
+    RK_S32 pos_x_end  = pos_x_init + roi_width;
+    RK_S32 pos_y_end  = pos_y_init + roi_height;
+    RK_S32 x, y;
+
+    pos_x_end = MPP_MIN(pos_x_end, mb_w);
+    pos_y_end = MPP_MIN(pos_y_end, mb_h);
+    pos_x_init = MPP_MAX(pos_x_init, 0);
+    pos_y_init = MPP_MAX(pos_y_init, 0);
+
+    mpp_assert(pos_x_end > pos_x_init);
+    mpp_assert(pos_y_end > pos_y_init);
+
+    cfg.force_intra = 1;
+
+    ptr += pos_y_init * stride_h + pos_x_init;
+    roi_width = pos_x_end - pos_x_init;
+    roi_height = pos_y_end - pos_y_init;
+
+    for (y = 0; y < roi_height; y++) {
+        Vepu510RoiH264BsCfg *dst = ptr;
+
+        for (x = 0; x < roi_width; x++, dst++)
+            memcpy(dst, &cfg, sizeof(cfg));
+
+        ptr += stride_h;
+    }
+DONE:
+    return ret;
+}
+
+static MPP_RET setup_vepu510_intra_refresh(HalVepu510RegSet *regs, HalH264eVepu510Ctx *ctx, RK_U32 refresh_idx)
+{
+    MPP_RET ret = MPP_OK;
+    RK_U32 mb_w = ctx->sps->pic_width_in_mbs;
+    RK_U32 mb_h = ctx->sps->pic_height_in_mbs;
+    RK_U32 w = mb_w * 16;
+    RK_U32 h = mb_h * 16;
+    MppEncROIRegion *region = NULL;
+    H264eVepu510Frame *reg_frm = &regs->reg_frm;
+    RK_U32 refresh_num = ctx->cfg->rc.refresh_num;
+    RK_U32 stride_h = MPP_ALIGN(mb_w, 4);
+    RK_U32 stride_v = MPP_ALIGN(mb_h, 4);
+    RK_U32 roi_base_buf_size = stride_h * stride_v * 8;
+    RK_U32 i = 0;
+
+    hal_h264e_dbg_func("enter\n");
+
+    if (!ctx->cfg->rc.refresh_en) {
+        ret = MPP_ERR_VALUE;
+        goto RET;
+    }
+
+    if (NULL == ctx->roi_base_cfg_buf) {
+        if (NULL == ctx->roi_grp)
+            mpp_buffer_group_get_internal(&ctx->roi_grp, MPP_BUFFER_TYPE_ION);
+        mpp_buffer_get(ctx->roi_grp, &ctx->roi_base_cfg_buf, roi_base_buf_size);
+        ctx->roi_base_buf_size = roi_base_buf_size;
+    }
+
+    mpp_assert(ctx->roi_base_cfg_buf);
+    void *base_cfg_buf = mpp_buffer_get_ptr(ctx->roi_base_cfg_buf);
+    Vepu510RoiH264BsCfg base_cfg;
+    Vepu510RoiH264BsCfg *base_cfg_ptr = (Vepu510RoiH264BsCfg *)base_cfg_buf;
+
+    base_cfg.force_intra = 0;
+    base_cfg.qp_adj_en   = 1;
+
+    for (i = 0; i < stride_h * stride_v; i++, base_cfg_ptr++)
+        memcpy(base_cfg_ptr, &base_cfg, sizeof(base_cfg));
+
+    region = mpp_calloc(MppEncROIRegion, 1);
+
+    if (NULL == region) {
+        mpp_err_f("Failed to calloc for MppEncROIRegion !\n");
+        ret = MPP_ERR_MALLOC;
+    }
+
+    if (ctx->cfg->rc.refresh_mode == MPP_ENC_RC_INTRA_REFRESH_ROW) {
+        region->x = 0;
+        region->w = w;
+        if (refresh_idx > 0) {
+            region->y = refresh_idx * 16 * refresh_num - 32;
+            region->h = 16 * refresh_num + 32;
+        } else {
+            region->y = refresh_idx * 16 * refresh_num;
+            region->h = 16 * refresh_num;
+        }
+        reg_frm->common.me_rnge.cime_srch_uph = 1;
+    } else if (ctx->cfg->rc.refresh_mode == MPP_ENC_RC_INTRA_REFRESH_COL) {
+        region->y = 0;
+        region->h = h;
+        if (refresh_idx > 0) {
+            region->x = refresh_idx * 16 * refresh_num - 32;
+            region->w = 16 * refresh_num + 32;
+        } else {
+            region->x = refresh_idx * 16 * refresh_num;
+            region->w = 16 * refresh_num;
+        }
+        reg_frm->common.me_rnge.cime_srch_dwnh = 1;
+    }
+
+    region->intra = 1;
+    region->quality = -ctx->cfg->rc.qp_delta_ip;
+
+    region->area_map_en = 1;
+    region->qp_area_idx = 1;
+    region->abs_qp_en = 0;
+
+    vepu510_h264_set_one_roi(base_cfg_buf, region, w, h);
+    mpp_free(region);
+RET:
+    hal_h264e_dbg_func("leave, ret %d\n", ret);
+    return ret;
+}
+
+static void setup_vepu510_recn_refr(HalH264eVepu510Ctx *ctx, HalVepu510RegSet *regs)
+{
+
+    H264eVepu510Frame *reg_frm = &regs->reg_frm;
+    H264eFrmInfo *frms = ctx->frms;
+    HalBufs bufs = ctx->hw_recn;
+    RK_S32 fbc_hdr_size = ctx->pixel_buf_fbc_hdr_size;
+
+    HalBuf *curr = hal_bufs_get_buf(bufs, frms->curr_idx);
+    HalBuf *refr = hal_bufs_get_buf(bufs, frms->refr_idx);
+
+    hal_h264e_dbg_func("enter\n");
+
+    if (curr && curr->cnt) {
+        MppBuffer buf_pixel = curr->buf[0];
+        MppBuffer buf_thumb = curr->buf[1];
+        MppBuffer buf_smear = curr->buf[2];
+        RK_S32 fd = mpp_buffer_get_fd(buf_pixel);
+
+        mpp_assert(buf_pixel);
+        mpp_assert(buf_thumb);
+
+        reg_frm->common.rfpw_h_addr = fd;
+        reg_frm->common.rfpw_b_addr = fd;
+        reg_frm->common.dspw_addr = mpp_buffer_get_fd(buf_thumb);
+        reg_frm->common.adr_smear_wr = mpp_buffer_get_fd(buf_smear);
+    }
+
+    if (refr && refr->cnt) {
+        MppBuffer buf_pixel = refr->buf[0];
+        MppBuffer buf_thumb = refr->buf[1];
+        MppBuffer buf_smear = curr->buf[2];
+        RK_S32 fd = mpp_buffer_get_fd(buf_pixel);
+
+        mpp_assert(buf_pixel);
+        mpp_assert(buf_thumb);
+
+        reg_frm->common.rfpr_h_addr = fd;
+        reg_frm->common.rfpr_b_addr = fd;
+        reg_frm->common.dspr_addr = mpp_buffer_get_fd(buf_thumb);
+        reg_frm->common.adr_smear_rd = mpp_buffer_get_fd(buf_smear);
+    }
+    mpp_dev_multi_offset_update(ctx->offsets, 164, fbc_hdr_size);
+    mpp_dev_multi_offset_update(ctx->offsets, 166, fbc_hdr_size);
+
+    hal_h264e_dbg_func("leave\n");
+}
+
+static void setup_vepu510_split(HalVepu510RegSet *regs, MppEncCfgSet *enc_cfg)
+{
+    H264eVepu510Frame *reg_frm = &regs->reg_frm;
+    MppEncSliceSplit *cfg = &enc_cfg->split;
+
+    hal_h264e_dbg_func("enter\n");
+
+    switch (cfg->split_mode) {
+    case MPP_ENC_SPLIT_NONE : {
+        reg_frm->common.sli_splt.sli_splt         = 0;
+        reg_frm->common.sli_splt.sli_splt_mode    = 0;
+        reg_frm->common.sli_splt.sli_splt_cpst    = 0;
+        reg_frm->common.sli_splt.sli_max_num_m1   = 0;
+        reg_frm->common.sli_splt.sli_flsh         = 0;
+        reg_frm->common.sli_cnum.sli_splt_cnum_m1 = 0;
+
+        reg_frm->common.sli_byte.sli_splt_byte    = 0;
+        reg_frm->common.enc_pic.slen_fifo         = 0;
+    } break;
+    case MPP_ENC_SPLIT_BY_BYTE : {
+        reg_frm->common.sli_splt.sli_splt         = 1;
+        reg_frm->common.sli_splt.sli_splt_mode    = 0;
+        reg_frm->common.sli_splt.sli_splt_cpst    = 0;
+        reg_frm->common.sli_splt.sli_max_num_m1   = 500;
+        reg_frm->common.sli_splt.sli_flsh         = 1;
+        reg_frm->common.sli_cnum.sli_splt_cnum_m1 = 0;
+
+        reg_frm->common.sli_byte.sli_splt_byte    = cfg->split_arg;
+        reg_frm->common.enc_pic.slen_fifo         = cfg->split_out ? 1 : 0;
+        regs->reg_ctl.int_en.vslc_done_en         = reg_frm->common.enc_pic.slen_fifo;
+    } break;
+    case MPP_ENC_SPLIT_BY_CTU : {
+        RK_U32 mb_w = MPP_ALIGN(enc_cfg->prep.width, 16) / 16;
+        RK_U32 mb_h = MPP_ALIGN(enc_cfg->prep.height, 16) / 16;
+        RK_U32 slice_num = (mb_w * mb_h + cfg->split_arg - 1) / cfg->split_arg;
+
+        reg_frm->common.sli_splt.sli_splt         = 1;
+        reg_frm->common.sli_splt.sli_splt_mode    = 1;
+        reg_frm->common.sli_splt.sli_splt_cpst    = 0;
+        reg_frm->common.sli_splt.sli_max_num_m1   = 500;
+        reg_frm->common.sli_splt.sli_flsh         = 1;
+        reg_frm->common.sli_cnum.sli_splt_cnum_m1 = cfg->split_arg - 1;
+
+        reg_frm->common.sli_byte.sli_splt_byte    = 0;
+        reg_frm->common.enc_pic.slen_fifo         = cfg->split_out ? 1 : 0;
+        if ((cfg->split_out & MPP_ENC_SPLIT_OUT_LOWDELAY) ||
+            (regs->reg_frm.common.enc_pic.slen_fifo && (slice_num > VEPU510_SLICE_FIFO_LEN)))
+            regs->reg_ctl.int_en.vslc_done_en = 1;
+    } break;
+    default : {
+        mpp_log_f("invalide slice split mode %d\n", cfg->split_mode);
+    } break;
+    }
+    cfg->change = 0;
+
+    hal_h264e_dbg_func("leave\n");
+}
+
+static void setup_vepu510_me(HalH264eVepu510Ctx *ctx)
+{
+    HalVepu510RegSet *regs = ctx->regs_set;
+    H264eVepu510Frame *reg_frm = &regs->reg_frm;
+    H264eVepu510Param *reg_param = &regs->reg_param;
+    MppEncSceneMode sm = ctx->cfg->tune.scene_mode;
+
+    hal_h264e_dbg_func("enter\n");
+
+    reg_frm->common.me_rnge.cime_srch_dwnh    = 15;
+    reg_frm->common.me_rnge.cime_srch_uph     = 15;
+    reg_frm->common.me_rnge.cime_srch_rgtw    = 12;
+    reg_frm->common.me_rnge.cime_srch_lftw    = 12;
+    reg_frm->common.me_cfg.rme_srch_h         = 3;
+    reg_frm->common.me_cfg.rme_srch_v         = 3;
+
+    reg_frm->common.me_cfg.srgn_max_num       = 54;
+    reg_frm->common.me_cfg.cime_dist_thre     = 1024;
+    reg_frm->common.me_cfg.rme_dis            = 0;
+    reg_frm->common.me_cfg.fme_dis            = 0;
+    reg_frm->common.me_rnge.dlt_frm_num       = 0x0;
+    reg_frm->common.me_cach.cime_zero_thre    = 64;
+
+    /* CIME: 0x1760 - 0x176C */
+    reg_param->me_sqi_comb.cime_pmv_num = 1;
+    reg_param->me_sqi_comb.cime_fuse    = 1;
+    reg_param->me_sqi_comb.itp_mode     = 0;
+    reg_param->me_sqi_comb.move_lambda  = 0;
+    reg_param->me_sqi_comb.rime_lvl_mrg     = 1;
+    reg_param->me_sqi_comb.rime_prelvl_en   = 0;
+    reg_param->me_sqi_comb.rime_prersu_en   = 0;
+    reg_param->cime_mvd_th_comb.cime_mvd_th0 = 16;
+    reg_param->cime_mvd_th_comb.cime_mvd_th1 = 48;
+    reg_param->cime_mvd_th_comb.cime_mvd_th2 = 80;
+    reg_param->cime_madp_th_comb.cime_madp_th = 16;
+    reg_param->cime_multi_comb.cime_multi0 = 8;
+    reg_param->cime_multi_comb.cime_multi1 = 12;
+    reg_param->cime_multi_comb.cime_multi2 = 16;
+    reg_param->cime_multi_comb.cime_multi3 = 20;
+
+    /* RFME: 0x1770 - 0x1778 */
+    reg_param->rime_mvd_th_comb.rime_mvd_th0  = 1;
+    reg_param->rime_mvd_th_comb.rime_mvd_th1  = 2;
+    reg_param->rime_mvd_th_comb.fme_madp_th   = 0;
+    reg_param->rime_madp_th_comb.rime_madp_th0 = 8;
+    reg_param->rime_madp_th_comb.rime_madp_th1 = 16;
+    reg_param->rime_multi_comb.rime_multi0 = 4;
+    reg_param->rime_multi_comb.rime_multi1 = 8;
+    reg_param->rime_multi_comb.rime_multi2 = 12;
+    reg_param->cmv_st_th_comb.cmv_th0 = 64;
+    reg_param->cmv_st_th_comb.cmv_th1 = 96;
+    reg_param->cmv_st_th_comb.cmv_th2 = 128;
+
+    if (sm != MPP_ENC_SCENE_MODE_IPC) {
+        /* disable subjective optimization */
+        reg_param->cime_madp_th_comb.cime_madp_th = 0;
+        reg_param->rime_madp_th_comb.rime_madp_th0 = 0;
+        reg_param->rime_madp_th_comb.rime_madp_th1 = 0;
+        reg_param->cime_multi_comb.cime_multi0 = 4;
+        reg_param->cime_multi_comb.cime_multi1 = 4;
+        reg_param->cime_multi_comb.cime_multi2 = 4;
+        reg_param->cime_multi_comb.cime_multi3 = 4;
+        reg_param->rime_multi_comb.rime_multi0 = 4;
+        reg_param->rime_multi_comb.rime_multi1 = 4;
+        reg_param->rime_multi_comb.rime_multi2 = 4;
+    }
+
+    /* 0x1064 */
+    regs->reg_rc_roi.madi_st_thd.madi_th0 = 5;
+    regs->reg_rc_roi.madi_st_thd.madi_th1 = 12;
+    regs->reg_rc_roi.madi_st_thd.madi_th2 = 20;
+    /* 0x1068 */
+    regs->reg_rc_roi.madp_st_thd0.madp_th0 = 4 << 4;
+    regs->reg_rc_roi.madp_st_thd0.madp_th1 = 9 << 4;
+    /* 0x106C */
+    regs->reg_rc_roi.madp_st_thd1.madp_th2 = 15 << 4;
+
+    hal_h264e_dbg_func("leave\n");
+}
+
+#define H264E_LAMBDA_TAB_SIZE       (52 * sizeof(RK_U32))
+
+static RK_U32 h264e_lambda_default[60] = {
+    0x00000005, 0x00000006, 0x00000007, 0x00000009,
+    0x0000000b, 0x0000000e, 0x00000012, 0x00000016,
+    0x0000001c, 0x00000024, 0x0000002d, 0x00000039,
+    0x00000048, 0x0000005b, 0x00000073, 0x00000091,
+    0x000000b6, 0x000000e6, 0x00000122, 0x0000016d,
+    0x000001cc, 0x00000244, 0x000002db, 0x00000399,
+    0x00000489, 0x000005b6, 0x00000733, 0x00000912,
+    0x00000b6d, 0x00000e66, 0x00001224, 0x000016db,
+    0x00001ccc, 0x00002449, 0x00002db7, 0x00003999,
+    0x00004892, 0x00005b6f, 0x00007333, 0x00009124,
+    0x0000b6de, 0x0000e666, 0x00012249, 0x00016dbc,
+    0x0001cccc, 0x00024492, 0x0002db79, 0x00039999,
+    0x00048924, 0x0005b6f2, 0x00073333, 0x00091249,
+    0x000b6de5, 0x000e6666, 0x00122492, 0x0016dbcb,
+    0x001ccccc, 0x00244924, 0x002db796, 0x00399998,
+};
+
+static RK_U32 h264e_lambda_cvr[60] = {
+    0x00000009, 0x0000000b, 0x0000000e, 0x00000011,
+    0x00000016, 0x0000001b, 0x00000022, 0x0000002b,
+    0x00000036, 0x00000045, 0x00000056, 0x0000006d,
+    0x00000089, 0x000000ad, 0x000000da, 0x00000112,
+    0x00000159, 0x000001b3, 0x00000224, 0x000002b3,
+    0x00000366, 0x00000449, 0x00000566, 0x000006cd,
+    0x00000891, 0x00000acb, 0x00000d9a, 0x000013c1,
+    0x000018e4, 0x00001f5c, 0x00002783, 0x000031c8,
+    0x00003eb8, 0x00004f06, 0x00006390, 0x00008e14,
+    0x0000b302, 0x0000e18a, 0x00011c29, 0x00016605,
+    0x0001c313, 0x00027ae1, 0x00031fe6, 0x0003efcf,
+    0x0004f5c3, 0x0006e785, 0x0008b2ef, 0x000af5c3,
+    0x000f1e7a, 0x00130c7f, 0x00180000, 0x001e3cf4,
+    0x002618fe, 0x00300000, 0x003c79e8, 0x004c31fc,
+    0x00600000, 0x0078f3d0, 0x009863f8, 0x0c000000,
+};
+
+static void
+setup_vepu510_l2(HalH264eVepu510Ctx *ctx, MppEncHwCfg *hw)
+{
+    HalVepu510RegSet *regs = ctx->regs_set;
+    MppEncSceneMode sm = ctx->cfg->tune.scene_mode;
+    RK_S32 lambda_idx = ctx->cfg->tune.lambda_idx_i; //TODO: lambda_idx_p
+
+    hal_h264e_dbg_func("enter\n");
+
+    if (sm == MPP_ENC_SCENE_MODE_IPC) {
+        memcpy(regs->reg_param.rdo_wgta_qp_grpa_0_51,
+               &h264e_lambda_default[lambda_idx], H264E_LAMBDA_TAB_SIZE);
+    } else {
+        memcpy(regs->reg_param.rdo_wgta_qp_grpa_0_51,
+               &h264e_lambda_cvr[lambda_idx], H264E_LAMBDA_TAB_SIZE);
+    }
+
+    if (hw->qbias_en) {
+        regs->reg_param.qnt_bias_comb.qnt_f_bias_i = hw->qbias_i;
+        regs->reg_param.qnt_bias_comb.qnt_f_bias_p = hw->qbias_p;
+    } else {
+        regs->reg_param.qnt_bias_comb.qnt_f_bias_i = 683;
+        regs->reg_param.qnt_bias_comb.qnt_f_bias_p = 341;
+    }
+
+    hal_h264e_dbg_func("leave\n");
+}
+
+static void setup_vepu510_ext_line_buf(HalVepu510RegSet *regs, HalH264eVepu510Ctx *ctx)
+{
+    H264eVepu510Frame *reg_frm = &regs->reg_frm;
+    MppDevRcbInfoCfg rcb_cfg;
+    RK_S32 offset = 0;
+    RK_S32 fd;
+
+    if (!ctx->ext_line_buf) {
+        reg_frm->common.ebufb_addr = 0;
+        reg_frm->common.ebufb_addr = 0;
+        return;
+    }
+
+    fd = mpp_buffer_get_fd(ctx->ext_line_buf);
+    offset = ctx->ext_line_buf_size;
+
+    reg_frm->common.ebuft_addr = fd;
+    reg_frm->common.ebufb_addr = fd;
+
+    mpp_dev_multi_offset_update(ctx->offsets, 178, offset);
+
+    /* rcb info for sram */
+    rcb_cfg.reg_idx = 179;
+    rcb_cfg.size = offset;
+
+    mpp_dev_ioctl(ctx->dev, MPP_DEV_RCB_INFO, &rcb_cfg);
+
+    rcb_cfg.reg_idx = 178;
+    rcb_cfg.size = 0;
+
+    mpp_dev_ioctl(ctx->dev, MPP_DEV_RCB_INFO, &rcb_cfg);
+}
+
+static MPP_RET setup_vepu510_dual_core(HalH264eVepu510Ctx *ctx, H264SliceType slice_type)
+{
+    H264eVepu510Frame *reg_frm = &ctx->regs_set->reg_frm;
+    RK_U32 dchs_ofst = 9;
+    RK_U32 dchs_rxe  = 1;
+    RK_U32 dchs_dly  = 0;
+
+    if (ctx->task_cnt == 1)
+        return MPP_OK;
+
+    if (slice_type == H264_I_SLICE) {
+        ctx->curr_idx = 0;
+        ctx->prev_idx = 0;
+        dchs_rxe = 0;
+    }
+
+    reg_frm->common.dual_core.dchs_txid = ctx->curr_idx;
+    reg_frm->common.dual_core.dchs_rxid = ctx->prev_idx;
+    reg_frm->common.dual_core.dchs_txe  = 1;
+    reg_frm->common.dual_core.dchs_rxe  = dchs_rxe;
+    reg_frm->common.dual_core.dchs_ofst = dchs_ofst;
+    reg_frm->common.dual_core.dchs_dly  = dchs_dly;
+
+    ctx->prev_idx = ctx->curr_idx++;
+    if (ctx->curr_idx > 3)
+        ctx->curr_idx = 0;
+
+    return MPP_OK;
+}
+
+static void setup_vepu510_aq(HalH264eVepu510Ctx *ctx)
+{
+    MppEncCfgSet *cfg = ctx->cfg;
+    MppEncHwCfg *hw = &cfg->hw;
+    Vepu510RcRoi *s = &ctx->regs_set->reg_rc_roi;
+    RK_U8* thd = (RK_U8*)&s->aq_tthd0;
+    RK_S32 *aq_step, *aq_thd;
+    RK_U8 i;
+
+    if (ctx->slice->slice_type == H264_I_SLICE) {
+        aq_thd = (RK_S32 *)&hw->aq_thrd_i[0];
+        aq_step = &hw->aq_step_i[0];
+    } else {
+        aq_thd = (RK_S32 *)&hw->aq_thrd_p[0];
+        aq_step = &hw->aq_step_p[0];
+    }
+
+    for (i = 0; i < 16; i++)
+        thd[i] = aq_thd[i] & 0xff;
+
+    s->aq_stp0.aq_stp_s0 = aq_step[0] & 0x1f;
+    s->aq_stp0.aq_stp_0t1 = aq_step[1] & 0x1f;
+    s->aq_stp0.aq_stp_1t2 = aq_step[2] & 0x1f;
+    s->aq_stp0.aq_stp_2t3 = aq_step[3] & 0x1f;
+    s->aq_stp0.aq_stp_3t4 = aq_step[4] & 0x1f;
+    s->aq_stp0.aq_stp_4t5 = aq_step[5] & 0x1f;
+    s->aq_stp1.aq_stp_5t6 = aq_step[6] & 0x1f;
+    s->aq_stp1.aq_stp_6t7 = aq_step[7] & 0x1f;
+    s->aq_stp1.aq_stp_7t8 = 0;
+    s->aq_stp1.aq_stp_8t9 = aq_step[8] & 0x1f;
+    s->aq_stp1.aq_stp_9t10 = aq_step[9] & 0x1f;
+    s->aq_stp1.aq_stp_10t11 = aq_step[10] & 0x1f;
+    s->aq_stp2.aq_stp_11t12 = aq_step[11] & 0x1f;
+    s->aq_stp2.aq_stp_12t13 = aq_step[12] & 0x1f;
+    s->aq_stp2.aq_stp_13t14 = aq_step[13] & 0x1f;
+    s->aq_stp2.aq_stp_14t15 = aq_step[14] & 0x1f;
+    s->aq_stp2.aq_stp_b15 = aq_step[15] & 0x1f;
+}
+
+static void setup_vepu510_anti_stripe(HalH264eVepu510Ctx *ctx)
+{
+    HalVepu510RegSet *regs = ctx->regs_set;
+    H264eVepu510Param *s = &regs->reg_param;
+    RK_S32 str = ctx->cfg->tune.atl_str;
+
+    s->iprd_tthdy4_0.iprd_tthdy4_0 = 1;
+    s->iprd_tthdy4_0.iprd_tthdy4_1 = 3;
+    s->iprd_tthdy4_1.iprd_tthdy4_2 = 6;
+    s->iprd_tthdy4_1.iprd_tthdy4_3 = 8;
+    s->iprd_tthdc8_0.iprd_tthdc8_0 = 1;
+    s->iprd_tthdc8_0.iprd_tthdc8_1 = 3;
+    s->iprd_tthdc8_1.iprd_tthdc8_2 = 6;
+    s->iprd_tthdc8_1.iprd_tthdc8_3 = 8;
+    s->iprd_tthdy8_0.iprd_tthdy8_0 = 1;
+    s->iprd_tthdy8_0.iprd_tthdy8_1 = 3;
+    s->iprd_tthdy8_1.iprd_tthdy8_2 = 6;
+    s->iprd_tthdy8_1.iprd_tthdy8_3 = 8;
+
+    if (ctx->cfg->tune.scene_mode != MPP_ENC_SCENE_MODE_IPC)
+        s->iprd_tthd_ul.iprd_tthd_ul = 4095; /* disable anti-stripe */
+    else
+        s->iprd_tthd_ul.iprd_tthd_ul = str ? 4 : 255;
+
+    s->iprd_wgty8.iprd_wgty8_0 = str ? 22 : 16;
+    s->iprd_wgty8.iprd_wgty8_1 = str ? 23 : 16;
+    s->iprd_wgty8.iprd_wgty8_2 = str ? 20 : 16;
+    s->iprd_wgty8.iprd_wgty8_3 = str ? 22 : 16;
+    s->iprd_wgty4.iprd_wgty4_0 = str ? 22 : 16;
+    s->iprd_wgty4.iprd_wgty4_1 = str ? 26 : 16;
+    s->iprd_wgty4.iprd_wgty4_2 = str ? 20 : 16;
+    s->iprd_wgty4.iprd_wgty4_3 = str ? 22 : 16;
+    s->iprd_wgty16.iprd_wgty16_0 = 22;
+    s->iprd_wgty16.iprd_wgty16_1 = 26;
+    s->iprd_wgty16.iprd_wgty16_2 = 20;
+    s->iprd_wgty16.iprd_wgty16_3 = 22;
+    s->iprd_wgtc8.iprd_wgtc8_0 = 18;
+    s->iprd_wgtc8.iprd_wgtc8_1 = 21;
+    s->iprd_wgtc8.iprd_wgtc8_2 = 20;
+    s->iprd_wgtc8.iprd_wgtc8_3 = 19;
+}
+
+static void setup_vepu510_anti_ringing(HalH264eVepu510Ctx *ctx)
+{
+    HalVepu510RegSet *regs = ctx->regs_set;
+    H264eVepu510Param *s = &regs->reg_param;
+    MppEncSceneMode sm = ctx->cfg->tune.scene_mode;
+
+    s->atr_thd1.thdqp = (sm == MPP_ENC_SCENE_MODE_IPC) ? 32 : 45;
+    if (ctx->slice->slice_type == H264_I_SLICE) {
+        s->atr_thd0.thd0 = 1;
+        s->atr_thd0.thd1 = 2;
+        s->atr_thd1.thd2 = 6;
+        s->atr_wgt16.atr_lv16_wgt0 = 16;
+        s->atr_wgt16.atr_lv16_wgt1 = 16;
+        s->atr_wgt16.atr_lv16_wgt2 = 16;
+
+        if (sm == MPP_ENC_SCENE_MODE_IPC) {
+            s->atr_wgt8.atr_lv8_wgt0 = 22;
+            s->atr_wgt8.atr_lv8_wgt1 = 21;
+            s->atr_wgt8.atr_lv8_wgt2 = 20;
+            s->atr_wgt4.atr_lv4_wgt0 = 20;
+            s->atr_wgt4.atr_lv4_wgt1 = 18;
+            s->atr_wgt4.atr_lv4_wgt2 = 16;
+        } else {
+            s->atr_wgt8.atr_lv8_wgt0 = 18;
+            s->atr_wgt8.atr_lv8_wgt1 = 17;
+            s->atr_wgt8.atr_lv8_wgt2 = 18;
+            s->atr_wgt4.atr_lv4_wgt0 = 16;
+            s->atr_wgt4.atr_lv4_wgt1 = 16;
+            s->atr_wgt4.atr_lv4_wgt2 = 16;
+        }
+    } else {
+        if (sm == MPP_ENC_SCENE_MODE_IPC) {
+            s->atr_thd0.thd0 = 2;
+            s->atr_thd0.thd1 = 4;
+            s->atr_thd1.thd2 = 9;
+            s->atr_wgt16.atr_lv16_wgt0 = 25;
+            s->atr_wgt16.atr_lv16_wgt1 = 20;
+            s->atr_wgt16.atr_lv16_wgt2 = 16;
+            s->atr_wgt8.atr_lv8_wgt0 = 25;
+            s->atr_wgt8.atr_lv8_wgt1 = 20;
+            s->atr_wgt8.atr_lv8_wgt2 = 18;
+            s->atr_wgt4.atr_lv4_wgt0 = 25;
+            s->atr_wgt4.atr_lv4_wgt1 = 20;
+            s->atr_wgt4.atr_lv4_wgt2 = 16;
+        } else {
+            s->atr_thd0.thd0 = 1;
+            s->atr_thd0.thd1 = 2;
+            s->atr_thd1.thd2 = 7;
+            s->atr_wgt16.atr_lv16_wgt0 = 23;
+            s->atr_wgt16.atr_lv16_wgt1 = 22;
+            s->atr_wgt16.atr_lv16_wgt2 = 20;
+            s->atr_wgt8.atr_lv8_wgt0 = 24;
+            s->atr_wgt8.atr_lv8_wgt1 = 24;
+            s->atr_wgt8.atr_lv8_wgt2 = 24;
+            s->atr_wgt4.atr_lv4_wgt0 = 23;
+            s->atr_wgt4.atr_lv4_wgt1 = 22;
+            s->atr_wgt4.atr_lv4_wgt2 = 20;
+        }
+    }
+}
+
+static void setup_vepu510_anti_flicker(HalH264eVepu510Ctx *ctx)
+{
+    HalVepu510RegSet *regs = ctx->regs_set;
+    H264eVepu510Sqi *reg = &regs->reg_sqi;
+    RK_U32 str = ctx->cfg->tune.anti_flicker_str;
+    rdo_skip_par *p_skip = NULL;
+    rdo_noskip_par *p_no_skip = NULL;
+
+    static RK_U8 pskip_atf_th0[4] = { 0, 0, 0, 1 };
+    static RK_U8 pskip_atf_th1[4] = { 7, 7, 7, 10 };
+    static RK_U8 pskip_atf_wgt0[4] = { 16, 16, 16, 20 };
+    static RK_U8 pskip_atf_wgt1[4] = { 16, 16, 14, 16 };
+    static RK_U8 intra_atf_th0[4] = { 8, 16, 20, 20 };
+    static RK_U8 intra_atf_th1[4] = { 16, 32, 40, 40 };
+    static RK_U8 intra_atf_th2[4] = { 32, 56, 72, 72 };
+    static RK_U8 intra_atf_wgt0[4] = { 16, 24, 27, 27 };
+    static RK_U8 intra_atf_wgt1[4] = { 16, 22, 25, 25 };
+    static RK_U8 intra_atf_wgt2[4] = { 16, 19, 20, 20 };
+
+    p_skip = &reg->rdo_b16_skip;
+    p_skip->atf_thd0.madp_thd0 = pskip_atf_th0[str];
+    p_skip->atf_thd0.madp_thd1 = pskip_atf_th1[str];
+    p_skip->atf_thd1.madp_thd2 = 15;
+    p_skip->atf_thd1.madp_thd3 = 25;
+    p_skip->atf_wgt0.wgt0 = pskip_atf_wgt0[str];
+    p_skip->atf_wgt0.wgt1 = pskip_atf_wgt1[str];
+    p_skip->atf_wgt0.wgt2 = 16;
+    p_skip->atf_wgt0.wgt3 = 16;
+    p_skip->atf_wgt1.wgt4 = 16;
+
+    p_no_skip = &reg->rdo_b16_inter;
+    p_no_skip->ratf_thd0.madp_thd0 = 20;
+    p_no_skip->ratf_thd0.madp_thd1 = 40;
+    p_no_skip->ratf_thd1.madp_thd2 = 72;
+    p_no_skip->atf_wgt.wgt0 = 16;
+    p_no_skip->atf_wgt.wgt1 = 16;
+    p_no_skip->atf_wgt.wgt2 = 16;
+    p_no_skip->atf_wgt.wgt3 = 16;
+
+    p_no_skip = &reg->rdo_b16_intra;
+    p_no_skip->ratf_thd0.madp_thd0 = intra_atf_th0[str];
+    p_no_skip->ratf_thd0.madp_thd1 = intra_atf_th1[str];
+    p_no_skip->ratf_thd1.madp_thd2 = intra_atf_th2[str];
+    p_no_skip->atf_wgt.wgt0 = intra_atf_wgt0[str];
+    p_no_skip->atf_wgt.wgt1 = intra_atf_wgt1[str];
+    p_no_skip->atf_wgt.wgt2 = intra_atf_wgt2[str];
+    p_no_skip->atf_wgt.wgt3 = 16;
+
+    reg->rdo_b16_intra_atf_cnt_thd.thd0 = 1;
+    reg->rdo_b16_intra_atf_cnt_thd.thd1 = 4;
+    reg->rdo_b16_intra_atf_cnt_thd.thd2 = 1;
+    reg->rdo_b16_intra_atf_cnt_thd.thd3 = 4;
+
+    reg->rdo_atf_resi_thd.big_th0 = 16;
+    reg->rdo_atf_resi_thd.big_th1 = 16;
+    reg->rdo_atf_resi_thd.small_th0 = 8;
+    reg->rdo_atf_resi_thd.small_th1 = 8;
+}
+
+static void setup_vepu510_anti_smear(HalH264eVepu510Ctx *ctx)
+{
+    HalVepu510RegSet *regs = ctx->regs_set;
+    H264eVepu510Sqi *reg = &regs->reg_sqi;
+    H264eSlice *slice = ctx->slice;
+    Vepu510H264Fbk *last_fb = &ctx->last_frame_fb;
+    RK_U32 mb_cnt = last_fb->st_mb_num;
+    RK_U32 *smear_cnt = last_fb->st_smear_cnt;
+    RK_S32 deblur_str = ctx->cfg->tune.deblur_str;
+    RK_S32 delta_qp = 0;
+    RK_S32 flg0 = smear_cnt[4] < (mb_cnt >> 6);
+    RK_S32 flg1 = 1, flg2 = 0, flg3 = 0;
+    RK_S32 smear_multi[4] = { 9, 12, 16, 16 };
+
+    hal_h264e_dbg_func("enter\n");
+
+    if ((smear_cnt[3] < ((5 * mb_cnt) >> 10)) ||
+        (smear_cnt[3] < ((1126 * MPP_MAX3(smear_cnt[0], smear_cnt[1], smear_cnt[2])) >> 10)) ||
+        (deblur_str == 6) || (deblur_str == 7))
+        flg1 = 0;
+
+    flg3 = flg1 ? 3 : (smear_cnt[4] > ((102 * mb_cnt) >> 10)) ? 2 :
+           (smear_cnt[4] > ((66 * mb_cnt) >> 10)) ? 1 : 0;
+
+    if (ctx->cfg->tune.scene_mode == MPP_ENC_SCENE_MODE_IPC) {
+        reg->smear_opt_cfg.rdo_smear_en = ctx->qpmap_en;
+        if (ctx->qpmap_en && deblur_str > 3)
+            reg->smear_opt_cfg.rdo_smear_lvl16_multi = smear_multi[flg3];
+        else
+            reg->smear_opt_cfg.rdo_smear_lvl16_multi = flg0 ? 9 : 12;
+    } else {
+        reg->smear_opt_cfg.rdo_smear_en = 0;
+        reg->smear_opt_cfg.rdo_smear_lvl16_multi = 16;
+    }
+
+    if (ctx->qpmap_en && deblur_str > 3) {
+        flg2 = 1;
+        if (smear_cnt[2] + smear_cnt[3] > (3 * smear_cnt[4] / 4))
+            delta_qp = 1;
+        if (smear_cnt[4] < (mb_cnt >> 4))
+            delta_qp -= 8;
+        else if (smear_cnt[4] < ((3 * mb_cnt) >> 5))
+            delta_qp -= 7;
+        else
+            delta_qp -= 6;
+
+        if (flg3 == 2)
+            delta_qp = 0;
+        else if (flg3 == 1)
+            delta_qp = -2;
+    } else {
+        if (smear_cnt[2] + smear_cnt[3] > smear_cnt[4] / 2)
+            delta_qp = 1;
+        if (smear_cnt[4] < (mb_cnt >> 8))
+            delta_qp -= (deblur_str < 2) ? 6 : 8;
+        else if (smear_cnt[4] < (mb_cnt >> 7))
+            delta_qp -= (deblur_str < 2) ? 5 : 6;
+        else if (smear_cnt[4] < (mb_cnt >> 6))
+            delta_qp -= (deblur_str < 2) ? 3 : 4;
+        else
+            delta_qp -= 1;
+    }
+    reg->smear_opt_cfg.rdo_smear_dlt_qp = delta_qp;
+
+    if ((H264_I_SLICE == slice->slice_type) ||
+        (H264_I_SLICE == last_fb->frame_type))
+        reg->smear_opt_cfg.stated_mode = 1;
+    else
+        reg->smear_opt_cfg.stated_mode = 2;
+
+    reg->smear_madp_thd0.madp_cur_thd0 = 0;
+    reg->smear_madp_thd0.madp_cur_thd1 = flg2 ? 48 : 24;
+    reg->smear_madp_thd1.madp_cur_thd2 = flg2 ? 64 : 48;
+    reg->smear_madp_thd1.madp_cur_thd3 = flg2 ? 72 : 64;
+    reg->smear_madp_thd2.madp_around_thd0 = flg2 ? 4095 : 16;
+    reg->smear_madp_thd2.madp_around_thd1 = 32;
+    reg->smear_madp_thd3.madp_around_thd2 = 48;
+    reg->smear_madp_thd3.madp_around_thd3 = flg2 ? 0 : 96;
+    reg->smear_madp_thd4.madp_around_thd4 = 48;
+    reg->smear_madp_thd4.madp_around_thd5 = 24;
+    reg->smear_madp_thd5.madp_ref_thd0 = flg2 ? 64 : 96;
+    reg->smear_madp_thd5.madp_ref_thd1 = 48;
+
+    reg->smear_cnt_thd0.cnt_cur_thd0 = flg2 ?  2 : 1;
+    reg->smear_cnt_thd0.cnt_cur_thd1 = flg2 ?  5 : 3;
+    reg->smear_cnt_thd0.cnt_cur_thd2 = 1;
+    reg->smear_cnt_thd0.cnt_cur_thd3 = 3;
+    reg->smear_cnt_thd1.cnt_around_thd0 = 1;
+    reg->smear_cnt_thd1.cnt_around_thd1 = 4;
+    reg->smear_cnt_thd1.cnt_around_thd2 = 1;
+    reg->smear_cnt_thd1.cnt_around_thd3 = 4;
+    reg->smear_cnt_thd2.cnt_around_thd4 = 0;
+    reg->smear_cnt_thd2.cnt_around_thd5 = 3;
+    reg->smear_cnt_thd2.cnt_around_thd6 = 0;
+    reg->smear_cnt_thd2.cnt_around_thd7 = 3;
+    reg->smear_cnt_thd3.cnt_ref_thd0 = 1;
+    reg->smear_cnt_thd3.cnt_ref_thd1 = 3;
+
+    reg->smear_resi_thd0.resi_small_cur_th0 = 6;
+    reg->smear_resi_thd0.resi_big_cur_th0 = 9;
+    reg->smear_resi_thd0.resi_small_cur_th1 = 6;
+    reg->smear_resi_thd0.resi_big_cur_th1 = 9;
+    reg->smear_resi_thd1.resi_small_around_th0 = 6;
+    reg->smear_resi_thd1.resi_big_around_th0 = 11;
+    reg->smear_resi_thd1.resi_small_around_th1 = 6;
+    reg->smear_resi_thd1.resi_big_around_th1 = 8;
+    reg->smear_resi_thd2.resi_small_around_th2 = 9;
+    reg->smear_resi_thd2.resi_big_around_th2 = 20;
+    reg->smear_resi_thd2.resi_small_around_th3 = 6;
+    reg->smear_resi_thd2.resi_big_around_th3 = 20;
+    reg->smear_resi_thd3.resi_small_ref_th0 = 7;
+    reg->smear_resi_thd3.resi_big_ref_th0 = 16;
+    reg->smear_resi_thd4.resi_th0 = flg2 ? 0 : 10;
+    reg->smear_resi_thd4.resi_th1 = flg2 ? 0 : 6;
+
+    reg->smear_st_thd.madp_cnt_th0 = flg2 ? 0 : 1;
+    reg->smear_st_thd.madp_cnt_th1 = flg2 ? 0 : 5;
+    reg->smear_st_thd.madp_cnt_th2 = flg2 ? 0 : 1;
+    reg->smear_st_thd.madp_cnt_th3 = flg2 ? 0 : 3;
+
+    hal_h264e_dbg_func("leave\n");
+}
+
+static void setup_vepu510_scaling_list(HalH264eVepu510Ctx *ctx)
+{
+    HalVepu510RegSet *regs = ctx->regs_set;
+    Vepu510SclCfg *s = &regs->reg_scl;
+    RK_U8 *p = (RK_U8 *)&s->tu8_intra_y[0];
+    RK_U8 idx;
+
+    hal_h264e_dbg_func("enter\n");
+
+    /* intra4x4 and inter4x4 is not supported on VEPU500.
+     * valid range: 0x2200 ~ 0x221F
+     */
+    if (ctx->pps->pic_scaling_matrix_present == 1) {
+        for (idx = 0; idx < 64; idx++) {
+            p[idx] = vepu510_h264_cqm_jvt8i[63 - idx]; /* intra8x8 */
+            p[idx + 64] = vepu510_h264_cqm_jvt8p[63 - idx]; /* inter8x8 */
+        }
+    } else if (ctx->pps->pic_scaling_matrix_present == 2) {
+        //TODO: Update scaling list for (scaling_list_mode == 2)
+        mpp_log_f("scaling_list_mode 2 is not supported yet\n");
+    }
+
+    hal_h264e_dbg_func("leave\n");
+}
+
+static MPP_RET hal_h264e_vepu510_gen_regs(void *hal, HalEncTask *task)
+{
+    HalH264eVepu510Ctx *ctx = (HalH264eVepu510Ctx *)hal;
+    HalVepu510RegSet *regs = ctx->regs_set;
+    H264eVepu510Frame *reg_frm = &regs->reg_frm;
+    MppEncCfgSet *cfg = ctx->cfg;
+    H264eSps *sps = ctx->sps;
+    H264ePps *pps = ctx->pps;
+    H264eSlice *slice = ctx->slice;
+    EncRcTask *rc_task = task->rc_task;
+    EncFrmStatus *frm = &rc_task->frm;
+    MPP_RET ret = MPP_OK;
+    EncFrmStatus *frm_status = &task->rc_task->frm;
+
+    hal_h264e_dbg_func("enter %p\n", hal);
+    hal_h264e_dbg_detail("frame %d generate regs now", ctx->frms->seq_idx);
+
+    /* register setup */
+    memset(regs, 0, sizeof(*regs));
+
+    setup_vepu510_normal(regs);
+    ret = setup_vepu510_prep(regs, &ctx->cfg->prep);
+    if (ret)
+        return ret;
+
+    setup_vepu510_dual_core(ctx, slice->slice_type);
+    setup_vepu510_codec(regs, sps, pps, slice);
+    setup_vepu510_rdo_pred(ctx, sps, pps, slice);
+    setup_vepu510_aq(ctx);
+    setup_vepu510_anti_stripe(ctx);
+    setup_vepu510_anti_ringing(ctx);
+    setup_vepu510_anti_flicker(ctx);
+    setup_vepu510_anti_smear(ctx);
+    setup_vepu510_scaling_list(ctx);
+
+    setup_vepu510_rc_base(regs, ctx, rc_task);
+    setup_vepu510_io_buf(regs, ctx->offsets, task);
+    setup_vepu510_recn_refr(ctx, regs);
+
+    reg_frm->common.meiw_addr = task->md_info ? mpp_buffer_get_fd(task->md_info) : 0;
+    reg_frm->common.enc_pic.mei_stor = 0;
+
+    reg_frm->common.pic_ofst.pic_ofst_y = mpp_frame_get_offset_y(task->frame);
+    reg_frm->common.pic_ofst.pic_ofst_x = mpp_frame_get_offset_x(task->frame);
+
+    setup_vepu510_split(regs, cfg);
+    setup_vepu510_me(ctx);
+
+    if (frm_status->is_i_refresh)
+        setup_vepu510_intra_refresh(regs, ctx, frm_status->seq_idx % cfg->rc.gop);
+
+    setup_vepu510_l2(ctx, &cfg->hw);
+    setup_vepu510_ext_line_buf(regs, ctx);
+    if (ctx->roi_data)
+        vepu510_set_roi(&ctx->regs_set->reg_rc_roi.roi_cfg, ctx->roi_data,
+                        ctx->cfg->prep.width, ctx->cfg->prep.height);
+
+    vepu510_h264e_tune_reg_patch(ctx->tune);
+
+    /* two pass register patch */
+    if (frm->save_pass1)
+        vepu510_h264e_save_pass1_patch(regs, ctx);
+
+    if (frm->use_pass1)
+        vepu510_h264e_use_pass1_patch(regs, ctx);
+
+    ctx->frame_cnt++;
+
+    hal_h264e_dbg_func("leave %p\n", hal);
+    return MPP_OK;
+}
+
+static MPP_RET hal_h264e_vepu510_start(void *hal, HalEncTask *task)
+{
+    MPP_RET ret = MPP_OK;
+    HalH264eVepu510Ctx *ctx = (HalH264eVepu510Ctx *)hal;
+    HalVepu510RegSet *regs = ctx->regs_set;
+
+    (void) task;
+
+    hal_h264e_dbg_func("enter %p\n", hal);
+
+    do {
+        MppDevRegWrCfg wr_cfg;
+        MppDevRegRdCfg rd_cfg;
+
+        wr_cfg.reg = &regs->reg_ctl;
+        wr_cfg.size = sizeof(regs->reg_ctl);
+        wr_cfg.offset = VEPU510_CTL_OFFSET;
+#if DUMP_REG
+        {
+            RK_U32 i;
+            RK_U32 *reg = (RK_U32)wr_cfg.reg;
+            for ( i = 0; i < sizeof(regs->reg_ctl) / sizeof(RK_U32); i++) {
+                mpp_log("reg[%d] = 0x%08x\n", i, reg[i]);
+            }
+
+        }
+#endif
+        ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);
+        if (ret) {
+            mpp_err_f("set register write failed %d\n", ret);
+            break;
+        }
+
+        wr_cfg.reg = &regs->reg_frm;
+        wr_cfg.size = sizeof(regs->reg_frm);
+        wr_cfg.offset = VEPU510_FRAME_OFFSET;
+
+        ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);
+        if (ret) {
+            mpp_err_f("set register write failed %d\n", ret);
+            break;
+        }
+
+        wr_cfg.reg = &regs->reg_rc_roi;
+        wr_cfg.size = sizeof(regs->reg_rc_roi);
+        wr_cfg.offset = VEPU510_RC_ROI_OFFSET;
+
+        ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);
+        if (ret) {
+            mpp_err_f("set register write failed %d\n", ret);
+            break;
+        }
+
+        wr_cfg.reg = &regs->reg_param;
+        wr_cfg.size = sizeof(regs->reg_param);
+        wr_cfg.offset = VEPU510_PARAM_OFFSET;
+
+        ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);
+        if (ret) {
+            mpp_err_f("set register write failed %d\n", ret);
+            break;
+        }
+
+        wr_cfg.reg = &regs->reg_sqi;
+        wr_cfg.size = sizeof(regs->reg_sqi);
+        wr_cfg.offset = VEPU510_SQI_OFFSET;
+
+        ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);
+        if (ret) {
+            mpp_err_f("set register write failed %d\n", ret);
+            break;
+        }
+
+        wr_cfg.reg = &regs->reg_scl;
+        wr_cfg.size = sizeof(regs->reg_scl);
+        wr_cfg.offset = VEPU510_SCL_OFFSET ;
+
+        ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);
+        if (ret) {
+            mpp_err_f("set register write failed %d\n", ret);
+            break;
+        }
+
+        ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFS, ctx->offsets);
+        if (ret) {
+            mpp_err_f("set register offsets failed %d\n", ret);
+            break;
+        }
+
+        rd_cfg.reg = &regs->reg_ctl.int_sta;
+        rd_cfg.size = sizeof(RK_U32);
+        rd_cfg.offset = VEPU510_REG_BASE_HW_STATUS;
+        ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg);
+        if (ret) {
+            mpp_err_f("set register read failed %d\n", ret);
+            break;
+        }
+
+        rd_cfg.reg = &regs->reg_st;
+        rd_cfg.size = sizeof(regs->reg_st);
+        rd_cfg.offset = VEPU510_STATUS_OFFSET;
+
+        ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg);
+        if (ret) {
+            mpp_err_f("set register read failed %d\n", ret);
+            break;
+        }
+
+        /* send request to hardware */
+        ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL);
+        if (ret) {
+            mpp_err_f("send cmd failed %d\n", ret);
+            break;
+        }
+    } while (0);
+
+    hal_h264e_dbg_func("leave %p\n", hal);
+
+    return ret;
+}
+
+static MPP_RET hal_h264e_vepu510_status_check(HalVepu510RegSet *regs)
+{
+    MPP_RET ret = MPP_OK;
+
+    if (regs->reg_ctl.int_sta.lkt_node_done_sta)
+        hal_h264e_dbg_detail("lkt_done finish");
+
+    if (regs->reg_ctl.int_sta.enc_done_sta)
+        hal_h264e_dbg_detail("enc_done finish");
+
+    if (regs->reg_ctl.int_sta.vslc_done_sta)
+        hal_h264e_dbg_detail("enc_slice finsh");
+
+    if (regs->reg_ctl.int_sta.sclr_done_sta)
+        hal_h264e_dbg_detail("safe clear finsh");
+
+    if (regs->reg_ctl.int_sta.vbsf_oflw_sta) {
+        mpp_err_f("bit stream overflow");
+        ret = MPP_NOK;
+    }
+
+    if (regs->reg_ctl.int_sta.vbuf_lens_sta) {
+        mpp_err_f("bus write full");
+        ret = MPP_NOK;
+    }
+
+    if (regs->reg_ctl.int_sta.enc_err_sta) {
+        mpp_err_f("bus error");
+        ret = MPP_NOK;
+    }
+
+    if (regs->reg_ctl.int_sta.wdg_sta) {
+        mpp_err_f("wdg timeout");
+        ret = MPP_NOK;
+    }
+
+    return ret;
+}
+
+static MPP_RET hal_h264e_vepu510_wait(void *hal, HalEncTask *task)
+{
+    MPP_RET ret = MPP_OK;
+    HalH264eVepu510Ctx *ctx = (HalH264eVepu510Ctx *)hal;
+    HalVepu510RegSet *regs = &ctx->regs_sets[task->flags.reg_idx];
+    RK_U32 split_out = ctx->cfg->split.split_out;
+    MppPacket pkt = task->packet;
+    RK_S32 offset = mpp_packet_get_length(pkt);
+    H264NaluType type = task->rc_task->frm.is_idr ?  H264_NALU_TYPE_IDR : H264_NALU_TYPE_SLICE;
+    MppEncH264HwCfg *hw_cfg = &ctx->cfg->codec.h264.hw_cfg;
+    RK_S32 i;
+
+    hal_h264e_dbg_func("enter %p\n", hal);
+
+    /* if pass1 mode, it will disable split mode and the split out need to be disable */
+    if (task->rc_task->frm.save_pass1)
+        split_out = 0;
+
+    /* update split_out in hw_cfg */
+    hw_cfg->hw_split_out = split_out;
+
+    if (split_out) {
+        EncOutParam param;
+        RK_U32 slice_len;
+        RK_U32 slice_last;
+        MppDevPollCfg *poll_cfg = (MppDevPollCfg *)((char *)ctx->poll_cfgs +
+                                                    task->flags.reg_idx * ctx->poll_cfg_size);
+        param.task = task;
+        param.base = mpp_packet_get_data(task->packet);
+
+        do {
+            poll_cfg->poll_type = 0;
+            poll_cfg->poll_ret  = 0;
+            poll_cfg->count_max = ctx->poll_slice_max;
+            poll_cfg->count_ret = 0;
+
+            ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, poll_cfg);
+
+            for (i = 0; i < poll_cfg->count_ret; i++) {
+                slice_last = poll_cfg->slice_info[i].last;
+                slice_len = poll_cfg->slice_info[i].length;
+
+                mpp_packet_add_segment_info(pkt, type, offset, slice_len);
+                offset += slice_len;
+
+                if (split_out & MPP_ENC_SPLIT_OUT_LOWDELAY) {
+                    param.length = slice_len;
+
+                    if (slice_last)
+                        ctx->output_cb->cmd = ENC_OUTPUT_FINISH;
+                    else
+                        ctx->output_cb->cmd = ENC_OUTPUT_SLICE;
+
+                    mpp_callback(ctx->output_cb, &param);
+                }
+            }
+        } while (!slice_last);
+
+        ret = hal_h264e_vepu510_status_check(regs);
+        if (!ret)
+            task->hw_length += regs->reg_st.bs_lgth_l32;
+    } else {
+        ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, NULL);
+        if (ret) {
+            mpp_err_f("poll cmd failed %d\n", ret);
+            ret = MPP_ERR_VPUHW;
+        } else {
+            ret = hal_h264e_vepu510_status_check(regs);
+            if (!ret)
+                task->hw_length += regs->reg_st.bs_lgth_l32;
+        }
+
+        mpp_packet_add_segment_info(pkt, type, offset, regs->reg_st.bs_lgth_l32);
+    }
+
+    if (!(split_out & MPP_ENC_SPLIT_OUT_LOWDELAY) && !ret) {
+        HalH264eVepuStreamAmend *amend = &ctx->amend_sets[task->flags.reg_idx];
+
+        if (amend->enable) {
+            amend->old_length = task->hw_length;
+            amend->slice->is_multi_slice = (ctx->cfg->split.split_mode > 0);
+            h264e_vepu_stream_amend_proc(amend, &ctx->cfg->codec.h264.hw_cfg);
+            task->hw_length = amend->new_length;
+        } else if (amend->prefix) {
+            /* check prefix value */
+            amend->old_length = task->hw_length;
+            h264e_vepu_stream_amend_sync_ref_idc(amend);
+        }
+    }
+
+    hal_h264e_dbg_func("leave %p ret %d\n", hal, ret);
+
+    return ret;
+}
+
+static MPP_RET hal_h264e_vepu510_ret_task(void * hal, HalEncTask * task)
+{
+    HalH264eVepu510Ctx *ctx = (HalH264eVepu510Ctx *)hal;
+    HalVepu510RegSet *regs = &ctx->regs_sets[task->flags.reg_idx];
+    EncRcTaskInfo *rc_info = &task->rc_task->info;
+    Vepu510H264Fbk *fb = &ctx->feedback;
+    Vepu510Status *reg_st = &regs->reg_st;
+    RK_U32 mb_w = ctx->sps->pic_width_in_mbs;
+    RK_U32 mb_h = ctx->sps->pic_height_in_mbs;
+    RK_U32 mbs = mb_w * mb_h;
+
+    hal_h264e_dbg_func("enter %p\n", hal);
+
+    fb->st_mb_num = mbs;
+    fb->st_smear_cnt[0] = reg_st->st_smear_cnt.rdo_smear_cnt0 * 4;
+    fb->st_smear_cnt[1] = reg_st->st_smear_cnt.rdo_smear_cnt1 * 4;
+    fb->st_smear_cnt[2] = reg_st->st_smear_cnt.rdo_smear_cnt2 * 4;
+    fb->st_smear_cnt[3] = reg_st->st_smear_cnt.rdo_smear_cnt3 * 4;
+    fb->st_smear_cnt[4] = fb->st_smear_cnt[0] + fb->st_smear_cnt[1] +
+                          fb->st_smear_cnt[2] + fb->st_smear_cnt[3];
+    fb->frame_type = ctx->slice->slice_type;
+
+    // update total hardware length
+    task->length += task->hw_length;
+
+    // setup bit length for rate control
+    rc_info->bit_real = task->hw_length * 8;
+    rc_info->quality_real = regs->reg_st.qp_sum / mbs;
+    rc_info->iblk4_prop = (regs->reg_st.st_pnum_i4.pnum_i4 +
+                           regs->reg_st.st_pnum_i8.pnum_i8 +
+                           regs->reg_st.st_pnum_i16.pnum_i16) * 256 / mbs;
+
+    rc_info->sse = ((RK_S64)regs->reg_st.sse_h32 << 16) +
+                   (regs->reg_st.st_sse_bsl.sse_l16 & 0xffff);
+    rc_info->lvl16_inter_num = regs->reg_st.st_pnum_p16.pnum_p16;
+    rc_info->lvl8_inter_num  = regs->reg_st.st_pnum_p8.pnum_p8;
+    rc_info->lvl16_intra_num = regs->reg_st.st_pnum_i16.pnum_i16;
+    rc_info->lvl8_intra_num  = regs->reg_st.st_pnum_i8.pnum_i8;
+    rc_info->lvl4_intra_num  = regs->reg_st.st_pnum_i4.pnum_i4;
+
+    ctx->hal_rc_cfg.bit_real = rc_info->bit_real;
+    ctx->hal_rc_cfg.quality_real = rc_info->quality_real;
+    ctx->hal_rc_cfg.iblk4_prop = rc_info->iblk4_prop;
+
+    task->hal_ret.data   = &ctx->hal_rc_cfg;
+    task->hal_ret.number = 1;
+
+    mpp_dev_multi_offset_reset(ctx->offsets);
+
+    if (ctx->dpb) {
+        h264e_dpb_hal_end(ctx->dpb, task->flags.curr_idx);
+        h264e_dpb_hal_end(ctx->dpb, task->flags.refr_idx);
+    }
+
+    vepu510_h264e_tune_stat_update(ctx->tune, task);
+
+    hal_h264e_dbg_func("leave %p\n", hal);
+
+    return MPP_OK;
+}
+
+const MppEncHalApi hal_h264e_vepu510 = {
+    .name       = "hal_h264e_vepu510",
+    .coding     = MPP_VIDEO_CodingAVC,
+    .ctx_size   = sizeof(HalH264eVepu510Ctx),
+    .flag       = 0,
+    .init       = hal_h264e_vepu510_init,
+    .deinit     = hal_h264e_vepu510_deinit,
+    .prepare    = hal_h264e_vepu510_prepare,
+    .get_task   = hal_h264e_vepu510_get_task,
+    .gen_regs   = hal_h264e_vepu510_gen_regs,
+    .start      = hal_h264e_vepu510_start,
+    .wait       = hal_h264e_vepu510_wait,
+    .part_start = NULL,
+    .part_wait  = NULL,
+    .ret_task   = hal_h264e_vepu510_ret_task,
+};
diff --git a/mpp/hal/rkenc/h264e/hal_h264e_vepu510.h b/mpp/hal/rkenc/h264e/hal_h264e_vepu510.h
new file mode 100644
index 000000000..fe7a9382e
--- /dev/null
+++ b/mpp/hal/rkenc/h264e/hal_h264e_vepu510.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef __HAL_H264E_VEPU510_H__
+#define __HAL_H264E_VEPU510_H__
+
+#include "mpp_enc_hal.h"
+
+extern const MppEncHalApi hal_h264e_vepu510;
+
+#endif /* __HAL_H264E_VEPU510_H__ */
diff --git a/mpp/hal/rkenc/h264e/hal_h264e_vepu510_reg.h b/mpp/hal/rkenc/h264e/hal_h264e_vepu510_reg.h
new file mode 100644
index 000000000..e40e294fb
--- /dev/null
+++ b/mpp/hal/rkenc/h264e/hal_h264e_vepu510_reg.h
@@ -0,0 +1,641 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef __HAL_H264E_VEPU510_REG_H__
+#define __HAL_H264E_VEPU510_REG_H__
+
+#include "rk_type.h"
+#include "vepu510_common.h"
+
+/* class: buffer/video syntax */
+/* 0x00000270 reg156 - 0x000003f4 reg253*/
+typedef struct H264eVepu510Frame_t {
+
+    Vepu510FrmCommon    common;
+
+    /* 0x000003a0 reg232 */
+    struct {
+        RK_U32 rect_size         : 1;
+        RK_U32 reserved          : 2;
+        RK_U32 vlc_lmt           : 1;
+        RK_U32 chrm_spcl         : 1;
+        RK_U32 reserved1         : 8;
+        RK_U32 ccwa_e            : 1;
+        RK_U32 reserved2         : 1;
+        RK_U32 atr_e             : 1;
+        RK_U32 reserved3         : 4;
+        RK_U32 scl_lst_sel       : 2;
+        RK_U32 reserved4         : 6;
+        RK_U32 atf_e             : 1;
+        RK_U32 atr_mult_sel_e    : 1;
+        RK_U32 reserved5         : 2;
+    } rdo_cfg;
+
+    /* 0x000003a4 reg233 */
+    struct {
+        RK_U32 rdo_mark_mode    : 9;
+        RK_U32 reserved         : 23;
+    } iprd_csts;
+
+    /* 0x3a8 - 0x3ac */
+    RK_U32 reserved234_235[2];
+
+    /* 0x000003b0 reg236 */
+    struct {
+        RK_U32 nal_ref_idc      : 2;
+        RK_U32 nal_unit_type    : 5;
+        RK_U32 reserved         : 25;
+    } synt_nal;
+
+    /* 0x000003b4 reg237 */
+    struct {
+        RK_U32 max_fnum    : 4;
+        RK_U32 drct_8x8    : 1;
+        RK_U32 mpoc_lm4    : 4;
+        RK_U32 poc_type    : 2;
+        RK_U32 reserved    : 21;
+    } synt_sps;
+
+    /* 0x000003b8 reg238 */
+    struct {
+        RK_U32 etpy_mode       : 1;
+        RK_U32 trns_8x8        : 1;
+        RK_U32 csip_flag       : 1;
+        RK_U32 num_ref0_idx    : 2;
+        RK_U32 num_ref1_idx    : 2;
+        RK_U32 pic_init_qp     : 6;
+        RK_U32 cb_ofst         : 5;
+        RK_U32 cr_ofst         : 5;
+        RK_U32 reserved        : 1;
+        RK_U32 dbf_cp_flg      : 1;
+        RK_U32 reserved1       : 7;
+    } synt_pps;
+
+    /* 0x000003bc reg239 */
+    struct {
+        RK_U32 sli_type        : 2;
+        RK_U32 pps_id          : 8;
+        RK_U32 drct_smvp       : 1;
+        RK_U32 num_ref_ovrd    : 1;
+        RK_U32 cbc_init_idc    : 2;
+        RK_U32 reserved        : 2;
+        RK_U32 frm_num         : 16;
+    } synt_sli0;
+
+    /* 0x000003c0 reg240 */
+    struct {
+        RK_U32 idr_pid    : 16;
+        RK_U32 poc_lsb    : 16;
+    } synt_sli1;
+
+    /* 0x000003c4 reg241 */
+    struct {
+        RK_U32 rodr_pic_idx      : 2;
+        RK_U32 ref_list0_rodr    : 1;
+        RK_U32 sli_beta_ofst     : 4;
+        RK_U32 sli_alph_ofst     : 4;
+        RK_U32 dis_dblk_idc      : 2;
+        RK_U32 reserved          : 3;
+        RK_U32 rodr_pic_num      : 16;
+    } synt_sli2;
+
+    /* 0x000003c8 reg242 */
+    struct {
+        RK_U32 nopp_flg      : 1;
+        RK_U32 ltrf_flg      : 1;
+        RK_U32 arpm_flg      : 1;
+        RK_U32 mmco4_pre     : 1;
+        RK_U32 mmco_type0    : 3;
+        RK_U32 mmco_parm0    : 16;
+        RK_U32 mmco_type1    : 3;
+        RK_U32 mmco_type2    : 3;
+        RK_U32 reserved      : 3;
+    } synt_refm0;
+
+    /* 0x000003cc reg243 */
+    struct {
+        RK_U32 mmco_parm1    : 16;
+        RK_U32 mmco_parm2    : 16;
+    } synt_refm1;
+
+    /* 0x000003d0 reg244 */
+    struct {
+        RK_U32 long_term_frame_idx0    : 4;
+        RK_U32 long_term_frame_idx1    : 4;
+        RK_U32 long_term_frame_idx2    : 4;
+        RK_U32 reserved                : 20;
+    } synt_refm2;
+
+    /* 0x000003d4 reg245 */
+    struct {
+        RK_U32 dlt_poc_s0_m12    : 16;
+        RK_U32 dlt_poc_s0_m13    : 16;
+    } synt_refm3_hevc;
+
+    /* 0x000003d8 reg246 */
+    struct {
+        RK_U32 poc_lsb_lt1    : 16;
+        RK_U32 poc_lsb_lt2    : 16;
+    } synt_long_refm0_hevc;
+
+    /* 0x000003dc reg247 */
+    struct {
+        RK_U32 dlt_poc_msb_cycl1    : 16;
+        RK_U32 dlt_poc_msb_cycl2    : 16;
+    } synt_long_refm1_hevc;
+
+    /* 0x000003e0 reg248 */
+    struct {
+        RK_U32 sao_lambda_multi    : 3;
+        RK_U32 reserved            : 29;
+    } sao_cfg_hevc;
+
+    /* 0x3e4 - 0x3ec */
+    RK_U32 reserved249_251[3];
+
+    /* 0x000003f0 reg252 */
+    struct {
+        RK_U32 mv_v_lmt_thd    : 14;
+        RK_U32 reserved        : 1;
+        RK_U32 mv_v_lmt_en     : 1;
+        RK_U32 reserved1       : 16;
+    } sli_cfg;
+
+    /* 0x000003f4 reg253 */
+    struct {
+        RK_U32 tile_x       : 9;
+        RK_U32 reserved     : 7;
+        RK_U32 tile_y       : 9;
+        RK_U32 reserved1    : 7;
+    } tile_pos_hevc;
+} H264eVepu510Frame;
+
+/* class: param */
+/* 0x00001700 reg1472 - 0x000019cc reg1651 */
+typedef struct H264eVepu510Param_t {
+    /* 0x00001700 reg1472 */
+    struct {
+        RK_U32 iprd_tthdy4_0    : 12;
+        RK_U32 reserved         : 4;
+        RK_U32 iprd_tthdy4_1    : 12;
+        RK_U32 reserved1        : 4;
+    } iprd_tthdy4_0;
+
+    /* 0x00001704 reg1473 */
+    struct {
+        RK_U32 iprd_tthdy4_2    : 12;
+        RK_U32 reserved         : 4;
+        RK_U32 iprd_tthdy4_3    : 12;
+        RK_U32 reserved1        : 4;
+    } iprd_tthdy4_1;
+
+    /* 0x00001708 reg1474 */
+    struct {
+        RK_U32 iprd_tthdc8_0    : 12;
+        RK_U32 reserved         : 4;
+        RK_U32 iprd_tthdc8_1    : 12;
+        RK_U32 reserved1        : 4;
+    } iprd_tthdc8_0;
+
+    /* 0x0000170c reg1475 */
+    struct {
+        RK_U32 iprd_tthdc8_2    : 12;
+        RK_U32 reserved         : 4;
+        RK_U32 iprd_tthdc8_3    : 12;
+        RK_U32 reserved1        : 4;
+    } iprd_tthdc8_1;
+
+    /* 0x00001710 reg1476 */
+    struct {
+        RK_U32 iprd_tthdy8_0    : 12;
+        RK_U32 reserved         : 4;
+        RK_U32 iprd_tthdy8_1    : 12;
+        RK_U32 reserved1        : 4;
+    } iprd_tthdy8_0;
+
+    /* 0x00001714 reg1477 */
+    struct {
+        RK_U32 iprd_tthdy8_2    : 12;
+        RK_U32 reserved         : 4;
+        RK_U32 iprd_tthdy8_3    : 12;
+        RK_U32 reserved1        : 4;
+    } iprd_tthdy8_1;
+
+    /* 0x00001718 reg1478 */
+    struct {
+        RK_U32 iprd_tthd_ul    : 12;
+        RK_U32 reserved        : 20;
+    } iprd_tthd_ul;
+
+    /* 0x0000171c reg1479 */
+    struct {
+        RK_U32 iprd_wgty8_0    : 8;
+        RK_U32 iprd_wgty8_1    : 8;
+        RK_U32 iprd_wgty8_2    : 8;
+        RK_U32 iprd_wgty8_3    : 8;
+    } iprd_wgty8;
+
+    /* 0x00001720 reg1480 */
+    struct {
+        RK_U32 iprd_wgty4_0    : 8;
+        RK_U32 iprd_wgty4_1    : 8;
+        RK_U32 iprd_wgty4_2    : 8;
+        RK_U32 iprd_wgty4_3    : 8;
+    } iprd_wgty4;
+
+    /* 0x00001724 reg1481 */
+    struct {
+        RK_U32 iprd_wgty16_0    : 8;
+        RK_U32 iprd_wgty16_1    : 8;
+        RK_U32 iprd_wgty16_2    : 8;
+        RK_U32 iprd_wgty16_3    : 8;
+    } iprd_wgty16;
+
+    /* 0x00001728 reg1482 */
+    struct {
+        RK_U32 iprd_wgtc8_0    : 8;
+        RK_U32 iprd_wgtc8_1    : 8;
+        RK_U32 iprd_wgtc8_2    : 8;
+        RK_U32 iprd_wgtc8_3    : 8;
+    } iprd_wgtc8;
+
+    /* 0x172c */
+    RK_U32 reserved_1483;
+
+    /* 0x00001730 reg1484 */
+    struct {
+        RK_U32    qnt_f_bias_i  : 10;
+        RK_U32    qnt_f_bias_p  : 10;
+        RK_U32    reserve       : 12;
+    } qnt_bias_comb;
+
+    /* 0x1734 - 0x173c */
+    RK_U32 reserved1485_1487[3];
+
+    /* 0x00001740 reg1488 */
+    struct {
+        RK_U32    thd0      : 8;
+        RK_U32    reserve0  : 8;
+        RK_U32    thd1      : 8;
+        RK_U32    reserve1  : 8;
+    } atr_thd0;
+
+    /* 0x00001744 reg1489 */
+    struct {
+        RK_U32    thd2      : 8;
+        RK_U32    reserve0  : 8;
+        RK_U32    thdqp     : 6;
+        RK_U32    reserve1  : 10;
+    } atr_thd1;
+
+    /* 0x1748 - 0x174c */
+    RK_U32 reserved1490_1491[2];
+
+    /* 0x00001750 reg1492 */
+    struct {
+        RK_U32 atr_lv16_wgt0    : 8;
+        RK_U32 atr_lv16_wgt1    : 8;
+        RK_U32 atr_lv16_wgt2    : 8;
+        RK_U32 reserved         : 8;
+    } atr_wgt16;
+
+    /* 0x00001754  reg1493*/
+    struct {
+        RK_U32 atr_lv8_wgt0    : 8;
+        RK_U32 atr_lv8_wgt1    : 8;
+        RK_U32 atr_lv8_wgt2    : 8;
+        RK_U32 reserved        : 8;
+    } atr_wgt8;
+
+    /* 0x00001758 reg1494 */
+    struct {
+        RK_U32 atr_lv4_wgt0    : 8;
+        RK_U32 atr_lv4_wgt1    : 8;
+        RK_U32 atr_lv4_wgt2    : 8;
+        RK_U32 reserved        : 8;
+    } atr_wgt4;
+
+    /* 0x175c */
+    RK_U32 reserved_1495;
+
+    /* 0x00001760 reg1496 */
+    struct {
+        RK_U32 cime_pmv_num      : 1;
+        RK_U32 cime_fuse         : 1;
+        RK_U32 itp_mode          : 1;
+        RK_U32 reserved          : 1;
+        RK_U32 move_lambda       : 4;
+        RK_U32 rime_lvl_mrg      : 2;
+        RK_U32 rime_prelvl_en    : 2;
+        RK_U32 rime_prersu_en    : 3;
+        RK_U32 reserved1         : 17;
+    } me_sqi_comb;
+
+    /* 0x00001764 reg1497 */
+    struct {
+        RK_U32 cime_mvd_th0    : 9;
+        RK_U32 reserved        : 1;
+        RK_U32 cime_mvd_th1    : 9;
+        RK_U32 reserved1       : 1;
+        RK_U32 cime_mvd_th2    : 9;
+        RK_U32 reserved2       : 3;
+    }  cime_mvd_th_comb;
+
+    /* 0x00001768 reg1498 */
+    struct {
+        RK_U32 cime_madp_th    : 12;
+        RK_U32 reserved        : 20;
+    } cime_madp_th_comb;
+
+    /* 0x0000176c reg1499 */
+    struct {
+        RK_U32 cime_multi0    : 8;
+        RK_U32 cime_multi1    : 8;
+        RK_U32 cime_multi2    : 8;
+        RK_U32 cime_multi3    : 8;
+    } cime_multi_comb;
+
+    /* 0x00001770 reg1500 */
+    struct {
+        RK_U32 rime_mvd_th0    : 3;
+        RK_U32 reserved        : 1;
+        RK_U32 rime_mvd_th1    : 3;
+        RK_U32 reserved1       : 9;
+        RK_U32 fme_madp_th     : 12;
+        RK_U32 reserved2       : 4;
+    } rime_mvd_th_comb;
+
+    /* 0x00001774 reg1501 */
+    struct {
+        RK_U32 rime_madp_th0    : 12;
+        RK_U32 reserved         : 4;
+        RK_U32 rime_madp_th1    : 12;
+        RK_U32 reserved1        : 4;
+    } rime_madp_th_comb;
+
+    /* 0x00001778 reg1502 */
+    struct {
+        RK_U32 rime_multi0    : 10;
+        RK_U32 rime_multi1    : 10;
+        RK_U32 rime_multi2    : 10;
+        RK_U32 reserved       : 2;
+    } rime_multi_comb;
+
+    /* 0x0000177c reg1503 */
+    struct {
+        RK_U32 cmv_th0     : 8;
+        RK_U32 cmv_th1     : 8;
+        RK_U32 cmv_th2     : 8;
+        RK_U32 reserved    : 8;
+    } cmv_st_th_comb;
+
+    /* 0x1780 - 0x17fc */
+    RK_U32 reserved1504_1535[32];
+
+    /* 0x00001800 reg1536 - 0x000018cc reg1587*/
+    RK_U32 pprd_lamb_satd_0_51[52];
+
+    /* 0x000018d0 reg1588 */
+    struct {
+        RK_U32 lambda_satd_offset    : 5;
+        RK_U32 reserved              : 27;
+    } iprd_lamb_satd_ofst;
+
+    /* 0x18d4 - 0x18fc */
+    RK_U32 reserved1589_1599[11];
+
+    /* 0x00001900 reg1600 - 0x000019cc reg1651*/
+    RK_U32 rdo_wgta_qp_grpa_0_51[52];
+} H264eVepu510Param;
+
+/* class: rdo/q_i */
+/* 0x00002000 reg2048 - 0x000020fc reg2111 */
+typedef struct H264eVepu510SqiCfg_t {
+    /* 0x00002000 reg2048 - 0x00002010 reg2052*/
+    RK_U32 reserved_2048_2052[5];
+
+    /* 0x00002014 reg2053 */
+    struct {
+        RK_U32 rdo_smear_lvl16_multi    : 8;
+        RK_U32 rdo_smear_dlt_qp         : 4;
+        RK_U32 reserved                 : 1;
+        RK_U32 stated_mode              : 2;
+        RK_U32 rdo_smear_en             : 1;
+        RK_U32 reserved1                : 16;
+    } smear_opt_cfg;
+
+    /* 0x00002018 reg2054 */
+    struct {
+        RK_U32 madp_cur_thd0    : 12;
+        RK_U32 reserved         : 4;
+        RK_U32 madp_cur_thd1    : 12;
+        RK_U32 reserved1        : 4;
+    } smear_madp_thd0;
+
+    /* 0x0000201c reg2055 */
+    struct {
+        RK_U32 madp_cur_thd2    : 12;
+        RK_U32 reserved         : 4;
+        RK_U32 madp_cur_thd3    : 12;
+        RK_U32 reserved1        : 4;
+    } smear_madp_thd1;
+
+    /* 0x00002020 reg2056 */
+    struct {
+        RK_U32 madp_around_thd0    : 12;
+        RK_U32 reserved            : 4;
+        RK_U32 madp_around_thd1    : 12;
+        RK_U32 reserved1           : 4;
+    } smear_madp_thd2;
+
+    /* 0x00002024 reg2057 */
+    struct {
+        RK_U32 madp_around_thd2    : 12;
+        RK_U32 reserved            : 4;
+        RK_U32 madp_around_thd3    : 12;
+        RK_U32 reserved1           : 4;
+    } smear_madp_thd3;
+
+    /* 0x00002028 reg2058 */
+    struct {
+        RK_U32 madp_around_thd4    : 12;
+        RK_U32 reserved            : 4;
+        RK_U32 madp_around_thd5    : 12;
+        RK_U32 reserved1           : 4;
+    } smear_madp_thd4;
+
+    /* 0x0000202c reg2059 */
+    struct {
+        RK_U32 madp_ref_thd0    : 12;
+        RK_U32 reserved         : 4;
+        RK_U32 madp_ref_thd1    : 12;
+        RK_U32 reserved1        : 4;
+    } smear_madp_thd5;
+
+    /* 0x00002030 reg2060 */
+    struct {
+        RK_U32 cnt_cur_thd0    : 4;
+        RK_U32 reserved        : 4;
+        RK_U32 cnt_cur_thd1    : 4;
+        RK_U32 reserved1       : 4;
+        RK_U32 cnt_cur_thd2    : 4;
+        RK_U32 reserved2       : 4;
+        RK_U32 cnt_cur_thd3    : 4;
+        RK_U32 reserved3       : 4;
+    } smear_cnt_thd0;
+
+    /* 0x00002034 reg2061 */
+    struct {
+        RK_U32 cnt_around_thd0    : 4;
+        RK_U32 reserved           : 4;
+        RK_U32 cnt_around_thd1    : 4;
+        RK_U32 reserved1          : 4;
+        RK_U32 cnt_around_thd2    : 4;
+        RK_U32 reserved2          : 4;
+        RK_U32 cnt_around_thd3    : 4;
+        RK_U32 reserved3          : 4;
+    } smear_cnt_thd1;
+
+    /* 0x00002038 reg2062 */
+    struct {
+        RK_U32 cnt_around_thd4    : 4;
+        RK_U32 reserved           : 4;
+        RK_U32 cnt_around_thd5    : 4;
+        RK_U32 reserved1          : 4;
+        RK_U32 cnt_around_thd6    : 4;
+        RK_U32 reserved2          : 4;
+        RK_U32 cnt_around_thd7    : 4;
+        RK_U32 reserved3          : 4;
+    } smear_cnt_thd2;
+
+    /* 0x0000203c reg2063 */
+    struct {
+        RK_U32 cnt_ref_thd0    : 4;
+        RK_U32 reserved        : 4;
+        RK_U32 cnt_ref_thd1    : 4;
+        RK_U32 reserved1       : 20;
+    } smear_cnt_thd3;
+
+    /* 0x00002040 reg2064 */
+    struct {
+        RK_U32 resi_small_cur_th0    : 6;
+        RK_U32 reserved              : 2;
+        RK_U32 resi_big_cur_th0      : 6;
+        RK_U32 reserved1             : 2;
+        RK_U32 resi_small_cur_th1    : 6;
+        RK_U32 reserved2             : 2;
+        RK_U32 resi_big_cur_th1      : 6;
+        RK_U32 reserved3             : 2;
+    } smear_resi_thd0;
+
+    /* 0x00002044 reg2065 */
+    struct {
+        RK_U32 resi_small_around_th0    : 6;
+        RK_U32 reserved                 : 2;
+        RK_U32 resi_big_around_th0      : 6;
+        RK_U32 reserved1                : 2;
+        RK_U32 resi_small_around_th1    : 6;
+        RK_U32 reserved2                : 2;
+        RK_U32 resi_big_around_th1      : 6;
+        RK_U32 reserved3                : 2;
+    } smear_resi_thd1;
+
+    /* 0x00002048 reg2066 */
+    struct {
+        RK_U32 resi_small_around_th2    : 6;
+        RK_U32 reserved                 : 2;
+        RK_U32 resi_big_around_th2      : 6;
+        RK_U32 reserved1                : 2;
+        RK_U32 resi_small_around_th3    : 6;
+        RK_U32 reserved2                : 2;
+        RK_U32 resi_big_around_th3      : 6;
+        RK_U32 reserved3                : 2;
+    } smear_resi_thd2;
+
+    /* 0x0000204c reg2067 */
+    struct {
+        RK_U32 resi_small_ref_th0    : 6;
+        RK_U32 reserved              : 2;
+        RK_U32 resi_big_ref_th0      : 6;
+        RK_U32 reserved1             : 18;
+    } smear_resi_thd3;
+
+    /* 0x00002050 reg2068 */
+    struct {
+        RK_U32 resi_th0    : 8;
+        RK_U32 reserved    : 8;
+        RK_U32 resi_th1    : 8;
+        RK_U32 reserved1   : 8;
+    } smear_resi_thd4;
+
+    /* 0x00002054 reg2069 */
+    struct {
+        RK_U32 madp_cnt_th0    : 4;
+        RK_U32 madp_cnt_th1    : 4;
+        RK_U32 madp_cnt_th2    : 4;
+        RK_U32 madp_cnt_th3    : 4;
+        RK_U32 reserved        : 16;
+    } smear_st_thd;
+
+    /* 0x2058 - 0x206c */
+    RK_U32 reserved2070_2075[6];
+
+    /* 0x00002070 reg2076 - 0x0000207c reg2079*/
+    rdo_skip_par rdo_b16_skip;
+
+    /* 0x00002080 reg2080 - 0x00002088 reg2082 */
+    RK_U32 reserved2080_2082[3];
+
+    /* 0x0000208c reg2083 - 0x00002094 reg2085 */
+    rdo_noskip_par rdo_b16_inter;
+
+    /* 0x00002098 reg2086 - 0x000020a4 reg2088 */
+    RK_U32 reserved2086_2088[3];
+
+    /* 0x000020a8 reg2089 - 0x000020ac reg2091 */
+    rdo_noskip_par rdo_b16_intra;
+
+    /* 0x000020b0 reg2092 */
+    RK_U32 reserved2092;
+
+    /* 0x000020b4 reg2093 */
+    struct {
+        RK_U32 thd0         : 4;
+        RK_U32 reserved     : 4;
+        RK_U32 thd1         : 4;
+        RK_U32 reserved1    : 4;
+        RK_U32 thd2         : 4;
+        RK_U32 reserved2    : 4;
+        RK_U32 thd3         : 4;
+        RK_U32 reserved3    : 4;
+    } rdo_b16_intra_atf_cnt_thd;
+
+    /* 0x000020b8 reg2094 */
+    struct {
+        RK_U32 big_th0      : 6;
+        RK_U32 reserved     : 2;
+        RK_U32 big_th1      : 6;
+        RK_U32 reserved1    : 2;
+        RK_U32 small_th0    : 6;
+        RK_U32 reserved2    : 2;
+        RK_U32 small_th1    : 6;
+        RK_U32 reserved3    : 2;
+    } rdo_atf_resi_thd;
+} H264eVepu510Sqi;
+
+/* class: mmu */
+/* 0x0000f000 reg15360 - 0x0000f024 reg15369 */
+typedef struct HalVepu510Reg_t {
+    Vepu510ControlCfg       reg_ctl;
+    H264eVepu510Frame       reg_frm;
+    Vepu510RcRoi            reg_rc_roi;
+    H264eVepu510Param       reg_param;
+    H264eVepu510Sqi         reg_sqi;
+    Vepu510SclCfg           reg_scl;
+    Vepu510Status           reg_st;
+    Vepu510Dbg              reg_dbg;
+} HalVepu510RegSet;
+
+#endif
\ No newline at end of file
diff --git a/mpp/hal/rkenc/h264e/hal_h264e_vepu510_tune.c b/mpp/hal/rkenc/h264e/hal_h264e_vepu510_tune.c
new file mode 100644
index 000000000..1a55b5efd
--- /dev/null
+++ b/mpp/hal/rkenc/h264e/hal_h264e_vepu510_tune.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright 2024 Rockchip Electronics Co. LTD
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "hal_enc_task.h"
+#include "hal_h264e_vepu510_reg.h"
+
+#define HAL_H264E_DBG_CONTENT           (0x00000200)
+#define hal_h264e_dbg_content(fmt, ...) hal_h264e_dbg_f(HAL_H264E_DBG_CONTENT, fmt, ## __VA_ARGS__)
+
+typedef struct HalH264eVepu510Tune_t {
+    HalH264eVepu510Ctx  *ctx;
+
+    RK_S32  pre_madp[2];
+    RK_S32  pre_madi[2];
+} HalH264eVepu510Tune;
+
+static HalH264eVepu510Tune *vepu510_h264e_tune_init(HalH264eVepu510Ctx *ctx)
+{
+    HalH264eVepu510Tune *tune = mpp_malloc(HalH264eVepu510Tune, 1);
+
+    if (NULL == tune)
+        return tune;
+
+    tune->ctx = ctx;
+    tune->pre_madi[0] = tune->pre_madi[1] = -1;
+    tune->pre_madp[0] = tune->pre_madp[1] = -1;
+
+    return tune;
+}
+
+static void vepu510_h264e_tune_deinit(void *tune)
+{
+    MPP_FREE(tune);
+}
+
+static void vepu510_h264e_tune_reg_patch(void *p)
+{
+    HalH264eVepu510Tune *tune = (HalH264eVepu510Tune *)p;
+
+    if (NULL == tune)
+        return;
+}
+
+static void vepu510_h264e_tune_stat_update(void *p, HalEncTask *task)
+{
+    HalH264eVepu510Tune *tune = (HalH264eVepu510Tune *)p;
+
+    if (NULL == tune)
+        return;
+
+    EncRcTaskInfo *rc_info = &task->rc_task->info;
+    HalH264eVepu510Ctx *ctx = tune->ctx;
+    HalVepu510RegSet *regs = &ctx->regs_sets[task->flags.reg_idx];
+    Vepu510Status *st = &regs->reg_st;
+    RK_U32 mb_w = ctx->sps->pic_width_in_mbs;
+    RK_U32 mb_h = ctx->sps->pic_height_in_mbs;
+    RK_U32 b16_num = mb_w * mb_h;
+    RK_U32 madi_cnt = 0;
+
+    RK_U32 madi_th_cnt0 = st->st_madi_lt_num0.madi_th_lt_cnt0 +
+                          st->st_madi_rt_num0.madi_th_rt_cnt0 +
+                          st->st_madi_lb_num0.madi_th_lb_cnt0 +
+                          st->st_madi_rb_num0.madi_th_rb_cnt0;
+    RK_U32 madi_th_cnt1 = st->st_madi_lt_num0.madi_th_lt_cnt1 +
+                          st->st_madi_rt_num0.madi_th_rt_cnt1 +
+                          st->st_madi_lb_num0.madi_th_lb_cnt1 +
+                          st->st_madi_rb_num0.madi_th_rb_cnt1;
+    RK_U32 madi_th_cnt2 = st->st_madi_lt_num1.madi_th_lt_cnt2 +
+                          st->st_madi_rt_num1.madi_th_rt_cnt2 +
+                          st->st_madi_lb_num1.madi_th_lb_cnt2 +
+                          st->st_madi_rb_num1.madi_th_rb_cnt2;
+    RK_U32 madi_th_cnt3 = st->st_madi_lt_num1.madi_th_lt_cnt3 +
+                          st->st_madi_rt_num1.madi_th_rt_cnt3 +
+                          st->st_madi_lb_num1.madi_th_lb_cnt3 +
+                          st->st_madi_rb_num1.madi_th_rb_cnt3;
+    RK_U32 madp_th_cnt0 = st->st_madp_lt_num0.madp_th_lt_cnt0 +
+                          st->st_madp_rt_num0.madp_th_rt_cnt0 +
+                          st->st_madp_lb_num0.madp_th_lb_cnt0 +
+                          st->st_madp_rb_num0.madp_th_rb_cnt0;
+    RK_U32 madp_th_cnt1 = st->st_madp_lt_num0.madp_th_lt_cnt1 +
+                          st->st_madp_rt_num0.madp_th_rt_cnt1 +
+                          st->st_madp_lb_num0.madp_th_lb_cnt1 +
+                          st->st_madp_rb_num0.madp_th_rb_cnt1;
+    RK_U32 madp_th_cnt2 = st->st_madp_lt_num1.madp_th_lt_cnt2 +
+                          st->st_madp_rt_num1.madp_th_rt_cnt2 +
+                          st->st_madp_lb_num1.madp_th_lb_cnt2 +
+                          st->st_madp_rb_num1.madp_th_rb_cnt2;
+    RK_U32 madp_th_cnt3 = st->st_madp_lt_num1.madp_th_lt_cnt3 +
+                          st->st_madp_rt_num1.madp_th_rt_cnt3 +
+                          st->st_madp_lb_num1.madp_th_lb_cnt3 +
+                          st->st_madp_rb_num1.madp_th_rb_cnt3;
+
+    madi_cnt = (6 * madi_th_cnt3 + 5 * madi_th_cnt2 + 4 * madi_th_cnt1) >> 2;
+    rc_info->complex_level = (madi_cnt * 100 > 30 * b16_num) ? 2 :
+                             (madi_cnt * 100 > 13 * b16_num) ? 1 : 0;
+
+    {
+        RK_U32 md_cnt = 0, motion_level = 0;
+
+        if (ctx->smart_en)
+            md_cnt = (12 * madp_th_cnt3 + 11 * madp_th_cnt2 + 8 * madp_th_cnt1) >> 2;
+        else
+            md_cnt = (24 * madp_th_cnt3 + 22 * madp_th_cnt2 + 17 * madp_th_cnt1) >> 2;
+
+        if (md_cnt * 100 > 15 * b16_num)
+            motion_level = 200;
+        else if (md_cnt * 100 > 5 * b16_num)
+            motion_level = 100;
+        else if (md_cnt * 100 > (b16_num >> 2))
+            motion_level = 1;
+        else
+            motion_level = 0;
+        rc_info->motion_level = motion_level;
+    }
+    hal_h264e_dbg_rc("complex_level %d motion_level %d\n",
+                     rc_info->complex_level, rc_info->motion_level);
+
+    (void)madi_th_cnt0;
+    (void)madp_th_cnt0;
+}
diff --git a/mpp/hal/rkenc/h264e/hal_h264e_vepu540c.c b/mpp/hal/rkenc/h264e/hal_h264e_vepu540c.c
index fb19d83b2..55a2cd46a 100644
--- a/mpp/hal/rkenc/h264e/hal_h264e_vepu540c.c
+++ b/mpp/hal/rkenc/h264e/hal_h264e_vepu540c.c
@@ -23,6 +23,7 @@
 #include "mpp_common.h"
 #include "mpp_frame_impl.h"
 #include "mpp_rc.h"
+#include "mpp_packet_impl.h"
 
 #include "h264e_sps.h"
 #include "h264e_pps.h"
@@ -86,9 +87,6 @@ typedef struct HalH264eVepu540cCtx_t {
     MppBuffer               ext_line_buf;
 } HalH264eVepu540cCtx;
 
-static RK_U32 dump_l1_reg = 0;
-static RK_U32 dump_l2_reg = 0;
-
 static RK_S32 h264_aq_tthd_default[16] = {
     0,  0,  0,  0,
     3,  3,  5,  5,
@@ -402,7 +400,7 @@ static void setup_vepu540c_normal(HalVepu540cRegSet *regs)
     regs->reg_ctl.int_en.enc_done_en        = 1;
     regs->reg_ctl.int_en.lkt_node_done_en   = 1;
     regs->reg_ctl.int_en.sclr_done_en       = 1;
-    regs->reg_ctl.int_en.vslc_done_en       = 1;
+    regs->reg_ctl.int_en.vslc_done_en       = 0;
     regs->reg_ctl.int_en.vbsf_oflw_en       = 1;
     regs->reg_ctl.int_en.vbuf_lens_en       = 1;
     regs->reg_ctl.int_en.enc_err_en         = 1;
@@ -553,9 +551,6 @@ static void setup_vepu540c_codec(HalVepu540cRegSet *regs, H264eSps *sps,
     regs->reg_base.enc_pic.enc_stnd       = 0;
     regs->reg_base.enc_pic.cur_frm_ref    = slice->nal_reference_idc > 0;
     regs->reg_base.enc_pic.bs_scp         = 1;
-    //regs->reg013.lamb_mod_sel   = (slice->slice_type == H264_I_SLICE) ? 0 : 1;
-    //regs->reg013.atr_thd_sel    = 0;
-    // regs->reg_ctl.lkt_node_cfg.node_int       = 0;
 
     regs->reg_base.synt_nal.nal_ref_idc    = slice->nal_reference_idc;
     regs->reg_base.synt_nal.nal_unit_type  = slice->nalu_type;
@@ -572,7 +567,6 @@ static void setup_vepu540c_codec(HalVepu540cRegSet *regs, H264eSps *sps,
     regs->reg_base.synt_pps.pic_init_qp    = pps->pic_init_qp;
     regs->reg_base.synt_pps.cb_ofst        = pps->chroma_qp_index_offset;
     regs->reg_base.synt_pps.cr_ofst        = pps->second_chroma_qp_index_offset;
-//    regs->reg_base.synt_pps.wght_pred      = pps->weighted_pred;
     regs->reg_base.synt_pps.dbf_cp_flg     = pps->deblocking_filter_control;
 
     regs->reg_base.synt_sli0.sli_type       = (slice->slice_type == H264_I_SLICE) ? (2) : (0);
@@ -890,10 +884,13 @@ static void setup_vepu540c_rdo_cfg(vepu540c_rdo_cfg *reg)
     hal_h264e_dbg_func("leave\n");
 }
 
-static void setup_vepu540c_rc_base(HalVepu540cRegSet *regs, H264eSps *sps,
-                                   H264eSlice *slice, MppEncHwCfg *hw,
-                                   EncRcTask *rc_task)
+static void setup_vepu540c_rc_base(HalVepu540cRegSet *regs, HalH264eVepu540cCtx *ctx, EncRcTask *rc_task)
 {
+    H264eSps *sps = ctx->sps;
+    H264eSlice *slice = ctx->slice;
+    MppEncCfgSet *cfg = ctx->cfg;
+    MppEncRcCfg *rc = &cfg->rc;
+    MppEncHwCfg *hw = &cfg->hw;
     EncRcTaskInfo *rc_info = &rc_task->info;
     RK_S32 mb_w = sps->pic_width_in_mbs;
     RK_S32 mb_h = sps->pic_height_in_mbs;
@@ -909,16 +906,44 @@ static void setup_vepu540c_rc_base(HalVepu540cRegSet *regs, H264eSps *sps,
     hal_h264e_dbg_rc("bittarget %d qp [%d %d %d]\n", rc_info->bit_target,
                      qp_min, qp_target, qp_max);
 
-    if (mb_target_bits_mul_16 >= 0x100000) {
-        mb_target_bits_mul_16 = 0x50000;
+    hal_h264e_dbg_func("enter\n");
+
+    regs->reg_rc_roi.roi_qthd0.qpmin_area0    = qp_min;
+    regs->reg_rc_roi.roi_qthd0.qpmax_area0    = qp_max;
+    regs->reg_rc_roi.roi_qthd0.qpmin_area1    = qp_min;
+    regs->reg_rc_roi.roi_qthd0.qpmax_area1    = qp_max;
+    regs->reg_rc_roi.roi_qthd0.qpmin_area2    = qp_min;
+
+    regs->reg_rc_roi.roi_qthd1.qpmax_area2    = qp_max;
+    regs->reg_rc_roi.roi_qthd1.qpmin_area3    = qp_min;
+    regs->reg_rc_roi.roi_qthd1.qpmax_area3    = qp_max;
+    regs->reg_rc_roi.roi_qthd1.qpmin_area4    = qp_min;
+    regs->reg_rc_roi.roi_qthd1.qpmax_area4    = qp_max;
+
+    regs->reg_rc_roi.roi_qthd2.qpmin_area5    = qp_min;
+    regs->reg_rc_roi.roi_qthd2.qpmax_area5    = qp_max;
+    regs->reg_rc_roi.roi_qthd2.qpmin_area6    = qp_min;
+    regs->reg_rc_roi.roi_qthd2.qpmax_area6    = qp_max;
+    regs->reg_rc_roi.roi_qthd2.qpmin_area7    = qp_min;
+
+    regs->reg_rc_roi.roi_qthd3.qpmax_area7    = qp_max;
+    regs->reg_rc_roi.roi_qthd3.qpmap_mode     = qpmap_mode;
+
+    if (rc->rc_mode == MPP_ENC_RC_MODE_FIXQP) {
+        regs->reg_base.enc_pic.pic_qp    = rc_info->quality_target;
+        regs->reg_base.rc_qp.rc_max_qp   = rc_info->quality_target;
+        regs->reg_base.rc_qp.rc_min_qp   = rc_info->quality_target;
+
+        return;
     }
 
+    if (mb_target_bits_mul_16 >= 0x100000)
+        mb_target_bits_mul_16 = 0x50000;
+
     mb_target_bits = (mb_target_bits_mul_16 * mb_w) >> 4;
     negative_bits_thd = 0 - 5 * mb_target_bits / 16;
     positive_bits_thd = 5 * mb_target_bits / 16;
 
-    hal_h264e_dbg_func("enter\n");
-
     regs->reg_base.enc_pic.pic_qp         = qp_target;
 
     regs->reg_base.rc_cfg.rc_en          = 1;
@@ -953,27 +978,6 @@ static void setup_vepu540c_rc_base(HalVepu540cRegSet *regs, H264eSps *sps,
     regs->reg_rc_roi.rc_dthd_0_8[7] = 0x7FFFFFFF;
     regs->reg_rc_roi.rc_dthd_0_8[8] = 0x7FFFFFFF;
 
-    regs->reg_rc_roi.roi_qthd0.qpmin_area0    = qp_min;
-    regs->reg_rc_roi.roi_qthd0.qpmax_area0    = qp_max;
-    regs->reg_rc_roi.roi_qthd0.qpmin_area1    = qp_min;
-    regs->reg_rc_roi.roi_qthd0.qpmax_area1    = qp_max;
-    regs->reg_rc_roi.roi_qthd0.qpmin_area2    = qp_min;
-
-    regs->reg_rc_roi.roi_qthd1.qpmax_area2    = qp_max;
-    regs->reg_rc_roi.roi_qthd1.qpmin_area3    = qp_min;
-    regs->reg_rc_roi.roi_qthd1.qpmax_area3    = qp_max;
-    regs->reg_rc_roi.roi_qthd1.qpmin_area4    = qp_min;
-    regs->reg_rc_roi.roi_qthd1.qpmax_area4    = qp_max;
-
-    regs->reg_rc_roi.roi_qthd2.qpmin_area5    = qp_min;
-    regs->reg_rc_roi.roi_qthd2.qpmax_area5    = qp_max;
-    regs->reg_rc_roi.roi_qthd2.qpmin_area6    = qp_min;
-    regs->reg_rc_roi.roi_qthd2.qpmax_area6    = qp_max;
-    regs->reg_rc_roi.roi_qthd2.qpmin_area7    = qp_min;
-
-    regs->reg_rc_roi.roi_qthd3.qpmax_area7    = qp_max;
-    regs->reg_rc_roi.roi_qthd3.qpmap_mode     = qpmap_mode;
-
     hal_h264e_dbg_func("leave\n");
 }
 
@@ -1100,11 +1104,11 @@ static void setup_vepu540c_recn_refr(HalH264eVepu540cCtx *ctx, HalVepu540cRegSet
     hal_h264e_dbg_func("leave\n");
 }
 
-static void setup_vepu540c_split(HalVepu540cRegSet *regs, MppEncSliceSplit *cfg)
+static void setup_vepu540c_split(HalVepu540cRegSet *regs, MppEncCfgSet *cfg)
 {
     hal_h264e_dbg_func("enter\n");
 
-    switch (cfg->split_mode) {
+    switch (cfg->split.split_mode) {
     case MPP_ENC_SPLIT_NONE : {
         regs->reg_base.sli_splt.sli_splt = 0;
         regs->reg_base.sli_splt.sli_splt_mode = 0;
@@ -1124,26 +1128,35 @@ static void setup_vepu540c_split(HalVepu540cRegSet *regs, MppEncSliceSplit *cfg)
         regs->reg_base.sli_splt.sli_flsh = 1;
         regs->reg_base.sli_cnum.sli_splt_cnum_m1 = 0;
 
-        regs->reg_base.sli_byte.sli_splt_byte = cfg->split_arg;
+        regs->reg_base.sli_byte.sli_splt_byte = cfg->split.split_arg;
         regs->reg_base.enc_pic.slen_fifo = 0;
+        regs->reg_base.enc_pic.slen_fifo = cfg->split.split_out ? 1 : 0;
+        regs->reg_ctl.int_en.vslc_done_en = regs->reg_base.enc_pic.slen_fifo;
     } break;
     case MPP_ENC_SPLIT_BY_CTU : {
+        RK_U32 mb_w = MPP_ALIGN(cfg->prep.width, 16) / 16;
+        RK_U32 mb_h = MPP_ALIGN(cfg->prep.height, 16) / 16;
+        RK_U32 slice_num = (mb_w * mb_h + cfg->split.split_arg - 1) / cfg->split.split_arg;
+
         regs->reg_base.sli_splt.sli_splt = 1;
         regs->reg_base.sli_splt.sli_splt_mode = 1;
         regs->reg_base.sli_splt.sli_splt_cpst = 0;
         regs->reg_base.sli_splt.sli_max_num_m1 = 500;
         regs->reg_base.sli_splt.sli_flsh = 1;
-        regs->reg_base.sli_cnum.sli_splt_cnum_m1 = cfg->split_arg - 1;
+        regs->reg_base.sli_cnum.sli_splt_cnum_m1 = cfg->split.split_arg - 1;
 
         regs->reg_base.sli_byte.sli_splt_byte = 0;
-        regs->reg_base.enc_pic.slen_fifo = 0;
+        regs->reg_base.enc_pic.slen_fifo = cfg->split.split_out ? 1 : 0;
+        if ((cfg->split.split_out & MPP_ENC_SPLIT_OUT_LOWDELAY) ||
+            (regs->reg_base.enc_pic.slen_fifo && (slice_num > VEPU540C_SLICE_FIFO_LEN)))
+            regs->reg_ctl.int_en.vslc_done_en = 1;
     } break;
     default : {
-        mpp_log_f("invalide slice split mode %d\n", cfg->split_mode);
+        mpp_log_f("invalide slice split mode %d\n", cfg->split.split_mode);
     } break;
     }
 
-    cfg->change = 0;
+    cfg->split.change = 0;
 
     hal_h264e_dbg_func("leave\n");
 }
@@ -1433,18 +1446,6 @@ static void setup_vepu540c_l2(HalVepu540cRegSet *regs, H264eSlice *slice, MppEnc
         }
     }
 
-    mpp_env_get_u32("dump_l2_reg", &dump_l2_reg, 0);
-
-    if (dump_l2_reg) {
-        mpp_log("L2 reg dump start:\n");
-        RK_U32 *p = (RK_U32 *)regs;
-
-        for (i = 0; i < (sizeof(*regs) / sizeof(RK_U32)); i++)
-            mpp_log("%04x %08x\n", 4 + i * 4, p[i]);
-
-        mpp_log("L2 reg done\n");
-    }
-
     hal_h264e_dbg_func("leave\n");
 }
 
@@ -1491,7 +1492,7 @@ static MPP_RET hal_h264e_vepu540c_gen_regs(void *hal, HalEncTask *task)
     // scl cfg
     memcpy(&regs->reg_scl.q_intra_y8, vepu580_540_h264_flat_scl_tab, sizeof(vepu580_540_h264_flat_scl_tab));
 
-    setup_vepu540c_rc_base(regs, sps, slice, &cfg->hw, task->rc_task);
+    setup_vepu540c_rc_base(regs, ctx, task->rc_task);
     setup_vepu540c_io_buf(regs, ctx->dev, task);
     setup_vepu540c_recn_refr(ctx, regs);
 
@@ -1500,7 +1501,7 @@ static MPP_RET hal_h264e_vepu540c_gen_regs(void *hal, HalEncTask *task)
     regs->reg_base.pic_ofst.pic_ofst_y = mpp_frame_get_offset_y(task->frame);
     regs->reg_base.pic_ofst.pic_ofst_x = mpp_frame_get_offset_x(task->frame);
 
-    setup_vepu540c_split(regs, &cfg->split);
+    setup_vepu540c_split(regs, cfg);
     setup_vepu540c_me(regs, sps, slice);
 
     setup_vepu540c_l2(ctx->regs_set, slice, &cfg->hw);
@@ -1510,20 +1511,6 @@ static MPP_RET hal_h264e_vepu540c_gen_regs(void *hal, HalEncTask *task)
         vepu540c_set_roi(&ctx->regs_set->reg_rc_roi.roi_cfg, ctx->roi_data,
                          ctx->cfg->prep.width, ctx->cfg->prep.height);
 
-    mpp_env_get_u32("dump_l1_reg", &dump_l1_reg, 0);
-
-    if (dump_l1_reg) {
-        mpp_log("L1 reg dump start:\n");
-        RK_U32 *p = (RK_U32 *)regs;
-        RK_S32 n = 0x1D0 / sizeof(RK_U32);
-        RK_S32 i;
-
-        for (i = 0; i < n; i++)
-            mpp_log("%04x %08x\n", i * 4, p[i]);
-
-        mpp_log("L1 reg done\n");
-    }
-
     ctx->frame_cnt++;
 
     hal_h264e_dbg_func("leave %p\n", hal);
@@ -1669,6 +1656,9 @@ static MPP_RET hal_h264e_vepu540c_wait(void *hal, HalEncTask *task)
     MPP_RET ret = MPP_OK;
     HalH264eVepu540cCtx *ctx = (HalH264eVepu540cCtx *)hal;
     HalVepu540cRegSet *regs_set = ctx->regs_set;
+    H264NaluType type = task->rc_task->frm.is_idr ?  H264_NALU_TYPE_IDR : H264_NALU_TYPE_SLICE;
+    MppPacket pkt = task->packet;
+    RK_S32 offset = mpp_packet_get_length(pkt);
 
     hal_h264e_dbg_func("enter %p\n", hal);
     ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, NULL);
@@ -1680,6 +1670,8 @@ static MPP_RET hal_h264e_vepu540c_wait(void *hal, HalEncTask *task)
         task->hw_length += regs_set->reg_st.bs_lgth_l32;
     }
 
+    mpp_packet_add_segment_info(pkt, type, offset, regs_set->reg_st.bs_lgth_l32);
+
     {
         HalH264eVepuStreamAmend *amend = &ctx->amend;
 
diff --git a/mpp/hal/rkenc/h264e/hal_h264e_vepu541.c b/mpp/hal/rkenc/h264e/hal_h264e_vepu541.c
index f3eb8a449..27806f0c2 100644
--- a/mpp/hal/rkenc/h264e/hal_h264e_vepu541.c
+++ b/mpp/hal/rkenc/h264e/hal_h264e_vepu541.c
@@ -26,6 +26,7 @@
 #include "mpp_device.h"
 #include "mpp_frame_impl.h"
 #include "mpp_rc.h"
+#include "mpp_packet_impl.h"
 
 #include "hal_h264e_debug.h"
 #include "h264e_sps.h"
@@ -175,8 +176,9 @@ static MPP_RET hal_h264e_vepu541_init(void *hal, MppEncHalCfg *cfg)
     p->dev = cfg->dev;
 
     {
-        const char *soc_name = mpp_get_soc_name();
-        if (strstr(soc_name, "rk3566") || strstr(soc_name, "rk3568"))
+        RockchipSocType soc_type = mpp_get_soc_type();
+
+        if (soc_type == ROCKCHIP_SOC_RK3566 || soc_type == ROCKCHIP_SOC_RK3568)
             p->is_vepu540 = 1;
         else
             p->is_vepu540 = 0;
@@ -1777,6 +1779,9 @@ static MPP_RET hal_h264e_vepu541_wait(void *hal, HalEncTask *task)
 {
     MPP_RET ret = MPP_OK;
     HalH264eVepu541Ctx *ctx = (HalH264eVepu541Ctx *)hal;
+    H264NaluType type = task->rc_task->frm.is_idr ?  H264_NALU_TYPE_IDR : H264_NALU_TYPE_SLICE;
+    MppPacket pkt = task->packet;
+    RK_S32 offset = mpp_packet_get_length(pkt);
 
     hal_h264e_dbg_func("enter %p\n", hal);
 
@@ -1788,6 +1793,9 @@ static MPP_RET hal_h264e_vepu541_wait(void *hal, HalEncTask *task)
         hal_h264e_vepu541_status_check(hal);
         task->hw_length += ctx->regs_ret.st_bsl.bs_lgth;
     }
+
+    mpp_packet_add_segment_info(pkt, type, offset, ctx->regs_ret.st_bsl.bs_lgth);
+
     {
         HalH264eVepuStreamAmend *amend = &ctx->amend;
 
diff --git a/mpp/hal/rkenc/h264e/hal_h264e_vepu580.c b/mpp/hal/rkenc/h264e/hal_h264e_vepu580.c
index e560e6af5..0b57b8e2f 100644
--- a/mpp/hal/rkenc/h264e/hal_h264e_vepu580.c
+++ b/mpp/hal/rkenc/h264e/hal_h264e_vepu580.c
@@ -99,6 +99,12 @@ typedef struct HalH264eVepu580Ctx_t {
 
     /* finetune */
     void                    *tune;
+    MppBuffer               qpmap_base_cfg_buf;
+    MppBuffer               qpmap_qp_cfg_buf;
+    RK_U8*                  md_flag_buf;
+    RK_S32                  qpmap_base_cfg_size;
+    RK_S32                  qpmap_qp_cfg_size;
+    RK_S32                  md_flag_size;
 
     /* two-pass deflicker */
     MppBuffer               buf_pass1;
@@ -141,8 +147,6 @@ static RK_U32 h264e_klut_weight[30] = {
     0xFF83FFFF, 0x000001FF,
 };
 
-static RK_U32 dump_l1_reg = 0;
-static RK_U32 dump_l2_reg = 0;
 static RK_U32 disable_rcb_buf = 0;
 
 static RK_U32 h264_mode_bias[16] = {
@@ -214,8 +218,10 @@ static MPP_RET hal_h264e_vepu580_deinit(void *hal)
 
     clear_ext_line_bufs(p);
 
-    for (i = 0; i < p->task_cnt; i++)
-        h264e_vepu_stream_amend_deinit(&p->amend_sets[i]);
+    if (p->amend_sets) {
+        for (i = 0; i < p->task_cnt; i++)
+            h264e_vepu_stream_amend_deinit(&p->amend_sets[i]);
+    }
 
     MPP_FREE(p->regs_sets);
     MPP_FREE(p->amend_sets);
@@ -261,6 +267,20 @@ static MPP_RET hal_h264e_vepu580_deinit(void *hal)
         p->tune = NULL;
     }
 
+    if (p->qpmap_base_cfg_buf) {
+        mpp_buffer_put(p->qpmap_base_cfg_buf);
+        p->qpmap_base_cfg_buf = NULL;
+    }
+
+    if (p->qpmap_qp_cfg_buf) {
+        mpp_buffer_put(p->qpmap_qp_cfg_buf);
+        p->qpmap_qp_cfg_buf = NULL;
+    }
+
+    if (p->md_flag_buf) {
+        MPP_FREE(p->md_flag_buf);
+    }
+
     hal_h264e_dbg_func("leave %p\n", p);
 
     return MPP_OK;
@@ -625,7 +645,6 @@ static MPP_RET hal_h264e_vepu580_get_task(void *hal, HalEncTask *task)
 static void setup_vepu580_normal(HalVepu580RegSet *regs)
 {
     hal_h264e_dbg_func("enter\n");
-    /* reg000 VERSION is read only */
 
     /* reg001 ENC_STRT */
     regs->reg_ctl.enc_strt.lkt_num           = 0;
@@ -638,9 +657,6 @@ static void setup_vepu580_normal(HalVepu580RegSet *regs)
     regs->reg_ctl.enc_clr.safe_clr           = 0;
     regs->reg_ctl.enc_clr.force_clr          = 0;
 
-    /* reg003 LKT_ADDR */
-    // regs->reg_ctl.lkt_addr           = 0;
-
     /* reg004 INT_EN */
     regs->reg_ctl.int_en.enc_done_en         = 1;
     regs->reg_ctl.int_en.lkt_node_done_en    = 1;
@@ -663,9 +679,6 @@ static void setup_vepu580_normal(HalVepu580RegSet *regs)
     regs->reg_ctl.int_msk.rbus_err_msk       = 0;
     regs->reg_ctl.int_msk.wdg_msk            = 0;
 
-    /* reg006 INT_CLR is not set */
-    /* reg007 INT_STA is read only */
-    /* reg008 ~ reg0011 gap */
     regs->reg_ctl.enc_wdg.vs_load_thd        = 0x1fffff;
     regs->reg_ctl.enc_wdg.rfp_load_thd       = 0;
 
@@ -808,7 +821,7 @@ static MPP_RET setup_vepu580_prep(HalVepu580RegSet *regs, MppEncPrepCfg *prep,
 
 static MPP_RET vepu580_h264e_save_pass1_patch(HalVepu580RegSet *regs, HalH264eVepu580Ctx *ctx)
 {
-    RK_S32 width_align = MPP_ALIGN(ctx->cfg->prep.width, 16);
+    RK_S32 width_align = MPP_ALIGN(ctx->cfg->prep.width, 64);
     RK_S32 height_align = MPP_ALIGN(ctx->cfg->prep.height, 16);
 
     if (NULL == ctx->buf_pass1) {
@@ -836,12 +849,10 @@ static MPP_RET vepu580_h264e_save_pass1_patch(HalVepu580RegSet *regs, HalH264eVe
 static MPP_RET vepu580_h264e_use_pass1_patch(HalVepu580RegSet *regs, HalH264eVepu580Ctx *ctx)
 {
     MppEncPrepCfg *prep = &ctx->cfg->prep;
-    RK_S32 hor_stride = MPP_ALIGN(prep->width, 16);
+    RK_S32 hor_stride = MPP_ALIGN(prep->width, 64);
     RK_S32 ver_stride = MPP_ALIGN(prep->height, 16);
     RK_S32 frame_size = hor_stride * ver_stride;
     RK_S32 fd_in = mpp_buffer_get_fd(ctx->buf_pass1);
-    RK_S32 y_stride;
-    RK_S32 c_stride;
 
     hal_h264e_dbg_func("enter\n");
 
@@ -850,12 +861,9 @@ static MPP_RET vepu580_h264e_use_pass1_patch(HalVepu580RegSet *regs, HalH264eVep
     regs->reg_base.src_fmt.rbuv_swap  = 0;
     regs->reg_base.src_fmt.out_fmt    = 1;
 
-    y_stride = MPP_ALIGN(prep->width, 16);
-    c_stride = y_stride;
-
     regs->reg_base.src_proc.afbcd_en   =  0;
-    regs->reg_base.src_strd0.src_strd0  = y_stride;
-    regs->reg_base.src_strd1.src_strd1  = c_stride;
+    regs->reg_base.src_strd0.src_strd0  = hor_stride;
+    regs->reg_base.src_strd1.src_strd1  = hor_stride;
 
     regs->reg_base.src_proc.src_mirr   = 0;
     regs->reg_base.src_proc.src_rot    = 0;
@@ -884,9 +892,6 @@ static void setup_vepu580_codec(HalVepu580RegSet *regs, H264eSps *sps,
     regs->reg_base.enc_pic.enc_stnd       = 0;
     regs->reg_base.enc_pic.cur_frm_ref    = slice->nal_reference_idc > 0;
     regs->reg_base.enc_pic.bs_scp         = 1;
-    //regs->reg013.lamb_mod_sel   = (slice->slice_type == H264_I_SLICE) ? 0 : 1;
-    //regs->reg013.atr_thd_sel    = 0;
-    // regs->reg_ctl.lkt_node_cfg.node_int       = 0;
 
     regs->reg_base.synt_nal.nal_ref_idc    = slice->nal_reference_idc;
     regs->reg_base.synt_nal.nal_unit_type  = slice->nalu_type;
@@ -1231,11 +1236,14 @@ static void setup_vepu580_rdo_cfg(Vepu580RdoCfg *regs)
     hal_h264e_dbg_func("leave\n");
 }
 
-static void setup_vepu580_rc_base(HalVepu580RegSet *regs, H264eSps *sps,
-                                  H264eSlice *slice, MppEncHwCfg *hw,
-                                  EncRcTask *rc_task)
+static void setup_vepu580_rc_base(HalVepu580RegSet *regs, HalH264eVepu580Ctx *ctx, EncRcTask *rc_task)
 {
     EncRcTaskInfo *rc_info = &rc_task->info;
+    H264eSlice *slice = ctx->slice;
+    MppEncCfgSet *cfg = ctx->cfg;
+    MppEncHwCfg *hw = &cfg->hw;
+    H264eSps *sps = ctx->sps;
+    MppEncRcCfg *rc = &cfg->rc;
     RK_S32 mb_w = sps->pic_width_in_mbs;
     RK_S32 mb_h = sps->pic_height_in_mbs;
     RK_U32 qp_target = rc_info->quality_target;
@@ -1250,28 +1258,53 @@ static void setup_vepu580_rc_base(HalVepu580RegSet *regs, H264eSps *sps,
     hal_h264e_dbg_rc("bittarget %d qp [%d %d %d]\n", rc_info->bit_target,
                      qp_min, qp_target, qp_max);
 
-    if (mb_target_bits_mul_16 >= 0x100000) {
-        mb_target_bits_mul_16 = 0x50000;
+    hal_h264e_dbg_func("enter\n");
+
+    regs->reg_rc_klut.roi_qthd0.qpmin_area0    = qp_min;
+    regs->reg_rc_klut.roi_qthd0.qpmax_area0    = qp_max;
+    regs->reg_rc_klut.roi_qthd0.qpmin_area1    = qp_min;
+    regs->reg_rc_klut.roi_qthd0.qpmax_area1    = qp_max;
+    regs->reg_rc_klut.roi_qthd0.qpmin_area2    = qp_min;
+
+    regs->reg_rc_klut.roi_qthd1.qpmax_area2    = qp_max;
+    regs->reg_rc_klut.roi_qthd1.qpmin_area3    = qp_min;
+    regs->reg_rc_klut.roi_qthd1.qpmax_area3    = qp_max;
+    regs->reg_rc_klut.roi_qthd1.qpmin_area4    = qp_min;
+    regs->reg_rc_klut.roi_qthd1.qpmax_area4    = qp_max;
+
+    regs->reg_rc_klut.roi_qthd2.qpmin_area5    = qp_min;
+    regs->reg_rc_klut.roi_qthd2.qpmax_area5    = qp_max;
+    regs->reg_rc_klut.roi_qthd2.qpmin_area6    = qp_min;
+    regs->reg_rc_klut.roi_qthd2.qpmax_area6    = qp_max;
+    regs->reg_rc_klut.roi_qthd2.qpmin_area7    = qp_min;
+
+    regs->reg_rc_klut.roi_qthd3.qpmax_area7    = qp_max;
+    regs->reg_rc_klut.roi_qthd3.qpmap_mode     = qpmap_mode;
+
+    if (rc->rc_mode == MPP_ENC_RC_MODE_FIXQP) {
+        regs->reg_base.enc_pic.pic_qp    = qp_target;
+        regs->reg_base.rc_qp.rc_max_qp   = qp_target;
+        regs->reg_base.rc_qp.rc_min_qp   = qp_target;
+
+        return;
     }
 
+    if (mb_target_bits_mul_16 >= 0x100000)
+        mb_target_bits_mul_16 = 0x50000;
+
     mb_target_bits = (mb_target_bits_mul_16 * mb_w) >> 4;
     negative_bits_thd = 0 - 5 * mb_target_bits / 16;
     positive_bits_thd = 5 * mb_target_bits / 16;
 
-    hal_h264e_dbg_func("enter\n");
-
     regs->reg_base.enc_pic.pic_qp       = qp_target;
-
     regs->reg_base.rc_cfg.rc_en         = 1;
     regs->reg_base.rc_cfg.aq_en         = 1;
     regs->reg_base.rc_cfg.aq_mode       = 0;
     regs->reg_base.rc_cfg.rc_ctu_num    = mb_w;
-
     regs->reg_base.rc_qp.rc_qp_range    = (slice->slice_type == H264_I_SLICE) ?
                                           hw->qp_delta_row_i : hw->qp_delta_row;
     regs->reg_base.rc_qp.rc_max_qp      = qp_max;
     regs->reg_base.rc_qp.rc_min_qp      = qp_min;
-
     regs->reg_base.rc_tgt.ctu_ebit      = mb_target_bits_mul_16;
 
     regs->reg_rc_klut.rc_adj0.qp_adj0   = -2;
@@ -1294,27 +1327,6 @@ static void setup_vepu580_rc_base(HalVepu580RegSet *regs, H264eSps *sps,
     regs->reg_rc_klut.rc_dthd_0_8[7] = 0x7FFFFFFF;
     regs->reg_rc_klut.rc_dthd_0_8[8] = 0x7FFFFFFF;
 
-    regs->reg_rc_klut.roi_qthd0.qpmin_area0    = qp_min;
-    regs->reg_rc_klut.roi_qthd0.qpmax_area0    = qp_max;
-    regs->reg_rc_klut.roi_qthd0.qpmin_area1    = qp_min;
-    regs->reg_rc_klut.roi_qthd0.qpmax_area1    = qp_max;
-    regs->reg_rc_klut.roi_qthd0.qpmin_area2    = qp_min;
-
-    regs->reg_rc_klut.roi_qthd1.qpmax_area2    = qp_max;
-    regs->reg_rc_klut.roi_qthd1.qpmin_area3    = qp_min;
-    regs->reg_rc_klut.roi_qthd1.qpmax_area3    = qp_max;
-    regs->reg_rc_klut.roi_qthd1.qpmin_area4    = qp_min;
-    regs->reg_rc_klut.roi_qthd1.qpmax_area4    = qp_max;
-
-    regs->reg_rc_klut.roi_qthd2.qpmin_area5    = qp_min;
-    regs->reg_rc_klut.roi_qthd2.qpmax_area5    = qp_max;
-    regs->reg_rc_klut.roi_qthd2.qpmin_area6    = qp_min;
-    regs->reg_rc_klut.roi_qthd2.qpmax_area6    = qp_max;
-    regs->reg_rc_klut.roi_qthd2.qpmin_area7    = qp_min;
-
-    regs->reg_rc_klut.roi_qthd3.qpmax_area7    = qp_max;
-    regs->reg_rc_klut.roi_qthd3.qpmap_mode     = qpmap_mode;
-
     {
         /* 0x1070 ~ 0x1074 */
         regs->reg_rc_klut.md_sad_thd.md_sad_thd0 = 4;
@@ -1326,6 +1338,10 @@ static void setup_vepu580_rc_base(HalVepu580RegSet *regs, H264eSps *sps,
         regs->reg_rc_klut.madi_thd.madi_thd2 = 15;
     }
 
+    if (cfg->rc.rc_mode == MPP_ENC_RC_MODE_SMTRC) {
+        regs->reg_base.rc_qp.rc_qp_range = 0;
+    }
+
     hal_h264e_dbg_func("leave\n");
 }
 
@@ -1674,7 +1690,7 @@ static void setup_vepu580_split(HalVepu580RegSet *regs, MppEncCfgSet *enc_cfg)
 
         regs->reg_base.sli_byte.sli_splt_byte = cfg->split_arg;
         regs->reg_base.enc_pic.slen_fifo = cfg->split_out ? 1 : 0;
-        regs->reg_ctl.int_en.slc_done_en = 1;
+        regs->reg_ctl.int_en.slc_done_en = regs->reg_base.enc_pic.slen_fifo;
     } break;
     case MPP_ENC_SPLIT_BY_CTU : {
         RK_U32 mb_w = MPP_ALIGN(enc_cfg->prep.width, 16) / 16;
@@ -1690,10 +1706,11 @@ static void setup_vepu580_split(HalVepu580RegSet *regs, MppEncCfgSet *enc_cfg)
 
         regs->reg_base.sli_byte.sli_splt_byte = 0;
         regs->reg_base.enc_pic.slen_fifo = cfg->split_out ? 1 : 0;
-        regs->reg_ctl.int_en.slc_done_en = (cfg->split_out & MPP_ENC_SPLIT_OUT_LOWDELAY) ? 1 : 0;
 
-        if (slice_num > VEPU580_SLICE_FIFO_LEN)
+        if ((cfg->split_out & MPP_ENC_SPLIT_OUT_LOWDELAY) ||
+            (regs->reg_base.enc_pic.slen_fifo && (slice_num > VEPU580_SLICE_FIFO_LEN)))
             regs->reg_ctl.int_en.slc_done_en = 1;
+
     } break;
     default : {
         mpp_log_f("invalide slice split mode %d\n", cfg->split_mode);
@@ -2030,18 +2047,6 @@ static void setup_vepu580_l2(HalVepu580RegSet *regs, H264eSlice *slice, MppEncHw
         }
     }
 
-    mpp_env_get_u32("dump_l2_reg", &dump_l2_reg, 0);
-
-    if (dump_l2_reg) {
-        mpp_log("L2 reg dump start:\n");
-        RK_U32 *p = (RK_U32 *)regs;
-
-        for (i = 0; i < (sizeof(*regs) / sizeof(RK_U32)); i++)
-            mpp_log("%04x %08x\n", 4 + i * 4, p[i]);
-
-        mpp_log("L2 reg done\n");
-    }
-
     hal_h264e_dbg_func("leave\n");
 }
 
@@ -2141,14 +2146,13 @@ static MPP_RET hal_h264e_vepu580_gen_regs(void *hal, HalEncTask *task)
     // scl cfg
     memcpy(&regs->reg_scl, vepu580_540_h264_flat_scl_tab, sizeof(vepu580_540_h264_flat_scl_tab));
 
-    setup_vepu580_rc_base(regs, sps, slice, &cfg->hw, rc_task);
+    setup_vepu580_rc_base(regs, ctx, rc_task);
     setup_vepu580_io_buf(regs, ctx->offsets, task);
     setup_vepu580_roi(regs, ctx);
     setup_vepu580_recn_refr(ctx, regs);
 
     regs->reg_base.meiw_addr = task->md_info ? mpp_buffer_get_fd(task->md_info) : 0;
     regs->reg_base.enc_pic.mei_stor = task->md_info ? 1 : 0;
-
     regs->reg_base.pic_ofst.pic_ofst_y = mpp_frame_get_offset_y(task->frame);
     regs->reg_base.pic_ofst.pic_ofst_x = mpp_frame_get_offset_x(task->frame);
 
@@ -2158,6 +2162,13 @@ static MPP_RET hal_h264e_vepu580_gen_regs(void *hal, HalEncTask *task)
     if (frm_status->is_i_refresh)
         setup_vepu580_intra_refresh(regs, ctx, frm_status->seq_idx % cfg->rc.gop);
 
+    if (cfg->tune.deblur_en && (!rc_task->info.complex_scene) &&
+        cfg->rc.rc_mode == MPP_ENC_RC_MODE_SMTRC &&
+        cfg->tune.scene_mode == MPP_ENC_SCENE_MODE_IPC) {
+        if (MPP_OK != setup_vepu580_qpmap_buf(ctx))
+            mpp_err("qpmap malloc buffer failed!\n");
+    }
+
     vepu580_set_osd(&ctx->osd_cfg);
     setup_vepu580_l2(regs, slice, &cfg->hw);
     setup_vepu580_ext_line_buf(regs, ctx);
@@ -2170,20 +2181,6 @@ static MPP_RET hal_h264e_vepu580_gen_regs(void *hal, HalEncTask *task)
     if (frm->use_pass1)
         vepu580_h264e_use_pass1_patch(regs, ctx);
 
-    mpp_env_get_u32("dump_l1_reg", &dump_l1_reg, 0);
-
-    if (dump_l1_reg) {
-        mpp_log("L1 reg dump start:\n");
-        RK_U32 *p = (RK_U32 *)regs;
-        RK_S32 n = 0x1D0 / sizeof(RK_U32);
-        RK_S32 i;
-
-        for (i = 0; i < n; i++)
-            mpp_log("%04x %08x\n", i * 4, p[i]);
-
-        mpp_log("L1 reg done\n");
-    }
-
     ctx->frame_cnt++;
 
     hal_h264e_dbg_func("leave %p\n", hal);
@@ -2372,10 +2369,18 @@ static MPP_RET hal_h264e_vepu580_wait(void *hal, HalEncTask *task)
     MppPacket pkt = task->packet;
     RK_S32 offset = mpp_packet_get_length(pkt);
     H264NaluType type = task->rc_task->frm.is_idr ?  H264_NALU_TYPE_IDR : H264_NALU_TYPE_SLICE;
+    MppEncH264HwCfg *hw_cfg = &ctx->cfg->codec.h264.hw_cfg;
     RK_S32 i;
 
     hal_h264e_dbg_func("enter %p\n", hal);
 
+    /* if pass1 mode, it will disable split mode and the split out need to be disable */
+    if (task->rc_task->frm.save_pass1)
+        split_out = 0;
+
+    /* update split_out in hw_cfg */
+    hw_cfg->hw_split_out = split_out;
+
     if (split_out) {
         EncOutParam param;
         RK_U32 slice_len;
@@ -2388,7 +2393,7 @@ static MPP_RET hal_h264e_vepu580_wait(void *hal, HalEncTask *task)
         do {
             poll_cfg->poll_type = 0;
             poll_cfg->poll_ret  = 0;
-            poll_cfg->count_max = ctx->poll_slice_max;
+            poll_cfg->count_max = split_out & MPP_ENC_SPLIT_OUT_LOWDELAY ? 1 : ctx->poll_slice_max;
             poll_cfg->count_ret = 0;
 
             ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, poll_cfg);
@@ -2434,7 +2439,6 @@ static MPP_RET hal_h264e_vepu580_wait(void *hal, HalEncTask *task)
         HalH264eVepuStreamAmend *amend = &ctx->amend_sets[task->flags.reg_idx];
 
         if (amend->enable) {
-            amend->diable_split_out = !split_out;
             amend->old_length = task->hw_length;
             amend->slice->is_multi_slice = (ctx->cfg->split.split_mode > 0);
             h264e_vepu_stream_amend_proc(amend, &ctx->cfg->codec.h264.hw_cfg);
@@ -2490,6 +2494,36 @@ static MPP_RET hal_h264e_vepu580_ret_task(void * hal, HalEncTask * task)
     task->hal_ret.data   = &ctx->hal_rc_cfg;
     task->hal_ret.number = 1;
 
+    //RK_U32 madi_th_cnt0 = ctx->regs_set->reg_st.madi_b16num0;
+    RK_U32 madi_th_cnt1 = ctx->regs_set->reg_st.madi_b16num1;
+    RK_U32 madi_th_cnt2 = ctx->regs_set->reg_st.madi_b16num2;
+    RK_U32 madi_th_cnt3 = ctx->regs_set->reg_st.madi_b16num3;
+    //RK_U32 madp_th_cnt0 = ctx->regs_set->reg_st.md_sad_b16num0;
+    RK_U32 madp_th_cnt1 = ctx->regs_set->reg_st.md_sad_b16num1;
+    RK_U32 madp_th_cnt2 = ctx->regs_set->reg_st.md_sad_b16num2;
+    RK_U32 madp_th_cnt3 = ctx->regs_set->reg_st.md_sad_b16num3;
+
+    RK_U32 md_cnt = (24 * madp_th_cnt3 + 22 * madp_th_cnt2 + 17 * madp_th_cnt1) >> 2;
+    RK_U32 madi_cnt = (6 * madi_th_cnt3 + 5 * madi_th_cnt2 + 4 * madi_th_cnt1) >> 2;
+
+    rc_info->motion_level = 0;
+    if (md_cnt * 100 > 15 * mbs)
+        rc_info->motion_level = 200;
+    else if (md_cnt * 100 > 5 * mbs)
+        rc_info->motion_level = 100;
+    else
+        rc_info->motion_level = 0;
+
+    rc_info->complex_level = 0;
+    if (madi_cnt * 100 > 30 * mbs)
+        rc_info->complex_level = 2;
+    else if (madi_cnt * 100 > 13 * mbs)
+        rc_info->complex_level = 1;
+    else
+        rc_info->complex_level = 0;
+
+    hal_h264e_dbg_rc("motion_level %u, complex_level %u\n", rc_info->motion_level, rc_info->complex_level);
+
     vepu580_h264e_tune_stat_update(ctx->tune, task);
 
     mpp_dev_multi_offset_reset(ctx->offsets);
diff --git a/mpp/hal/rkenc/h264e/hal_h264e_vepu580_tune.c b/mpp/hal/rkenc/h264e/hal_h264e_vepu580_tune.c
index 15922c3a8..367fd14a3 100644
--- a/mpp/hal/rkenc/h264e/hal_h264e_vepu580_tune.c
+++ b/mpp/hal/rkenc/h264e/hal_h264e_vepu580_tune.c
@@ -133,7 +133,9 @@ static void vepu580_h264e_tune_reg_patch(void *p)
 
     /* modify register here */
     if (slice->slice_type != H264_I_SLICE) {
-        RK_U32 *src = tune->curr_scene_motion_flag ? &h264e_klut_weight[0] : &h264e_klut_weight[4];
+        RK_U32 *src = (tune->curr_scene_motion_flag ||
+                       ctx->cfg->rc.rc_mode == MPP_ENC_RC_MODE_SMTRC) ?
+                      &h264e_klut_weight[0] : &h264e_klut_weight[4];
         memcpy(&regs->reg_rc_klut.klut_wgt0, src, CHROMA_KLUT_TAB_SIZE);
     }
 
@@ -215,8 +217,8 @@ static void vepu580_h264e_tune_reg_patch(void *p)
     regs->reg_s3.rime_sqi_multi.rime_multi2 = rime_multi[scene_motion_flag][2];
 
     if (hw->qbias_en) {
-        regs->reg_s3.RDO_QUANT.quant_f_bias_I = hw->qbias_i;
-        regs->reg_s3.RDO_QUANT.quant_f_bias_P = hw->qbias_p;
+        regs->reg_s3.RDO_QUANT.quant_f_bias_I = hw->qbias_i ? hw->qbias_i : 683;
+        regs->reg_s3.RDO_QUANT.quant_f_bias_P = hw->qbias_p ? hw->qbias_p : 341;
     }
 }
 
@@ -333,3 +335,52 @@ static void vepu580_h264e_tune_stat_update(void *p, HalEncTask *task)
     tune->pre_madi[1] = tune->pre_madi[0];
     tune->pre_madp[1] = tune->pre_madp[0];
 }
+
+static MPP_RET setup_vepu580_qpmap_buf(HalH264eVepu580Ctx *ctx)
+{
+    MPP_RET ret = MPP_OK;
+    RK_S32 mb_w = MPP_ALIGN(ctx->cfg->prep.width, 64) / 16;
+    RK_S32 mb_h = MPP_ALIGN(ctx->cfg->prep.height, 16) / 16;
+    RK_S32 qpmap_base_cfg_size = ctx->qpmap_base_cfg_size
+                                 = mb_w * mb_h * 8;
+    RK_S32 qpmap_qp_cfg_size   = ctx->qpmap_qp_cfg_size
+                                 = mb_w * mb_h * 2;
+    RK_S32 md_flag_size        = ctx->md_flag_size
+                                 = mb_w * mb_h;
+
+    if (!ctx->cfg->tune.deblur_en) {
+        mpp_log("deblurring is closed!\n");
+        goto __RET;
+    }
+
+    if (NULL == ctx->qpmap_base_cfg_buf) {
+        mpp_buffer_get(NULL, &ctx->qpmap_base_cfg_buf, qpmap_base_cfg_size);
+        if (!ctx->qpmap_base_cfg_buf) {
+            mpp_err("qpmap_base_cfg_buf malloc fail, qpmap invalid\n");
+            ret = MPP_ERR_VALUE;
+            goto __RET;
+        }
+    }
+
+    if (NULL == ctx->qpmap_qp_cfg_buf) {
+        mpp_buffer_get(NULL, &ctx->qpmap_qp_cfg_buf, qpmap_qp_cfg_size);
+        if (!ctx->qpmap_qp_cfg_buf) {
+            mpp_err("qpmap_qp_cfg_buf malloc fail, qpmap invalid\n");
+            ret = MPP_ERR_VALUE;
+            goto __RET;
+        }
+    }
+
+    if (NULL == ctx->md_flag_buf) {
+        ctx->md_flag_buf = mpp_malloc(RK_U8, md_flag_size);
+        if (!ctx->md_flag_buf) {
+            mpp_err("md_flag_buf malloc fail, qpmap invalid\n");
+            ret = MPP_ERR_VALUE;
+            goto __RET;
+        }
+    }
+
+__RET:
+    hal_h264e_dbg_func("leave, ret %d\n", ret);
+    return ret;
+}
\ No newline at end of file
diff --git a/mpp/hal/rkenc/h265e/CMakeLists.txt b/mpp/hal/rkenc/h265e/CMakeLists.txt
index c6931c3c9..7dd872e60 100644
--- a/mpp/hal/rkenc/h265e/CMakeLists.txt
+++ b/mpp/hal/rkenc/h265e/CMakeLists.txt
@@ -9,6 +9,7 @@ include_directories(../../../codec/enc/h265/)
 set(HAL_H265E_HDR
     hal_h265e_vepu541_reg.h
     hal_h265e_vepu580_reg.h
+    hal_h265e_vepu510_reg.h
     )
 
 # hal h265 encoder sourse
@@ -16,6 +17,7 @@ set(HAL_H265E_SRC
     hal_h265e_vepu541.c
     hal_h265e_vepu580.c
     hal_h265e_vepu540c.c
+    hal_h265e_vepu510.c
     )
 
 add_library(hal_h265e_vepu541 STATIC
@@ -23,5 +25,5 @@ add_library(hal_h265e_vepu541 STATIC
             ${HAL_H265E_SRC}
             )
 
-target_link_libraries(hal_h265e_vepu541 hal_h265e hal_common hal_vepu541_common)
+target_link_libraries(hal_h265e_vepu541 hal_h265e_com hal_common hal_vepu541_common)
 set_target_properties(hal_h265e_vepu541 PROPERTIES FOLDER "mpp/hal")
diff --git a/mpp/hal/rkenc/h265e/hal_h265e_vepu510.c b/mpp/hal/rkenc/h265e/hal_h265e_vepu510.c
new file mode 100644
index 000000000..c806dc99a
--- /dev/null
+++ b/mpp/hal/rkenc/h265e/hal_h265e_vepu510.c
@@ -0,0 +1,2608 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#define MODULE_TAG  "hal_h265e_v510"
+
+#include <string.h>
+#include <math.h>
+#include <limits.h>
+
+#include "mpp_env.h"
+#include "mpp_mem.h"
+#include "mpp_common.h"
+#include "mpp_frame_impl.h"
+#include "mpp_packet_impl.h"
+#include "mpp_enc_cb_param.h"
+
+#include "rkv_enc_def.h"
+#include "h265e_syntax_new.h"
+#include "h265e_dpb.h"
+#include "hal_bufs.h"
+#include "hal_h265e_debug.h"
+#include "hal_h265e_vepu510.h"
+#include "hal_h265e_vepu510_reg.h"
+#include "hal_h265e_stream_amend.h"
+
+#include "vepu5xx_common.h"
+#include "vepu541_common.h"
+#include "vepu510_common.h"
+
+#define MAX_FRAME_TASK_NUM      2
+#define H265E_LAMBDA_TAB_SIZE  (52 * sizeof(RK_U32))
+
+#define hal_h265e_err(fmt, ...) \
+    do {\
+        mpp_err_f(fmt, ## __VA_ARGS__);\
+    } while (0)
+
+typedef struct Vepu510H265Fbk_t {
+    RK_U32 hw_status; /* 0:corret, 1:error */
+    RK_U32 frame_type;
+    RK_U32 qp_sum;
+    RK_U32 out_strm_size;
+    RK_U32 out_hw_strm_size;
+    RK_S64 sse_sum;
+    RK_U32 st_lvl64_inter_num;
+    RK_U32 st_lvl32_inter_num;
+    RK_U32 st_lvl16_inter_num;
+    RK_U32 st_lvl8_inter_num;
+    RK_U32 st_lvl32_intra_num;
+    RK_U32 st_lvl16_intra_num;
+    RK_U32 st_lvl8_intra_num;
+    RK_U32 st_lvl4_intra_num;
+    RK_U32 st_cu_num_qp[52];
+    RK_U32 st_madp;
+    RK_U32 st_madi;
+    RK_U32 st_mb_num;
+    RK_U32 st_ctu_num;
+    RK_U32 st_smear_cnt[5];
+    RK_S32 reg_idx;
+    RK_U32 acc_cover16_num;
+    RK_U32 acc_bndry16_num;
+    RK_U32 acc_zero_mv;
+    RK_S8 tgt_sub_real_lvl[6];
+} Vepu510H265Fbk;
+
+typedef struct Vepu510H265eFrmCfg_t {
+    RK_S32              frame_count;
+    RK_S32              frame_type;
+
+    /* dchs cfg on frame parallel */
+    RK_S32              dchs_curr_idx;
+    RK_S32              dchs_prev_idx;
+
+    /* hal dpb management slot idx */
+    RK_S32              hal_curr_idx;
+    RK_S32              hal_refr_idx;
+
+    /* regs cfg */
+    H265eV510RegSet     *regs_set;
+    H265eV510StatusElem *regs_ret;
+
+    /* hardware return info collection cfg */
+    Vepu510H265Fbk      feedback;
+
+    /* osd cfg */
+    Vepu541OsdCfg       osd_cfg;
+    void                *roi_data;
+
+    /* roi buffer for qpmap or gdr */
+    MppBuffer           roir_buf;
+    RK_S32              roir_buf_size;
+    void                *roi_base_cfg_sw_buf;
+
+    /* variable length cfg */
+    MppDevRegOffCfgs    *reg_cfg;
+} Vepu510H265eFrmCfg;
+
+typedef struct H265eV510HalContext_t {
+    MppEncHalApi        api;
+    MppDev              dev;
+    void                *regs;
+    void                *reg_out;
+    Vepu510H265eFrmCfg  *frms[MAX_FRAME_TASK_NUM];
+
+    /* current used frame config */
+    Vepu510H265eFrmCfg  *frm;
+
+    /* slice split poll cfg */
+    RK_S32              poll_slice_max;
+    RK_S32              poll_cfg_size;
+    MppDevPollCfg       *poll_cfgs;
+    MppCbCtx            *output_cb;
+
+    /* @frame_cnt starts from ZERO */
+    RK_S32              frame_count;
+
+    /* frame parallel info */
+    RK_S32              task_cnt;
+    RK_S32              task_idx;
+
+    /* dchs cfg */
+    RK_S32              curr_idx;
+    RK_S32              prev_idx;
+
+    Vepu510H265Fbk      feedback;
+    Vepu510H265Fbk      last_frame_fb;
+    void                *dump_files;
+    RK_U32              frame_cnt_gen_ready;
+
+    RK_S32              frame_type;
+    RK_S32              last_frame_type;
+
+    MppBufferGroup      roi_grp;
+    void                *roi_data;
+    MppEncCfgSet        *cfg;
+    MppDevRegOffCfgs    *reg_cfg;
+    H265eSyntax_new     *syn;
+    H265eDpb            *dpb;
+
+    RK_U32              enc_mode;
+    RK_U32              frame_size;
+    RK_S32              max_buf_cnt;
+    RK_S32              hdr_status;
+    void                *input_fmt;
+    RK_U8               *src_buf;
+    RK_U8               *dst_buf;
+    RK_S32              buf_size;
+    RK_U32              frame_num;
+    HalBufs             dpb_bufs;
+    RK_S32              fbc_header_len;
+    RK_U32              title_num;
+
+    RK_S32              qpmap_en;
+    RK_S32              smart_en;
+
+    /* external line buffer over 3K */
+    MppBufferGroup      ext_line_buf_grp;
+    RK_S32              ext_line_buf_size;
+    MppBuffer           ext_line_buf;
+    MppBuffer           buf_pass1;
+    MppBuffer           ext_line_bufs[MAX_FRAME_TASK_NUM];
+
+    void                *tune;
+} H265eV510HalContext;
+
+#include "hal_h265e_vepu510_tune.c"
+
+static RK_S32 atf_b32_skip_thd2[4] = {15, 15, 15, 200};
+static RK_S32 atf_b32_skip_thd3[4] = {72, 72, 72, 1000};
+static RK_S32 atf_b32_skip_wgt0[4] = {16, 20, 20, 16};
+static RK_S32 atf_b32_skip_wgt3[4] = {16, 16, 16, 17};
+static RK_S32 atf_b16_skip_thd2[4] = {15, 15, 15, 200};
+static RK_S32 atf_b16_skip_thd3[4] = {25, 25, 25, 1000};
+static RK_S32 atf_b16_skip_wgt0[4] = {16, 20, 20, 16};
+static RK_S32 atf_b16_skip_wgt3[4] = {16, 16, 16, 17};
+static RK_S32 atf_b32_intra_thd0[4] = {20, 20, 20, 24};
+static RK_S32 atf_b32_intra_thd1[4] = {40, 40, 40, 48};
+static RK_S32 atf_b32_intra_thd2[4] = {60, 72, 72, 96};
+static RK_S32 atf_b32_intra_wgt0[4] = {16, 22, 27, 28};
+static RK_S32 atf_b32_intra_wgt1[4] = {16, 20, 25, 26};
+static RK_S32 atf_b32_intra_wgt2[4] = {16, 18, 20, 24};
+static RK_S32 atf_b16_intra_thd0[4] = {20, 20, 20, 24};
+static RK_S32 atf_b16_intra_thd1[4] = {40, 40, 40, 48};
+static RK_S32 atf_b16_intra_thd2[4] = {60, 72, 72, 96};
+static RK_S32 atf_b16_intra_wgt0[4] = {16, 22, 27, 28};
+static RK_S32 atf_b16_intra_wgt1[4] = {16, 20, 25, 26};
+static RK_S32 atf_b16_intra_wgt2[4] = {16, 18, 20, 24};
+
+static RK_S32 smear_qp_strength[8] = {4, 6, 7, 7, 3, 5, 7, 7};
+static RK_S32 smear_strength[8] = {1, 1, 1, 1, 1, 1, 1, 1};
+static RK_S32 smear_common_intra_r_dep0[8] = {224, 224, 200, 200, 224, 224, 200, 200};
+static RK_S32 smear_common_intra_r_dep1[8] = {224, 224, 180, 200, 224, 224, 180, 200};
+static RK_S32 smear_bndry_intra_r_dep0[8] = {240, 240, 240, 240, 240, 240, 240, 240};
+static RK_S32 smear_bndry_intra_r_dep1[8] = {240, 240, 240, 240, 240, 240, 240, 240};
+static RK_S32 smear_thre_madp_stc_cover0[8] = {20, 22, 22, 22, 20, 22, 22, 30};
+static RK_S32 smear_thre_madp_stc_cover1[8] = {20, 22, 22, 22, 20, 22, 22, 30};
+static RK_S32 smear_thre_madp_mov_cover0[8] = {10, 9, 9, 9, 10, 9, 9, 6};
+static RK_S32 smear_thre_madp_mov_cover1[8] = {10, 9, 9, 9, 10, 9, 9, 6};
+
+static RK_S32 smear_flag_cover_thd0[8] = {12, 13, 13, 13, 12, 13, 13, 17};
+static RK_S32 smear_flag_cover_thd1[8] = {61, 70, 70, 70, 61, 70, 70, 90};
+static RK_S32 smear_flag_bndry_thd0[8] = {12, 12, 12, 12, 12, 12, 12, 12};
+static RK_S32 smear_flag_bndry_thd1[8] = {73, 73, 73, 73, 73, 73, 73, 73};
+
+static RK_S32 smear_flag_cover_wgt[3] = {1, 0, -3};
+static RK_S32 smear_flag_cover_intra_wgt0[3] = { -12, 0, 12};
+static RK_S32 smear_flag_cover_intra_wgt1[3] = { -12, 0, 12};
+static RK_S32 smear_flag_bndry_wgt[3] = {0, 0, 0};
+static RK_S32 smear_flag_bndry_intra_wgt0[3] = { -12, 0, 12};
+static RK_S32 smear_flag_bndry_intra_wgt1[3] = { -12, 0, 12};
+
+static RK_U32 rdo_lambda_table_I[60] = {
+    0x00000012, 0x00000017,
+    0x0000001d, 0x00000024, 0x0000002e, 0x0000003a,
+    0x00000049, 0x0000005c, 0x00000074, 0x00000092,
+    0x000000b8, 0x000000e8, 0x00000124, 0x00000170,
+    0x000001cf, 0x00000248, 0x000002df, 0x0000039f,
+    0x0000048f, 0x000005bf, 0x0000073d, 0x0000091f,
+    0x00000b7e, 0x00000e7a, 0x0000123d, 0x000016fb,
+    0x00001cf4, 0x0000247b, 0x00002df6, 0x000039e9,
+    0x000048f6, 0x00005bed, 0x000073d1, 0x000091ec,
+    0x0000b7d9, 0x0000e7a2, 0x000123d7, 0x00016fb2,
+    0x0001cf44, 0x000247ae, 0x0002df64, 0x00039e89,
+    0x00048f5c, 0x0005bec8, 0x00073d12, 0x00091eb8,
+    0x000b7d90, 0x000e7a23, 0x00123d71, 0x0016fb20,
+    0x001cf446, 0x00247ae1, 0x002df640, 0x0039e88c,
+    0x0048f5c3, 0x005bec81, 0x0073d119, 0x0091eb85,
+    0x00b7d902, 0x00e7a232
+};
+
+static RK_U32 rdo_lambda_table_P[60] = {
+    0x0000002c, 0x00000038, 0x00000044, 0x00000058,
+    0x00000070, 0x00000089, 0x000000b0, 0x000000e0,
+    0x00000112, 0x00000160, 0x000001c0, 0x00000224,
+    0x000002c0, 0x00000380, 0x00000448, 0x00000580,
+    0x00000700, 0x00000890, 0x00000b00, 0x00000e00,
+    0x00001120, 0x00001600, 0x00001c00, 0x00002240,
+    0x00002c00, 0x00003800, 0x00004480, 0x00005800,
+    0x00007000, 0x00008900, 0x0000b000, 0x0000e000,
+    0x00011200, 0x00016000, 0x0001c000, 0x00022400,
+    0x0002c000, 0x00038000, 0x00044800, 0x00058000,
+    0x00070000, 0x00089000, 0x000b0000, 0x000e0000,
+    0x00112000, 0x00160000, 0x001c0000, 0x00224000,
+    0x002c0000, 0x00380000, 0x00448000, 0x00580000,
+    0x00700000, 0x00890000, 0x00b00000, 0x00e00000,
+    0x01120000, 0x01600000, 0x01c00000, 0x02240000,
+};
+
+static RK_U8 vepu510_h265_cqm_intra8[64] = {
+    16, 16, 16, 16, 17, 18, 21, 24,
+    16, 16, 16, 16, 17, 19, 22, 25,
+    16, 16, 17, 18, 20, 22, 25, 29,
+    16, 16, 18, 21, 24, 27, 31, 36,
+    17, 17, 20, 24, 30, 35, 41, 47,
+    18, 19, 22, 27, 35, 44, 54, 65,
+    21, 22, 25, 31, 41, 54, 70, 88,
+    24, 25, 29, 36, 47, 65, 88, 115
+};
+
+static RK_U8 vepu510_h265_cqm_inter8[64] = {
+    16, 16, 16, 16, 17, 18, 20, 24,
+    16, 16, 16, 17, 18, 20, 24, 25,
+    16, 16, 17, 18, 20, 24, 25, 28,
+    16, 17, 18, 20, 24, 25, 28, 33,
+    17, 18, 20, 24, 25, 28, 33, 41,
+    18, 20, 24, 25, 28, 33, 41, 54,
+    20, 24, 25, 28, 33, 41, 54, 71,
+    24, 25, 28, 33, 41, 54, 71, 91
+};
+
+static void setup_ext_line_bufs(H265eV510HalContext *ctx)
+{
+    RK_S32 i;
+
+    for (i = 0; i < ctx->task_cnt; i++) {
+        if (ctx->ext_line_bufs[i])
+            continue;
+
+        mpp_buffer_get(ctx->ext_line_buf_grp, &ctx->ext_line_bufs[i],
+                       ctx->ext_line_buf_size);
+    }
+}
+
+static void clear_ext_line_bufs(H265eV510HalContext *ctx)
+{
+    RK_S32 i;
+
+    for (i = 0; i < ctx->task_cnt; i++) {
+        if (ctx->ext_line_bufs[i]) {
+            mpp_buffer_put(ctx->ext_line_bufs[i]);
+            ctx->ext_line_bufs[i] = NULL;
+        }
+    }
+}
+
+static MPP_RET vepu510_h265_setup_hal_bufs(H265eV510HalContext *ctx)
+{
+    MPP_RET ret = MPP_OK;
+    VepuFmtCfg *fmt = (VepuFmtCfg *)ctx->input_fmt;
+    RK_U32 frame_size;
+    Vepu541Fmt input_fmt = VEPU541_FMT_YUV420P;
+    RK_S32 mb_wd64, mb_h64;
+    MppEncRefCfg ref_cfg = ctx->cfg->ref_cfg;
+    MppEncPrepCfg *prep = &ctx->cfg->prep;
+    RK_S32 old_max_cnt = ctx->max_buf_cnt;
+    RK_S32 new_max_cnt = 4;
+    RK_S32 alignment = 32;
+    RK_S32 aligned_w = MPP_ALIGN(prep->width,  alignment);
+
+    hal_h265e_enter();
+
+    mb_wd64 = (prep->width + 63) / 64;
+    mb_h64 = (prep->height + 63) / 64 + 1;
+
+    frame_size = MPP_ALIGN(prep->width, 16) * MPP_ALIGN(prep->height, 16);
+    vepu541_set_fmt(fmt, ctx->cfg->prep.format);
+    input_fmt = (Vepu541Fmt)fmt->format;
+    switch (input_fmt) {
+    case VEPU540_FMT_YUV400:
+        break;
+    case VEPU541_FMT_YUV420P:
+    case VEPU541_FMT_YUV420SP: {
+        frame_size = frame_size * 3 / 2;
+    } break;
+    case VEPU541_FMT_YUV422P:
+    case VEPU541_FMT_YUV422SP:
+    case VEPU541_FMT_YUYV422:
+    case VEPU541_FMT_UYVY422:
+    case VEPU541_FMT_BGR565: {
+        frame_size *= 2;
+    } break;
+    case VEPU541_FMT_BGR888:
+    case VEPU580_FMT_YUV444SP:
+    case VEPU580_FMT_YUV444P: {
+        frame_size *= 3;
+    } break;
+    case VEPU541_FMT_BGRA8888: {
+        frame_size *= 4;
+    } break;
+    default: {
+        hal_h265e_err("invalid src color space: %d\n", input_fmt);
+        return MPP_NOK;
+    }
+    }
+
+    if (ref_cfg) {
+        MppEncCpbInfo *info = mpp_enc_ref_cfg_get_cpb_info(ref_cfg);
+        new_max_cnt = MPP_MAX(new_max_cnt, info->dpb_size + 1);
+    }
+
+    if (aligned_w > SZ_4K) {
+        RK_S32 ctu_w = (aligned_w + 31) / 32;
+        RK_S32 ext_line_buf_size = ((ctu_w - 113) * 27 + 15) / 16 * 16 * 16;
+
+        if (NULL == ctx->ext_line_buf_grp)
+            mpp_buffer_group_get_internal(&ctx->ext_line_buf_grp, MPP_BUFFER_TYPE_ION);
+        else if (ext_line_buf_size != ctx->ext_line_buf_size) {
+            clear_ext_line_bufs(ctx);
+            mpp_buffer_group_clear(ctx->ext_line_buf_grp);
+        }
+
+        mpp_assert(ctx->ext_line_buf_grp);
+        setup_ext_line_bufs(ctx);
+        ctx->ext_line_buf_size = ext_line_buf_size;
+    } else {
+        clear_ext_line_bufs(ctx);
+
+        if (ctx->ext_line_buf_grp) {
+            mpp_buffer_group_clear(ctx->ext_line_buf_grp);
+            mpp_buffer_group_put(ctx->ext_line_buf_grp);
+            ctx->ext_line_buf_grp = NULL;
+        }
+        ctx->ext_line_buf_size = 0;
+    }
+
+    if (frame_size > ctx->frame_size || new_max_cnt > old_max_cnt) {
+        size_t size[4] = {0};
+        RK_S32 ctu_w = (prep->width + 31) / 32;
+        RK_S32 ctu_h = (prep->height + 31) / 32;
+
+        hal_bufs_deinit(ctx->dpb_bufs);
+        hal_bufs_init(&ctx->dpb_bufs);
+
+        ctx->fbc_header_len = MPP_ALIGN(((mb_wd64 * mb_h64) << 6), SZ_8K);
+        size[0] = ctx->fbc_header_len + ((mb_wd64 * mb_h64) << 12) * 3 / 2; //fbc_h + fbc_b
+        size[1] = (mb_wd64 * mb_h64 << 8);
+        size[2] = MPP_ALIGN(mb_wd64 * mb_h64 * 16 * 4, 256) * 16;
+        /* smear bufs */
+        size[3] = MPP_ALIGN(ctu_w, 16) * MPP_ALIGN(ctu_h, 16);
+        new_max_cnt = MPP_MAX(new_max_cnt, old_max_cnt);
+
+        hal_h265e_dbg_detail("frame size %d -> %d max count %d -> %d\n",
+                             ctx->frame_size, frame_size, old_max_cnt, new_max_cnt);
+
+        hal_bufs_setup(ctx->dpb_bufs, new_max_cnt, MPP_ARRAY_ELEMS(size), size);
+
+        ctx->frame_size = frame_size;
+        ctx->max_buf_cnt = new_max_cnt;
+    }
+    hal_h265e_leave();
+    return ret;
+}
+
+static void vepu510_h265_set_atr_regs(H265eVepu510Sqi *reg_sqi, MppEncSceneMode sm, int atr_level)
+{
+    // atr_level 0~3
+    // 0 close
+    // 1 weak
+    // 2 medium
+    // 3 strong
+    H265eVepu510Sqi *reg = reg_sqi;
+    (void)sm;
+    if (atr_level == 0) {
+        reg->block_opt_cfg.block_en = 0;
+        reg->cmplx_opt_cfg.cmplx_en = 0;
+        reg->line_opt_cfg.line_en = 0;
+    } else {
+        reg->block_opt_cfg.block_en = 0;
+        reg->cmplx_opt_cfg.cmplx_en = 0;
+        reg->line_opt_cfg.line_en = 1;
+    }
+
+    if (atr_level == 3) {
+        reg->block_opt_cfg.block_thre_cst_best_mad          = 1000;
+        reg->block_opt_cfg.block_thre_cst_best_grdn_blk     = 39;
+        reg->block_opt_cfg.thre_num_grdnt_point_cmplx       = 3;
+        reg->block_opt_cfg.block_delta_qp_flag              = 3;
+
+        reg->cmplx_opt_cfg.cmplx_thre_cst_best_mad_dep0     = 4000;
+        reg->cmplx_opt_cfg.cmplx_thre_cst_best_mad_dep1     = 2000;
+
+        reg->cmplx_bst_mad_thd.cmplx_thre_cst_best_mad_dep2         = 200;
+        reg->cmplx_bst_mad_thd.cmplx_thre_cst_best_grdn_blk_dep0    = 977;
+
+        reg->cmplx_bst_grdn_thd.cmplx_thre_cst_best_grdn_blk_dep1   = 0;
+        reg->cmplx_bst_grdn_thd.cmplx_thre_cst_best_grdn_blk_dep2   = 488;
+
+        reg->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep0      = 4;
+        reg->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep1      = 30;//20
+        reg->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep2      = 30;//20
+        reg->line_opt_cfg.line_thre_ratio_best_grdn_blk_dep0        = 7;//7
+        reg->line_opt_cfg.line_thre_ratio_best_grdn_blk_dep1        = 6;//8
+
+        reg->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep0    = 1;
+        reg->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep1    = 50;
+        reg->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep2    = 50;
+
+        reg->subj_opt_dqp0.line_thre_qp                     = 20;
+        reg->subj_opt_dqp0.block_strength                   = 4;
+        reg->subj_opt_dqp0.block_thre_qp                    = 30;
+        reg->subj_opt_dqp0.cmplx_strength                   = 4;
+        reg->subj_opt_dqp0.cmplx_thre_qp                    = 34;
+        reg->subj_opt_dqp0.cmplx_thre_max_grdn_blk          = 32;
+    } else if (atr_level == 2) {
+        reg->block_opt_cfg.block_thre_cst_best_mad          = 1000;
+        reg->block_opt_cfg.block_thre_cst_best_grdn_blk     = 39;
+        reg->block_opt_cfg.thre_num_grdnt_point_cmplx       = 3;
+        reg->block_opt_cfg.block_delta_qp_flag              = 3;
+
+        reg->cmplx_opt_cfg.cmplx_thre_cst_best_mad_dep0     = 4000;
+        reg->cmplx_opt_cfg.cmplx_thre_cst_best_mad_dep1     = 2000;
+
+        reg->cmplx_bst_mad_thd.cmplx_thre_cst_best_mad_dep2         = 200;
+        reg->cmplx_bst_mad_thd.cmplx_thre_cst_best_grdn_blk_dep0    = 977;
+
+        reg->cmplx_bst_grdn_thd.cmplx_thre_cst_best_grdn_blk_dep1   = 0;
+        reg->cmplx_bst_grdn_thd.cmplx_thre_cst_best_grdn_blk_dep2   = 488;
+
+        reg->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep0      = 3;
+        reg->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep1      = 20;
+        reg->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep2      = 20;
+        reg->line_opt_cfg.line_thre_ratio_best_grdn_blk_dep0        = 7;
+        reg->line_opt_cfg.line_thre_ratio_best_grdn_blk_dep1        = 8;
+
+        reg->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep0    = 1;
+        reg->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep1    = 60;
+        reg->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep2    = 60;
+
+        reg->subj_opt_dqp0.line_thre_qp                     = 25;
+        reg->subj_opt_dqp0.block_strength                   = 4;
+        reg->subj_opt_dqp0.block_thre_qp                    = 30;
+        reg->subj_opt_dqp0.cmplx_strength                   = 4;
+        reg->subj_opt_dqp0.cmplx_thre_qp                    = 34;
+        reg->subj_opt_dqp0.cmplx_thre_max_grdn_blk          = 32;
+    } else {
+        reg->block_opt_cfg.block_thre_cst_best_mad          = 1000;
+        reg->block_opt_cfg.block_thre_cst_best_grdn_blk     = 39;
+        reg->block_opt_cfg.thre_num_grdnt_point_cmplx       = 3;
+        reg->block_opt_cfg.block_delta_qp_flag              = 3;
+
+        reg->cmplx_opt_cfg.cmplx_thre_cst_best_mad_dep0     = 6000;
+        reg->cmplx_opt_cfg.cmplx_thre_cst_best_mad_dep1     = 2000;
+
+        reg->cmplx_bst_mad_thd.cmplx_thre_cst_best_mad_dep2         = 300;
+        reg->cmplx_bst_mad_thd.cmplx_thre_cst_best_grdn_blk_dep0    = 1280;
+
+        reg->cmplx_bst_grdn_thd.cmplx_thre_cst_best_grdn_blk_dep1   = 0;
+        reg->cmplx_bst_grdn_thd.cmplx_thre_cst_best_grdn_blk_dep2   = 512;
+
+        reg->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep0      = 3;
+        reg->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep1      = 20;
+        reg->line_opt_cfg.line_thre_min_cst_best_grdn_blk_dep2      = 20;
+        reg->line_opt_cfg.line_thre_ratio_best_grdn_blk_dep0        = 7;
+        reg->line_opt_cfg.line_thre_ratio_best_grdn_blk_dep1        = 8;
+
+        reg->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep0    = 1;
+        reg->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep1    = 70;
+        reg->line_cst_bst_grdn.line_thre_max_cst_best_grdn_blk_dep2    = 70;
+
+        reg->subj_opt_dqp0.line_thre_qp                     = 30;
+        reg->subj_opt_dqp0.block_strength                   = 4;
+        reg->subj_opt_dqp0.block_thre_qp                    = 30;
+        reg->subj_opt_dqp0.cmplx_strength                   = 4;
+        reg->subj_opt_dqp0.cmplx_thre_qp                    = 34;
+        reg->subj_opt_dqp0.cmplx_thre_max_grdn_blk          = 32;
+    }
+}
+
+static void vepu510_h265_set_anti_blur_regs(H265eVepu510Sqi *reg_sqi, int anti_blur_level)
+{
+    H265eVepu510Sqi *reg = reg_sqi;
+    if (anti_blur_level >= 1)
+        reg->subj_anti_blur_thd.anti_blur_en = 1;
+    else
+        reg->subj_anti_blur_thd.anti_blur_en = 0;
+    reg->subj_anti_blur_thd.blur_low_madi_thd = 5;
+    reg->subj_anti_blur_thd.blur_high_madi_thd = 27;
+    reg->subj_anti_blur_thd.blur_low_cnt_thd = 0;
+    reg->subj_anti_blur_thd.blur_hight_cnt_thd = 0;
+    reg->subj_anti_blur_thd.blur_sum_cnt_thd = 5;
+
+    reg->subj_anti_blur_sao.blur_motion_thd = 32;
+    reg->subj_anti_blur_sao.sao_ofst_thd_eo_luma = 2;
+    reg->subj_anti_blur_sao.sao_ofst_thd_bo_luma = 4;
+    reg->subj_anti_blur_sao.sao_ofst_thd_eo_chroma = 2;
+    reg->subj_anti_blur_sao.sao_ofst_thd_bo_chroma = 4;
+}
+
+static void vepu510_h265_set_anti_stripe_regs(H265eVepu510Sqi *reg_sqi, int atl_level)
+{
+    pre_cst_par* pre_i32 = (pre_cst_par*)&reg_sqi->preintra32_cst;
+    pre_cst_par* pre_i16 = (pre_cst_par*)&reg_sqi->preintra16_cst;
+
+    pre_i32->cst_madi_thd0.madi_thd0 = 5;
+    pre_i32->cst_madi_thd0.madi_thd1 = 15;
+    pre_i32->cst_madi_thd0.madi_thd2 = 5;
+    pre_i32->cst_madi_thd0.madi_thd3 = 3;
+    pre_i32->cst_madi_thd1.madi_thd4 = 3;
+    pre_i32->cst_madi_thd1.madi_thd5 = 6;
+    pre_i32->cst_madi_thd1.madi_thd6 = 7;
+    pre_i32->cst_madi_thd1.madi_thd7 = 5;
+    pre_i32->cst_madi_thd2.madi_thd8 = 10;
+    pre_i32->cst_madi_thd2.madi_thd9 = 5;
+    pre_i32->cst_madi_thd2.madi_thd10 = 7;
+    pre_i32->cst_madi_thd2.madi_thd11 = 5;
+    pre_i32->cst_madi_thd3.madi_thd12 = 7;
+    pre_i32->cst_madi_thd3.madi_thd13 = 5;
+    pre_i32->cst_madi_thd3.mode_th = 5;
+
+    pre_i32->cst_wgt0.wgt0 = 20;
+    pre_i32->cst_wgt0.wgt1 = 18;
+    pre_i32->cst_wgt0.wgt2 = 19;
+    pre_i32->cst_wgt0.wgt3 = 18;
+    pre_i32->cst_wgt1.wgt4 = 12;
+    pre_i32->cst_wgt1.wgt5 = 6;
+    pre_i32->cst_wgt1.wgt6 = 13;
+    pre_i32->cst_wgt1.wgt7 = 9;
+    pre_i32->cst_wgt2.wgt8 = 12;
+    pre_i32->cst_wgt2.wgt9 = 6;
+    pre_i32->cst_wgt2.wgt10 = 13;
+    pre_i32->cst_wgt2.wgt11 = 9;
+    pre_i32->cst_wgt3.wgt12 = 18;
+    pre_i32->cst_wgt3.wgt13 = 17;
+    pre_i32->cst_wgt3.wgt14 = 17;
+
+    pre_i16->cst_madi_thd0.madi_thd0 = 5;
+    pre_i16->cst_madi_thd0.madi_thd1 = 15;
+    pre_i16->cst_madi_thd0.madi_thd2 = 5;
+    pre_i16->cst_madi_thd0.madi_thd3 = 3;
+    pre_i16->cst_madi_thd1.madi_thd4 = 3;
+    pre_i16->cst_madi_thd1.madi_thd5 = 6;
+    pre_i16->cst_madi_thd1.madi_thd6 = 7;
+    pre_i16->cst_madi_thd1.madi_thd7 = 5;
+    pre_i16->cst_madi_thd2.madi_thd8 = 10;
+    pre_i16->cst_madi_thd2.madi_thd9 = 5;
+    pre_i16->cst_madi_thd2.madi_thd10 = 7;
+    pre_i16->cst_madi_thd2.madi_thd11 = 5;
+    pre_i16->cst_madi_thd3.madi_thd12 = 7;
+    pre_i16->cst_madi_thd3.madi_thd13 = 5;
+    pre_i16->cst_madi_thd3.mode_th = 5;
+
+    pre_i16->cst_wgt0.wgt0 = 20;
+    pre_i16->cst_wgt0.wgt1 = 18;
+    pre_i16->cst_wgt0.wgt2 = 19;
+    pre_i16->cst_wgt0.wgt3 = 18;
+    pre_i16->cst_wgt1.wgt4 = 12;
+    pre_i16->cst_wgt1.wgt5 = 6;
+    pre_i16->cst_wgt1.wgt6 = 13;
+    pre_i16->cst_wgt1.wgt7 = 9;
+    pre_i16->cst_wgt2.wgt8 = 12;
+    pre_i16->cst_wgt2.wgt9 = 6;
+    pre_i16->cst_wgt2.wgt10 = 13;
+    pre_i16->cst_wgt2.wgt11 = 9;
+    pre_i16->cst_wgt3.wgt12 = 18;
+    pre_i16->cst_wgt3.wgt13 = 17;
+    pre_i16->cst_wgt3.wgt14 = 17;
+
+    pre_i32->cst_madi_thd3.qp_thd = 28;
+    pre_i32->cst_wgt3.lambda_mv_bit_0 = 5; // lv32
+    pre_i32->cst_wgt3.lambda_mv_bit_1 = 4; // lv16
+    pre_i16->cst_wgt3.lambda_mv_bit_0 = 4; // lv8
+    pre_i16->cst_wgt3.lambda_mv_bit_1 = 3; // lv4
+    if (atl_level >= 1)
+        pre_i32->cst_wgt3.anti_strp_e = 1;
+    else
+        pre_i32->cst_wgt3.anti_strp_e = 0;
+}
+
+static void vepu510_h265_rdo_cfg(H265eV510HalContext *ctx, H265eVepu510Sqi *reg, MppEncSceneMode sm)
+{
+    reg->subj_opt_cfg.subj_opt_en               = 1;
+    reg->subj_opt_cfg.subj_opt_strength         = 3;
+    reg->subj_opt_cfg.aq_subj_en                = (sm == MPP_ENC_SCENE_MODE_IPC);
+    reg->subj_opt_cfg.aq_subj_strength          = 4;
+
+    /* skin_opt */
+    reg->skin_opt_cfg.skin_en                       = 0;
+    reg->skin_opt_cfg.skin_strength                 = 3;
+    reg->skin_opt_cfg.thre_uvsqr16_skin             = 128;
+    reg->skin_opt_cfg.skin_thre_cst_best_mad        = 1000;
+    reg->skin_opt_cfg.skin_thre_cst_best_grdn_blk   = 98;
+    reg->skin_opt_cfg.frame_skin_ratio              = 3;
+    reg->skin_chrm_thd.thre_sum_mad_intra           = 3;
+    reg->skin_chrm_thd.thre_sum_grdn_blk_intra      = 3;
+    reg->skin_chrm_thd.vld_thre_skin_v              = 7;
+    reg->skin_chrm_thd.thre_min_skin_u              = 107;
+    reg->skin_chrm_thd.thre_max_skin_u              = 129;
+    reg->skin_chrm_thd.thre_min_skin_v              = 135;
+    reg->subj_opt_dqp1.skin_thre_qp                 = 31;
+
+    /* 0x00002100 reg2112 */
+    reg->cudecis_thd0.base_thre_rough_mad32_intra           = 9;
+    reg->cudecis_thd0.delta0_thre_rough_mad32_intra         = 10;
+    reg->cudecis_thd0.delta1_thre_rough_mad32_intra         = 55;
+    reg->cudecis_thd0.delta2_thre_rough_mad32_intra         = 55;
+    reg->cudecis_thd0.delta3_thre_rough_mad32_intra         = 66;
+    reg->cudecis_thd0.delta4_thre_rough_mad32_intra_low5    = 2;
+
+    /* 0x00002104 reg2113 */
+    reg->cudecis_thd1.delta4_thre_rough_mad32_intra_high2   = 2;
+    reg->cudecis_thd1.delta5_thre_rough_mad32_intra         = 74;
+    reg->cudecis_thd1.delta6_thre_rough_mad32_intra         = 106;
+    reg->cudecis_thd1.base_thre_fine_mad32_intra            = 8;
+    reg->cudecis_thd1.delta0_thre_fine_mad32_intra          = 0;
+    reg->cudecis_thd1.delta1_thre_fine_mad32_intra          = 13;
+    reg->cudecis_thd1.delta2_thre_fine_mad32_intra_low3     = 6;
+
+    /* 0x00002108 reg2114 */
+    reg->cudecis_thd2.delta2_thre_fine_mad32_intra_high2    = 1;
+    reg->cudecis_thd2.delta3_thre_fine_mad32_intra          = 17;
+    reg->cudecis_thd2.delta4_thre_fine_mad32_intra          = 23;
+    reg->cudecis_thd2.delta5_thre_fine_mad32_intra          = 50;
+    reg->cudecis_thd2.delta6_thre_fine_mad32_intra          = 54;
+    reg->cudecis_thd2.base_thre_str_edge_mad32_intra        = 6;
+    reg->cudecis_thd2.delta0_thre_str_edge_mad32_intra      = 0;
+    reg->cudecis_thd2.delta1_thre_str_edge_mad32_intra      = 0;
+
+    /* 0x0000210c reg2115 */
+    reg->cudecis_thd3.delta2_thre_str_edge_mad32_intra      = 3;
+    reg->cudecis_thd3.delta3_thre_str_edge_mad32_intra      = 8;
+    reg->cudecis_thd3.base_thre_str_edge_bgrad32_intra      = 25;
+    reg->cudecis_thd3.delta0_thre_str_edge_bgrad32_intra    = 0;
+    reg->cudecis_thd3.delta1_thre_str_edge_bgrad32_intra    = 0;
+    reg->cudecis_thd3.delta2_thre_str_edge_bgrad32_intra    = 7;
+    reg->cudecis_thd3.delta3_thre_str_edge_bgrad32_intra    = 19;
+    reg->cudecis_thd3.base_thre_mad16_intra                 = 6;
+    reg->cudecis_thd3.delta0_thre_mad16_intra               = 0;
+
+    /* 0x00002110 reg2116 */
+    reg->cudecis_thd4.delta1_thre_mad16_intra          = 3;
+    reg->cudecis_thd4.delta2_thre_mad16_intra          = 3;
+    reg->cudecis_thd4.delta3_thre_mad16_intra          = 24;
+    reg->cudecis_thd4.delta4_thre_mad16_intra          = 28;
+    reg->cudecis_thd4.delta5_thre_mad16_intra          = 40;
+    reg->cudecis_thd4.delta6_thre_mad16_intra          = 52;
+    reg->cudecis_thd4.delta0_thre_mad16_ratio_intra    = 7;
+
+    /* 0x00002114 reg2117 */
+    reg->cudecis_thd5.delta1_thre_mad16_ratio_intra           =  7;
+    reg->cudecis_thd5.delta2_thre_mad16_ratio_intra           =  2;
+    reg->cudecis_thd5.delta3_thre_mad16_ratio_intra           =  2;
+    reg->cudecis_thd5.delta4_thre_mad16_ratio_intra           =  0;
+    reg->cudecis_thd5.delta5_thre_mad16_ratio_intra           =  0;
+    reg->cudecis_thd5.delta6_thre_mad16_ratio_intra           =  0;
+    reg->cudecis_thd5.delta7_thre_mad16_ratio_intra           =  4;
+    reg->cudecis_thd5.delta0_thre_rough_bgrad32_intra         =  1;
+    reg->cudecis_thd5.delta1_thre_rough_bgrad32_intra         =  5;
+    reg->cudecis_thd5.delta2_thre_rough_bgrad32_intra_low4    =  8;
+
+    /* 0x00002118 reg2118 */
+    reg->cudecis_thd6.delta2_thre_rough_bgrad32_intra_high2    = 2;
+    reg->cudecis_thd6.delta3_thre_rough_bgrad32_intra          = 540;
+    reg->cudecis_thd6.delta4_thre_rough_bgrad32_intra          = 692;
+    reg->cudecis_thd6.delta5_thre_rough_bgrad32_intra_low10    = 866;
+
+    /* 0x0000211c reg2119 */
+    reg->cudecis_thd7.delta5_thre_rough_bgrad32_intra_high1   = 1;
+    reg->cudecis_thd7.delta6_thre_rough_bgrad32_intra         = 3286;
+    reg->cudecis_thd7.delta7_thre_rough_bgrad32_intra         = 6620;
+    reg->cudecis_thd7.delta0_thre_bgrad16_ratio_intra         = 8;
+    reg->cudecis_thd7.delta1_thre_bgrad16_ratio_intra_low2    = 3;
+
+    /* 0x00002120 reg2120 */
+    reg->cudecis_thdt8.delta1_thre_bgrad16_ratio_intra_high2    = 2;
+    reg->cudecis_thdt8.delta2_thre_bgrad16_ratio_intra          = 15;
+    reg->cudecis_thdt8.delta3_thre_bgrad16_ratio_intra          = 15;
+    reg->cudecis_thdt8.delta4_thre_bgrad16_ratio_intra          = 13;
+    reg->cudecis_thdt8.delta5_thre_bgrad16_ratio_intra          = 13;
+    reg->cudecis_thdt8.delta6_thre_bgrad16_ratio_intra          = 7;
+    reg->cudecis_thdt8.delta7_thre_bgrad16_ratio_intra          = 15;
+    reg->cudecis_thdt8.delta0_thre_fme_ratio_inter              = 4;
+    reg->cudecis_thdt8.delta1_thre_fme_ratio_inter              = 4;
+
+    /* 0x00002124 reg2121 */
+    reg->cudecis_thd9.delta2_thre_fme_ratio_inter    = 3;
+    reg->cudecis_thd9.delta3_thre_fme_ratio_inter    = 2;
+    reg->cudecis_thd9.delta4_thre_fme_ratio_inter    = 0;
+    reg->cudecis_thd9.delta5_thre_fme_ratio_inter    = 0;
+    reg->cudecis_thd9.delta6_thre_fme_ratio_inter    = 0;
+    reg->cudecis_thd9.delta7_thre_fme_ratio_inter    = 0;
+    reg->cudecis_thd9.base_thre_fme32_inter          = 4;
+    reg->cudecis_thd9.delta0_thre_fme32_inter        = 2;
+    reg->cudecis_thd9.delta1_thre_fme32_inter        = 7;
+    reg->cudecis_thd9.delta2_thre_fme32_inter        = 12;
+
+    /* 0x00002128 reg2122 */
+    reg->cudecis_thd10.delta3_thre_fme32_inter    = 23;
+    reg->cudecis_thd10.delta4_thre_fme32_inter    = 41;
+    reg->cudecis_thd10.delta5_thre_fme32_inter    = 71;
+    reg->cudecis_thd10.delta6_thre_fme32_inter    = 123;
+    reg->cudecis_thd10.thre_cme32_inter           = 48;
+
+    /* 0x0000212c reg2123 */
+    reg->cudecis_thd11.delta0_thre_mad_fme_ratio_inter    = 0;
+    reg->cudecis_thd11.delta1_thre_mad_fme_ratio_inter    = 7;
+    reg->cudecis_thd11.delta2_thre_mad_fme_ratio_inter    = 7;
+    reg->cudecis_thd11.delta3_thre_mad_fme_ratio_inter    = 6;
+    reg->cudecis_thd11.delta4_thre_mad_fme_ratio_inter    = 5;
+    reg->cudecis_thd11.delta5_thre_mad_fme_ratio_inter    = 4;
+    reg->cudecis_thd11.delta6_thre_mad_fme_ratio_inter    = 4;
+    reg->cudecis_thd11.delta7_thre_mad_fme_ratio_inter    = 4;
+
+    vepu510_h265_set_anti_stripe_regs(reg, ctx->cfg->tune.atl_str);
+    if (ctx->frame_type == INTRA_FRAME)
+        vepu510_h265_set_atr_regs(reg, sm, ctx->cfg->tune.atr_str_i);
+    else
+        vepu510_h265_set_atr_regs(reg, sm, ctx->cfg->tune.atr_str_p);
+
+    if (ctx->frame_type == INTRA_FRAME)
+        vepu510_h265_set_anti_blur_regs(reg, ctx->cfg->tune.sao_str_i);
+    else
+        vepu510_h265_set_anti_blur_regs(reg, ctx->cfg->tune.sao_str_p);
+}
+
+static void vepu510_h265_atf_cfg(H265eVepu510Sqi *reg, RK_S32 atf_str)
+{
+    rdo_skip_par   *p_rdo_skip   = NULL;
+    rdo_noskip_par *p_rdo_noskip = NULL;
+
+    p_rdo_skip = &reg->rdo_b32_skip;
+    p_rdo_skip->atf_thd0.madp_thd0 = 5  ;
+    p_rdo_skip->atf_thd0.madp_thd1 = 10 ;
+    p_rdo_skip->atf_thd1.madp_thd2 = atf_b32_skip_thd2[atf_str];
+    p_rdo_skip->atf_thd1.madp_thd3 = atf_b32_skip_thd3[atf_str];
+    p_rdo_skip->atf_wgt0.wgt0 =      atf_b32_skip_wgt0[atf_str];
+    p_rdo_skip->atf_wgt0.wgt1 =      16 ;
+    p_rdo_skip->atf_wgt0.wgt2 =      16 ;
+    p_rdo_skip->atf_wgt0.wgt3 =      atf_b32_skip_wgt3[atf_str];
+
+    p_rdo_noskip = &reg->rdo_b32_inter;
+    p_rdo_noskip->ratf_thd0.madp_thd0 = 20;
+    p_rdo_noskip->ratf_thd0.madp_thd1 = 40;
+    p_rdo_noskip->ratf_thd1.madp_thd2 = 72;
+    p_rdo_noskip->atf_wgt.wgt0 =        16;
+    p_rdo_noskip->atf_wgt.wgt1 =        16;
+    p_rdo_noskip->atf_wgt.wgt2 =        16;
+
+    p_rdo_noskip = &reg->rdo_b32_intra;
+    p_rdo_noskip->ratf_thd0.madp_thd0 = atf_b32_intra_thd0[atf_str];
+    p_rdo_noskip->ratf_thd0.madp_thd1 = atf_b32_intra_thd1[atf_str];
+    p_rdo_noskip->ratf_thd1.madp_thd2 = atf_b32_intra_thd2[atf_str];
+    p_rdo_noskip->atf_wgt.wgt0 =        atf_b32_intra_wgt0[atf_str];
+    p_rdo_noskip->atf_wgt.wgt1 =        atf_b32_intra_wgt1[atf_str];
+    p_rdo_noskip->atf_wgt.wgt2 =        atf_b32_intra_wgt2[atf_str];
+
+    p_rdo_skip = &reg->rdo_b16_skip;
+    p_rdo_skip->atf_thd0.madp_thd0 = 1  ;
+    p_rdo_skip->atf_thd0.madp_thd1 = 10 ;
+    p_rdo_skip->atf_thd1.madp_thd2 = atf_b16_skip_thd2[atf_str];
+    p_rdo_skip->atf_thd1.madp_thd3 = atf_b16_skip_thd3[atf_str];
+    p_rdo_skip->atf_wgt0.wgt0 =      atf_b16_skip_wgt0[atf_str];
+    p_rdo_skip->atf_wgt0.wgt1 =      16 ;
+    p_rdo_skip->atf_wgt0.wgt2 =      16 ;
+    p_rdo_skip->atf_wgt0.wgt3 =      atf_b16_skip_wgt3[atf_str];
+    p_rdo_skip->atf_wgt1.wgt4 =      16 ;
+
+    p_rdo_noskip = &reg->rdo_b16_inter;
+    p_rdo_noskip->ratf_thd0.madp_thd0 = 20;
+    p_rdo_noskip->ratf_thd0.madp_thd1 = 40;
+    p_rdo_noskip->ratf_thd1.madp_thd2 = 72;
+    p_rdo_noskip->atf_wgt.wgt0 =        16;
+    p_rdo_noskip->atf_wgt.wgt1 =        16;
+    p_rdo_noskip->atf_wgt.wgt2 =        16;
+    p_rdo_noskip->atf_wgt.wgt3 =        16;
+
+    p_rdo_noskip = &reg->rdo_b16_intra;
+    p_rdo_noskip->ratf_thd0.madp_thd0 = atf_b16_intra_thd0[atf_str];
+    p_rdo_noskip->ratf_thd0.madp_thd1 = atf_b16_intra_thd1[atf_str];
+    p_rdo_noskip->ratf_thd1.madp_thd2 = atf_b16_intra_thd2[atf_str];
+    p_rdo_noskip->atf_wgt.wgt0 =        atf_b16_intra_wgt0[atf_str];
+    p_rdo_noskip->atf_wgt.wgt1 =        atf_b16_intra_wgt1[atf_str];
+    p_rdo_noskip->atf_wgt.wgt2 =        atf_b16_intra_wgt2[atf_str];
+    p_rdo_noskip->atf_wgt.wgt3 =        16;
+}
+
+static void vepu510_h265_smear_cfg(H265eVepu510Sqi *reg, H265eV510HalContext *ctx)
+{
+    RK_S32 frame_num = ctx->frame_num;
+    RK_S32 frame_keyint = ctx->cfg->rc.gop;
+    RK_U32 cover_num = ctx->feedback.acc_cover16_num;
+    RK_U32 bndry_num = ctx->feedback.acc_bndry16_num;
+    RK_U32 st_ctu_num = ctx->feedback.st_ctu_num;
+    RK_S32 deblur_en = ctx->cfg->tune.deblur_en;
+    RK_S32 deblur_str = ctx->cfg->tune.deblur_str;
+    RK_S16 flag_cover = 0;
+    RK_S16 flag_bndry = 0;
+
+    if (cover_num * 1000 < smear_flag_cover_thd0[deblur_str] * st_ctu_num)
+        flag_cover = 0;
+    else if (cover_num * 1000 < smear_flag_cover_thd1[deblur_str] * st_ctu_num)
+        flag_cover = 1;
+    else
+        flag_cover = 2;
+
+    if (bndry_num * 1000 < smear_flag_bndry_thd0[deblur_str] * st_ctu_num)
+        flag_bndry = 0;
+    else if (bndry_num * 1000 < smear_flag_bndry_thd1[deblur_str] * st_ctu_num)
+        flag_bndry = 1;
+    else
+        flag_bndry = 2;
+
+    reg->subj_opt_dpth_thd.common_thre_num_grdn_point_dep0      = 64;
+    reg->subj_opt_dpth_thd.common_thre_num_grdn_point_dep1      = 32;
+    reg->subj_opt_dpth_thd.common_thre_num_grdn_point_dep2      = 16;
+    reg->subj_opt_inrar_coef.common_rdo_cu_intra_r_coef_dep0    = smear_common_intra_r_dep0[deblur_str] + smear_flag_cover_intra_wgt0[flag_bndry];
+    reg->subj_opt_inrar_coef.common_rdo_cu_intra_r_coef_dep1    = smear_common_intra_r_dep1[deblur_str] + smear_flag_cover_intra_wgt1[flag_bndry];
+
+    /* anti smear */
+    reg->smear_opt_cfg0.anti_smear_en               = 1;
+    if (deblur_en == 0)
+        reg->smear_opt_cfg0.anti_smear_en           = 0;
+    reg->smear_opt_cfg0.smear_strength              = smear_strength[deblur_str] + smear_flag_bndry_wgt[deblur_en];
+    reg->smear_opt_cfg0.thre_mv_inconfor_cime       = 8;
+    reg->smear_opt_cfg0.thre_mv_confor_cime         = 2;
+    reg->smear_opt_cfg0.thre_mv_inconfor_cime_gmv   = 8;
+    reg->smear_opt_cfg0.thre_mv_confor_cime_gmv     = 2;
+    reg->smear_opt_cfg0.thre_num_mv_confor_cime     = 3;
+    reg->smear_opt_cfg0.thre_num_mv_confor_cime_gmv = 2;
+    reg->smear_opt_cfg0.frm_static                  = 1;
+
+    if (((frame_num) % frame_keyint == 0) || reg->smear_opt_cfg0.frm_static == 0 || (frame_num) % frame_keyint == 1) {
+        reg->smear_opt_cfg0.smear_load_en = 0;
+    } else {
+        reg->smear_opt_cfg0.smear_load_en = 1;
+    }
+
+    if (((frame_num) % frame_keyint == 0) || reg->smear_opt_cfg0.frm_static == 0 || (frame_num) % frame_keyint == frame_keyint - 1) {
+        reg->smear_opt_cfg0.smear_stor_en = 0;
+    } else {
+        reg->smear_opt_cfg0.smear_stor_en = 1;
+    }
+
+    reg->smear_opt_cfg1.dist0_frm_avg               = 0;
+    reg->smear_opt_cfg1.thre_dsp_static             = 10;
+    reg->smear_opt_cfg1.thre_dsp_mov                = 15;
+    reg->smear_opt_cfg1.thre_dist_mv_confor_cime    = 32;
+
+    reg->smear_madp_thd.thre_madp_stc_dep0          = 10;
+    reg->smear_madp_thd.thre_madp_stc_dep1          = 8;
+    reg->smear_madp_thd.thre_madp_stc_dep2          = 8;
+    reg->smear_madp_thd.thre_madp_mov_dep0          = 16;
+    reg->smear_madp_thd.thre_madp_mov_dep1          = 18;
+    reg->smear_madp_thd.thre_madp_mov_dep2          = 20;
+
+    reg->smear_stat_thd.thre_num_pt_stc_dep0        = 47;
+    reg->smear_stat_thd.thre_num_pt_stc_dep1        = 11;
+    reg->smear_stat_thd.thre_num_pt_stc_dep2        = 3;
+    reg->smear_stat_thd.thre_num_pt_mov_dep0        = 47;
+    reg->smear_stat_thd.thre_num_pt_mov_dep1        = 11;
+    reg->smear_stat_thd.thre_num_pt_mov_dep2        = 3;
+
+    reg->smear_bmv_dist_thd0.thre_ratio_dist_mv_confor_cime_gmv0      = 21;
+    reg->smear_bmv_dist_thd0.thre_ratio_dist_mv_confor_cime_gmv1      = 16;
+    reg->smear_bmv_dist_thd0.thre_ratio_dist_mv_inconfor_cime_gmv0    = 48;
+    reg->smear_bmv_dist_thd0.thre_ratio_dist_mv_inconfor_cime_gmv1    = 34;
+
+    reg->smear_bmv_dist_thd1.thre_ratio_dist_mv_inconfor_cime_gmv2    = 32;
+    reg->smear_bmv_dist_thd1.thre_ratio_dist_mv_inconfor_cime_gmv3    = 29;
+    reg->smear_bmv_dist_thd1.thre_ratio_dist_mv_inconfor_cime_gmv4    = 27;
+
+    reg->smear_min_bndry_gmv.thre_min_num_confor_csu0_bndry_cime_gmv      = 0;
+    reg->smear_min_bndry_gmv.thre_max_num_confor_csu0_bndry_cime_gmv      = 3;
+    reg->smear_min_bndry_gmv.thre_min_num_inconfor_csu0_bndry_cime_gmv    = 0;
+    reg->smear_min_bndry_gmv.thre_max_num_inconfor_csu0_bndry_cime_gmv    = 3;
+    reg->smear_min_bndry_gmv.thre_split_dep0                              = 2;
+    reg->smear_min_bndry_gmv.thre_zero_srgn                               = 8;
+    reg->smear_min_bndry_gmv.madi_thre_dep0                               = 22;
+    reg->smear_min_bndry_gmv.madi_thre_dep1                               = 18;
+
+    reg->smear_madp_cov_thd.thre_madp_stc_cover0    = smear_thre_madp_stc_cover0[deblur_str];
+    reg->smear_madp_cov_thd.thre_madp_stc_cover1    = smear_thre_madp_stc_cover1[deblur_str];
+    reg->smear_madp_cov_thd.thre_madp_mov_cover0    = smear_thre_madp_mov_cover0[deblur_str];
+    reg->smear_madp_cov_thd.thre_madp_mov_cover1    = smear_thre_madp_mov_cover1[deblur_str];
+    reg->smear_madp_cov_thd.smear_qp_strength       = smear_qp_strength[deblur_str] + smear_flag_cover_wgt[flag_cover];
+    reg->smear_madp_cov_thd.smear_thre_qp           = 30;
+
+    reg->subj_opt_dqp1.bndry_rdo_cu_intra_r_coef_dep0   = smear_bndry_intra_r_dep0[deblur_str] + smear_flag_bndry_intra_wgt0[flag_bndry];
+    reg->subj_opt_dqp1.bndry_rdo_cu_intra_r_coef_dep1   = smear_bndry_intra_r_dep1[deblur_str] + smear_flag_bndry_intra_wgt1[flag_bndry];
+}
+
+static void vepu510_h265_global_cfg_set(H265eV510HalContext *ctx, H265eV510RegSet *regs)
+{
+    MppEncHwCfg *hw = &ctx->cfg->hw;
+    H265eVepu510Param *reg_param = &regs->reg_param;
+    H265eVepu510Sqi  *reg_sqi = &regs->reg_sqi;
+    MppEncSceneMode sm = ctx->cfg->tune.scene_mode;
+    RK_S32 atf_str = ctx->cfg->tune.anti_flicker_str;
+    RK_S32 lambda_idx = 0;
+
+    vepu510_h265_rdo_cfg(ctx, reg_sqi, sm);
+    vepu510_h265_atf_cfg(reg_sqi, atf_str);
+    vepu510_h265_smear_cfg(reg_sqi, ctx);
+    memcpy(&reg_param->pprd_lamb_satd_0_51[0], lamd_satd_qp_510, sizeof(lamd_satd_qp));
+
+    if (ctx->frame_type == INTRA_FRAME) {
+        reg_param->iprd_lamb_satd_ofst.lambda_satd_offset = 11;
+        lambda_idx = ctx->cfg->tune.lambda_idx_i;
+        memcpy(&reg_param->rdo_wgta_qp_grpa_0_51[0],
+               &rdo_lambda_table_I[lambda_idx], H265E_LAMBDA_TAB_SIZE);
+    } else {
+        reg_param->iprd_lamb_satd_ofst.lambda_satd_offset = 11;
+        lambda_idx = ctx->cfg->tune.lambda_idx_p;
+        memcpy(&reg_param->rdo_wgta_qp_grpa_0_51[0],
+               &rdo_lambda_table_P[lambda_idx], H265E_LAMBDA_TAB_SIZE);
+    }
+
+    reg_param->qnt_bias_comb.qnt_f_bias_i = 171;
+    reg_param->qnt_bias_comb.qnt_f_bias_p = 85;
+    if (hw->qbias_en) {
+        reg_param->qnt_bias_comb.qnt_f_bias_i = hw->qbias_i;
+        reg_param->qnt_bias_comb.qnt_f_bias_p = hw->qbias_p;
+    } else if (ctx->smart_en) {
+        reg_param->qnt_bias_comb.qnt_f_bias_i = 144;
+    }
+
+    /* CIME */
+    {
+        reg_param->me_sqi_comb.cime_pmv_num = 1;
+        reg_param->me_sqi_comb.cime_fuse   = 1;
+        reg_param->me_sqi_comb.itp_mode    = 1;
+        reg_param->me_sqi_comb.move_lambda = (sm == MPP_ENC_SCENE_MODE_IPC) ? 2 : 8;
+        reg_param->me_sqi_comb.rime_lvl_mrg     = 1;
+        reg_param->me_sqi_comb.rime_prelvl_en   = 3;
+        reg_param->me_sqi_comb.rime_prersu_en   = 0;
+        reg_param->cime_mvd_th_comb.cime_mvd_th0 = 8;
+        reg_param->cime_mvd_th_comb.cime_mvd_th1 = 20;
+        reg_param->cime_mvd_th_comb.cime_mvd_th2 = 32;
+        reg_param->cime_madp_th_comb.cime_madp_th = (sm == MPP_ENC_SCENE_MODE_IPC) ? 16 : 0;
+
+        if (sm == MPP_ENC_SCENE_MODE_IPC) {
+            reg_param->cime_multi_comb.cime_multi0 = 8;
+            reg_param->cime_multi_comb.cime_multi1 = 12;
+            reg_param->cime_multi_comb.cime_multi2 = 16;
+            reg_param->cime_multi_comb.cime_multi3 = 20;
+        } else {
+            reg_param->cime_multi_comb.cime_multi0 = 4;
+            reg_param->cime_multi_comb.cime_multi1 = 4;
+            reg_param->cime_multi_comb.cime_multi2 = 4;
+            reg_param->cime_multi_comb.cime_multi3 = 4;
+        }
+    }
+
+    /* RIME && FME */
+    if (sm == MPP_ENC_SCENE_MODE_IPC) {
+        reg_param->rime_mvd_th_comb.rime_mvd_th0  = 1;
+        reg_param->rime_mvd_th_comb.rime_mvd_th1  = 2;
+        reg_param->rime_mvd_th_comb.fme_madp_th   = 0;
+        reg_param->rime_madp_th_comb.rime_madp_th0 = 8;
+        reg_param->rime_madp_th_comb.rime_madp_th1 = 16;
+        reg_param->rime_multi_comb.rime_multi0 = 4;
+        reg_param->rime_multi_comb.rime_multi1 = 8;
+        reg_param->rime_multi_comb.rime_multi2 = 12;
+    } else {
+        reg_param->rime_mvd_th_comb.rime_mvd_th0  = 0;
+        reg_param->rime_mvd_th_comb.rime_mvd_th1  = 0;
+        reg_param->rime_mvd_th_comb.fme_madp_th   = 30;
+        reg_param->rime_madp_th_comb.rime_madp_th0 = 0;
+        reg_param->rime_madp_th_comb.rime_madp_th1 = 0;
+        reg_param->rime_multi_comb.rime_multi0 = 4;
+        reg_param->rime_multi_comb.rime_multi1 = 4;
+        reg_param->rime_multi_comb.rime_multi2 = 4;
+    }
+
+    {
+        /* 0x1064 */
+        regs->reg_rc_roi.madi_st_thd.madi_th0 = 5;
+        regs->reg_rc_roi.madi_st_thd.madi_th1 = 12;
+        regs->reg_rc_roi.madi_st_thd.madi_th2 = 20;
+        /* 0x1068 */
+        regs->reg_rc_roi.madp_st_thd0.madp_th0 = 4 << 4;
+        regs->reg_rc_roi.madp_st_thd0.madp_th1 = 9 << 4;
+        /* 0x106C */
+        regs->reg_rc_roi.madp_st_thd1.madp_th2 = 15 << 4;
+
+        /* 0x177C */
+        reg_param->cmv_st_th_comb.cmv_th0 = 64;
+        reg_param->cmv_st_th_comb.cmv_th1 = 96;
+        reg_param->cmv_st_th_comb.cmv_th2 = 128;
+    }
+}
+
+MPP_RET hal_h265e_v510_deinit(void *hal)
+{
+    H265eV510HalContext *ctx = (H265eV510HalContext *)hal;
+    RK_S32 i = 0;
+
+    hal_h265e_enter();
+    MPP_FREE(ctx->poll_cfgs);
+    MPP_FREE(ctx->input_fmt);
+    hal_bufs_deinit(ctx->dpb_bufs);
+
+    for (i = 0; i < ctx->task_cnt; i++) {
+        Vepu510H265eFrmCfg *frm = ctx->frms[i];
+
+        if (!frm)
+            continue;
+
+        if (frm->roir_buf) {
+            mpp_buffer_put(frm->roir_buf);
+            frm->roir_buf = NULL;
+            frm->roir_buf_size = 0;
+        }
+
+        MPP_FREE(frm->roi_base_cfg_sw_buf);
+
+        if (frm->reg_cfg) {
+            mpp_dev_multi_offset_deinit(frm->reg_cfg);
+            frm->reg_cfg = NULL;
+        }
+
+        MPP_FREE(frm->regs_set);
+        MPP_FREE(frm->regs_ret);
+        MPP_FREE(ctx->frms[i]);
+    }
+
+    clear_ext_line_bufs(ctx);
+
+    if (ctx->ext_line_buf_grp) {
+        mpp_buffer_group_put(ctx->ext_line_buf_grp);
+        ctx->ext_line_buf_grp = NULL;
+    }
+
+    if (ctx->buf_pass1) {
+        mpp_buffer_put(ctx->buf_pass1);
+        ctx->buf_pass1 = NULL;
+    }
+
+    if (ctx->dev) {
+        mpp_dev_deinit(ctx->dev);
+        ctx->dev = NULL;
+    }
+
+    if (ctx->reg_cfg) {
+        mpp_dev_multi_offset_deinit(ctx->reg_cfg);
+        ctx->reg_cfg = NULL;
+    }
+
+    if (ctx->roi_grp) {
+        mpp_buffer_group_put(ctx->roi_grp);
+        ctx->roi_grp = NULL;
+    }
+
+    if (ctx->tune) {
+        vepu510_h265e_tune_deinit(ctx->tune);
+        ctx->tune = NULL;
+    }
+
+    hal_h265e_leave();
+    return MPP_OK;
+}
+
+MPP_RET hal_h265e_v510_init(void *hal, MppEncHalCfg *cfg)
+{
+    MPP_RET ret = MPP_OK;
+    H265eV510HalContext *ctx = (H265eV510HalContext *)hal;
+    RK_S32 i = 0;
+
+    mpp_env_get_u32("hal_h265e_debug", &hal_h265e_debug, 0);
+    hal_h265e_enter();
+
+    ctx->task_cnt = cfg->task_cnt;
+    mpp_assert(ctx->task_cnt && ctx->task_cnt <= MAX_FRAME_TASK_NUM);
+    if (ctx->task_cnt > MAX_FRAME_TASK_NUM)
+        ctx->task_cnt = MAX_FRAME_TASK_NUM;
+
+    for (i = 0; i < ctx->task_cnt; i++) {
+        Vepu510H265eFrmCfg *frm_cfg = mpp_calloc(Vepu510H265eFrmCfg, 1);
+
+        frm_cfg->regs_set = mpp_calloc(H265eV510RegSet, 1);
+        frm_cfg->regs_ret = mpp_calloc(H265eV510StatusElem, 1);
+        frm_cfg->frame_type = INTRA_FRAME;
+        ctx->frms[i] = frm_cfg;
+    }
+
+    ctx->input_fmt      = mpp_calloc(VepuFmtCfg, 1);
+    ctx->cfg            = cfg->cfg;
+    hal_bufs_init(&ctx->dpb_bufs);
+
+    ctx->frame_count = -1;
+    ctx->frame_cnt_gen_ready = 0;
+    ctx->enc_mode = 1;
+    cfg->cap_recn_out = 1;
+    cfg->type = VPU_CLIENT_RKVENC;
+    ret = mpp_dev_init(&cfg->dev, cfg->type);
+    if (ret) {
+        mpp_err_f("mpp_dev_init failed. ret: %d\n", ret);
+        return ret;
+    }
+    mpp_dev_multi_offset_init(&ctx->reg_cfg, 24);
+    ctx->dev = cfg->dev;
+    ctx->frame_type = INTRA_FRAME;
+
+    {   /* setup default hardware config */
+        MppEncHwCfg *hw = &cfg->cfg->hw;
+        RK_U32 j;
+
+        hw->qp_delta_row_i  = 2;
+        hw->qp_delta_row    = 2;
+        hw->qbias_i         = 171;
+        hw->qbias_p         = 85;
+        hw->qbias_en        = 0;
+
+        for (j = 0; j < MPP_ARRAY_ELEMS(hw->mode_bias); j++)
+            hw->mode_bias[j] = 8;
+    }
+
+    ctx->poll_slice_max = 8;
+    ctx->poll_cfg_size = (sizeof(ctx->poll_cfgs) + sizeof(RK_S32) * ctx->poll_slice_max) * 2;
+    ctx->poll_cfgs = mpp_malloc_size(MppDevPollCfg, ctx->poll_cfg_size);
+
+    if (NULL == ctx->poll_cfgs) {
+        ret = MPP_ERR_MALLOC;
+        mpp_err_f("init poll cfg buffer failed\n");
+        goto DONE;
+    }
+
+    ctx->output_cb = cfg->output_cb;
+    cfg->cap_recn_out = 1;
+
+    ctx->tune = vepu510_h265e_tune_init(ctx);
+
+DONE:
+    if (ret)
+        hal_h265e_v510_deinit(hal);
+
+    hal_h265e_leave();
+    return ret;
+}
+
+static MPP_RET hal_h265e_vepu510_prepare(void *hal)
+{
+    H265eV510HalContext *ctx = (H265eV510HalContext *)hal;
+    MppEncPrepCfg *prep = &ctx->cfg->prep;
+
+    hal_h265e_dbg_func("enter %p\n", hal);
+
+    if (prep->change & (MPP_ENC_PREP_CFG_CHANGE_INPUT | MPP_ENC_PREP_CFG_CHANGE_FORMAT)) {
+        RK_S32 i;
+
+        // pre-alloc required buffers to reduce first frame delay
+        vepu510_h265_setup_hal_bufs(ctx);
+        for (i = 0; i < ctx->max_buf_cnt; i++)
+            hal_bufs_get_buf(ctx->dpb_bufs, i);
+
+        prep->change = 0;
+    }
+
+    hal_h265e_dbg_func("leave %p\n", hal);
+
+    return MPP_OK;
+}
+
+static MPP_RET
+vepu510_h265_set_patch_info(H265eSyntax_new *syn, Vepu541Fmt input_fmt,  MppDevRegOffCfgs *offsets, HalEncTask *task)
+{
+    RK_U32 hor_stride = syn->pp.hor_stride;
+    RK_U32 ver_stride = syn->pp.ver_stride ? syn->pp.ver_stride : syn->pp.pic_height;
+    RK_U32 frame_size = hor_stride * ver_stride;
+    RK_U32 u_offset = 0, v_offset = 0;
+    MPP_RET ret = MPP_OK;
+
+    if (MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(task->frame))) {
+        mpp_err("VEPU_510 unsupports FBC format input.\n");
+
+        ret = MPP_NOK;
+    } else {
+        switch (input_fmt) {
+        case VEPU541_FMT_YUV420P: {
+            u_offset = frame_size;
+            v_offset = frame_size * 5 / 4;
+        } break;
+        case VEPU541_FMT_YUV420SP:
+        case VEPU541_FMT_YUV422SP: {
+            u_offset = frame_size;
+            v_offset = frame_size;
+        } break;
+        case VEPU541_FMT_YUV422P: {
+            u_offset = frame_size;
+            v_offset = frame_size * 3 / 2;
+        } break;
+        case VEPU540_FMT_YUV400:
+        case VEPU541_FMT_YUYV422:
+        case VEPU541_FMT_UYVY422: {
+            u_offset = 0;
+            v_offset = 0;
+        } break;
+        case VEPU541_FMT_BGR565:
+        case VEPU541_FMT_BGR888:
+        case VEPU541_FMT_BGRA8888: {
+            u_offset = 0;
+            v_offset = 0;
+        } break;
+        case VEPU580_FMT_YUV444SP : {
+            u_offset = hor_stride * ver_stride;
+            v_offset = hor_stride * ver_stride;
+        } break;
+        case VEPU580_FMT_YUV444P : {
+            u_offset = hor_stride * ver_stride;
+            v_offset = hor_stride * ver_stride * 2;
+        } break;
+        default: {
+            hal_h265e_err("unknown color space: %d\n", input_fmt);
+            u_offset = frame_size;
+            v_offset = frame_size * 5 / 4;
+        }
+        }
+    }
+    mpp_dev_multi_offset_update(offsets, 161, u_offset);
+    mpp_dev_multi_offset_update(offsets, 162, v_offset);
+
+    return ret;
+}
+
+
+#if 0
+static MPP_RET vepu510_h265_set_roi_regs(H265eV510HalContext *ctx, H265eVepu510Frame *regs)
+{
+    /* memset register on start so do not clear registers again here */
+    if (ctx->roi_data) {
+        /* roi setup */
+        MppEncROICfg2 *cfg = ( MppEncROICfg2 *)ctx->roi_data;
+
+        regs->reg0192_enc_pic.roi_en = 1;
+        regs->reg0178_roi_addr = mpp_dev_get_iova_address(ctx->dev, cfg->base_cfg_buf, 0);
+        if (cfg->roi_qp_en) {
+            regs->reg0179_roi_qp_addr = mpp_dev_get_iova_address(ctx->dev, cfg->qp_cfg_buf, 0);
+            regs->reg0228_roi_en.roi_qp_en = 1;
+        }
+
+        if (cfg->roi_amv_en) {
+            regs->reg0180_roi_amv_addr = mpp_dev_get_iova_address(ctx->dev, cfg->amv_cfg_buf, 0);
+            regs->reg0228_roi_en.roi_amv_en = 1;
+        }
+
+        if (cfg->roi_mv_en) {
+            regs->reg0181_roi_mv_addr = mpp_dev_get_iova_address(ctx->dev, cfg->mv_cfg_buf, 0);
+            regs->reg0228_roi_en.roi_mv_en = 1;
+        }
+    }
+
+    return MPP_OK;
+}
+#endif
+
+static MPP_RET vepu510_h265_set_rc_regs(H265eV510HalContext *ctx, H265eV510RegSet *regs, HalEncTask *task)
+{
+    H265eSyntax_new *syn = ctx->syn;
+    EncRcTaskInfo *rc_cfg = &task->rc_task->info;
+    H265eVepu510Frame *reg_frm = &regs->reg_frm;
+    Vepu510RcRoi *reg_rc = &regs->reg_rc_roi;
+    MppEncCfgSet *cfg = ctx->cfg;
+    MppEncRcCfg *rc = &cfg->rc;
+    MppEncHwCfg *hw = &cfg->hw;
+    MppEncCodecCfg *codec = &cfg->codec;
+    MppEncH265Cfg *h265 = &codec->h265;
+    RK_S32 mb_wd32 = (syn->pp.pic_width + 31) / 32;
+    RK_S32 mb_h32 = (syn->pp.pic_height + 31) / 32;
+
+    RK_U32 ctu_target_bits_mul_16 = (rc_cfg->bit_target << 4) / (mb_wd32 * mb_h32);
+    RK_U32 ctu_target_bits;
+    RK_S32 negative_bits_thd, positive_bits_thd;
+
+    if (rc->rc_mode == MPP_ENC_RC_MODE_FIXQP) {
+        reg_frm->common.enc_pic.pic_qp    = rc_cfg->quality_target;
+        reg_frm->synt_sli1.sli_qp         = rc_cfg->quality_target;
+        reg_frm->common.rc_qp.rc_max_qp   = rc_cfg->quality_target;
+        reg_frm->common.rc_qp.rc_min_qp   = rc_cfg->quality_target;
+    } else {
+        if (ctu_target_bits_mul_16 >= 0x100000) {
+            ctu_target_bits_mul_16 = 0x50000;
+        }
+        ctu_target_bits = (ctu_target_bits_mul_16 * mb_wd32) >> 4;
+        negative_bits_thd = 0 - 5 * ctu_target_bits / 16;
+        positive_bits_thd = 5 * ctu_target_bits / 16;
+
+        reg_frm->common.enc_pic.pic_qp      = rc_cfg->quality_target;
+        reg_frm->synt_sli1.sli_qp           = rc_cfg->quality_target;
+        reg_frm->common.rc_cfg.rc_en        = 1;
+        reg_frm->common.rc_cfg.aq_en        = 1;
+        reg_frm->common.rc_cfg.rc_ctu_num   = mb_wd32;
+
+        reg_frm->common.rc_qp.rc_max_qp     = rc_cfg->quality_max;
+        reg_frm->common.rc_qp.rc_min_qp     = rc_cfg->quality_min;
+        reg_frm->common.rc_tgt.ctu_ebit     = ctu_target_bits_mul_16;
+
+        if (ctx->smart_en) {
+            reg_frm->common.rc_qp.rc_qp_range = 0;
+        } else {
+            reg_frm->common.rc_qp.rc_qp_range = (ctx->frame_type == INTRA_FRAME) ?
+                                                hw->qp_delta_row_i : hw->qp_delta_row;
+        }
+
+        {
+            /* fixed frame qp */
+            RK_S32 fqp_min, fqp_max;
+
+            if (ctx->frame_type == INTRA_FRAME) {
+                fqp_min = rc->fqp_min_i;
+                fqp_max = rc->fqp_max_i;
+            } else {
+                fqp_min = rc->fqp_min_p;
+                fqp_max = rc->fqp_max_p;
+            }
+
+            if ((fqp_min == fqp_max) && (fqp_min >= 0) && (fqp_max <= 51)) {
+                reg_frm->common.enc_pic.pic_qp = fqp_min;
+                reg_frm->synt_sli1.sli_qp  = fqp_min;
+                reg_frm->common.rc_qp.rc_qp_range = 0;
+            }
+        }
+
+        reg_rc->rc_dthd_0_8[0] = 2 * negative_bits_thd;
+        reg_rc->rc_dthd_0_8[1] = negative_bits_thd;
+        reg_rc->rc_dthd_0_8[2] = positive_bits_thd;
+        reg_rc->rc_dthd_0_8[3] = 2 * positive_bits_thd;
+        reg_rc->rc_dthd_0_8[4] = 0x7FFFFFFF;
+        reg_rc->rc_dthd_0_8[5] = 0x7FFFFFFF;
+        reg_rc->rc_dthd_0_8[6] = 0x7FFFFFFF;
+        reg_rc->rc_dthd_0_8[7] = 0x7FFFFFFF;
+        reg_rc->rc_dthd_0_8[8] = 0x7FFFFFFF;
+
+        reg_rc->rc_adj0.qp_adj0  = -2;
+        reg_rc->rc_adj0.qp_adj1  = -1;
+        reg_rc->rc_adj0.qp_adj2  = 0;
+        reg_rc->rc_adj0.qp_adj3  = 1;
+        reg_rc->rc_adj0.qp_adj4  = 2;
+        reg_rc->rc_adj1.qp_adj5  = 0;
+        reg_rc->rc_adj1.qp_adj6  = 0;
+        reg_rc->rc_adj1.qp_adj7  = 0;
+        reg_rc->rc_adj1.qp_adj8  = 0;
+    }
+
+    reg_rc->roi_qthd0.qpmin_area0 = h265->qpmin_map[0] > 0 ? h265->qpmin_map[0] : rc_cfg->quality_min;
+    reg_rc->roi_qthd0.qpmax_area0 = h265->qpmax_map[0] > 0 ? h265->qpmax_map[0] : rc_cfg->quality_max;
+    reg_rc->roi_qthd0.qpmin_area1 = h265->qpmin_map[1] > 0 ? h265->qpmin_map[1] : rc_cfg->quality_min;
+    reg_rc->roi_qthd0.qpmax_area1 = h265->qpmax_map[1] > 0 ? h265->qpmax_map[1] : rc_cfg->quality_max;
+    reg_rc->roi_qthd0.qpmin_area2 = h265->qpmin_map[2] > 0 ? h265->qpmin_map[2] : rc_cfg->quality_min;
+    reg_rc->roi_qthd1.qpmax_area2 = h265->qpmax_map[2] > 0 ? h265->qpmax_map[2] : rc_cfg->quality_max;
+    reg_rc->roi_qthd1.qpmin_area3 = h265->qpmin_map[3] > 0 ? h265->qpmin_map[3] : rc_cfg->quality_min;
+    reg_rc->roi_qthd1.qpmax_area3 = h265->qpmax_map[3] > 0 ? h265->qpmax_map[3] : rc_cfg->quality_max;
+    reg_rc->roi_qthd1.qpmin_area4 = h265->qpmin_map[4] > 0 ? h265->qpmin_map[4] : rc_cfg->quality_min;
+    reg_rc->roi_qthd1.qpmax_area4 = h265->qpmax_map[4] > 0 ? h265->qpmax_map[4] : rc_cfg->quality_max;
+    reg_rc->roi_qthd2.qpmin_area5 = h265->qpmin_map[5] > 0 ? h265->qpmin_map[5] : rc_cfg->quality_min;
+    reg_rc->roi_qthd2.qpmax_area5 = h265->qpmax_map[5] > 0 ? h265->qpmax_map[5] : rc_cfg->quality_max;
+    reg_rc->roi_qthd2.qpmin_area6 = h265->qpmin_map[6] > 0 ? h265->qpmin_map[6] : rc_cfg->quality_min;
+    reg_rc->roi_qthd2.qpmax_area6 = h265->qpmax_map[6] > 0 ? h265->qpmax_map[6] : rc_cfg->quality_max;
+    reg_rc->roi_qthd2.qpmin_area7 = h265->qpmin_map[7] > 0 ? h265->qpmin_map[7] : rc_cfg->quality_min;
+    reg_rc->roi_qthd3.qpmax_area7 = h265->qpmax_map[7] > 0 ? h265->qpmax_map[7] : rc_cfg->quality_max;
+    reg_rc->roi_qthd3.qpmap_mode  = h265->qpmap_mode;
+
+    return MPP_OK;
+}
+
+static MPP_RET vepu510_h265_set_pp_regs(H265eV510RegSet *regs, VepuFmtCfg *fmt, MppEncPrepCfg *prep_cfg)
+{
+    Vepu510ControlCfg *reg_ctl = &regs->reg_ctl;
+    H265eVepu510Frame        *reg_frm = &regs->reg_frm;
+    RK_S32 stridey = 0;
+    RK_S32 stridec = 0;
+
+    reg_ctl->dtrns_map.src_bus_edin = fmt->src_endian;
+    reg_frm->common.src_fmt.src_cfmt = fmt->format;
+    reg_frm->common.src_fmt.alpha_swap = fmt->alpha_swap;
+    reg_frm->common.src_fmt.rbuv_swap = fmt->rbuv_swap;
+
+    reg_frm->common.src_fmt.out_fmt = ((prep_cfg->format & MPP_FRAME_FMT_MASK) == MPP_FMT_YUV400) ? 0 : 1;
+
+    reg_frm->common.src_proc.src_mirr = prep_cfg->mirroring > 0;
+    reg_frm->common.src_proc.src_rot = prep_cfg->rotation;
+    reg_frm->common.src_proc.tile4x4_en = 0;
+
+    if (prep_cfg->hor_stride) {
+        if (MPP_FRAME_FMT_IS_TILE(prep_cfg->format)) {
+            reg_frm->common.src_proc.tile4x4_en = 1;
+
+            switch (prep_cfg->format & MPP_FRAME_FMT_MASK) {
+            case MPP_FMT_YUV400:
+                stridey = prep_cfg->hor_stride * 4;
+                break;
+            case MPP_FMT_YUV420P:
+            case MPP_FMT_YUV420SP:
+                stridey = prep_cfg->hor_stride * 4 * 3 / 2;
+                break;
+            case MPP_FMT_YUV422P:
+            case MPP_FMT_YUV422SP:
+                stridey = prep_cfg->hor_stride * 4 * 2;
+                break;
+            case MPP_FMT_YUV444P:
+            case MPP_FMT_YUV444SP:
+                stridey = prep_cfg->hor_stride * 4 * 3;
+                break;
+            default:
+                mpp_err("Unsupported input format 0x%08x, with TILE mask.\n", fmt);
+                return MPP_ERR_VALUE;
+                break;
+            }
+        } else {
+            stridey = prep_cfg->hor_stride;
+        }
+    } else {
+        if (reg_frm->common.src_fmt.src_cfmt == VEPU541_FMT_BGRA8888 )
+            stridey = prep_cfg->width * 4;
+        else if (reg_frm->common.src_fmt.src_cfmt == VEPU541_FMT_BGR888 )
+            stridey = prep_cfg->width * 3;
+        else if (reg_frm->common.src_fmt.src_cfmt == VEPU541_FMT_BGR565 ||
+                 reg_frm->common.src_fmt.src_cfmt == VEPU541_FMT_YUYV422 ||
+                 reg_frm->common.src_fmt.src_cfmt == VEPU541_FMT_UYVY422)
+            stridey = prep_cfg->width * 2;
+    }
+
+    stridec = (reg_frm->common.src_fmt.src_cfmt == VEPU541_FMT_YUV420SP ||
+               reg_frm->common.src_fmt.src_cfmt == VEPU541_FMT_YUV422SP ||
+               reg_frm->common.src_fmt.src_cfmt == VEPU580_FMT_YUV444P) ?
+              stridey : stridey / 2;
+
+    if (reg_frm->common.src_fmt.src_cfmt == VEPU580_FMT_YUV444SP)
+        stridec = stridey * 2;
+
+    if (reg_frm->common.src_fmt.src_cfmt < VEPU541_FMT_NONE) {
+        const VepuRgb2YuvCfg *cfg_coeffs = cfg_coeffs = get_rgb2yuv_cfg(prep_cfg->range, prep_cfg->color);
+
+        hal_h265e_dbg_simple("input color range %d colorspace %d", prep_cfg->range, prep_cfg->color);
+
+        reg_frm->common.src_udfy.csc_wgt_r2y = cfg_coeffs->_2y.r_coeff;
+        reg_frm->common.src_udfy.csc_wgt_g2y = cfg_coeffs->_2y.g_coeff;
+        reg_frm->common.src_udfy.csc_wgt_b2y = cfg_coeffs->_2y.b_coeff;
+
+        reg_frm->common.src_udfu.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff;
+        reg_frm->common.src_udfu.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff;
+        reg_frm->common.src_udfu.csc_wgt_b2u = cfg_coeffs->_2u.b_coeff;
+
+        reg_frm->common.src_udfv.csc_wgt_r2v = cfg_coeffs->_2v.r_coeff;
+        reg_frm->common.src_udfv.csc_wgt_g2v = cfg_coeffs->_2v.g_coeff;
+        reg_frm->common.src_udfv.csc_wgt_b2v = cfg_coeffs->_2v.b_coeff;
+
+        reg_frm->common.src_udfo.csc_ofst_y = cfg_coeffs->_2y.offset;
+        reg_frm->common.src_udfo.csc_ofst_u = cfg_coeffs->_2u.offset;
+        reg_frm->common.src_udfo.csc_ofst_v = cfg_coeffs->_2v.offset;
+
+        hal_h265e_dbg_simple("use color range %d colorspace %d", cfg_coeffs->dst_range, cfg_coeffs->color);
+    }
+
+    reg_frm->common.src_strd0.src_strd0  = stridey;
+    reg_frm->common.src_strd1.src_strd1  = stridec;
+
+    return MPP_OK;
+}
+
+static void vepu510_h265_set_slice_regs(H265eSyntax_new *syn, H265eVepu510Frame *regs)
+{
+    regs->synt_sps.smpl_adpt_ofst_e     = syn->pp.sample_adaptive_offset_enabled_flag;
+    regs->synt_sps.num_st_ref_pic       = syn->pp.num_short_term_ref_pic_sets;
+    regs->synt_sps.num_lt_ref_pic       = syn->pp.num_long_term_ref_pics_sps;
+    regs->synt_sps.lt_ref_pic_prsnt     = syn->pp.long_term_ref_pics_present_flag;
+    regs->synt_sps.tmpl_mvp_e           = syn->pp.sps_temporal_mvp_enabled_flag;
+    regs->synt_sps.log2_max_poc_lsb     = syn->pp.log2_max_pic_order_cnt_lsb_minus4;
+    regs->synt_sps.strg_intra_smth      = syn->pp.strong_intra_smoothing_enabled_flag;
+
+    regs->synt_pps.dpdnt_sli_seg_en     = syn->pp.dependent_slice_segments_enabled_flag;
+    regs->synt_pps.out_flg_prsnt_flg    = syn->pp.output_flag_present_flag;
+    regs->synt_pps.num_extr_sli_hdr     = syn->pp.num_extra_slice_header_bits;
+    regs->synt_pps.sgn_dat_hid_en       = syn->pp.sign_data_hiding_enabled_flag;
+    regs->synt_pps.cbc_init_prsnt_flg   = syn->pp.cabac_init_present_flag;
+    regs->synt_pps.pic_init_qp          = syn->pp.init_qp_minus26 + 26;
+    regs->synt_pps.cu_qp_dlt_en         = syn->pp.cu_qp_delta_enabled_flag;
+    regs->synt_pps.chrm_qp_ofst_prsn    = syn->pp.pps_slice_chroma_qp_offsets_present_flag;
+    regs->synt_pps.lp_fltr_acrs_sli     = syn->pp.pps_loop_filter_across_slices_enabled_flag;
+    regs->synt_pps.dblk_fltr_ovrd_en    = syn->pp.deblocking_filter_override_enabled_flag;
+    regs->synt_pps.lst_mdfy_prsnt_flg   = syn->pp.lists_modification_present_flag;
+    regs->synt_pps.sli_seg_hdr_extn     = syn->pp.slice_segment_header_extension_present_flag;
+    regs->synt_pps.cu_qp_dlt_depth      = syn->pp.diff_cu_qp_delta_depth;
+    regs->synt_pps.lpf_fltr_acrs_til    = syn->pp.loop_filter_across_tiles_enabled_flag;
+    regs->synt_pps.csip_flag            = syn->pp.constrained_intra_pred_flag;
+
+    regs->synt_sli0.cbc_init_flg        = syn->sp.cbc_init_flg;
+    regs->synt_sli0.mvd_l1_zero_flg     = syn->sp.mvd_l1_zero_flg;
+    regs->synt_sli0.ref_pic_lst_mdf_l0  = syn->sp.ref_pic_lst_mdf_l0;
+    regs->synt_sli0.num_refidx_l1_act   = syn->sp.num_refidx_l1_act;
+    regs->synt_sli0.num_refidx_l0_act   = syn->sp.num_refidx_l0_act;
+
+    regs->synt_sli0.num_refidx_act_ovrd = syn->sp.num_refidx_act_ovrd;
+
+    regs->synt_sli0.sli_sao_chrm_flg            = syn->sp.sli_sao_chrm_flg;
+    regs->synt_sli0.sli_sao_luma_flg            = syn->sp.sli_sao_luma_flg;
+    regs->synt_sli0.sli_tmprl_mvp_e             = syn->sp.sli_tmprl_mvp_en;
+    regs->common.enc_pic.num_pic_tot_cur_hevc   = syn->sp.tot_poc_num;
+
+    regs->synt_sli0.pic_out_flg         = syn->sp.pic_out_flg;
+    regs->synt_sli0.sli_type            = syn->sp.slice_type;
+    regs->synt_sli0.sli_rsrv_flg        = syn->sp.slice_rsrv_flg;
+    regs->synt_sli0.dpdnt_sli_seg_flg   = syn->sp.dpdnt_sli_seg_flg;
+    regs->synt_sli0.sli_pps_id          = syn->sp.sli_pps_id;
+    regs->synt_sli0.no_out_pri_pic      = syn->sp.no_out_pri_pic;
+
+    regs->synt_sli1.sp_tc_ofst_div2       = syn->sp.sli_tc_ofst_div2;;
+    regs->synt_sli1.sp_beta_ofst_div2     = syn->sp.sli_beta_ofst_div2;
+    regs->synt_sli1.sli_lp_fltr_acrs_sli  = syn->sp.sli_lp_fltr_acrs_sli;
+    regs->synt_sli1.sp_dblk_fltr_dis      = syn->sp.sli_dblk_fltr_dis;
+    regs->synt_sli1.dblk_fltr_ovrd_flg    = syn->sp.dblk_fltr_ovrd_flg;
+    regs->synt_sli1.sli_cb_qp_ofst        = syn->sp.sli_cb_qp_ofst;
+    regs->synt_sli1.max_mrg_cnd           = 3;//syn->sp.max_mrg_cnd;
+
+    regs->synt_sli1.col_ref_idx           = syn->sp.col_ref_idx;
+    regs->synt_sli1.col_frm_l0_flg        = syn->sp.col_frm_l0_flg;
+    regs->synt_sli2.sli_poc_lsb           = syn->sp.sli_poc_lsb;
+    regs->synt_sli2.sli_hdr_ext_len       = syn->sp.sli_hdr_ext_len;
+}
+
+static void vepu510_h265_set_ref_regs(H265eSyntax_new *syn, H265eVepu510Frame *regs)
+{
+    regs->synt_refm0.st_ref_pic_flg = syn->sp.st_ref_pic_flg;
+    regs->synt_refm0.poc_lsb_lt0 = syn->sp.poc_lsb_lt0;
+    regs->synt_refm0.num_lt_pic = syn->sp.num_lt_pic;
+
+    regs->synt_refm1.dlt_poc_msb_prsnt0 = syn->sp.dlt_poc_msb_prsnt0;
+    regs->synt_refm1.dlt_poc_msb_cycl0 = syn->sp.dlt_poc_msb_cycl0;
+    regs->synt_refm1.used_by_lt_flg0 = syn->sp.used_by_lt_flg0;
+    regs->synt_refm1.used_by_lt_flg1 = syn->sp.used_by_lt_flg1;
+    regs->synt_refm1.used_by_lt_flg2 = syn->sp.used_by_lt_flg2;
+    regs->synt_refm1.dlt_poc_msb_prsnt0 = syn->sp.dlt_poc_msb_prsnt0;
+    regs->synt_refm1.dlt_poc_msb_cycl0 = syn->sp.dlt_poc_msb_cycl0;
+    regs->synt_refm1.dlt_poc_msb_prsnt1 = syn->sp.dlt_poc_msb_prsnt1;
+    regs->synt_refm1.num_negative_pics = syn->sp.num_neg_pic;
+    regs->synt_refm1.num_pos_pic = syn->sp.num_pos_pic;
+
+    regs->synt_refm1.used_by_s0_flg = syn->sp.used_by_s0_flg;
+    regs->synt_refm2.dlt_poc_s0_m10 = syn->sp.dlt_poc_s0_m10;
+    regs->synt_refm2.dlt_poc_s0_m11 = syn->sp.dlt_poc_s0_m11;
+    regs->synt_refm3.dlt_poc_s0_m12 = syn->sp.dlt_poc_s0_m12;
+    regs->synt_refm3.dlt_poc_s0_m13 = syn->sp.dlt_poc_s0_m13;
+
+    regs->synt_long_refm0.poc_lsb_lt1 = syn->sp.poc_lsb_lt1;
+    regs->synt_long_refm1.dlt_poc_msb_cycl1 = syn->sp.dlt_poc_msb_cycl1;
+    regs->synt_long_refm0.poc_lsb_lt2 = syn->sp.poc_lsb_lt2;
+    regs->synt_refm1.dlt_poc_msb_prsnt2 = syn->sp.dlt_poc_msb_prsnt2;
+    regs->synt_long_refm1.dlt_poc_msb_cycl2 = syn->sp.dlt_poc_msb_cycl2;
+    regs->synt_sli1.lst_entry_l0 = syn->sp.lst_entry_l0;
+    regs->synt_sli0.ref_pic_lst_mdf_l0 = syn->sp.ref_pic_lst_mdf_l0;
+}
+
+static void vepu510_h265_set_me_regs(H265eV510HalContext *ctx, H265eSyntax_new *syn, H265eVepu510Frame *regs)
+{
+    regs->common.me_rnge.cime_srch_dwnh    = 15;
+    regs->common.me_rnge.cime_srch_uph     = 15;
+    regs->common.me_rnge.cime_srch_rgtw    = 12;
+    regs->common.me_rnge.cime_srch_lftw    = 12;
+    regs->common.me_cfg.rme_srch_h         = 3;
+    regs->common.me_cfg.rme_srch_v         = 3;
+
+    regs->common.me_cfg.srgn_max_num       = 54;
+    regs->common.me_cfg.cime_dist_thre     = 1024;
+    regs->common.me_cfg.rme_dis            = 0;
+    regs->common.me_cfg.fme_dis            = 0;
+    regs->common.me_rnge.dlt_frm_num       = 0x1;
+
+    if (syn->pp.sps_temporal_mvp_enabled_flag &&
+        (ctx->frame_type != INTRA_FRAME)) {
+        if (ctx->last_frame_type == INTRA_FRAME) {
+            regs->common.me_cach.colmv_load_hevc = 0;
+        } else {
+            regs->common.me_cach.colmv_load_hevc = 1;
+        }
+        regs->common.me_cach.colmv_stor_hevc     = 1;
+    }
+
+    regs->common.me_cach.cime_zero_thre = (ctx->cfg->tune.scene_mode ==
+                                           MPP_ENC_SCENE_MODE_IPC) ? 1024 : 64;
+    regs->common.me_cach.fme_prefsu_en     = 0;
+}
+
+void vepu510_h265_set_hw_address(H265eV510HalContext *ctx, H265eVepu510Frame *regs, HalEncTask *task)
+{
+    HalEncTask *enc_task = task;
+    HalBuf *recon_buf, *ref_buf;
+    MppBuffer md_info_buf = enc_task->md_info;
+    Vepu510H265eFrmCfg *frm = ctx->frm;
+    H265eSyntax_new *syn = ctx->syn;
+
+    hal_h265e_enter();
+
+    regs->common.adr_src0  = mpp_buffer_get_fd(enc_task->input);
+    regs->common.adr_src1  = regs->common.adr_src0;
+    regs->common.adr_src2  = regs->common.adr_src0;
+
+    recon_buf = hal_bufs_get_buf(ctx->dpb_bufs, frm->hal_curr_idx);
+    ref_buf = hal_bufs_get_buf(ctx->dpb_bufs, frm->hal_refr_idx);
+
+    if (!syn->sp.non_reference_flag) {
+        regs->common.rfpw_h_addr  = mpp_buffer_get_fd(recon_buf->buf[0]);
+        regs->common.rfpw_b_addr  = regs->common.rfpw_h_addr;
+        mpp_dev_multi_offset_update(ctx->reg_cfg, 164, ctx->fbc_header_len);
+    }
+    regs->common.rfpr_h_addr = mpp_buffer_get_fd(ref_buf->buf[0]);
+    regs->common.rfpr_b_addr = regs->common.rfpr_h_addr;
+    regs->common.colmvw_addr = mpp_buffer_get_fd(recon_buf->buf[2]);
+    regs->common.colmvr_addr = mpp_buffer_get_fd(ref_buf->buf[2]);
+    regs->common.dspw_addr = mpp_buffer_get_fd(recon_buf->buf[1]);
+    regs->common.dspr_addr = mpp_buffer_get_fd(ref_buf->buf[1]);
+
+    mpp_dev_multi_offset_update(ctx->reg_cfg, 166, ctx->fbc_header_len);
+
+    if (md_info_buf) {
+        regs->common.enc_pic.mei_stor = 1;
+        regs->common.meiw_addr = mpp_buffer_get_fd(md_info_buf);
+    } else {
+        regs->common.enc_pic.mei_stor = 0;
+        regs->common.meiw_addr = 0;
+    }
+
+    regs->common.bsbt_addr = mpp_buffer_get_fd(enc_task->output);
+    /* TODO: stream size relative with syntax */
+    regs->common.bsbb_addr  = regs->common.bsbt_addr;
+    regs->common.bsbr_addr  = regs->common.bsbt_addr;
+    regs->common.adr_bsbs   = regs->common.bsbt_addr;
+
+    regs->common.rfpt_h_addr = 0xffffffff;
+    regs->common.rfpb_h_addr = 0;
+    regs->common.rfpt_b_addr = 0xffffffff;
+    regs->common.adr_rfpb_b = 0;
+
+    mpp_dev_multi_offset_update(ctx->reg_cfg, 174, mpp_packet_get_length(task->packet));
+    mpp_dev_multi_offset_update(ctx->reg_cfg, 172, mpp_buffer_get_size(enc_task->output));
+
+    regs->common.pic_ofst.pic_ofst_y = mpp_frame_get_offset_y(task->frame);
+    regs->common.pic_ofst.pic_ofst_x = mpp_frame_get_offset_x(task->frame);
+
+    /* smear bufs */
+    regs->common.adr_smear_rd = mpp_buffer_get_fd(ref_buf->buf[3]);
+    regs->common.adr_smear_wr = mpp_buffer_get_fd(recon_buf->buf[3]);
+}
+
+static MPP_RET vepu510_h265e_save_pass1_patch(H265eV510RegSet *regs, H265eV510HalContext *ctx,
+                                              RK_S32 tiles_enabled_flag)
+{
+    H265eVepu510Frame *reg_frm = &regs->reg_frm;
+    RK_S32 width = ctx->cfg->prep.width;
+    RK_S32 height = ctx->cfg->prep.height;
+    RK_S32 width_align = MPP_ALIGN(width, 16);
+    RK_S32 height_align = MPP_ALIGN(height, 16);
+
+    if (NULL == ctx->buf_pass1) {
+        mpp_buffer_get(NULL, &ctx->buf_pass1, width_align * height_align * 3 / 2);
+        if (!ctx->buf_pass1) {
+            mpp_err("buf_pass1 malloc fail, debreath invaild");
+            return MPP_NOK;
+        }
+    }
+
+    reg_frm->common.enc_pic.cur_frm_ref = 1;
+    reg_frm->common.rfpw_h_addr = mpp_buffer_get_fd(ctx->buf_pass1);
+    reg_frm->common.rfpw_b_addr = reg_frm->common.rfpw_h_addr;
+    reg_frm->common.enc_pic.rec_fbc_dis = 1;
+
+    if (tiles_enabled_flag)
+        reg_frm->synt_pps.lpf_fltr_acrs_til = 0;
+
+    mpp_dev_multi_offset_update(ctx->reg_cfg, 164, 0);
+
+    /* NOTE: disable split to avoid lowdelay slice output */
+    reg_frm->common.sli_splt.sli_splt = 0;
+    reg_frm->common.enc_pic.slen_fifo = 0;
+
+    return MPP_OK;
+}
+
+static MPP_RET vepu510_h265e_use_pass1_patch(H265eV510RegSet *regs, H265eV510HalContext *ctx)
+{
+    Vepu510ControlCfg *reg_ctl = &regs->reg_ctl;
+    H265eVepu510Frame *reg_frm = &regs->reg_frm;
+    RK_U32 hor_stride = MPP_ALIGN(ctx->cfg->prep.width, 16);
+    VepuFmtCfg *fmt = (VepuFmtCfg *)ctx->input_fmt;
+    MPP_RET ret = MPP_OK;
+
+    hal_h265e_dbg_func("enter\n");
+
+    reg_ctl->dtrns_map.src_bus_edin = fmt->src_endian;
+    reg_frm->common.src_fmt.src_cfmt = VEPU541_FMT_YUV420SP;
+    reg_frm->common.src_fmt.alpha_swap = 0;
+    reg_frm->common.src_fmt.rbuv_swap = 0;
+    reg_frm->common.src_fmt.out_fmt = 1;
+    reg_frm->common.src_fmt.src_rcne   = 1;
+
+    reg_frm->common.src_strd0.src_strd0 = hor_stride;
+    reg_frm->common.src_strd1.src_strd1 = 3 * hor_stride;
+
+    reg_frm->common.src_proc.src_mirr = 0;
+    reg_frm->common.src_proc.src_rot = 0;
+
+    reg_frm->common.adr_src0 = mpp_buffer_get_fd(ctx->buf_pass1);
+    reg_frm->common.adr_src1 = reg_frm->common.adr_src0;
+    reg_frm->common.adr_src2 = 0;
+
+    /* input cb addr */
+    ret = mpp_dev_multi_offset_update(ctx->reg_cfg, 161, 2 * hor_stride);
+    if (ret)
+        mpp_err_f("set input cb addr offset failed %d\n", ret);
+
+    return MPP_OK;
+}
+
+static void setup_vepu510_ext_line_buf(H265eV510HalContext *ctx, H265eV510RegSet *regs)
+{
+    MppDevRcbInfoCfg rcb_cfg;
+    H265eVepu510Frame *reg_frm = &regs->reg_frm;
+    RK_S32 offset = 0;
+    RK_S32 fd;
+
+    if (ctx->ext_line_buf) {
+        fd = mpp_buffer_get_fd(ctx->ext_line_buf);
+        offset = ctx->ext_line_buf_size;
+
+        reg_frm->common.ebufb_addr = fd;
+        reg_frm->common.ebuft_addr = fd;
+        mpp_dev_multi_offset_update(ctx->reg_cfg, 178, ctx->ext_line_buf_size);
+    } else {
+        reg_frm->common.ebufb_addr = 0;
+        reg_frm->common.ebuft_addr = 0;
+    }
+
+    /* rcb info for sram */
+    rcb_cfg.reg_idx = 179;
+    rcb_cfg.size = offset;
+
+    mpp_dev_ioctl(ctx->dev, MPP_DEV_RCB_INFO, &rcb_cfg);
+
+    rcb_cfg.reg_idx = 178;
+    rcb_cfg.size = 0;
+
+    mpp_dev_ioctl(ctx->dev, MPP_DEV_RCB_INFO, &rcb_cfg);
+}
+
+static MPP_RET setup_vepu510_dual_core(H265eV510HalContext *ctx)
+{
+    Vepu510H265eFrmCfg *frm = ctx->frm;
+    H265eV510RegSet *regs = frm->regs_set;
+    H265eVepu510Frame        *reg_frm = &regs->reg_frm;
+    RK_U32 dchs_ofst = 9;
+    RK_U32 dchs_dly = 0;
+    RK_U32 dchs_rxe  = 1;
+
+    if (ctx->task_cnt == 1)
+        return MPP_OK;
+
+    if (ctx->frame_type == INTRA_FRAME) {
+        ctx->curr_idx = 0;
+        ctx->prev_idx = 0;
+        dchs_rxe = 0;
+    }
+
+    reg_frm->common.dual_core.dchs_txid = ctx->curr_idx;
+    reg_frm->common.dual_core.dchs_rxid = ctx->prev_idx;
+    reg_frm->common.dual_core.dchs_txe = 1;
+    reg_frm->common.dual_core.dchs_rxe = dchs_rxe;
+    reg_frm->common.dual_core.dchs_ofst = dchs_ofst;
+    reg_frm->common.dual_core.dchs_dly = dchs_dly;
+
+    ctx->prev_idx = ctx->curr_idx++;
+    if (ctx->curr_idx > 3)
+        ctx->curr_idx = 0;
+
+    return MPP_OK;
+}
+
+static void setup_vepu510_split(H265eV510RegSet *regs, MppEncCfgSet *enc_cfg, RK_U32 title_en)
+{
+    MppEncSliceSplit *cfg = &enc_cfg->split;
+
+    hal_h265e_dbg_func("enter\n");
+
+    switch (cfg->split_mode) {
+    case MPP_ENC_SPLIT_NONE : {
+        regs->reg_frm.common.sli_splt.sli_splt = 0;
+        regs->reg_frm.common.sli_splt.sli_splt_mode = 0;
+        regs->reg_frm.common.sli_splt.sli_splt_cpst = 0;
+        regs->reg_frm.common.sli_splt.sli_max_num_m1 = 0;
+        regs->reg_frm.common.sli_splt.sli_flsh = 0;
+        regs->reg_frm.common.sli_cnum.sli_splt_cnum_m1 = 0;
+
+        regs->reg_frm.common.sli_byte.sli_splt_byte = 0;
+        regs->reg_frm.common.enc_pic.slen_fifo = 0;
+    } break;
+    case MPP_ENC_SPLIT_BY_BYTE : {
+        regs->reg_frm.common.sli_splt.sli_splt = 1;
+        regs->reg_frm.common.sli_splt.sli_splt_mode = 0;
+        regs->reg_frm.common.sli_splt.sli_splt_cpst = 0;
+        regs->reg_frm.common.sli_splt.sli_max_num_m1 = 500;
+        regs->reg_frm.common.sli_splt.sli_flsh = 1;
+        regs->reg_frm.common.sli_cnum.sli_splt_cnum_m1 = 0;
+
+        regs->reg_frm.common.sli_byte.sli_splt_byte = cfg->split_arg;
+        regs->reg_frm.common.enc_pic.slen_fifo = cfg->split_out ? 1 : 0;
+        regs->reg_ctl.int_en.vslc_done_en = regs->reg_frm.common.enc_pic.slen_fifo ;
+    } break;
+    case MPP_ENC_SPLIT_BY_CTU : {
+        RK_U32 mb_w = MPP_ALIGN(enc_cfg->prep.width, 32) / 32;
+        RK_U32 mb_h = MPP_ALIGN(enc_cfg->prep.height, 32) / 32;
+        RK_U32 slice_num = 0;
+
+        if (title_en)
+            mb_w = mb_w / 2;
+
+        slice_num = (mb_w * mb_h + cfg->split_arg - 1) / cfg->split_arg;
+
+        regs->reg_frm.common.sli_splt.sli_splt = 1;
+        regs->reg_frm.common.sli_splt.sli_splt_mode = 1;
+        regs->reg_frm.common.sli_splt.sli_splt_cpst = 0;
+        regs->reg_frm.common.sli_splt.sli_max_num_m1 = 500;
+        regs->reg_frm.common.sli_splt.sli_flsh = 1;
+        regs->reg_frm.common.sli_cnum.sli_splt_cnum_m1 = cfg->split_arg - 1;
+
+        regs->reg_frm.common.sli_byte.sli_splt_byte = 0;
+        regs->reg_frm.common.enc_pic.slen_fifo = cfg->split_out ? 1 : 0;
+        if ((cfg->split_out & MPP_ENC_SPLIT_OUT_LOWDELAY) ||
+            (regs->reg_frm.common.enc_pic.slen_fifo && (slice_num > VEPU510_SLICE_FIFO_LEN)))
+            regs->reg_ctl.int_en.vslc_done_en = 1;
+
+    } break;
+    default : {
+        mpp_log_f("invalide slice split mode %d\n", cfg->split_mode);
+    } break;
+    }
+
+    cfg->change = 0;
+
+    hal_h265e_dbg_func("leave\n");
+}
+
+static void vepu510_h265_set_scaling_list(H265eV510HalContext *ctx)
+{
+    Vepu510H265eFrmCfg *frm_cfg = ctx->frm;
+    H265eV510RegSet *regs = frm_cfg->regs_set;
+    Vepu510SclCfg *s = &regs->reg_scl;
+    RK_U8 *p = (RK_U8 *)&s->tu8_intra_y[0];
+    RK_U32 scl_lst_sel = regs->reg_frm.rdo_cfg.scl_lst_sel;
+    RK_U8 idx;
+
+    hal_h265e_dbg_func("enter\n");
+
+    if (scl_lst_sel == 1) {
+        for (idx = 0; idx < 64; idx++) {
+            /* TU8 intra Y/U/V */
+            p[idx + 64 * 0] = vepu510_h265_cqm_intra8[63 - idx];
+            p[idx + 64 * 1] = vepu510_h265_cqm_intra8[63 - idx];
+            p[idx + 64 * 2] = vepu510_h265_cqm_intra8[63 - idx];
+
+            /* TU8 inter Y/U/V */
+            p[idx + 64 * 3] = vepu510_h265_cqm_inter8[63 - idx];
+            p[idx + 64 * 4] = vepu510_h265_cqm_inter8[63 - idx];
+            p[idx + 64 * 5] = vepu510_h265_cqm_inter8[63 - idx];
+
+            /* TU16 intra Y/U/V AC */
+            p[idx + 64 * 6] = vepu510_h265_cqm_intra8[63 - idx];
+            p[idx + 64 * 7] = vepu510_h265_cqm_intra8[63 - idx];
+            p[idx + 64 * 8] = vepu510_h265_cqm_intra8[63 - idx];
+
+            /* TU16 inter Y/U/V AC */
+            p[idx + 64 *  9] = vepu510_h265_cqm_inter8[63 - idx];
+            p[idx + 64 * 10] = vepu510_h265_cqm_inter8[63 - idx];
+            p[idx + 64 * 11] = vepu510_h265_cqm_inter8[63 - idx];
+
+            /* TU32 intra/inter Y AC */
+            p[idx + 64 * 12] = vepu510_h265_cqm_intra8[63 - idx];
+            p[idx + 64 * 13] = vepu510_h265_cqm_inter8[63 - idx];
+        }
+
+        s->tu_dc0.tu16_intra_y_dc = 16;
+        s->tu_dc0.tu16_intra_u_dc = 16;
+        s->tu_dc0.tu16_intra_v_dc = 16;
+        s->tu_dc0.tu16_inter_y_dc = 16;
+        s->tu_dc1.tu16_inter_u_dc = 16;
+        s->tu_dc1.tu16_inter_v_dc = 16;
+        s->tu_dc1.tu32_intra_y_dc = 16;
+        s->tu_dc1.tu32_inter_y_dc = 16;
+    } else if (scl_lst_sel == 2) {
+        //TODO: Update scaling list for (scaling_list_mode == 2)
+        mpp_log_f("scaling_list_mode 2 is not supported yet\n");
+    }
+
+    hal_h265e_dbg_func("leave\n");
+}
+
+MPP_RET hal_h265e_v510_gen_regs(void *hal, HalEncTask *task)
+{
+    H265eV510HalContext *ctx = (H265eV510HalContext *)hal;
+    HalEncTask *enc_task = task;
+    EncRcTask *rc_task = enc_task->rc_task;
+    EncFrmStatus *frm = &rc_task->frm;
+    H265eSyntax_new *syn = ctx->syn;
+    Vepu510H265eFrmCfg *frm_cfg = ctx->frm;
+    H265eV510RegSet *regs = frm_cfg->regs_set;
+    RK_U32 pic_width_align8, pic_height_align8;
+    RK_S32 pic_wd32, pic_h32;
+    VepuFmtCfg *fmt = (VepuFmtCfg *)ctx->input_fmt;
+    Vepu510ControlCfg *reg_ctl = &regs->reg_ctl;
+    H265eVepu510Frame        *reg_frm = &regs->reg_frm;
+    Vepu510RcRoi *reg_klut = &regs->reg_rc_roi;
+    MppEncSceneMode sm = ctx->cfg->tune.scene_mode;
+    MPP_RET ret = MPP_OK;
+
+    hal_h265e_enter();
+    pic_width_align8 = (syn->pp.pic_width + 7) & (~7);
+    pic_height_align8 = (syn->pp.pic_height + 7) & (~7);
+    pic_wd32 = (syn->pp.pic_width +  31) / 32;
+    pic_h32 = (syn->pp.pic_height + 31) / 32;
+
+    hal_h265e_dbg_simple("frame %d | type %d | start gen regs",
+                         ctx->frame_count, ctx->frame_type);
+    vepu510_h265e_tune_aq_prepare(ctx->tune);
+    memset(regs, 0, sizeof(H265eV510RegSet));
+
+    reg_ctl->enc_strt.lkt_num      = 0;
+    reg_ctl->enc_strt.vepu_cmd     = ctx->enc_mode;
+    reg_ctl->enc_clr.safe_clr      = 0x0;
+    reg_ctl->enc_clr.force_clr     = 0x0;
+
+    reg_ctl->int_en.enc_done_en        = 1;
+    reg_ctl->int_en.lkt_node_done_en   = 1;
+    reg_ctl->int_en.sclr_done_en       = 1;
+    reg_ctl->int_en.vslc_done_en       = 0;
+    reg_ctl->int_en.vbsf_oflw_en       = 1;
+    reg_ctl->int_en.vbuf_lens_en       = 1;
+    reg_ctl->int_en.enc_err_en         = 1;
+    reg_ctl->int_en.vsrc_err_en        = 1;
+    reg_ctl->int_en.wdg_en             = 1;
+    reg_ctl->int_en.lkt_err_int_en     = 0;
+    reg_ctl->int_en.lkt_err_stop_en    = 1;
+    reg_ctl->int_en.lkt_force_stop_en  = 1;
+    reg_ctl->int_en.jslc_done_en       = 1;
+    reg_ctl->int_en.jbsf_oflw_en       = 1;
+    reg_ctl->int_en.jbuf_lens_en       = 1;
+    reg_ctl->int_en.dvbm_err_en        = 0;
+
+    reg_ctl->dtrns_map.jpeg_bus_edin    = 0x0;
+    reg_ctl->dtrns_map.src_bus_edin     = 0x0;
+    reg_ctl->dtrns_map.meiw_bus_edin    = 0x0;
+    reg_ctl->dtrns_map.bsw_bus_edin     = 0x7;
+    reg_ctl->dtrns_map.lktw_bus_edin    = 0x0;
+    reg_ctl->dtrns_map.rec_nfbc_bus_edin   = 0x0;
+
+    reg_ctl->dtrns_cfg.axi_brsp_cke     = 0x0;
+    reg_ctl->enc_wdg.vs_load_thd        = 0;
+
+    reg_ctl->opt_strg.cke                = 1;
+    reg_ctl->opt_strg.resetn_hw_en       = 1;
+    reg_ctl->opt_strg.rfpr_err_e         = 1;
+
+    reg_frm->common.enc_rsl.pic_wd8_m1    = pic_width_align8 / 8 - 1;
+    reg_frm->common.src_fill.pic_wfill    = (syn->pp.pic_width & 0x7)
+                                            ? (8 - (syn->pp.pic_width & 0x7)) : 0;
+    reg_frm->common.enc_rsl.pic_hd8_m1    = pic_height_align8 / 8 - 1;
+    reg_frm->common.src_fill.pic_hfill    = (syn->pp.pic_height & 0x7)
+                                            ? (8 - (syn->pp.pic_height & 0x7)) : 0;
+
+    reg_frm->common.enc_pic.enc_stnd            = 1; //H265
+    reg_frm->common.enc_pic.cur_frm_ref         = !syn->sp.non_reference_flag; //current frame will be refered
+    reg_frm->common.enc_pic.bs_scp              = 1;
+    reg_frm->common.enc_pic.log2_ctu_num_hevc   = mpp_ceil_log2(pic_wd32 * pic_h32);
+
+    reg_frm->common.src_proc.src_mirr     = 0;
+    reg_frm->common.src_proc.src_rot      = 0;
+    reg_frm->common.src_proc.tile4x4_en   = 0;
+
+    reg_klut->klut_ofst.chrm_klut_ofst = (ctx->frame_type == INTRA_FRAME) ? 6 :
+                                         (sm == MPP_ENC_SCENE_MODE_IPC ? 9 : 6);
+
+    reg_frm->sao_cfg.sao_lambda_multi          = 5;
+
+    setup_vepu510_split(regs, ctx->cfg, syn->pp.tiles_enabled_flag);
+
+    if (ctx->task_cnt > 1)
+        setup_vepu510_dual_core(ctx);
+
+    vepu510_h265_set_me_regs(ctx, syn, reg_frm);
+
+    reg_frm->rdo_cfg.chrm_spcl                      = 0;
+    reg_frm->rdo_cfg.cu_inter_e                     = 0xdb;
+    reg_frm->rdo_cfg.lambda_qp_use_avg_cu16_flag    = (sm == MPP_ENC_SCENE_MODE_IPC);
+    reg_frm->rdo_cfg.yuvskip_calc_en                = 1;
+    reg_frm->rdo_cfg.atf_e = (sm == MPP_ENC_SCENE_MODE_IPC);
+    reg_frm->rdo_cfg.atr_e = 1;
+
+    if (syn->pp.num_long_term_ref_pics_sps) {
+        reg_frm->rdo_cfg.ltm_col    = 0;
+        reg_frm->rdo_cfg.ltm_idx0l0 = 1;
+    } else {
+        reg_frm->rdo_cfg.ltm_col    = 0;
+        reg_frm->rdo_cfg.ltm_idx0l0 = 0;
+    }
+
+    reg_frm->rdo_cfg.ccwa_e         = 1;
+    reg_frm->rdo_cfg.scl_lst_sel    = syn->pp.scaling_list_enabled_flag;
+    {
+        RK_U32 i_nal_type = 0;
+
+        /* TODO: extend syn->frame_coding_type definition */
+        if (ctx->frame_type == INTRA_FRAME) {
+            /* reset ref pictures */
+            i_nal_type    = NAL_IDR_W_RADL;
+        } else if (ctx->frame_type == INTER_P_FRAME ) {
+            i_nal_type    = NAL_TRAIL_R;
+        } else {
+            i_nal_type    = NAL_TRAIL_R;
+        }
+        reg_frm->synt_nal.nal_unit_type  = syn->sp.temporal_id ?  NAL_TSA_R : i_nal_type;
+    }
+
+    vepu510_h265_set_scaling_list(ctx);
+    vepu510_h265_set_hw_address(ctx, reg_frm, task);
+    vepu510_h265_set_pp_regs(regs, fmt, &ctx->cfg->prep);
+    vepu510_h265_set_rc_regs(ctx, regs, task);
+    vepu510_h265_set_slice_regs(syn, reg_frm);
+    vepu510_h265_set_ref_regs(syn, reg_frm);
+    ret = vepu510_h265_set_patch_info(syn, (Vepu541Fmt)fmt->format, ctx->reg_cfg, enc_task);
+    if (ret)
+        return ret;
+
+    setup_vepu510_ext_line_buf(ctx, regs);
+
+    /* ROI configure */
+    if (ctx->roi_data)
+        vepu510_set_roi(&regs->reg_rc_roi.roi_cfg, ctx->roi_data,
+                        ctx->cfg->prep.width, ctx->cfg->prep.height);
+    /*paramet cfg*/
+    vepu510_h265_global_cfg_set(ctx, regs);
+    vepu510_h265e_tune_reg_patch(ctx->tune, task);
+
+    /* two pass register patch */
+    if (frm->save_pass1)
+        vepu510_h265e_save_pass1_patch(regs, ctx, syn->pp.tiles_enabled_flag);
+
+    if (frm->use_pass1)
+        vepu510_h265e_use_pass1_patch(regs, ctx);
+
+
+    ctx->frame_num++;
+
+    hal_h265e_leave();
+    return MPP_OK;
+}
+
+MPP_RET hal_h265e_v510_start(void *hal, HalEncTask *enc_task)
+{
+    MPP_RET ret = MPP_OK;
+    H265eV510HalContext *ctx = (H265eV510HalContext *)hal;
+    Vepu510H265eFrmCfg *frm = ctx->frm;
+    RK_U32 *regs = (RK_U32*)frm->regs_set;
+    H265eV510RegSet *hw_regs = frm->regs_set;
+    H265eV510StatusElem *reg_out = (H265eV510StatusElem *)frm->regs_ret;
+    MppDevRegWrCfg cfg;
+    MppDevRegRdCfg cfg1;
+    RK_U32 i = 0;
+
+    hal_h265e_enter();
+    if (enc_task->flags.err) {
+        hal_h265e_err("enc_task->flags.err %08x, return e arly",
+                      enc_task->flags.err);
+        return MPP_NOK;
+    }
+
+    cfg.reg = (RK_U32*)&hw_regs->reg_ctl;
+    cfg.size = sizeof(Vepu510ControlCfg);
+    cfg.offset = VEPU510_CTL_OFFSET;
+
+    ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
+    if (ret) {
+        mpp_err_f("set register write failed %d\n", ret);
+        return ret;
+    }
+
+    if (hal_h265e_debug & HAL_H265E_DBG_CTL_REGS) {
+        regs = (RK_U32*)&hw_regs->reg_ctl;
+        for (i = 0; i < sizeof(Vepu510ControlCfg) / 4; i++) {
+            hal_h265e_dbg_ctl("ctl reg[%04x]: 0%08x\n", i * 4, regs[i]);
+        }
+    }
+
+    cfg.reg = &hw_regs->reg_frm;
+    cfg.size = sizeof(H265eVepu510Frame);
+    cfg.offset = VEPU510_FRAME_OFFSET;
+
+    ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
+    if (ret) {
+        mpp_err_f("set register write failed %d\n", ret);
+        return ret;
+    }
+
+    if (hal_h265e_debug & HAL_H265E_DBG_REGS) {
+        regs = (RK_U32*)(&hw_regs->reg_frm);
+        for (i = 0; i < 32; i++) {
+            hal_h265e_dbg_regs("hw add cfg reg[%04x]: 0%08x\n", i * 4, regs[i]);
+        }
+        regs += 32;
+        for (i = 0; i < (sizeof(H265eVepu510Frame) - 128) / 4; i++) {
+            hal_h265e_dbg_regs("set reg[%04x]: 0%08x\n", i * 4, regs[i]);
+        }
+    }
+    cfg.reg = &hw_regs->reg_rc_roi;
+    cfg.size = sizeof(Vepu510RcRoi);
+    cfg.offset = VEPU510_RC_ROI_OFFSET;
+
+    ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
+    if (ret) {
+        mpp_err_f("set register write failed %d\n", ret);
+        return ret;
+    }
+
+    if (hal_h265e_debug & HAL_H265E_DBG_RCKUT_REGS) {
+        regs = (RK_U32*)&hw_regs->reg_rc_roi;
+        for (i = 0; i < sizeof(Vepu510RcRoi) / 4; i++) {
+            hal_h265e_dbg_rckut("set reg[%04x]: 0%08x\n", i * 4, regs[i]);
+        }
+    }
+
+    cfg.reg =  &hw_regs->reg_param;
+    cfg.size = sizeof(H265eVepu510Param);
+    cfg.offset = VEPU510_PARAM_OFFSET;
+
+    ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
+    if (ret) {
+        mpp_err_f("set register write failed %d\n", ret);
+        return ret;
+    }
+
+    if (hal_h265e_debug & HAL_H265E_DBG_WGT_REGS) {
+        regs = (RK_U32*)&hw_regs->reg_param;
+        for (i = 0; i < sizeof(H265eVepu510Param) / 4; i++) {
+            hal_h265e_dbg_wgt("set reg[%04x]: 0%08x\n", i * 4, regs[i]);
+        }
+    }
+
+    cfg.reg = &hw_regs->reg_sqi;
+    cfg.size = sizeof(H265eVepu510Sqi);
+    cfg.offset = VEPU510_SQI_OFFSET;
+
+    ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
+    if (ret) {
+        mpp_err_f("set register write failed %d\n", ret);
+        return ret;
+    }
+
+    cfg.reg = &hw_regs->reg_scl;
+    cfg.size = sizeof(hw_regs->reg_scl);
+    cfg.offset = VEPU510_SCL_OFFSET ;
+
+    ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg);
+    if (ret) {
+        mpp_err_f("set register write failed %d\n", ret);
+        return ret;
+    }
+
+    ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFS, ctx->reg_cfg);
+    if (ret) {
+        mpp_err_f("set register offsets failed %d\n", ret);
+        return ret;
+    }
+
+    cfg1.reg = &reg_out->hw_status;
+    cfg1.size = sizeof(RK_U32);
+    cfg1.offset = VEPU510_REG_BASE_HW_STATUS;
+
+    ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &cfg1);
+    if (ret) {
+        mpp_err_f("set register read failed %d\n", ret);
+        return ret;
+    }
+
+    cfg1.reg = &reg_out->st;
+    cfg1.size = sizeof(H265eV510StatusElem) - 4;
+    cfg1.offset = VEPU510_STATUS_OFFSET;
+
+    ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &cfg1);
+    if (ret) {
+        mpp_err_f("set register read failed %d\n", ret);
+        return ret;
+    }
+
+    ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL);
+    if (ret) {
+        mpp_err_f("send cmd failed %d\n", ret);
+    }
+    hal_h265e_leave();
+    return ret;
+}
+
+static MPP_RET vepu510_h265_set_feedback(H265eV510HalContext *ctx, HalEncTask *enc_task)
+{
+    EncRcTaskInfo *hal_rc_ret = (EncRcTaskInfo *)&enc_task->rc_task->info;
+    Vepu510H265eFrmCfg *frm = ctx->frms[enc_task->flags.reg_idx];
+    Vepu510H265Fbk  *fb = &frm->feedback;
+    MppEncCfgSet    *cfg = ctx->cfg;
+    RK_S32 mb8_num = MPP_ALIGN(cfg->prep.width, 8) * MPP_ALIGN(cfg->prep.height, 8) / 64;
+    RK_S32 mb4_num = (mb8_num << 2);
+    H265eV510StatusElem *elem = (H265eV510StatusElem *)frm->regs_ret;
+    RK_U32 hw_status = elem->hw_status;
+
+    hal_h265e_enter();
+
+    fb->qp_sum += elem->st.qp_sum;
+    fb->out_strm_size += elem->st.bs_lgth_l32;
+    fb->sse_sum += (RK_S64)(elem->st.sse_h32 << 16) +
+                   (elem->st.st_sse_bsl.sse_l16 & 0xffff);
+
+    fb->hw_status = hw_status;
+    hal_h265e_dbg_detail("hw_status: 0x%08x", hw_status);
+    if (hw_status & RKV_ENC_INT_LINKTABLE_FINISH)
+        hal_h265e_err("RKV_ENC_INT_LINKTABLE_FINISH");
+
+    if (hw_status & RKV_ENC_INT_ONE_FRAME_FINISH)
+        hal_h265e_dbg_detail("RKV_ENC_INT_ONE_FRAME_FINISH");
+
+    if (hw_status & RKV_ENC_INT_ONE_SLICE_FINISH)
+        hal_h265e_dbg_detail("RKV_ENC_INT_ONE_SLICE_FINISH");
+
+    if (hw_status & RKV_ENC_INT_SAFE_CLEAR_FINISH)
+        hal_h265e_err("RKV_ENC_INT_SAFE_CLEAR_FINISH");
+
+    if (hw_status & RKV_ENC_INT_BIT_STREAM_OVERFLOW)
+        hal_h265e_err("RKV_ENC_INT_BIT_STREAM_OVERFLOW");
+
+    if (hw_status & RKV_ENC_INT_BUS_WRITE_FULL)
+        hal_h265e_err("RKV_ENC_INT_BUS_WRITE_FULL");
+
+    if (hw_status & RKV_ENC_INT_BUS_WRITE_ERROR)
+        hal_h265e_err("RKV_ENC_INT_BUS_WRITE_ERROR");
+
+    if (hw_status & RKV_ENC_INT_BUS_READ_ERROR)
+        hal_h265e_err("RKV_ENC_INT_BUS_READ_ERROR");
+
+    if (hw_status & RKV_ENC_INT_TIMEOUT_ERROR)
+        hal_h265e_err("RKV_ENC_INT_TIMEOUT_ERROR");
+
+    fb->st_mb_num += elem->st.st_bnum_b16.num_b16;
+
+    fb->st_lvl64_inter_num += elem->st.st_pnum_p64.pnum_p64;
+    fb->st_lvl32_inter_num += elem->st.st_pnum_p32.pnum_p32;
+    fb->st_lvl32_intra_num += elem->st.st_pnum_i32.pnum_i32;
+    fb->st_lvl16_inter_num += elem->st.st_pnum_p16.pnum_p16;
+    fb->st_lvl16_intra_num += elem->st.st_pnum_i16.pnum_i16;
+    fb->st_lvl8_inter_num  += elem->st.st_pnum_p8.pnum_p8;
+    fb->st_lvl8_intra_num  += elem->st.st_pnum_i8.pnum_i8;
+    fb->st_lvl4_intra_num  += elem->st.st_pnum_i4.pnum_i4;
+    ctx->feedback.acc_cover16_num = elem->st.st_skin_sum1.acc_cover16_num;
+    ctx->feedback.acc_bndry16_num = elem->st.st_skin_sum2.acc_bndry16_num;
+    ctx->feedback.acc_zero_mv = elem->st.acc_zero_mv;
+    ctx->feedback.st_ctu_num = elem->st.st_bnum_b16.num_b16;
+    memcpy(&fb->st_cu_num_qp[0], &elem->st.st_b8_qp, 52 * sizeof(RK_U32));
+
+    if (mb4_num > 0)
+        hal_rc_ret->iblk4_prop =  ((((fb->st_lvl4_intra_num + fb->st_lvl8_intra_num) << 2) +
+                                    (fb->st_lvl16_intra_num << 4) +
+                                    (fb->st_lvl32_intra_num << 6)) << 8) / mb4_num;
+
+    if (mb8_num > 0) {
+        hal_rc_ret->quality_real = fb->qp_sum / mb8_num;
+    }
+
+    hal_h265e_leave();
+    return MPP_OK;
+}
+
+static MPP_RET hal_h265e_vepu510_status_check(H265eV510RegSet *regs)
+{
+    MPP_RET ret = MPP_OK;
+
+    if (regs->reg_ctl.int_sta.lkt_node_done_sta)
+        hal_h265e_dbg_detail("lkt_done finish");
+
+    if (regs->reg_ctl.int_sta.enc_done_sta)
+        hal_h265e_dbg_detail("enc_done finish");
+
+    if (regs->reg_ctl.int_sta.vslc_done_sta)
+        hal_h265e_dbg_detail("enc_slice finsh");
+
+    if (regs->reg_ctl.int_sta.sclr_done_sta)
+        hal_h265e_dbg_detail("safe clear finsh");
+
+    if (regs->reg_ctl.int_sta.vbsf_oflw_sta) {
+        mpp_err_f("bit stream overflow");
+        ret = MPP_NOK;
+    }
+
+    if (regs->reg_ctl.int_sta.vbuf_lens_sta) {
+        mpp_err_f("bus write full");
+        ret = MPP_NOK;
+    }
+
+    if (regs->reg_ctl.int_sta.enc_err_sta) {
+        mpp_err_f("bus error");
+        ret = MPP_NOK;
+    }
+
+    if (regs->reg_ctl.int_sta.wdg_sta) {
+        mpp_err_f("wdg timeout");
+        ret = MPP_NOK;
+    }
+
+    return ret;
+}
+
+//#define DUMP_DATA
+MPP_RET hal_h265e_v510_wait(void *hal, HalEncTask *task)
+{
+    MPP_RET ret = MPP_OK;
+    H265eV510HalContext *ctx = (H265eV510HalContext *)hal;
+    HalEncTask *enc_task = task;
+    MppPacket pkt = enc_task->packet;
+    RK_U32 split_out = ctx->cfg->split.split_out;
+    RK_S32 task_idx = task->flags.reg_idx;
+    Vepu510H265eFrmCfg *frm = ctx->frms[task_idx];
+    H265eV510RegSet *regs = frm->regs_set;
+    RK_U32 offset = mpp_packet_get_length(pkt);
+    RK_U32 seg_offset = offset;
+    H265eVepu510Frame *reg_frm = &regs->reg_frm;
+    RK_U32 type = reg_frm->synt_nal.nal_unit_type;
+    H265eV510StatusElem *elem = (H265eV510StatusElem *)frm->regs_ret;
+
+    hal_h265e_enter();
+
+    if (enc_task->flags.err) {
+        hal_h265e_err("enc_task->flags.err %08x, return early",
+                      enc_task->flags.err);
+        return MPP_NOK;
+    }
+
+    /* if pass1 mode, it will disable split mode and the split out need to be disable */
+    if (enc_task->rc_task->frm.save_pass1)
+        split_out = 0;
+
+    if (split_out) {
+        EncOutParam param;
+        RK_U32 slice_len = 0;
+        RK_U32 slice_last = 0;
+        MppDevPollCfg *poll_cfg = (MppDevPollCfg *)((char *)ctx->poll_cfgs);
+        param.task = task;
+        param.base = mpp_packet_get_data(task->packet);
+
+        do {
+            RK_S32 i = 0;
+            poll_cfg->poll_type = 0;
+            poll_cfg->poll_ret  = 0;
+            poll_cfg->count_max = ctx->poll_slice_max;
+            poll_cfg->count_ret = 0;
+
+            ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, poll_cfg);
+            for (i = 0; i < poll_cfg->count_ret; i++) {
+                slice_last = poll_cfg->slice_info[i].last;
+                slice_len = poll_cfg->slice_info[i].length;
+                param.length = slice_len;
+
+                mpp_packet_add_segment_info(pkt, type, seg_offset, slice_len);
+                seg_offset += slice_len;
+
+                if (split_out & MPP_ENC_SPLIT_OUT_LOWDELAY) {
+                    param.length = slice_len;
+                    if (slice_last)
+                        ctx->output_cb->cmd = ENC_OUTPUT_FINISH;
+                    else
+                        ctx->output_cb->cmd = ENC_OUTPUT_SLICE;
+
+                    mpp_callback(ctx->output_cb, &param);
+                }
+            }
+        } while (!slice_last);
+
+        ret = hal_h265e_vepu510_status_check(regs);
+        if (!ret)
+            task->hw_length += elem->st.bs_lgth_l32;
+
+    } else {
+        ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, NULL);
+        if (ret) {
+            mpp_err_f("poll cmd failed %d\n", ret);
+            ret = MPP_ERR_VPUHW;
+        } else {
+            ret = hal_h265e_vepu510_status_check(regs);
+            if (!ret)
+                task->hw_length += elem->st.bs_lgth_l32;
+        }
+        mpp_packet_add_segment_info(pkt, type, offset, elem->st.bs_lgth_l32);
+    }
+
+#ifdef DUMP_DATA
+    static FILE *fp_fbd = NULL;
+    static FILE *fp_fbh = NULL;
+    static FILE *fp_dws = NULL;
+    HalBuf *recon_buf;
+    static RK_U32 frm_num = 0;
+    H265eSyntax_new *syn = (H265eSyntax_new *)enc_task->syntax.data;
+    recon_buf = hal_bufs_get_buf(ctx->dpb_bufs, syn->sp.recon_pic.slot_idx);
+    char file_name[20] = "";
+    size_t rec_size = mpp_buffer_get_size(recon_buf->buf[0]);
+    size_t dws_size = mpp_buffer_get_size(recon_buf->buf[1]);
+
+    void *ptr = mpp_buffer_get_ptr(recon_buf->buf[0]);
+    void *dws_ptr = mpp_buffer_get_ptr(recon_buf->buf[1]);
+
+    sprintf(&file_name[0], "fbd%d.bin", frm_num);
+    if (fp_fbd != NULL) {
+        fclose(fp_fbd);
+        fp_fbd = NULL;
+    } else {
+        fp_fbd = fopen(file_name, "wb+");
+    }
+    if (fp_fbd) {
+        fwrite(ptr + ctx->fbc_header_len, 1, rec_size - ctx->fbc_header_len, fp_fbd);
+        fflush(fp_fbd);
+    }
+
+    sprintf(&file_name[0], "fbh%d.bin", frm_num);
+
+    if (fp_fbh != NULL) {
+        fclose(fp_fbh);
+        fp_fbh = NULL;
+    } else {
+        fp_fbh = fopen(file_name, "wb+");
+    }
+
+    if (fp_fbh) {
+        fwrite(ptr , 1, ctx->fbc_header_len, fp_fbh);
+        fflush(fp_fbh);
+    }
+
+    sprintf(&file_name[0], "dws%d.bin", frm_num);
+
+    if (fp_dws != NULL) {
+        fclose(fp_dws);
+        fp_dws = NULL;
+    } else {
+        fp_dws = fopen(file_name, "wb+");
+    }
+
+    if (fp_dws) {
+        fwrite(dws_ptr , 1, dws_size, fp_dws);
+        fflush(fp_dws);
+    }
+    frm_num++;
+#endif
+    if (ret)
+        mpp_err_f("poll cmd failed %d status %d \n", ret, elem->hw_status);
+
+    hal_h265e_leave();
+    return ret;
+}
+
+MPP_RET hal_h265e_v510_get_task(void *hal, HalEncTask *task)
+{
+    H265eV510HalContext *ctx = (H265eV510HalContext *)hal;
+    Vepu510H265eFrmCfg *frm_cfg = NULL;
+    MppFrame frame = task->frame;
+    EncFrmStatus  *frm_status = &task->rc_task->frm;
+    RK_S32 task_idx = ctx->task_idx;
+
+    hal_h265e_enter();
+
+    ctx->syn = (H265eSyntax_new *)task->syntax.data;
+    ctx->dpb = (H265eDpb*)ctx->syn->dpb;
+    ctx->smart_en = (ctx->cfg->rc.rc_mode == MPP_ENC_RC_MODE_SMTRC);
+    ctx->qpmap_en = ctx->cfg->tune.deblur_en;
+
+    if (vepu510_h265_setup_hal_bufs(ctx)) {
+        hal_h265e_err("vepu541_h265_allocate_buffers failed, free buffers and return\n");
+        task->flags.err |= HAL_ENC_TASK_ERR_ALLOC;
+        return MPP_ERR_MALLOC;
+    }
+
+    ctx->last_frame_type = ctx->frame_type;
+    frm_cfg = ctx->frms[task_idx];
+    ctx->frm = frm_cfg;
+
+    if (frm_status->is_intra) {
+        ctx->frame_type = INTRA_FRAME;
+    } else {
+        ctx->frame_type = INTER_P_FRAME;
+    }
+
+    if (!frm_status->reencode && mpp_frame_has_meta(task->frame)) {
+        MppMeta meta = mpp_frame_get_meta(frame);
+
+        mpp_meta_get_ptr(meta, KEY_ROI_DATA, (void **)&ctx->roi_data);
+    }
+
+    task->flags.reg_idx = ctx->task_idx;
+    ctx->ext_line_buf = ctx->ext_line_bufs[ctx->task_idx];
+    frm_cfg->frame_count = ctx->frame_count++;
+
+    ctx->task_idx++;
+    if (ctx->task_idx >= ctx->task_cnt)
+        ctx->task_idx = 0;
+
+    frm_cfg->hal_curr_idx = ctx->syn->sp.recon_pic.slot_idx;
+    frm_cfg->hal_refr_idx = ctx->syn->sp.ref_pic.slot_idx;
+
+    h265e_dpb_hal_start(ctx->dpb, frm_cfg->hal_curr_idx);
+    h265e_dpb_hal_start(ctx->dpb, frm_cfg->hal_refr_idx);
+
+    memset(&frm_cfg->feedback, 0, sizeof(Vepu510H265Fbk));
+
+    hal_h265e_leave();
+    return MPP_OK;
+}
+
+MPP_RET hal_h265e_v510_ret_task(void *hal, HalEncTask *task)
+{
+    H265eV510HalContext *ctx = (H265eV510HalContext *)hal;
+    HalEncTask *enc_task = task;
+    RK_S32 task_idx = task->flags.reg_idx;
+    Vepu510H265eFrmCfg *frm = ctx->frms[task_idx];
+    Vepu510H265Fbk *fb = &frm->feedback;
+    EncRcTaskInfo *rc_info = &task->rc_task->info;
+    RK_U32 offset = mpp_packet_get_length(enc_task->packet);
+
+    hal_h265e_enter();
+
+    vepu510_h265_set_feedback(ctx, enc_task);
+    mpp_buffer_sync_partial_begin(enc_task->output, offset, fb->out_strm_size);
+    hal_h265e_amend_temporal_id(task, fb->out_strm_size);
+
+    rc_info->sse = fb->sse_sum;
+    rc_info->lvl64_inter_num = fb->st_lvl64_inter_num;
+    rc_info->lvl32_inter_num = fb->st_lvl32_inter_num;
+    rc_info->lvl16_inter_num = fb->st_lvl16_inter_num;
+    rc_info->lvl8_inter_num  = fb->st_lvl8_inter_num;
+    rc_info->lvl32_intra_num = fb->st_lvl32_intra_num;
+    rc_info->lvl16_intra_num = fb->st_lvl16_intra_num;
+    rc_info->lvl8_intra_num  = fb->st_lvl8_intra_num;
+    rc_info->lvl4_intra_num  = fb->st_lvl4_intra_num;
+
+    enc_task->hw_length = fb->out_strm_size;
+    enc_task->length += fb->out_strm_size;
+
+    h265e_dpb_hal_end(ctx->dpb, frm->hal_curr_idx);
+    h265e_dpb_hal_end(ctx->dpb, frm->hal_refr_idx);
+
+    vepu510_h265e_tune_stat_update(ctx->tune, enc_task);
+
+    hal_h265e_dbg_detail("output stream size %d\n", fb->out_strm_size);
+    hal_h265e_leave();
+    return MPP_OK;
+}
+
+const MppEncHalApi hal_h265e_vepu510 = {
+    "hal_h265e_v510",
+    MPP_VIDEO_CodingHEVC,
+    sizeof(H265eV510HalContext),
+    0,
+    hal_h265e_v510_init,
+    hal_h265e_v510_deinit,
+    hal_h265e_vepu510_prepare,
+    hal_h265e_v510_get_task,
+    hal_h265e_v510_gen_regs,
+    hal_h265e_v510_start,
+    hal_h265e_v510_wait,
+    NULL,
+    NULL,
+    hal_h265e_v510_ret_task,
+};
diff --git a/mpp/hal/rkenc/h265e/hal_h265e_vepu510.h b/mpp/hal/rkenc/h265e/hal_h265e_vepu510.h
new file mode 100644
index 000000000..81c7cf4d4
--- /dev/null
+++ b/mpp/hal/rkenc/h265e/hal_h265e_vepu510.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef __HAL_H265E_VEPU510_H__
+#define __HAL_H265E_VEPU510_H__
+
+#include "mpp_enc_hal.h"
+
+extern const MppEncHalApi hal_h265e_vepu510;
+
+#endif /* __HAL_H265E_VEPU510_H__ */
diff --git a/mpp/hal/rkenc/h265e/hal_h265e_vepu510_reg.h b/mpp/hal/rkenc/h265e/hal_h265e_vepu510_reg.h
new file mode 100644
index 000000000..d658b3af9
--- /dev/null
+++ b/mpp/hal/rkenc/h265e/hal_h265e_vepu510_reg.h
@@ -0,0 +1,822 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef __HAL_H265E_VEPU510_REG_H__
+#define __HAL_H265E_VEPU510_REG_H__
+
+#include "rk_type.h"
+#include "vepu510_common.h"
+
+typedef struct PreCstPar_t {
+    struct {
+        RK_U32 madi_thd0    : 7;
+        RK_U32 reserved     : 1;
+        RK_U32 madi_thd1    : 7;
+        RK_U32 reserved1    : 1;
+        RK_U32 madi_thd2    : 7;
+        RK_U32 reserved2    : 1;
+        RK_U32 madi_thd3    : 7;
+        RK_U32 reserved3    : 1;
+    } cst_madi_thd0;
+
+    /* 0x000020c4 reg2097 */
+    struct {
+        RK_U32 madi_thd4    : 7;
+        RK_U32 reserved     : 1;
+        RK_U32 madi_thd5    : 7;
+        RK_U32 reserved1    : 1;
+        RK_U32 madi_thd6    : 7;
+        RK_U32 reserved2    : 1;
+        RK_U32 madi_thd7    : 7;
+        RK_U32 reserved3    : 1;
+    } cst_madi_thd1;
+
+    /* 0x000020c8 reg2098 */
+    struct {
+        RK_U32 madi_thd8    : 7;
+        RK_U32 reserved     : 1;
+        RK_U32 madi_thd9    : 7;
+        RK_U32 reserved1    : 1;
+        RK_U32 madi_thd10   : 7;
+        RK_U32 reserved2    : 1;
+        RK_U32 madi_thd11   : 7;
+        RK_U32 reserved3    : 1;
+    } cst_madi_thd2;
+
+    /* 0x000020cc reg2099 */
+    struct {
+        RK_U32 madi_thd12   : 7;
+        RK_U32 reserved     : 1;
+        RK_U32 madi_thd13   : 7;
+        RK_U32 reserved1    : 1;
+        RK_U32 mode_th      : 3;
+        RK_U32 reserved2    : 1;
+        RK_U32 qp_thd       : 6;
+        RK_U32 reserved3    : 6;
+    } cst_madi_thd3;
+
+    /* 0x000020d0 reg2100 */
+    struct {
+        RK_U32 wgt0    : 8;
+        RK_U32 wgt1    : 8;
+        RK_U32 wgt2    : 8;
+        RK_U32 wgt3    : 8;
+    } cst_wgt0;
+
+    /* 0x000020d4 reg2101 */
+    struct {
+        RK_U32 wgt4    : 8;
+        RK_U32 wgt5    : 8;
+        RK_U32 wgt6    : 8;
+        RK_U32 wgt7    : 8;
+    } cst_wgt1;
+
+    /* 0x000020d8 reg2102 */
+    struct {
+        RK_U32 wgt8     : 8;
+        RK_U32 wgt9     : 8;
+        RK_U32 wgt10    : 8;
+        RK_U32 wgt11    : 8;
+    } cst_wgt2;
+
+    /* 0x000020dc reg2103 */
+    struct {
+        RK_U32 wgt12            : 8;
+        RK_U32 wgt13            : 8;
+        RK_U32 wgt14            : 8;
+        RK_U32 lambda_mv_bit_0  : 3;
+        RK_U32 reserved         : 1;
+        RK_U32 lambda_mv_bit_1  : 3;
+        RK_U32 anti_strp_e      : 1;
+    } cst_wgt3;
+} pre_cst_par;
+
+/* class: buffer/video syntax */
+/* 0x00000270 reg156 - 0x000003f4 reg253*/
+typedef struct H265eVepu510Frame_t {
+    Vepu510FrmCommon    common;
+
+    /* 0x000003a0 reg232 */
+    struct {
+        RK_U32 ltm_col                        : 1;
+        RK_U32 ltm_idx0l0                     : 1;
+        RK_U32 chrm_spcl                      : 1;
+        RK_U32 cu_inter_e                     : 12;
+        RK_U32 reserved                       : 8;
+        RK_U32 ccwa_e                         : 1;
+        RK_U32 scl_lst_sel                    : 2;
+        RK_U32 lambda_qp_use_avg_cu16_flag    : 1;
+        RK_U32 yuvskip_calc_en                : 1;
+        RK_U32 atf_e                          : 1;
+        RK_U32 atr_e                          : 1;
+        RK_U32 reserved1                      : 2;
+    } rdo_cfg;
+
+    /* 0x000003a4 reg233 */
+    struct {
+        RK_U32 rdo_mark_mode    : 9;
+        RK_U32 reserved         : 23;
+    } iprd_csts;
+
+    /* 0x3a8 - 0x3ac */
+    RK_U32 reserved234_235[2];
+
+    /* 0x000003b0 reg236 */
+    struct {
+        RK_U32 nal_unit_type    : 6;
+        RK_U32 reserved         : 26;
+    } synt_nal;
+
+    /* 0x000003b4 reg237 */
+    struct {
+        RK_U32 smpl_adpt_ofst_e    : 1;
+        RK_U32 num_st_ref_pic      : 7;
+        RK_U32 lt_ref_pic_prsnt    : 1;
+        RK_U32 num_lt_ref_pic      : 6;
+        RK_U32 tmpl_mvp_e          : 1;
+        RK_U32 log2_max_poc_lsb    : 4;
+        RK_U32 strg_intra_smth     : 1;
+        RK_U32 reserved            : 11;
+    } synt_sps;
+
+    /* 0x000003b8 reg238 */
+    struct {
+        RK_U32 dpdnt_sli_seg_en       : 1;
+        RK_U32 out_flg_prsnt_flg      : 1;
+        RK_U32 num_extr_sli_hdr       : 3;
+        RK_U32 sgn_dat_hid_en         : 1;
+        RK_U32 cbc_init_prsnt_flg     : 1;
+        RK_U32 pic_init_qp            : 6;
+        RK_U32 cu_qp_dlt_en           : 1;
+        RK_U32 chrm_qp_ofst_prsn      : 1;
+        RK_U32 lp_fltr_acrs_sli       : 1;
+        RK_U32 dblk_fltr_ovrd_en      : 1;
+        RK_U32 lst_mdfy_prsnt_flg     : 1;
+        RK_U32 sli_seg_hdr_extn       : 1;
+        RK_U32 cu_qp_dlt_depth        : 2;
+        RK_U32 lpf_fltr_acrs_til      : 1;
+        RK_U32 csip_flag              : 1;
+        RK_U32 reserved               : 9;
+    } synt_pps;
+
+    /* 0x000003bc reg239 */
+    struct {
+        RK_U32 cbc_init_flg           : 1;
+        RK_U32 mvd_l1_zero_flg        : 1;
+        RK_U32 reserved               : 3;
+        RK_U32 ref_pic_lst_mdf_l0     : 1;
+        RK_U32 num_refidx_l1_act      : 2;
+        RK_U32 num_refidx_l0_act      : 2;
+        RK_U32 num_refidx_act_ovrd    : 1;
+        RK_U32 sli_sao_chrm_flg       : 1;
+        RK_U32 sli_sao_luma_flg       : 1;
+        RK_U32 sli_tmprl_mvp_e        : 1;
+        RK_U32 pic_out_flg            : 1;
+        RK_U32 sli_type               : 2;
+        RK_U32 sli_rsrv_flg           : 7;
+        RK_U32 dpdnt_sli_seg_flg      : 1;
+        RK_U32 sli_pps_id             : 6;
+        RK_U32 no_out_pri_pic         : 1;
+    } synt_sli0;
+
+    /* 0x000003c0 reg240 */
+    struct {
+        RK_U32 sp_tc_ofst_div2         : 4;
+        RK_U32 sp_beta_ofst_div2       : 4;
+        RK_U32 sli_lp_fltr_acrs_sli    : 1;
+        RK_U32 sp_dblk_fltr_dis        : 1;
+        RK_U32 dblk_fltr_ovrd_flg      : 1;
+        RK_U32 sli_cb_qp_ofst          : 5;
+        RK_U32 sli_qp                  : 6;
+        RK_U32 max_mrg_cnd             : 2;
+        RK_U32 reserved                : 1;
+        RK_U32 col_ref_idx             : 1;
+        RK_U32 col_frm_l0_flg          : 1;
+        RK_U32 lst_entry_l0            : 4;
+        RK_U32 reserved1               : 1;
+    } synt_sli1;
+
+    /* 0x000003c4 reg241 */
+    struct {
+        RK_U32 sli_poc_lsb        : 16;
+        RK_U32 sli_hdr_ext_len    : 9;
+        RK_U32 reserved           : 7;
+    } synt_sli2;
+
+    /* 0x000003c8 reg242 */
+    struct {
+        RK_U32 st_ref_pic_flg    : 1;
+        RK_U32 poc_lsb_lt0       : 16;
+        RK_U32 lt_idx_sps        : 5;
+        RK_U32 num_lt_pic        : 2;
+        RK_U32 st_ref_pic_idx    : 6;
+        RK_U32 num_lt_sps        : 2;
+    } synt_refm0;
+
+    /* 0x000003cc reg243 */
+    struct {
+        RK_U32 used_by_s0_flg        : 4;
+        RK_U32 num_pos_pic           : 1;
+        RK_U32 num_negative_pics     : 5;
+        RK_U32 dlt_poc_msb_cycl0     : 16;
+        RK_U32 dlt_poc_msb_prsnt0    : 1;
+        RK_U32 dlt_poc_msb_prsnt1    : 1;
+        RK_U32 dlt_poc_msb_prsnt2    : 1;
+        RK_U32 used_by_lt_flg0       : 1;
+        RK_U32 used_by_lt_flg1       : 1;
+        RK_U32 used_by_lt_flg2       : 1;
+    } synt_refm1;
+
+    /* 0x000003d0 reg244 */
+    struct {
+        RK_U32 dlt_poc_s0_m10    : 16;
+        RK_U32 dlt_poc_s0_m11    : 16;
+    } synt_refm2;
+
+    /* 0x000003d4 reg245 */
+    struct {
+        RK_U32 dlt_poc_s0_m12    : 16;
+        RK_U32 dlt_poc_s0_m13    : 16;
+    } synt_refm3;
+
+    /* 0x000003d8 reg246 */
+    struct {
+        RK_U32 poc_lsb_lt1    : 16;
+        RK_U32 poc_lsb_lt2    : 16;
+    } synt_long_refm0;
+
+    /* 0x000003dc reg247 */
+    struct {
+        RK_U32 dlt_poc_msb_cycl1    : 16;
+        RK_U32 dlt_poc_msb_cycl2    : 16;
+    } synt_long_refm1;
+
+    struct {
+        RK_U32 sao_lambda_multi    : 3;
+        RK_U32 reserved            : 29;
+    } sao_cfg;
+
+    /* 0x3e4 - 0x3ec */
+    RK_U32 reserved249_251[3];
+
+    /* 0x000003f0 reg252 */
+    struct {
+        RK_U32 tile_w_m1    : 9;
+        RK_U32 reserved     : 7;
+        RK_U32 tile_h_m1    : 9;
+        RK_U32 reserved1    : 6;
+        RK_U32 tile_en      : 1;
+    } tile_cfg;
+
+    /* 0x000003f4 reg253 */
+    struct {
+        RK_U32 tile_x       : 9;
+        RK_U32 reserved     : 7;
+        RK_U32 tile_y       : 9;
+        RK_U32 reserved1    : 7;
+    } tile_pos_hevc;
+} H265eVepu510Frame;
+
+/* class: param */
+/* 0x00001700 reg1472 - 0x000019cc reg1651 */
+typedef struct H265eVepu510Param_t {
+    /* 0x00001700 reg1472 - 0x0000172c reg1483*/
+    RK_U32 reserved_1472_1483[12];
+
+    /* 0x00001730 reg1484 */
+    struct {
+        RK_U32    qnt_f_bias_i  : 10;
+        RK_U32    qnt_f_bias_p  : 10;
+        RK_U32    reserve       : 12;
+    } qnt_bias_comb;
+
+    /* 0x00001734 reg1485 - 0x0000175c reg1495*/
+    RK_U32 reserved1485_1495[11];
+
+    /* 0x00001760 reg1496 */
+    struct {
+        RK_U32 cime_pmv_num      : 1;
+        RK_U32 cime_fuse         : 1;
+        RK_U32 itp_mode          : 1;
+        RK_U32 reserved          : 1;
+        RK_U32 move_lambda       : 4;
+        RK_U32 rime_lvl_mrg      : 2;
+        RK_U32 rime_prelvl_en    : 2;
+        RK_U32 rime_prersu_en    : 3;
+        RK_U32 reserved1         : 17;
+    } me_sqi_comb;
+
+    /* 0x00001764 reg1497 */
+    struct {
+        RK_U32 cime_mvd_th0    : 9;
+        RK_U32 reserved        : 1;
+        RK_U32 cime_mvd_th1    : 9;
+        RK_U32 reserved1       : 1;
+        RK_U32 cime_mvd_th2    : 9;
+        RK_U32 reserved2       : 3;
+    }  cime_mvd_th_comb;
+
+    /* 0x00001768 reg1498 */
+    struct {
+        RK_U32 cime_madp_th    : 12;
+        RK_U32 reserved        : 20;
+    } cime_madp_th_comb;
+
+    /* 0x0000176c reg1499 */
+    struct {
+        RK_U32 cime_multi0    : 8;
+        RK_U32 cime_multi1    : 8;
+        RK_U32 cime_multi2    : 8;
+        RK_U32 cime_multi3    : 8;
+    } cime_multi_comb;
+
+    /* 0x00001770 reg1500 */
+    struct {
+        RK_U32 rime_mvd_th0    : 3;
+        RK_U32 reserved        : 1;
+        RK_U32 rime_mvd_th1    : 3;
+        RK_U32 reserved1       : 9;
+        RK_U32 fme_madp_th     : 12;
+        RK_U32 reserved2       : 4;
+    } rime_mvd_th_comb;
+
+    /* 0x00001774 reg1501 */
+    struct {
+        RK_U32 rime_madp_th0    : 12;
+        RK_U32 reserved         : 4;
+        RK_U32 rime_madp_th1    : 12;
+        RK_U32 reserved1        : 4;
+    } rime_madp_th_comb;
+
+    /* 0x00001778 reg1502 */
+    struct {
+        RK_U32 rime_multi0    : 10;
+        RK_U32 rime_multi1    : 10;
+        RK_U32 rime_multi2    : 10;
+        RK_U32 reserved       : 2;
+    } rime_multi_comb;
+
+    /* 0x0000177c reg1503 */
+    struct {
+        RK_U32 cmv_th0     : 8;
+        RK_U32 cmv_th1     : 8;
+        RK_U32 cmv_th2     : 8;
+        RK_U32 reserved    : 8;
+    } cmv_st_th_comb;
+
+    /* 0x1780 - 0x17fc */
+    RK_U32 reserved1504_1535[32];
+
+    /* 0x00001800 reg1536 - 0x000018cc reg1587*/
+    RK_U32 pprd_lamb_satd_0_51[52];
+
+    /* 0x000018d0 reg1588 */
+    struct {
+        RK_U32 lambda_satd_offset    : 5;
+        RK_U32 reserved              : 27;
+    } iprd_lamb_satd_ofst;
+
+    /* 0x18d4 - 0x18fc */
+    RK_U32 reserved1589_1599[11];
+
+    /* 0x00001900 reg1600 - 0x000019cc reg1651*/
+    RK_U32 rdo_wgta_qp_grpa_0_51[52];
+} H265eVepu510Param;
+
+/* class: rdo/q_i */
+/* 0x00002000 reg2048 - 0x000020fc reg2111 */
+typedef struct H265eVepu510SqiCfg_t {
+    /* 0x00002000 reg2048 */
+    struct {
+        RK_U32 subj_opt_en            : 1;
+        RK_U32 subj_opt_strength      : 3;
+        RK_U32 aq_subj_en             : 1;
+        RK_U32 aq_subj_strength       : 3;
+        RK_U32 reserved               : 4;
+        RK_U32 thre_sum_grdn_point    : 20;
+    } subj_opt_cfg;
+
+    /* 0x00002004 reg2049 */
+    struct {
+        RK_U32 common_thre_num_grdn_point_dep0    : 8;
+        RK_U32 common_thre_num_grdn_point_dep1    : 8;
+        RK_U32 common_thre_num_grdn_point_dep2    : 8;
+        RK_U32 reserved                           : 8;
+    } subj_opt_dpth_thd;
+
+    /* 0x00002008 reg2050 */
+    struct {
+        RK_U32 common_rdo_cu_intra_r_coef_dep0    : 8;
+        RK_U32 common_rdo_cu_intra_r_coef_dep1    : 8;
+        RK_U32 reserved                           : 16;
+    } subj_opt_inrar_coef;
+
+    /* 0x200c */
+    RK_U32 reserved_2051;
+
+    /* 0x00002010 reg2052 */
+    struct {
+        RK_U32 anti_smear_en                  : 1;
+        RK_U32 frm_static                     : 1;
+        RK_U32 smear_stor_en                  : 1;
+        RK_U32 smear_load_en                  : 1;
+        RK_U32 smear_strength                 : 3;
+        RK_U32 reserved                       : 1;
+        RK_U32 thre_mv_inconfor_cime          : 4;
+        RK_U32 thre_mv_confor_cime            : 2;
+        RK_U32 thre_mv_confor_cime_gmv        : 2;
+        RK_U32 thre_mv_inconfor_cime_gmv      : 4;
+        RK_U32 thre_num_mv_confor_cime        : 2;
+        RK_U32 thre_num_mv_confor_cime_gmv    : 2;
+        RK_U32 reserved1                      : 8;
+    } smear_opt_cfg0;
+
+    /* 0x00002014 reg2053 */
+    struct {
+        RK_U32 dist0_frm_avg               : 14;
+        RK_U32 thre_dsp_static             : 5;
+        RK_U32 thre_dsp_mov                : 5;
+        RK_U32 thre_dist_mv_confor_cime    : 7;
+        RK_U32 reserved                    : 1;
+    } smear_opt_cfg1;
+
+    /* 0x00002018 reg2054 */
+    struct {
+        RK_U32 thre_madp_stc_dep0    : 4;
+        RK_U32 thre_madp_stc_dep1    : 4;
+        RK_U32 thre_madp_stc_dep2    : 4;
+        RK_U32 thre_madp_mov_dep0    : 6;
+        RK_U32 thre_madp_mov_dep1    : 6;
+        RK_U32 thre_madp_mov_dep2    : 6;
+        RK_U32 reserved              : 2;
+    } smear_madp_thd;
+
+    /* 0x0000201c reg2055 */
+    struct {
+        RK_U32 thre_num_pt_stc_dep0    : 6;
+        RK_U32 thre_num_pt_stc_dep1    : 4;
+        RK_U32 thre_num_pt_stc_dep2    : 2;
+        RK_U32 reserved                : 4;
+        RK_U32 thre_num_pt_mov_dep0    : 6;
+        RK_U32 thre_num_pt_mov_dep1    : 4;
+        RK_U32 thre_num_pt_mov_dep2    : 2;
+        RK_U32 reserved1               : 4;
+    } smear_stat_thd;
+
+    /* 0x00002020 reg2056 */
+    struct {
+        RK_U32 thre_ratio_dist_mv_confor_cime_gmv0      : 5;
+        RK_U32 reserved                                 : 3;
+        RK_U32 thre_ratio_dist_mv_confor_cime_gmv1      : 5;
+        RK_U32 reserved1                                : 3;
+        RK_U32 thre_ratio_dist_mv_inconfor_cime_gmv0    : 6;
+        RK_U32 reserved2                                : 2;
+        RK_U32 thre_ratio_dist_mv_inconfor_cime_gmv1    : 6;
+        RK_U32 reserved3                                : 2;
+    } smear_bmv_dist_thd0;
+
+    /* 0x00002024 reg2057 */
+    struct {
+        RK_U32 thre_ratio_dist_mv_inconfor_cime_gmv2    : 6;
+        RK_U32 reserved                                 : 2;
+        RK_U32 thre_ratio_dist_mv_inconfor_cime_gmv3    : 6;
+        RK_U32 reserved1                                : 2;
+        RK_U32 thre_ratio_dist_mv_inconfor_cime_gmv4    : 6;
+        RK_U32 reserved2                                : 10;
+    } smear_bmv_dist_thd1;
+
+    /* 0x00002028 reg2058 */
+    struct {
+        RK_U32 thre_min_num_confor_csu0_bndry_cime_gmv      : 2;
+        RK_U32 thre_max_num_confor_csu0_bndry_cime_gmv      : 2;
+        RK_U32 thre_min_num_inconfor_csu0_bndry_cime_gmv    : 2;
+        RK_U32 thre_max_num_inconfor_csu0_bndry_cime_gmv    : 2;
+        RK_U32 thre_split_dep0                              : 2;
+        RK_U32 thre_zero_srgn                               : 5;
+        RK_U32 reserved                                     : 1;
+        RK_U32 madi_thre_dep0                               : 8;
+        RK_U32 madi_thre_dep1                               : 8;
+    } smear_min_bndry_gmv;
+
+    /* 0x0000202c reg2059 */
+    struct {
+        RK_U32 thre_madp_stc_cover0    : 6;
+        RK_U32 thre_madp_stc_cover1    : 6;
+        RK_U32 thre_madp_mov_cover0    : 5;
+        RK_U32 thre_madp_mov_cover1    : 5;
+        RK_U32 smear_qp_strength       : 4;
+        RK_U32 smear_thre_qp           : 6;
+    } smear_madp_cov_thd;
+
+    /* 0x00002030 reg2060 */
+    struct {
+        RK_U32 skin_en                        : 1;
+        RK_U32 skin_strength                  : 3;
+        RK_U32 thre_uvsqr16_skin              : 8;
+        RK_U32 skin_thre_cst_best_mad         : 10;
+        RK_U32 skin_thre_cst_best_grdn_blk    : 7;
+        RK_U32 reserved                       : 1;
+        RK_U32 frame_skin_ratio               : 2;
+    } skin_opt_cfg;
+
+    /* 0x00002034 reg2061 */
+    struct {
+        RK_U32 thre_sum_mad_intra         : 2;
+        RK_U32 thre_sum_grdn_blk_intra    : 2;
+        RK_U32 vld_thre_skin_v            : 3;
+        RK_U32 reserved                   : 1;
+        RK_U32 thre_min_skin_u            : 8;
+        RK_U32 thre_max_skin_u            : 8;
+        RK_U32 thre_min_skin_v            : 8;
+    } skin_chrm_thd;
+
+    /* 0x00002038 reg2062 */
+    struct {
+        RK_U32 block_en                        : 1;
+        RK_U32 reserved                        : 1;
+        RK_U32 block_thre_cst_best_mad         : 10;
+        RK_U32 reserved1                       : 4;
+        RK_U32 block_thre_cst_best_grdn_blk    : 6;
+        RK_U32 reserved2                       : 2;
+        RK_U32 thre_num_grdnt_point_cmplx      : 2;
+        RK_U32 block_delta_qp_flag             : 2;
+        RK_U32 reserved3                       : 4;
+    } block_opt_cfg;
+
+    /* 0x0000203c reg2063 */
+    struct {
+        RK_U32 cmplx_thre_cst_best_mad_dep0    : 13;
+        RK_U32 reserved                        : 3;
+        RK_U32 cmplx_thre_cst_best_mad_dep1    : 13;
+        RK_U32 reserved1                       : 2;
+        RK_U32 cmplx_en                        : 1;
+    } cmplx_opt_cfg;
+
+    /* 0x00002040 reg2064 */
+    struct {
+        RK_U32 cmplx_thre_cst_best_mad_dep2         : 13;
+        RK_U32 reserved                             : 3;
+        RK_U32 cmplx_thre_cst_best_grdn_blk_dep0    : 11;
+        RK_U32 reserved1                            : 5;
+    } cmplx_bst_mad_thd;
+
+    /* 0x00002044 reg2065 */
+    struct {
+        RK_U32 cmplx_thre_cst_best_grdn_blk_dep1    : 11;
+        RK_U32 reserved                             : 5;
+        RK_U32 cmplx_thre_cst_best_grdn_blk_dep2    : 11;
+        RK_U32 reserved1                            : 5;
+    } cmplx_bst_grdn_thd;
+
+    /* 0x00002048 reg2066 */
+    struct {
+        RK_U32 line_en                                 : 1;
+        RK_U32 line_thre_min_cst_best_grdn_blk_dep0    : 5;
+        RK_U32 line_thre_min_cst_best_grdn_blk_dep1    : 5;
+        RK_U32 line_thre_min_cst_best_grdn_blk_dep2    : 5;
+        RK_U32 line_thre_ratio_best_grdn_blk_dep0      : 4;
+        RK_U32 line_thre_ratio_best_grdn_blk_dep1      : 4;
+        RK_U32 reserved                                : 8;
+    } line_opt_cfg;
+
+    /* 0x0000204c reg2067 */
+    struct {
+        RK_U32 line_thre_max_cst_best_grdn_blk_dep0    : 7;
+        RK_U32 reserved                                : 1;
+        RK_U32 line_thre_max_cst_best_grdn_blk_dep1    : 7;
+        RK_U32 reserved1                               : 1;
+        RK_U32 line_thre_max_cst_best_grdn_blk_dep2    : 7;
+        RK_U32 reserved2                               : 9;
+    } line_cst_bst_grdn;
+
+    /* 0x00002050 reg2068 */
+    struct {
+        RK_U32 line_thre_qp               : 6;
+        RK_U32 block_strength             : 3;
+        RK_U32 block_thre_qp              : 6;
+        RK_U32 cmplx_strength             : 3;
+        RK_U32 cmplx_thre_qp              : 6;
+        RK_U32 cmplx_thre_max_grdn_blk    : 6;
+        RK_U32 reserved                   : 2;
+    } subj_opt_dqp0;
+
+    /* 0x00002054 reg2069 */
+    struct {
+        RK_U32 skin_thre_qp                      : 6;
+        RK_U32 reserved                          : 2;
+        RK_U32 bndry_rdo_cu_intra_r_coef_dep0    : 8;
+        RK_U32 bndry_rdo_cu_intra_r_coef_dep1    : 8;
+        RK_U32 reserved1                         : 8;
+    } subj_opt_dqp1;
+
+    /* 0x2058 - 0x205c */
+    RK_U32 reserved2070_2071[2];
+
+    /* 0x00002060 reg2072 - 0x0000206c reg2075 */
+    rdo_skip_par rdo_b32_skip;
+
+    /* 0x00002070 reg2076 - 0x0000207c reg2079*/
+    rdo_skip_par rdo_b16_skip;
+
+    /* 0x00002080 reg2080 - 0x00002088 reg2082 */
+    rdo_noskip_par rdo_b32_inter;
+
+    /* 0x0000208c reg2083 - 0x00002094 reg2085 */
+    rdo_noskip_par rdo_b16_inter;
+
+    /* 0x00002098 reg2086 - 0x000020a4 reg2088 */
+    rdo_noskip_par rdo_b32_intra;
+
+    /* 0x000020a8 reg2089 - 0x000020ac reg2091 */
+    rdo_noskip_par rdo_b16_intra;
+
+    /* 0x000020b0 reg2092 */
+    struct {
+        RK_U32 blur_low_madi_thd     : 7;
+        RK_U32 reserved              : 1;
+        RK_U32 blur_high_madi_thd    : 7;
+        RK_U32 reserved1             : 1;
+        RK_U32 blur_low_cnt_thd      : 4;
+        RK_U32 blur_hight_cnt_thd    : 4;
+        RK_U32 blur_sum_cnt_thd      : 4;
+        RK_U32 anti_blur_en          : 1;
+        RK_U32 reserved2             : 3;
+    } subj_anti_blur_thd;
+
+    /* 0x000020b4 reg2093 */
+    struct {
+        RK_U32 blur_motion_thd           : 12;
+        RK_U32 sao_ofst_thd_eo_luma      : 3;
+        RK_U32 reserved                  : 1;
+        RK_U32 sao_ofst_thd_bo_luma      : 3;
+        RK_U32 reserved1                 : 1;
+        RK_U32 sao_ofst_thd_eo_chroma    : 3;
+        RK_U32 reserved2                 : 1;
+        RK_U32 sao_ofst_thd_bo_chroma    : 3;
+        RK_U32 reserved3                 : 5;
+    } subj_anti_blur_sao;
+
+    /* 0x000020b8 reg2094 - 0x000020bc reg2095*/
+    RK_U32 reserved_2094_2095[2];
+
+    /* 0x000020c0 reg2096 - 0x000020dc reg2103 */
+    pre_cst_par preintra32_cst;
+
+    /* 0x000020e0 reg2104 - 0x000020fc reg2111 */
+    pre_cst_par preintra16_cst;
+
+    /* 0x00002100 reg2112 */
+    struct {
+        RK_U32 base_thre_rough_mad32_intra           : 4;
+        RK_U32 delta0_thre_rough_mad32_intra         : 4;
+        RK_U32 delta1_thre_rough_mad32_intra         : 6;
+        RK_U32 delta2_thre_rough_mad32_intra         : 6;
+        RK_U32 delta3_thre_rough_mad32_intra         : 7;
+        RK_U32 delta4_thre_rough_mad32_intra_low5    : 5;
+    } cudecis_thd0;
+
+    /* 0x00002104 reg2113 */
+    struct {
+        RK_U32 delta4_thre_rough_mad32_intra_high2    : 2;
+        RK_U32 delta5_thre_rough_mad32_intra          : 7;
+        RK_U32 delta6_thre_rough_mad32_intra          : 7;
+        RK_U32 base_thre_fine_mad32_intra             : 4;
+        RK_U32 delta0_thre_fine_mad32_intra           : 4;
+        RK_U32 delta1_thre_fine_mad32_intra           : 5;
+        RK_U32 delta2_thre_fine_mad32_intra_low3      : 3;
+    } cudecis_thd1;
+
+    /* 0x00002108 reg2114 */
+    struct {
+        RK_U32 delta2_thre_fine_mad32_intra_high2    : 2;
+        RK_U32 delta3_thre_fine_mad32_intra          : 5;
+        RK_U32 delta4_thre_fine_mad32_intra          : 5;
+        RK_U32 delta5_thre_fine_mad32_intra          : 6;
+        RK_U32 delta6_thre_fine_mad32_intra          : 6;
+        RK_U32 base_thre_str_edge_mad32_intra        : 3;
+        RK_U32 delta0_thre_str_edge_mad32_intra      : 2;
+        RK_U32 delta1_thre_str_edge_mad32_intra      : 3;
+    } cudecis_thd2;
+
+    /* 0x0000210c reg2115 */
+    struct {
+        RK_U32 delta2_thre_str_edge_mad32_intra      : 3;
+        RK_U32 delta3_thre_str_edge_mad32_intra      : 4;
+        RK_U32 base_thre_str_edge_bgrad32_intra      : 5;
+        RK_U32 delta0_thre_str_edge_bgrad32_intra    : 2;
+        RK_U32 delta1_thre_str_edge_bgrad32_intra    : 3;
+        RK_U32 delta2_thre_str_edge_bgrad32_intra    : 4;
+        RK_U32 delta3_thre_str_edge_bgrad32_intra    : 5;
+        RK_U32 base_thre_mad16_intra                 : 3;
+        RK_U32 delta0_thre_mad16_intra               : 3;
+    } cudecis_thd3;
+
+    /* 0x00002110 reg2116 */
+    struct {
+        RK_U32 delta1_thre_mad16_intra          : 3;
+        RK_U32 delta2_thre_mad16_intra          : 4;
+        RK_U32 delta3_thre_mad16_intra          : 5;
+        RK_U32 delta4_thre_mad16_intra          : 5;
+        RK_U32 delta5_thre_mad16_intra          : 6;
+        RK_U32 delta6_thre_mad16_intra          : 6;
+        RK_U32 delta0_thre_mad16_ratio_intra    : 3;
+    } cudecis_thd4;
+
+    /* 0x00002114 reg2117 */
+    struct {
+        RK_U32 delta1_thre_mad16_ratio_intra           : 3;
+        RK_U32 delta2_thre_mad16_ratio_intra           : 3;
+        RK_U32 delta3_thre_mad16_ratio_intra           : 3;
+        RK_U32 delta4_thre_mad16_ratio_intra           : 3;
+        RK_U32 delta5_thre_mad16_ratio_intra           : 3;
+        RK_U32 delta6_thre_mad16_ratio_intra           : 3;
+        RK_U32 delta7_thre_mad16_ratio_intra           : 3;
+        RK_U32 delta0_thre_rough_bgrad32_intra         : 3;
+        RK_U32 delta1_thre_rough_bgrad32_intra         : 4;
+        RK_U32 delta2_thre_rough_bgrad32_intra_low4    : 4;
+    } cudecis_thd5;
+
+    /* 0x00002118 reg2118 */
+    struct {
+        RK_U32 delta2_thre_rough_bgrad32_intra_high2    : 2;
+        RK_U32 delta3_thre_rough_bgrad32_intra          : 10;
+        RK_U32 delta4_thre_rough_bgrad32_intra          : 10;
+        RK_U32 delta5_thre_rough_bgrad32_intra_low10    : 10;
+    } cudecis_thd6;
+
+    /* 0x0000211c reg2119 */
+    struct {
+        RK_U32 delta5_thre_rough_bgrad32_intra_high1    : 1;
+        RK_U32 delta6_thre_rough_bgrad32_intra          : 12;
+        RK_U32 delta7_thre_rough_bgrad32_intra          : 13;
+        RK_U32 delta0_thre_bgrad16_ratio_intra          : 4;
+        RK_U32 delta1_thre_bgrad16_ratio_intra_low2     : 2;
+    } cudecis_thd7;
+
+    /* 0x00002120 reg2120 */
+    struct {
+        RK_U32 delta1_thre_bgrad16_ratio_intra_high2    : 2;
+        RK_U32 delta2_thre_bgrad16_ratio_intra          : 4;
+        RK_U32 delta3_thre_bgrad16_ratio_intra          : 4;
+        RK_U32 delta4_thre_bgrad16_ratio_intra          : 4;
+        RK_U32 delta5_thre_bgrad16_ratio_intra          : 4;
+        RK_U32 delta6_thre_bgrad16_ratio_intra          : 4;
+        RK_U32 delta7_thre_bgrad16_ratio_intra          : 4;
+        RK_U32 delta0_thre_fme_ratio_inter              : 3;
+        RK_U32 delta1_thre_fme_ratio_inter              : 3;
+    } cudecis_thdt8;
+
+    /* 0x00002124 reg2121 */
+    struct {
+        RK_U32 delta2_thre_fme_ratio_inter    : 3;
+        RK_U32 delta3_thre_fme_ratio_inter    : 3;
+        RK_U32 delta4_thre_fme_ratio_inter    : 3;
+        RK_U32 delta5_thre_fme_ratio_inter    : 3;
+        RK_U32 delta6_thre_fme_ratio_inter    : 3;
+        RK_U32 delta7_thre_fme_ratio_inter    : 3;
+        RK_U32 base_thre_fme32_inter          : 3;
+        RK_U32 delta0_thre_fme32_inter        : 3;
+        RK_U32 delta1_thre_fme32_inter        : 4;
+        RK_U32 delta2_thre_fme32_inter        : 4;
+    } cudecis_thd9;
+
+    /* 0x00002128 reg2122 */
+    struct {
+        RK_U32 delta3_thre_fme32_inter    : 5;
+        RK_U32 delta4_thre_fme32_inter    : 6;
+        RK_U32 delta5_thre_fme32_inter    : 7;
+        RK_U32 delta6_thre_fme32_inter    : 8;
+        RK_U32 thre_cme32_inter           : 6;
+    } cudecis_thd10;
+
+    /* 0x0000212c reg2123 */
+    struct {
+        RK_U32 delta0_thre_mad_fme_ratio_inter    : 4;
+        RK_U32 delta1_thre_mad_fme_ratio_inter    : 4;
+        RK_U32 delta2_thre_mad_fme_ratio_inter    : 4;
+        RK_U32 delta3_thre_mad_fme_ratio_inter    : 4;
+        RK_U32 delta4_thre_mad_fme_ratio_inter    : 4;
+        RK_U32 delta5_thre_mad_fme_ratio_inter    : 4;
+        RK_U32 delta6_thre_mad_fme_ratio_inter    : 4;
+        RK_U32 delta7_thre_mad_fme_ratio_inter    : 4;
+    } cudecis_thd11;
+} H265eVepu510Sqi;
+
+typedef struct H265eV510RegSet_t {
+    Vepu510ControlCfg         reg_ctl;
+    H265eVepu510Frame         reg_frm;
+    Vepu510RcRoi              reg_rc_roi;
+    H265eVepu510Param         reg_param;
+    H265eVepu510Sqi           reg_sqi;
+    Vepu510SclCfg             reg_scl;
+    Vepu510Dbg                reg_dbg;
+} H265eV510RegSet;
+
+typedef struct H265eV510StatusElem_t {
+    RK_U32 hw_status;
+    Vepu510Status st;
+} H265eV510StatusElem;
+
+#endif
diff --git a/mpp/hal/rkenc/h265e/hal_h265e_vepu510_tune.c b/mpp/hal/rkenc/h265e/hal_h265e_vepu510_tune.c
new file mode 100644
index 000000000..b8b325d5a
--- /dev/null
+++ b/mpp/hal/rkenc/h265e/hal_h265e_vepu510_tune.c
@@ -0,0 +1,310 @@
+/*
+ * Copyright 2024 Rockchip Electronics Co. LTD
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "hal_enc_task.h"
+#include "hal_h265e_vepu510_reg.h"
+
+typedef struct HalH265eVepu510Tune_t {
+    H265eV510HalContext *ctx;
+
+    RK_U8 *qm_mv_buf; /* qpmap move flag buffer */
+    RK_U32 qm_mv_buf_size;
+
+    RK_S32 pre_madp[2];
+    RK_S32 pre_madi[2];
+} HalH265eVepu510Tune;
+
+static RK_U32 aq_thd_default[16] = {
+    0,  0,  0,  0,  3,  3,  5,  5,
+    8,  8,  15, 15, 20, 25, 25, 25
+};
+
+static RK_S32 aq_qp_delta_default[16] = {
+    -8, -7, -6, -5, -4, -3, -2, -1,
+    1,  2,  3,  4,  5,  6,  7,  8
+};
+
+static RK_U32 aq_thd_smt_I[16] = {
+    1,  2,  3,   3,  3,  3,  5,  5,
+    8,  8,  13,  15, 20, 25, 25, 25
+};
+
+static RK_S32 aq_qp_delta_smt_I[16] = {
+    -8, -7, -6, -5, -4, -3, -2, -1,
+    1,  2,  3,  5,  7,  8,  9,  9
+};
+
+static RK_U32 aq_thd_smt_P[16] = {
+    0,  0,  0,   0,  3,  3,  5,  5,
+    8,  8,  15, 15, 20, 25, 25, 25
+};
+
+static RK_S32 aq_qp_delta_smt_P[16] = {
+    -8, -7, -6, -5, -4, -3, -2, -1,
+    1,  2,  3,  4,  6,  7,  9,  9
+};
+
+static HalH265eVepu510Tune *vepu510_h265e_tune_init(H265eV510HalContext *ctx)
+{
+    HalH265eVepu510Tune *tune = mpp_calloc(HalH265eVepu510Tune, 1);
+
+    if (NULL == tune)
+        return tune;
+
+    tune->ctx = ctx;
+    tune->pre_madi[0] = tune->pre_madi[1] = -1;
+    tune->pre_madp[0] = tune->pre_madp[1] = -1;
+
+    return tune;
+}
+
+static void vepu510_h265e_tune_deinit(void *tune)
+{
+    HalH265eVepu510Tune *t = (HalH265eVepu510Tune *)tune;
+
+    MPP_FREE(t->qm_mv_buf);
+    MPP_FREE(tune);
+}
+
+static void vepu510_h265e_tune_aq_prepare(HalH265eVepu510Tune *tune)
+{
+    if (tune == NULL) {
+        return;
+    }
+
+    H265eV510HalContext *ctx = tune->ctx;
+    MppEncHwCfg *hw = &ctx->cfg->hw;
+
+    if (ctx->smart_en) {
+        memcpy(hw->aq_thrd_i, aq_thd_smt_I, sizeof(hw->aq_thrd_i));
+        memcpy(hw->aq_thrd_p, aq_thd_smt_P, sizeof(hw->aq_thrd_p));
+        memcpy(hw->aq_step_i, aq_qp_delta_smt_I, sizeof(hw->aq_step_i));
+        memcpy(hw->aq_step_p, aq_qp_delta_smt_P, sizeof(hw->aq_step_p));
+    } else {
+        memcpy(hw->aq_thrd_i, aq_thd_default, sizeof(hw->aq_thrd_i));
+        memcpy(hw->aq_thrd_p, aq_thd_default, sizeof(hw->aq_thrd_p));
+        memcpy(hw->aq_step_i, aq_qp_delta_default, sizeof(hw->aq_step_i));
+        memcpy(hw->aq_step_p, aq_qp_delta_default, sizeof(hw->aq_step_p));
+    }
+}
+
+static void vepu510_h265e_tune_aq(HalH265eVepu510Tune *tune)
+{
+    H265eV510HalContext *ctx = tune->ctx;
+    Vepu510H265eFrmCfg *frm_cfg = ctx->frm;
+    H265eV510RegSet *regs = frm_cfg->regs_set;
+    Vepu510RcRoi *r = &regs->reg_rc_roi;
+    MppEncHwCfg *hw = &ctx->cfg->hw;
+    RK_U32 i = 0;
+    RK_S32 aq_step[16];
+
+    RK_U8 *thd  = (RK_U8 *)&r->aq_tthd0;
+    for (i = 0; i < MPP_ARRAY_ELEMS(aq_thd_default); i++) {
+        if (ctx->frame_type == INTRA_FRAME) {
+            thd[i] = hw->aq_thrd_i[i];
+            aq_step[i] = hw->aq_step_i[i] & 0x1F;
+        } else {
+            thd[i] = hw->aq_thrd_p[i];
+            aq_step[i] = hw->aq_step_p[i] & 0x1F;
+        }
+    }
+
+    r->aq_stp0.aq_stp_s0 = aq_step[0];
+    r->aq_stp0.aq_stp_0t1 = aq_step[1];
+    r->aq_stp0.aq_stp_1t2 = aq_step[2];
+    r->aq_stp0.aq_stp_2t3 = aq_step[3];
+    r->aq_stp0.aq_stp_3t4 = aq_step[4];
+    r->aq_stp0.aq_stp_4t5 = aq_step[5];
+    r->aq_stp1.aq_stp_5t6 = aq_step[6];
+    r->aq_stp1.aq_stp_6t7 = aq_step[7];
+    r->aq_stp1.aq_stp_7t8 = 0;
+    r->aq_stp1.aq_stp_8t9 = aq_step[8];
+    r->aq_stp1.aq_stp_9t10 = aq_step[9];
+    r->aq_stp1.aq_stp_10t11 = aq_step[10];
+    r->aq_stp2.aq_stp_11t12 = aq_step[11];
+    r->aq_stp2.aq_stp_12t13 = aq_step[12];
+    r->aq_stp2.aq_stp_13t14 = aq_step[13];
+    r->aq_stp2.aq_stp_14t15 = aq_step[14];
+    r->aq_stp2.aq_stp_b15 = aq_step[15];
+
+    r->aq_clip.aq16_rnge = 5;
+    r->aq_clip.aq32_rnge = 5;
+    r->aq_clip.aq8_rnge = 10;
+    r->aq_clip.aq16_dif0 = 12;
+    r->aq_clip.aq16_dif1 = 12;
+}
+
+static void vepu510_h265e_tune_reg_patch(void *p, HalEncTask *task)
+{
+    HalH265eVepu510Tune *tune = (HalH265eVepu510Tune *)p;
+    (void)task;
+
+    if (NULL == tune)
+        return;
+
+    vepu510_h265e_tune_aq(tune);
+}
+
+static void vepu510_h265e_tune_stat_update(void *p, HalEncTask *task)
+{
+    HalH265eVepu510Tune *tune = (HalH265eVepu510Tune *)p;
+    EncRcTaskInfo *hal_rc_ret = (EncRcTaskInfo *)&task->rc_task->info;
+
+    if (NULL == tune)
+        return;
+
+    H265eV510HalContext *ctx = tune->ctx;;
+    RK_S32 task_idx = task->flags.reg_idx;
+    Vepu510H265eFrmCfg *frm = ctx->frms[task_idx];
+    Vepu510H265Fbk *fb = &frm->feedback;
+    H265eV510RegSet *regs_set = frm->regs_set;
+    H265eV510StatusElem *elem = frm->regs_ret;
+    MppEncCfgSet *cfg = ctx->cfg;
+    RK_U32 b16_num = MPP_ALIGN(cfg->prep.width, 16) * MPP_ALIGN(cfg->prep.height, 16) / 256;
+    RK_U32 madi_cnt = 0, madp_cnt = 0;
+    RK_S32 i = 0;
+
+    RK_U32 madi_th_cnt0 = elem->st.st_madi_lt_num0.madi_th_lt_cnt0 +
+                          elem->st.st_madi_rt_num0.madi_th_rt_cnt0 +
+                          elem->st.st_madi_lb_num0.madi_th_lb_cnt0 +
+                          elem->st.st_madi_rb_num0.madi_th_rb_cnt0;
+    RK_U32 madi_th_cnt1 = elem->st.st_madi_lt_num0.madi_th_lt_cnt1 +
+                          elem->st.st_madi_rt_num0.madi_th_rt_cnt1 +
+                          elem->st.st_madi_lb_num0.madi_th_lb_cnt1 +
+                          elem->st.st_madi_rb_num0.madi_th_rb_cnt1;
+    RK_U32 madi_th_cnt2 = elem->st.st_madi_lt_num1.madi_th_lt_cnt2 +
+                          elem->st.st_madi_rt_num1.madi_th_rt_cnt2 +
+                          elem->st.st_madi_lb_num1.madi_th_lb_cnt2 +
+                          elem->st.st_madi_rb_num1.madi_th_rb_cnt2;
+    RK_U32 madi_th_cnt3 = elem->st.st_madi_lt_num1.madi_th_lt_cnt3 +
+                          elem->st.st_madi_rt_num1.madi_th_rt_cnt3 +
+                          elem->st.st_madi_lb_num1.madi_th_lb_cnt3 +
+                          elem->st.st_madi_rb_num1.madi_th_rb_cnt3;
+    RK_U32 madp_th_cnt0 = elem->st.st_madp_lt_num0.madp_th_lt_cnt0 +
+                          elem->st.st_madp_rt_num0.madp_th_rt_cnt0 +
+                          elem->st.st_madp_lb_num0.madp_th_lb_cnt0 +
+                          elem->st.st_madp_rb_num0.madp_th_rb_cnt0;
+    RK_U32 madp_th_cnt1 = elem->st.st_madp_lt_num0.madp_th_lt_cnt1 +
+                          elem->st.st_madp_rt_num0.madp_th_rt_cnt1 +
+                          elem->st.st_madp_lb_num0.madp_th_lb_cnt1 +
+                          elem->st.st_madp_rb_num0.madp_th_rb_cnt1;
+    RK_U32 madp_th_cnt2 = elem->st.st_madp_lt_num1.madp_th_lt_cnt2 +
+                          elem->st.st_madp_rt_num1.madp_th_rt_cnt2 +
+                          elem->st.st_madp_lb_num1.madp_th_lb_cnt2 +
+                          elem->st.st_madp_rb_num1.madp_th_rb_cnt2;
+    RK_U32 madp_th_cnt3 = elem->st.st_madp_lt_num1.madp_th_lt_cnt3 +
+                          elem->st.st_madp_rt_num1.madp_th_rt_cnt3 +
+                          elem->st.st_madp_lb_num1.madp_th_lb_cnt3 +
+                          elem->st.st_madp_rb_num1.madp_th_rb_cnt3;
+
+    madi_cnt = (6 * madi_th_cnt3 + 5 * madi_th_cnt2 + 4 * madi_th_cnt1) >> 2;
+    hal_rc_ret->complex_level = (madi_cnt * 100 > 30 * b16_num) ? 2 :
+                                (madi_cnt * 100 > 13 * b16_num) ? 1 : 0;
+
+    {
+        RK_U32 md_cnt = 0, motion_level = 0;
+
+        if (ctx->smart_en)
+            md_cnt = (12 * madp_th_cnt3 + 11 * madp_th_cnt2 + 8 * madp_th_cnt1) >> 2;
+        else
+            md_cnt = (24 * madp_th_cnt3 + 22 * madp_th_cnt2 + 17 * madp_th_cnt1) >> 2;
+
+        if (md_cnt * 100 > 15 * b16_num)
+            motion_level = 200;
+        else if (md_cnt * 100 > 5 * b16_num)
+            motion_level = 100;
+        else if (md_cnt * 100 > (b16_num >> 2))
+            motion_level = 1;
+        else
+            motion_level = 0;
+        hal_rc_ret->motion_level = motion_level;
+    }
+    hal_h265e_dbg_output("complex_level %d motion_level %d\n",
+                         hal_rc_ret->complex_level, hal_rc_ret->motion_level);
+
+    fb->st_madi = madi_th_cnt0 * regs_set->reg_rc_roi.madi_st_thd.madi_th0 +
+                  madi_th_cnt1 * (regs_set->reg_rc_roi.madi_st_thd.madi_th0 +
+                                  regs_set->reg_rc_roi.madi_st_thd.madi_th1) / 2 +
+                  madi_th_cnt2 * (regs_set->reg_rc_roi.madi_st_thd.madi_th1 +
+                                  regs_set->reg_rc_roi.madi_st_thd.madi_th2) / 2 +
+                  madi_th_cnt3 * regs_set->reg_rc_roi.madi_st_thd.madi_th2;
+
+    madi_cnt = madi_th_cnt0 + madi_th_cnt1 + madi_th_cnt2 + madi_th_cnt3;
+    if (madi_cnt)
+        fb->st_madi = fb->st_madi / madi_cnt;
+
+    fb->st_madp = madp_th_cnt0 * regs_set->reg_rc_roi.madp_st_thd0.madp_th0 +
+                  madp_th_cnt1 * (regs_set->reg_rc_roi.madp_st_thd0.madp_th0 +
+                                  regs_set->reg_rc_roi.madp_st_thd0.madp_th1) / 2 +
+                  madp_th_cnt2 * (regs_set->reg_rc_roi.madp_st_thd0.madp_th1 +
+                                  regs_set->reg_rc_roi.madp_st_thd1.madp_th2) / 2 +
+                  madp_th_cnt3 * regs_set->reg_rc_roi.madp_st_thd1.madp_th2;
+
+    madp_cnt = madp_th_cnt0 + madp_th_cnt1 + madp_th_cnt2 + madp_th_cnt3;
+    if (madp_cnt)
+        fb->st_madp =  fb->st_madp  / madp_cnt;
+
+    fb->st_mb_num += elem->st.st_bnum_b16.num_b16;
+    fb->frame_type = task->rc_task->frm.is_intra ? INTRA_FRAME : INTER_P_FRAME;
+    hal_rc_ret->bit_real += fb->out_strm_size * 8;
+    hal_h265e_dbg_output("bit_real %d quality_real %d\n",
+                         hal_rc_ret->bit_real, hal_rc_ret->quality_real);
+
+    {
+        /* This code snippet may be unnecessary, but it is kept for rv1103b compatibility. */
+        RK_S32 bit_tgt = hal_rc_ret->bit_target;
+        RK_S32 bit_real = hal_rc_ret->bit_real;
+        RK_S32 real_lvl = 0;
+
+        memcpy(fb->tgt_sub_real_lvl, ctx->last_frame_fb.tgt_sub_real_lvl, 6 * sizeof(RK_S8));
+        for (i = 3; i >= 0; i--)
+            fb->tgt_sub_real_lvl[i + 1] = fb->tgt_sub_real_lvl[i];
+
+        if (bit_tgt > bit_real) {
+            fb->tgt_sub_real_lvl[0] = (bit_tgt > bit_real * 6 / 4) ? 3 :
+                                      (bit_tgt > bit_real * 5 / 4) ? 2 :
+                                      (bit_tgt > bit_real * 9 / 8) ? 1 : 0;
+        } else {
+            fb->tgt_sub_real_lvl[0] = (bit_real > bit_tgt * 2) ? -5 :
+                                      (bit_real > bit_tgt * 7 / 4) ? -4 :
+                                      (bit_real > bit_tgt * 6 / 4) ? -3 :
+                                      (bit_real > bit_tgt * 5 / 4) ? -2 : -1;
+        }
+
+        for (i = 0; i < 5; i ++)
+            real_lvl += fb->tgt_sub_real_lvl[i];
+        if (task->rc_task->frm.is_intra)
+            fb->tgt_sub_real_lvl[5] = 0;
+
+        if (real_lvl < -9)
+            fb->tgt_sub_real_lvl[5] = 2;
+        else if (real_lvl < -2 && fb->tgt_sub_real_lvl[5] < 2)
+            fb->tgt_sub_real_lvl[5] = 1;
+    }
+
+    if (fb->st_mb_num)
+        fb->st_madi = fb->st_madi / fb->st_mb_num;
+    else
+        fb->st_madi = 0;
+
+    if (fb->st_ctu_num)
+        fb->st_madp = fb->st_madp / fb->st_ctu_num;
+    else
+        fb->st_madp = 0;
+
+    hal_rc_ret->madi = fb->st_madi;
+    hal_rc_ret->madp = fb->st_madp; /* unused ?? */
+}
\ No newline at end of file
diff --git a/mpp/hal/rkenc/h265e/hal_h265e_vepu540c.c b/mpp/hal/rkenc/h265e/hal_h265e_vepu540c.c
index 4c8f58435..3d7d6792a 100644
--- a/mpp/hal/rkenc/h265e/hal_h265e_vepu540c.c
+++ b/mpp/hal/rkenc/h265e/hal_h265e_vepu540c.c
@@ -30,6 +30,7 @@
 
 #include "hal_h265e_debug.h"
 #include "h265e_syntax_new.h"
+#include "hal_h265e_stream_amend.h"
 #include "hal_bufs.h"
 #include "rkv_enc_def.h"
 #include "vepu541_common.h"
@@ -776,25 +777,26 @@ static MPP_RET vepu540c_h265_set_rc_regs(H265eV540cHalContext *ctx, H265eV540cRe
         reg_rc->rc_adj1.qp_adj6    = 0;
         reg_rc->rc_adj1.qp_adj7    = 0;
         reg_rc->rc_adj1.qp_adj8    = 0;
-
-        reg_rc->roi_qthd0.qpmin_area0 = h265->qpmin_map[0] > 0 ? h265->qpmin_map[0] : rc_cfg->quality_min;
-        reg_rc->roi_qthd0.qpmax_area0 = h265->qpmax_map[0] > 0 ? h265->qpmax_map[0] : rc_cfg->quality_max;
-        reg_rc->roi_qthd0.qpmin_area1 = h265->qpmin_map[1] > 0 ? h265->qpmin_map[1] : rc_cfg->quality_min;
-        reg_rc->roi_qthd0.qpmax_area1 = h265->qpmax_map[1] > 0 ? h265->qpmax_map[1] : rc_cfg->quality_max;
-        reg_rc->roi_qthd0.qpmin_area2 = h265->qpmin_map[2] > 0 ? h265->qpmin_map[2] : rc_cfg->quality_min;;
-        reg_rc->roi_qthd1.qpmax_area2 = h265->qpmax_map[2] > 0 ? h265->qpmax_map[2] : rc_cfg->quality_max;
-        reg_rc->roi_qthd1.qpmin_area3 = h265->qpmin_map[3] > 0 ? h265->qpmin_map[3] : rc_cfg->quality_min;;
-        reg_rc->roi_qthd1.qpmax_area3 = h265->qpmax_map[3] > 0 ? h265->qpmax_map[3] : rc_cfg->quality_max;
-        reg_rc->roi_qthd1.qpmin_area4 = h265->qpmin_map[4] > 0 ? h265->qpmin_map[4] : rc_cfg->quality_min;;
-        reg_rc->roi_qthd1.qpmax_area4 = h265->qpmax_map[4] > 0 ? h265->qpmax_map[4] : rc_cfg->quality_max;
-        reg_rc->roi_qthd2.qpmin_area5 = h265->qpmin_map[5] > 0 ? h265->qpmin_map[5] : rc_cfg->quality_min;;
-        reg_rc->roi_qthd2.qpmax_area5 = h265->qpmax_map[5] > 0 ? h265->qpmax_map[5] : rc_cfg->quality_max;
-        reg_rc->roi_qthd2.qpmin_area6 = h265->qpmin_map[6] > 0 ? h265->qpmin_map[6] : rc_cfg->quality_min;;
-        reg_rc->roi_qthd2.qpmax_area6 = h265->qpmax_map[6] > 0 ? h265->qpmax_map[6] : rc_cfg->quality_max;
-        reg_rc->roi_qthd2.qpmin_area7 = h265->qpmin_map[7] > 0 ? h265->qpmin_map[7] : rc_cfg->quality_min;;
-        reg_rc->roi_qthd3.qpmax_area7 = h265->qpmax_map[7] > 0 ? h265->qpmax_map[7] : rc_cfg->quality_max;
-        reg_rc->roi_qthd3.qpmap_mode  = h265->qpmap_mode;
     }
+
+    reg_rc->roi_qthd0.qpmin_area0 = h265->qpmin_map[0] > 0 ? h265->qpmin_map[0] : rc_cfg->quality_min;
+    reg_rc->roi_qthd0.qpmax_area0 = h265->qpmax_map[0] > 0 ? h265->qpmax_map[0] : rc_cfg->quality_max;
+    reg_rc->roi_qthd0.qpmin_area1 = h265->qpmin_map[1] > 0 ? h265->qpmin_map[1] : rc_cfg->quality_min;
+    reg_rc->roi_qthd0.qpmax_area1 = h265->qpmax_map[1] > 0 ? h265->qpmax_map[1] : rc_cfg->quality_max;
+    reg_rc->roi_qthd0.qpmin_area2 = h265->qpmin_map[2] > 0 ? h265->qpmin_map[2] : rc_cfg->quality_min;
+    reg_rc->roi_qthd1.qpmax_area2 = h265->qpmax_map[2] > 0 ? h265->qpmax_map[2] : rc_cfg->quality_max;
+    reg_rc->roi_qthd1.qpmin_area3 = h265->qpmin_map[3] > 0 ? h265->qpmin_map[3] : rc_cfg->quality_min;
+    reg_rc->roi_qthd1.qpmax_area3 = h265->qpmax_map[3] > 0 ? h265->qpmax_map[3] : rc_cfg->quality_max;
+    reg_rc->roi_qthd1.qpmin_area4 = h265->qpmin_map[4] > 0 ? h265->qpmin_map[4] : rc_cfg->quality_min;
+    reg_rc->roi_qthd1.qpmax_area4 = h265->qpmax_map[4] > 0 ? h265->qpmax_map[4] : rc_cfg->quality_max;
+    reg_rc->roi_qthd2.qpmin_area5 = h265->qpmin_map[5] > 0 ? h265->qpmin_map[5] : rc_cfg->quality_min;
+    reg_rc->roi_qthd2.qpmax_area5 = h265->qpmax_map[5] > 0 ? h265->qpmax_map[5] : rc_cfg->quality_max;
+    reg_rc->roi_qthd2.qpmin_area6 = h265->qpmin_map[6] > 0 ? h265->qpmin_map[6] : rc_cfg->quality_min;
+    reg_rc->roi_qthd2.qpmax_area6 = h265->qpmax_map[6] > 0 ? h265->qpmax_map[6] : rc_cfg->quality_max;
+    reg_rc->roi_qthd2.qpmin_area7 = h265->qpmin_map[7] > 0 ? h265->qpmin_map[7] : rc_cfg->quality_min;
+    reg_rc->roi_qthd3.qpmax_area7 = h265->qpmax_map[7] > 0 ? h265->qpmax_map[7] : rc_cfg->quality_max;
+    reg_rc->roi_qthd3.qpmap_mode  = h265->qpmap_mode;
+
     return MPP_OK;
 }
 
@@ -1137,6 +1139,70 @@ static void setup_vepu540c_ext_line_buf(H265eV540cHalContext *ctx, H265eV540cReg
     }
 }
 
+static void vepu540c_h265_set_split(H265eV540cRegSet *regs, MppEncCfgSet *enc_cfg, RK_U32 title_en)
+{
+    MppEncSliceSplit *cfg = &enc_cfg->split;
+
+    hal_h265e_dbg_func("enter\n");
+
+    switch (cfg->split_mode) {
+    case MPP_ENC_SPLIT_NONE : {
+        regs->reg_base.reg0216_sli_splt.sli_splt = 0;
+        regs->reg_base.reg0216_sli_splt.sli_splt_mode = 0;
+        regs->reg_base.reg0216_sli_splt.sli_splt_cpst = 0;
+        regs->reg_base.reg0216_sli_splt.sli_max_num_m1 = 0;
+        regs->reg_base.reg0216_sli_splt.sli_flsh = 0;
+        regs->reg_base.reg0218_sli_cnum.sli_splt_cnum_m1 = 0;
+
+        regs->reg_base.reg0217_sli_byte.sli_splt_byte = 0;
+        regs->reg_base.reg0192_enc_pic.slen_fifo = 0;
+    } break;
+    case MPP_ENC_SPLIT_BY_BYTE : {
+        regs->reg_base.reg0216_sli_splt.sli_splt = 1;
+        regs->reg_base.reg0216_sli_splt.sli_splt_mode = 0;
+        regs->reg_base.reg0216_sli_splt.sli_splt_cpst = 0;
+        regs->reg_base.reg0216_sli_splt.sli_max_num_m1 = 500;
+        regs->reg_base.reg0216_sli_splt.sli_flsh = 1;
+        regs->reg_base.reg0218_sli_cnum.sli_splt_cnum_m1 = 0;
+
+        regs->reg_base.reg0217_sli_byte.sli_splt_byte = cfg->split_arg;
+        regs->reg_base.reg0192_enc_pic.slen_fifo = cfg->split_out ? 1 : 0;
+        regs->reg_ctl.reg0008_int_en.vslc_done_en = regs->reg_base.reg0192_enc_pic.slen_fifo;
+    } break;
+    case MPP_ENC_SPLIT_BY_CTU : {
+        RK_U32 mb_w = MPP_ALIGN(enc_cfg->prep.width, 64) / 64;
+        RK_U32 mb_h = MPP_ALIGN(enc_cfg->prep.height, 64) / 64;
+        RK_U32 slice_num = 0;
+
+        if (title_en)
+            mb_w = mb_w / 2;
+
+        slice_num = (mb_w * mb_h + cfg->split_arg - 1) / cfg->split_arg;
+
+        regs->reg_base.reg0216_sli_splt.sli_splt = 1;
+        regs->reg_base.reg0216_sli_splt.sli_splt_mode = 1;
+        regs->reg_base.reg0216_sli_splt.sli_splt_cpst = 0;
+        regs->reg_base.reg0216_sli_splt.sli_max_num_m1 = 500;
+        regs->reg_base.reg0216_sli_splt.sli_flsh = 1;
+        regs->reg_base.reg0218_sli_cnum.sli_splt_cnum_m1 = cfg->split_arg - 1;
+
+        regs->reg_base.reg0217_sli_byte.sli_splt_byte = 0;
+        regs->reg_base.reg0192_enc_pic.slen_fifo = cfg->split_out ? 1 : 0;
+
+        if ((cfg->split_out & MPP_ENC_SPLIT_OUT_LOWDELAY) ||
+            (regs->reg_base.reg0192_enc_pic.slen_fifo && (slice_num > VEPU540C_SLICE_FIFO_LEN)))
+            regs->reg_ctl.reg0008_int_en.vslc_done_en = 1 ;
+    } break;
+    default : {
+        mpp_log_f("invalide slice split mode %d\n", cfg->split_mode);
+    } break;
+    }
+
+    cfg->change = 0;
+
+    hal_h265e_dbg_func("leave\n");
+}
+
 MPP_RET hal_h265e_v540c_gen_regs(void *hal, HalEncTask *task)
 {
     H265eV540cHalContext *ctx = (H265eV540cHalContext *)hal;
@@ -1169,7 +1235,7 @@ MPP_RET hal_h265e_v540c_gen_regs(void *hal, HalEncTask *task)
     reg_ctl->reg0008_int_en.enc_done_en        = 1;
     reg_ctl->reg0008_int_en.lkt_node_done_en   = 1;
     reg_ctl->reg0008_int_en.sclr_done_en       = 1;
-    reg_ctl->reg0008_int_en.vslc_done_en       = 1;
+    reg_ctl->reg0008_int_en.vslc_done_en       = 0;
     reg_ctl->reg0008_int_en.vbsf_oflw_en       = 1;
     reg_ctl->reg0008_int_en.vbuf_lens_en       = 1;
     reg_ctl->reg0008_int_en.enc_err_en         = 1;
@@ -1224,15 +1290,6 @@ MPP_RET hal_h265e_v540c_gen_regs(void *hal, HalEncTask *task)
     reg_klut->klut_ofst.chrm_klut_ofst = (ctx->frame_type == INTRA_FRAME) ? 6 :
                                          (ctx->cfg->tune.scene_mode == MPP_ENC_SCENE_MODE_IPC ? 9 : 6);
     reg_klut->klut_ofst.inter_chrm_dist_multi = 4;
-
-    reg_base->reg0216_sli_splt.sli_splt_mode     = syn->sp.sli_splt_mode;
-    reg_base->reg0216_sli_splt.sli_splt_cpst     = syn->sp.sli_splt_cpst;
-    reg_base->reg0216_sli_splt.sli_splt          = syn->sp.sli_splt;
-    reg_base->reg0216_sli_splt.sli_flsh          = syn->sp.sli_flsh;
-    reg_base->reg0216_sli_splt.sli_max_num_m1    = syn->sp.sli_max_num_m1;
-
-    reg_base->reg0218_sli_cnum.sli_splt_cnum_m1  = syn->sp.sli_splt_cnum_m1;
-    reg_base->reg0217_sli_byte.sli_splt_byte = syn->sp.sli_splt_byte;
     reg_base->reg0248_sao_cfg.sao_lambda_multi = 5;
 
     vepu540c_h265_set_me_regs(ctx, syn, reg_base);
@@ -1267,7 +1324,7 @@ MPP_RET hal_h265e_v540c_gen_regs(void *hal, HalEncTask *task)
         } else {
             i_nal_type    = NAL_TRAIL_R;
         }
-        reg_base->reg0236_synt_nal.nal_unit_type    = i_nal_type;
+        reg_base->reg0236_synt_nal.nal_unit_type    = syn->sp.temporal_id ? NAL_TSA_R : i_nal_type;
     }
 
     vepu540c_h265_set_hw_address(ctx, reg_base, task);
@@ -1277,6 +1334,7 @@ MPP_RET hal_h265e_v540c_gen_regs(void *hal, HalEncTask *task)
     vepu540c_h265_set_ref_regs(syn, reg_base);
     vepu540c_h265_set_patch_info(ctx->dev, syn, (Vepu541Fmt)fmt->format, enc_task);
     setup_vepu540c_ext_line_buf(ctx, ctx->regs);
+    vepu540c_h265_set_split(regs, ctx->cfg, syn->pp.tiles_enabled_flag);
 
     /* ROI configure */
     if (ctx->roi_data)
@@ -1436,7 +1494,7 @@ static MPP_RET vepu540c_h265_set_feedback(H265eV540cHalContext *ctx, HalEncTask
     fb->out_strm_size += elem->st.bs_lgth_l32;
 
     fb->sse_sum += (RK_S64)(elem->st.sse_h32 << 16) +
-                   ((elem->st.st_sse_bsl.sse_l16 >> 16) & 0xffff) ;
+                   (elem->st.st_sse_bsl.sse_l16 & 0xffff) ;
 
     fb->hw_status = hw_status;
     hal_h265e_dbg_detail("hw_status: 0x%08x", hw_status);
@@ -1635,10 +1693,13 @@ MPP_RET hal_h265e_v540c_ret_task(void *hal, HalEncTask *task)
     HalEncTask *enc_task = task;
     vepu540c_h265_fbk *fb = &ctx->feedback;
     EncRcTaskInfo *rc_info = &task->rc_task->info;
+    RK_U32 offset = mpp_packet_get_length(enc_task->packet);
 
     hal_h265e_enter();
 
     vepu540c_h265_set_feedback(ctx, enc_task);
+    mpp_buffer_sync_partial_begin(enc_task->output, offset, fb->out_strm_size);
+    hal_h265e_amend_temporal_id(task, fb->out_strm_size);
 
     rc_info->sse = fb->sse_sum;
     rc_info->lvl64_inter_num = fb->st_lvl64_inter_num;
diff --git a/mpp/hal/rkenc/h265e/hal_h265e_vepu540c_reg.h b/mpp/hal/rkenc/h265e/hal_h265e_vepu540c_reg.h
index fa8c06242..348a40723 100644
--- a/mpp/hal/rkenc/h265e/hal_h265e_vepu540c_reg.h
+++ b/mpp/hal/rkenc/h265e/hal_h265e_vepu540c_reg.h
@@ -1135,9 +1135,6 @@ typedef struct HevcVepu540cWgt_t {
     /* wgt_qp48_grpa */
     /* 0x00001900 reg1600 */
     RK_U32 rdo_wgta_qp_grpa_0_51[52];
-
-    /* 0x19d0 - 0x1ffc */
-    // RK_U32 reserved1652_2047[396];
 } hevc_vepu540c_wgt;
 
 typedef struct H265eV540cRegSet_t {
diff --git a/mpp/hal/rkenc/h265e/hal_h265e_vepu541.c b/mpp/hal/rkenc/h265e/hal_h265e_vepu541.c
index 439220169..cc27c03c3 100644
--- a/mpp/hal/rkenc/h265e/hal_h265e_vepu541.c
+++ b/mpp/hal/rkenc/h265e/hal_h265e_vepu541.c
@@ -29,6 +29,7 @@
 
 #include "h265e_syntax_new.h"
 #include "hal_h265e_debug.h"
+#include "hal_h265e_stream_amend.h"
 #include "hal_h265e_vepu541_reg.h"
 #include "hal_h265e_vepu54x_reg_l2.h"
 #include "vepu541_common.h"
@@ -625,10 +626,10 @@ MPP_RET hal_h265e_v541_init(void *hal, MppEncHalCfg *cfg)
 
     ctx->dev = cfg->dev;
     {
-        const char *soc_name = mpp_get_soc_name();
-        if (strstr(soc_name, "rk3566") || strstr(soc_name, "rk3568")) {
+        RockchipSocType soc_type = mpp_get_soc_type();
+
+        if (soc_type == ROCKCHIP_SOC_RK3566 || soc_type == ROCKCHIP_SOC_RK3568)
             ctx->is_vepu540 = 1;
-        }
     }
 
     ctx->osd_cfg.reg_base = ctx->regs;
@@ -1330,7 +1331,8 @@ static void vepu541_h265_set_me_regs(H265eV541HalContext *ctx, H265eSyntax_new *
         regs->me_ram.cach_l2_tag  = 0x3;
 }
 
-static void vepu540_h265_set_me_ram(H265eSyntax_new *syn, H265eV541RegSet *regs, RK_U32 index)
+static void vepu540_h265_set_me_ram(H265eSyntax_new *syn, H265eV541RegSet *regs,
+                                    RK_U32 index, RK_S32 tile_start_x)
 {
     RK_U32 cime_w = 11, cime_h = 7;
     RK_U32 pic_cime_temp = 0;
@@ -1339,16 +1341,10 @@ static void vepu540_h265_set_me_ram(H265eSyntax_new *syn, H265eV541RegSet *regs,
         regs->me_ram.cime_linebuf_w = pic_cime_temp / 64;
     } else {
         RK_S32 pic_wd64 = MPP_ALIGN(syn->pp.pic_width, 64) >> 6;
-        RK_S32 tile_ctu_stax = index * pic_wd64 / (syn->pp.num_tile_columns_minus1 + 1);
-        RK_S32 tile_ctu_endx = 0;
+        RK_S32 tile_ctu_stax = tile_start_x;
+        RK_S32 tile_ctu_endx = tile_start_x + syn->pp.column_width_minus1[index];
         RK_S32 cime_srch_w = regs->me_rnge.cime_srch_h;
 
-        if (index == syn->pp.num_tile_columns_minus1) {
-            tile_ctu_endx = ((regs->enc_rsl.pic_wd8_m1 + 1) * 8 + 63) / 64 - 1;
-        } else {
-            tile_ctu_endx = (index + 1) * pic_wd64 / (syn->pp.num_tile_columns_minus1 + 1) - 1;
-        }
-
         if (tile_ctu_stax < (cime_srch_w + 3) / 4) {
             if (tile_ctu_endx + 1 + (cime_srch_w + 3) / 4 > pic_wd64)
                 pic_cime_temp = pic_wd64 * 64;
@@ -1641,7 +1637,7 @@ MPP_RET hal_h265e_v541_gen_regs(void *hal, HalEncTask *task)
         } else {
             i_nal_type    = NAL_TRAIL_N;
         }
-        regs->synt_nal.nal_unit_type    = i_nal_type;
+        regs->synt_nal.nal_unit_type    = syn->sp.temporal_id ?  NAL_TSA_R : i_nal_type;
     }
     vepu54x_h265_set_hw_address(ctx, regs, task);
     vepu541_h265_set_pp_regs(regs, fmt, &ctx->cfg->prep, task);
@@ -1667,21 +1663,18 @@ MPP_RET hal_h265e_v541_gen_regs(void *hal, HalEncTask *task)
     hal_h265e_leave();
     return MPP_OK;
 }
-void hal_h265e_v540_set_uniform_tile(H265eV541RegSet *regs, H265eSyntax_new *syn, RK_U32 index)
+void hal_h265e_v540_set_uniform_tile(H265eV541RegSet *regs, H265eSyntax_new *syn,
+                                     RK_U32 index, RK_S32 tile_start_x)
 {
     if (syn->pp.tiles_enabled_flag) {
-        RK_S32 mb_w = MPP_ALIGN(syn->pp.pic_width, 64) / 64;
         RK_S32 mb_h = MPP_ALIGN(syn->pp.pic_height, 64) / 64;
-        RK_S32 tile_width = (index + 1) * mb_w / (syn->pp.num_tile_columns_minus1 + 1) -
-                            index * mb_w / (syn->pp.num_tile_columns_minus1 + 1);
-        if (index == syn->pp.num_tile_columns_minus1) {
-            tile_width = mb_w - index * mb_w / (syn->pp.num_tile_columns_minus1 + 1);
-        }
+        RK_S32 tile_width = syn->pp.column_width_minus1[index] + 1;
+
         regs->tile_cfg.tile_width_m1 = tile_width - 1;
         regs->tile_cfg.tile_height_m1 = mb_h - 1;
         regs->rc_cfg.rc_ctu_num   = tile_width;
         regs->tile_cfg.tile_en = syn->pp.tiles_enabled_flag;
-        regs->tile_pos.tile_x = (index * mb_w / (syn->pp.num_tile_columns_minus1 + 1));
+        regs->tile_pos.tile_x = tile_start_x;
         regs->tile_pos.tile_y = 0;
         if (index > 0) {
             RK_U32 tmp = regs->lpfr_addr_hevc;
@@ -1706,6 +1699,7 @@ MPP_RET hal_h265e_v540_start(void *hal, HalEncTask *enc_task)
     hal_h265e_enter();
     RK_U32 stream_len = 0;
     VepuFmtCfg *fmt = (VepuFmtCfg *)ctx->input_fmt;
+    RK_S32 tile_start_x = 0;
 
     if (enc_task->flags.err) {
         hal_h265e_err("enc_task->flags.err %08x, return e arly",
@@ -1720,13 +1714,13 @@ MPP_RET hal_h265e_v540_start(void *hal, HalEncTask *enc_task)
         MppDevRegWrCfg cfg;
         MppDevRegRdCfg cfg1;
 
-        vepu540_h265_set_me_ram(syn, hw_regs, k);
+        vepu540_h265_set_me_ram(syn, hw_regs, k, tile_start_x);
 
         /* set input info */
         vepu541_h265_set_l2_regs(ctx, (H265eV54xL2RegSet*)ctx->l2_regs);
         vepu541_h265_set_patch_info(ctx->dev, syn, (Vepu541Fmt)fmt->format, enc_task);
         if (title_num > 1)
-            hal_h265e_v540_set_uniform_tile(hw_regs, syn, k);
+            hal_h265e_v540_set_uniform_tile(hw_regs, syn, k, tile_start_x);
         if (k > 0) {
             MppDevRegOffsetCfg cfg_fd;
             RK_U32 offset = mpp_packet_get_length(enc_task->packet);
@@ -1806,6 +1800,7 @@ MPP_RET hal_h265e_v540_start(void *hal, HalEncTask *enc_task)
             }
 
         }
+        tile_start_x += (syn->pp.column_width_minus1[k] + 1);
     }
 
     hal_h265e_dbg_detail("vpu client is sending %d regs", length);
@@ -1885,6 +1880,7 @@ MPP_RET hal_h265e_v541_start(void *hal, HalEncTask *task)
     hal_h265e_leave();
     return ret;
 }
+
 MPP_RET hal_h265e_v54x_start(void *hal, HalEncTask *task)
 {
     H265eV541HalContext *ctx = (H265eV541HalContext *)hal;
@@ -2057,10 +2053,13 @@ MPP_RET hal_h265e_v541_ret_task(void *hal, HalEncTask *task)
     HalEncTask *enc_task = task;
     vepu541_h265_fbk *fb = &ctx->feedback;
     EncRcTaskInfo *rc_info = &task->rc_task->info;
+    RK_U32 offset = mpp_packet_get_length(enc_task->packet);
 
     hal_h265e_enter();
 
     vepu541_h265_set_feedback(ctx, enc_task);
+    mpp_buffer_sync_partial_begin(enc_task->output, offset, fb->out_strm_size);
+    hal_h265e_amend_temporal_id(task, fb->out_strm_size);
 
     rc_info->sse = fb->sse_sum;
     rc_info->lvl64_inter_num = fb->st_lvl64_inter_num;
diff --git a/mpp/hal/rkenc/h265e/hal_h265e_vepu580.c b/mpp/hal/rkenc/h265e/hal_h265e_vepu580.c
index d3c93de76..1074c1c2c 100644
--- a/mpp/hal/rkenc/h265e/hal_h265e_vepu580.c
+++ b/mpp/hal/rkenc/h265e/hal_h265e_vepu580.c
@@ -30,6 +30,7 @@
 
 #include "hal_h265e_debug.h"
 #include "h265e_syntax_new.h"
+#include "hal_h265e_stream_amend.h"
 #include "hal_bufs.h"
 #include "rkv_enc_def.h"
 #include "h265e_dpb.h"
@@ -80,13 +81,43 @@ typedef struct vepu580_h265_fbk_t {
     RK_U32 st_ctu_num;
 } Vepu580H265Fbk;
 
-typedef struct Vepu580RoiH265BsCfg_t {
+typedef struct Vepu580RoiHevcBsCfg_t {
     RK_U8 amv_en        : 1;
     RK_U8 qp_adj        : 1;
     RK_U8 force_split   : 1;
     RK_U8 force_intra   : 2;
     RK_U8 force_inter   : 2;
-} Vepu580RoiH265BsCfg;
+} Vepu580RoiHevcBsCfg;
+
+typedef struct Vepu580MdInfo_t {
+    RK_U8 vld;
+    RK_U16 sad[16];
+} Vepu580MdInfo;
+
+typedef struct Vepu580RoiHevcQpCfg_t {
+    RK_U16 reserved     : 4;
+    /*
+     * Qp area index
+     * The choosed qp area index.
+     */
+    RK_U16 qp_area_idx  : 4;
+    /*
+     * Qp_adj
+     * Qp_adj
+     * in absolute qp mode qp_adj is the final qp used by encoder
+     * in relative qp mode qp_adj is a adjustment to final qp
+     */
+    RK_S16 qp_adj       : 7;
+    /*
+     * Qp_adj_mode
+     * Qp adjustment mode
+     * 1 - absolute qp mode:
+     *     the 16x16 MB qp is set to the qp_adj value
+     * 0 - relative qp mode
+     *     the 16x16 MB qp is adjusted by qp_adj value
+     */
+    RK_U16 qp_adj_mode  : 1;
+} Vepu580RoiHevcQpCfg;
 
 typedef struct Vepu580H265eFrmCfg_t {
     RK_S32              frame_count;
@@ -154,6 +185,7 @@ typedef struct H265eV580HalContext_t {
     RK_S32              last_frame_type;
 
     MppBufferGroup      roi_grp;
+    MppBufferGroup      qpmap_grp;
 
     MppEncCfgSet        *cfg;
     H265eSyntax_new     *syn;
@@ -183,6 +215,14 @@ typedef struct H265eV580HalContext_t {
 
     /* finetune */
     void                *tune;
+    MppBuffer           md_info_buf; /* md info buffer for deblurring */
+    MppBuffer           qpmap_base_cfg_buf;
+    MppBuffer           qpmap_qp_cfg_buf;
+    RK_U8*              md_flag_buf;
+    RK_S32              md_info_buf_size;
+    RK_S32              qpmap_base_cfg_size;
+    RK_S32              qpmap_qp_cfg_size;
+    RK_S32              md_flag_size;
 } H265eV580HalContext;
 
 static RK_U32 aq_thd_default[16] = {
@@ -201,11 +241,12 @@ static RK_U32 h265e_mode_bias[16] = {
 
 static RK_S32 aq_qp_dealt_default[16] = {
     -8, -7, -6, -5,
-    -4, -2, -1, -1,
-    0,  2,  3,  4,
+    -4, -3, -2, -1,
+    0,  1,  2,  3,
     5,  7,  8,  9,
 };
 
+
 static RK_U16 lvl32_intra_cst_thd[4] = {2, 6, 16, 36};
 
 static RK_U16 lvl16_intra_cst_thd[4] = {2, 6, 16, 36};
@@ -216,7 +257,8 @@ static RK_U8 lvl16_intra_cst_wgt[8] = {17, 17, 17, 18, 17, 18, 18};
 
 #include "hal_h265e_vepu580_tune.c"
 
-static void vepu580_h265_set_me_ram(H265eSyntax_new *syn, hevc_vepu580_base *regs, RK_U32 index)
+static void vepu580_h265_set_me_ram(H265eSyntax_new *syn, hevc_vepu580_base *regs,
+                                    RK_U32 index, RK_S32 tile_start_x)
 {
     RK_S32 frm_sta = 0, frm_end = 0, pic_w = 0;
     RK_S32 srch_w = regs->reg0220_me_rnge.cme_srch_h * 4;
@@ -239,14 +281,8 @@ static void vepu580_h265_set_me_ram(H265eSyntax_new *syn, hevc_vepu580_base *reg
         }
         frm_end = mpp_clip(frm_end, 0, pic_wd64 - 1);
     } else {
-        RK_S32 tile_ctu_stax = index * pic_wd64 / (syn->pp.num_tile_columns_minus1 + 1);
-        RK_S32 tile_ctu_endx = 0;
-
-        if (index == syn->pp.num_tile_columns_minus1) {
-            tile_ctu_endx = ((regs->reg0196_enc_rsl.pic_wd8_m1 + 1) * 8 + 63) / 64 - 1;
-        } else {
-            tile_ctu_endx = (index + 1) * pic_wd64 / (syn->pp.num_tile_columns_minus1 + 1) - 1;
-        }
+        RK_S32 tile_ctu_stax = tile_start_x;
+        RK_S32 tile_ctu_endx = tile_start_x + syn->pp.column_width_minus1[index];
 
         if (x_gmv - srch_w < 0) {
             frm_sta = tile_ctu_stax + (x_gmv - srch_w - 15) / 16;
@@ -1336,7 +1372,6 @@ static void vepu580_h265_global_cfg_set(H265eV580HalContext *ctx, H265eV580RegSe
     rc_regs->madi_thd.madi_thd0    = 25;
     rc_regs->madi_thd.madi_thd1    = 35;
     rc_regs->madi_thd.madi_thd2    = 45;
-
     reg_wgt->reg1484_qnt_bias_comb.qnt_bias_i = 171;
     reg_wgt->reg1484_qnt_bias_comb.qnt_bias_p = 85;
 
@@ -1445,6 +1480,31 @@ MPP_RET hal_h265e_v580_deinit(void *hal)
         vepu580_h265e_tune_deinit(ctx->tune);
         ctx->tune = NULL;
     }
+
+    if (ctx->md_info_buf) {
+        mpp_buffer_put(ctx->md_info_buf);
+        ctx->md_info_buf = NULL;
+    }
+
+    if (ctx->qpmap_base_cfg_buf) {
+        mpp_buffer_put(ctx->qpmap_base_cfg_buf);
+        ctx->qpmap_base_cfg_buf = NULL;
+    }
+
+    if (ctx->qpmap_qp_cfg_buf) {
+        mpp_buffer_put(ctx->qpmap_qp_cfg_buf);
+        ctx->qpmap_qp_cfg_buf = NULL;
+    }
+
+    if (ctx->md_flag_buf) {
+        MPP_FREE(ctx->md_flag_buf);
+    }
+
+    if (ctx->qpmap_grp) {
+        mpp_buffer_group_put(ctx->qpmap_grp);
+        ctx->qpmap_grp = NULL;
+    }
+
     hal_h265e_leave();
     return MPP_OK;
 }
@@ -1900,24 +1960,29 @@ static MPP_RET vepu580_h265_set_rc_regs(H265eV580HalContext *ctx, H265eV580RegSe
         reg_rc->rc_adj1.qp_adj7    = 0;
         reg_rc->rc_adj1.qp_adj8    = 0;
 
-        reg_rc->roi_qthd0.qpmin_area0 = h265->qpmin_map[0] > 0 ? h265->qpmin_map[0] : rc_cfg->quality_min;
-        reg_rc->roi_qthd0.qpmax_area0 = h265->qpmax_map[0] > 0 ? h265->qpmax_map[0] : rc_cfg->quality_max;
-        reg_rc->roi_qthd0.qpmin_area1 = h265->qpmin_map[1] > 0 ? h265->qpmin_map[1] : rc_cfg->quality_min;
-        reg_rc->roi_qthd0.qpmax_area1 = h265->qpmax_map[1] > 0 ? h265->qpmax_map[1] : rc_cfg->quality_max;
-        reg_rc->roi_qthd0.qpmin_area2 = h265->qpmin_map[2] > 0 ? h265->qpmin_map[2] : rc_cfg->quality_min;
-        reg_rc->roi_qthd1.qpmax_area2 = h265->qpmax_map[2] > 0 ? h265->qpmax_map[2] : rc_cfg->quality_max;
-        reg_rc->roi_qthd1.qpmin_area3 = h265->qpmin_map[3] > 0 ? h265->qpmin_map[3] : rc_cfg->quality_min;
-        reg_rc->roi_qthd1.qpmax_area3 = h265->qpmax_map[3] > 0 ? h265->qpmax_map[3] : rc_cfg->quality_max;
-        reg_rc->roi_qthd1.qpmin_area4 = h265->qpmin_map[4] > 0 ? h265->qpmin_map[4] : rc_cfg->quality_min;
-        reg_rc->roi_qthd1.qpmax_area4 = h265->qpmax_map[4] > 0 ? h265->qpmax_map[4] : rc_cfg->quality_max;
-        reg_rc->roi_qthd2.qpmin_area5 = h265->qpmin_map[5] > 0 ? h265->qpmin_map[5] : rc_cfg->quality_min;
-        reg_rc->roi_qthd2.qpmax_area5 = h265->qpmax_map[5] > 0 ? h265->qpmax_map[5] : rc_cfg->quality_max;
-        reg_rc->roi_qthd2.qpmin_area6 = h265->qpmin_map[6] > 0 ? h265->qpmin_map[6] : rc_cfg->quality_min;
-        reg_rc->roi_qthd2.qpmax_area6 = h265->qpmax_map[6] > 0 ? h265->qpmax_map[6] : rc_cfg->quality_max;
-        reg_rc->roi_qthd2.qpmin_area7 = h265->qpmin_map[7] > 0 ? h265->qpmin_map[7] : rc_cfg->quality_min;
-        reg_rc->roi_qthd3.qpmax_area7 = h265->qpmax_map[7] > 0 ? h265->qpmax_map[7] : rc_cfg->quality_max;
-        reg_rc->roi_qthd3.qpmap_mode  = h265->qpmap_mode;
+        if (rc->rc_mode == MPP_ENC_RC_MODE_SMTRC) {
+            reg_base->reg213_rc_qp.rc_qp_range = 0;
+        }
     }
+
+    reg_rc->roi_qthd0.qpmin_area0 = h265->qpmin_map[0] > 0 ? h265->qpmin_map[0] : rc_cfg->quality_min;
+    reg_rc->roi_qthd0.qpmax_area0 = h265->qpmax_map[0] > 0 ? h265->qpmax_map[0] : rc_cfg->quality_max;
+    reg_rc->roi_qthd0.qpmin_area1 = h265->qpmin_map[1] > 0 ? h265->qpmin_map[1] : rc_cfg->quality_min;
+    reg_rc->roi_qthd0.qpmax_area1 = h265->qpmax_map[1] > 0 ? h265->qpmax_map[1] : rc_cfg->quality_max;
+    reg_rc->roi_qthd0.qpmin_area2 = h265->qpmin_map[2] > 0 ? h265->qpmin_map[2] : rc_cfg->quality_min;
+    reg_rc->roi_qthd1.qpmax_area2 = h265->qpmax_map[2] > 0 ? h265->qpmax_map[2] : rc_cfg->quality_max;
+    reg_rc->roi_qthd1.qpmin_area3 = h265->qpmin_map[3] > 0 ? h265->qpmin_map[3] : rc_cfg->quality_min;
+    reg_rc->roi_qthd1.qpmax_area3 = h265->qpmax_map[3] > 0 ? h265->qpmax_map[3] : rc_cfg->quality_max;
+    reg_rc->roi_qthd1.qpmin_area4 = h265->qpmin_map[4] > 0 ? h265->qpmin_map[4] : rc_cfg->quality_min;
+    reg_rc->roi_qthd1.qpmax_area4 = h265->qpmax_map[4] > 0 ? h265->qpmax_map[4] : rc_cfg->quality_max;
+    reg_rc->roi_qthd2.qpmin_area5 = h265->qpmin_map[5] > 0 ? h265->qpmin_map[5] : rc_cfg->quality_min;
+    reg_rc->roi_qthd2.qpmax_area5 = h265->qpmax_map[5] > 0 ? h265->qpmax_map[5] : rc_cfg->quality_max;
+    reg_rc->roi_qthd2.qpmin_area6 = h265->qpmin_map[6] > 0 ? h265->qpmin_map[6] : rc_cfg->quality_min;
+    reg_rc->roi_qthd2.qpmax_area6 = h265->qpmax_map[6] > 0 ? h265->qpmax_map[6] : rc_cfg->quality_max;
+    reg_rc->roi_qthd2.qpmin_area7 = h265->qpmin_map[7] > 0 ? h265->qpmin_map[7] : rc_cfg->quality_min;
+    reg_rc->roi_qthd3.qpmax_area7 = h265->qpmax_map[7] > 0 ? h265->qpmax_map[7] : rc_cfg->quality_max;
+    reg_rc->roi_qthd3.qpmap_mode  = h265->qpmap_mode;
+
     return MPP_OK;
 }
 
@@ -2353,13 +2418,41 @@ static void vepu580_h265_set_me_regs(H265eV580HalContext *ctx, H265eSyntax_new *
 
 }
 
+static MppBuffer vepu580_h265_get_md_info_buf(H265eV580HalContext *ctx)
+{
+    RK_S32 w = ctx->cfg->prep.width;
+    RK_S32 h = ctx->cfg->prep.height;
+    RK_S32 buf_size = (MPP_ALIGN(w, 64) >> 6) * (MPP_ALIGN(h, 64) >> 6) * 32;
+
+    /* prepare md info internal buffer when deblur is enabled */
+    if (ctx->cfg->tune.deblur_en && (buf_size > ctx->md_info_buf_size)) {
+        if (ctx->md_info_buf) {
+            mpp_buffer_put(ctx->md_info_buf);
+            ctx->md_info_buf = NULL;
+        }
+
+        if (!ctx->qpmap_grp)
+            mpp_buffer_group_get_internal(&ctx->qpmap_grp, MPP_BUFFER_TYPE_ION);
+
+        mpp_buffer_get(ctx->qpmap_grp, &ctx->md_info_buf, buf_size);
+        if (!ctx->md_info_buf)
+            mpp_err_f("failed to get md info buffer\n");
+        else {
+            hal_h265e_dbg_flow("get md info internal buffer %p size %d %d\n",
+                               ctx->md_info_buf, buf_size, ctx->md_info_buf_size);
+            ctx->md_info_buf_size = buf_size;
+        }
+    }
+
+    return ctx->md_info_buf;
+}
+
 void vepu580_h265_set_hw_address(H265eV580HalContext *ctx, HalEncTask *task)
 {
     Vepu580H265eFrmCfg *frm = ctx->frm;
     hevc_vepu580_base *regs = &frm->regs_set[0]->reg_base;
     HalEncTask *enc_task = task;
     HalBuf *recon_buf, *ref_buf;
-    MppBuffer md_info_buf = enc_task->md_info;
     H265eSyntax_new *syn = ctx->syn;
 
     hal_h265e_enter();
@@ -2419,12 +2512,17 @@ void vepu580_h265_set_hw_address(H265eV580HalContext *ctx, HalEncTask *task)
         regs->reg0177_lpfr_addr  = mpp_buffer_get_fd(frm->hw_tile_buf[1]);
     }
 
-    if (md_info_buf) {
-        regs->reg0192_enc_pic.mei_stor    = 1;
-        regs->reg0171_meiw_addr = mpp_buffer_get_fd(md_info_buf);
-    } else {
-        regs->reg0192_enc_pic.mei_stor    = 0;
-        regs->reg0171_meiw_addr = 0;
+    {
+        if (!enc_task->md_info)
+            enc_task->md_info = vepu580_h265_get_md_info_buf(ctx);
+
+        if (enc_task->md_info) {
+            regs->reg0192_enc_pic.mei_stor    = 1;
+            regs->reg0171_meiw_addr = mpp_buffer_get_fd(enc_task->md_info);
+        } else {
+            regs->reg0192_enc_pic.mei_stor    = 0;
+            regs->reg0171_meiw_addr = 0;
+        }
     }
 
     regs->reg0172_bsbt_addr = mpp_buffer_get_fd(enc_task->output);
@@ -2466,7 +2564,7 @@ static MPP_RET vepu580_h265e_save_pass1_patch(H265eV580RegSet *regs, H265eV580Ha
     if (tiles_enabled_flag)
         reg_base->reg0238_synt_pps.lpf_fltr_acrs_til = 0;
 
-    mpp_dev_multi_offset_update(frm->reg_cfg, 164, width_align * height);
+    mpp_dev_multi_offset_update(frm->reg_cfg, 164, width_align * height_align);
 
     /* NOTE: disable split to avoid lowdelay slice output */
     regs->reg_base.reg0216_sli_splt.sli_splt = 0;
@@ -2488,10 +2586,16 @@ static MPP_RET vepu580_h265e_use_pass1_patch(H265eV580RegSet *regs, H265eV580Hal
 
     reg_ctl->reg0012_dtrns_map.src_bus_edin = fmt->src_endian;
     reg_base->reg0198_src_fmt.src_cfmt = VEPU541_FMT_YUV420SP;
+    reg_base->reg0198_src_fmt.alpha_swap = 0;
+    reg_base->reg0198_src_fmt.rbuv_swap = 0;
     reg_base->reg0198_src_fmt.out_fmt = 1;
     reg_base->reg0203_src_proc.afbcd_en = 0;
     reg_base->reg0205_src_strd0.src_strd0 = hor_stride;
     reg_base->reg0206_src_strd1.src_strd1 = hor_stride;
+    reg_base->reg0203_src_proc.src_mirr = 0;
+    reg_base->reg0203_src_proc.src_rot = 0;
+    reg_base->reg0204_pic_ofst.pic_ofst_x = 0;
+    reg_base->reg0204_pic_ofst.pic_ofst_y = 0;
     reg_base->reg0160_adr_src0 = mpp_buffer_get_fd(ctx->buf_pass1);
     reg_base->reg0161_adr_src1 = reg_base->reg0160_adr_src0;
     reg_base->reg0162_adr_src2 = reg_base->reg0160_adr_src0;
@@ -2509,7 +2613,7 @@ static MPP_RET vepu580_h265e_use_pass1_patch(H265eV580RegSet *regs, H265eV580Hal
     return MPP_OK;
 }
 
-static void setup_vepu580_split(H265eV580RegSet *regs, MppEncCfgSet *enc_cfg, RK_U32 title_en)
+static void vepu580_setup_split(H265eV580RegSet *regs, MppEncCfgSet *enc_cfg, RK_U32 title_en)
 {
     MppEncSliceSplit *cfg = &enc_cfg->split;
 
@@ -2537,6 +2641,7 @@ static void setup_vepu580_split(H265eV580RegSet *regs, MppEncCfgSet *enc_cfg, RK
 
         regs->reg_base.reg0217_sli_byte.sli_splt_byte = cfg->split_arg;
         regs->reg_base.reg0192_enc_pic.slen_fifo = cfg->split_out ? 1 : 0;
+        regs->reg_ctl.reg0008_int_en.slc_done_en = regs->reg_base.reg0192_enc_pic.slen_fifo;
     } break;
     case MPP_ENC_SPLIT_BY_CTU : {
         RK_U32 mb_w = MPP_ALIGN(enc_cfg->prep.width, 64) / 64;
@@ -2557,10 +2662,10 @@ static void setup_vepu580_split(H265eV580RegSet *regs, MppEncCfgSet *enc_cfg, RK
 
         regs->reg_base.reg0217_sli_byte.sli_splt_byte = 0;
         regs->reg_base.reg0192_enc_pic.slen_fifo = cfg->split_out ? 1 : 0;
-        regs->reg_ctl.reg0008_int_en.slc_done_en = (cfg->split_out & MPP_ENC_SPLIT_OUT_LOWDELAY) ? 1 : 0;
 
-        if (slice_num > VEPU580_SLICE_FIFO_LEN)
-            regs->reg_ctl.reg0008_int_en.slc_done_en = 1;
+        if ((cfg->split_out & MPP_ENC_SPLIT_OUT_LOWDELAY) ||
+            (regs->reg_base.reg0192_enc_pic.slen_fifo && (slice_num > VEPU580_SLICE_FIFO_LEN)))
+            regs->reg_ctl.reg0008_int_en.slc_done_en = 1 ;
     } break;
     default : {
         mpp_log_f("invalide slice split mode %d\n", cfg->split_mode);
@@ -2587,6 +2692,7 @@ MPP_RET hal_h265e_v580_gen_regs(void *hal, HalEncTask *task)
     hevc_vepu580_control_cfg *reg_ctl = &regs->reg_ctl;
     hevc_vepu580_base        *reg_base = &regs->reg_base;
     hevc_vepu580_rc_klut *reg_klut = &regs->reg_rc_klut;
+    MppEncCfgSet *cfg = ctx->cfg;
 
     hal_h265e_enter();
     pic_width_align8 = (syn->pp.pic_width + 7) & (~7);
@@ -2688,7 +2794,8 @@ MPP_RET hal_h265e_v580_gen_regs(void *hal, HalEncTask *task)
         } else {
             i_nal_type    = NAL_TRAIL_R;
         }
-        reg_base->reg0236_synt_nal.nal_unit_type    = i_nal_type;
+
+        reg_base->reg0236_synt_nal.nal_unit_type    = syn->sp.temporal_id ? NAL_TSA_R : i_nal_type;
     }
 
     vepu580_h265_set_hw_address(ctx, task);
@@ -2703,29 +2810,30 @@ MPP_RET hal_h265e_v580_gen_regs(void *hal, HalEncTask *task)
     if (frm->is_i_refresh)
         setup_intra_refresh(ctx, frm->seq_idx % ctx->cfg->rc.gop);
 
+    if (cfg->tune.deblur_en && (!rc_task->info.complex_scene) &&
+        cfg->rc.rc_mode == MPP_ENC_RC_MODE_SMTRC && task->md_info &&
+        cfg->tune.scene_mode == MPP_ENC_SCENE_MODE_IPC) {
+        if (MPP_OK != vepu580_setup_qpmap_buf(ctx))
+            mpp_err("qpmap malloc buffer failed!\n");
+    }
+
     /*paramet cfg*/
     vepu580_h265_global_cfg_set(ctx, regs);
 
     vepu580_h265e_tune_reg_patch(ctx->tune);
-    setup_vepu580_split(regs, ctx->cfg, syn->pp.tiles_enabled_flag);
-    /* two pass register patch */
-    if (frm->save_pass1)
-        vepu580_h265e_save_pass1_patch(regs, ctx, syn->pp.tiles_enabled_flag);
 
-    if (frm->use_pass1)
-        vepu580_h265e_use_pass1_patch(regs, ctx);
+    vepu580_setup_split(regs, cfg, syn->pp.tiles_enabled_flag);
 
     hal_h265e_leave();
     return MPP_OK;
 }
 
-void hal_h265e_v580_set_uniform_tile(hevc_vepu580_base *regs, H265eSyntax_new *syn, RK_U32 index)
+void hal_h265e_v580_set_uniform_tile(hevc_vepu580_base *regs, H265eSyntax_new *syn,
+                                     RK_U32 index, RK_S32 tile_start_x)
 {
     if (syn->pp.tiles_enabled_flag) {
-        RK_S32 mb_w = MPP_ALIGN(syn->pp.pic_width, 64) / 64;
         RK_S32 mb_h = MPP_ALIGN(syn->pp.pic_height, 64) / 64;
-        RK_S32 tile_width = (index + 1) * mb_w / (syn->pp.num_tile_columns_minus1 + 1) -
-                            index * mb_w / (syn->pp.num_tile_columns_minus1 + 1);
+        RK_S32 tile_width = syn->pp.column_width_minus1[index] + 1;
 
         if (!regs->reg0192_enc_pic.cur_frm_ref &&
             !(regs->reg0238_synt_pps.lpf_fltr_acrs_til &&
@@ -2751,7 +2859,6 @@ void hal_h265e_v580_set_uniform_tile(hevc_vepu580_base *regs, H265eSyntax_new *s
         regs->reg0193_dual_core.dchs_ofst = 2;
 
         if (index == syn->pp.num_tile_columns_minus1) {
-            tile_width = mb_w - index * mb_w / (syn->pp.num_tile_columns_minus1 + 1);
             regs->reg0193_dual_core.dchs_txid = 0;
             regs->reg0193_dual_core.dchs_txe = 0;
         }
@@ -2759,7 +2866,7 @@ void hal_h265e_v580_set_uniform_tile(hevc_vepu580_base *regs, H265eSyntax_new *s
         regs->reg0252_tile_cfg.tile_h_m1 = mb_h - 1;
         regs->reg212_rc_cfg.rc_ctu_num   = tile_width;
         regs->reg0252_tile_cfg.tile_en = syn->pp.tiles_enabled_flag;
-        regs->reg0253_tile_pos.tile_x = (index * mb_w / (syn->pp.num_tile_columns_minus1 + 1));
+        regs->reg0253_tile_pos.tile_x = tile_start_x;
         regs->reg0253_tile_pos.tile_y = 0;
 
         hal_h265e_dbg_detail("tile_x %d, rc_ctu_num %d, tile_width_m1 %d",
@@ -2778,6 +2885,7 @@ MPP_RET hal_h265e_v580_start(void *hal, HalEncTask *enc_task)
     Vepu580H265eFrmCfg *frm = ctx->frm;
     RK_U32 k = 0;
     MPP_RET ret = MPP_OK;
+    RK_S32 tile_start_x = 0;
 
     hal_h265e_enter();
 
@@ -2813,12 +2921,12 @@ MPP_RET hal_h265e_v580_start(void *hal, HalEncTask *enc_task)
         if (k)
             memcpy(hw_regs, frm->regs_set[0], sizeof(*hw_regs));
 
-        vepu580_h265_set_me_ram(syn, reg_base, k);
+        vepu580_h265_set_me_ram(syn, reg_base, k, tile_start_x);
 
         /* set input info */
         vepu580_h265_set_patch_info(frm->reg_cfg, syn, (Vepu541Fmt)fmt->format, enc_task);
         if (tile_num > 1)
-            hal_h265e_v580_set_uniform_tile(reg_base, syn, k);
+            hal_h265e_v580_set_uniform_tile(reg_base, syn, k, tile_start_x);
 
         if (k) {
             RK_U32 offset = 0;
@@ -2849,13 +2957,14 @@ MPP_RET hal_h265e_v580_start(void *hal, HalEncTask *enc_task)
 
             mpp_dev_multi_offset_update(frm->reg_cfg, 166, offset);
             mpp_dev_multi_offset_update(frm->reg_cfg, 164, offset);
+        }
 
-            if (enc_task->rc_task->frm.save_pass1)
-                vepu580_h265e_save_pass1_patch(hw_regs, ctx, syn->pp.tiles_enabled_flag);
+        if (enc_task->rc_task->frm.save_pass1)
+            vepu580_h265e_save_pass1_patch(hw_regs, ctx, syn->pp.tiles_enabled_flag);
+
+        if (enc_task->rc_task->frm.use_pass1)
+            vepu580_h265e_use_pass1_patch(hw_regs, ctx);
 
-            if (enc_task->rc_task->frm.use_pass1)
-                vepu580_h265e_use_pass1_patch(hw_regs, ctx);
-        }
         hal_h265e_v580_send_regs(ctx->dev, hw_regs, reg_out);
 
         mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFS, frm->reg_cfg);
@@ -2878,7 +2987,7 @@ MPP_RET hal_h265e_v580_start(void *hal, HalEncTask *enc_task)
                 fb->qp_sum += reg_out->st.qp_sum;
                 fb->out_strm_size += reg_out->st.bs_lgth_l32;
                 fb->sse_sum += (RK_S64)(reg_out->st.sse_h32 << 16) +
-                               ((reg_out->st.st_sse_bsl.sse_l16 >> 16) & 0xffff);
+                               (reg_out->st.st_sse_bsl.sse_l16 & 0xffff);
                 fb->st_madi += reg_out->st.madi;
                 fb->st_madp += reg_out->st.madp;
                 fb->st_mb_num += reg_out->st.st_bnum_b16.num_b16;
@@ -2886,6 +2995,7 @@ MPP_RET hal_h265e_v580_start(void *hal, HalEncTask *enc_task)
             } else
                 mpp_dev_ioctl(ctx->dev, MPP_DEV_DELIMIT, NULL);
         }
+        tile_start_x += (syn->pp.column_width_minus1[k] + 1);
     }
 
     ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL);
@@ -2915,7 +3025,7 @@ static MPP_RET vepu580_h265_set_feedback(H265eV580HalContext *ctx, HalEncTask *e
     fb->out_strm_size += elem->st.bs_lgth_l32;
 
     fb->sse_sum += (RK_S64)(elem->st.sse_h32 << 16) +
-                   ((elem->st.st_sse_bsl.sse_l16 >> 16) & 0xffff);
+                   (elem->st.st_sse_bsl.sse_l16 & 0xffff);
 
     fb->hw_status = hw_status;
     hal_h265e_dbg_detail("hw_status: 0x%08x", hw_status);
@@ -3106,6 +3216,10 @@ MPP_RET hal_h265e_v580_wait(void *hal, HalEncTask *task)
         return MPP_NOK;
     }
 
+    /* if pass1 mode, it will disable split mode and the split out need to be disable */
+    if (enc_task->rc_task->frm.save_pass1)
+        split_out = 0;
+
     if (split_out) {
         EncOutParam param;
         RK_U32 slice_len = 0;
@@ -3128,7 +3242,7 @@ MPP_RET hal_h265e_v580_wait(void *hal, HalEncTask *task)
             RK_S32 i = 0;
             poll_cfg->poll_type = 0;
             poll_cfg->poll_ret  = 0;
-            poll_cfg->count_max = ctx->poll_slice_max;
+            poll_cfg->count_max = split_out & MPP_ENC_SPLIT_OUT_LOWDELAY ? 1 : ctx->poll_slice_max;
             poll_cfg->count_ret = 0;
 
             ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, poll_cfg);
@@ -3270,14 +3384,14 @@ MPP_RET hal_h265e_v580_get_task(void *hal, HalEncTask *task)
 
         frm_cfg->hal_curr_idx = ctx->syn->sp.recon_pic.slot_idx;
         frm_cfg->hal_refr_idx = ctx->syn->sp.ref_pic.slot_idx;
-
-        h265e_dpb_hal_start(ctx->dpb, frm_cfg->hal_curr_idx);
-        h265e_dpb_hal_start(ctx->dpb, frm_cfg->hal_refr_idx);
     } else {
         /* reencode path may change the frame type */
         frm_cfg = ctx->frm;
     }
 
+    h265e_dpb_hal_start(ctx->dpb, frm_cfg->hal_curr_idx);
+    h265e_dpb_hal_start(ctx->dpb, frm_cfg->hal_refr_idx);
+
     ctx->frame_type = (frm_status->is_intra) ? INTRA_FRAME : INTER_P_FRAME;
     frm_cfg->frame_type = ctx->frame_type;
     mpp_dev_multi_offset_reset(frm_cfg->reg_cfg);
@@ -3290,17 +3404,18 @@ MPP_RET hal_h265e_v580_get_task(void *hal, HalEncTask *task)
 MPP_RET hal_h265e_v580_ret_task(void *hal, HalEncTask *task)
 {
     H265eV580HalContext *ctx = (H265eV580HalContext *)hal;
-    HalEncTask *enc_task = task;
     EncRcTaskInfo *rc_info = &task->rc_task->info;
+    HalEncTask *enc_task = task;
     RK_S32 task_idx = task->flags.reg_idx;
     Vepu580H265eFrmCfg *frm = ctx->frms[task_idx];
     Vepu580H265Fbk *fb = &frm->feedback;
+    H265eSyntax_new *syn = (H265eSyntax_new *) enc_task->syntax.data;
+    RK_U32 offset = mpp_packet_get_length(enc_task->packet);
 
     hal_h265e_enter();
 
     if (ctx->tile_parall_en) {
         RK_U32 i = 0, stream_len = 0;
-        RK_U32 offset = mpp_packet_get_length(enc_task->packet);
         void* ptr = mpp_packet_get_pos(enc_task->packet);
 
         for (i = 0; i < ctx->tile_num; i ++) {
@@ -3309,21 +3424,32 @@ MPP_RET hal_h265e_v580_ret_task(void *hal, HalEncTask *task)
                 if (i) {  //copy tile 1 stream
                     RK_U32 len = fb->out_strm_size - stream_len;
                     MppBuffer buf = frm->hw_tile_stream[i - 1];
-                    void *tile1_ptr  = mpp_buffer_get_ptr(buf);
+                    RK_U8 *tile1_ptr  = mpp_buffer_get_ptr(buf);
+
+                    mpp_buffer_sync_partial_begin(buf, 0, len);
+
+                    if (syn->sp.temporal_id && len > 5)
+                        tile1_ptr[5] = (tile1_ptr[5] & 0xf8) | ((syn->sp.temporal_id + 1) & 0x7);
 
-                    mpp_buffer_sync_ro_partial_begin(buf, 0, len);
                     memcpy(ptr + stream_len + offset, tile1_ptr, len);
                 } else {
                     MppBuffer buf = enc_task->output;
                     RK_U32 len = fb->out_strm_size;
+                    RK_U8 *stream_ptr = (RK_U8 *) ptr;
+
+                    mpp_buffer_sync_partial_begin(buf, offset, len);
 
-                    mpp_buffer_sync_ro_partial_begin(buf, offset, len);
+                    if (syn->sp.temporal_id) {
+                        stream_ptr[5] = (stream_ptr[5] & 0xf8) | ((syn->sp.temporal_id + 1) & 0x7);
+                    }
                 }
                 stream_len = fb->out_strm_size;
             }
         }
     } else {
         vepu580_h265_set_feedback(ctx, enc_task, ctx->tile_num - 1);
+        mpp_buffer_sync_partial_begin(enc_task->output, offset, fb->out_strm_size);
+        hal_h265e_amend_temporal_id(task, fb->out_strm_size);
     }
 
     rc_info->sse = fb->sse_sum;
@@ -3339,7 +3465,7 @@ MPP_RET hal_h265e_v580_ret_task(void *hal, HalEncTask *task)
     enc_task->hw_length = fb->out_strm_size;
     enc_task->length += fb->out_strm_size;
 
-    vepu580_h265e_tune_stat_update(ctx->tune);
+    vepu580_h265e_tune_stat_update(ctx->tune, rc_info);
 
     h265e_dpb_hal_end(ctx->dpb, frm->hal_curr_idx);
     h265e_dpb_hal_end(ctx->dpb, frm->hal_refr_idx);
diff --git a/mpp/hal/rkenc/h265e/hal_h265e_vepu580_tune.c b/mpp/hal/rkenc/h265e/hal_h265e_vepu580_tune.c
index 2bb292080..b85e5aa87 100644
--- a/mpp/hal/rkenc/h265e/hal_h265e_vepu580_tune.c
+++ b/mpp/hal/rkenc/h265e/hal_h265e_vepu580_tune.c
@@ -15,10 +15,14 @@
  */
 
 #include "vepu580_tune.h"
+#include "hal_h265e_vepu580_reg.h"
 
 #define HAL_H265E_DBG_CONTENT           (0x00200000)
 #define hal_h264e_dbg_content(fmt, ...) hal_h264e_dbg_f(HAL_H264E_DBG_CONTENT, fmt, ## __VA_ARGS__)
 
+#define CTU_BASE_CFG_BYTE 64
+#define CTU_QP_CFG_BYTE 192
+
 /*
  * Please follow the configuration below:
  *
@@ -227,6 +231,143 @@ static void vepu580_h265e_tune_deinit(void *tune)
     MPP_FREE(tune);
 }
 
+static void vepu580_h265e_tune_atf(H265eV580HalContext *ctx, RK_U32 sm_flag)
+{
+    H265eV580RegSet *regs = ctx->frm->regs_set[0];
+    vepu580_rdo_cfg  *reg_rdo = &regs->reg_rdo;
+    RdoAtfSkipCfg *s;
+    RdoAtfCfg* p;
+    RK_U32 atf_idx = ctx->cfg->tune.vmaf_opt ? 3 : sm_flag;
+
+    s = &reg_rdo->rdo_b64_skip_atf;
+    s->rdo_b_cime_thd0.cu_rdo_cime_thd0 = 1;
+    s->rdo_b_cime_thd0.cu_rdo_cime_thd1 = 2;
+    s->rdo_b_cime_thd1.cu_rdo_cime_thd2 = 4;
+    s->rdo_b_cime_thd1.cu_rdo_cime_thd3 = 6;
+
+    s->rdo_b_atf_wgt0.cu_rdo_atf_wgt00  = skip_b64_atf_wgt[atf_idx][0];
+    s->rdo_b_atf_wgt0.cu_rdo_atf_wgt10  = skip_b64_atf_wgt[atf_idx][1];
+    s->rdo_b_atf_wgt0.cu_rdo_atf_wgt11  = skip_b64_atf_wgt[atf_idx][2];
+    s->rdo_b_atf_wgt0.cu_rdo_atf_wgt12  = skip_b64_atf_wgt[atf_idx][3];
+    s->rdo_b_atf_wgt1.cu_rdo_atf_wgt20  = skip_b64_atf_wgt[atf_idx][4];
+    s->rdo_b_atf_wgt1.cu_rdo_atf_wgt21  = skip_b64_atf_wgt[atf_idx][5];
+    s->rdo_b_atf_wgt1.cu_rdo_atf_wgt22  = skip_b64_atf_wgt[atf_idx][6];
+    s->rdo_b_atf_wgt2.cu_rdo_atf_wgt30  = skip_b64_atf_wgt[atf_idx][7];
+    s->rdo_b_atf_wgt2.cu_rdo_atf_wgt31  = skip_b64_atf_wgt[atf_idx][8];
+    s->rdo_b_atf_wgt2.cu_rdo_atf_wgt32  = skip_b64_atf_wgt[atf_idx][9];
+    s->rdo_b_atf_wgt3.cu_rdo_atf_wgt40  = skip_b64_atf_wgt[atf_idx][10];
+    s->rdo_b_atf_wgt3.cu_rdo_atf_wgt41  = skip_b64_atf_wgt[atf_idx][11];
+    s->rdo_b_atf_wgt3.cu_rdo_atf_wgt42  = skip_b64_atf_wgt[atf_idx][12];
+
+    p = &reg_rdo->rdo_b32_intra_atf;
+    p->rdo_b_cime_thd0.cu_rdo_cime_thd0 = 24;
+    p->rdo_b_cime_thd0.cu_rdo_cime_thd1 = 48;
+    p->rdo_b_cime_thd1.cu_rdo_cime_thd2 = 64;
+    p->rdo_b_atf_wgt0.cu_rdo_atf_wgt00  = intra_b32_atf_wgt[atf_idx][0];
+    p->rdo_b_atf_wgt0.cu_rdo_atf_wgt01  = intra_b32_atf_wgt[atf_idx][1];
+    p->rdo_b_atf_wgt0.cu_rdo_atf_wgt02  = intra_b32_atf_wgt[atf_idx][2];
+    p->rdo_b_atf_wgt1.cu_rdo_atf_wgt10  = intra_b32_atf_wgt[atf_idx][3];
+    p->rdo_b_atf_wgt1.cu_rdo_atf_wgt11  = intra_b32_atf_wgt[atf_idx][4];
+    p->rdo_b_atf_wgt1.cu_rdo_atf_wgt12  = intra_b32_atf_wgt[atf_idx][5];
+    p->rdo_b_atf_wgt2.cu_rdo_atf_wgt20  = intra_b32_atf_wgt[atf_idx][6];
+    p->rdo_b_atf_wgt2.cu_rdo_atf_wgt21  = intra_b32_atf_wgt[atf_idx][7];
+    p->rdo_b_atf_wgt2.cu_rdo_atf_wgt22  = intra_b32_atf_wgt[atf_idx][8];
+    p->rdo_b_atf_wgt3.cu_rdo_atf_wgt30  = intra_b32_atf_wgt[atf_idx][9];
+    p->rdo_b_atf_wgt3.cu_rdo_atf_wgt31  = intra_b32_atf_wgt[atf_idx][10];
+    p->rdo_b_atf_wgt3.cu_rdo_atf_wgt32  = intra_b32_atf_wgt[atf_idx][11];
+
+    s = &reg_rdo->rdo_b32_skip_atf;
+    s->rdo_b_cime_thd0.cu_rdo_cime_thd0 =  1;
+    s->rdo_b_cime_thd0.cu_rdo_cime_thd1 =  2;
+    s->rdo_b_cime_thd1.cu_rdo_cime_thd2 =  4;
+    s->rdo_b_cime_thd1.cu_rdo_cime_thd3 =  6;
+    s->rdo_b_atf_wgt0.cu_rdo_atf_wgt00  =  skip_b32_atf_wgt[atf_idx][0];
+    s->rdo_b_atf_wgt0.cu_rdo_atf_wgt10  =  skip_b32_atf_wgt[atf_idx][1];
+    s->rdo_b_atf_wgt0.cu_rdo_atf_wgt11  =  skip_b32_atf_wgt[atf_idx][2];
+    s->rdo_b_atf_wgt0.cu_rdo_atf_wgt12  =  skip_b32_atf_wgt[atf_idx][3];
+    s->rdo_b_atf_wgt1.cu_rdo_atf_wgt20  =  skip_b32_atf_wgt[atf_idx][4];
+    s->rdo_b_atf_wgt1.cu_rdo_atf_wgt21  =  skip_b32_atf_wgt[atf_idx][5];
+    s->rdo_b_atf_wgt1.cu_rdo_atf_wgt22  =  skip_b32_atf_wgt[atf_idx][6];
+    s->rdo_b_atf_wgt2.cu_rdo_atf_wgt30  =  skip_b32_atf_wgt[atf_idx][7];
+    s->rdo_b_atf_wgt2.cu_rdo_atf_wgt31  =  skip_b32_atf_wgt[atf_idx][8];
+    s->rdo_b_atf_wgt2.cu_rdo_atf_wgt32  =  skip_b32_atf_wgt[atf_idx][9];
+    s->rdo_b_atf_wgt3.cu_rdo_atf_wgt40  =  skip_b32_atf_wgt[atf_idx][10];
+    s->rdo_b_atf_wgt3.cu_rdo_atf_wgt41  =  skip_b32_atf_wgt[atf_idx][11];
+    s->rdo_b_atf_wgt3.cu_rdo_atf_wgt42  =  skip_b32_atf_wgt[atf_idx][12];
+
+    p = &reg_rdo->rdo_b16_intra_atf;
+    p->rdo_b_cime_thd0.cu_rdo_cime_thd0 = 24;
+    p->rdo_b_cime_thd0.cu_rdo_cime_thd1 = 48;
+    p->rdo_b_cime_thd1.cu_rdo_cime_thd2 = 64;
+    p->rdo_b_atf_wgt0.cu_rdo_atf_wgt00  = intra_b16_atf_wgt[atf_idx][0];
+    p->rdo_b_atf_wgt0.cu_rdo_atf_wgt01  = intra_b16_atf_wgt[atf_idx][1];
+    p->rdo_b_atf_wgt0.cu_rdo_atf_wgt02  = intra_b16_atf_wgt[atf_idx][2];
+    p->rdo_b_atf_wgt1.cu_rdo_atf_wgt10  = intra_b16_atf_wgt[atf_idx][3];
+    p->rdo_b_atf_wgt1.cu_rdo_atf_wgt11  = intra_b16_atf_wgt[atf_idx][4];
+    p->rdo_b_atf_wgt1.cu_rdo_atf_wgt12  = intra_b16_atf_wgt[atf_idx][5];
+    p->rdo_b_atf_wgt2.cu_rdo_atf_wgt20  = intra_b16_atf_wgt[atf_idx][6];
+    p->rdo_b_atf_wgt2.cu_rdo_atf_wgt21  = intra_b16_atf_wgt[atf_idx][7];
+    p->rdo_b_atf_wgt2.cu_rdo_atf_wgt22  = intra_b16_atf_wgt[atf_idx][8];
+    p->rdo_b_atf_wgt3.cu_rdo_atf_wgt30  = intra_b16_atf_wgt[atf_idx][9];
+    p->rdo_b_atf_wgt3.cu_rdo_atf_wgt31  = intra_b16_atf_wgt[atf_idx][10];
+    p->rdo_b_atf_wgt3.cu_rdo_atf_wgt32  = intra_b16_atf_wgt[atf_idx][11];
+
+    s = &reg_rdo->rdo_b16_skip_atf;
+    s->rdo_b_cime_thd0.cu_rdo_cime_thd0 = 1;
+    s->rdo_b_cime_thd0.cu_rdo_cime_thd1 = 2;
+    s->rdo_b_cime_thd1.cu_rdo_cime_thd2 = 4;
+    s->rdo_b_cime_thd1.cu_rdo_cime_thd3 = 6;
+    s->rdo_b_atf_wgt0.cu_rdo_atf_wgt00  = skip_b16_atf_wgt[atf_idx][0];
+    s->rdo_b_atf_wgt0.cu_rdo_atf_wgt10  = skip_b16_atf_wgt[atf_idx][1];
+    s->rdo_b_atf_wgt0.cu_rdo_atf_wgt11  = skip_b16_atf_wgt[atf_idx][2];
+    s->rdo_b_atf_wgt0.cu_rdo_atf_wgt12  = skip_b16_atf_wgt[atf_idx][3];
+    s->rdo_b_atf_wgt1.cu_rdo_atf_wgt20  = skip_b16_atf_wgt[atf_idx][4];
+    s->rdo_b_atf_wgt1.cu_rdo_atf_wgt21  = skip_b16_atf_wgt[atf_idx][5];
+    s->rdo_b_atf_wgt1.cu_rdo_atf_wgt22  = skip_b16_atf_wgt[atf_idx][6];
+    s->rdo_b_atf_wgt2.cu_rdo_atf_wgt30  = skip_b16_atf_wgt[atf_idx][7];
+    s->rdo_b_atf_wgt2.cu_rdo_atf_wgt31  = skip_b16_atf_wgt[atf_idx][8];
+    s->rdo_b_atf_wgt2.cu_rdo_atf_wgt32  = skip_b16_atf_wgt[atf_idx][9];
+    s->rdo_b_atf_wgt3.cu_rdo_atf_wgt40  = skip_b16_atf_wgt[atf_idx][10];
+    s->rdo_b_atf_wgt3.cu_rdo_atf_wgt41  = skip_b16_atf_wgt[atf_idx][11];
+    s->rdo_b_atf_wgt3.cu_rdo_atf_wgt42  = skip_b16_atf_wgt[atf_idx][12];
+
+    p = &reg_rdo->rdo_b8_intra_atf;
+    p->rdo_b_cime_thd0.cu_rdo_cime_thd0 = 24;
+    p->rdo_b_cime_thd0.cu_rdo_cime_thd1 = 48;
+    p->rdo_b_cime_thd1.cu_rdo_cime_thd2 = 64;
+    p->rdo_b_atf_wgt0.cu_rdo_atf_wgt00  = intra_b8_atf_wgt[atf_idx][0];
+    p->rdo_b_atf_wgt0.cu_rdo_atf_wgt01  = intra_b8_atf_wgt[atf_idx][1];
+    p->rdo_b_atf_wgt0.cu_rdo_atf_wgt02  = intra_b8_atf_wgt[atf_idx][2];
+    p->rdo_b_atf_wgt1.cu_rdo_atf_wgt10  = intra_b8_atf_wgt[atf_idx][3];
+    p->rdo_b_atf_wgt1.cu_rdo_atf_wgt11  = intra_b8_atf_wgt[atf_idx][4];
+    p->rdo_b_atf_wgt1.cu_rdo_atf_wgt12  = intra_b8_atf_wgt[atf_idx][5];
+    p->rdo_b_atf_wgt2.cu_rdo_atf_wgt20  = intra_b8_atf_wgt[atf_idx][6];
+    p->rdo_b_atf_wgt2.cu_rdo_atf_wgt21  = intra_b8_atf_wgt[atf_idx][7];
+    p->rdo_b_atf_wgt2.cu_rdo_atf_wgt22  = intra_b8_atf_wgt[atf_idx][8];
+    p->rdo_b_atf_wgt3.cu_rdo_atf_wgt30  = intra_b8_atf_wgt[atf_idx][9];
+    p->rdo_b_atf_wgt3.cu_rdo_atf_wgt31  = intra_b8_atf_wgt[atf_idx][10];
+    p->rdo_b_atf_wgt3.cu_rdo_atf_wgt32  = intra_b8_atf_wgt[atf_idx][11];
+
+    s = &reg_rdo->rdo_b8_skip_atf;
+    s->rdo_b_cime_thd0.cu_rdo_cime_thd0 = 1;
+    s->rdo_b_cime_thd0.cu_rdo_cime_thd1 = 2;
+    s->rdo_b_cime_thd1.cu_rdo_cime_thd2 = 4;
+    s->rdo_b_cime_thd1.cu_rdo_cime_thd3 = 6;
+    s->rdo_b_atf_wgt0.cu_rdo_atf_wgt00  = skip_b8_atf_wgt[atf_idx][0];
+    s->rdo_b_atf_wgt0.cu_rdo_atf_wgt10  = skip_b8_atf_wgt[atf_idx][1];
+    s->rdo_b_atf_wgt0.cu_rdo_atf_wgt11  = skip_b8_atf_wgt[atf_idx][2];
+    s->rdo_b_atf_wgt0.cu_rdo_atf_wgt12  = skip_b8_atf_wgt[atf_idx][3];
+    s->rdo_b_atf_wgt1.cu_rdo_atf_wgt20  = skip_b8_atf_wgt[atf_idx][4];
+    s->rdo_b_atf_wgt1.cu_rdo_atf_wgt21  = skip_b8_atf_wgt[atf_idx][5];
+    s->rdo_b_atf_wgt1.cu_rdo_atf_wgt22  = skip_b8_atf_wgt[atf_idx][6];
+    s->rdo_b_atf_wgt2.cu_rdo_atf_wgt30  = skip_b8_atf_wgt[atf_idx][7];
+    s->rdo_b_atf_wgt2.cu_rdo_atf_wgt31  = skip_b8_atf_wgt[atf_idx][8];
+    s->rdo_b_atf_wgt2.cu_rdo_atf_wgt32  = skip_b8_atf_wgt[atf_idx][9];
+    s->rdo_b_atf_wgt3.cu_rdo_atf_wgt40  = skip_b8_atf_wgt[atf_idx][10];
+    s->rdo_b_atf_wgt3.cu_rdo_atf_wgt41  = skip_b8_atf_wgt[atf_idx][11];
+    s->rdo_b_atf_wgt3.cu_rdo_atf_wgt42  = skip_b8_atf_wgt[atf_idx][12];
+}
+
 static void vepu580_h265e_tune_reg_patch(void *p)
 {
     HalH265eVepu580Tune *tune = (HalH265eVepu580Tune *)p;
@@ -244,155 +385,33 @@ static void vepu580_h265e_tune_reg_patch(void *p)
     hevc_vepu580_rc_klut *rc_regs =  &regs->reg_rc_klut;
     hevc_vepu580_wgt *reg_wgt = &regs->reg_wgt;
     vepu580_rdo_cfg  *reg_rdo = &regs->reg_rdo;
-    RdoAtfSkipCfg *p_rdo_atf_skip;
-    RdoAtfCfg* p_rdo_atf;
     RK_U32 scene_motion_flag = tune->ap_motion_flag * 2 + tune->curr_scene_motion_flag;
     MppEncHwCfg *hw = &ctx->cfg->hw;
+    RK_S32 vmaf_opt = ctx->cfg->tune.vmaf_opt;
+    RK_U32 pre_intra_idx = vmaf_opt ? 3 : scene_motion_flag;
 
     if (scene_motion_flag > 3) {
         mpp_err_f("scene_motion_flag is a wrong value %d\n", scene_motion_flag);
         return;
     }
 
-    memcpy(&reg_wgt->lvl32_intra_CST_WGT0, lvl32_preintra_cst_wgt[scene_motion_flag], sizeof(lvl32_preintra_cst_wgt[scene_motion_flag]));
-    memcpy(&reg_wgt->lvl16_intra_CST_WGT0, lvl16_preintra_cst_wgt[scene_motion_flag], sizeof(lvl16_preintra_cst_wgt[scene_motion_flag]));
-
-    p_rdo_atf_skip = &reg_rdo->rdo_b64_skip_atf;
-    p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd0 = 1;
-    p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd1 = 2;
-    p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd2 = 4;
-    p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd3 = 6;
-
-    p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt00  = skip_b64_atf_wgt[scene_motion_flag][0];
-    p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt10  = skip_b64_atf_wgt[scene_motion_flag][1];
-    p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt11  = skip_b64_atf_wgt[scene_motion_flag][2];
-    p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt12  = skip_b64_atf_wgt[scene_motion_flag][3];
-    p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt20  = skip_b64_atf_wgt[scene_motion_flag][4];
-    p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt21  = skip_b64_atf_wgt[scene_motion_flag][5];
-    p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt22  = skip_b64_atf_wgt[scene_motion_flag][6];
-    p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt30  = skip_b64_atf_wgt[scene_motion_flag][7];
-    p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt31  = skip_b64_atf_wgt[scene_motion_flag][8];
-    p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt32  = skip_b64_atf_wgt[scene_motion_flag][9];
-    p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt40  = skip_b64_atf_wgt[scene_motion_flag][10];
-    p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt41  = skip_b64_atf_wgt[scene_motion_flag][11];
-    p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt42  = skip_b64_atf_wgt[scene_motion_flag][12];
-
-    p_rdo_atf = &reg_rdo->rdo_b32_intra_atf;
-    p_rdo_atf->rdo_b_cime_thd0.cu_rdo_cime_thd0 = 24;
-    p_rdo_atf->rdo_b_cime_thd0.cu_rdo_cime_thd1 = 48;
-    p_rdo_atf->rdo_b_cime_thd1.cu_rdo_cime_thd2 = 64;
-    p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt00  = intra_b32_atf_wgt[scene_motion_flag][0];
-    p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt01  = intra_b32_atf_wgt[scene_motion_flag][1];
-    p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt02  = intra_b32_atf_wgt[scene_motion_flag][2];
-    p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt10  = intra_b32_atf_wgt[scene_motion_flag][3];
-    p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt11  = intra_b32_atf_wgt[scene_motion_flag][4];
-    p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt12  = intra_b32_atf_wgt[scene_motion_flag][5];
-    p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt20  = intra_b32_atf_wgt[scene_motion_flag][6];
-    p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt21  = intra_b32_atf_wgt[scene_motion_flag][7];
-    p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt22  = intra_b32_atf_wgt[scene_motion_flag][8];
-    p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt30  = intra_b32_atf_wgt[scene_motion_flag][9];
-    p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt31  = intra_b32_atf_wgt[scene_motion_flag][10];
-    p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt32  = intra_b32_atf_wgt[scene_motion_flag][11];
-
-    p_rdo_atf_skip = &reg_rdo->rdo_b32_skip_atf;
-    p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd0 =  1;
-    p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd1 =  2;
-    p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd2 =  4;
-    p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd3 =  6;
-    p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt00  =  skip_b32_atf_wgt[scene_motion_flag][0];
-    p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt10  =  skip_b32_atf_wgt[scene_motion_flag][1];
-    p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt11  =  skip_b32_atf_wgt[scene_motion_flag][2];
-    p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt12  =  skip_b32_atf_wgt[scene_motion_flag][3];
-    p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt20  =  skip_b32_atf_wgt[scene_motion_flag][4];
-    p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt21  =  skip_b32_atf_wgt[scene_motion_flag][5];
-    p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt22  =  skip_b32_atf_wgt[scene_motion_flag][6];
-    p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt30  =  skip_b32_atf_wgt[scene_motion_flag][7];
-    p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt31  =  skip_b32_atf_wgt[scene_motion_flag][8];
-    p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt32  =  skip_b32_atf_wgt[scene_motion_flag][9];
-    p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt40  =  skip_b32_atf_wgt[scene_motion_flag][10];
-    p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt41  =  skip_b32_atf_wgt[scene_motion_flag][11];
-    p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt42  =  skip_b32_atf_wgt[scene_motion_flag][12];
-
-    p_rdo_atf = &reg_rdo->rdo_b16_intra_atf;
-    p_rdo_atf->rdo_b_cime_thd0.cu_rdo_cime_thd0 = 24;
-    p_rdo_atf->rdo_b_cime_thd0.cu_rdo_cime_thd1 = 48;
-    p_rdo_atf->rdo_b_cime_thd1.cu_rdo_cime_thd2 = 64;
-    p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt00  = intra_b16_atf_wgt[scene_motion_flag][0];
-    p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt01  = intra_b16_atf_wgt[scene_motion_flag][1];
-    p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt02  = intra_b16_atf_wgt[scene_motion_flag][2];
-    p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt10  = intra_b16_atf_wgt[scene_motion_flag][3];
-    p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt11  = intra_b16_atf_wgt[scene_motion_flag][4];
-    p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt12  = intra_b16_atf_wgt[scene_motion_flag][5];
-    p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt20  = intra_b16_atf_wgt[scene_motion_flag][6];
-    p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt21  = intra_b16_atf_wgt[scene_motion_flag][7];
-    p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt22  = intra_b16_atf_wgt[scene_motion_flag][8];
-    p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt30  = intra_b16_atf_wgt[scene_motion_flag][9];
-    p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt31  = intra_b16_atf_wgt[scene_motion_flag][10];
-    p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt32  = intra_b16_atf_wgt[scene_motion_flag][11];
-
-    p_rdo_atf_skip = &reg_rdo->rdo_b16_skip_atf;
-    p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd0 = 1;
-    p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd1 = 2;
-    p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd2 = 4;
-    p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd3 = 6;
-    p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt00  = skip_b16_atf_wgt[scene_motion_flag][0];
-    p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt10  = skip_b16_atf_wgt[scene_motion_flag][1];
-    p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt11  = skip_b16_atf_wgt[scene_motion_flag][2];
-    p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt12  = skip_b16_atf_wgt[scene_motion_flag][3];
-    p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt20  = skip_b16_atf_wgt[scene_motion_flag][4];
-    p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt21  = skip_b16_atf_wgt[scene_motion_flag][5];
-    p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt22  = skip_b16_atf_wgt[scene_motion_flag][6];
-    p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt30  = skip_b16_atf_wgt[scene_motion_flag][7];
-    p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt31  = skip_b16_atf_wgt[scene_motion_flag][8];
-    p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt32  = skip_b16_atf_wgt[scene_motion_flag][9];
-    p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt40  = skip_b16_atf_wgt[scene_motion_flag][10];
-    p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt41  = skip_b16_atf_wgt[scene_motion_flag][11];
-    p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt42  = skip_b16_atf_wgt[scene_motion_flag][12];
-
-    p_rdo_atf = &reg_rdo->rdo_b8_intra_atf;
-    p_rdo_atf->rdo_b_cime_thd0.cu_rdo_cime_thd0 = 24;
-    p_rdo_atf->rdo_b_cime_thd0.cu_rdo_cime_thd1 = 48;
-    p_rdo_atf->rdo_b_cime_thd1.cu_rdo_cime_thd2 = 64;
-    p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt00  = intra_b8_atf_wgt[scene_motion_flag][0];
-    p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt01  = intra_b8_atf_wgt[scene_motion_flag][1];
-    p_rdo_atf->rdo_b_atf_wgt0.cu_rdo_atf_wgt02  = intra_b8_atf_wgt[scene_motion_flag][2];
-    p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt10  = intra_b8_atf_wgt[scene_motion_flag][3];
-    p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt11  = intra_b8_atf_wgt[scene_motion_flag][4];
-    p_rdo_atf->rdo_b_atf_wgt1.cu_rdo_atf_wgt12  = intra_b8_atf_wgt[scene_motion_flag][5];
-    p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt20  = intra_b8_atf_wgt[scene_motion_flag][6];
-    p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt21  = intra_b8_atf_wgt[scene_motion_flag][7];
-    p_rdo_atf->rdo_b_atf_wgt2.cu_rdo_atf_wgt22  = intra_b8_atf_wgt[scene_motion_flag][8];
-    p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt30  = intra_b8_atf_wgt[scene_motion_flag][9];
-    p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt31  = intra_b8_atf_wgt[scene_motion_flag][10];
-    p_rdo_atf->rdo_b_atf_wgt3.cu_rdo_atf_wgt32  = intra_b8_atf_wgt[scene_motion_flag][11];
-
-    p_rdo_atf_skip = &reg_rdo->rdo_b8_skip_atf;
-    p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd0 = 1;
-    p_rdo_atf_skip->rdo_b_cime_thd0.cu_rdo_cime_thd1 = 2;
-    p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd2 = 4;
-    p_rdo_atf_skip->rdo_b_cime_thd1.cu_rdo_cime_thd3 = 6;
-    p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt00  = skip_b8_atf_wgt[scene_motion_flag][0];
-    p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt10  = skip_b8_atf_wgt[scene_motion_flag][1];
-    p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt11  = skip_b8_atf_wgt[scene_motion_flag][2];
-    p_rdo_atf_skip->rdo_b_atf_wgt0.cu_rdo_atf_wgt12  = skip_b8_atf_wgt[scene_motion_flag][3];
-    p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt20  = skip_b8_atf_wgt[scene_motion_flag][4];
-    p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt21  = skip_b8_atf_wgt[scene_motion_flag][5];
-    p_rdo_atf_skip->rdo_b_atf_wgt1.cu_rdo_atf_wgt22  = skip_b8_atf_wgt[scene_motion_flag][6];
-    p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt30  = skip_b8_atf_wgt[scene_motion_flag][7];
-    p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt31  = skip_b8_atf_wgt[scene_motion_flag][8];
-    p_rdo_atf_skip->rdo_b_atf_wgt2.cu_rdo_atf_wgt32  = skip_b8_atf_wgt[scene_motion_flag][9];
-    p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt40  = skip_b8_atf_wgt[scene_motion_flag][10];
-    p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt41  = skip_b8_atf_wgt[scene_motion_flag][11];
-    p_rdo_atf_skip->rdo_b_atf_wgt3.cu_rdo_atf_wgt42  = skip_b8_atf_wgt[scene_motion_flag][12];
+    memcpy(&reg_wgt->lvl32_intra_CST_WGT0, lvl32_preintra_cst_wgt[pre_intra_idx],
+           sizeof(lvl32_preintra_cst_wgt[pre_intra_idx]));
+    memcpy(&reg_wgt->lvl16_intra_CST_WGT0, lvl16_preintra_cst_wgt[pre_intra_idx],
+           sizeof(lvl16_preintra_cst_wgt[pre_intra_idx]));
+
+    /* Do not adjust the ATF weight when skip bias is enabled */
+    if (!hw->skip_bias_en)
+        vepu580_h265e_tune_atf(ctx, scene_motion_flag);
 
     reg_rdo->preintra_b32_cst_wgt.pre_intra32_cst_wgt00 = pre_intra_b32_cost[scene_motion_flag][0];
     reg_rdo->preintra_b32_cst_wgt.pre_intra32_cst_wgt01 = pre_intra_b32_cost[scene_motion_flag][1];
     reg_rdo->preintra_b16_cst_wgt.pre_intra16_cst_wgt00 = pre_intra_b16_cost[scene_motion_flag][0];
     reg_rdo->preintra_b16_cst_wgt.pre_intra16_cst_wgt01 = pre_intra_b16_cost[scene_motion_flag][1];
 
-    rc_regs->md_sad_thd.md_sad_thd0 = 4;
-    rc_regs->md_sad_thd.md_sad_thd1 = 9;
-    rc_regs->md_sad_thd.md_sad_thd2 = 15;
+    rc_regs->md_sad_thd.md_sad_thd0 = 7;
+    rc_regs->md_sad_thd.md_sad_thd1 = 15;
+    rc_regs->md_sad_thd.md_sad_thd2 = 25;
     rc_regs->madi_thd.madi_thd0     = 4;
     rc_regs->madi_thd.madi_thd1     = 9;
     rc_regs->madi_thd.madi_thd2     = 15;
@@ -411,8 +430,8 @@ static void vepu580_h265e_tune_reg_patch(void *p)
         reg_wgt->fme_sqi_thd1.move_lambda = 8;
     }
 
-    reg_rdo->rdo_sqi_cfg.rdo_segment_en = !tune->curr_scene_motion_flag;
-    reg_rdo->rdo_sqi_cfg.rdo_smear_en = !tune->curr_scene_motion_flag;
+    reg_rdo->rdo_sqi_cfg.rdo_segment_en = vmaf_opt ? 0 : !tune->curr_scene_motion_flag;
+    reg_rdo->rdo_sqi_cfg.rdo_smear_en = vmaf_opt ? 0 : !tune->curr_scene_motion_flag;
 
     reg_wgt->i16_sobel_a_00.intra_l16_sobel_a0_qp0 = intra_lvl16_sobel_a[scene_motion_flag][0];
     reg_wgt->i16_sobel_a_00.intra_l16_sobel_a0_qp1 = intra_lvl16_sobel_a[scene_motion_flag][1];
@@ -453,12 +472,13 @@ static void vepu580_h265e_tune_reg_patch(void *p)
     reg_wgt->i32_sobel_c.intra_l32_sobel_c1_qp4 = intra_lvl32_sobel_c[scene_motion_flag][4];
 
     if (hw->qbias_en) {
-        reg_wgt->reg1484_qnt_bias_comb.qnt_bias_i = hw->qbias_i;
-        reg_wgt->reg1484_qnt_bias_comb.qnt_bias_p = hw->qbias_p;
+        reg_wgt->reg1484_qnt_bias_comb.qnt_bias_i = hw->qbias_i ? hw->qbias_i : 171;
+        reg_wgt->reg1484_qnt_bias_comb.qnt_bias_p = hw->qbias_p ? hw->qbias_p : 85;
     } else {
         reg_wgt->reg1484_qnt_bias_comb.qnt_bias_i = qnt_bias_i[scene_motion_flag];
         reg_wgt->reg1484_qnt_bias_comb.qnt_bias_p = qnt_bias_p[scene_motion_flag];
     }
+
     reg_wgt->rime_sqi_thd.cime_sad_th0 = rime_sqi_cime_sad_th[scene_motion_flag];
     reg_wgt->fme_sqi_thd0.cime_sad_pu16_th = fme_sqi_cime_sad_pu16_th[scene_motion_flag];
     reg_wgt->fme_sqi_thd0.cime_sad_pu32_th = fme_sqi_cime_sad_pu32_th[scene_motion_flag];
@@ -466,7 +486,7 @@ static void vepu580_h265e_tune_reg_patch(void *p)
     rc_regs->klut_ofst.chrm_klut_ofst = chrm_klut_ofst[scene_motion_flag];
 }
 
-static void vepu580_h265e_tune_stat_update(void *p)
+static void vepu580_h265e_tune_stat_update(void *p, EncRcTaskInfo *rc_info)
 {
     HalH265eVepu580Tune *tune = (HalH265eVepu580Tune *)p;
     H265eV580HalContext *ctx = NULL;
@@ -503,9 +523,16 @@ static void vepu580_h265e_tune_stat_update(void *p)
     RK_S32 nScore = 0;
     RK_S32 nScoreT = ((MD_WIN_LEN - 2) * 6 + 2 * 8 + 2 * 11 + 2 * 13) / 2;
     RK_S32 madp_cnt_statistics[5];
+    RK_U32 md_cnt = (24 * fb->st_md_sad_b16num3 + 22 * fb->st_md_sad_b16num2 + 17 *
+                     fb->st_md_sad_b16num1) >> 2;
+    RK_U32 madi_cnt = (6 * fb->st_madi_b16num3 + 5 * fb->st_madi_b16num2 + 4 *
+                       fb->st_madi_b16num1) >> 2;
+    RK_U32 mbs = ((ctx->cfg->prep.width + 15) / 16) * ((ctx->cfg->prep.height + 15) / 16);
     for (i = 0; i < 5; i++) {
-        madp_cnt_statistics[i] = fb->st_md_sad_b16num0 * madp_num_map[i][0] + fb->st_md_sad_b16num1 * madp_num_map[i][1]
-                                 + fb->st_md_sad_b16num2 * madp_num_map[i][2] + fb->st_md_sad_b16num3 * madp_num_map[i][3];
+        madp_cnt_statistics[i] = fb->st_md_sad_b16num0 * madp_num_map[i][0] +
+                                 fb->st_md_sad_b16num1 * madp_num_map[i][1] +
+                                 fb->st_md_sad_b16num2 * madp_num_map[i][2] +
+                                 fb->st_md_sad_b16num3 * madp_num_map[i][3];
     }
 
     tune->pre_madi[0] = fb->st_madi;
@@ -558,7 +585,8 @@ static void vepu580_h265e_tune_stat_update(void *p)
     tune->curr_scene_motion_flag = 0;
     if (tune->md_flag_matrix[0] && tune->md_flag_matrix[1] && tune->md_flag_matrix[2]) {
         tune->curr_scene_motion_flag = 1;
-    } else if ((tune->md_flag_matrix[0] && tune->md_flag_matrix[1]) || (tune->md_flag_matrix[1] && tune->md_flag_matrix[2] && tune->md_flag_matrix[3])) {
+    } else if ((tune->md_flag_matrix[0] && tune->md_flag_matrix[1]) ||
+               (tune->md_flag_matrix[1] && tune->md_flag_matrix[2] && tune->md_flag_matrix[3])) {
         tune->curr_scene_motion_flag = md_flag;
     }
 
@@ -580,4 +608,73 @@ static void vepu580_h265e_tune_stat_update(void *p)
 
     tune->pre_madi[1] = tune->pre_madi[0];
     tune->pre_madp[1] = tune->pre_madp[0];
+
+    rc_info->motion_level = 0;
+    if (md_cnt * 100 > 15 * mbs)
+        rc_info->motion_level = 200;
+    else if (md_cnt * 100 > 5 * mbs)
+        rc_info->motion_level = 100;
+    else
+        rc_info->motion_level = 0;
+
+    rc_info->complex_level = 0;
+    if (madi_cnt * 100 > 30 * mbs)
+        rc_info->complex_level = 2;
+    else if (madi_cnt * 100 > 13 * mbs)
+        rc_info->complex_level = 1;
+    else
+        rc_info->complex_level = 0;
+    hal_h265e_dbg_detail("motion_level = %u, complex_level = %u\n", rc_info->motion_level,
+                         rc_info->complex_level);
 }
+
+static MPP_RET vepu580_setup_qpmap_buf(H265eV580HalContext *ctx)
+{
+    MPP_RET ret = MPP_OK;
+    RK_S32 w = ctx->cfg->prep.width;
+    RK_S32 h = ctx->cfg->prep.height;
+    RK_S32 ctu_w = MPP_ALIGN(w, 64) / 64;
+    RK_S32 ctu_h = MPP_ALIGN(h, 64) / 64;
+    RK_S32 qpmap_base_cfg_size   = ctx->qpmap_base_cfg_size
+                                   = ctu_w * ctu_h * 64;
+    RK_S32 qpmap_qp_cfg_size     = ctx->qpmap_qp_cfg_size
+                                   = ctu_w * ctu_h * 192;
+    RK_S32 md_flag_size = ctx->md_flag_size
+                          = ctu_w * ctu_h * 16;
+
+    if (!ctx->cfg->tune.deblur_en) {
+        mpp_log("deblurring is closed!\n");
+        goto __RET;
+    }
+
+    if (NULL == ctx->qpmap_base_cfg_buf) {
+        mpp_buffer_get(NULL, &ctx->qpmap_base_cfg_buf, qpmap_base_cfg_size);
+        if (!ctx->qpmap_base_cfg_buf) {
+            mpp_err("qpmap_base_cfg_buf malloc fail, qpmap invalid\n");
+            ret = MPP_ERR_VALUE;
+            goto __RET;
+        }
+    }
+
+    if (NULL == ctx->qpmap_qp_cfg_buf) {
+        mpp_buffer_get(NULL, &ctx->qpmap_qp_cfg_buf, qpmap_qp_cfg_size);
+        if (!ctx->qpmap_qp_cfg_buf) {
+            mpp_err("qpmap_qp_cfg_buf malloc fail, qpmap invalid\n");
+            ret = MPP_ERR_VALUE;
+            goto __RET;
+        }
+    }
+
+    if (NULL == ctx->md_flag_buf) {
+        ctx->md_flag_buf = mpp_malloc(RK_U8, md_flag_size);
+        if (!ctx->md_flag_buf) {
+            mpp_err("md_flag_buf malloc fail, qpmap invalid\n");
+            ret = MPP_ERR_VALUE;
+            goto __RET;
+        }
+    }
+
+__RET:
+    hal_h265e_dbg_func("leave, ret %d\n", ret);
+    return ret;
+}
\ No newline at end of file
diff --git a/mpp/hal/rkenc/jpege/CMakeLists.txt b/mpp/hal/rkenc/jpege/CMakeLists.txt
index 75f809c16..a78f38cf9 100644
--- a/mpp/hal/rkenc/jpege/CMakeLists.txt
+++ b/mpp/hal/rkenc/jpege/CMakeLists.txt
@@ -6,11 +6,14 @@ include_directories(../common/)
 # hal jpeg header
 set(HAL_JPEGE_HDR
     hal_jpege_vepu540c_reg.h
+    hal_jpege_vpu720_reg.h
+    hal_jpege_vpu720.h
     )
 
 # hal jpeg encoder sourse
 set(HAL_JPEGE_SRC
     hal_jpege_vepu540c.c
+    hal_jpege_vpu720.c
     )
 
 add_library(hal_jpege_rkv STATIC
@@ -18,5 +21,5 @@ add_library(hal_jpege_rkv STATIC
             ${HAL_JPEGE_SRC}
             )
 
-target_link_libraries(hal_jpege_rkv  hal_jpege hal_common hal_vepu541_common)
+target_link_libraries(hal_jpege_rkv  hal_jpege_com hal_common hal_vepu541_common)
 set_target_properties(hal_jpege_rkv  PROPERTIES FOLDER "mpp/hal")
diff --git a/mpp/hal/rkenc/jpege/hal_jpege_vpu720.c b/mpp/hal/rkenc/jpege/hal_jpege_vpu720.c
new file mode 100644
index 000000000..547a04a5d
--- /dev/null
+++ b/mpp/hal/rkenc/jpege/hal_jpege_vpu720.c
@@ -0,0 +1,665 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#define MODULE_TAG "hal_jpege_vpu720"
+
+#include <string.h>
+
+#include "mpp_mem.h"
+#include "mpp_env.h"
+#include "mpp_common.h"
+#include "mpp_buffer_impl.h"
+#include "mpp_enc_hal.h"
+
+#include "jpege_syntax.h"
+#include "hal_jpege_hdr.h"
+#include "hal_jpege_debug.h"
+#include "hal_jpege_vpu720.h"
+#include "hal_jpege_vpu720_reg.h"
+
+typedef enum JpegeVpu720InFmt_e {
+    JPEGE_VPU720_IN_FMT_TILE_400,
+    JPEGE_VPU720_IN_FMT_TILE_420,
+    JPEGE_VPU720_IN_FMT_TILE_422,
+    JPEGE_VPU720_IN_FMT_TILE_444,
+    JPEGE_VPU720_IN_FMT_YUV422SP,
+    JPEGE_VPU720_IN_FMT_YUV422P,
+    JPEGE_VPU720_IN_FMT_YUV420SP,
+    JPEGE_VPU720_IN_FMT_YUV420P,
+    JPEGE_VPU720_IN_FMT_YUYV,
+    JPEGE_VPU720_IN_FMT_UYVY,
+    JPEGE_VPU720_IN_FMT_YUV400,
+    JPEGE_VPU720_IN_FMT_RESERVED,
+    JPEGE_VPU720_IN_FMT_YUV444SP,
+    JPEGE_VPU720_IN_FMT_YUV444P,
+} JpegeVpu720InFmt;
+
+typedef enum JpegeVpu720OutFmt_e {
+    JPEGE_VPU720_OUT_FMT_400 = 0,
+    JPEGE_VPU720_OUT_FMT_420 = 1,
+    JPEGE_VPU720_OUT_FMT_422 = 2,
+    JPEGE_VPU720_OUT_FMT_444 = 3,
+} JpegeVpu720OutFmt;
+
+typedef enum JpegeVpu720EncCmd_e {
+    JPEG_VPU720_ENC_MODE_NONE,
+    JPEG_VPU720_ENC_MODE_ONE_FRAME,
+    JPEG_VPU720_ENC_MODE_MULTI_FRAME_START,
+    JPEG_VPU720_ENC_MODE_MULTI_FRAME_UPDATE,
+    JPEG_VPU720_ENC_MODE_LKT_FORCE_PAUSE,
+    JPEG_VPU720_ENC_MODE_LKT_CONTINUE,
+    JPEG_VPU720_ENC_MODE_SAFE_CLR,
+    JPEG_VPU720_ENC_MODE_FORCE_CLR,
+    JPEG_VPU720_ENC_MODE_FORCE_BUTT,
+} JpegeVpu720EncCmd;
+
+typedef enum JPEGVpu720ColorRangeTrans_t {
+    JPEG_VPU720_COLOR_RANGE_FULL_TO_LIMIT,
+    JPEG_VPU720_COLOR_RANGE_LIMIT_TO_FULL,
+} JPEGVpu720ColorRangeTrans;
+
+typedef enum JPEGVpu720ChromaDownSampleMode_t {
+    JPEG_VPU720_CHROMA_DOWN_SAMPLE_MODE_Average,
+    JPEG_VPU720_CHROMA_DOWN_SAMPLE_MODE_Discard,
+} JPEGVpu720ChromaDownSampleMode;
+
+typedef struct JpegeVpu720FmtCfg_t {
+    JpegeVpu720InFmt input_format;
+    JpegeVpu720OutFmt out_format;
+    MppFrameColorRange src_range;
+    MppFrameColorRange dst_range;
+    JPEGVpu720ChromaDownSampleMode chroma_ds_mode;
+    RK_U32 uv_swap;
+    RK_U32 mirror;
+    RK_U32 fix_chroma_en;
+    RK_U32 fix_chroma_u;
+    RK_U32 fix_chroma_v;
+    RK_U32 out_nb_comp;
+    RK_U32 y_stride;
+    RK_U32 uv_stride;
+    RK_U32 u_offset;
+    RK_U32 v_offset;
+} JpegeVpu720FmtCfg;
+
+typedef struct JpegeVpu720HalCtx_t {
+    MppEncHalApi        api;
+    MppDev              dev;
+    void                *regs;
+
+    /* @frame_cnt starts from ZERO */
+    RK_U32              frame_cnt;
+    MppEncCfgSet        *cfg;
+
+    RK_U32              enc_mode;
+    RK_U32              frame_size;
+    RK_S32              max_buf_cnt;
+    RK_S32              hdr_status;
+    JpegeVpu720FmtCfg   fmt_cfg;
+    RK_U8               *src_buf;
+    RK_U8               *dst_buf;
+    RK_S32              buf_size;
+    RK_U32              frame_num;
+
+    JpegeBits           bits;
+    JpegeSyntax         syntax;
+    RK_S32              hal_start_pos;
+
+    MppBufferGroup      group;
+    MppBuffer           qtbl_buffer;
+    RK_U16              *qtbl_sw_buf;
+} JpegeVpu720HalCtx;
+
+#define JPEGE_VPU720_QTABLE_SIZE (64 * 3)
+
+static MPP_RET hal_jpege_vpu720_init(void *hal, MppEncHalCfg *cfg)
+{
+    MPP_RET ret = MPP_OK;
+    JpegeVpu720HalCtx *ctx = (JpegeVpu720HalCtx *)hal;
+
+    mpp_env_get_u32("hal_jpege_debug", &hal_jpege_debug, 0);
+
+    hal_jpege_enter();
+
+    ctx->regs   = mpp_calloc(JpegeVpu720Reg, 1);
+    ctx->cfg    = cfg->cfg;
+
+    ctx->frame_cnt = 0;
+    ctx->enc_mode = JPEG_VPU720_ENC_MODE_ONE_FRAME;
+    cfg->type = VPU_CLIENT_JPEG_ENC;
+    ret = mpp_dev_init(&cfg->dev, cfg->type);
+    if (ret) {
+        mpp_err_f("mpp_dev_init failed. ret: %d\n", ret);
+        return ret;
+    }
+
+    ctx->dev = cfg->dev;
+    jpege_bits_init(&ctx->bits);
+    mpp_assert(ctx->bits);
+    if (ctx->group == NULL) {
+        ret = mpp_buffer_group_get_internal(&ctx->group, MPP_BUFFER_TYPE_ION);
+        if (ret) {
+            mpp_err_f("mpp_buffer_group_get failed ret %d\n", ret);
+            return ret;
+        }
+    }
+
+    ret = mpp_buffer_get(ctx->group, &ctx->qtbl_buffer, JPEGE_VPU720_QTABLE_SIZE * sizeof(RK_U16));
+    mpp_buffer_attach_dev(ctx->qtbl_buffer, ctx->dev);
+    ctx->qtbl_sw_buf = (RK_U16 *)mpp_calloc(RK_U16, JPEGE_VPU720_QTABLE_SIZE);
+
+    hal_jpege_leave();
+    return ret;
+}
+
+static MPP_RET hal_jpege_vpu720_deinit(void *hal)
+{
+    MPP_RET ret = MPP_OK;
+    JpegeVpu720HalCtx *ctx = (JpegeVpu720HalCtx *)hal;
+
+    hal_jpege_enter();
+    jpege_bits_deinit(ctx->bits);
+
+    MPP_FREE(ctx->regs);
+    MPP_FREE(ctx->qtbl_sw_buf);
+
+    if (ctx->dev) {
+        mpp_dev_deinit(ctx->dev);
+        ctx->dev = NULL;
+    }
+
+    if (ctx->qtbl_buffer) {
+        ret = mpp_buffer_put(ctx->qtbl_buffer);
+        if (ret) {
+            mpp_err_f("put qtbl buffer failed\n");
+        }
+    }
+
+    if (ctx->group) {
+        ret = mpp_buffer_group_put(ctx->group);
+        if (ret) {
+            mpp_err_f("group free buffer failed\n");
+        }
+    }
+
+    hal_jpege_leave();
+    return MPP_OK;
+}
+
+static MPP_RET jpege_vpu720_setup_format(void *hal, HalEncTask *task)
+{
+    JpegeVpu720HalCtx *ctx = (JpegeVpu720HalCtx *) hal;
+    MppFrameFormat in_fmt = ctx->cfg->prep.format & MPP_FRAME_FMT_MASK;
+    JpegeVpu720FmtCfg *fmt_cfg = &ctx->fmt_cfg;
+    JpegeSyntax *syntax = &ctx->syntax;
+    MppFrameChromaFormat out_fmt = syntax->format_out;
+    RK_U32 hor_stride = mpp_frame_get_hor_stride(task->frame);
+    RK_U32 ver_stride = mpp_frame_get_ver_stride(task->frame);
+
+    hal_jpege_enter();
+
+    memset(fmt_cfg, 0, sizeof(JpegeVpu720FmtCfg));
+
+    if (MPP_FRAME_FMT_IS_TILE(ctx->cfg->prep.format)) {
+        switch (in_fmt) {
+        case MPP_FMT_YUV400:
+            fmt_cfg->input_format = JPEGE_VPU720_IN_FMT_TILE_400;
+            fmt_cfg->y_stride = hor_stride * 4;
+            fmt_cfg->out_format = JPEGE_VPU720_OUT_FMT_400;
+            break;
+        case MPP_FMT_YUV420P:
+        case MPP_FMT_YUV420SP:
+            fmt_cfg->input_format = JPEGE_VPU720_IN_FMT_TILE_420;
+            fmt_cfg->y_stride = hor_stride * 4 * 3 / 2;
+            break;
+        case MPP_FMT_YUV422P:
+        case MPP_FMT_YUV422SP:
+            fmt_cfg->input_format = JPEGE_VPU720_IN_FMT_TILE_422;
+            fmt_cfg->y_stride = hor_stride * 4 * 2;
+            break;
+        case MPP_FMT_YUV444P:
+        case MPP_FMT_YUV444SP:
+            fmt_cfg->input_format = JPEGE_VPU720_IN_FMT_TILE_444;
+            fmt_cfg->y_stride = hor_stride * 4 * 3;
+            break;
+        default:
+            mpp_err("Unsupported input format 0x%08x, with TILE mask.\n", in_fmt);
+            return MPP_ERR_VALUE;
+            break;
+        }
+    } else {
+        switch (in_fmt) {
+        case MPP_FMT_YUV400:
+            fmt_cfg->input_format = JPEGE_VPU720_IN_FMT_YUV400;
+            fmt_cfg->y_stride = hor_stride;
+            fmt_cfg->out_format = JPEGE_VPU720_OUT_FMT_400;
+            break;
+        case MPP_FMT_YUV420P:
+            fmt_cfg->input_format = JPEGE_VPU720_IN_FMT_YUV420P;
+            fmt_cfg->y_stride = hor_stride;
+            fmt_cfg->uv_stride = hor_stride >> 1;
+            fmt_cfg->u_offset = hor_stride * ver_stride;
+            fmt_cfg->v_offset = fmt_cfg->u_offset + fmt_cfg->uv_stride * (ver_stride >> 1);
+            break;
+        case MPP_FMT_YUV420SP:
+            fmt_cfg->input_format = JPEGE_VPU720_IN_FMT_YUV420SP;
+            fmt_cfg->y_stride = hor_stride;
+            fmt_cfg->uv_stride = hor_stride;
+            fmt_cfg->u_offset = hor_stride * ver_stride;
+            break;
+        case MPP_FMT_YUV420SP_VU:
+            fmt_cfg->input_format = JPEGE_VPU720_IN_FMT_YUV420SP;
+            fmt_cfg->y_stride = hor_stride;
+            fmt_cfg->uv_stride = hor_stride;
+            fmt_cfg->u_offset = hor_stride * ver_stride;
+            fmt_cfg->uv_swap = 1;
+            break;
+        case MPP_FMT_YUV422P:
+            fmt_cfg->input_format = JPEGE_VPU720_IN_FMT_YUV422P;
+            fmt_cfg->y_stride = hor_stride;
+            fmt_cfg->uv_stride = hor_stride >> 1;
+            fmt_cfg->u_offset = hor_stride * ver_stride;
+            fmt_cfg->v_offset = fmt_cfg->u_offset + fmt_cfg->uv_stride * ver_stride;
+            break;
+        case MPP_FMT_YUV422SP:
+            fmt_cfg->input_format = JPEGE_VPU720_IN_FMT_YUV422SP;
+            fmt_cfg->y_stride = hor_stride;
+            fmt_cfg->uv_stride = hor_stride;
+            fmt_cfg->u_offset = hor_stride * ver_stride;
+            break;
+        case MPP_FMT_YUV422SP_VU:
+            fmt_cfg->input_format = JPEGE_VPU720_IN_FMT_YUV422SP;
+            fmt_cfg->y_stride = hor_stride;
+            fmt_cfg->uv_stride = hor_stride;
+            fmt_cfg->u_offset = hor_stride * ver_stride;
+            fmt_cfg->uv_swap = 1;
+            break;
+        case MPP_FMT_YUV422_YUYV:
+            fmt_cfg->input_format = JPEGE_VPU720_IN_FMT_YUYV;
+            fmt_cfg->y_stride = hor_stride;
+            break;
+        case MPP_FMT_YUV422_UYVY:
+            fmt_cfg->input_format = JPEGE_VPU720_IN_FMT_UYVY;
+            fmt_cfg->y_stride = hor_stride;
+            break;
+        case MPP_FMT_YUV422_YVYU:
+            fmt_cfg->input_format = JPEGE_VPU720_IN_FMT_YUYV;
+            fmt_cfg->y_stride = hor_stride;
+            fmt_cfg->uv_swap = 1;
+            break;
+        case MPP_FMT_YUV422_VYUY:
+            fmt_cfg->input_format = JPEGE_VPU720_IN_FMT_UYVY;
+            fmt_cfg->y_stride = hor_stride;
+            fmt_cfg->uv_swap = 1;
+            break;
+        case MPP_FMT_YUV444SP:
+            fmt_cfg->input_format = JPEGE_VPU720_IN_FMT_YUV444SP;
+            fmt_cfg->y_stride = hor_stride;
+            fmt_cfg->uv_stride = hor_stride << 1;
+            fmt_cfg->u_offset = hor_stride * ver_stride;
+            break;
+        case MPP_FMT_YUV444P:
+            fmt_cfg->input_format = JPEGE_VPU720_IN_FMT_YUV444P;
+            fmt_cfg->y_stride = hor_stride;
+            fmt_cfg->uv_stride = hor_stride;
+            fmt_cfg->u_offset = hor_stride * ver_stride;
+            fmt_cfg->v_offset = fmt_cfg->u_offset  << 1;
+            break;
+        default :
+            mpp_err("Unsupported input format 0x%08x\n", in_fmt);
+            return MPP_ERR_VALUE;
+            break;
+        }
+    }
+
+    switch (out_fmt) {
+    case MPP_CHROMA_400:
+        ctx->fmt_cfg.out_format = JPEGE_VPU720_OUT_FMT_400;
+        break;
+    case MPP_CHROMA_420:
+        ctx->fmt_cfg.out_format = JPEGE_VPU720_OUT_FMT_420;
+        break;
+    case MPP_CHROMA_422:
+        ctx->fmt_cfg.out_format = JPEGE_VPU720_OUT_FMT_422;
+        break;
+    case MPP_CHROMA_444:
+        ctx->fmt_cfg.out_format = JPEGE_VPU720_OUT_FMT_444;
+        break;
+    default:
+        ctx->fmt_cfg.out_format = JPEGE_VPU720_OUT_FMT_420;
+        break;
+    }
+    ctx->fmt_cfg.out_nb_comp = ctx->syntax.nb_components;
+
+    switch (ctx->cfg->prep.chroma_ds_mode) {
+    case MPP_FRAME_CHORMA_DOWN_SAMPLE_MODE_AVERAGE:
+        ctx->fmt_cfg.chroma_ds_mode = JPEG_VPU720_CHROMA_DOWN_SAMPLE_MODE_Average;
+        break;
+    case MPP_FRAME_CHORMA_DOWN_SAMPLE_MODE_DISCARD:
+        ctx->fmt_cfg.chroma_ds_mode = JPEG_VPU720_CHROMA_DOWN_SAMPLE_MODE_Discard;
+        break;
+    default:
+        ctx->fmt_cfg.chroma_ds_mode = JPEG_VPU720_CHROMA_DOWN_SAMPLE_MODE_Average;
+        break;
+    }
+
+    hal_jpege_dbg_detail("JPEG format: in 0x%x out 0x%x, hw in_fmt %d, out_fmt %d, ds_mode %d\n",
+                         ctx->cfg->prep.format, ctx->cfg->prep.format_out,
+                         ctx->fmt_cfg.input_format, ctx->fmt_cfg.out_format,
+                         ctx->fmt_cfg.chroma_ds_mode);
+
+    if (ctx->cfg->prep.mirroring)
+        ctx->fmt_cfg.mirror = 1;
+
+    if (ctx->cfg->prep.fix_chroma_en) {
+        ctx->fmt_cfg.fix_chroma_en = 1;
+        ctx->fmt_cfg.fix_chroma_u = ctx->cfg->prep.fix_chroma_u & 0xff;
+        ctx->fmt_cfg.fix_chroma_v = ctx->cfg->prep.fix_chroma_v & 0xff;
+    }
+
+    ctx->fmt_cfg.src_range = (ctx->cfg->prep.range == MPP_FRAME_RANGE_UNSPECIFIED) ?
+                             MPP_FRAME_RANGE_JPEG : ctx->cfg->prep.range;
+    ctx->fmt_cfg.dst_range = (ctx->cfg->prep.range_out == MPP_FRAME_RANGE_UNSPECIFIED) ?
+                             MPP_FRAME_RANGE_JPEG : ctx->cfg->prep.range_out;
+    hal_jpege_leave();
+    return MPP_OK;
+}
+
+MPP_RET hal_jpege_vpu720_gen_regs(void *hal, HalEncTask *task)
+{
+    MPP_RET ret = MPP_OK;
+    JpegeVpu720HalCtx *ctx = (JpegeVpu720HalCtx *) hal;
+    JpegeVpu720Reg *regs = ctx->regs;
+    JpegeVpu720BaseReg *reg_base = &regs->reg_base;
+    JpegeBits bits = ctx->bits;
+    const RK_U8 *qtable[2] = {NULL};
+    size_t length = mpp_packet_get_length(task->packet);
+    RK_U8 *buf = mpp_buffer_get_ptr(task->output);
+    size_t size = mpp_buffer_get_size(task->output);
+    JpegeSyntax *syntax = &ctx->syntax;
+    RK_U8 *qtbl_base = (RK_U8 *)mpp_buffer_get_ptr(ctx->qtbl_buffer);
+    RK_S32 bitpos;
+    RK_U32 i, j;
+
+    hal_jpege_enter();
+
+    jpege_vpu720_setup_format(hal, task);
+
+    memset(regs, 0, sizeof(JpegeVpu720Reg));
+
+    mpp_buffer_sync_begin(task->output);
+    jpege_bits_setup(bits, buf, (RK_U32)size);
+    jpege_seek_bits(bits, length << 3);
+    write_jpeg_header(bits, syntax, qtable);
+    mpp_buffer_sync_end(task->output);
+
+    bitpos = jpege_bits_get_bitpos(bits);
+    task->length = (bitpos + 7) >> 3;
+
+    mpp_packet_set_length(task->packet, task->length);
+
+    reg_base->reg001_enc_strt.lkt_num = 0;
+    reg_base->reg001_enc_strt.vepu_cmd = ctx->enc_mode;
+
+    // interupt
+    reg_base->reg004_int_en.fenc_done_en = 1;
+    reg_base->reg004_int_en.lkt_node_done_en = 1;
+    reg_base->reg004_int_en.sclr_done_en = 1;
+    reg_base->reg004_int_en.vslc_done_en = 1;
+    reg_base->reg004_int_en.vbsb_oflw_en = 1;
+    reg_base->reg004_int_en.vbsb_sct_en = 1;
+    reg_base->reg004_int_en.fenc_err_en = 1;
+    reg_base->reg004_int_en.wdg_en = 1;
+    reg_base->reg004_int_en.lkt_oerr_en = 1;
+    reg_base->reg004_int_en.lkt_estp_en = 1;
+    reg_base->reg004_int_en.lkt_fstp_en = 1;
+    reg_base->reg004_int_en.lkt_note_stp_en = 1;
+    reg_base->reg004_int_en.lkt_data_error_en = 1;
+
+    reg_base->reg005_int_msk.fenc_done_msk = 1;
+    reg_base->reg005_int_msk.lkt_node_done_msk = 1;
+    reg_base->reg005_int_msk.sclr_done_msk = 1;
+    reg_base->reg005_int_msk.vslc_done_msk = 1;
+    reg_base->reg005_int_msk.vbsb_oflw_msk = 1;
+    reg_base->reg005_int_msk.vbsb_sct_msk = 1;
+    reg_base->reg005_int_msk.fenc_err_msk = 1;
+    reg_base->reg005_int_msk.wdg_msk = 1;
+    reg_base->reg005_int_msk.lkt_oerr_msk = 1;
+    reg_base->reg005_int_msk.lkt_estp_msk = 1;
+    reg_base->reg005_int_msk.lkt_fstp_msk = 1;
+    reg_base->reg005_int_msk.lkt_note_stp_msk = 1;
+    reg_base->reg005_int_msk.lkt_data_error_msk = 1;
+
+    reg_base->reg008_cru_ctrl.resetn_hw_en = 1;
+    reg_base->reg008_cru_ctrl.sram_ckg_en = 1;
+    reg_base->reg008_cru_ctrl.cke = 1;
+
+    reg_base->reg042_dbus_endn.jbsw_bus_edin = 0xf;
+    reg_base->reg042_dbus_endn.vsl_bus_edin = 0;
+    reg_base->reg042_dbus_endn.ecs_len_edin = 0xf;
+    reg_base->reg042_dbus_endn.sw_qtbl_edin = 0;
+
+    reg_base->reg011_wdg_jpeg = syntax->mcu_cnt * 1000;
+
+    reg_base->reg026_axi_perf_ctrl0.perf_work_e = 1;
+    reg_base->reg026_axi_perf_ctrl0.perf_clr_e = 1;
+
+    for (i = 0; i < 8; i++) {
+        for (j = 0; j < 8; j++) {
+            ctx->qtbl_sw_buf[i * 8 + j] = 0x8000 / qtable[0][j * 8 + i];
+            ctx->qtbl_sw_buf[64 + i * 8 + j] = 0x8000 / qtable[1][j * 8 + i];
+        }
+    }
+
+    memcpy(&ctx->qtbl_sw_buf[64 * 2], &ctx->qtbl_sw_buf[64], sizeof(RK_U16) * 64);
+
+    reg_base->reg029_sw_enc_rsl.pic_wd8_m1 = MPP_ALIGN(syntax->width, 8) / 8 - 1;
+    reg_base->reg029_sw_enc_rsl.pic_hd8_m1 = MPP_ALIGN(syntax->height, 8) / 8 - 1;
+    reg_base->reg030_sw_src_fill.pic_wfill_jpeg = (syntax->width & 0x7) ? (8 - (syntax->width & 7)) : 0;
+    reg_base->reg030_sw_src_fill.pic_hfill_jpeg = (syntax->height & 0x7) ? (8 - (syntax->height & 7)) : 0;
+
+    reg_base->reg032_sw_src_fmt.src_fmt = ctx->fmt_cfg.input_format;
+    reg_base->reg032_sw_src_fmt.out_fmt = ctx->fmt_cfg.out_format;
+    reg_base->reg032_sw_src_fmt.rbuv_swap_jpeg = ctx->fmt_cfg.uv_swap;
+    reg_base->reg032_sw_src_fmt.chroma_ds_mode = ctx->fmt_cfg.chroma_ds_mode;
+    reg_base->reg032_sw_src_fmt.src_mirr_jpeg = ctx->fmt_cfg.mirror;
+    reg_base->reg032_sw_src_fmt.chroma_force_en = ctx->fmt_cfg.fix_chroma_en;
+    reg_base->reg032_sw_src_fmt.u_force_value = ctx->fmt_cfg.fix_chroma_u;
+    reg_base->reg032_sw_src_fmt.v_force_value = ctx->fmt_cfg.fix_chroma_v;
+
+    if (ctx->fmt_cfg.src_range != ctx->fmt_cfg.dst_range) {
+        reg_base->reg032_sw_src_fmt.src_range_trns_en = 1;
+        if (ctx->fmt_cfg.src_range == MPP_FRAME_RANGE_MPEG)
+            reg_base->reg032_sw_src_fmt.src_range_trns_sel = JPEG_VPU720_COLOR_RANGE_LIMIT_TO_FULL;
+        else
+            reg_base->reg032_sw_src_fmt.src_range_trns_sel = JPEG_VPU720_COLOR_RANGE_FULL_TO_LIMIT;
+    }
+
+    reg_base->reg033_sw_pic_ofst.pic_ofst_x = mpp_frame_get_offset_x(task->frame);
+    reg_base->reg033_sw_pic_ofst.pic_ofst_y = mpp_frame_get_offset_y(task->frame);
+
+    reg_base->reg034_sw_src_strd_0.src_strd_0 = ctx->fmt_cfg.y_stride;
+    reg_base->reg035_sw_src_strd_1.src_strd_1 = ctx->fmt_cfg.uv_stride;
+
+    reg_base->reg036_sw_jpeg_enc_cfg.rst_intv = syntax->restart_ri;
+    reg_base->reg036_sw_jpeg_enc_cfg.rst_m = 0;
+    reg_base->reg036_sw_jpeg_enc_cfg.pic_last_ecs = 1;
+
+    reg_base->reg022_adr_src0 = mpp_buffer_get_fd(task->input);
+    reg_base->reg023_adr_src1 = reg_base->reg022_adr_src0;
+    reg_base->reg024_adr_src2 = reg_base->reg022_adr_src0;
+
+    reg_base->reg017_adr_bsbt = mpp_buffer_get_fd(task->output);
+    reg_base->reg018_adr_bsbb = reg_base->reg017_adr_bsbt;
+    reg_base->reg019_adr_bsbr = reg_base->reg017_adr_bsbt;
+    reg_base->reg020_adr_bsbs = reg_base->reg017_adr_bsbt;
+
+    reg_base->reg016_adr_qtbl = mpp_buffer_get_fd(ctx->qtbl_buffer);
+    memcpy(qtbl_base, ctx->qtbl_sw_buf, JPEGE_VPU720_QTABLE_SIZE * sizeof(RK_U16));
+    mpp_buffer_sync_end(ctx->qtbl_buffer);
+
+    MppDevRegOffsetCfg trans_cfg_offset;
+    MppDevRegOffsetCfg trans_cfg_size;
+    MppDevRegOffsetCfg trans_cfg_chroma;
+
+    trans_cfg_offset.reg_idx = 20;
+    trans_cfg_offset.offset = mpp_packet_get_length(task->packet);
+    mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFSET, &trans_cfg_offset);
+    trans_cfg_size.reg_idx = 17;
+    trans_cfg_size.offset = mpp_buffer_get_size(task->output);
+    mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFSET, & trans_cfg_size);
+    trans_cfg_chroma.reg_idx = 23;
+    trans_cfg_chroma.offset = ctx->fmt_cfg.u_offset;
+    mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFSET, &trans_cfg_chroma);
+    trans_cfg_chroma.reg_idx = 24;
+    trans_cfg_chroma.offset = ctx->fmt_cfg.v_offset;
+    mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_OFFSET, &trans_cfg_chroma);
+
+    ctx->frame_num++;
+
+    hal_jpege_leave();
+    return ret;
+}
+
+MPP_RET hal_jpege_vpu720_start(void *hal, HalEncTask *task)
+{
+    MPP_RET ret = MPP_OK;
+    JpegeVpu720HalCtx *ctx = (JpegeVpu720HalCtx *) hal;
+    JpegeVpu720Reg *regs = ctx->regs;
+    MppDevRegWrCfg cfg_base;
+    MppDevRegRdCfg cfg_st;
+
+    hal_jpege_enter();
+
+    if (task->flags.err) {
+        mpp_err_f("task->flags.err 0x%08x, return early\n", task->flags.err);
+        return MPP_NOK;
+    }
+
+    if (hal_jpege_debug & HAL_JPEGE_DBG_DETAIL) {
+        RK_U32 i = 0;
+        RK_U32 *reg = (RK_U32 *)regs;
+
+        for (i = 0; i < 43; i++) {
+            mpp_log_f("set reg[%03d] : %04x : 0x%08x\n", i, i * 4, reg[i]);
+        }
+    }
+
+    cfg_base.reg = &regs->reg_base;
+    cfg_base.size = sizeof(JpegeVpu720BaseReg);
+    cfg_base.offset = 0;
+
+    ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &cfg_base);
+    if (ret) {
+        mpp_err_f("set register write failed %d\n", ret);
+        return ret;
+    }
+
+    cfg_st.reg = &regs->int_state;
+    cfg_st.size = sizeof(RK_U32);
+    cfg_st.offset = JPEGE_VPU720_REG_BASE_INT_STATE;
+    ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &cfg_st);
+    if (ret) {
+        mpp_err_f("set register to read int state failed %d\n", ret);
+    }
+    cfg_st.reg = &regs->reg_st;
+    cfg_st.size = sizeof(JpegeVpu720StatusReg);
+    cfg_st.offset = JPEGE_VPU720_REG_STATUS_OFFSET;
+
+    ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &cfg_st);
+
+    if (ret) {
+        mpp_err_f("set register to read hw status failed %d\n", ret);
+    }
+
+    ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL);
+    if (ret) {
+        mpp_err_f("send cmd failed %d\n", ret);
+    }
+
+    hal_jpege_leave();
+    return MPP_OK;
+}
+
+MPP_RET hal_jpege_vpu720_wait(void *hal, HalEncTask *task)
+{
+    MPP_RET ret = MPP_OK;
+    JpegeVpu720HalCtx *ctx = (JpegeVpu720HalCtx *) hal;
+    JpegeVpu720Reg *regs = (JpegeVpu720Reg *)ctx->regs;
+    JpegeVpu720StatusReg *reg_st = &regs->reg_st;
+    RK_U32 int_state = regs->int_state;
+
+    hal_jpege_enter();
+
+    if (task->flags.err) {
+        mpp_err_f("task->flags.err 0x%08x, return earyl\n", task->flags.err);
+        return ret = MPP_NOK;
+    }
+
+    ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, NULL);
+    if (ret) {
+        mpp_err_f("poll cmd failed %d\n", ret);
+        return ret = MPP_ERR_VPUHW;
+    } else {
+        if (int_state & 0x170)
+            mpp_err_f("JPEG encoder hw error 0x%08x\n", int_state);
+        else
+            hal_jpege_dbg_simple("JPEG encoder int state 0x%08x\n", int_state);
+
+        hal_jpege_dbg_detail("hw length %d, cycle %d\n",
+                             reg_st->st_bsl_l32_jpeg_head_bits,
+                             reg_st->st_perf_working_cnt);
+        task->hw_length += reg_st->st_bsl_l32_jpeg_head_bits;
+    }
+
+    hal_jpege_leave();
+    return MPP_OK;
+}
+
+MPP_RET hal_jpege_vpu720_get_task(void *hal, HalEncTask *task)
+{
+    JpegeVpu720HalCtx *ctx = (JpegeVpu720HalCtx *) hal;
+    JpegeSyntax *syntax = (JpegeSyntax *) task->syntax.data;
+
+    hal_jpege_enter();
+    memcpy(&ctx->syntax, syntax, sizeof(ctx->syntax));
+
+    // TODO config rc
+    hal_jpege_leave();
+    return MPP_OK;
+}
+
+MPP_RET hal_jpege_vpu720_ret_task(void *hal, HalEncTask *task)
+{
+    (void)hal;
+    EncRcTaskInfo * rc_info = &task->rc_task->info;
+
+    hal_jpege_enter();
+
+    task->length += task->hw_length;
+
+    // setup bit length for rate control
+    rc_info->bit_real = task->hw_length * 8;
+    rc_info->quality_real = rc_info->quality_target;
+    mpp_buffer_sync_ro_begin(task->output);
+
+    hal_jpege_leave();
+    return MPP_OK;
+}
+const MppEncHalApi hal_jpege_vpu720 = {
+    .name = "hal_jpege_vpu720",
+    .coding = MPP_VIDEO_CodingMJPEG,
+    .ctx_size = sizeof(JpegeVpu720HalCtx),
+    .flag = 0,
+    .init = hal_jpege_vpu720_init,
+    .deinit = hal_jpege_vpu720_deinit,
+    .prepare = NULL,
+    .get_task = hal_jpege_vpu720_get_task,
+    .gen_regs = hal_jpege_vpu720_gen_regs,
+    .start = hal_jpege_vpu720_start,
+    .wait = hal_jpege_vpu720_wait,
+    .part_start = NULL,
+    .part_wait = NULL,
+    .ret_task = hal_jpege_vpu720_ret_task,
+};
diff --git a/mpp/hal/rkenc/jpege/hal_jpege_vpu720.h b/mpp/hal/rkenc/jpege/hal_jpege_vpu720.h
new file mode 100644
index 000000000..e5328f4ce
--- /dev/null
+++ b/mpp/hal/rkenc/jpege/hal_jpege_vpu720.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef __HAL_JPEGE_VPU720_H__
+#define __HAL_JPEGE_VPU720_H__
+
+#include "mpp_enc_hal.h"
+
+extern const MppEncHalApi hal_jpege_vpu720;
+
+#endif /* __HAL_JPEGE_VPU720_H__ */
diff --git a/mpp/hal/rkenc/jpege/hal_jpege_vpu720_reg.h b/mpp/hal/rkenc/jpege/hal_jpege_vpu720_reg.h
new file mode 100644
index 000000000..8e11ae5d9
--- /dev/null
+++ b/mpp/hal/rkenc/jpege/hal_jpege_vpu720_reg.h
@@ -0,0 +1,555 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef __HAL_JPEGE_VPU720_REG_H__
+#define __HAL_JPEGE_VPU720_REG_H__
+
+#include "rk_type.h"
+
+typedef struct JpegeVpu720BaseReg_t {
+    // 0x0000, IP version
+    RK_U32 reg000_version;
+    // 0x0004, Start Command
+    struct {
+        // Number of new nodes added to link table
+        RK_U32 lkt_num                  : 8;
+        /**
+         * @brief VEPU command
+         * 0 -- N/A
+         * 1 -- One-frame encoding by register configuration
+         * 2 -- Multi-frame encoding start with link table mode
+         * 3 -- Multi-frame encoding update (with link table mode)
+         * 4 -- link table encoding force pause
+         * 5 -- continue link table encoder when link table stop
+         * 6 -- safe_clr
+         * 7 -- force_clr
+         */
+        RK_U32 vepu_cmd                 : 4;
+        RK_U32                          : 20;
+    } reg001_enc_strt;
+
+    /*reserved 0x8 ~ 0xC*/
+    RK_U32 reg002_003[2];
+
+    // 0x0010, Interrupt Enable
+    struct {
+        // One frame encoding finish interrupt enable
+        RK_U32 fenc_done_en             : 1;
+        // Link table one node finish interrupt enable
+        RK_U32 lkt_node_done_en         : 1;
+        // Safe clear finish interrupt enable
+        RK_U32 sclr_done_en             : 1;
+        // One slice of video encoding finish interrupt enable
+        RK_U32 vslc_done_en             : 1;
+        // Video bit stream buffer overflow interrupt enable
+        RK_U32 vbsb_oflw_en             : 1;
+        // Video bit stream buffer write section interrupt enable
+        RK_U32 vbsb_sct_en              : 1;
+        // Frame encoding error interrupt enable
+        RK_U32 fenc_err_en              : 1;
+        // Watch dog (timeout) interrupt enable
+        RK_U32 wdg_en                   : 1;
+        // Link table operation error interrupt enable
+        RK_U32 lkt_oerr_en              : 1;
+        // Link table encoding error stop interrupt enable
+        RK_U32 lkt_estp_en              : 1;
+        // Link cmd force pause interrupt enable
+        RK_U32 lkt_fstp_en              : 1;
+        // Link table note stop interrupt enable
+        RK_U32 lkt_note_stp_en          : 1;
+        RK_U32 lkt_data_error_en        : 1;
+        RK_U32                          : 19;
+    } reg004_int_en;
+
+    // 0x0014, Interrupt Mask
+    struct {
+        RK_U32 fenc_done_msk            : 1;
+        RK_U32 lkt_node_done_msk        : 1;
+        RK_U32 sclr_done_msk            : 1;
+        RK_U32 vslc_done_msk            : 1;
+        RK_U32 vbsb_oflw_msk            : 1;
+        RK_U32 vbsb_sct_msk             : 1;
+        RK_U32 fenc_err_msk             : 1;
+        RK_U32 wdg_msk                  : 1;
+        RK_U32 lkt_oerr_msk             : 1;
+        RK_U32 lkt_estp_msk             : 1;
+        RK_U32 lkt_fstp_msk             : 1;
+        RK_U32 lkt_note_stp_msk         : 1;
+        RK_U32 lkt_data_error_msk       : 1;
+        RK_U32                          : 19;
+    } reg005_int_msk;
+
+    // 0x0018, Interrupt Clear
+    struct {
+        RK_U32 fenc_done_clr            : 1;
+        RK_U32 lkt_node_done_clr        : 1;
+        RK_U32 sclr_done_clr            : 1;
+        RK_U32 vslc_done_clr            : 1;
+        RK_U32 vbsb_oflw_clr            : 1;
+        RK_U32 vbsb_sct_clr             : 1;
+        RK_U32 fenc_err_clr             : 1;
+        RK_U32 wdg_clr                  : 1;
+        RK_U32 lkt_oerr_clr             : 1;
+        RK_U32 lkt_estp_clr             : 1;
+        RK_U32 lkt_fstp_clr             : 1;
+        RK_U32 lkt_note_stp_clr         : 1;
+        RK_U32 lkt_data_error_clr       : 1;
+        RK_U32                          : 19;
+    } reg006_int_clr;
+
+    // 0x001c, Interrupt State;
+    struct {
+        RK_U32 fenc_done_state          : 1;
+        RK_U32 lkt_node_done_state      : 1;
+        RK_U32 sclr_done_state          : 1;
+        RK_U32 vslc_done_state          : 1;
+        RK_U32 vbsb_oflw_state          : 1;
+        RK_U32 vbsb_sct_state           : 1;
+        RK_U32 fenc_err_state           : 1;
+        RK_U32 wdg_state                : 1;
+        RK_U32 lkt_oerr_state           : 1;
+        RK_U32 lkt_estp_state           : 1;
+        RK_U32 lkt_fstp_state           : 1;
+        RK_U32 lkt_note_stp_state       : 1;
+        RK_U32 lkt_data_error_state     : 1;
+        RK_U32                          : 19;
+    } reg007_int_state;
+
+    // 0x0020, Clock and RST CTRL
+    struct {
+        // Encoder auto reset core clock domain when frame finished
+        RK_U32 resetn_hw_en             : 1;
+        // Encoder SRAM auto clock gating enable
+        RK_U32 sram_ckg_en              : 1;
+        // Auto clock gating enable
+        RK_U32 cke                      : 1;
+        RK_U32                          : 29;
+    } reg008_cru_ctrl;
+
+    // 0x0024, Fast link table cfg buffer addr, 128 byte aligned
+    RK_U32 reg009_lkt_base_addr;
+
+    // 0x0028, Link table node operation configuration
+    struct {
+        // Only the ejpeg with the same core ID can use this node
+        RK_U32 core_id                  : 4;
+        // The enable of lkt error stop next frame
+        RK_U32 lkt_err_stop_en          : 1;
+        // The enable of lkt frame stop when the frame end
+        RK_U32 lkt_node_stop_en         : 1;
+        RK_U32                          : 10;
+        /**
+         * @brief  Data swap for link table read channel.
+         * bit[3] -- swap 64 bits in 128 bits
+         * bit[2] -- swap 32 bits in 64 bits;
+         * bit[1] -- swap 16 bits in 32 bits;
+         * bit[0] -- swap 8 bits in 16 bits;
+         */
+        RK_U32 lktr_bus_edin            : 4;
+        /**
+         * @brief
+         * Data swap for link table write channel.
+         * bit[3] -- swap 64 bits in 128 bits
+         * bit[2] -- swap 32 bits in 64 bits;
+         * bit[1] -- swap 16 bits in 32 bits;
+         * bit[0] -- swap 8 bits in 16 bits;
+         */
+        RK_U32 lktw_bus_edin            : 4;
+        RK_U32                          : 8;
+    } reg010_node_ocfg;
+
+    // 0x002c, watch dog configure register
+    RK_U32 reg011_wdg_jpeg;
+
+    // reserved, 0x0030
+    RK_U32 reg012;
+
+    // 0x0034, low delay esc operation configuration. Bit[0-30] : read ecs num.
+    RK_U32 reg013_low_delay_ecs_ocfg;
+    // 0x0038, low delay packet operation configuration. Bit[0-30] : read packet num.
+    RK_U32 reg014_low_delay_packet_ocfg;
+
+    // reserved, 0x003c
+    RK_U32 reg015;
+
+    // 0x0040, Address of JPEG Q table buffer, 128 byte aligned
+    RK_U32 reg016_adr_qtbl;
+    // 0x0044, Top address of JPEG Bit stream buffer, 16 byte aligned
+    RK_U32 reg017_adr_bsbt;
+    // 0x0048, Bottom address of JPEG bit stream buffer, 16 byte aligned
+    RK_U32 reg018_adr_bsbb;
+    // 0x004c, Read Address of JPEG bit stream buffer, 1 byte aligned
+    RK_U32 reg019_adr_bsbr;
+    // 0x0050, Start address of JPEG bit stream buffer, 1 byte aligned
+    RK_U32 reg020_adr_bsbs;
+    // 0x0054, Base address of ECS length buffer, 8 byte align
+    RK_U32 reg021_adr_ecs_len;
+    // 0x0058, Base address of the 1st storage area for video source buffer
+    RK_U32 reg022_adr_src0;
+    // 0x005c, Base address of the 2nd storage area for video source buffer
+    RK_U32 reg023_adr_src1;
+    // 0x0060, Base address of the 3rd storage area for video source buffer
+    RK_U32 reg024_adr_src2;
+
+    // reserved, 0x0064
+    RK_U32 reg025;
+
+    // 0x0068, rk jpeg encoder axi performance ctrl0 description
+    struct {
+        RK_U32 perf_work_e              : 1;
+        RK_U32 perf_clr_e               : 1;
+        RK_U32 perf_frm_type            : 1;
+        RK_U32 cnt_type                 : 1;
+        RK_U32 rd_latency_id            : 4;
+        RK_U32 rd_latency_thr           : 12;
+        RK_U32                          : 12;
+    } reg026_axi_perf_ctrl0;
+
+    // 0x006c, rk jpeg encoder axi performance ctrl1 description
+    struct {
+        RK_U32 addr_align_type          : 2;
+        RK_U32 ar_cnt_id_type           : 1;
+        RK_U32 aw_cnt_id_type           : 1;
+        RK_U32 ar_count_id              : 4;
+        RK_U32 aw_count_id              : 4;
+        RK_U32 rd_total_bytes_mode      : 1;
+        RK_U32                          : 19;
+    } reg027_axi_perf_ctrl1;
+
+    // 0x0070, reserved
+    RK_U32 reg028;
+
+    // 0x0074, picture size
+    struct {
+        // Ceil(encoding picture height / 8) -1
+        RK_U32 pic_wd8_m1               : 13;
+        RK_U32                          : 3;
+        // Ceil(encoding picture height / 8) -1
+        RK_U32 pic_hd8_m1               : 13;
+        RK_U32                          : 3;
+    } reg029_sw_enc_rsl;
+
+    // 0x0078, JPEG source filling pixels for align
+    struct {
+        RK_U32 pic_wfill_jpeg           : 6;
+        RK_U32                          : 10;
+        RK_U32 pic_hfill_jpeg           : 6;
+        RK_U32                          : 10;
+    } reg030_sw_src_fill;
+
+    /* reserved 0x7c */
+    RK_U32 reg031;
+
+    // 0x0080, JPEG source format
+    struct {
+        RK_U32                          : 1;
+        RK_U32 rbuv_swap_jpeg           : 1;
+        /**
+         * @brief srouce color format
+         * 4'h0: tile400
+         * 4'h1: tile420
+         * 4'h2: tile422
+         * 4'h3: tile444
+         * 4'h4: YUV422SP
+         * 4'h5: YUV422P
+         * 4'h6: YUV420SP
+         * 4'h7: YUV420P
+         * 4'h8: YUYV422
+         * 4'h9: UYVY422
+         * 4'ha: YUV400
+         * 4'hc: YUV444SP
+         * 4'hd: YUV444P
+         * Others: Reserved
+         */
+        RK_U32 src_fmt                  : 4;
+        /**
+         * @brief color format of output from preprocess
+         * 2'h0: YUV400;
+         * 2'h1: YUV420;
+         * 2'h2: YUV422;
+         * 2'h3: YUV444;
+         *
+        */
+        RK_U32 out_fmt                  : 2;
+        RK_U32                          : 1;
+        RK_U32 src_range_trns_en        : 1;
+        RK_U32 src_range_trns_sel       : 1;
+        /**
+         * @brief Chroma downsample mode
+         * 0 -- Average
+         * 1 -- Drop
+         */
+        RK_U32 chroma_ds_mode           : 1;
+        // Chroma value will be force to some value
+        RK_U32 chroma_force_en          : 1;
+        RK_U32                          : 2;
+        // 1 00 src mirror image
+        RK_U32 src_mirr_jpeg            : 1;
+        RK_U32 u_force_value            : 8;
+        RK_U32 v_force_value            : 8;
+    } reg032_sw_src_fmt;
+
+    // 0x0084, encoding picture offset
+    struct {
+        RK_U32 pic_ofst_x               : 16;
+        RK_U32 pic_ofst_y               : 16;
+    } reg033_sw_pic_ofst;
+
+    // 0x0088, JPEG source stride0
+    struct {
+        RK_U32 src_strd_0               : 20;
+        RK_U32                          : 12;
+    } reg034_sw_src_strd_0;
+
+    // 0x008c, JPEG source stride1
+    struct {
+        RK_U32 src_strd_1               : 19;
+        RK_U32                          : 13;
+    } reg035_sw_src_strd_1;
+
+    // 0x0090, JPEG common config
+    struct {
+        /* the number of MCU in the restart interval */
+        RK_U32 rst_intv                 : 16;
+        RK_U32                          : 9;
+        /**
+         * @brief JPEG encoder output mode
+         * 1'b0: frame by frame, without interrupt at any ECS;
+         * 1'b1: low latency mode, with interrupt per ECS, flush all the
+         *       bit stream after each ECS finished.
+         */
+        RK_U32 out_mode                 : 1;
+        /* the number of the fisrt RSTm */
+        RK_U32 rst_m                    : 3;
+        /**
+         * @brief Indicate if the current ECS is the last ECS of the whole picture.
+         * If it is the last ecs, add EOI.
+         */
+        RK_U32 pic_last_ecs             : 1;
+        /**
+         * @brief reload Q table or not
+         * 0 -- load Q table for current task
+         * 1 -- no need to load Q table
+         */
+        RK_U32 jpeg_qtble_noload        : 1;
+        RK_U32                          : 1;
+    } reg036_sw_jpeg_enc_cfg;
+
+    // 0x0094, Low dealy packet size config
+    RK_U32 reg037_bsp_size_jpeg;
+
+    // 0x0098, Bit stream output padding config
+    struct {
+        RK_U32 uvc_partition0_len       : 12;
+        RK_U32 uvc_partition_len        : 12;
+        RK_U32 uvc_skip_len             : 6;
+        RK_U32                          : 2;
+    } reg038_sw_uvc_cfg;
+
+    // 0x009c, Y Quantify rounding
+    struct {
+        /* bias for Y at quantization */
+        RK_U32 bias_y                   : 15;
+        RK_U32                          : 17;
+    } reg039_sw_jpeg_y_cfg;
+
+    // 0x00a0, U Quantify rounding
+    struct {
+
+        /* bias for U at quantization */
+        RK_U32 bias_u                   : 15;
+        RK_U32                          : 17;
+    } reg040_sw_jpeg_u_cfg;
+
+    // 0x00a4, V Quantify rounding
+    struct {
+        /* bias for V at quantization */
+        RK_U32 bias_v                   : 15;
+        RK_U32                          : 17;
+    } reg041_sw_jpeg_v_cfg;
+
+    // 0x00a8, Data bus endian
+    struct {
+        /**
+         * @brief Data swap for jpeg bit stream write channel
+         * [3]: Swap 64 bits in 128 bits
+         * [2]: Swap 32 bits in 64 bits
+         * [1]: Swap 16 bits in 32 bits
+         * [0]: Swap 8 bits in 16 bits
+         */
+        RK_U32 jbsw_bus_edin            : 4;
+        // Data swap for video source loading channel.
+        RK_U32 vsl_bus_edin             : 4;
+        // Data swap for lkt state write channel
+        RK_U32 ecs_len_edin             : 4;
+        // Data swap for qtbl read channel
+        RK_U32 sw_qtbl_edin             : 4;
+    } reg042_dbus_endn;
+
+} JpegeVpu720BaseReg;
+
+typedef struct JpegeVpu720StatusReg_t {
+    // 0x00c0, Low 32 bits of JPEG header bits length.
+    RK_U32 st_bsl_l32_jpeg_head_bits;
+    // 0x00c4, High 32 bits of JPEG header bits length
+    RK_U32 st_bsl_h32_jpeg_head_bits;
+
+    // 0x00c8, Y and U source range
+    struct {
+        RK_U32 y_max_value              : 8;
+        RK_U32 y_min_value              : 8;
+        RK_U32 u_max_value              : 8;
+        RK_U32 u_min_vlaue              : 8;
+    } st_vsp_value0;
+
+    // 0x00cc, V source range and total_ecs_num_minus
+    struct {
+        RK_U32 v_max_value              : 8;
+        RK_U32 v_min_vlaue              : 8;
+        RK_U32 total_ecs_num_minus1     : 8;
+    } st_vsp_value1;
+
+    // 0x00d0, bit[0-15]
+    RK_U32 st_perf_rd_max_latency_num0;
+    // 0x00d4
+    RK_U32 st_perf_rd_latency_samp_num;
+    // 0x00d8
+    RK_U32 st_perf_rd_latency_acc_sum;
+    // 0x00dc
+    RK_U32 st_perf_rd_axi_total_byte;
+    // 0x00e0
+    RK_U32 st_perf_wr_axi_total_byte;
+    // 0x00e4
+    RK_U32 st_perf_working_cnt;
+
+    RK_U32 sw_reserved_00e8_00ec[2];
+
+    // 0x00f0
+    struct {
+        RK_U32 vsp_work_flag            : 1;
+        RK_U32 jpeg_core_work_flag      : 1;
+        RK_U32 dma_wr_work_flag         : 1;
+        RK_U32 dma_work_flag            : 1;
+    } st_wdg;
+
+    // 0x00f4
+    RK_U32 st_ppl_pos;
+    // 0x00f8
+    RK_U32 st_core_pos;
+
+    // 0x00fc, Bus status
+    struct {
+        RK_U32 ejpeg_arready            : 1;
+        RK_U32 ejpeg_cfg_arvalid        : 1;
+        RK_U32 ejpeg_cfg_arvalid_type   : 1;
+        RK_U32 ejpeg_cfg_arready        : 1;
+        RK_U32 ejpeg_vsp_arvalid        : 1;
+        RK_U32 ejpeg_vsp_arready        : 1;
+        RK_U32 rkejpeg_arvalid          : 1;
+        RK_U32 ejpeg_cfg_ar_cnt         : 2;
+        RK_U32 rkejpeg_arready          : 1;
+        RK_U32 rkejpeg_ravlid           : 1;
+        RK_U32 rkejpeg_rid              : 4;
+        RK_U32 rkejpeg_rresp            : 2;
+        RK_U32 rkejpeg_rready           : 1;
+        RK_U32 axi_wr_state_cs          : 1;
+        RK_U32 ejpeg_strmd_awvalid      : 1;
+        RK_U32 ejpeg_strmd_awtype       : 1;
+        RK_U32 ejpeg_strmd_awready      : 1;
+        RK_U32 ejpeg_strmd_wvalid       : 1;
+        RK_U32 ejpeg_strmd_wready       : 1;
+        RK_U32 ejpeg_cfg_awvalid        : 1;
+        RK_U32 ejpeg_cfg_awready        : 1;
+        RK_U32 rkejpeg_awvalid          : 1;
+        RK_U32 rkejpeg_awid             : 1;
+        RK_U32 rkejpeg_wvalid           : 1;
+        RK_U32 rkejpeg_wready           : 1;
+        RK_U32 ejpeg_freeze_flag        : 1;
+        RK_U32                          : 1;
+    } st_bus;
+
+    // 0x0100, vsp_dbg_status
+    RK_U32 dbg_ppl;
+    // 0x0104, jpeg core dbg status
+    RK_U32 dbg_jpeg_core;
+    // reserved, 0x0108
+    RK_U32 sw_reserved_0108;
+    // 0x010c, The bit stream write address status
+    RK_U32 st_adr_jbsbw;
+    // 0x0110, ECS length buffer write address status
+    RK_U32 st_adr_ecs_len;
+    // 0x0114, the 1st storage aread for video source buffer read address status
+    RK_U32 st_adr_src0_jpeg;
+    // 0x0118, the 2nd storage aread for video source buffer read address status
+    RK_U32 st_adr_src1_jpeg;
+    // 0x011c, the 3rd storage aread for video source buffer read address status
+    RK_U32 st_adr_src2_jpeg;
+
+    // 0x0120, low delay packet num status
+    struct {
+        RK_U32 bs_packet_num            : 16;
+        RK_U32 bs_packet_lst            : 1;
+    } st_low_delay_packet_num;
+
+    // 0x0124, low delay ecs_len num status
+    struct {
+        RK_U32 ecs_len_num              : 16;
+        RK_U32 ecs_len_lst              : 1;
+    } st_ecs_len_num;
+
+    // 0x0128, JPEG common status
+    struct {
+        /**
+         * @brief
+         * 0: idle
+         * 1: cru open
+         * 2: lkt cfg load
+         * 3: qtbl_cfg_load
+         * 4:enc
+         * 5:frame end
+         * 6:cru_close
+         * 7:lkt_error_stop
+         * 8:lkt_force_stop
+         * 9:lkt_node_stop
+         */
+        RK_U32 jpeg_enc_state           : 4;
+        RK_U32 lkt_mode_en              : 1;
+    } st_enc;
+
+    // 0x012c, Link table num
+    struct {
+        RK_U32 lkt_cfg_num              : 8;
+        RK_U32 lkt_done_num             : 8;
+        RK_U32 lkt_int_num              : 8;
+        RK_U32 lkt_cfg_load_num         : 8;
+    } st_lkt_num;
+
+    // 0x0130, link table cfg info
+    struct {
+        RK_U32 lkt_core_id              : 4;
+        RK_U32                          : 4;
+        RK_U32 lkt_stop_flag            : 1;
+        RK_U32 lkt_node_int             : 1;
+        RK_U32 lkt_task_id              : 12;
+        RK_U32                          : 10;
+    } st_lkt_info;
+
+    //0x0134, next read addr for lkt_cfg
+    RK_U32 st_lkt_cfg_next_addr;
+    //0x0138, lkt state buffer write addr
+    RK_U32 st_lkt_waddr;
+} JpegeVpu720StatusReg;
+
+
+#define JPEGE_VPU720_REG_BASE_INT_STATE (0x1c)
+#define JPEGE_VPU720_REG_STATUS_OFFSET (0xc0)
+
+typedef struct JpegeVpu720RegSet_t {
+    JpegeVpu720BaseReg reg_base;
+    JpegeVpu720StatusReg reg_st;
+    RK_U32 int_state;
+} JpegeVpu720Reg;
+
+#endif /* __HAL_JPEGE_VPU720_REG_H__ */
\ No newline at end of file
diff --git a/mpp/hal/vpu/av1d/CMakeLists.txt b/mpp/hal/vpu/av1d/CMakeLists.txt
index 616ce7cfc..9b286bc68 100644
--- a/mpp/hal/vpu/av1d/CMakeLists.txt
+++ b/mpp/hal/vpu/av1d/CMakeLists.txt
@@ -1,22 +1,23 @@
 # vim: syntax=cmake
-# hal jpeg reg
+# hal av1 reg
+
+include_directories(../../common/av1)
+include_directories(../../rkdec/inc)
 
 set(HAL_AV1D_HDR
-    hal_av1d_common.h
+    ../../common/av1/hal_av1d_common.h
     )
 
 set(HAL_AV1D_SRC
-    hal_av1d_api.c
     hal_av1d_vdpu.c
-    film_grain_noise_table.c
     )
 
-add_library(${HAL_AV1D} STATIC
+add_library(hal_av1d_vpu STATIC
             ${HAL_AV1D_SRC}
             ${HAL_AV1D_HDR}
             )
 
-set_target_properties(${HAL_AV1D} PROPERTIES FOLDER "mpp/hal")
-target_link_libraries(${HAL_AV1D} mpp_base)
+set_target_properties(hal_av1d_vpu PROPERTIES FOLDER "mpp/hal")
+target_link_libraries(hal_av1d_vpu mpp_base hal_av1d_com)
 
 #add_subdirectory(test)
diff --git a/mpp/hal/vpu/av1d/hal_av1d_vdpu.c b/mpp/hal/vpu/av1d/hal_av1d_vdpu.c
index b3edaf529..5b6e1f9ad 100644
--- a/mpp/hal/vpu/av1d/hal_av1d_vdpu.c
+++ b/mpp/hal/vpu/av1d/hal_av1d_vdpu.c
@@ -35,7 +35,6 @@
 #include "av1d_syntax.h"
 #include "film_grain_noise_table.h"
 #include "av1d_common.h"
-#include "rk_hdr_meta_com.h"
 
 #define VDPU_FAST_REG_SET_CNT    3
 #define AV1_MAX_TILES 128
@@ -676,7 +675,7 @@ static void set_ref_sign_bias(VdpuAv1dRegSet *regs, RK_S32 i, RK_S32 val)
 #define MAX_FRAME_DISTANCE 31
 #define MAX_ACTIVE_REFS AV1_ACTIVE_REFS_EX
 
-RK_S32 GetRelativeDist(DXVA_PicParams_AV1 *dxva, RK_S32 a, RK_S32 b)
+static RK_S32 GetRelativeDist(DXVA_PicParams_AV1 *dxva, RK_S32 a, RK_S32 b)
 {
     if (!dxva->order_hint_bits) return 0;
     const RK_S32 bits = dxva->order_hint_bits - 1;
@@ -733,7 +732,7 @@ RK_S32 GetRelativeDist(DXVA_PicParams_AV1 *dxva, RK_S32 a, RK_S32 b)
 }
 
 
-void set_frame_sign_bias(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)
+static void set_frame_sign_bias(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)
 {
     RK_U32 i = 0;
     VdpuAv1dRegCtx *reg_ctx = (VdpuAv1dRegCtx *)p_hal->reg_ctx;
@@ -757,7 +756,7 @@ void set_frame_sign_bias(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)
     }
 }
 
-void vdpu_av1d_set_prob(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)
+static void vdpu_av1d_set_prob(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)
 {
     VdpuAv1dRegCtx *reg_ctx = (VdpuAv1dRegCtx *)p_hal->reg_ctx;
     const int mv_cdf_offset = offsetof(AV1CDFs, mv_cdf);
@@ -776,7 +775,7 @@ void vdpu_av1d_set_prob(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)
     regs->addr_cfg.swreg173.sw_prob_tab_base_lsb        = mpp_buffer_get_fd(reg_ctx->prob_tbl_base);
 }
 
-void vdpu_av1d_set_reference_frames(Av1dHalCtx *p_hal, VdpuAv1dRegCtx *ctx, DXVA_PicParams_AV1 *dxva)
+static void vdpu_av1d_set_reference_frames(Av1dHalCtx *p_hal, VdpuAv1dRegCtx *ctx, DXVA_PicParams_AV1 *dxva)
 {
     RK_U32 tmp1, tmp2, i;
     RK_U32 cur_height, cur_width;
@@ -1097,7 +1096,7 @@ void vdpu_av1d_set_reference_frames(Av1dHalCtx *p_hal, VdpuAv1dRegCtx *ctx, DXVA
 }
 #undef MAX_FRAME_DISTANCE
 
-void vdpu_av1d_superres_params(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)
+static void vdpu_av1d_superres_params(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)
 {
     // Compute and store scaling paramers needed for superres
 #define SUPERRES_SCALE_BITS 3
@@ -1209,7 +1208,7 @@ void vdpu_av1d_superres_params(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)
 }
 
 
-void vdpu_av1d_set_picture_dimensions(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)
+static void vdpu_av1d_set_picture_dimensions(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)
 {
     /* Write dimensions for the current picture
        (This is needed when scaling is used) */
@@ -1227,7 +1226,7 @@ void vdpu_av1d_set_picture_dimensions(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxv
     vdpu_av1d_superres_params(p_hal, dxva);
 }
 
-void vdpu_av1d_set_segmentation(VdpuAv1dRegCtx *ctx, DXVA_PicParams_AV1 *dxva)
+static void vdpu_av1d_set_segmentation(VdpuAv1dRegCtx *ctx, DXVA_PicParams_AV1 *dxva)
 {
     RK_U32 segval[MAX_MB_SEGMENTS][SEG_AV1_LVL_MAX];
     VdpuAv1dRegSet *regs = ctx->regs;
@@ -1391,7 +1390,7 @@ void vdpu_av1d_set_segmentation(VdpuAv1dRegCtx *ctx, DXVA_PicParams_AV1 *dxva)
     regs->swreg27.sw_global_mv_seg7 = segval[7][SEG_AV1_LVL_GLOBALMV];
 }
 
-void vdpu_av1d_set_loopfilter(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)
+static void vdpu_av1d_set_loopfilter(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)
 {
     VdpuAv1dRegCtx *ctx = p_hal->reg_ctx;
     VdpuAv1dRegSet *regs = ctx->regs;
@@ -1427,7 +1426,7 @@ void vdpu_av1d_set_loopfilter(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)
     mpp_dev_set_reg_offset(p_hal->dev, 183, ctx->filt_info[DB_CTRL_COL].offset);
 }
 
-void vdpu_av1d_set_global_model(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)
+static void vdpu_av1d_set_global_model(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)
 {
     VdpuAv1dRegCtx *ctx = p_hal->reg_ctx;
     VdpuAv1dRegSet *regs = ctx->regs;
@@ -1469,7 +1468,7 @@ void vdpu_av1d_set_global_model(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)
     regs->addr_cfg.swreg83.sw_global_model_base_lsb = mpp_buffer_get_fd(ctx->global_model);
 }
 
-void vdpu_av1d_set_tile_info_regs(VdpuAv1dRegCtx *ctx, DXVA_PicParams_AV1 *dxva)
+static void vdpu_av1d_set_tile_info_regs(VdpuAv1dRegCtx *ctx, DXVA_PicParams_AV1 *dxva)
 {
     int transpose = ctx->tile_transpose;
     VdpuAv1dRegSet *regs = ctx->regs;
@@ -1518,7 +1517,7 @@ static int check_tile_width(DXVA_PicParams_AV1 *dxva, RK_S32 width, RK_S32 leftm
     return valid;
 }
 
-void vdpu_av1d_set_tile_info_mem(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)
+static void vdpu_av1d_set_tile_info_mem(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)
 {
     VdpuAv1dRegCtx *ctx = (VdpuAv1dRegCtx *)p_hal->reg_ctx;
 
@@ -1530,6 +1529,25 @@ void vdpu_av1d_set_tile_info_mem(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)
     RK_S32 size1 = transpose ? dxva->tiles.rows  :  dxva->tiles.cols;
     RK_S32 tile0, tile1;
     RK_U32 not_valid_tile_dimension = 0;
+    RK_U32 tiles[2][64];
+
+    /* convert to per tile position */
+    {
+        RK_U8 val = 0, i;
+
+        for (i = 0; i < dxva->tiles.cols; i++) {
+            tiles[0][i] = val;
+            val += dxva->tiles.widths[i];
+        }
+        tiles[0][i] = val;
+
+        val = 0;
+        for (i = 0; i < dxva->tiles.rows; i++) {
+            tiles[1][i] = val;
+            val += dxva->tiles.heights[i];
+        }
+        tiles[1][i] = val;
+    }
 
     // Write tile dimensions
     for (tile0 = 0; tile0 < size0; tile0++) {
@@ -1539,10 +1557,10 @@ void vdpu_av1d_set_tile_info_mem(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)
             RK_S32 tile_id = transpose ? tile1 * size0 + tile0 : tile0 * size1 + tile1;
             RK_U32 start, end;
 
-            RK_U32 y0 = dxva->tiles.heights[tile_y];
-            RK_U32 y1 = dxva->tiles.heights[tile_y + 1];
-            RK_U32 x0 = dxva->tiles.widths[tile_x];
-            RK_U32 x1 = dxva->tiles.widths[tile_x + 1];
+            RK_U32 y0 = tiles[1][tile_y];
+            RK_U32 y1 = tiles[1][tile_y + 1];
+            RK_U32 x0 = tiles[0][tile_x];
+            RK_U32 x1 = tiles[0][tile_x + 1];
 
             RK_U8 leftmost = (tile_x == dxva->tiles.cols - 1);
             if (!not_valid_tile_dimension)
@@ -1589,7 +1607,7 @@ void vdpu_av1d_set_tile_info_mem(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)
     mpp_buffer_sync_end(ctx->tile_info);
 }
 
-void vdpu_av1d_set_cdef(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)
+static void vdpu_av1d_set_cdef(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)
 {
     RK_U32 luma_pri_strength = 0;
     RK_U16 luma_sec_strength = 0;
@@ -1621,7 +1639,7 @@ void vdpu_av1d_set_cdef(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)
     mpp_dev_set_reg_offset(p_hal->dev, 85, ctx->filt_info[CDEF_COL].offset);
 }
 
-void vdpu_av1d_set_lr(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)
+static void vdpu_av1d_set_lr(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)
 {
     VdpuAv1dRegCtx *ctx = p_hal->reg_ctx;
     VdpuAv1dRegSet *regs = ctx->regs;
@@ -1639,8 +1657,8 @@ void vdpu_av1d_set_lr(Av1dHalCtx *p_hal, DXVA_PicParams_AV1 *dxva)
     mpp_dev_set_reg_offset(p_hal->dev, 91, ctx->filt_info[LR_COL].offset);
 }
 
-void init_scaling_function(RK_U8 scaling_points[][2], RK_U8 num_points,
-                           RK_U8 scaling_lut[])
+static void init_scaling_function(RK_U8 scaling_points[][2], RK_U8 num_points,
+                                  RK_U8 scaling_lut[])
 {
     RK_S32 i, point;
 
@@ -1668,7 +1686,7 @@ void init_scaling_function(RK_U8 scaling_points[][2], RK_U8 num_points,
         scaling_lut[i] = scaling_points[num_points - 1][1];
 }
 
-void vdpu_av1d_set_fgs(VdpuAv1dRegCtx *ctx, DXVA_PicParams_AV1 *dxva)
+static void vdpu_av1d_set_fgs(VdpuAv1dRegCtx *ctx, DXVA_PicParams_AV1 *dxva)
 {
     VdpuAv1dRegSet *regs = ctx->regs;
     RK_S32 ar_coeffs_y[24];
@@ -1897,8 +1915,6 @@ MPP_RET vdpu_av1d_gen_regs(void *hal, HalTaskInfo *task)
     tile_out_buf = hal_bufs_get_buf(ctx->tile_out_bufs, task->dec.output);
     hor_stride = mpp_frame_get_hor_stride(mframe);
     ver_stride = mpp_frame_get_ver_stride(mframe);
-    if (MPP_FRAME_FMT_IS_HDR(mpp_frame_get_fmt(mframe)) && p_hal->cfg->base.enable_hdr_meta)
-        fill_hdr_meta_to_frame(mframe, HDR_AV1);
 
     ctx->ver_stride = ver_stride;
 
@@ -2049,8 +2065,8 @@ MPP_RET vdpu_av1d_gen_regs(void *hal, HalTaskInfo *task)
 
     regs->swreg11.sw_mcomp_filt_type    = dxva->interp_filter;
     regs->swreg11.sw_high_prec_mv_e     = dxva->coding.high_precision_mv;
-    regs->swreg11.sw_comp_pred_mode     =  dxva->coding.reference_mode ? 2 : 0;
-    regs->swreg11.sw_transform_mode     = dxva->coding.tx_mode;
+    regs->swreg11.sw_comp_pred_mode     = dxva->coding.reference_mode ? 2 : 0;
+    regs->swreg11.sw_transform_mode     = dxva->coding.tx_mode ? (dxva->coding.tx_mode + 2) : 0;
     regs->swreg12.sw_max_cb_size        = dxva->coding.use_128x128_superblock ? 7 : 6;;
     regs->swreg12.sw_min_cb_size        = 3;
 
@@ -2199,7 +2215,7 @@ MPP_RET vdpu_av1d_gen_regs(void *hal, HalTaskInfo *task)
         RK_U32 y_stride = out_w * out_h;
         RK_U32 out_fmt = 0;
 
-        if (mpp_frame_get_fmt(mframe) == MPP_FMT_YUV420SP)
+        if ((mpp_frame_get_fmt(mframe) & MPP_FRAME_FMT_MASK) == MPP_FMT_YUV420SP)
             out_fmt = 3;
 
         /*
diff --git a/mpp/hal/vpu/h264e/CMakeLists.txt b/mpp/hal/vpu/h264e/CMakeLists.txt
index f7649903d..cee8dadde 100644
--- a/mpp/hal/vpu/h264e/CMakeLists.txt
+++ b/mpp/hal/vpu/h264e/CMakeLists.txt
@@ -21,5 +21,5 @@ add_library(hal_h264e_vpu STATIC
             ${HAL_H264E_SRC}
            )
 
-target_link_libraries(hal_h264e_vpu hal_h264e hal_vepu_common ${CODEC_H264E})
+target_link_libraries(hal_h264e_vpu hal_h264e_com hal_vepu_common ${CODEC_H264E})
 set_target_properties(hal_h264e_vpu PROPERTIES FOLDER "mpp/hal")
diff --git a/mpp/hal/vpu/h264e/hal_h264e_vepu1_v2.c b/mpp/hal/vpu/h264e/hal_h264e_vepu1_v2.c
index e39ffa5aa..8ad02d7d4 100644
--- a/mpp/hal/vpu/h264e/hal_h264e_vepu1_v2.c
+++ b/mpp/hal/vpu/h264e/hal_h264e_vepu1_v2.c
@@ -24,6 +24,7 @@
 #include "mpp_common.h"
 #include "mpp_device.h"
 #include "mpp_rc.h"
+#include "mpp_packet_impl.h"
 
 #include "mpp_enc_hal.h"
 #include "h264e_debug.h"
@@ -653,8 +654,10 @@ static MPP_RET hal_h264e_vepu1_wait_v2(void *hal, HalEncTask *task)
 {
     HalH264eVepu1Ctx *ctx = (HalH264eVepu1Ctx *)hal;
     HalH264eVepuMbRc *hw_mbrc = &ctx->hw_mbrc;
+    H264NaluType type = task->rc_task->frm.is_idr ?  H264_NALU_TYPE_IDR : H264_NALU_TYPE_SLICE;
+    MppPacket pkt = task->packet;
+    RK_S32 offset = mpp_packet_get_length(pkt);
     MPP_RET ret = MPP_NOK;
-    (void) task;
 
     hal_h264e_dbg_func("enter %p\n", hal);
 
@@ -670,8 +673,11 @@ static MPP_RET hal_h264e_vepu1_wait_v2(void *hal, HalEncTask *task)
     h264e_vepu1_get_mbrc(hw_mbrc, &ctx->regs_get);
     h264e_vepu_mbrc_update(ctx->rc_ctx, hw_mbrc);
 
+    mpp_packet_add_segment_info(pkt, type, offset, hw_mbrc->out_strm_size);
+
     {
         HalH264eVepuStreamAmend *amend = &ctx->amend;
+
         if (amend->enable) {
             amend->old_length = hw_mbrc->out_strm_size;
             h264e_vepu_stream_amend_proc(amend, &ctx->cfg->codec.h264.hw_cfg);
diff --git a/mpp/hal/vpu/h264e/hal_h264e_vepu2_v2.c b/mpp/hal/vpu/h264e/hal_h264e_vepu2_v2.c
index a40c2150b..954638bd8 100644
--- a/mpp/hal/vpu/h264e/hal_h264e_vepu2_v2.c
+++ b/mpp/hal/vpu/h264e/hal_h264e_vepu2_v2.c
@@ -24,6 +24,7 @@
 #include "mpp_common.h"
 #include "mpp_device.h"
 #include "mpp_rc.h"
+#include "mpp_packet_impl.h"
 
 #include "mpp_enc_hal.h"
 #include "h264e_debug.h"
@@ -718,8 +719,10 @@ static MPP_RET hal_h264e_vepu2_wait_v2(void *hal, HalEncTask *task)
 {
     HalH264eVepu2Ctx *ctx = (HalH264eVepu2Ctx *)hal;
     HalH264eVepuMbRc *hw_mbrc = &ctx->hw_mbrc;
+    H264NaluType type = task->rc_task->frm.is_idr ?  H264_NALU_TYPE_IDR : H264_NALU_TYPE_SLICE;
+    MppPacket pkt = task->packet;
+    RK_S32 offset = mpp_packet_get_length(pkt);
     MPP_RET ret = MPP_NOK;
-    (void) task;
 
     hal_h264e_dbg_func("enter %p\n", hal);
 
@@ -735,8 +738,11 @@ static MPP_RET hal_h264e_vepu2_wait_v2(void *hal, HalEncTask *task)
     h264e_vepu2_get_mbrc(hw_mbrc, &ctx->regs_get);
     h264e_vepu_mbrc_update(ctx->rc_ctx, hw_mbrc);
 
+    mpp_packet_add_segment_info(pkt, type, offset, hw_mbrc->out_strm_size);
+
     {
         HalH264eVepuStreamAmend *amend = &ctx->amend;
+
         if (amend->enable) {
             amend->old_length = hw_mbrc->out_strm_size;
             h264e_vepu_stream_amend_proc(amend, &ctx->cfg->codec.h264.hw_cfg);
diff --git a/mpp/hal/vpu/h264e/hal_h264e_vepu_v2.c b/mpp/hal/vpu/h264e/hal_h264e_vepu_v2.c
index 1123bd80d..7db471d27 100644
--- a/mpp/hal/vpu/h264e/hal_h264e_vepu_v2.c
+++ b/mpp/hal/vpu/h264e/hal_h264e_vepu_v2.c
@@ -44,9 +44,9 @@ typedef struct HalH264eVepuMbRcImpl_t {
 
     /* frame rate control */
     RK_S32          fps_in_num;
-    RK_S32          fps_in_denorm;
+    RK_S32          fps_in_denom;
     RK_S32          fps_out_num;
-    RK_S32          fps_out_denorm;
+    RK_S32          fps_out_denom;
 
     RK_S32          fps_count;
     RK_S32          fps_step;
@@ -524,21 +524,21 @@ MPP_RET h264e_vepu_mbrc_setup(HalH264eVepuMbRcCtx ctx, MppEncCfgSet*cfg)
     p->mb_h     = MPP_ALIGN(prep->height, 16) / 16;
     p->pels     = p->width * p->height;
     p->mbs      = p->mb_w * p->mb_h;
-    p->bits_per_pic = axb_div_c(rc->bps_target, rc->fps_out_denorm,
+    p->bits_per_pic = axb_div_c(rc->bps_target, rc->fps_out_denom,
                                 rc->fps_out_num);
 
     mpp_assert(p->pels);
 
     // frame rate control
-    mpp_assert(rc->fps_out_num / rc->fps_out_denorm <= rc->fps_in_num / rc->fps_in_denorm);
+    mpp_assert(rc->fps_out_num / rc->fps_out_denom <= rc->fps_in_num / rc->fps_in_denom);
 
     p->fps_in_num       = rc->fps_in_num;
-    p->fps_in_denorm    = rc->fps_in_denorm;
+    p->fps_in_denom    = rc->fps_in_denom;
     p->fps_out_num      = rc->fps_out_num;
-    p->fps_out_denorm   = rc->fps_out_denorm;
+    p->fps_out_denom   = rc->fps_out_denom;
 
-    p->fps_step         = rc->fps_in_denorm * rc->fps_out_num;
-    p->fps_threshold    = rc->fps_in_num * rc->fps_out_denorm;
+    p->fps_step         = rc->fps_in_denom * rc->fps_out_num;
+    p->fps_threshold    = rc->fps_in_num * rc->fps_out_denom;
     p->fps_count        = p->fps_threshold;
 
     // if not constant
diff --git a/mpp/hal/vpu/h264e/hal_h264e_vpu_tbl.c b/mpp/hal/vpu/h264e/hal_h264e_vpu_tbl.c
index 02e249592..18f5f0207 100644
--- a/mpp/hal/vpu/h264e/hal_h264e_vpu_tbl.c
+++ b/mpp/hal/vpu/h264e/hal_h264e_vpu_tbl.c
@@ -53,7 +53,7 @@ const RK_U32 h264_intra16_favor[52] = {
 };
 
 const RK_U32 h264_inter_favor[52] = {
-    40, 40, 41, 42, 43, 44, 45, 48, 51, 53, 55, 60, 62, 67, 69, 72,
+    0, 0, 0, 0, 0, 0, 45, 48, 51, 53, 55, 60, 62, 67, 69, 72,
     78, 84, 90, 96, 110, 120, 135, 152, 170, 189, 210, 235, 265,
     297, 335, 376, 420, 470, 522, 572, 620, 670, 724, 770, 820,
     867, 915, 970, 1020, 1076, 1132, 1180, 1230, 1275, 1320, 1370
diff --git a/mpp/hal/vpu/jpegd/hal_jpegd_api.c b/mpp/hal/vpu/jpegd/hal_jpegd_api.c
index 3d88a779b..d6629097a 100644
--- a/mpp/hal/vpu/jpegd/hal_jpegd_api.c
+++ b/mpp/hal/vpu/jpegd/hal_jpegd_api.c
@@ -74,6 +74,7 @@ static MPP_RET hal_jpegd_deinit(void *hal)
 
 static MPP_RET hal_jpegd_init(void *hal, MppHalCfg *cfg)
 {
+    MPP_RET ret = MPP_ERR_UNKNOW;
     JpegdHalCtx *self = (JpegdHalCtx *)hal;
     MppHalApi *p_api = NULL;
     MppClientType client_type = VPU_CLIENT_BUTT;
@@ -155,20 +156,24 @@ static MPP_RET hal_jpegd_init(void *hal, MppHalCfg *cfg)
     } break;
     }
 
-    {
-        // report hw_info to parser
-        const MppSocInfo *info = mpp_get_soc_info();
-        RK_U32 i;
-
-        for (i = 0; i < MPP_ARRAY_ELEMS(info->dec_caps); i++) {
-            if (info->dec_caps[i] && info->dec_caps[i]->type == client_type) {
-                cfg->hw_info = info->dec_caps[i];
-                break;
-            }
-        }
+    ret = mpp_dev_init(&cfg->dev, client_type);
+    if (ret) {
+        mpp_err("mpp_dev_init failed ret: %d\n", ret);
+        goto __RETURN;
     }
 
-    return p_api->init(hal, cfg);
+    cfg->hw_info = mpp_get_dec_hw_info_by_client_type(client_type);
+    self->hw_info = cfg->hw_info;
+    self->dev = cfg->dev;
+
+    ret = p_api->init(hal, cfg);
+    if (ret) {
+        mpp_err("init device with client_type %d failed!\n", client_type);
+        mpp_dev_deinit(cfg->dev);
+    }
+
+__RETURN:
+    return ret;
 }
 
 const MppHalApi hal_api_jpegd = {
diff --git a/mpp/hal/vpu/jpegd/hal_jpegd_base.h b/mpp/hal/vpu/jpegd/hal_jpegd_base.h
index e66a63eb9..5e7e57c62 100644
--- a/mpp/hal/vpu/jpegd/hal_jpegd_base.h
+++ b/mpp/hal/vpu/jpegd/hal_jpegd_base.h
@@ -38,11 +38,8 @@ typedef struct JpegdHalCtx {
     MppBufSlots            packet_slots;
     MppBufSlots            frame_slots;
     MppDev                 dev;
-    MppClientType          dev_type;
-    RK_U32                 codec_type;
     void                   *regs;
     MppBufferGroup         group;
-    MppBuffer              frame_buf;
     MppBuffer              pTableBase;
     MppHalApi              hal_api;
     MppCbCtx               *dec_cb;
@@ -59,6 +56,7 @@ typedef struct JpegdHalCtx {
 
     RK_U32                 have_pp;
     PPInfo                 pp_info;
+    const MppDecHwCap       *hw_info;
 } JpegdHalCtx;
 
 #endif /* __HAL_JPEGD_COMMON_H__ */
diff --git a/mpp/hal/vpu/jpegd/hal_jpegd_common.c b/mpp/hal/vpu/jpegd/hal_jpegd_common.c
index d1098ef0b..32f7f0d87 100644
--- a/mpp/hal/vpu/jpegd/hal_jpegd_common.c
+++ b/mpp/hal/vpu/jpegd/hal_jpegd_common.c
@@ -432,22 +432,12 @@ void jpegd_write_qp_ac_dc_table(JpegdHalCtx *ctx,
     return;
 }
 
-void jpegd_check_have_pp(JpegdHalCtx *ctx)
-{
-    ctx->codec_type = mpp_get_vcodec_type();
-    ctx->have_pp = ((ctx->dev_type == VPU_CLIENT_VDPU1) &&
-                    (ctx->codec_type & (1 << VPU_CLIENT_VDPU1_PP))) ||
-                   ((ctx->dev_type == VPU_CLIENT_VDPU2) &&
-                    (ctx->codec_type & (1 << VPU_CLIENT_VDPU2_PP)));
-}
-
 MPP_RET jpegd_setup_output_fmt(JpegdHalCtx *ctx, JpegdSyntax *s, RK_S32 output)
 {
     jpegd_dbg_func("enter\n");
     RK_U32 pp_in_fmt = 0;
     RK_U32 stride = 0;
     PPInfo *pp_info = &ctx->pp_info;
-    MppClientType dev_type = ctx->dev_type;
     MppFrame frm = NULL;
     MPP_RET ret = MPP_OK;
 
@@ -513,40 +503,10 @@ MPP_RET jpegd_setup_output_fmt(JpegdHalCtx *ctx, JpegdSyntax *s, RK_S32 output)
 
         jpegd_dbg_hal("Post Process! pp_in_fmt:%d, pp_out_fmt:%d",
                       pp_in_fmt, pp_info->pp_out_fmt);
-
-        /* check and switch to dev with pp */
-        if (ctx->dev_type == VPU_CLIENT_VDPU1)
-            dev_type = VPU_CLIENT_VDPU1_PP;
-        else if (ctx->dev_type == VPU_CLIENT_VDPU2)
-            dev_type = VPU_CLIENT_VDPU2_PP;
     } else {
         /* keep original output format */
         ctx->output_fmt = s->output_fmt;
         pp_info->pp_enable = 0;
-
-        /* check and switch to dev without pp */
-        if (ctx->dev_type == VPU_CLIENT_VDPU1_PP)
-            dev_type = VPU_CLIENT_VDPU1;
-        else if (ctx->dev_type == VPU_CLIENT_VDPU2_PP)
-            dev_type = VPU_CLIENT_VDPU2;
-    }
-
-    mpp_assert(ctx->dev);
-    if (ctx->dev_type != dev_type && ctx->dev) {
-        MppDev dev = NULL;
-
-        ret = mpp_dev_init(&dev, dev_type);
-        if (ret) {
-            mpp_err_f("dev type %x -> %x switch failed ret %d\n",
-                      ctx->dev_type, dev_type, ret);
-            return ret;
-        }
-
-        mpp_dev_deinit(ctx->dev);
-        ctx->dev = dev;
-        ctx->dev_type = dev_type;
-
-        jpegd_dbg_hal("mpp_dev_init success.\n");
     }
 
     mpp_buf_slot_get_prop(ctx->frame_slots, output,
diff --git a/mpp/hal/vpu/jpegd/hal_jpegd_common.h b/mpp/hal/vpu/jpegd/hal_jpegd_common.h
index 6770895fc..d1ce7f148 100644
--- a/mpp/hal/vpu/jpegd/hal_jpegd_common.h
+++ b/mpp/hal/vpu/jpegd/hal_jpegd_common.h
@@ -75,7 +75,6 @@ RK_U32 jpegd_vdpu_tail_0xFF_patch(MppBuffer stream, RK_U32 length);
 void jpegd_write_qp_ac_dc_table(JpegdHalCtx *ctx,
                                 JpegdSyntax*syntax);
 
-void jpegd_check_have_pp(JpegdHalCtx *ctx);
 MPP_RET jpegd_setup_output_fmt(JpegdHalCtx *ctx, JpegdSyntax *syntax,
                                RK_S32 output);
 
diff --git a/mpp/hal/vpu/jpegd/hal_jpegd_rkv.c b/mpp/hal/vpu/jpegd/hal_jpegd_rkv.c
index c3e3f4f48..34b879662 100644
--- a/mpp/hal/vpu/jpegd/hal_jpegd_rkv.c
+++ b/mpp/hal/vpu/jpegd/hal_jpegd_rkv.c
@@ -24,6 +24,7 @@
 #include "mpp_debug.h"
 #include "mpp_frame.h"
 #include "mpp_common.h"
+#include "mpp_buffer_impl.h"
 
 #include "jpegd_syntax.h"
 #include "hal_jpegd_common.h"
@@ -82,8 +83,6 @@ MPP_RET jpegd_write_rkv_htbl(JpegdHalCtx *ctx, JpegdSyntax *jpegd_syntax)
     MPP_RET ret = MPP_OK;
 
     JpegdSyntax *s = jpegd_syntax;
-    AcTable *ac_ptr0 = NULL, *ac_ptr1 = NULL;
-    DcTable *dc_ptr0 = NULL, *dc_ptr1 = NULL;
     void * htbl_ptr[6] = {NULL};
     RK_U32 i, j, k = 0;
     RK_U8 *p_htbl_value = (RK_U8 *)mpp_buffer_get_ptr(ctx->pTableBase) + RKD_HUFFMAN_VALUE_TBL_OFFSET;
@@ -99,30 +98,14 @@ MPP_RET jpegd_write_rkv_htbl(JpegdHalCtx *ctx, JpegdSyntax *jpegd_syntax)
     AcTable *ac_ptr;
     DcTable *dc_ptr;
 
-    if (s->ac_index[0] == HUFFMAN_TABLE_ID_ZERO) {
-        /* Luma's AC uses Huffman table zero */
-        ac_ptr0 = &(s->ac_table[HUFFMAN_TABLE_ID_ZERO]);
-        ac_ptr1 = &(s->ac_table[HUFFMAN_TABLE_ID_ONE]);
-    } else {
-        ac_ptr0 = &(s->ac_table[HUFFMAN_TABLE_ID_ONE]);
-        ac_ptr1 = &(s->ac_table[HUFFMAN_TABLE_ID_ZERO]);
-    }
+    htbl_ptr[0] = &s->dc_table[s->dc_index[0]];
+    htbl_ptr[1] = &s->ac_table[s->ac_index[0]];
 
-    if (s->dc_index[0] == HUFFMAN_TABLE_ID_ZERO) {
-        /* Luma's DC uses Huffman table zero */
-        dc_ptr0 = &(s->dc_table[HUFFMAN_TABLE_ID_ZERO]);
-        dc_ptr1 = &(s->dc_table[HUFFMAN_TABLE_ID_ONE]);
-    } else {
-        dc_ptr0 = &(s->dc_table[HUFFMAN_TABLE_ID_ONE]);
-        dc_ptr1 = &(s->dc_table[HUFFMAN_TABLE_ID_ZERO]);
-    }
+    htbl_ptr[2] = &s->dc_table[s->dc_index[1]];
+    htbl_ptr[3] = &s->ac_table[s->ac_index[1]];
 
-    htbl_ptr[0] = dc_ptr0;
-    htbl_ptr[1] = ac_ptr0;
-    htbl_ptr[2] = dc_ptr1;
-    htbl_ptr[3] = ac_ptr1;
-    htbl_ptr[4] = dc_ptr1;
-    htbl_ptr[5] = ac_ptr1;
+    htbl_ptr[4] = htbl_ptr[2];
+    htbl_ptr[5] = htbl_ptr[3];
 
     for (k = 0; k < s->nb_components; k++) {
         dc_ptr = (DcTable *)htbl_ptr[k * 2];
@@ -254,13 +237,6 @@ MPP_RET hal_jpegd_rkv_init(void *hal, MppHalCfg *cfg)
     ctx->dec_cb       = cfg->dec_cb;
     ctx->packet_slots = cfg->packet_slots;
     ctx->frame_slots  = cfg->frame_slots;
-    ctx->dev_type     = VPU_CLIENT_JPEG_DEC;
-
-    ret = mpp_dev_init(&ctx->dev, ctx->dev_type);
-    if (ret) {
-        mpp_err("mpp_dev_init failed. ret: %d\n", ret);
-        return ret;
-    }
 
     /* allocate regs buffer */
     if (ctx->regs == NULL) {
@@ -281,18 +257,13 @@ MPP_RET hal_jpegd_rkv_init(void *hal, MppHalCfg *cfg)
         }
     }
 
-    ret = mpp_buffer_get(ctx->group, &ctx->frame_buf,
-                         JPEGD_STREAM_BUFF_SIZE);
-    if (ret) {
-        mpp_err_f("Get frame buffer failed ret %d\n", ret);
-        return ret;
-    }
-
     ret = mpp_buffer_get(ctx->group, &ctx->pTableBase, RKD_TABLE_SIZE);
     if (ret) {
         mpp_err_f("Get table buffer failed, ret %d\n", ret);
     }
 
+    mpp_buffer_attach_dev(ctx->pTableBase, ctx->dev);
+
     jpegd_dbg_func("exit\n");
     return ret;
 }
@@ -363,6 +334,11 @@ static MPP_RET setup_output_fmt(JpegdHalCtx *ctx, JpegdSyntax *syntax, RK_S32 ou
         ctx->output_fmt = s->output_fmt;
     }
 
+    if (MPP_FRAME_FMT_IS_TILE(ctx->output_fmt))
+        regs->reg2_sys.dec_out_sequence = OUTPUT_TILE;
+    else
+        regs->reg2_sys.dec_out_sequence = OUTPUT_RASTER;
+
     jpegd_dbg_hal("convert format %d to format %d\n", s->output_fmt, ctx->output_fmt);
 
     if ((s->yuv_mode == YUV_MODE_420 && regs->reg2_sys.yuv_out_format == YUV_OUT_FMT_NO_TRANS) ||
@@ -392,8 +368,7 @@ static MPP_RET jpegd_gen_regs(JpegdHalCtx *ctx, JpegdSyntax *syntax)
     regs->reg3_pic_size.pic_width_m1 = s->width - 1;
     regs->reg3_pic_size.pic_height_m1 = s->height - 1;
 
-    if (s->sample_precision != DCT_SAMPLE_PRECISION_8 || (s->htbl_entry & 0x0f) != 0x0f
-        || s->qtbl_entry > TBL_ENTRY_3)
+    if (s->sample_precision != DCT_SAMPLE_PRECISION_8 || s->qtbl_entry > TBL_ENTRY_3)
         return MPP_NOK;
 
     regs->reg4_pic_fmt.pixel_depth = BIT_DEPTH_8;
@@ -402,8 +377,8 @@ static MPP_RET jpegd_gen_regs(JpegdHalCtx *ctx, JpegdSyntax *syntax)
     }
 
     if (s->nb_components > 1) {
-        regs->reg4_pic_fmt.qtables_sel = (s->qtbl_entry > 1) ? s->qtbl_entry : TBL_ENTRY_2;
-        regs->reg4_pic_fmt.htables_sel = (s->htbl_entry > 0x0f) ? s->htbl_entry : TBL_ENTRY_2;
+        regs->reg4_pic_fmt.qtables_sel = (s->qtbl_entry > 1) ? TBL_ENTRY_3 : TBL_ENTRY_2;
+        regs->reg4_pic_fmt.htables_sel = (s->htbl_entry > 0x0f) ? TBL_ENTRY_3 : TBL_ENTRY_2;
     } else {
         regs->reg4_pic_fmt.qtables_sel = TBL_ENTRY_1;
         regs->reg4_pic_fmt.htables_sel = TBL_ENTRY_1;
@@ -478,8 +453,42 @@ static MPP_RET jpegd_gen_regs(JpegdHalCtx *ctx, JpegdSyntax *syntax)
 
     y_virstride = y_hor_stride * out_height;
     if (regs->reg2_sys.dec_out_sequence == OUTPUT_TILE) {
-        y_hor_stride <<= 3;
-        uv_hor_virstride <<= 3;
+        if (mpp_get_soc_type() == ROCKCHIP_SOC_RK3576) {
+            switch (regs->reg2_sys.yuv_out_format) {
+            case YUV_OUT_FMT_2_YUYV:
+                y_hor_stride = y_hor_stride * 4 * 2;
+                break;
+            case YUV_OUT_FMT_NO_TRANS:
+                switch (regs->reg4_pic_fmt.jpeg_mode) {
+                case YUV_MODE_422:
+                case YUV_MODE_440:
+                    y_hor_stride = y_hor_stride * 4 * 2;
+                    break;
+                case YUV_MODE_444:
+                    y_hor_stride = y_hor_stride * 4 * 3;
+                    break;
+                case YUV_MODE_411:
+                case YUV_MODE_420:
+                    y_hor_stride = y_hor_stride * 4 * 3 / 2;
+                    break;
+                case YUV_MODE_400:
+                    y_hor_stride = y_hor_stride * 4;
+                    break;
+                default:
+                    return MPP_NOK;
+                    break;
+                }
+                break;
+            case YUV_OUT_FMT_2_NV12:
+                y_hor_stride = y_hor_stride * 4 * 3 / 2;
+                break;
+            }
+
+            uv_hor_virstride = 0;
+        } else {
+            y_hor_stride <<= 3;
+            uv_hor_virstride <<= 3;
+        }
     }
 
     regs->reg5_hor_virstride.y_hor_virstride = y_hor_stride & 0xffff;
@@ -584,14 +593,6 @@ MPP_RET hal_jpegd_rkv_deinit(void *hal)
         ctx->dev = NULL;
     }
 
-    if (ctx->frame_buf) {
-        ret = mpp_buffer_put(ctx->frame_buf);
-        if (ret) {
-            mpp_err_f("put buffer failed\n");
-            return ret;
-        }
-    }
-
     if (ctx->pTableBase) {
         ret = mpp_buffer_put(ctx->pTableBase);
         if (ret) {
@@ -656,6 +657,7 @@ MPP_RET hal_jpegd_rkv_gen_regs(void *hal,  HalTaskInfo *syn)
     setup_output_fmt(ctx, s, syn->dec.output);
 
     ret = jpegd_gen_regs(ctx, s);
+    mpp_buffer_sync_end(strm_buf);
     mpp_buffer_sync_end(ctx->pTableBase);
 
     if (ret != MPP_OK) {
@@ -818,29 +820,33 @@ MPP_RET hal_jpegd_rkv_control(void *hal, MpiCmd cmd_type, void *param)
     case MPP_DEC_SET_OUTPUT_FORMAT: {
         MppFrameFormat output_fmt = *((MppFrameFormat *)param);
         RockchipSocType soc_type = mpp_get_soc_type();
+        MppFrameFormat frm_fmt = output_fmt & MPP_FRAME_FMT_MASK;
 
-        ret = MPP_NOK;
-
-        switch ((RK_S32)output_fmt) {
-        case MPP_FMT_YUV420SP :
-        case MPP_FMT_YUV420SP_VU :
-        case MPP_FMT_YUV422_YUYV :
-        case MPP_FMT_YUV422_YVYU :
-        case MPP_FMT_RGB888 : {
-            ret = MPP_OK;
-        } break;
-        case (MPP_FMT_RGB565) : { // rgb565be
-            if (soc_type >= ROCKCHIP_SOC_RK3588 &&
-                soc_type < ROCKCHIP_SOC_BUTT)
-                ret = MPP_OK;
-        } break;
-        case (MPP_FMT_BGR565 | MPP_FRAME_FMT_LE_MASK) : { // bgr565le
-            if (soc_type < ROCKCHIP_SOC_RK3588 &&
-                soc_type > ROCKCHIP_SOC_AUTO)
-                ret = MPP_OK;
-        } break;
-        default:
-            break;
+        if (MPP_FRAME_FMT_IS_FBC(output_fmt)) {
+            ret = MPP_ERR_VALUE;
+        }
+
+        if (MPP_FRAME_FMT_IS_TILE(output_fmt)) {
+            if (soc_type < ROCKCHIP_SOC_RK3576 || MPP_FRAME_FMT_IS_RGB(output_fmt)) {
+                ret = MPP_ERR_VALUE;
+            }
+        }
+
+        if (MPP_FRAME_FMT_IS_RGB(output_fmt)) {
+            if (soc_type == ROCKCHIP_SOC_RK3576) {
+                ret = MPP_ERR_VALUE;
+            } else if (soc_type >= ROCKCHIP_SOC_RK3588) {
+                // only rgb565be and rgb888 supported
+                if (output_fmt != MPP_FMT_RGB555 && output_fmt != MPP_FMT_RGB888 ) {
+                    ret = MPP_ERR_VALUE;
+                }
+            } else {
+                // only bgr565le and rgb 888 supported
+                if (frm_fmt != (MPP_FMT_BGR565 | MPP_FRAME_FMT_LE_MASK)
+                    && output_fmt != MPP_FMT_RGB888) {
+                    ret = MPP_ERR_VALUE;
+                }
+            }
         }
 
         if (ret) {
diff --git a/mpp/hal/vpu/jpegd/hal_jpegd_rkv_reg.h b/mpp/hal/vpu/jpegd/hal_jpegd_rkv_reg.h
index 9b803564e..0d615a6b6 100644
--- a/mpp/hal/vpu/jpegd/hal_jpegd_rkv_reg.h
+++ b/mpp/hal/vpu/jpegd/hal_jpegd_rkv_reg.h
@@ -99,7 +99,14 @@ typedef struct {
         RK_U32 soft_rest_rdy                    : 1;
         RK_U32 buf_empty_force_end_flag         : 1;
         RK_U32 care_strm_error_e                : 1;
-        RK_U32                                  : 15;
+        RK_U32 low_delay_out_sta                : 1;
+        RK_U32 lkt_operation_error_sta          : 1;
+        RK_U32 lkt_mode_int_sta                 : 1;
+        RK_U32 lkt_force_stop_sta               : 1;
+        RK_U32 lkt_node_int_sta                 : 1;
+        RK_U32 lkt_err_stop_sta                 : 1;
+        RK_U32 lkt_data_err_sta                 : 1;
+        RK_U32                                  : 8;
     } reg1_int;
 
     struct {
@@ -113,7 +120,8 @@ typedef struct {
         RK_U32 out_swap32_e                     : 1;
         RK_U32 out_swap64_e                     : 1;
         RK_U32 out_cbcr_swap                    : 1;
-        RK_U32                                  : 2;
+        RK_U32 out_byte_swap                    : 1;
+        RK_U32                                  : 1;
         RK_U32 scaledown_mode                   : 2;
         RK_U32                                  : 2;
         RK_U32 time_out_mode                    : 1;
@@ -122,7 +130,8 @@ typedef struct {
         RK_U32 fbc_e                            : 1;
         RK_U32 allow_16x8_cp_flag               : 1;
         RK_U32 fbc_force_uncompress             : 1;
-        RK_U32                                  : 1;
+        // 0 -- rgb565/rgb888, 1 -- bgr565, bgr888
+        RK_U32 bgr_sequence                     : 1;
         RK_U32 fill_down_e                      : 1;
         RK_U32 fill_right_e                     : 1;
         RK_U32 dec_out_sequence                 : 1;
@@ -220,8 +229,15 @@ typedef struct {
         RK_U32 val;
     } reg16_clk_gate;
 
-    RK_U32 reg17_29[13];
+    // 0x0044, bit[16:0]
+    RK_U32 reg17_low_delay_output;
+    // 0x0048, bit[16:0]
+    RK_U32 reg18_low_delay_output_status;
+
+    // 0x004c ~ 0x0074
+    RK_U32 reg19_29[11];
 
+    // 0x0078
     struct {
         RK_U32 axi_per_work_e                   : 1;
         RK_U32 axi_per_clr_e                    : 1;
diff --git a/mpp/hal/vpu/jpegd/hal_jpegd_vdpu1.c b/mpp/hal/vpu/jpegd/hal_jpegd_vdpu1.c
index 4ce983a25..96692ad18 100644
--- a/mpp/hal/vpu/jpegd/hal_jpegd_vdpu1.c
+++ b/mpp/hal/vpu/jpegd/hal_jpegd_vdpu1.c
@@ -740,14 +740,7 @@ MPP_RET hal_jpegd_vdpu1_init(void *hal, MppHalCfg *cfg)
     JpegHalCtx->dec_cb       = cfg->dec_cb;
     JpegHalCtx->packet_slots = cfg->packet_slots;
     JpegHalCtx->frame_slots  = cfg->frame_slots;
-    JpegHalCtx->dev_type     = VPU_CLIENT_VDPU1;
-
-    ret = mpp_dev_init(&JpegHalCtx->dev, JpegHalCtx->dev_type);
-    if (ret) {
-        mpp_err_f("mpp_dev_init failed. ret: %d\n", ret);
-        return ret;
-    }
-    cfg->dev = JpegHalCtx->dev;
+    JpegHalCtx->have_pp      = cfg->hw_info->cap_jpg_pp_out;
 
     /* allocate regs buffer */
     if (JpegHalCtx->regs == NULL) {
@@ -772,13 +765,6 @@ MPP_RET hal_jpegd_vdpu1_init(void *hal, MppHalCfg *cfg)
         }
     }
 
-    ret = mpp_buffer_get(JpegHalCtx->group, &JpegHalCtx->frame_buf,
-                         JPEGD_STREAM_BUFF_SIZE);
-    if (ret) {
-        mpp_err_f("get frame buffer failed ret %d\n", ret);
-        return ret;
-    }
-
     ret = mpp_buffer_get(JpegHalCtx->group, &JpegHalCtx->pTableBase,
                          JPEGD_BASELINE_TABLE_SIZE);
     if (ret) {
@@ -791,7 +777,6 @@ MPP_RET hal_jpegd_vdpu1_init(void *hal, MppHalCfg *cfg)
     pp_info->pp_enable = 0;
     pp_info->pp_in_fmt = PP_IN_FORMAT_YUV420SEMI;
     pp_info->pp_out_fmt = PP_OUT_FORMAT_YUV420INTERLAVE;
-    jpegd_check_have_pp(JpegHalCtx);
 
     JpegHalCtx->output_fmt = MPP_FMT_YUV420SP;
     JpegHalCtx->set_output_fmt_flag = 0;
@@ -817,14 +802,6 @@ MPP_RET hal_jpegd_vdpu1_deinit(void *hal)
         JpegHalCtx->dev = NULL;
     }
 
-    if (JpegHalCtx->frame_buf) {
-        ret = mpp_buffer_put(JpegHalCtx->frame_buf);
-        if (ret) {
-            mpp_err_f("put buffer failed\n");
-            return ret;
-        }
-    }
-
     if (JpegHalCtx->pTableBase) {
         ret = mpp_buffer_put(JpegHalCtx->pTableBase);
         if (ret) {
@@ -905,6 +882,7 @@ MPP_RET hal_jpegd_vdpu1_gen_regs(void *hal,  HalTaskInfo *syn)
         }
 
         ret = jpegd_gen_regs(JpegHalCtx, syntax);
+        mpp_buffer_sync_end(streambuf);
         mpp_buffer_sync_end(JpegHalCtx->pTableBase);
         if (ret != MPP_OK) {
             mpp_err_f("generate registers failed\n");
@@ -937,10 +915,15 @@ MPP_RET hal_jpegd_vdpu1_start(void *hal, HalTaskInfo *task)
     do {
         MppDevRegWrCfg wr_cfg;
         MppDevRegRdCfg rd_cfg;
-        RK_U32 reg_size = mpp_get_ioctl_version() ?
+        MppIoctlVersion ioctl_version = mpp_get_ioctl_version();
+        RK_U32 reg_size = ioctl_version ?
                           sizeof(((JpegdIocRegInfo *)0)->regs) :
                           sizeof(JpegdIocRegInfo) - EXTRA_INFO_SIZE;
 
+        if (ROCKCHIP_SOC_RK3036 == mpp_get_soc_type() &&
+            IOCTL_VCODEC_SERVICE == ioctl_version)
+            reg_size -= sizeof(((JpegdIocRegInfo *)0)->regs_diff);
+
         wr_cfg.reg = regs;
         wr_cfg.size = reg_size;
         wr_cfg.offset = 0;
@@ -1029,14 +1012,14 @@ MPP_RET hal_jpegd_vdpu1_wait(void *hal, HalTaskInfo *task)
     /* debug information */
     if (jpegd_debug & JPEGD_DBG_IO) {
         static FILE *jpg_file;
-        static char name[32];
+        static char name[64];
         MppBuffer outputBuf = NULL;
         void *base = NULL;
         mpp_buf_slot_get_prop(JpegHalCtx->frame_slots, task->dec.output,
                               SLOT_BUFFER, &outputBuf);
         base = mpp_buffer_get_ptr(outputBuf);
 
-        snprintf(name, sizeof(name) - 1, "/tmp/output%02d.yuv",
+        snprintf(name, sizeof(name) - 1, "/data/tmp/output%02d.yuv",
                  JpegHalCtx->output_yuv_count);
         jpg_file = fopen(name, "wb+");
         if (jpg_file) {
diff --git a/mpp/hal/vpu/jpegd/hal_jpegd_vdpu2.c b/mpp/hal/vpu/jpegd/hal_jpegd_vdpu2.c
index 846a02387..cd98ee115 100644
--- a/mpp/hal/vpu/jpegd/hal_jpegd_vdpu2.c
+++ b/mpp/hal/vpu/jpegd/hal_jpegd_vdpu2.c
@@ -729,14 +729,8 @@ MPP_RET hal_jpegd_vdpu2_init(void *hal, MppHalCfg *cfg)
     JpegHalCtx->dec_cb       = cfg->dec_cb;
     JpegHalCtx->packet_slots = cfg->packet_slots;
     JpegHalCtx->frame_slots  = cfg->frame_slots;
-    JpegHalCtx->dev_type     = VPU_CLIENT_VDPU2;
+    JpegHalCtx->have_pp      = cfg->hw_info->cap_jpg_pp_out;
 
-    ret = mpp_dev_init(&JpegHalCtx->dev, JpegHalCtx->dev_type);
-    if (ret) {
-        mpp_err_f("mpp_dev_init failed. ret: %d\n", ret);
-        return ret;
-    }
-    cfg->dev = JpegHalCtx->dev;
     //init regs
     JpegdIocRegInfo *info = NULL;
     info = mpp_calloc(JpegdIocRegInfo, 1);
@@ -757,13 +751,6 @@ MPP_RET hal_jpegd_vdpu2_init(void *hal, MppHalCfg *cfg)
         }
     }
 
-    ret = mpp_buffer_get(JpegHalCtx->group, &JpegHalCtx->frame_buf,
-                         JPEGD_STREAM_BUFF_SIZE);
-    if (ret) {
-        mpp_err_f("get buffer failed\n");
-        return ret;
-    }
-
     ret = mpp_buffer_get(JpegHalCtx->group, &JpegHalCtx->pTableBase,
                          JPEGD_BASELINE_TABLE_SIZE);
     if (ret) {
@@ -776,7 +763,6 @@ MPP_RET hal_jpegd_vdpu2_init(void *hal, MppHalCfg *cfg)
     pp_info->pp_enable = 0;
     pp_info->pp_in_fmt = PP_IN_FORMAT_YUV420SEMI;
     pp_info->pp_out_fmt = PP_OUT_FORMAT_YUV420INTERLAVE;
-    jpegd_check_have_pp(JpegHalCtx);
 
     JpegHalCtx->output_fmt = MPP_FMT_YUV420SP;
     JpegHalCtx->set_output_fmt_flag = 0;
@@ -802,14 +788,6 @@ MPP_RET hal_jpegd_vdpu2_deinit(void *hal)
         JpegHalCtx->dev = NULL;
     }
 
-    if (JpegHalCtx->frame_buf) {
-        ret = mpp_buffer_put(JpegHalCtx->frame_buf);
-        if (ret) {
-            mpp_err_f("put frame buffer failed\n");
-            return ret;
-        }
-    }
-
     if (JpegHalCtx->pTableBase) {
         ret = mpp_buffer_put(JpegHalCtx->pTableBase);
         if (ret) {
@@ -888,6 +866,7 @@ MPP_RET hal_jpegd_vdpu2_gen_regs(void *hal,  HalTaskInfo *syn)
         }
 
         ret = jpegd_gen_regs(JpegHalCtx, syntax);
+        mpp_buffer_sync_end(streambuf);
         mpp_buffer_sync_end(JpegHalCtx->pTableBase);
         if (ret != MPP_OK) {
             mpp_err_f("generate registers failed\n");
@@ -1001,14 +980,14 @@ MPP_RET hal_jpegd_vdpu2_wait(void *hal, HalTaskInfo *task)
     /* debug information */
     if (jpegd_debug & JPEGD_DBG_IO) {
         static FILE *jpg_file;
-        static char name[32];
+        static char name[64];
         MppBuffer outputBuf = NULL;
         void *base = NULL;
         mpp_buf_slot_get_prop(JpegHalCtx->frame_slots, task->dec.output,
                               SLOT_BUFFER, &outputBuf);
         base = mpp_buffer_get_ptr(outputBuf);
 
-        snprintf(name, sizeof(name) - 1, "/tmp/output%02d.yuv",
+        snprintf(name, sizeof(name) - 1, "/data/tmp/output%02d.yuv",
                  JpegHalCtx->output_yuv_count);
         jpg_file = fopen(name, "wb+");
         if (jpg_file) {
diff --git a/mpp/hal/vpu/jpege/hal_jpege_vepu1_v2.c b/mpp/hal/vpu/jpege/hal_jpege_vepu1_v2.c
index d544bb3f0..0e8bb73af 100644
--- a/mpp/hal/vpu/jpege/hal_jpege_vepu1_v2.c
+++ b/mpp/hal/vpu/jpege/hal_jpege_vepu1_v2.c
@@ -127,7 +127,7 @@ static MPP_RET hal_jpege_vepu1_get_task(void *hal, HalEncTask *task)
 
     /* prepare for part encoding */
     ctx->mcu_y = 0;
-    ctx->mcu_h = syntax->mcu_h;
+    ctx->mcu_h = syntax->mcu_ver_cnt;
     ctx->sw_bit = 0;
     ctx->part_bytepos = 0;
     ctx->part_x_fill = 0;
@@ -492,8 +492,8 @@ static MPP_RET hal_jpege_vepu1_part_start(void *hal, HalEncTask *task)
     MPP_RET ret = MPP_OK;
     HalJpegeCtx *ctx = (HalJpegeCtx *)hal;
     JpegeSyntax *syntax = (JpegeSyntax *)task->syntax.data;
-    RK_U32 mcu_w = syntax->mcu_w;
-    RK_U32 mcu_h = syntax->mcu_h;
+    RK_U32 mcu_w = syntax->mcu_hor_cnt;
+    RK_U32 mcu_h = syntax->mcu_ver_cnt;
     RK_U32 mcu_y = ctx->mcu_y;
     RK_U32 part_mcu_h = syntax->part_rows;
     RK_U32 *regs = (RK_U32 *)ctx->regs;
diff --git a/mpp/hal/vpu/jpege/hal_jpege_vepu2_v2.c b/mpp/hal/vpu/jpege/hal_jpege_vepu2_v2.c
index 731d2a9c4..0185aaec8 100644
--- a/mpp/hal/vpu/jpege/hal_jpege_vepu2_v2.c
+++ b/mpp/hal/vpu/jpege/hal_jpege_vepu2_v2.c
@@ -182,7 +182,7 @@ MPP_RET hal_jpege_vepu2_get_task(void *hal, HalEncTask *task)
 
     /* prepare for part encoding */
     ctx->mcu_y = 0;
-    ctx->mcu_h = syntax->mcu_h;
+    ctx->mcu_h = syntax->mcu_ver_cnt;
     ctx->sw_bit = 0;
     ctx->part_bytepos = 0;
     ctx->part_x_fill = 0;
@@ -662,7 +662,7 @@ static MPP_RET multi_core_start(HalJpegeCtx *ctx, HalEncTask *task)
                        (part_y_fill);
         }
 
-        regs[103] = syntax->mcu_w << 8  |
+        regs[103] = syntax->mcu_hor_cnt << 8  |
                     (part_enc_mcu_h) << 20 |
                     (1 << 6) |  /* intra coding  */
                     (2 << 4) |  /* format jpeg   */
@@ -688,7 +688,7 @@ static MPP_RET multi_core_start(HalJpegeCtx *ctx, HalEncTask *task)
 
         if (syntax->rotation == MPP_ENC_ROT_90 || syntax->rotation == MPP_ENC_ROT_270) {
             regs[103] = part_enc_mcu_h << 8  |
-                        (syntax->mcu_w) << 20 |
+                        (syntax->mcu_hor_cnt) << 20 |
                         (1 << 6) |  /* intra coding  */
                         (2 << 4) |  /* format jpeg   */
                         1;          /* encoder start */
@@ -699,7 +699,7 @@ static MPP_RET multi_core_start(HalJpegeCtx *ctx, HalEncTask *task)
              */
             if (syntax->rotation == MPP_ENC_ROT_270)
                 cfg.offset_x = syntax->offset_x +
-                               (syntax->mcu_h - ctx_ext->part_rows[0] - mcu_y) * 16;
+                               (syntax->mcu_ver_cnt - ctx_ext->part_rows[0] - mcu_y) * 16;
             else
                 cfg.offset_x = syntax->offset_x + mcu_y * 16;
 
@@ -925,8 +925,8 @@ MPP_RET hal_jpege_vepu2_part_start(void *hal, HalEncTask *task)
     MPP_RET ret = MPP_OK;
     HalJpegeCtx *ctx = (HalJpegeCtx *)hal;
     JpegeSyntax *syntax = (JpegeSyntax *)task->syntax.data;
-    RK_U32 mcu_w = syntax->mcu_w;
-    RK_U32 mcu_h = syntax->mcu_h;
+    RK_U32 mcu_w = syntax->mcu_hor_cnt;
+    RK_U32 mcu_h = syntax->mcu_ver_cnt;
     RK_U32 mcu_y = ctx->mcu_y;
     RK_U32 part_mcu_h = syntax->part_rows;
     RK_S32 reg_idx = task->flags.reg_idx;
diff --git a/mpp/hal/vpu/vp8e/hal_vp8e_base.c b/mpp/hal/vpu/vp8e/hal_vp8e_base.c
index 21509e49c..68246b295 100644
--- a/mpp/hal/vpu/vp8e/hal_vp8e_base.c
+++ b/mpp/hal/vpu/vp8e/hal_vp8e_base.c
@@ -821,10 +821,10 @@ void write_ivf_header(void *hal, RK_U8 *dst)
     data[18] = (rc->fps_out_num >> 16) & 0xff;
     data[19] = (rc->fps_out_num >> 24) & 0xff;
 
-    data[20] = rc->fps_out_denorm & 0xff;
-    data[21] = (rc->fps_out_denorm >> 8) & 0xff;
-    data[22] = (rc->fps_out_denorm >> 16) & 0xff;
-    data[23] = (rc->fps_out_denorm >> 24) & 0xff;
+    data[20] = rc->fps_out_denom & 0xff;
+    data[21] = (rc->fps_out_denom >> 8) & 0xff;
+    data[22] = (rc->fps_out_denom >> 16) & 0xff;
+    data[23] = (rc->fps_out_denom >> 24) & 0xff;
 
     data[24] = ctx->frame_cnt & 0xff;
     data[25] = (ctx->frame_cnt >> 8) & 0xff;
diff --git a/mpp/inc/mpp_cfg.h b/mpp/inc/mpp_cfg.h
index 7f530c8dc..2f4b79087 100644
--- a/mpp/inc/mpp_cfg.h
+++ b/mpp/inc/mpp_cfg.h
@@ -30,100 +30,61 @@ typedef enum CfgType_e {
     CFG_FUNC_TYPE_BUTT,
 } CfgType;
 
-typedef struct MppCfgApi_t {
-    const char          *name;
+typedef struct MppCfgInfo_t {
     CfgType             data_type;
+    /* update flag info 32bit */
+    RK_U32              flag_type;
     RK_U32              flag_offset;
     RK_U32              flag_value;
+    /* data access info */
     RK_U32              data_offset;
     RK_S32              data_size;
-} MppCfgApi;
-
-typedef struct MppCfgInfo_t {
-    /* size for the whole node including name */
-    RK_S32          node_size;
-    RK_U32          name_len;
-    /* CfgType */
-    RK_S32          data_type;
-    /* update flag info 32bit */
-    RK_S32          flag_offset;
-    RK_U32          flag_value;
-    /* data access info */
-    RK_S32          data_offset;
-    RK_S32          data_size;
-    /* linked next node offset for pointer type */
-    RK_S32          node_next;
-    /* function pointer for get / put accessor (user filled) */
-    RK_U64          set_func;
-    RK_U64          get_func;
-    /* reserve for extension */
-    RK_U64          stuff[2];
-    char            name[];
-} MppCfgInfoNode;
-
-typedef MPP_RET (*CfgSetS32)(MppCfgInfoNode *info, void *cfg, RK_S32 val);
-typedef MPP_RET (*CfgGetS32)(MppCfgInfoNode *info, void *cfg, RK_S32 *val);
-typedef MPP_RET (*CfgSetU32)(MppCfgInfoNode *info, void *cfg, RK_U32 val);
-typedef MPP_RET (*CfgGetU32)(MppCfgInfoNode *info, void *cfg, RK_U32 *val);
-typedef MPP_RET (*CfgSetS64)(MppCfgInfoNode *info, void *cfg, RK_S64 val);
-typedef MPP_RET (*CfgGetS64)(MppCfgInfoNode *info, void *cfg, RK_S64 *val);
-typedef MPP_RET (*CfgSetU64)(MppCfgInfoNode *info, void *cfg, RK_U64 val);
-typedef MPP_RET (*CfgGetU64)(MppCfgInfoNode *info, void *cfg, RK_U64 *val);
-typedef MPP_RET (*CfgSetSt) (MppCfgInfoNode *info, void *cfg, void *val);
-typedef MPP_RET (*CfgGetSt) (MppCfgInfoNode *info, void *cfg, void *val);
-typedef MPP_RET (*CfgSetPtr)(MppCfgInfoNode *info, void *cfg, void *val);
-typedef MPP_RET (*CfgGetPtr)(MppCfgInfoNode *info, void *cfg, void **val);
-
-#define MPP_CFG_SET_S32(info, cfg, val) (mpp_cfg_ops.fp_SetS32)(info, cfg, val)
-#define MPP_CFG_GET_S32(info, cfg, val) (mpp_cfg_ops.fp_GetS32)(info, cfg, (RK_S32 *)(val))
-#define MPP_CFG_SET_U32(info, cfg, val) (mpp_cfg_ops.fp_SetU32)(info, cfg, val)
-#define MPP_CFG_GET_U32(info, cfg, val) (mpp_cfg_ops.fp_GetU32)(info, cfg, (RK_U32 *)(val))
-#define MPP_CFG_SET_S64(info, cfg, val) (mpp_cfg_ops.fp_SetS64)(info, cfg, val)
-#define MPP_CFG_GET_S64(info, cfg, val) (mpp_cfg_ops.fp_GetS64)(info, cfg, (RK_S64 *)(val))
-#define MPP_CFG_SET_U64(info, cfg, val) (mpp_cfg_ops.fp_SetU64)(info, cfg, val)
-#define MPP_CFG_GET_U64(info, cfg, val) (mpp_cfg_ops.fp_GetU64)(info, cfg, (RK_U64 *)(val))
-#define MPP_CFG_SET_St(info, cfg, val)  (mpp_cfg_ops.fp_SetSt )(info, cfg, val)
-#define MPP_CFG_GET_St(info, cfg, val)  (mpp_cfg_ops.fp_GetSt )(info, cfg, (void *)(val))
-#define MPP_CFG_SET_Ptr(info, cfg, val) (mpp_cfg_ops.fp_SetPtr)(info, cfg, val)
-#define MPP_CFG_GET_Ptr(info, cfg, val) (mpp_cfg_ops.fp_GetPtr)(info, cfg, (void **)(val))
+} MppCfgInfo;
+
+MPP_RET mpp_cfg_set_s32(MppCfgInfo *info, void *cfg, RK_S32 val);
+MPP_RET mpp_cfg_get_s32(MppCfgInfo *info, void *cfg, RK_S32 *val);
+MPP_RET mpp_cfg_set_u32(MppCfgInfo *info, void *cfg, RK_U32 val);
+MPP_RET mpp_cfg_get_u32(MppCfgInfo *info, void *cfg, RK_U32 *val);
+MPP_RET mpp_cfg_set_s64(MppCfgInfo *info, void *cfg, RK_S64 val);
+MPP_RET mpp_cfg_get_s64(MppCfgInfo *info, void *cfg, RK_S64 *val);
+MPP_RET mpp_cfg_set_u64(MppCfgInfo *info, void *cfg, RK_U64 val);
+MPP_RET mpp_cfg_get_u64(MppCfgInfo *info, void *cfg, RK_U64 *val);
+MPP_RET mpp_cfg_set_st(MppCfgInfo *info, void *cfg, void *val);
+MPP_RET mpp_cfg_get_st(MppCfgInfo *info, void *cfg, void *val);
+MPP_RET mpp_cfg_set_ptr(MppCfgInfo *info, void *cfg, void *val);
+MPP_RET mpp_cfg_get_ptr(MppCfgInfo *info, void *cfg, void **val);
+
+#define MPP_CFG_SET_S32(info, cfg, val) (mpp_cfg_set_s32)(info, cfg, val)
+#define MPP_CFG_GET_S32(info, cfg, val) (mpp_cfg_get_s32)(info, cfg, (RK_S32 *)(val))
+#define MPP_CFG_SET_U32(info, cfg, val) (mpp_cfg_set_u32)(info, cfg, val)
+#define MPP_CFG_GET_U32(info, cfg, val) (mpp_cfg_get_u32)(info, cfg, (RK_U32 *)(val))
+#define MPP_CFG_SET_S64(info, cfg, val) (mpp_cfg_set_s64)(info, cfg, val)
+#define MPP_CFG_GET_S64(info, cfg, val) (mpp_cfg_get_s64)(info, cfg, (RK_S64 *)(val))
+#define MPP_CFG_SET_U64(info, cfg, val) (mpp_cfg_set_u64)(info, cfg, val)
+#define MPP_CFG_GET_U64(info, cfg, val) (mpp_cfg_get_u64)(info, cfg, (RK_U64 *)(val))
+#define MPP_CFG_SET_St(info, cfg, val)  (mpp_cfg_set_st )(info, cfg, val)
+#define MPP_CFG_GET_St(info, cfg, val)  (mpp_cfg_get_st )(info, cfg, (void *)(val))
+#define MPP_CFG_SET_Ptr(info, cfg, val) (mpp_cfg_set_ptr)(info, cfg, val)
+#define MPP_CFG_GET_Ptr(info, cfg, val) (mpp_cfg_get_ptr)(info, cfg, (void **)(val))
 
 /* header size 128 byte */
 typedef struct MppCfgInfoHead_t {
-    char            version[112];
+    char            version[116];
     RK_S32          info_size;
     RK_S32          info_count;
     RK_S32          node_count;
-    RK_S32          cfg_size;
 } MppCfgInfoHead;
 
-typedef struct MppCfgOps_t {
-    CfgSetS32       fp_SetS32;
-    CfgGetS32       fp_GetS32;
-    CfgSetU32       fp_SetU32;
-    CfgGetU32       fp_GetU32;
-    CfgSetS64       fp_SetS64;
-    CfgGetS64       fp_GetS64;
-    CfgSetU64       fp_SetU64;
-    CfgGetU64       fp_GetU64;
-    CfgSetSt        fp_SetSt;
-    CfgGetSt        fp_GetSt;
-    CfgSetPtr       fp_SetPtr;
-    CfgGetPtr       fp_GetPtr;
-} MppCfgOps;
-
 #ifdef  __cplusplus
 extern "C" {
 #endif
 
-extern const char *cfg_type_names[];
-
-extern MppCfgOps mpp_cfg_ops;
-MPP_RET mpp_cfg_node_fixup_func(MppCfgInfoNode *node);
+const char *strof_cfg_type(CfgType type);
 
 #define CHECK_CFG_INFO(node, name, type) \
     check_cfg_info(node, name, type, __FUNCTION__)
 
-MPP_RET check_cfg_info(MppCfgInfoNode *node, const char *name, CfgType type,
+MPP_RET check_cfg_info(MppCfgInfo *node, const char *name, CfgType type,
                        const char *func);
 
 #ifdef  __cplusplus
diff --git a/mpp/inc/mpp_dec_cfg.h b/mpp/inc/mpp_dec_cfg.h
index bb54aec43..4766ab18c 100644
--- a/mpp/inc/mpp_dec_cfg.h
+++ b/mpp/inc/mpp_dec_cfg.h
@@ -21,33 +21,35 @@
 #include "rk_vdec_cmd.h"
 
 typedef enum MppDecCfgChange_e {
-    MPP_DEC_CFG_CHANGE_TYPE             = (1 << 0),
-    MPP_DEC_CFG_CHANGE_CODING           = (1 << 1),
-    MPP_DEC_CFG_CHANGE_HW_TYPE          = (1 << 2),
-    MPP_DEC_CFG_CHANGE_BATCH_MODE       = (1 << 3),
-
-    MPP_DEC_CFG_CHANGE_OUTPUT_FORMAT    = (1 << 8),
-    MPP_DEC_CFG_CHANGE_FAST_OUT         = (1 << 9),
-    MPP_DEC_CFG_CHANGE_FAST_PARSE       = (1 << 10),
-    MPP_DEC_CFG_CHANGE_SPLIT_PARSE      = (1 << 11),
-    MPP_DEC_CFG_CHANGE_INTERNAL_PTS     = (1 << 12),
-    MPP_DEC_CFG_CHANGE_SORT_PTS         = (1 << 13),
-    MPP_DEC_CFG_CHANGE_DISABLE_ERROR    = (1 << 14),
-    MPP_DEC_CFG_CHANGE_ENABLE_VPROC     = (1 << 15),
-    MPP_DEC_CFG_CHANGE_ENABLE_FAST_PLAY = (1 << 16),
-    MPP_DEC_CFG_CHANGE_ENABLE_HDR_META  = (1 << 17),
-    MPP_DEC_CFG_CHANGE_ENABLE_THUMBNAIL = (1 << 18),
-    MPP_DEC_CFG_CHANGE_ENABLE_MVC       = (1 << 19),
+    MPP_DEC_CFG_CHANGE_TYPE              = (1 << 0),
+    MPP_DEC_CFG_CHANGE_CODING            = (1 << 1),
+    MPP_DEC_CFG_CHANGE_HW_TYPE           = (1 << 2),
+    MPP_DEC_CFG_CHANGE_BATCH_MODE        = (1 << 3),
+
+    MPP_DEC_CFG_CHANGE_OUTPUT_FORMAT     = (1 << 8),
+    MPP_DEC_CFG_CHANGE_FAST_OUT          = (1 << 9),
+    MPP_DEC_CFG_CHANGE_FAST_PARSE        = (1 << 10),
+    MPP_DEC_CFG_CHANGE_SPLIT_PARSE       = (1 << 11),
+    MPP_DEC_CFG_CHANGE_INTERNAL_PTS      = (1 << 12),
+    MPP_DEC_CFG_CHANGE_SORT_PTS          = (1 << 13),
+    MPP_DEC_CFG_CHANGE_DISABLE_ERROR     = (1 << 14),
+    MPP_DEC_CFG_CHANGE_ENABLE_VPROC      = (1 << 15),
+    MPP_DEC_CFG_CHANGE_ENABLE_FAST_PLAY  = (1 << 16),
+    MPP_DEC_CFG_CHANGE_ENABLE_HDR_META   = (1 << 17),
+    MPP_DEC_CFG_CHANGE_ENABLE_THUMBNAIL  = (1 << 18),
+    MPP_DEC_CFG_CHANGE_ENABLE_MVC        = (1 << 19),
+    /* disable dpb discontinuous check */
+    MPP_DEC_CFG_CHANGE_DISABLE_DPB_CHECK = (1 << 20),
     /* reserve high bit for global config */
-    MPP_DEC_CFG_CHANGE_DISABLE_THREAD   = (1 << 28),
+    MPP_DEC_CFG_CHANGE_DISABLE_THREAD    = (1 << 28),
 
-    MPP_DEC_CFG_CHANGE_ALL              = (0xFFFFFFFF),
+    MPP_DEC_CFG_CHANGE_ALL               = (0xFFFFFFFF),
 } MppDecCfgChange;
 
 typedef enum MppVprocMode_e {
-    MPP_VPROC_MODE_DEINTELACE           = (1 << 0),
-    MPP_VPROC_MODE_DETECTION            = (1 << 1),
-    MPP_VPROC_MODE_ALL                  = (0xFFFFFFFF),
+    MPP_VPROC_MODE_DEINTELACE            = (1 << 0),
+    MPP_VPROC_MODE_DETECTION             = (1 << 1),
+    MPP_VPROC_MODE_ALL                   = (0xFFFFFFFF),
 } MppVprocMode;
 
 typedef enum FastPlayMode_e {
@@ -77,6 +79,7 @@ typedef struct MppDecBaseCfg_t {
     RK_U32              enable_hdr_meta;
     RK_U32              enable_thumbnail;
     RK_U32              enable_mvc;
+    RK_U32              disable_dpb_chk;
     RK_U32              disable_thread;
 } MppDecBaseCfg;
 
diff --git a/mpp/legacy/vpu_api.cpp b/mpp/legacy/vpu_api.cpp
index 4aaf31b93..8ffee9500 100644
--- a/mpp/legacy/vpu_api.cpp
+++ b/mpp/legacy/vpu_api.cpp
@@ -93,7 +93,7 @@ static RK_S32 vpu_api_getframe(VpuCodecContext *ctx, DecoderOut_t *aDecOut)
         return VPU_API_ERR_UNKNOW;
     }
 
-    return api->decode_getoutframe(aDecOut);
+    return api->decode_getoutframe(ctx, aDecOut);
 }
 
 static RK_S32
@@ -319,7 +319,7 @@ RK_S32 vpu_open_context(VpuCodecContext **ctx)
         if (s->videoCoding == OMX_RK_VIDEO_CodingAVC
             && s->codecType == CODEC_DECODER && s->width <= 1920
             && s->height <= 1088 && !s->extra_cfg.mpp_mode
-            && !strstr(mpp_get_soc_name(), "rk3399")) {
+            && mpp_get_soc_type() != ROCKCHIP_SOC_RK3399) {
             /* H.264 smaller than 1080p use original vpuapi library for better error process */
             // NOTE: rk3399 need better performance
             use_mpp = 0;
diff --git a/mpp/legacy/vpu_api_legacy.cpp b/mpp/legacy/vpu_api_legacy.cpp
index ff69f44d6..7437e3371 100644
--- a/mpp/legacy/vpu_api_legacy.cpp
+++ b/mpp/legacy/vpu_api_legacy.cpp
@@ -44,6 +44,9 @@ static MppFrameFormat vpu_pic_type_remap_to_mpp(EncInputPictureType type)
     case ENC_INPUT_YUV420_SEMIPLANAR : {
         ret = MPP_FMT_YUV420SP;
     } break;
+    case ENC_INPUT_YUV420_SEMIPLANAR_VU : {
+        ret = MPP_FMT_YUV420SP_VU;
+    } break;
     case ENC_INPUT_YUV422_INTERLEAVED_YUYV : {
         ret = MPP_FMT_YUV422_YUYV;
     } break;
@@ -69,10 +72,10 @@ static MppFrameFormat vpu_pic_type_remap_to_mpp(EncInputPictureType type)
         ret = MPP_FMT_BGR444;
     } break;
     case ENC_INPUT_RGB888 : {
-        ret = MPP_FMT_RGBA8888;
+        ret = MPP_FMT_RGB888;
     } break;
     case ENC_INPUT_BGR888 : {
-        ret = MPP_FMT_BGRA8888;
+        ret = MPP_FMT_BGR888;
     } break;
     case ENC_INPUT_RGB101010 : {
         ret = MPP_FMT_RGB101010;
@@ -134,6 +137,10 @@ static MPP_RET vpu_api_set_enc_cfg(MppCtx mpp_ctx, MppApi *mpi, MppEncCfg enc_cf
     case MPP_FMT_BGR555: {
         mpp_enc_cfg_set_s32(enc_cfg, "prep:hor_stride", 2 * MPP_ALIGN(width, 16));
     } break;
+    case MPP_FMT_RGB888 :
+    case MPP_FMT_BGR888 : {
+        mpp_enc_cfg_set_s32(enc_cfg, "prep:hor_stride", 3 * MPP_ALIGN(width, 16));
+    } break;
     case MPP_FMT_ARGB8888 :
     case MPP_FMT_ABGR8888 :
     case MPP_FMT_BGRA8888 :
@@ -154,10 +161,10 @@ static MPP_RET vpu_api_set_enc_cfg(MppCtx mpp_ctx, MppApi *mpi, MppEncCfg enc_cf
     mpp_enc_cfg_set_s32(enc_cfg, "rc:bps_min", rc_mode ? bps * 15 / 16 : bps * 1 / 16);
     mpp_enc_cfg_set_s32(enc_cfg, "rc:fps_in_flex", 0);
     mpp_enc_cfg_set_s32(enc_cfg, "rc:fps_in_num", fps_in);
-    mpp_enc_cfg_set_s32(enc_cfg, "rc:fps_in_denorm", 1);
+    mpp_enc_cfg_set_s32(enc_cfg, "rc:fps_in_denom", 1);
     mpp_enc_cfg_set_s32(enc_cfg, "rc:fps_out_flex", 0);
     mpp_enc_cfg_set_s32(enc_cfg, "rc:fps_out_num", fps_out);
-    mpp_enc_cfg_set_s32(enc_cfg, "rc:fps_out_denorm", 1);
+    mpp_enc_cfg_set_s32(enc_cfg, "rc:fps_out_denom", 1);
     mpp_enc_cfg_set_s32(enc_cfg, "rc:gop", gop);
 
     mpp_enc_cfg_set_s32(enc_cfg, "codec:type", coding);
@@ -227,7 +234,8 @@ static int copy_align_raw_buffer_to_dest(RK_U8 *dst, RK_U8 *src, RK_U32 width,
     RK_U8 *dst_v = dst_u + hor_stride * ver_stride / 4;
 
     switch (fmt) {
-    case MPP_FMT_YUV420SP : {
+    case MPP_FMT_YUV420SP :
+    case MPP_FMT_YUV420SP_VU : {
         for (row = 0; row < height; row++) {
             memcpy(dst_buf + row * hor_stride, src_buf + index, width);
             index += width;
@@ -251,8 +259,16 @@ static int copy_align_raw_buffer_to_dest(RK_U8 *dst, RK_U8 *src, RK_U32 width,
             index += width / 2;
         }
     } break;
+    case MPP_FMT_RGB888 :
+    case MPP_FMT_BGR888 : {
+        for (row = 0; row < height; row++) {
+            memcpy(dst_buf + row * hor_stride * 3, src_buf + row * width * 3, width * 3);
+        }
+    } break;
     case MPP_FMT_ABGR8888 :
-    case MPP_FMT_ARGB8888 : {
+    case MPP_FMT_ARGB8888 :
+    case MPP_FMT_BGRA8888 :
+    case MPP_FMT_RGBA8888 : {
         for (row = 0; row < height; row++) {
             memcpy(dst_buf + row * hor_stride * 4, src_buf + row * width * 4, width * 4);
         }
@@ -511,7 +527,7 @@ RK_S32 VpuApiLegacy::flush(VpuCodecContext *ctx)
     return 0;
 }
 
-static void setup_VPU_FRAME_from_mpp_frame(VPU_FRAME *vframe, MppFrame mframe)
+static void setup_VPU_FRAME_from_mpp_frame(VpuCodecContext *ctx, VPU_FRAME *vframe, MppFrame mframe)
 {
     MppBuffer buf = mpp_frame_get_buffer(mframe);
     RK_U64 pts  = mpp_frame_get_pts(mframe);
@@ -525,6 +541,7 @@ static void setup_VPU_FRAME_from_mpp_frame(VPU_FRAME *vframe, MppFrame mframe)
     if (buf)
         mpp_buffer_inc_ref(buf);
 
+    vframe->CodingType = ctx->videoCoding;
     vframe->DisplayWidth = mpp_frame_get_width(mframe);
     vframe->DisplayHeight = mpp_frame_get_height(mframe);
     vframe->FrameWidth = mpp_frame_get_hor_stride(mframe);
@@ -568,6 +585,10 @@ static void setup_VPU_FRAME_from_mpp_frame(VPU_FRAME *vframe, MppFrame mframe)
         vframe->ColorType |= VPU_OUTPUT_FORMAT_BIT_10;
         vframe->OutputWidth = 0x23;
     } break;
+    case MPP_FMT_YUV444SP: {
+        vframe->ColorType = VPU_OUTPUT_FORMAT_YUV444;
+        vframe->OutputWidth = 0x11;
+    } break;
     default: {
     } break;
     }
@@ -612,7 +633,7 @@ static void setup_VPU_FRAME_from_mpp_frame(VPU_FRAME *vframe, MppFrame mframe)
 
 static void setup_video_frame_meta(VideoFrame_t *videoFrame, MppFrame mframe)
 {
-    if (mpp_frame_get_thumbnail_en(mframe)) {
+    if (mpp_frame_get_thumbnail_en(mframe) == MPP_FRAME_THUMBNAIL_MIXED) {
         MppMeta meta = NULL;
         RK_S32 yOffset = 0;
         RK_S32 uvOffset = 0;
@@ -867,7 +888,7 @@ RK_S32 VpuApiLegacy::decode(VpuCodecContext *ctx, VideoPacket_t *pkt, DecoderOut
                 aDecOut->size = sizeof(VPU_FRAME);
             }
 
-            setup_VPU_FRAME_from_mpp_frame(vframe, mframe);
+            setup_VPU_FRAME_from_mpp_frame(ctx, vframe, mframe);
 
             aDecOut->timeUs = mpp_frame_get_pts(mframe);
             frame_count++;
@@ -943,7 +964,7 @@ RK_S32 VpuApiLegacy::decode_sendstream(VideoPacket_t *pkt)
     return MPP_OK;
 }
 
-RK_S32 VpuApiLegacy::decode_getoutframe(DecoderOut_t *aDecOut)
+RK_S32 VpuApiLegacy::decode_getoutframe(VpuCodecContext *ctx, DecoderOut_t *aDecOut)
 {
     RK_S32 ret = 0;
     VPU_FRAME *vframe = NULL;
@@ -984,7 +1005,7 @@ RK_S32 VpuApiLegacy::decode_getoutframe(DecoderOut_t *aDecOut)
             aDecOut->size = sizeof(VPU_FRAME);
         }
 
-        setup_VPU_FRAME_from_mpp_frame(vframe, mframe);
+        setup_VPU_FRAME_from_mpp_frame(ctx, vframe, mframe);
 
         aDecOut->timeUs = mpp_frame_get_pts(mframe);
         frame_count++;
@@ -1075,6 +1096,10 @@ RK_S32 VpuApiLegacy::encode(VpuCodecContext *ctx, EncInputStream_t *aEncInStrm,
     case MPP_FMT_BGR555: {
         mpp_frame_set_hor_stride(frame, hor_stride * 2);
     } break;
+    case MPP_FMT_RGB888 :
+    case MPP_FMT_BGR888 : {
+        mpp_frame_set_hor_stride(frame, hor_stride * 3);
+    } break;
     case MPP_FMT_ARGB8888 :
     case MPP_FMT_ABGR8888 :
     case MPP_FMT_BGRA8888 :
@@ -1085,6 +1110,11 @@ RK_S32 VpuApiLegacy::encode(VpuCodecContext *ctx, EncInputStream_t *aEncInStrm,
         mpp_err("unsupport format 0x%x\n", format & MPP_FRAME_FMT_MASK);
     } break;
     }
+    mpp_frame_set_fmt(frame, (MppFrameFormat)(format & MPP_FRAME_FMT_MASK));
+    if (aEncInStrm->nFlags) {
+        mpp_log_f("found eos\n");
+        mpp_frame_set_eos(frame, 1);
+    }
 
     fd = aEncInStrm->bufPhyAddr;
     if (fd_input < 0) {
@@ -1330,6 +1360,10 @@ RK_S32 VpuApiLegacy::encoder_sendframe(VpuCodecContext *ctx, EncInputStream_t *a
     case MPP_FMT_BGR555: {
         mpp_frame_set_hor_stride(frame, hor_stride * 2);
     } break;
+    case MPP_FMT_RGB888 :
+    case MPP_FMT_BGR888 : {
+        mpp_frame_set_hor_stride(frame, hor_stride * 3);
+    } break;
     case MPP_FMT_ARGB8888 :
     case MPP_FMT_ABGR8888 :
     case MPP_FMT_BGRA8888 :
@@ -1340,7 +1374,7 @@ RK_S32 VpuApiLegacy::encoder_sendframe(VpuCodecContext *ctx, EncInputStream_t *a
         mpp_err("unsupport format 0x%x\n", format & MPP_FRAME_FMT_MASK);
     } break;
     }
-
+    mpp_frame_set_fmt(frame, (MppFrameFormat)(format & MPP_FRAME_FMT_MASK));
     if (aEncInStrm->nFlags) {
         mpp_log_f("found eos true\n");
         mpp_frame_set_eos(frame, 1);
@@ -1383,6 +1417,8 @@ RK_S32 VpuApiLegacy::encoder_sendframe(VpuCodecContext *ctx, EncInputStream_t *a
         }
         if (format >= MPP_FMT_YUV420SP && format < MPP_FMT_YUV_BUTT) {
             align_size = hor_stride * MPP_ALIGN(ver_stride, 16) * 3 / 2;
+        } else  if (format >= MPP_FMT_YUV420SP_VU && format < MPP_FMT_YUV_BUTT) {
+            align_size = hor_stride * MPP_ALIGN(ver_stride, 16) * 3 / 2;
         } else if (format >= MPP_FMT_RGB565 && format < MPP_FMT_BGR888) {
             align_size = hor_stride * MPP_ALIGN(ver_stride, 16) * 3;
         } else if (format >= MPP_FMT_RGB101010 && format < MPP_FMT_RGB_BUTT) {
@@ -1680,6 +1716,9 @@ RK_S32 VpuApiLegacy::control(VpuCodecContext *ctx, VPU_API_CMD cmd, void *param)
         mpp_dec_cfg_deinit(cfg);
         return ret;
     } break;
+    case VPU_API_SET_DISABLE_ERROR: {
+        mpicmd = MPP_DEC_SET_DISABLE_ERROR;
+    } break;
     case VPU_API_SET_IMMEDIATE_OUT: {
         mpicmd = MPP_DEC_SET_IMMEDIATE_OUT;
     } break;
diff --git a/mpp/legacy/vpu_api_legacy.h b/mpp/legacy/vpu_api_legacy.h
index 7be752cd8..43a1e4569 100644
--- a/mpp/legacy/vpu_api_legacy.h
+++ b/mpp/legacy/vpu_api_legacy.h
@@ -57,7 +57,7 @@ class VpuApiLegacy
 
     RK_S32 decode(VpuCodecContext *ctx, VideoPacket_t *pkt, DecoderOut_t *aDecOut);
     RK_S32 decode_sendstream(VideoPacket_t *pkt);
-    RK_S32 decode_getoutframe(DecoderOut_t *aDecOut);
+    RK_S32 decode_getoutframe(VpuCodecContext *ctx, DecoderOut_t *aDecOut);
     RK_S32 preProcessPacket(VpuCodecContext *ctx, VideoPacket_t *pkt);
 
     RK_S32 encode(VpuCodecContext *ctx, EncInputStream_t *aEncInStrm, EncoderOut_t *aEncOut);
diff --git a/mpp/mpp.cpp b/mpp/mpp.cpp
index 11727bec2..1e8a5bece 100644
--- a/mpp/mpp.cpp
+++ b/mpp/mpp.cpp
@@ -50,6 +50,18 @@ static void mpp_notify_by_buffer_group(void *arg, void *group)
 
 static void *list_wraper_packet(void *arg)
 {
+    MppPacket packet = *(MppPacket*)arg;
+
+    if (mpp_packet_has_meta(packet)) {
+        MppMeta meta = mpp_packet_get_meta(packet);
+        MppFrame frm = NULL;
+
+        if (MPP_OK == mpp_meta_get_frame(meta, KEY_INPUT_FRAME, &frm)) {
+            mpp_assert(frm);
+            mpp_frame_deinit(&frm);
+        }
+    }
+
     mpp_packet_deinit((MppPacket *)arg);
     return NULL;
 }
@@ -62,15 +74,16 @@ static void *list_wraper_frame(void *arg)
 
 static RK_S32 check_frm_task_cnt_cap(MppCodingType coding)
 {
-    if (strstr(mpp_get_soc_name(), "rk3588")) {
+    RockchipSocType soc_type = mpp_get_soc_type();
+
+    if (soc_type == ROCKCHIP_SOC_RK3588 || soc_type == ROCKCHIP_SOC_RK3576) {
         if (coding == MPP_VIDEO_CodingAVC || coding == MPP_VIDEO_CodingHEVC)
             return 2;
-
-        if (coding == MPP_VIDEO_CodingMJPEG)
+        if (coding == MPP_VIDEO_CodingMJPEG && soc_type == ROCKCHIP_SOC_RK3588)
             return 4;
     }
 
-    mpp_log("Only rk3588 h264/jpeg encoder can use frame parallel\n");
+    mpp_log("Only rk3588's h264/265/jpeg and rk3576's h264/265 encoder can use frame parallel\n");
 
     return 1;
 }
@@ -195,10 +208,8 @@ MPP_RET Mpp::init(MppCtxType type, MppCodingType coding)
     case MPP_CTX_ENC : {
         RK_S32 input_task_count = 1;
 
-        mPktIn  = new mpp_list(list_wraper_packet);
         mPktOut = new mpp_list(list_wraper_packet);
-        mFrmIn  = new mpp_list(NULL);
-        mFrmOut = new mpp_list(NULL);
+        mFrmIn  = new mpp_list(list_wraper_frame);
 
         if (mInputTimeout == MPP_POLL_BUTT)
             mInputTimeout = MPP_POLL_BLOCK;
@@ -565,8 +576,12 @@ MPP_RET Mpp::decode(MppPacket packet, MppFrame *frame)
         AutoMutex autoFrameLock(mFrmOut->mutex());
 
         if (mFrmOut->list_size()) {
+            MppBuffer buffer;
+
             mFrmOut->del_at_head(frame, sizeof(*frame));
-            mpp_buffer_sync_ro_begin(mpp_frame_get_buffer(*frame));
+            buffer = mpp_frame_get_buffer(*frame);
+            if (buffer)
+                mpp_buffer_sync_ro_begin(buffer);
             mFrameGetCount++;
             return MPP_OK;
         }
@@ -585,8 +600,12 @@ MPP_RET Mpp::decode(MppPacket packet, MppFrame *frame)
             AutoMutex autoFrameLock(mFrmOut->mutex());
 
             if (mFrmOut->list_size()) {
+                MppBuffer buffer;
+
                 mFrmOut->del_at_head(frame, sizeof(*frame));
-                mpp_buffer_sync_ro_begin(mpp_frame_get_buffer(*frame));
+                buffer = mpp_frame_get_buffer(*frame);
+                if (buffer)
+                    mpp_buffer_sync_ro_begin(buffer);
                 mFrameGetCount++;
                 frm_rdy = 1;
             }
@@ -620,6 +639,8 @@ MPP_RET Mpp::put_frame(MppFrame frame)
     if (!mInitDone)
         return MPP_ERR_INIT;
 
+    mpp_dbg_pts("%p input frame pts %lld\n", this, mpp_frame_get_pts(frame));
+
     if (mInputTimeout == MPP_POLL_NON_BLOCK) {
         set_io_mode(MPP_IO_MODE_NORMAL);
         return put_frame_async(frame);
@@ -778,7 +799,7 @@ MPP_RET Mpp::get_packet(MppPacket *packet)
 
         mpp_buffer_sync_ro_partial_begin(buf, offset, impl->length);
 
-        mpp_dbg_pts("pts %lld\n", impl->pts);
+        mpp_dbg_pts("%p output packet pts %lld\n", this, impl->pts);
     }
 
     // dump output
@@ -842,12 +863,18 @@ MPP_RET Mpp::get_packet_async(MppPacket *packet)
 
     if (mPktOut->list_size()) {
         MppPacket pkt = NULL;
+        MppPacketImpl *impl = NULL;
+        RK_U32 offset;
 
         mPktOut->del_at_head(&pkt, sizeof(pkt));
         mPacketGetCount++;
         notify(MPP_OUTPUT_DEQUEUE);
 
         *packet = pkt;
+
+        impl = (MppPacketImpl *)pkt;
+        offset = (RK_U32)((char *)impl->pos - (char *)impl->data);
+        mpp_buffer_sync_ro_partial_begin(impl->buffer, offset, impl->length);
     } else {
         AutoMutex autoFrameLock(mFrmIn->mutex());
 
@@ -1169,6 +1196,7 @@ MPP_RET Mpp::control_dec(MpiCmd cmd, MppParam param)
     MPP_RET ret = MPP_NOK;
 
     switch (cmd) {
+    case MPP_DEC_GET_THUMBNAIL_FRAME_INFO:
     case MPP_DEC_SET_FRAME_INFO: {
         ret = mpp_dec_control(mDec, cmd, param);
     } break;
@@ -1242,7 +1270,8 @@ MPP_RET Mpp::control_dec(MpiCmd cmd, MppParam param)
     case MPP_DEC_SET_DISABLE_ERROR :
     case MPP_DEC_SET_ENABLE_DEINTERLACE :
     case MPP_DEC_SET_ENABLE_FAST_PLAY :
-    case MPP_DEC_SET_ENABLE_MVC: {
+    case MPP_DEC_SET_ENABLE_MVC :
+    case MPP_DEC_SET_DISABLE_DPB_CHECK: {
         /*
          * These control may be set before mpp_init
          * When this case happen record the config and wait for decoder init
diff --git a/mpp/mpp_impl.cpp b/mpp/mpp_impl.cpp
index 85c6391a5..e4b17c550 100644
--- a/mpp/mpp_impl.cpp
+++ b/mpp/mpp_impl.cpp
@@ -150,6 +150,21 @@ static RK_U8 fetch_data(RK_U32 fmt, RK_U8 *line, RK_U32 num)
     return RK_U8(value);
 }
 
+static void rearrange_pix(RK_U8 *tmp_line, RK_U8 *base, RK_U32 n)
+{
+    RK_U16 * pix = (RK_U16 *)(tmp_line + n * 16);
+    RK_U16 * base_u16 = (RK_U16 *)(base + n * 10);
+
+    pix[0] =  base_u16[0] & 0x03FF;
+    pix[1] = (base_u16[0] & 0xFC00) >> 10 | (base_u16[1] & 0x000F) << 6;
+    pix[2] = (base_u16[1] & 0x3FF0) >> 4;
+    pix[3] = (base_u16[1] & 0xC000) >> 14 | (base_u16[2] & 0x00FF) << 2;
+    pix[4] = (base_u16[2] & 0xFF00) >> 8  | (base_u16[3] & 0x0003) << 8;
+    pix[5] = (base_u16[3] & 0x0FFC) >> 2;
+    pix[6] = (base_u16[3] & 0xF000) >> 12 | (base_u16[4] & 0x003F) << 4;
+    pix[7] = (base_u16[4] & 0xFFC0) >> 6;
+}
+
 static void dump_frame(FILE *fp, MppFrame frame, RK_U8 *tmp, RK_U32 w, RK_U32 h)
 {
     RK_U32 i = 0, j = 0;
@@ -221,12 +236,36 @@ static void dump_frame(FILE *fp, MppFrame frame, RK_U8 *tmp, RK_U32 w, RK_U32 h)
         case MPP_FMT_YUV444SP : {
             size = hor_stride * ver_stride * 3;
         } break;
+        case MPP_FMT_YUV420SP_10BIT : {
+            RK_U8 *base_y = p_buf;
+            RK_U8 *base_c = p_buf + hor_stride * ver_stride;
+            RK_U8 *tmp_line = (RK_U8 *)mpp_malloc(RK_U16, width);
+
+            if (!tmp_line) {
+                mpp_log("tmp_line malloc fail");
+                return;
+            }
+
+            for (i = 0; i < height; i++, base_y += hor_stride) {
+                for (j = 0; j < MPP_ALIGN(width, 8) / 8; j++)
+                    rearrange_pix(tmp_line, base_y, j);
+                fwrite(tmp_line, width * sizeof(RK_U16), 1, fp);
+            }
+
+            for (i = 0; i < height / 2; i++, base_c += hor_stride) {
+                for (j = 0; j < MPP_ALIGN(width, 8) / 8; j++)
+                    rearrange_pix(tmp_line, base_c, j);
+                fwrite(tmp_line, width * sizeof(RK_U16), 1, fp);
+            }
+            MPP_FREE(tmp_line);
+        }
         default : break;
         }
     }
     mpp_log("dump_yuv: w:h [%d:%d] stride [%d:%d] pts %lld\n",
             width, height, hor_stride, ver_stride, mpp_frame_get_pts(frame));
-    fwrite(tmp, 1, size, fp);
+    if (size)
+        fwrite(tmp, 1, size, fp);
     fflush(fp);
 }
 
diff --git a/mpp/vproc.cmake b/mpp/vproc.cmake
index ff352e6d2..dd4ef6c77 100644
--- a/mpp/vproc.cmake
+++ b/mpp/vproc.cmake
@@ -3,3 +3,10 @@ if( ENABLE_VPROC )
     set(HAVE_VPROC true)
     add_definitions(-DHAVE_VPROC)
 endif()
+
+option(ENABLE_VPROC_VDPP "Enable video display post processor" OFF)
+if( ENABLE_VPROC_VDPP )
+    set(HAVE_VPROC_VDPP true)
+    set(VPROC_VDPP vproc_vdpp)
+    add_definitions(-DHAVE_VPROC_VDPP)
+endif()
diff --git a/mpp/vproc/CMakeLists.txt b/mpp/vproc/CMakeLists.txt
index 5004ad2d3..f860067bc 100644
--- a/mpp/vproc/CMakeLists.txt
+++ b/mpp/vproc/CMakeLists.txt
@@ -4,8 +4,9 @@
 # add mpp video process implement
 # ----------------------------------------------------------------------------
 add_library(mpp_vproc STATIC mpp_dec_vproc.cpp mpp_vproc_dev.cpp)
-target_link_libraries(mpp_vproc vproc_rga vproc_iep vproc_iep2 mpp_base)
+target_link_libraries(mpp_vproc vproc_rga vproc_iep vproc_iep2 ${VPROC_VDPP} mpp_base)
 
 add_subdirectory(rga)
 add_subdirectory(iep)
 add_subdirectory(iep2)
+add_subdirectory(vdpp)
\ No newline at end of file
diff --git a/mpp/vproc/iep2/test/iep2_test.c b/mpp/vproc/iep2/test/iep2_test.c
index 92560d1d6..286cea642 100644
--- a/mpp/vproc/iep2/test/iep2_test.c
+++ b/mpp/vproc/iep2/test/iep2_test.c
@@ -217,8 +217,6 @@ void iep2_test(iep2_test_cfg *cfg)
     IepImg imgsrc[3];
     IepImg imgdst[2];
 
-    int idx = 0;
-
     mpp_assert(iep2);
     MppBufferGroup memGroup;
     MPP_RET ret = mpp_buffer_group_get_internal(&memGroup, MPP_BUFFER_TYPE_DRM);
@@ -346,7 +344,6 @@ void iep2_test(iep2_test_cfg *cfg)
         }
 
         curr++;
-        idx++;
     }
 
 ret:
diff --git a/mpp/vproc/inc/hwpq_vdpp_proc_api.h b/mpp/vproc/inc/hwpq_vdpp_proc_api.h
new file mode 100644
index 000000000..e3dba6152
--- /dev/null
+++ b/mpp/vproc/inc/hwpq_vdpp_proc_api.h
@@ -0,0 +1,144 @@
+/* SPDX-License-Identifier: Apache-2.0 OR MIT */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef __HWPQ_VDPP_PROC_API_H__
+#define __HWPQ_VDPP_PROC_API_H__
+
+typedef void* rk_vdpp_context;
+
+/* hwpq vdpp color format definition */
+#define VDPP_FRAME_FMT_COLOR_MASK    (0x000f0000)
+#define VDPP_FRAME_FMT_YUV           (0x00000000)
+#define VDPP_FRAME_FMT_RGB           (0x00010000)
+
+typedef enum {
+    // YUV
+    VDPP_FMT_YUV_MIN = 0,   /* the min YUV format value, please DO NOT use this item! */
+    VDPP_FMT_NV24 = 0,      /* YUV444SP, 2 plane YCbCr, 24bpp/8 bpc, non-subsampled Cr:Cb plane */
+    VDPP_FMT_NV16,          /* YUV422SP, 2 plane YCbCr, 16bpp/8 bpc, 2x1 subsampled Cr:Cb plane */
+    VDPP_FMT_NV12,          /* YUV420SP, 2 plane YCbCr, 12bpp/8 bpc, 2x2 subsampled Cr:Cb plane */
+    VDPP_FMT_NV15,          /* YUV420SP, 2 plane YCbCr, 15bpp/10bpc, 10bit packed data */
+    VDPP_FMT_NV20,          /* YUV422SP, 2 plane YCbCr, 20bpp/10bpc, 10bit packed data, output supported only */ /* reserved */
+    VDPP_FMT_NV30,          /* YUV444SP, 2 plane YCbCr, 30bpp/10bpc, 10bit packed data, output supported only */
+    VDPP_FMT_P010,          /* YUV420SP, 2 plane YCbCr, 24bpp/16bpc, 10bit unpacked data with MSB aligned, output supported only */
+    VDPP_FMT_P210,          /* YUV422SP, 2 plane YCbCr, 32bpp/16bpc, 10bit unpacked data with MSB aligned, output supported only */ /* reserved */
+    VDPP_FMT_Q410,          /* YUV444P , 3 plane YCbCr, 48bpp/16bpc, 10bit unpacked data with MSB aligned, output supported only */
+    VDPP_FMT_Y_ONLY_8BIT,   /* Only 8bit-Y Plane, For VDPP y-uv diff mode */
+    VDPP_FMT_UV_ONLY_8BIT,  /* Only 8bit-UV Plane, For VDPP y-uv diff mode */
+    VDPP_FMT_NV24_VU,
+    VDPP_FMT_NV16_VU,
+    VDPP_FMT_NV12_VU,
+    VDPP_FMT_YUV_MAX,       /* the max YUV format value, please DO NOT use this item! */
+
+    // RGB
+    VDPP_FMT_RGB_MIN = 1000,/* the min RGB format value, please DO NOT use this item! */
+    VDPP_FMT_RGBA = 1000,   /* RGBA8888, 32bpp */
+    VDPP_FMT_RG24,          /* RGB888, 24bpp */
+    VDPP_FMT_BG24,          /* BGR888, 24bpp */
+    VDPP_FMT_AB30,          /* ABGR2101010, reserved */
+    VDPP_FMT_RGB_MAX,       /* the max RGB format value, please DO NOT use this item! */
+} vdpp_frame_format;
+
+typedef enum {
+    VDPP_RUN_MODE_UNSUPPORTED = -1,
+    VDPP_RUN_MODE_VEP         = 0,
+    VDPP_RUN_MODE_HIST        = 1,
+} VdppRunMode;
+
+#define VDPP_HIST_LENGTH        (10240)
+
+typedef struct {
+    int     fd;
+    void*   addr;
+    int     offset;
+
+    int     w_vld;
+    int     h_vld;
+    int     w_vir;
+    int     h_vir;
+} vdpp_plane_info;
+
+typedef struct {
+    vdpp_plane_info     img_yrgb;
+    vdpp_plane_info     img_cbcr;
+
+    vdpp_frame_format   img_fmt;
+} vdpp_img_info;
+
+/* vdpp module config */
+typedef struct {
+    // dmsr config
+    unsigned int dmsr_en;
+    unsigned int str_pri_y;
+    unsigned int str_sec_y;
+    unsigned int dumping_y;
+    unsigned int reserve_dmsr[4];
+
+    // es config
+    unsigned int es_en;
+    unsigned int es_iWgtGain;
+    unsigned int reserve_es[4];
+
+    // zme config
+    unsigned int zme_dering_en;
+    unsigned int reserve_zme[4];
+
+    // hist_cnt config
+    unsigned int hist_cnt_en;
+    unsigned int hist_csc_range;
+    unsigned int reserve_hist_cnt[4];
+
+    // sharp config
+    unsigned int shp_en;
+    unsigned int peaking_gain;
+    unsigned int shp_shoot_ctrl_en;
+    unsigned int shp_shoot_ctrl_over;
+    unsigned int shp_shoot_ctrl_under;
+    unsigned int reserve_shp[4];
+} vdpp_params;
+
+typedef struct {
+    void*               p_hist_addr;
+    unsigned int        hist_length;
+    unsigned short      vdpp_img_w_in;
+    unsigned short      vdpp_img_h_in;
+    unsigned short      vdpp_img_w_out;
+    unsigned short      vdpp_img_h_out;
+    unsigned short      vdpp_blk_size_h;
+    unsigned short      vdpp_blk_size_v;
+} hwpq_vdpp_info_t;
+
+typedef struct {
+    unsigned int    frame_idx;
+    unsigned int    yuv_diff_flag;
+    unsigned int    hist_mode_en;
+
+    vdpp_img_info   src_img_info;
+    vdpp_img_info   dst_img_info;
+    unsigned int    hist_buf_fd;
+    void*           p_hist_buf;
+
+    unsigned int    vdpp_config_update_flag;
+    vdpp_params     vdpp_config;
+
+    hwpq_vdpp_info_t dci_vdpp_info;
+
+} rk_vdpp_proc_params;
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+int hwpq_vdpp_init(rk_vdpp_context *p_ctx_ptr);
+int hwpq_vdpp_check_work_mode(rk_vdpp_context ctx, rk_vdpp_proc_params *p_proc_param);
+int hwpq_vdpp_proc(rk_vdpp_context ctx, rk_vdpp_proc_params *p_proc_param);
+int hwpq_vdpp_deinit(rk_vdpp_context ctx);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __HWPQ_VDPP_PROC_API_H__
\ No newline at end of file
diff --git a/mpp/vproc/inc/vdpp_api.h b/mpp/vproc/inc/vdpp_api.h
new file mode 100644
index 000000000..ee9fbf44f
--- /dev/null
+++ b/mpp/vproc/inc/vdpp_api.h
@@ -0,0 +1,376 @@
+/* SPDX-License-Identifier: Apache-2.0 OR MIT */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef __VDPP_API_H__
+#define __VDPP_API_H__
+
+#include <stdbool.h>
+
+#include "mpp_debug.h"
+#include "mpp_frame.h"
+
+#define CEIL(a)                 (int)( (double)(a) > (int)(a) ? (int)((a)+1) : (int)(a) )
+#define FLOOR(a)                (int)( (double)(a) < (int)(a) ? (int)((a)-1) : (int)(a) )
+#define ROUND(a)                (int)( (a) > 0 ? ((double) (a) + 0.5) : ((double) (a) - 0.5) )
+
+#define RKVOP_PQ_PREPROCESS_GLOBAL_HIST_BIN_BITS    (8)
+#define RKVOP_PQ_PREPROCESS_GLOBAL_HIST_BIN_NUMS    (1 << (RKVOP_PQ_PREPROCESS_GLOBAL_HIST_BIN_BITS))
+#define RKVOP_PQ_PREPROCESS_HIST_BITS_VERI          (4)
+#define RKVOP_PQ_PREPROCESS_HIST_BITS_HORI          (4)
+#define RKVOP_PQ_PREPROCESS_HIST_SIZE_VERI          (1 << RKVOP_PQ_PREPROCESS_HIST_BITS_VERI) /* 16 */
+#define RKVOP_PQ_PREPROCESS_HIST_SIZE_HORI          (1 << RKVOP_PQ_PREPROCESS_HIST_BITS_HORI) /* 16 */
+#define RKVOP_PQ_PREPROCESS_LOCAL_HIST_BIN_BITS     (4)
+#define RKVOP_PQ_PREPROCESS_LOCAL_HIST_BIN_NUMS     (1 << (RKVOP_PQ_PREPROCESS_LOCAL_HIST_BIN_BITS))
+
+#define VDPP_COLOR_SPACE_LIMIT_RANGE    (0)
+#define VDPP_COLOR_SPACE_FULL_RANGE     (1)
+
+#define VDPP_CAP_UNSUPPORTED      (0)
+#define VDPP_CAP_VEP              (1 << 0)
+#define VDPP_CAP_HIST             (1 << 1)
+
+#define VDPP_WORK_MODE_VEP        (2)
+#define VDPP_WORK_MODE_DCI        (3) /* hist mode */
+
+#define VDPP_DMSR_EN            (4)
+#define VDPP_ES_EN              (2)
+#define VDPP_SHARP_EN           (1)
+
+/* DCI horizontal scale down mode select */
+#define VDPP_DCI_HSD_DISABLE    (0)
+#define VDPP_DCI_HSD_MODE_1     (1)
+/* DCI vertical scale down mode select */
+#define VDPP_DCI_VSD_DISABLE    (0)
+#define VDPP_DCI_VSD_MODE_1     (1)
+#define VDPP_DCI_VSD_MODE_2     (2)
+
+enum VDPP_FMT {
+    VDPP_FMT_YUV444 = 0,
+    VDPP_FMT_YUV420 = 3,
+};
+
+enum VDPP_YUV_SWAP {
+    VDPP_YUV_SWAP_SP_UV,
+    VDPP_YUV_SWAP_SP_VU,
+};
+
+enum VDPP_PARAM_TYPE {
+    VDPP_PARAM_TYPE_COM,
+    VDPP_PARAM_TYPE_DMSR,
+    VDPP_PARAM_TYPE_ZME_COM,
+    VDPP_PARAM_TYPE_ZME_COEFF,
+    VDPP_PARAM_TYPE_COM2 = 0x10,
+    VDPP_PARAM_TYPE_ES,
+    VDPP_PARAM_TYPE_HIST,
+    VDPP_PARAM_TYPE_SHARP,
+};
+
+typedef enum VdppCmd_e {
+    VDPP_CMD_INIT,                            /* reset msg to all zero */
+    VDPP_CMD_SET_SRC,                         /* config source image info */
+    VDPP_CMD_SET_DST,                         /* config destination image info */
+    VDPP_CMD_SET_COM_CFG,
+    /* DMSR command */
+    VDPP_CMD_SET_DMSR_CFG         = 0x0100,   /* config DMSR configure */
+    /* ZME command */
+    VDPP_CMD_SET_ZME_COM_CFG      = 0x0200,   /* config ZME COM configure */
+    VDPP_CMD_SET_ZME_COEFF_CFG,               /* config ZME COEFF configure */
+    /* hardware trigger command */
+    VDPP_CMD_RUN_SYNC             = 0x1000,   /* start sync mode process */
+    VDPP_CMD_SET_COM2_CFG         = 0x2000,   /* config common params for RK3576 */
+    VDPP_CMD_SET_DST_C,                       /* config destination chroma info */
+    VDPP_CMD_SET_HIST_FD,                     /* config dci hist fd */
+    VDPP_CMD_SET_ES,                          /* config ES configure */
+    VDPP_CMD_SET_DCI_HIST,                    /* config dci hist configure */
+    VDPP_CMD_SET_SHARP,                       /* config sharp configure */
+} VdppCmd;
+
+typedef void* VdppCtx;
+typedef struct vdpp_com_ctx_t vdpp_com_ctx;
+
+typedef struct VdppImg_t {
+    RK_U32  mem_addr; /* base address fd */
+    RK_U32  uv_addr;  /* chroma address fd + (offset << 10) */
+    RK_U32  uv_off;
+} VdppImg;
+
+typedef struct vdpp_com_ops_t {
+    MPP_RET (*init)(VdppCtx *ctx);
+    MPP_RET (*deinit)(VdppCtx ctx);
+    MPP_RET (*control)(VdppCtx ctx, VdppCmd cmd, void *param);
+    void    (*release)(vdpp_com_ctx *ctx);
+    RK_S32  (*check_cap)(VdppCtx ctx);
+    MPP_RET (*reserve[3])(VdppCtx *ctx);
+} vdpp_com_ops;
+
+typedef struct vdpp_com_ctx_t {
+    vdpp_com_ops *ops;
+    VdppCtx priv;
+    RK_S32 ver;
+} vdpp_com_ctx;
+
+union vdpp_api_content {
+    struct {
+        enum VDPP_YUV_SWAP sswap;
+        enum VDPP_FMT dfmt;
+        enum VDPP_YUV_SWAP dswap;
+        RK_S32 src_width;
+        RK_S32 src_height;
+        RK_S32 dst_width;
+        RK_S32 dst_height;
+    } com;
+
+    struct {
+        bool enable;
+        RK_U32 str_pri_y;
+        RK_U32 str_sec_y;
+        RK_U32 dumping_y;
+        RK_U32 wgt_pri_gain_even_1;
+        RK_U32 wgt_pri_gain_even_2;
+        RK_U32 wgt_pri_gain_odd_1;
+        RK_U32 wgt_pri_gain_odd_2;
+        RK_U32 wgt_sec_gain;
+        RK_U32 blk_flat_th;
+        RK_U32 contrast_to_conf_map_x0;
+        RK_U32 contrast_to_conf_map_x1;
+        RK_U32 contrast_to_conf_map_y0;
+        RK_U32 contrast_to_conf_map_y1;
+        RK_U32 diff_core_th0;
+        RK_U32 diff_core_th1;
+        RK_U32 diff_core_wgt0;
+        RK_U32 diff_core_wgt1;
+        RK_U32 diff_core_wgt2;
+        RK_U32 edge_th_low_arr[7];
+        RK_U32 edge_th_high_arr[7];
+    } dmsr;
+
+    struct {
+        bool bypass_enable;
+        bool dering_enable;
+        RK_U32 dering_sen_0;
+        RK_U32 dering_sen_1;
+        RK_U32 dering_blend_alpha;
+        RK_U32 dering_blend_beta;
+        RK_S16 (*tap8_coeff)[17][8];
+        RK_S16 (*tap6_coeff)[17][8];
+    } zme;
+
+    struct {
+        MppFrameFormat sfmt;
+        enum VDPP_YUV_SWAP sswap;
+        enum VDPP_FMT dfmt;
+        enum VDPP_YUV_SWAP dswap;
+        RK_U32 src_width;
+        RK_U32 src_height;
+        RK_U32 src_width_vir;
+        RK_U32 src_height_vir;
+        RK_U32 dst_width;
+        RK_U32 dst_height;
+        RK_U32 dst_width_vir;
+        RK_U32 dst_height_vir;
+        RK_U32 yuv_out_diff;
+        RK_U32 dst_c_width;
+        RK_U32 dst_c_height;
+        RK_U32 dst_c_width_vir;
+        RK_U32 dst_c_height_vir;
+        RK_U32 hist_mode_en;  /* 0 - vdpp, 1 - hist */
+        /* high 16 bit: mask; low 3 bit: dmsr|es|sharp */
+        RK_U32 cfg_set;
+    } com2;
+
+    struct {
+        RK_U32 es_bEnabledES;
+        RK_U32 es_iAngleDelta;
+        RK_U32 es_iAngleDeltaExtra;
+        RK_U32 es_iGradNoDirTh;
+        RK_U32 es_iGradFlatTh;
+        RK_U32 es_iWgtGain;
+        RK_U32 es_iWgtDecay;
+        RK_U32 es_iLowConfTh;
+        RK_U32 es_iLowConfRatio;
+        RK_U32 es_iConfCntTh;
+        RK_U32 es_iWgtLocalTh;
+        RK_U32 es_iK1;
+        RK_U32 es_iK2;
+        RK_U32 es_iDeltaLimit;
+        RK_U32 es_iDiff2conf_lut_x[9];
+        RK_U32 es_iDiff2conf_lut_y[9];
+        RK_U32 es_bEndpointCheckEnable;
+        /* generated by es_iAngleDelta and es_iAngleDeltaExtra */
+        RK_U32 es_tan_hi_th;
+        RK_U32 es_tan_lo_th;
+    } es;
+
+    struct {
+        RK_U32 hist_cnt_en;
+        RK_U32 dci_hsd_mode;
+        RK_U32 dci_vsd_mode;
+        RK_U32 dci_yrgb_gather_num;
+        RK_U32 dci_yrgb_gather_en;
+        RK_U32 dci_csc_range;
+    } hist;
+
+    struct {
+        RK_S32 sharp_enable;
+        RK_S32 sharp_coloradj_bypass_en;
+
+        RK_S32 lti_h_enable;
+        RK_S32 lti_h_radius;
+        RK_S32 lti_h_slope;
+        RK_S32 lti_h_thresold;
+        RK_S32 lti_h_gain;
+        RK_S32 lti_h_noise_thr_pos;
+        RK_S32 lti_h_noise_thr_neg;
+
+        RK_S32 lti_v_enable;
+        RK_S32 lti_v_radius;
+        RK_S32 lti_v_slope;
+        RK_S32 lti_v_thresold;
+        RK_S32 lti_v_gain;
+        RK_S32 lti_v_noise_thr_pos;
+        RK_S32 lti_v_noise_thr_neg;
+
+        RK_S32 cti_h_enable;
+        RK_S32 cti_h_radius;
+        RK_S32 cti_h_slope;
+        RK_S32 cti_h_thresold;
+        RK_S32 cti_h_gain;
+        RK_S32 cti_h_noise_thr_pos;
+        RK_S32 cti_h_noise_thr_neg;
+
+        RK_S32 peaking_enable;
+        RK_S32 peaking_gain;
+
+        RK_S32 peaking_coring_enable;
+        RK_S32 peaking_coring_zero[8];
+        RK_S32 peaking_coring_thr[8];
+        RK_S32 peaking_coring_ratio[8];
+
+        RK_S32 peaking_gain_enable;
+        RK_S32 peaking_gain_pos[8];
+        RK_S32 peaking_gain_neg[8];
+
+        RK_S32 peaking_limit_ctrl_enable;
+        RK_S32 peaking_limit_ctrl_pos0[8];
+        RK_S32 peaking_limit_ctrl_pos1[8];
+        RK_S32 peaking_limit_ctrl_neg0[8];
+        RK_S32 peaking_limit_ctrl_neg1[8];
+        RK_S32 peaking_limit_ctrl_ratio[8];
+        RK_S32 peaking_limit_ctrl_bnd_pos[8];
+        RK_S32 peaking_limit_ctrl_bnd_neg[8];
+
+        RK_S32 peaking_edge_ctrl_enable;
+        RK_S32 peaking_edge_ctrl_non_dir_thr;
+        RK_S32 peaking_edge_ctrl_dir_cmp_ratio;
+        RK_S32 peaking_edge_ctrl_non_dir_wgt_offset;
+        RK_S32 peaking_edge_ctrl_non_dir_wgt_ratio;
+        RK_S32 peaking_edge_ctrl_dir_cnt_thr;
+        RK_S32 peaking_edge_ctrl_dir_cnt_avg;
+        RK_S32 peaking_edge_ctrl_dir_cnt_offset;
+        RK_S32 peaking_edge_ctrl_diag_dir_thr;
+        RK_S32 peaking_edge_ctrl_diag_adj_gain_tab[8];
+
+        RK_S32 peaking_estc_enable;
+        RK_S32 peaking_estc_delta_offset_h;
+        RK_S32 peaking_estc_alpha_over_h;
+        RK_S32 peaking_estc_alpha_under_h;
+        RK_S32 peaking_estc_alpha_over_unlimit_h;
+        RK_S32 peaking_estc_alpha_under_unlimit_h;
+        RK_S32 peaking_estc_delta_offset_v;
+        RK_S32 peaking_estc_alpha_over_v;
+        RK_S32 peaking_estc_alpha_under_v;
+        RK_S32 peaking_estc_alpha_over_unlimit_v;
+        RK_S32 peaking_estc_alpha_under_unlimit_v;
+        RK_S32 peaking_estc_delta_offset_d0;
+        RK_S32 peaking_estc_alpha_over_d0;
+        RK_S32 peaking_estc_alpha_under_d0;
+        RK_S32 peaking_estc_alpha_over_unlimit_d0;
+        RK_S32 peaking_estc_alpha_under_unlimit_d0;
+        RK_S32 peaking_estc_delta_offset_d1;
+        RK_S32 peaking_estc_alpha_over_d1;
+        RK_S32 peaking_estc_alpha_under_d1;
+        RK_S32 peaking_estc_alpha_over_unlimit_d1;
+        RK_S32 peaking_estc_alpha_under_unlimit_d1;
+        RK_S32 peaking_estc_delta_offset_non;
+        RK_S32 peaking_estc_alpha_over_non;
+        RK_S32 peaking_estc_alpha_under_non;
+        RK_S32 peaking_estc_alpha_over_unlimit_non;
+        RK_S32 peaking_estc_alpha_under_unlimit_non;
+        RK_S32 peaking_filter_cfg_diag_enh_coef;
+
+        RK_S32 peaking_filt_core_H0[6];
+        RK_S32 peaking_filt_core_H1[6];
+        RK_S32 peaking_filt_core_H2[6];
+        RK_S32 peaking_filt_core_H3[6];
+        RK_S32 peaking_filt_core_V0[3];
+        RK_S32 peaking_filt_core_V1[3];
+        RK_S32 peaking_filt_core_V2[3];
+        RK_S32 peaking_filt_core_USM[3];
+
+        RK_S32 shootctrl_enable;
+        RK_S32 shootctrl_filter_radius;
+        RK_S32 shootctrl_delta_offset;
+        RK_S32 shootctrl_alpha_over;
+        RK_S32 shootctrl_alpha_under;
+        RK_S32 shootctrl_alpha_over_unlimit;
+        RK_S32 shootctrl_alpha_under_unlimit;
+
+        RK_S32 global_gain_enable;
+        RK_S32 global_gain_lum_mode;
+        RK_S32 global_gain_lum_grd[6];
+        RK_S32 global_gain_lum_val[6];
+        RK_S32 global_gain_adp_grd[6];
+        RK_S32 global_gain_adp_val[6];
+        RK_S32 global_gain_var_grd[6];
+        RK_S32 global_gain_var_val[6];
+
+        RK_S32 color_ctrl_enable;
+
+        RK_S32 color_ctrl_p0_scaling_coef;
+        RK_S32 color_ctrl_p0_point_u;
+        RK_S32 color_ctrl_p0_point_v;
+        RK_S32 color_ctrl_p0_roll_tab[16];
+
+        RK_S32 color_ctrl_p1_scaling_coef;
+        RK_S32 color_ctrl_p1_point_u;
+        RK_S32 color_ctrl_p1_point_v;
+        RK_S32 color_ctrl_p1_roll_tab[16];
+
+        RK_S32 color_ctrl_p2_scaling_coef;
+        RK_S32 color_ctrl_p2_point_u;
+        RK_S32 color_ctrl_p2_point_v;
+        RK_S32 color_ctrl_p2_roll_tab[16];
+
+        RK_S32 color_ctrl_p3_scaling_coef;
+        RK_S32 color_ctrl_p3_point_u;
+        RK_S32 color_ctrl_p3_point_v;
+        RK_S32 color_ctrl_p3_roll_tab[16];
+
+        RK_S32 tex_adj_enable;
+        RK_S32 tex_adj_y_mode_select;
+        RK_S32 tex_adj_mode_select;
+        RK_S32 tex_adj_grd[6];
+        RK_S32 tex_adj_val[6];
+    } sharp;
+};
+
+struct vdpp_api_params {
+    enum VDPP_PARAM_TYPE ptype;
+    union vdpp_api_content param;
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+vdpp_com_ctx* rockchip_vdpp_api_alloc_ctx(void);
+void rockchip_vdpp_api_release_ctx(vdpp_com_ctx *com_ctx);
+MPP_RET dci_hist_info_parser(RK_U8* p_pack_hist_addr, RK_U32* p_hist_local, RK_U32* p_hist_global);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/mpp/vproc/mpp_dec_vproc.cpp b/mpp/vproc/mpp_dec_vproc.cpp
index 8fa4a699a..f566d223d 100644
--- a/mpp/vproc/mpp_dec_vproc.cpp
+++ b/mpp/vproc/mpp_dec_vproc.cpp
@@ -621,28 +621,31 @@ static void *dec_vproc_thread(void *data)
                 vproc_dbg_status("vproc thread wait %d", ctx->task_wait.val);
                 thd->wait();
             }
+        }
 
-            if (!ctx->task_status.task_rdy) {
-                if (hal_task_get_hnd(tasks, TASK_PROCESSING, &task)) {
-                    if (ctx->reset) {
-                        /* reset only on all task finished */
-                        vproc_dbg_reset("reset start\n");
+        if (!ctx->task_status.task_rdy) {
+            if (hal_task_get_hnd(tasks, TASK_PROCESSING, &task)) {
+                if (ctx->reset) {
+                    /* reset only on all task finished */
+                    vproc_dbg_reset("reset start\n");
 
-                        dec_vproc_clr_prev(ctx);
-                        ctx->reset = 0;
-                        sem_post(&ctx->reset_sem);
-                        ctx->task_wait.val = 0;
+                    dec_vproc_clr_prev(ctx);
 
-                        vproc_dbg_reset("reset done\n");
-                        continue;
-                    }
+                    thd->lock(THREAD_CONTROL);
+                    ctx->reset = 0;
+                    thd->unlock(THREAD_CONTROL);
+                    sem_post(&ctx->reset_sem);
+                    ctx->task_wait.val = 0;
 
-                    ctx->task_wait.task_in = 1;
+                    vproc_dbg_reset("reset done\n");
                     continue;
                 }
-                ctx->task_status.task_rdy = 1;
-                ctx->task_wait.task_in = 0;
+
+                ctx->task_wait.task_in = 1;
+                continue;
             }
+            ctx->task_status.task_rdy = 1;
+            ctx->task_wait.task_in = 0;
         }
 
         if (task) {
@@ -950,8 +953,10 @@ MPP_RET dec_vproc_reset(MppDecVprocCtx ctx)
         vproc_dbg_reset("reset contorl start\n");
         // wait reset finished
         thd->lock();
+        thd->lock(THREAD_CONTROL);
         p->reset = 1;
         thd->signal();
+        thd->unlock(THREAD_CONTROL);
         thd->unlock();
 
         vproc_dbg_reset("reset contorl wait\n");
diff --git a/mpp/vproc/vdpp/CMakeLists.txt b/mpp/vproc/vdpp/CMakeLists.txt
new file mode 100644
index 000000000..170f1ab0d
--- /dev/null
+++ b/mpp/vproc/vdpp/CMakeLists.txt
@@ -0,0 +1,20 @@
+# vim: syntax=cmake
+
+# ----------------------------------------------------------------------------
+# add vdpp (Video Display Post Processor) implement
+# ----------------------------------------------------------------------------
+add_library(vproc_vdpp STATIC vdpp_api.c
+                              vdpp.c
+                              vdpp2.c
+                              vdpp_common.c)
+set_target_properties(vproc_vdpp PROPERTIES FOLDER "mpp/vproc/vdpp")
+
+add_subdirectory(test)
+
+# libvdpp.so for hwpq
+add_library(vdpp SHARED hwpq_vdpp_proc.cpp ../../mpp_info.cpp)
+set_target_properties(vdpp PROPERTIES FOLDER "mpp/vproc/vdpp")
+set_target_properties(vdpp PROPERTIES CLEAN_DIRECT_OUTPUT 1)
+target_link_libraries(vdpp osal mpp_base vproc_vdpp)
+set_target_properties(vdpp PROPERTIES C_VISIBILITY_PRESET default)
+set_target_properties(vdpp PROPERTIES CXX_VISIBILITY_PRESET default)
diff --git a/mpp/vproc/vdpp/hwpq_debug.h b/mpp/vproc/vdpp/hwpq_debug.h
new file mode 100644
index 000000000..87fcb3523
--- /dev/null
+++ b/mpp/vproc/vdpp/hwpq_debug.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: Apache-2.0 OR MIT */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef __HWPQ_DEBUG_H_
+#define __HWPQ_DEBUG_H_
+
+#include <stdio.h>
+#include "mpp_log.h"
+
+#define HWPQ_VDPP_TRACE           (0x00000001)
+#define HWPQ_VDPP_INFO            (0x00000002)
+#define HWPQ_VDPP_DUMP_IN         (0x00000010)
+#define HWPQ_VDPP_DUMP_OUT        (0x00000020)
+
+#define HWPQ_VDPP_DBG(flag, fmt, ...)    _mpp_dbg(hwpq_vdpp_debug, flag, fmt, ## __VA_ARGS__)
+#define HWPQ_VDPP_DBG_F(flag, fmt, ...)  _mpp_dbg_f(hwpq_vdpp_debug, flag, fmt, ## __VA_ARGS__)
+
+#define hwpq_vdpp_dbg(type, fmt, ...) \
+    do {\
+        if (hwpq_vdpp_debug & type)\
+            mpp_log(fmt, ## __VA_ARGS__);\
+    } while (0)
+
+#define hwpq_vdpp_enter() \
+    do {\
+        if (hwpq_vdpp_debug & HWPQ_VDPP_TRACE)\
+            mpp_log("line(%d), func(%s), enter", __LINE__, __FUNCTION__);\
+    } while (0)
+
+#define hwpq_vdpp_leave() \
+    do {\
+        if (hwpq_vdpp_debug & HWPQ_VDPP_TRACE)\
+            mpp_log("line(%d), func(%s), leave", __LINE__, __FUNCTION__);\
+    } while (0)
+
+#define hwpq_vdpp_info(fmt, ...) \
+    do {\
+        if (hwpq_vdpp_debug & HWPQ_VDPP_INFO)\
+            mpp_log(fmt, ## __VA_ARGS__);\
+    } while (0)
+
+extern RK_U32 hwpq_vdpp_debug;
+
+#endif // __HWPQ_DEBUG_H_
\ No newline at end of file
diff --git a/mpp/vproc/vdpp/hwpq_vdpp_proc.cpp b/mpp/vproc/vdpp/hwpq_vdpp_proc.cpp
new file mode 100644
index 000000000..fcd7dd4a4
--- /dev/null
+++ b/mpp/vproc/vdpp/hwpq_vdpp_proc.cpp
@@ -0,0 +1,896 @@
+/* SPDX-License-Identifier: Apache-2.0 OR MIT */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/mman.h>
+#include <unistd.h>
+#include <sys/syscall.h>
+
+#include "mpp_mem.h"
+#include "mpp_env.h"
+#include "mpp_buffer.h"
+#include "mpp_soc.h"
+
+#include "vdpp_api.h"
+#include "hwpq_vdpp_proc_api.h"
+#include "hwpq_debug.h"
+
+RK_U32 hwpq_vdpp_debug = 0;
+
+#define HWPQ_VDPP_MAX_FILE_NAME_LEN         (256)
+#define HWPQ_VDPP_DEBUG_CFG_PROP            "vendor.vdpp.debug_cfg"
+
+static const char hwpq_vdpp_in_path[] = "/data/vendor/rkalgo/hwpq_vdpp_in.bin";
+static const char hwpq_vdpp_out_path[] = "/data/vendor/rkalgo/hwpq_vdpp_out.bin";
+
+typedef struct VdppCtxImpl_e {
+    vdpp_com_ctx* vdpp;
+
+    MppBufferGroup memGroup;
+    MppBuffer histbuf;
+} VdppCtxImpl;
+
+static void set_dmsr_default_config(struct vdpp_api_params* p_api_params)
+{
+    p_api_params->ptype = VDPP_PARAM_TYPE_DMSR;
+    p_api_params->param.dmsr.enable = 1;
+    p_api_params->param.dmsr.str_pri_y = 10;
+    p_api_params->param.dmsr.str_sec_y = 4;
+    p_api_params->param.dmsr.dumping_y = 6;
+    p_api_params->param.dmsr.wgt_pri_gain_even_1 = 12;
+    p_api_params->param.dmsr.wgt_pri_gain_even_2 = 12;
+    p_api_params->param.dmsr.wgt_pri_gain_odd_1 = 8;
+    p_api_params->param.dmsr.wgt_pri_gain_odd_2 = 16;
+    p_api_params->param.dmsr.wgt_sec_gain = 5;
+    p_api_params->param.dmsr.blk_flat_th = 20;
+    p_api_params->param.dmsr.contrast_to_conf_map_x0 = 1680;
+    p_api_params->param.dmsr.contrast_to_conf_map_x1 = 6720;
+    p_api_params->param.dmsr.contrast_to_conf_map_y0 = 0;
+    p_api_params->param.dmsr.contrast_to_conf_map_y1 = 65535;
+    p_api_params->param.dmsr.diff_core_th0 = 1;
+    p_api_params->param.dmsr.diff_core_th1 = 5;
+    p_api_params->param.dmsr.diff_core_wgt0 = 16;
+    p_api_params->param.dmsr.diff_core_wgt1 = 16;
+    p_api_params->param.dmsr.diff_core_wgt2 = 16;
+    p_api_params->param.dmsr.edge_th_low_arr[0] = 30;
+    p_api_params->param.dmsr.edge_th_low_arr[1] = 10;
+    p_api_params->param.dmsr.edge_th_low_arr[2] = 0;
+    p_api_params->param.dmsr.edge_th_low_arr[3] = 0;
+    p_api_params->param.dmsr.edge_th_low_arr[4] = 0;
+    p_api_params->param.dmsr.edge_th_low_arr[5] = 0;
+    p_api_params->param.dmsr.edge_th_low_arr[6] = 0;
+    p_api_params->param.dmsr.edge_th_high_arr[0] = 60;
+    p_api_params->param.dmsr.edge_th_high_arr[1] = 40;
+    p_api_params->param.dmsr.edge_th_high_arr[2] = 20;
+    p_api_params->param.dmsr.edge_th_high_arr[3] = 10;
+    p_api_params->param.dmsr.edge_th_high_arr[4] = 10;
+    p_api_params->param.dmsr.edge_th_high_arr[5] = 10;
+    p_api_params->param.dmsr.edge_th_high_arr[6] = 10;
+}
+
+static void set_es_default_config(struct vdpp_api_params* p_api_params)
+{
+    static RK_S32 diff2conf_lut_x_tmp[9] = {
+        0, 1024, 2048, 3072, 4096, 6144, 8192, 12288, 65535,
+    };
+    static RK_S32 diff2conf_lut_y_tmp[9] = {
+        0, 84, 141, 179, 204, 233, 246, 253, 255,
+    };
+
+    p_api_params->ptype = VDPP_PARAM_TYPE_ES;
+    p_api_params->param.es.es_bEnabledES          = 0;
+    p_api_params->param.es.es_iAngleDelta         = 17;
+    p_api_params->param.es.es_iAngleDeltaExtra    = 5;
+    p_api_params->param.es.es_iGradNoDirTh        = 37;
+    p_api_params->param.es.es_iGradFlatTh         = 75;
+    p_api_params->param.es.es_iWgtGain            = 128;
+    p_api_params->param.es.es_iWgtDecay           = 128;
+    p_api_params->param.es.es_iLowConfTh          = 96;
+    p_api_params->param.es.es_iLowConfRatio       = 32;
+    p_api_params->param.es.es_iConfCntTh          = 4;
+    p_api_params->param.es.es_iWgtLocalTh         = 64;
+    p_api_params->param.es.es_iK1                 = 4096;
+    p_api_params->param.es.es_iK2                 = 7168;
+    p_api_params->param.es.es_iDeltaLimit         = 65280;
+    memcpy(&p_api_params->param.es.es_iDiff2conf_lut_x[0], &diff2conf_lut_x_tmp[0],
+           sizeof(diff2conf_lut_x_tmp));
+    memcpy(&p_api_params->param.es.es_iDiff2conf_lut_y[0], &diff2conf_lut_y_tmp[0],
+           sizeof(diff2conf_lut_y_tmp));
+    p_api_params->param.es.es_bEndpointCheckEnable = 1;
+}
+
+static void set_hist_cnt_default_config(struct vdpp_api_params* p_api_params)
+{
+    p_api_params->ptype = VDPP_PARAM_TYPE_HIST;
+
+    p_api_params->param.hist.hist_cnt_en   = 1;
+    p_api_params->param.hist.dci_hsd_mode  = 0;
+    p_api_params->param.hist.dci_vsd_mode  = 0;
+    p_api_params->param.hist.dci_yrgb_gather_num  = 0;
+    p_api_params->param.hist.dci_yrgb_gather_en  = 0;
+}
+
+static void set_shp_default_config(struct vdpp_api_params* p_api_params)
+{
+    static RK_S32 coring_zero_tmp[7]        = {
+        5, 5, 8, 5, 8, 5, 5,
+    };
+    static RK_S32 coring_thr_tmp[7]         = {
+        40, 40, 40, 24, 26, 30, 26,
+    };
+    static RK_S32 coring_ratio_tmp[7]       = {
+        1479, 1188, 1024, 1422, 1024, 1024, 1024,
+    };
+    static RK_S32 gain_pos_tmp[7]           = {
+        128, 256, 512, 256, 512, 256, 256,
+    };
+    static RK_S32 gain_neg_tmp[7]           = {
+        128, 256, 512, 256, 512, 256, 256,
+    };
+    static RK_S32 limit_ctrl_pos0_tmp[7]    = {
+        64, 64, 64, 64, 64, 64, 64,
+    };
+    static RK_S32 limit_ctrl_pos1_tmp[7]    = {
+        120, 120, 120, 120, 120, 120, 120,
+    };
+    static RK_S32 limit_ctrl_neg0_tmp[7]    = {
+        64, 64, 64, 64, 64, 64, 64,
+    };
+    static RK_S32 limit_ctrl_neg1_tmp[7]    = {
+        120, 120, 120, 120, 120, 120, 120,
+    };
+    static RK_S32 limit_ctrl_ratio_tmp[7]   = {
+        128, 128, 128, 128, 128, 128, 128,
+    };
+    static RK_S32 limit_ctrl_bnd_pos_tmp[7] = {
+        81, 131, 63, 81, 63, 63, 63,
+    };
+    static RK_S32 limit_ctrl_bnd_neg_tmp[7] = {
+        81, 131, 63, 81, 63, 63, 63,
+    };
+    static RK_S32 lum_grd_tmp[6]            = {
+        0, 200, 300, 860, 960, 102,
+    };
+    static RK_S32 lum_val_tmp[6]            = {
+        64, 64, 64, 64, 64, 64,
+    };
+    static RK_S32 adp_grd_tmp[6]            = {
+        0, 4, 60, 180, 300, 1023,
+    };
+    static RK_S32 adp_val_tmp[6]            = {
+        64, 64, 64, 64, 64, 64,
+    };
+    static RK_S32 var_grd_tmp[6]            = {
+        0, 39, 102, 209, 500, 1023,
+    };
+    static RK_S32 var_val_tmp[6]            = {
+        64, 64, 64, 64, 64, 64,
+    };
+    static RK_S32 diag_adj_gain_tab_tmp[8]  = {
+        6, 7, 8, 9, 10, 11, 12, 13,
+    };
+    static RK_S32 roll_tab_pattern0[16]     = {
+        0, 0, 0, 1, 2, 3, 4, 6, 8, 10, 11, 12, 13, 14, 15, 15,
+    };
+    static RK_S32 roll_tab_pattern1[16]     = {
+        31, 31, 30, 29, 28, 27, 25, 23, 21, 19, 18, 17, 16, 16, 15, 15,
+    };
+    static RK_S32 roll_tab_pattern2[16]     = {
+        16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16,
+    };
+    static RK_S32 tex_grd_tmp[6]            = {
+        0, 128, 256, 400, 600, 1023,
+    };
+    static RK_S32 tex_val_tmp[6]            = {
+        40, 60, 80, 100, 127, 127,
+    };
+
+    p_api_params->ptype = VDPP_PARAM_TYPE_SHARP;
+
+    p_api_params->param.sharp.sharp_enable               = 1;
+    p_api_params->param.sharp.sharp_coloradj_bypass_en   = 1;
+
+    p_api_params->param.sharp.lti_h_enable           = 0;
+    p_api_params->param.sharp.lti_h_radius           = 1;
+    p_api_params->param.sharp.lti_h_slope            = 100;
+    p_api_params->param.sharp.lti_h_thresold         = 21;
+    p_api_params->param.sharp.lti_h_gain             = 8;
+    p_api_params->param.sharp.lti_h_noise_thr_pos    = 1023;
+    p_api_params->param.sharp.lti_h_noise_thr_neg    = 1023;
+
+    p_api_params->param.sharp.lti_v_enable           = 0;
+    p_api_params->param.sharp.lti_v_radius           = 1;
+    p_api_params->param.sharp.lti_v_slope            = 100;
+    p_api_params->param.sharp.lti_v_thresold         = 21;
+    p_api_params->param.sharp.lti_v_gain             = 8;
+    p_api_params->param.sharp.lti_v_noise_thr_pos    = 1023;
+    p_api_params->param.sharp.lti_v_noise_thr_neg    = 1023;
+
+    p_api_params->param.sharp.cti_h_enable           = 0;
+    p_api_params->param.sharp.cti_h_radius           = 1;
+    p_api_params->param.sharp.cti_h_slope            = 100;
+    p_api_params->param.sharp.cti_h_thresold         = 21;
+    p_api_params->param.sharp.cti_h_gain             = 8;
+    p_api_params->param.sharp.cti_h_noise_thr_pos    = 1023;
+    p_api_params->param.sharp.cti_h_noise_thr_neg    = 1023;
+
+    p_api_params->param.sharp.peaking_enable         = 1;
+    p_api_params->param.sharp.peaking_gain           = 196;
+
+    p_api_params->param.sharp.peaking_coring_enable      = 1;
+    p_api_params->param.sharp.peaking_limit_ctrl_enable  = 1;
+    p_api_params->param.sharp.peaking_gain_enable        = 1;
+
+    memcpy(p_api_params->param.sharp.peaking_coring_zero,    coring_zero_tmp,
+           sizeof(coring_zero_tmp));
+    memcpy(p_api_params->param.sharp.peaking_coring_thr,     coring_thr_tmp,
+           sizeof(coring_thr_tmp));
+    memcpy(p_api_params->param.sharp.peaking_coring_ratio,   coring_ratio_tmp,
+           sizeof(coring_ratio_tmp));
+    memcpy(p_api_params->param.sharp.peaking_gain_pos,   gain_pos_tmp,   sizeof(gain_pos_tmp));
+    memcpy(p_api_params->param.sharp.peaking_gain_neg,   gain_neg_tmp,   sizeof(gain_neg_tmp));
+    memcpy(p_api_params->param.sharp.peaking_limit_ctrl_pos0,    limit_ctrl_pos0_tmp,
+           sizeof(limit_ctrl_pos0_tmp));
+    memcpy(p_api_params->param.sharp.peaking_limit_ctrl_pos1,    limit_ctrl_pos1_tmp,
+           sizeof(limit_ctrl_pos1_tmp));
+    memcpy(p_api_params->param.sharp.peaking_limit_ctrl_neg0,    limit_ctrl_neg0_tmp,
+           sizeof(limit_ctrl_neg0_tmp));
+    memcpy(p_api_params->param.sharp.peaking_limit_ctrl_neg1,    limit_ctrl_neg1_tmp,
+           sizeof(limit_ctrl_neg1_tmp));
+    memcpy(p_api_params->param.sharp.peaking_limit_ctrl_ratio,   limit_ctrl_ratio_tmp,
+           sizeof(limit_ctrl_ratio_tmp));
+    memcpy(p_api_params->param.sharp.peaking_limit_ctrl_bnd_pos, limit_ctrl_bnd_pos_tmp,
+           sizeof(limit_ctrl_bnd_pos_tmp));
+    memcpy(p_api_params->param.sharp.peaking_limit_ctrl_bnd_neg, limit_ctrl_bnd_neg_tmp,
+           sizeof(limit_ctrl_bnd_neg_tmp));
+
+    p_api_params->param.sharp.peaking_edge_ctrl_enable               = 1;
+    p_api_params->param.sharp.peaking_edge_ctrl_non_dir_thr          = 16;
+    p_api_params->param.sharp.peaking_edge_ctrl_dir_cmp_ratio        = 4;
+    p_api_params->param.sharp.peaking_edge_ctrl_non_dir_wgt_offset   = 64;
+    p_api_params->param.sharp.peaking_edge_ctrl_non_dir_wgt_ratio    = 16;
+    p_api_params->param.sharp.peaking_edge_ctrl_dir_cnt_thr          = 2;
+    p_api_params->param.sharp.peaking_edge_ctrl_dir_cnt_avg          = 3;
+    p_api_params->param.sharp.peaking_edge_ctrl_dir_cnt_offset       = 2;
+    p_api_params->param.sharp.peaking_edge_ctrl_diag_dir_thr         = 16;
+
+    memcpy(p_api_params->param.sharp.peaking_edge_ctrl_diag_adj_gain_tab,
+           diag_adj_gain_tab_tmp, sizeof(diag_adj_gain_tab_tmp));
+
+    p_api_params->param.sharp.peaking_estc_enable                    = 1;
+    p_api_params->param.sharp.peaking_estc_delta_offset_h            = 4;
+    p_api_params->param.sharp.peaking_estc_alpha_over_h              = 8;
+    p_api_params->param.sharp.peaking_estc_alpha_under_h             = 16;
+    p_api_params->param.sharp.peaking_estc_alpha_over_unlimit_h      = 64;
+    p_api_params->param.sharp.peaking_estc_alpha_under_unlimit_h     = 112;
+    p_api_params->param.sharp.peaking_estc_delta_offset_v            = 4;
+    p_api_params->param.sharp.peaking_estc_alpha_over_v              = 8;
+    p_api_params->param.sharp.peaking_estc_alpha_under_v             = 16;
+    p_api_params->param.sharp.peaking_estc_alpha_over_unlimit_v      = 64;
+    p_api_params->param.sharp.peaking_estc_alpha_under_unlimit_v     = 112;
+    p_api_params->param.sharp.peaking_estc_delta_offset_d0           = 4;
+    p_api_params->param.sharp.peaking_estc_alpha_over_d0             = 16;
+    p_api_params->param.sharp.peaking_estc_alpha_under_d0            = 16;
+    p_api_params->param.sharp.peaking_estc_alpha_over_unlimit_d0     = 96;
+    p_api_params->param.sharp.peaking_estc_alpha_under_unlimit_d0    = 96;
+    p_api_params->param.sharp.peaking_estc_delta_offset_d1           = 4;
+    p_api_params->param.sharp.peaking_estc_alpha_over_d1             = 16;
+    p_api_params->param.sharp.peaking_estc_alpha_under_d1            = 16;
+    p_api_params->param.sharp.peaking_estc_alpha_over_unlimit_d1     = 96;
+    p_api_params->param.sharp.peaking_estc_alpha_under_unlimit_d1    = 96;
+    p_api_params->param.sharp.peaking_estc_delta_offset_non          = 4;
+    p_api_params->param.sharp.peaking_estc_alpha_over_non            = 8;
+    p_api_params->param.sharp.peaking_estc_alpha_under_non           = 8;
+    p_api_params->param.sharp.peaking_estc_alpha_over_unlimit_non    = 112;
+    p_api_params->param.sharp.peaking_estc_alpha_under_unlimit_non   = 112;
+    p_api_params->param.sharp.peaking_filter_cfg_diag_enh_coef       = 6;
+
+    p_api_params->param.sharp.peaking_filt_core_H0[0]                = 4;
+    p_api_params->param.sharp.peaking_filt_core_H0[1]                = 16;
+    p_api_params->param.sharp.peaking_filt_core_H0[2]                = 24;
+    p_api_params->param.sharp.peaking_filt_core_H1[0]                = -16;
+    p_api_params->param.sharp.peaking_filt_core_H1[1]                = 0;
+    p_api_params->param.sharp.peaking_filt_core_H1[2]                = 32;
+    p_api_params->param.sharp.peaking_filt_core_H2[0]                = 0;
+    p_api_params->param.sharp.peaking_filt_core_H2[1]                = -16;
+    p_api_params->param.sharp.peaking_filt_core_H2[2]                = 32;
+    p_api_params->param.sharp.peaking_filt_core_V0[0]                = 1;
+    p_api_params->param.sharp.peaking_filt_core_V0[1]                = 4;
+    p_api_params->param.sharp.peaking_filt_core_V0[2]                = 6;
+    p_api_params->param.sharp.peaking_filt_core_V1[0]                = -4;
+    p_api_params->param.sharp.peaking_filt_core_V1[1]                = 0;
+    p_api_params->param.sharp.peaking_filt_core_V1[2]                = 8;
+    p_api_params->param.sharp.peaking_filt_core_V2[0]                = 0;
+    p_api_params->param.sharp.peaking_filt_core_V2[1]                = -4;
+    p_api_params->param.sharp.peaking_filt_core_V2[2]                = 8;
+    p_api_params->param.sharp.peaking_filt_core_USM[0]               = 1;
+    p_api_params->param.sharp.peaking_filt_core_USM[1]               = 4;
+    p_api_params->param.sharp.peaking_filt_core_USM[2]               = 6;
+
+    p_api_params->param.sharp.shootctrl_enable               = 1;
+    p_api_params->param.sharp.shootctrl_filter_radius        = 1;
+    p_api_params->param.sharp.shootctrl_delta_offset         = 16;
+    p_api_params->param.sharp.shootctrl_alpha_over           = 8;
+    p_api_params->param.sharp.shootctrl_alpha_under          = 8;
+    p_api_params->param.sharp.shootctrl_alpha_over_unlimit   = 112;
+    p_api_params->param.sharp.shootctrl_alpha_under_unlimit  = 112;
+
+    p_api_params->param.sharp.global_gain_enable             = 0;
+    p_api_params->param.sharp.global_gain_lum_mode           = 0;
+
+    memcpy(p_api_params->param.sharp.global_gain_lum_grd, lum_grd_tmp, sizeof(lum_grd_tmp));
+    memcpy(p_api_params->param.sharp.global_gain_lum_val, lum_val_tmp, sizeof(lum_val_tmp));
+    memcpy(p_api_params->param.sharp.global_gain_adp_grd, adp_grd_tmp, sizeof(adp_grd_tmp));
+    memcpy(p_api_params->param.sharp.global_gain_adp_val, adp_val_tmp, sizeof(adp_val_tmp));
+    memcpy(p_api_params->param.sharp.global_gain_var_grd, var_grd_tmp, sizeof(var_grd_tmp));
+    memcpy(p_api_params->param.sharp.global_gain_var_val, var_val_tmp, sizeof(var_val_tmp));
+
+    p_api_params->param.sharp.color_ctrl_enable              = 0;
+
+    p_api_params->param.sharp.color_ctrl_p0_scaling_coef     = 1;
+    p_api_params->param.sharp.color_ctrl_p0_point_u          = 115;
+    p_api_params->param.sharp.color_ctrl_p0_point_v          = 155;
+    memcpy(p_api_params->param.sharp.color_ctrl_p0_roll_tab, roll_tab_pattern0,
+           sizeof(roll_tab_pattern0));
+    p_api_params->param.sharp.color_ctrl_p1_scaling_coef     = 1;
+    p_api_params->param.sharp.color_ctrl_p1_point_u          = 90;
+    p_api_params->param.sharp.color_ctrl_p1_point_v          = 120;
+    memcpy(p_api_params->param.sharp.color_ctrl_p1_roll_tab, roll_tab_pattern1,
+           sizeof(roll_tab_pattern1));
+    p_api_params->param.sharp.color_ctrl_p2_scaling_coef     = 1;
+    p_api_params->param.sharp.color_ctrl_p2_point_u          = 128;
+    p_api_params->param.sharp.color_ctrl_p2_point_v          = 128;
+    memcpy(p_api_params->param.sharp.color_ctrl_p2_roll_tab, roll_tab_pattern2,
+           sizeof(roll_tab_pattern2));
+    p_api_params->param.sharp.color_ctrl_p3_scaling_coef     = 1;
+    p_api_params->param.sharp.color_ctrl_p3_point_u          = 128;
+    p_api_params->param.sharp.color_ctrl_p3_point_v          = 128;
+    memcpy(p_api_params->param.sharp.color_ctrl_p3_roll_tab, roll_tab_pattern2,
+           sizeof(roll_tab_pattern2));
+
+    p_api_params->param.sharp.tex_adj_enable                 = 0;
+    p_api_params->param.sharp.tex_adj_y_mode_select          = 3;
+    p_api_params->param.sharp.tex_adj_mode_select            = 0;
+
+    memcpy(p_api_params->param.sharp.tex_adj_grd, tex_grd_tmp, sizeof(tex_grd_tmp));
+    memcpy(p_api_params->param.sharp.tex_adj_val, tex_val_tmp, sizeof(tex_val_tmp));
+}
+
+static RK_S32 vdpp_set_user_cfg(vdpp_com_ctx* vdpp, vdpp_params* p_vdpp_params,
+                                RK_U32 cfg_update_flag)
+{
+    struct vdpp_api_params params;
+    RK_S32 ret = MPP_OK;
+
+    if (cfg_update_flag == 0) {
+        hwpq_vdpp_info("vdpp config not changed\n");
+        return ret;
+    }
+
+    hwpq_vdpp_info("update vdpp config\n");
+
+    set_dmsr_default_config(&params);
+    params.param.dmsr.enable    = p_vdpp_params->dmsr_en;
+    params.param.dmsr.str_pri_y = p_vdpp_params->str_pri_y;
+    params.param.dmsr.str_sec_y = p_vdpp_params->str_sec_y;
+    params.param.dmsr.dumping_y = p_vdpp_params->dumping_y;
+    ret |= vdpp->ops->control(vdpp->priv, VDPP_CMD_SET_DMSR_CFG, &params);
+
+    set_es_default_config(&params);
+    params.param.es.es_bEnabledES   = p_vdpp_params->es_en;
+    params.param.es.es_iWgtGain     = p_vdpp_params->es_iWgtGain;
+    ret |= vdpp->ops->control(vdpp->priv, VDPP_CMD_SET_ES, &params);
+
+    set_hist_cnt_default_config(&params);
+    params.param.hist.hist_cnt_en   = p_vdpp_params->hist_cnt_en;
+    params.param.hist.dci_csc_range = p_vdpp_params->hist_csc_range;
+    ret |= vdpp->ops->control(vdpp->priv, VDPP_CMD_SET_DCI_HIST, &params);
+
+    set_shp_default_config(&params);
+    params.param.sharp.sharp_enable                     = p_vdpp_params->shp_en;
+    params.param.sharp.peaking_gain                     = p_vdpp_params->peaking_gain;
+    params.param.sharp.shootctrl_enable                 = p_vdpp_params->shp_shoot_ctrl_en;
+    params.param.sharp.shootctrl_alpha_over             = p_vdpp_params->shp_shoot_ctrl_over;
+    params.param.sharp.shootctrl_alpha_over_unlimit     = p_vdpp_params->shp_shoot_ctrl_over;
+    params.param.sharp.shootctrl_alpha_under            = p_vdpp_params->shp_shoot_ctrl_under;
+    params.param.sharp.shootctrl_alpha_under_unlimit    = p_vdpp_params->shp_shoot_ctrl_under;
+    ret |= vdpp->ops->control(vdpp->priv, VDPP_CMD_SET_SHARP, &params);
+
+    return ret;
+}
+
+static MPP_RET vdpp_set_img(vdpp_com_ctx *ctx, RK_S32 fd_yrgb, RK_S32 fd_cbcr,
+                            RK_S32 cbcr_offset, VdppCmd cmd)
+{
+    VdppImg img;
+
+    hwpq_vdpp_info("yrgb_fd=%d, cbcr_fd=%d, cbcr_offset=%d\n", fd_yrgb, fd_cbcr, cbcr_offset);
+    img.mem_addr = fd_yrgb;
+    img.uv_addr = fd_cbcr;
+    img.uv_off = cbcr_offset;
+
+    return ctx->ops->control(ctx->priv, cmd, &img);
+}
+
+static void* vdpp_map_buffer_with_fd(int fd, size_t bufSize)
+{
+    void* ptr = NULL;
+
+    if (fd > 0) {
+        ptr = mmap(NULL, bufSize, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);
+        if (ptr == MAP_FAILED) {
+            mpp_err_f("failed to mmap buffer, fd=%d, size=%zu\n", fd, bufSize);
+            return NULL;
+        }
+    } else {
+        mpp_err_f("failed to mmap buffer with fd! invalid fd value %d input!\n", fd);
+    }
+
+    return ptr;
+}
+
+static inline void vdpp_unmap_buffer(void* ptr, size_t bufSize)
+{
+    if (ptr) {
+        munmap(ptr, bufSize);
+    }
+}
+
+static FILE *try_env_file(const char *env, const char *path, pid_t tid, int index)
+{
+    const char *fname = NULL;
+    FILE *fp = NULL;
+    char name[HWPQ_VDPP_MAX_FILE_NAME_LEN];
+
+    mpp_env_get_str(env, &fname, path);
+    if (fname == path) {
+        snprintf(name, sizeof(name) - 1, "%s_%03d-%d", path, index, tid);
+        fname = name;
+    }
+
+    fp = fopen(fname, "w+b");
+    hwpq_vdpp_info("open %s %p for dump\n", fname, fp);
+
+    return fp;
+}
+
+static void vdpp_dump(rk_vdpp_proc_params *p_proc_param, int index)
+{
+    FILE *fp_in = NULL;
+    FILE *fp_out = NULL;
+    pid_t tid = syscall(SYS_gettid);
+
+    if (NULL == p_proc_param) {
+        mpp_err_f("found NULL proc_param %p\n", p_proc_param);
+        return;
+    }
+
+    if (hwpq_vdpp_debug & HWPQ_VDPP_DUMP_IN) {
+        fp_in = try_env_file("hwpq_vdpp_dump_in", hwpq_vdpp_in_path, tid, index);
+        if (NULL == fp_in) {
+            mpp_err_f("failed to open file %p\n", fp_in);
+        } else {
+            int fd = p_proc_param->src_img_info.img_yrgb.fd;
+            RK_U32 src_y_buf_len = p_proc_param->src_img_info.img_yrgb.w_vir *
+                                   p_proc_param->src_img_info.img_yrgb.h_vir;
+            RK_U8 *ptr = (RK_U8*)vdpp_map_buffer_with_fd(fd, src_y_buf_len);
+
+            if (ptr == NULL) {
+                mpp_err_f("vdpp dump fd(%d) map error!\n", fd);
+            } else {
+                fwrite(ptr, 1, src_y_buf_len, fp_in);
+                fclose(fp_in);
+            }
+
+            vdpp_unmap_buffer(ptr, src_y_buf_len);
+        }
+    }
+
+    if (hwpq_vdpp_debug & HWPQ_VDPP_DUMP_OUT) {
+        fp_out = try_env_file("hwpq_vdpp_dump_out", hwpq_vdpp_out_path, tid, index);
+        if (NULL == fp_out) {
+            mpp_err_f("failed to open file %p\n", fp_out);
+        } else {
+            int fd = p_proc_param->src_img_info.img_yrgb.fd;
+            RK_U32 dst_y_buf_len = p_proc_param->dst_img_info.img_yrgb.w_vir *
+                                   p_proc_param->dst_img_info.img_yrgb.h_vir;
+            RK_U8 *ptr = (RK_U8*)vdpp_map_buffer_with_fd(fd, dst_y_buf_len);
+
+            if (ptr == NULL) {
+                mpp_err_f("vdpp dump fd(%d) map error!\n", fd);
+            } else {
+                fwrite(ptr, 1, dst_y_buf_len, fp_out);
+                fclose(fp_out);
+            }
+
+            vdpp_unmap_buffer(ptr, dst_y_buf_len);
+        }
+    }
+
+    MPP_FCLOSE(fp_in);
+    MPP_FCLOSE(fp_out);
+}
+
+static MppFrameFormat img_format_convert(vdpp_frame_format img_fmt_in)
+{
+    MppFrameFormat img_fmt_out = MPP_FMT_YUV420SP;
+
+    switch (img_fmt_in) {
+    case VDPP_FMT_NV24:
+        img_fmt_out = MPP_FMT_YUV444SP;
+        break;
+    case VDPP_FMT_NV16:
+        img_fmt_out = MPP_FMT_YUV422SP;
+        break;
+    case VDPP_FMT_NV12:
+        img_fmt_out = MPP_FMT_YUV420SP;
+        break;
+    case VDPP_FMT_NV15:
+        img_fmt_out = MPP_FMT_YUV420SP_10BIT;
+        break;
+    case VDPP_FMT_NV20:
+        img_fmt_out = MPP_FMT_YUV420SP_10BIT;
+        break;
+    case VDPP_FMT_NV30:
+        img_fmt_out = MPP_FMT_YUV420SP_10BIT;
+        break;
+
+    case VDPP_FMT_RGBA:
+        img_fmt_out = MPP_FMT_RGBA8888;
+        break;
+    case VDPP_FMT_RG24:
+        img_fmt_out = MPP_FMT_RGB888;
+        break;
+    case VDPP_FMT_BG24:
+        img_fmt_out = MPP_FMT_BGR888;
+        break;
+
+    default:
+        mpp_err_f("unsupport input format(%x), set NV12!", img_fmt_in);
+        break;
+    }
+
+    return img_fmt_out;
+}
+
+static enum VDPP_YUV_SWAP get_img_format_swap(vdpp_frame_format img_fmt_in)
+{
+    enum VDPP_YUV_SWAP img_fmt_swap = VDPP_YUV_SWAP_SP_UV;
+
+    switch (img_fmt_in) {
+    case VDPP_FMT_NV24_VU:
+    case VDPP_FMT_NV16_VU:
+    case VDPP_FMT_NV12_VU:
+        img_fmt_swap = VDPP_YUV_SWAP_SP_VU;
+        break;
+
+    default:
+        img_fmt_swap = VDPP_YUV_SWAP_SP_UV;
+        break;
+    }
+
+    return img_fmt_swap;
+}
+
+int hwpq_vdpp_deinit(rk_vdpp_context ctx)
+{
+    VdppCtxImpl *p = (VdppCtxImpl*)ctx;
+    vdpp_com_ctx* vdpp = NULL;
+    MPP_RET ret = MPP_NOK;
+
+    hwpq_vdpp_enter();
+
+    if (NULL == ctx) {
+        mpp_err_f("found NULL input ctx %p\n", ctx);
+        ret = MPP_ERR_NULL_PTR;
+        goto __RET;
+    }
+
+    vdpp = p->vdpp;
+    if (NULL == vdpp || NULL == vdpp->ops) {
+        mpp_err_f("found NULL vdpp\n");
+        ret = MPP_ERR_NULL_PTR;
+        goto __RET;
+    }
+
+    if (vdpp->ops->deinit) {
+        ret = vdpp->ops->deinit(vdpp->priv);
+        if (ret) {
+            mpp_err_f("vdpp deinit failed! ret %d\n", ret);
+        }
+    }
+
+    if (p->histbuf) {
+        mpp_buffer_put(p->histbuf);
+        p->histbuf = NULL;
+    }
+
+    if (p->memGroup) {
+        mpp_buffer_group_put(p->memGroup);
+        p->memGroup = NULL;
+    }
+
+    rockchip_vdpp_api_release_ctx(vdpp);
+    MPP_FREE(p);
+    hwpq_vdpp_leave();
+
+__RET:
+    return ret;
+}
+
+int hwpq_vdpp_init(rk_vdpp_context *p_ctx_ptr)
+{
+    VdppCtxImpl *p = NULL;
+    vdpp_com_ctx *vdpp = NULL;
+    MppBufferGroup memGroup = NULL;
+    MppBuffer histbuf = NULL;
+    MPP_RET ret = MPP_NOK;
+
+    hwpq_vdpp_enter();
+
+    if (NULL == p_ctx_ptr) {
+        mpp_err("found NULL vdpp ctx pointer\n");
+        ret = MPP_ERR_NULL_PTR;
+        goto __ERR;
+    }
+    /* alloc vdpp ctx impl */
+    p = mpp_malloc(VdppCtxImpl, 1);
+    if (NULL == p) {
+        mpp_err("alloc vdpp ctx failed!");
+        ret = MPP_ERR_MALLOC;
+        goto __ERR;
+    }
+    /* alloc vdpp */
+    vdpp = rockchip_vdpp_api_alloc_ctx();
+    if (NULL == vdpp || NULL == vdpp->ops) {
+        mpp_err("alloc vdpp ctx failed!");
+        ret = MPP_ERR_MALLOC;
+        goto __ERR;
+    }
+    /* alloc buffer group */
+    ret = mpp_buffer_group_get_internal(&memGroup, MPP_BUFFER_TYPE_DRM);
+    if (ret) {
+        mpp_err("memGroup mpp_buffer_group_get failed\n");
+        ret = MPP_NOK;
+        goto __ERR;
+    }
+
+    mpp_buffer_get(memGroup, &histbuf, VDPP_HIST_LENGTH);
+    if (ret) {
+        mpp_err("alloc histbuf failed\n");
+        ret = MPP_NOK;
+        goto __ERR;
+    }
+
+    /* setup env prop */
+    mpp_env_get_u32(HWPQ_VDPP_DEBUG_CFG_PROP, &hwpq_vdpp_debug, 0);
+
+    if (vdpp->ops->init) {
+        ret = vdpp->ops->init(&vdpp->priv);
+        if (ret) {
+            mpp_err_f("vdpp init failed! ret %d\n", ret);
+            goto __ERR;
+        }
+    }
+
+    p->vdpp = vdpp;
+    p->memGroup = memGroup;
+    p->histbuf = histbuf;
+    *p_ctx_ptr = (rk_vdpp_context)p;
+
+    hwpq_vdpp_leave();
+    return ret;
+
+__ERR:
+    if (histbuf) {
+        mpp_buffer_put(histbuf);
+        histbuf = NULL;
+    }
+
+    if (memGroup) {
+        mpp_buffer_group_put(memGroup);
+        memGroup = NULL;
+    }
+
+    rockchip_vdpp_api_release_ctx(vdpp);
+    MPP_FREE(p);
+
+    return ret;
+}
+
+static MPP_RET hwpq_vdpp_common_config(vdpp_com_ctx *vdpp, rk_vdpp_proc_params *p_proc_param)
+{
+    struct vdpp_api_params params;
+    RK_U32 is_vdpp2 = (mpp_get_soc_type() == ROCKCHIP_SOC_RK3576);
+    RK_U32 yuv_out_diff;
+    MPP_RET ret = MPP_NOK;
+
+    yuv_out_diff = (p_proc_param->yuv_diff_flag && is_vdpp2);
+    hwpq_vdpp_info("is_vdpp2: %d, yuv_diff: %d\n", is_vdpp2, yuv_out_diff);
+
+    if (is_vdpp2) {
+        RK_U32 hist_mode_en = p_proc_param->hist_mode_en;
+
+        params.ptype = VDPP_PARAM_TYPE_COM2;
+        memset(&params.param, 0, sizeof(union vdpp_api_content));
+        params.param.com2.sfmt = img_format_convert(p_proc_param->src_img_info.img_fmt);
+        params.param.com2.src_width = p_proc_param->src_img_info.img_yrgb.w_vld;
+        params.param.com2.src_height = p_proc_param->src_img_info.img_yrgb.h_vld;
+        params.param.com2.src_width_vir = p_proc_param->src_img_info.img_yrgb.w_vir;
+        params.param.com2.src_height_vir = p_proc_param->src_img_info.img_yrgb.h_vir;
+        params.param.com2.sswap = get_img_format_swap(p_proc_param->src_img_info.img_fmt);
+        params.param.com2.dfmt = VDPP_FMT_YUV444; // TODO
+        params.param.com2.dst_width = p_proc_param->dst_img_info.img_yrgb.w_vld;
+        params.param.com2.dst_height = p_proc_param->dst_img_info.img_yrgb.h_vld;
+        params.param.com2.dst_width_vir = p_proc_param->dst_img_info.img_yrgb.w_vir;
+        params.param.com2.dst_height_vir = p_proc_param->dst_img_info.img_yrgb.h_vir;
+        if (yuv_out_diff) {
+            params.param.com2.yuv_out_diff = yuv_out_diff;
+            params.param.com2.dst_c_width = p_proc_param->dst_img_info.img_cbcr.w_vld;
+            params.param.com2.dst_c_height = p_proc_param->dst_img_info.img_cbcr.h_vld;
+            params.param.com2.dst_c_width_vir = p_proc_param->dst_img_info.img_cbcr.w_vir;
+            params.param.com2.dst_c_height_vir = p_proc_param->dst_img_info.img_cbcr.h_vir;
+        }
+        params.param.com2.dswap = get_img_format_swap(p_proc_param->dst_img_info.img_fmt);
+        params.param.com2.hist_mode_en = hist_mode_en;
+        hwpq_vdpp_info("hist_mode: %d\n", params.param.com2.hist_mode_en);
+        hwpq_vdpp_info("src-fmt: %d\n", p_proc_param->src_img_info.img_fmt);
+        hwpq_vdpp_info("dst-fmt: %d\n", p_proc_param->dst_img_info.img_fmt);
+        hwpq_vdpp_info("src-res: %d-%d  %d-%d\n", params.param.com2.src_width, params.param.com2.src_height,
+                       params.param.com2.src_width_vir, params.param.com2.src_height_vir);
+        hwpq_vdpp_info("dst-res: %d-%d  %d-%d\n", params.param.com2.dst_width, params.param.com2.dst_height,
+                       params.param.com2.dst_width_vir, params.param.com2.dst_height_vir);
+        ret = vdpp->ops->control(vdpp->priv, VDPP_CMD_SET_COM2_CFG, &params);
+    } else {
+        params.ptype = VDPP_PARAM_TYPE_COM;
+        memset(&params.param, 0, sizeof(union vdpp_api_content));
+        params.param.com.src_width = p_proc_param->src_img_info.img_yrgb.w_vld;
+        params.param.com.src_height = p_proc_param->src_img_info.img_yrgb.h_vld;
+        params.param.com.sswap = get_img_format_swap(p_proc_param->src_img_info.img_fmt);
+        params.param.com.dfmt = VDPP_FMT_YUV444; // TODO
+        params.param.com.dst_width = p_proc_param->dst_img_info.img_yrgb.w_vld;
+        params.param.com.dst_height = p_proc_param->dst_img_info.img_yrgb.h_vld;
+        params.param.com.dswap = get_img_format_swap(p_proc_param->dst_img_info.img_fmt);
+        ret = vdpp->ops->control(vdpp->priv, VDPP_CMD_SET_COM_CFG, &params);
+    }
+
+    return ret;
+}
+
+int hwpq_vdpp_proc(rk_vdpp_context ctx, rk_vdpp_proc_params *p_proc_param)
+{
+    VdppCtxImpl *p = (VdppCtxImpl*)ctx;
+    vdpp_com_ctx* vdpp = NULL;
+    RK_U32 is_vdpp2 = (mpp_get_soc_type() == ROCKCHIP_SOC_RK3576);
+    MppBuffer histbuf = NULL;
+    MppBufferGroup memGroup = NULL;
+    RK_S32 ret = MPP_OK;
+    void* phist;
+    RK_S32 fdhist;
+    static int frame_idx = 0;
+
+    hwpq_vdpp_enter();
+
+    if (NULL == ctx || NULL == p_proc_param) {
+        mpp_err_f("found NULL input ctx %p proc_param %p\n", ctx, p_proc_param);
+        return MPP_ERR_NULL_PTR;
+    }
+
+    vdpp = p->vdpp;
+    if (NULL == vdpp || NULL == vdpp->ops || NULL == vdpp->ops->control) {
+        mpp_err_f("found NULL vdpp or vdpp ops\n");
+        return MPP_ERR_NULL_PTR;
+    }
+
+    memGroup = p->memGroup;
+    histbuf = p->histbuf;
+    if (NULL == memGroup || NULL == histbuf) {
+        mpp_err_f("found NULL memGroup %p or histbuf %p\n", memGroup, histbuf);
+        return MPP_ERR_NULL_PTR;
+    }
+
+    mpp_env_get_u32(HWPQ_VDPP_DEBUG_CFG_PROP, &hwpq_vdpp_debug, 0);
+
+    hwpq_vdpp_info("proc frame_idx %d\n", p_proc_param->frame_idx);
+
+    hwpq_vdpp_info("begin set image info\n");
+    hwpq_vdpp_info("set src img_info\n");
+    ret |= vdpp_set_img(vdpp, p_proc_param->src_img_info.img_yrgb.fd, p_proc_param->src_img_info.img_cbcr.fd,
+                        p_proc_param->src_img_info.img_cbcr.offset, VDPP_CMD_SET_SRC);
+    hwpq_vdpp_info("set dst img_info\n");
+    ret |= vdpp_set_img(vdpp, p_proc_param->dst_img_info.img_yrgb.fd, p_proc_param->dst_img_info.img_cbcr.fd,
+                        p_proc_param->dst_img_info.img_cbcr.offset, VDPP_CMD_SET_DST);
+    ret |= vdpp_set_img(vdpp, p_proc_param->dst_img_info.img_yrgb.fd, p_proc_param->dst_img_info.img_cbcr.fd,
+                        p_proc_param->dst_img_info.img_cbcr.offset, VDPP_CMD_SET_DST_C);
+
+    ret |= hwpq_vdpp_common_config(vdpp, p_proc_param);
+    if (ret) {
+        mpp_err("vdpp common config failed\n");
+        return MPP_NOK;
+    }
+
+    /* set params */
+    if (vdpp_set_user_cfg(vdpp, &p_proc_param->vdpp_config, p_proc_param->vdpp_config_update_flag))
+        mpp_err_f("warning: set user cfg failed");
+
+    phist   = mpp_buffer_get_ptr(histbuf);
+    fdhist  = mpp_buffer_get_fd(histbuf);
+
+    if (is_vdpp2) {
+        ret = vdpp->ops->control(vdpp->priv, VDPP_CMD_SET_HIST_FD, &fdhist);
+        if (ret) {
+            mpp_err("set hist fd failed\n");
+            return MPP_NOK;
+        }
+    }
+
+    ret = vdpp->ops->control(vdpp->priv, VDPP_CMD_RUN_SYNC, NULL);
+    if (ret) {
+        mpp_err("run vdpp failed\n");
+        return MPP_NOK;
+    }
+
+    vdpp_dump(p_proc_param, frame_idx);
+
+    frame_idx++;
+
+    if (is_vdpp2) {
+        memcpy(p_proc_param->p_hist_buf, phist, VDPP_HIST_LENGTH);
+    }
+
+    p_proc_param->dci_vdpp_info.p_hist_addr     = p_proc_param->p_hist_buf;
+    p_proc_param->dci_vdpp_info.hist_length     = VDPP_HIST_LENGTH;
+    p_proc_param->dci_vdpp_info.vdpp_img_w_in   = p_proc_param->src_img_info.img_yrgb.w_vld;
+    p_proc_param->dci_vdpp_info.vdpp_img_h_in   = p_proc_param->src_img_info.img_yrgb.h_vld;
+    p_proc_param->dci_vdpp_info.vdpp_img_w_out  = p_proc_param->dst_img_info.img_yrgb.w_vld;
+    p_proc_param->dci_vdpp_info.vdpp_img_h_out  = p_proc_param->dst_img_info.img_yrgb.h_vld;
+
+    p_proc_param->dci_vdpp_info.vdpp_blk_size_h = p_proc_param->src_img_info.img_yrgb.w_vld / 16;
+    p_proc_param->dci_vdpp_info.vdpp_blk_size_v = p_proc_param->src_img_info.img_yrgb.h_vld / 16;
+
+    hwpq_vdpp_leave();
+
+    return MPP_OK;
+}
+
+int hwpq_vdpp_check_work_mode(rk_vdpp_context ctx, rk_vdpp_proc_params *p_proc_param)
+{
+    RK_S32 cap_mode = VDPP_CAP_UNSUPPORTED;
+    VdppCtxImpl *p = (VdppCtxImpl*)ctx;
+    vdpp_com_ctx* vdpp = NULL;
+    int run_mode = VDPP_RUN_MODE_UNSUPPORTED;
+    MPP_RET ret = MPP_NOK;
+
+    if (NULL == ctx || NULL == p_proc_param) {
+        mpp_err_f("found NULL vdpp %p proc_param %p", ctx, p_proc_param);
+        return VDPP_RUN_MODE_UNSUPPORTED;
+    }
+
+    vdpp = p->vdpp;
+    if (NULL == vdpp || NULL == vdpp->ops) {
+        mpp_err_f("found NULL vdpp or ops");
+        return VDPP_RUN_MODE_UNSUPPORTED;
+    }
+
+    ret = hwpq_vdpp_common_config(vdpp, p_proc_param);
+    if (ret) {
+        mpp_err("vdpp common config failed\n");
+        return VDPP_RUN_MODE_UNSUPPORTED;
+    }
+
+    if (vdpp->ops->check_cap)
+        cap_mode = vdpp->ops->check_cap(vdpp->priv);
+
+    hwpq_vdpp_info("vdpp cap_mode %d", cap_mode);
+    /* vep first */
+    if (VDPP_CAP_VEP & cap_mode)
+        run_mode = VDPP_RUN_MODE_VEP;
+    else if (VDPP_CAP_HIST & cap_mode)
+        run_mode = VDPP_RUN_MODE_HIST;
+
+    return run_mode;
+}
diff --git a/mpp/vproc/vdpp/test/CMakeLists.txt b/mpp/vproc/vdpp/test/CMakeLists.txt
new file mode 100644
index 000000000..a88935d6a
--- /dev/null
+++ b/mpp/vproc/vdpp/test/CMakeLists.txt
@@ -0,0 +1,16 @@
+# vim: syntax=cmake
+# ----------------------------------------------------------------------------
+# mpp/vproc/vdpp built-in unit test case
+# ----------------------------------------------------------------------------
+# vdpp unit test
+option(VDPP_TEST "Build base vdpp unit test" ON)
+add_executable(vdpp_test vdpp_test.c)
+target_link_libraries(vdpp_test ${MPP_SHARED} utils vproc_vdpp)
+set_target_properties(vdpp_test PROPERTIES FOLDER "mpp/vproc/vdpp")
+add_test(NAME vdpp_test COMMAND vdpp_test)
+
+# hwpq test (call libvdpp.so)
+add_executable(hwpq_test hwpq_test.cpp)
+target_link_libraries(hwpq_test vdpp)
+set_target_properties(hwpq_test PROPERTIES FOLDER "mpp/vproc/vdpp")
+add_test(NAME hwpq_test COMMAND hwpq_test)
diff --git a/mpp/vproc/vdpp/test/hwpq_test.cpp b/mpp/vproc/vdpp/test/hwpq_test.cpp
new file mode 100644
index 000000000..792d3f122
--- /dev/null
+++ b/mpp/vproc/vdpp/test/hwpq_test.cpp
@@ -0,0 +1,406 @@
+/* SPDX-License-Identifier: Apache-2.0 OR MIT */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#define MODULE_TAG "hwpq_test"
+
+#include <getopt.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdio.h>
+#include <pthread.h>
+#include <errno.h>
+
+#include "mpp_mem.h"
+#include "mpp_buffer.h"
+#include "mpp_log.h"
+
+#include "hwpq_vdpp_proc_api.h"
+
+typedef struct {
+    char src_file_name[128];
+    char dst_file_name_y[128];
+    char dst_file_name_uv[128];
+    char dst_file_name_hist[128];
+    unsigned int img_w_i;
+    unsigned int img_h_i;
+    unsigned int img_w_i_vir;
+    unsigned int img_h_i_vir;
+    unsigned int img_w_o;
+    unsigned int img_h_o;
+    unsigned int img_w_o_vir;
+    unsigned int img_h_o_vir;
+    unsigned int uv_diff_flag;
+    unsigned int img_w_o_c;
+    unsigned int img_h_o_c;
+    unsigned int img_w_o_c_vir;
+    unsigned int img_h_o_c_vir;
+
+    unsigned int work_mode;
+
+    int32_t      nthreads;
+    int32_t      frame_num;
+} VdppCmdCfg;
+
+typedef struct {
+    int             chn;
+
+    FILE           *fp_i;
+    FILE           *fp_o_y;
+    FILE           *fp_o_uv;
+    FILE           *fp_o_h;
+
+    unsigned int    frm_eos;
+    unsigned int    loop_times;
+} VdppTestMultiCtx;
+
+typedef struct {
+    VdppCmdCfg           *cmd;
+    int                   chn;
+
+    pthread_t             thd;     // thread for for each instance
+    VdppTestMultiCtx      ctx;     // context of vdpp
+} VdppTestMultiCtxInfo;
+
+static void parse_cmd(char** argv, int argc, VdppCmdCfg* p_cmd_cfg);
+
+extern char *optarg;
+extern int   opterr;
+
+static void *multi_vdpp(void *cmd_ctx)
+{
+    VdppTestMultiCtxInfo *info = (VdppTestMultiCtxInfo *)cmd_ctx;
+    VdppTestMultiCtx *ctx  = &info->ctx;
+    VdppCmdCfg *p_cmd_cfg  = info->cmd;
+
+    rk_vdpp_context vdpp_ctx;
+    rk_vdpp_proc_params vdpp_proc_cfg;
+
+    // cmd config params
+    if (p_cmd_cfg->uv_diff_flag == 0) {
+        p_cmd_cfg->img_w_o_c = p_cmd_cfg->img_w_o;
+        p_cmd_cfg->img_h_o_c = p_cmd_cfg->img_h_o;
+        p_cmd_cfg->img_w_o_c_vir = p_cmd_cfg->img_w_o_vir;
+        p_cmd_cfg->img_h_o_c_vir = p_cmd_cfg->img_h_o_vir;
+    }
+
+    size_t srcfrmsize = p_cmd_cfg->img_w_i_vir * p_cmd_cfg->img_h_i_vir * 3 / 2;
+    size_t dstfrmsize = p_cmd_cfg->img_w_o_vir * p_cmd_cfg->img_h_o_vir * 3;
+    size_t dstfrmsize_c = p_cmd_cfg->img_w_o_c_vir * p_cmd_cfg->img_h_o_c_vir * 2;
+
+    // malloc buffers
+    MppBuffer srcbuf;
+    MppBuffer dstbuf;
+    MppBuffer dstbuf_c;
+    MppBuffer histbuf;
+    void *psrc = NULL;
+    void *pdst = NULL;
+    void *phist = NULL;
+    RK_S32 fdsrc = -1;
+    RK_S32 fddst = -1;
+    RK_S32 fdhist = -1;
+    int frame_idx = 0;
+    MppBufferGroup memGroup;
+    MPP_RET ret = mpp_buffer_group_get_internal(&memGroup, MPP_BUFFER_TYPE_DRM);
+    if (MPP_OK != ret) {
+        mpp_err("memGroup mpp_buffer_group_get failed\n");
+        return NULL;
+    }
+
+    mpp_buffer_get(memGroup, &srcbuf, srcfrmsize);
+    mpp_buffer_get(memGroup, &dstbuf, dstfrmsize);
+    mpp_buffer_get(memGroup, &dstbuf_c, dstfrmsize_c);
+    mpp_buffer_get(memGroup, &histbuf, VDPP_HIST_LENGTH);
+    psrc    = mpp_buffer_get_ptr(srcbuf);
+    pdst    = mpp_buffer_get_ptr(dstbuf);
+    phist   = mpp_buffer_get_ptr(histbuf);
+
+    fdsrc   = mpp_buffer_get_fd(srcbuf);
+    fddst   = mpp_buffer_get_fd(dstbuf);
+    fdhist  = mpp_buffer_get_fd(histbuf);
+
+    hwpq_vdpp_init(&vdpp_ctx);
+
+    ctx->chn = info->chn;
+
+    ctx->fp_i = fopen(p_cmd_cfg->src_file_name, "rb");
+    if (!ctx->fp_i) {
+        mpp_err("failed to open file %s", p_cmd_cfg->src_file_name);
+        goto __RET;
+    }
+
+    ctx->fp_o_y = fopen(p_cmd_cfg->dst_file_name_y, "wb");
+    ctx->fp_o_uv = fopen(p_cmd_cfg->dst_file_name_uv, "wb");
+    ctx->fp_o_h = fopen(p_cmd_cfg->dst_file_name_hist, "wb");
+
+    while (1) {
+        vdpp_proc_cfg.frame_idx = frame_idx;
+
+        if ((srcfrmsize > fread(psrc, 1, srcfrmsize, ctx->fp_i)) || feof(ctx->fp_i)) {
+            ctx->frm_eos = 1;
+
+            if (p_cmd_cfg->frame_num < 0 || frame_idx < p_cmd_cfg->frame_num) {
+                clearerr(ctx->fp_i);
+                rewind(ctx->fp_i);
+                ctx->frm_eos = 0;
+                mpp_log("chn %d loop times %d\n", ctx->chn, ++ctx->loop_times);
+                continue;
+            }
+            mpp_log("chn %d found last frame. feof %d\n", ctx->chn, feof(ctx->fp_i));
+        } else if (ret == MPP_ERR_VALUE)
+            break;
+
+        vdpp_proc_cfg.src_img_info.img_fmt = VDPP_FMT_NV12;
+        vdpp_proc_cfg.src_img_info.img_yrgb.fd = fdsrc;
+        vdpp_proc_cfg.src_img_info.img_yrgb.addr = psrc;
+        vdpp_proc_cfg.src_img_info.img_yrgb.offset = 0;
+        vdpp_proc_cfg.src_img_info.img_yrgb.w_vld = p_cmd_cfg->img_w_i;
+        vdpp_proc_cfg.src_img_info.img_yrgb.h_vld = p_cmd_cfg->img_h_i;
+        vdpp_proc_cfg.src_img_info.img_yrgb.w_vir = p_cmd_cfg->img_w_i_vir;
+        vdpp_proc_cfg.src_img_info.img_yrgb.h_vir = p_cmd_cfg->img_h_i_vir;
+
+        vdpp_proc_cfg.src_img_info.img_cbcr.fd = fdsrc;
+        vdpp_proc_cfg.src_img_info.img_cbcr.addr = psrc;
+        vdpp_proc_cfg.src_img_info.img_cbcr.offset = p_cmd_cfg->img_w_i_vir * p_cmd_cfg->img_h_i_vir;
+        vdpp_proc_cfg.src_img_info.img_cbcr.w_vld = p_cmd_cfg->img_w_i / 2;
+        vdpp_proc_cfg.src_img_info.img_cbcr.h_vld = p_cmd_cfg->img_h_i / 2;
+        vdpp_proc_cfg.src_img_info.img_cbcr.w_vir = p_cmd_cfg->img_w_i_vir;
+        vdpp_proc_cfg.src_img_info.img_cbcr.h_vir = p_cmd_cfg->img_h_i_vir / 2;
+
+        vdpp_proc_cfg.dst_img_info.img_fmt = VDPP_FMT_NV24;
+        vdpp_proc_cfg.dst_img_info.img_yrgb.fd = fddst;
+        vdpp_proc_cfg.dst_img_info.img_yrgb.addr = pdst;
+        vdpp_proc_cfg.dst_img_info.img_yrgb.offset = 0;
+        vdpp_proc_cfg.dst_img_info.img_yrgb.w_vld = p_cmd_cfg->img_w_o;
+        vdpp_proc_cfg.dst_img_info.img_yrgb.h_vld = p_cmd_cfg->img_h_o;
+        vdpp_proc_cfg.dst_img_info.img_yrgb.w_vir = p_cmd_cfg->img_w_o_vir;
+        vdpp_proc_cfg.dst_img_info.img_yrgb.h_vir = p_cmd_cfg->img_h_o_vir;
+
+        vdpp_proc_cfg.dst_img_info.img_cbcr.fd = fddst;
+        vdpp_proc_cfg.dst_img_info.img_cbcr.addr = pdst;
+        vdpp_proc_cfg.dst_img_info.img_cbcr.offset = p_cmd_cfg->img_w_o_vir * p_cmd_cfg->img_h_o_vir;
+        vdpp_proc_cfg.dst_img_info.img_cbcr.w_vld = p_cmd_cfg->img_w_o_c;
+        vdpp_proc_cfg.dst_img_info.img_cbcr.h_vld = p_cmd_cfg->img_h_o_c;
+        vdpp_proc_cfg.dst_img_info.img_cbcr.w_vir = p_cmd_cfg->img_w_o_c_vir;
+        vdpp_proc_cfg.dst_img_info.img_cbcr.h_vir = p_cmd_cfg->img_h_o_c_vir;
+
+        {
+            int work_mode_ref = hwpq_vdpp_check_work_mode(vdpp_ctx, &vdpp_proc_cfg);
+
+            vdpp_proc_cfg.hist_mode_en = (VDPP_RUN_MODE_HIST == p_cmd_cfg->work_mode) ||
+                                         (VDPP_RUN_MODE_HIST == work_mode_ref);
+        }
+
+        vdpp_proc_cfg.hist_buf_fd = fdhist;
+        vdpp_proc_cfg.p_hist_buf = phist;
+
+        vdpp_proc_cfg.yuv_diff_flag = 0;
+        vdpp_proc_cfg.vdpp_config_update_flag = 0;
+
+        hwpq_vdpp_proc(vdpp_ctx, &vdpp_proc_cfg);
+
+        if (ctx->fp_o_y)
+            fwrite(vdpp_proc_cfg.dst_img_info.img_yrgb.addr, 1, p_cmd_cfg->img_w_o_vir * p_cmd_cfg->img_h_o_vir * 1, ctx->fp_o_y);
+        if (ctx->fp_o_uv)
+            fwrite((unsigned char*)vdpp_proc_cfg.dst_img_info.img_cbcr.addr + p_cmd_cfg->img_w_o_vir * p_cmd_cfg->img_h_o_vir, 1, p_cmd_cfg->img_w_o_c_vir * p_cmd_cfg->img_h_o_c_vir * 2, ctx->fp_o_uv);
+        if (ctx->fp_o_h)
+            fwrite(vdpp_proc_cfg.p_hist_buf, 1, VDPP_HIST_LENGTH, ctx->fp_o_h);
+
+        frame_idx++;
+
+        if (p_cmd_cfg->frame_num > 0 && frame_idx >= p_cmd_cfg->frame_num) {
+            ctx->frm_eos = 1;
+            break;
+        }
+
+        if (ctx->frm_eos)
+            break;
+    }
+
+__RET:
+    if (ctx->fp_i) {
+        fclose(ctx->fp_i);
+        ctx->fp_i = NULL;
+    }
+    if (ctx->fp_o_y) {
+        fclose(ctx->fp_o_y);
+        ctx->fp_o_y = NULL;
+    }
+    if (ctx->fp_o_uv) {
+        fclose(ctx->fp_o_uv);
+        ctx->fp_o_uv = NULL;
+    }
+    if (ctx->fp_o_h) {
+        fclose(ctx->fp_o_h);
+        ctx->fp_o_h = NULL;
+    }
+
+    mpp_buffer_put(srcbuf);
+    mpp_buffer_put(dstbuf);
+    mpp_buffer_put(histbuf);
+    mpp_buffer_put(dstbuf_c);
+
+    if (memGroup) {
+        mpp_buffer_group_put(memGroup);
+        memGroup = NULL;
+    }
+
+    hwpq_vdpp_deinit(vdpp_ctx);
+
+    return NULL;
+}
+
+int32_t main(int argc, char **argv)
+{
+    VdppCmdCfg vdpp_cmd_cfg;
+    VdppCmdCfg *p_cmd_cfg = &vdpp_cmd_cfg;
+    VdppTestMultiCtxInfo *ctxs = NULL;
+    int i = 0;
+    int ret = 0;
+
+    parse_cmd(argv, argc, p_cmd_cfg);
+
+    ctxs = mpp_calloc(VdppTestMultiCtxInfo, p_cmd_cfg->nthreads);
+    if (NULL == ctxs) {
+        mpp_err("failed to alloc context for instances\n");
+        ret = MPP_ERR_MALLOC;
+        goto __RET;
+    }
+
+    for (i = 0; i < p_cmd_cfg->nthreads; i++) {
+        ctxs[i].cmd = p_cmd_cfg;
+        ctxs[i].chn = i;
+
+        ret = pthread_create(&ctxs[i].thd, NULL, multi_vdpp, &ctxs[i]);
+        if (ret) {
+            mpp_err("failed to create thread %d\n", i);
+            ret = MPP_NOK;
+            goto __RET;
+        }
+    }
+
+    for (i = 0; i < p_cmd_cfg->nthreads; i++)
+        pthread_join(ctxs[i].thd, NULL);
+
+__RET:
+    MPP_FREE(ctxs);
+    ctxs = NULL;
+
+    return ret;
+}
+
+static void parse_cmd(char** argv, int argc, VdppCmdCfg* p_cmd_cfg)
+{
+    mpp_log("in parse 3\n");
+    int32_t ch;
+    int32_t option_index = 0;
+
+    opterr = 0;
+    static struct option long_options[] = {
+        {"ip",         required_argument, 0,  0 },
+        {"oy",         required_argument, 0,  0 },
+        {"oc",         required_argument, 0,  0 },
+        {"oh",         required_argument, 0,  0 },
+        {"wi_vld",     required_argument, 0,  0 },
+        {"hi_vld",     required_argument, 0,  0 },
+        {"wi_vir",     required_argument, 0,  0 },
+        {"hi_vir",     required_argument, 0,  0 },
+        {"wo_vld",     required_argument, 0,  0 },
+        {"ho_vld",     required_argument, 0,  0 },
+        {"wo_vir",     required_argument, 0,  0 },
+        {"ho_vir",     required_argument, 0,  0 },
+        {"uv_diff",    required_argument, 0,  0 },
+        {"wo_uv",      required_argument, 0,  0 },
+        {"ho_uv",      required_argument, 0,  0 },
+        {"wo_uv_vir",  required_argument, 0,  0 },
+        {"ho_uv_vir",  required_argument, 0,  0 },
+        {"work_mode",  required_argument, 0,  0 },
+        {"nthread",    required_argument, 0,  0 },
+        {"frame_num",  required_argument, 0,  0 },
+        { 0,           0,                 0,  0 },
+    };
+
+    p_cmd_cfg->nthreads = 1;
+
+    while ((ch = getopt_long_only(argc, argv, "", long_options, &option_index)) != -1) {
+        switch (ch) {
+        case 0: {
+            switch (option_index) {
+            case 0 : {
+                strncpy(p_cmd_cfg->src_file_name, optarg, sizeof(p_cmd_cfg->src_file_name) - 1);
+                mpp_log("ssrc file name: %s\n", p_cmd_cfg->src_file_name);
+            } break;
+            case 1 : {
+                strncpy(p_cmd_cfg->dst_file_name_y, optarg, sizeof(p_cmd_cfg->dst_file_name_y) - 1);
+                mpp_log("ddst-Y file name: %s\n", p_cmd_cfg->dst_file_name_y);
+            } break;
+            case 2 : {
+                strncpy(p_cmd_cfg->dst_file_name_uv, optarg, sizeof(p_cmd_cfg->dst_file_name_uv) - 1);
+                mpp_log("ddst-UV file name: %s\n", p_cmd_cfg->dst_file_name_uv);
+            } break;
+            case 3 : {
+                strncpy(p_cmd_cfg->dst_file_name_hist, optarg, sizeof(p_cmd_cfg->dst_file_name_hist) - 1);
+                mpp_log("ddst-Hist file name: %s\n", p_cmd_cfg->dst_file_name_hist);
+            } break;
+            case 4 : {
+                p_cmd_cfg->img_w_i = atoi(optarg);
+            } break;
+            case 5 : {
+                p_cmd_cfg->img_h_i = atoi(optarg);
+            } break;
+            case 6 : {
+                p_cmd_cfg->img_w_i_vir = atoi(optarg);
+            } break;
+            case 7 : {
+                p_cmd_cfg->img_h_i_vir = atoi(optarg);
+            } break;
+            case 8 : {
+                p_cmd_cfg->img_w_o = atoi(optarg);
+            } break;
+            case 9 : {
+                p_cmd_cfg->img_h_o = atoi(optarg);
+            } break;
+            case 10 : {
+                p_cmd_cfg->img_w_o_vir = atoi(optarg);
+            } break;
+            case 11 : {
+                p_cmd_cfg->img_h_o_vir = atoi(optarg);
+            } break;
+            case 12 : {
+                p_cmd_cfg->uv_diff_flag = atoi(optarg);
+            } break;
+            case 13 : {
+                p_cmd_cfg->img_w_o_c = atoi(optarg);
+            } break;
+            case 14 : {
+                p_cmd_cfg->img_h_o_c = atoi(optarg);
+            } break;
+            case 15 : {
+                p_cmd_cfg->img_w_o_c_vir = atoi(optarg);
+            } break;
+            case 16 : {
+                p_cmd_cfg->img_h_o_c_vir = atoi(optarg);
+            } break;
+            case 17 : {
+                p_cmd_cfg->work_mode = atoi(optarg);
+            } break;
+            case 18 : {
+                p_cmd_cfg->nthreads = atoi(optarg);
+                if (p_cmd_cfg->nthreads < 1)
+                    p_cmd_cfg->nthreads = 1;
+            } break;
+            case 19: {
+                p_cmd_cfg->frame_num = atoi(optarg);
+            } break;
+            default : {
+            } break;
+            }
+            mpp_log("%s: %s", long_options[option_index].name, optarg);
+
+        } break;
+        default: {
+        } break;
+        }
+    }
+}
diff --git a/mpp/vproc/vdpp/test/vdpp_test.c b/mpp/vproc/vdpp/test/vdpp_test.c
new file mode 100644
index 000000000..f7bb31a3c
--- /dev/null
+++ b/mpp/vproc/vdpp/test/vdpp_test.c
@@ -0,0 +1,681 @@
+/* SPDX-License-Identifier: Apache-2.0 OR MIT */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#define MODULE_TAG "vdpp_test"
+
+#include <getopt.h>
+#include <string.h>
+#include <errno.h>
+
+#include "mpp_mem.h"
+#include "mpp_common.h"
+#include "mpp_buffer.h"
+#include "mpp_soc.h"
+
+#include "utils.h"
+#include "vdpp_api.h"
+
+#define MAX_URL_LEN        (256)
+
+#define SHP_CFG_STRIDE     (684)
+#define DM_ZME_CFG_STRIDE  (260)
+#define ES_CFG_STRIDE      (68)
+#define YUV_MAX_SIZE       (12582912) // 4096 * 2048 * 3 / 2
+#define DCI_HIST_SIZE      (10240)    // (16*16*16*18/8/4 + 256) * 4
+
+typedef struct VdppTestCfg_t {
+    MppFrameFormat src_format;
+    RK_U32      src_width;
+    RK_U32      src_height;
+    RK_U32      src_width_vir;  // 16 align
+    RK_U32      src_height_vir; // 8 align
+    RK_U32      src_swa;
+
+    RK_U32      dst_width;
+    RK_U32      dst_height;
+    RK_U32      dst_width_vir;
+    RK_U32      dst_height_vir;
+    RK_U32      dst_fmt;
+    RK_U32      dst_swa;
+    RK_U32      yuv_out_diff;
+    RK_U32      dst_c_width;
+    RK_U32      dst_c_height;
+    RK_U32      dst_c_width_vir;
+    RK_U32      dst_c_height_vir;
+    /* high 16 bit: mask; low 3 bit: dmsr|es|sharp */
+    RK_U32      cfg_set;
+
+    char        src_url[MAX_URL_LEN];
+    char        dst_url[MAX_URL_LEN];
+    char        dst_c_url[MAX_URL_LEN];
+    char        hist_url[MAX_URL_LEN];
+    char        hist_l_url[MAX_URL_LEN];
+    char        hist_g_url[MAX_URL_LEN];
+    char        slt_url[MAX_URL_LEN];
+
+    FILE        *fp_src;
+    FILE        *fp_dst;
+    FILE        *fp_dst_c;
+    FILE        *fp_hist;
+    FILE        *fp_hist_l;
+    FILE        *fp_hist_g;
+    FILE        *fp_slt;
+
+    RK_U32      frame_num;
+
+    RK_U32      hist_mode_en;
+} VdppTestCfg;
+
+typedef struct {
+    MppFrameFormat  format;
+    const char      *name;
+} MppFrameFormatInfo;
+
+extern void mpp_show_color_format();
+
+static OptionInfo vdpp_test_cmd[] = {
+    {"w",         "src_width",        "input image width"},
+    {"h",         "src_height",       "input image height"},
+    {"s",         "src_swap",         "input image UV swap"},
+    {"f",         "src_format",       "input image format in MppFrameFormat"},
+    {"i",         "src_file",         "input image file name"},
+    {"W",         "dst_width",        "output image width"},
+    {"H",         "dst_height",       "output image height"},
+    {"F",         "dst_format",       "output image format in ASCII string"},
+    {"S",         "dst_swap",         "output image UV swap"},
+    {"o",         "dst_file",         "output image file name"},
+    {"n",         "frame_num",        "frame number"},
+    {"m",         "work_mode",        "work_mode : 0 - vdpp, 1 - dci hist"},
+    {"Y",         "packed_hist",      "output packed hist file name"},
+    {"O",         "dst_chroma_file",  "output chroma file name"},
+    {"wi_vir",    "src_width_vir",    "input virtual width"},
+    {"hi_vir",    "src_height_vir",   "input virtual height"},
+    {"wo_vir",    "dst_width_vir",    "output virtual width"},
+    {"ho_vir",    "dst_height_vir",   "output virtual height"},
+    {"wo_uv",     "dst_c_width",      "output chroma width"},
+    {"ho_uv",     "dst_c_height",     "output chroma height"},
+    {"wo_uv_vir", "dst_c_width_vir",  "output virtual chroma width"},
+    {"ho_uv_vir", "dst_c_height_vir", "output virtual chroma height"},
+    {"diff",      "yuv_out_diff",     "luma and chroma diff resolution flag"},
+    {"cfg_set",   "cfg_set",          "high 16 bit: mask; low 3 bit: dmsr|es|sharp"},
+    {"hist_l",    "local_hist",       "output local hist file name"},
+    {"hist_g",    "global_hist",      "output global hist file name"},
+    {"slt",       "slt_file",         "slt verify data file"},
+};
+
+static void vdpp_test_help()
+{
+    mpp_log("usage: vdpp_test [options]\n");
+    mpp_log("*******************************\n");
+    show_options(vdpp_test_cmd);
+    mpp_show_color_format();
+    mpp_log("*******************************\n");
+    mpp_log("supported ASCII format strings:\n");
+    mpp_log("1 - yuv444\n");
+    mpp_log("2 - yuv420 \n");
+    mpp_log("************ sample ***********\n");
+    mpp_log("vdpp_test -w 720 -h 480 -s 0 -i input.yuv -W 1920 -H 1080 -F yuv444 -S 0 -o output.yuv -n 1\n");
+}
+
+static RK_S32 str_to_vdpp_fmt(const char *str)
+{
+    RK_S32 fmt = -1;
+
+    mpp_log("format %s\n", str);
+
+    if (!strcmp(str, "yuv420"))
+        fmt = VDPP_FMT_YUV420;
+    else if (!strcmp(str, "yuv444"))
+        fmt = VDPP_FMT_YUV444;
+    else
+        mpp_err("invalid format %s\n", str);
+
+    return fmt;
+}
+
+static MPP_RET check_input_cmd(VdppTestCfg *cfg)
+{
+    MPP_RET ret = MPP_OK;
+
+    if (cfg->fp_src == NULL) {
+        mpp_err("failed to open input file %s\n", cfg->src_url);
+        ret = MPP_NOK;
+    }
+
+    return ret;
+}
+
+static inline size_t get_src_frm_size(RK_S32 fmt, RK_U32 w, RK_U32 h)
+{
+    RK_S32 frame_size;
+
+    switch (fmt & MPP_FRAME_FMT_MASK) {
+    case MPP_FMT_YUV420SP:
+    case MPP_FMT_YUV420P: {
+        frame_size = w * h * 3 / 2;
+    } break;
+
+    case MPP_FMT_YUV422_YUYV :
+    case MPP_FMT_YUV422_YVYU :
+    case MPP_FMT_YUV422_UYVY :
+    case MPP_FMT_YUV422_VYUY :
+    case MPP_FMT_YUV422P :
+    case MPP_FMT_YUV422SP :
+    case MPP_FMT_RGB444 :
+    case MPP_FMT_BGR444 :
+    case MPP_FMT_RGB555 :
+    case MPP_FMT_BGR555 :
+    case MPP_FMT_RGB565 :
+    case MPP_FMT_BGR565 : {
+        frame_size = w * h * 2;
+    } break;
+    case MPP_FMT_RGB888 :
+    case MPP_FMT_BGR888 : {
+        frame_size = w * h * 3;
+    } break;
+    case MPP_FMT_RGB101010 :
+    case MPP_FMT_BGR101010 :
+    case MPP_FMT_ARGB8888 :
+    case MPP_FMT_ABGR8888 :
+    case MPP_FMT_BGRA8888 :
+    case MPP_FMT_RGBA8888 : {
+        frame_size = w * h * 4;
+    } break;
+    default: {
+        frame_size = w * h * 4;
+    } break;
+    }
+
+    return frame_size;
+}
+
+static inline size_t get_dst_frm_size(RK_S32 fmt, RK_U32 w, RK_U32 h)
+{
+    switch (fmt) {
+    case VDPP_FMT_YUV444:
+        return w * h * 3;
+    case VDPP_FMT_YUV420:
+        return w * h * 3 / 2;
+    default:
+        mpp_err("warning: unsupported input format %d", fmt);
+        return 0;
+    }
+}
+
+static void vdpp_test_set_img(vdpp_com_ctx *ctx, RK_U32 w, RK_U32 h,
+                              VdppImg *img, RK_S32 fd, VdppCmd cmd)
+{
+    RK_S32 y_size = w * h;
+
+    img->mem_addr = fd;
+    img->uv_addr = fd;
+    img->uv_off = y_size;
+
+    MPP_RET ret = ctx->ops->control(ctx->priv, cmd, img);
+    if (ret)
+        mpp_log_f("control %08x failed %d\n", cmd, ret);
+}
+
+void vdpp_test(VdppTestCfg *cfg)
+{
+    vdpp_com_ctx* vdpp = rockchip_vdpp_api_alloc_ctx();
+    size_t srcfrmsize = get_src_frm_size(cfg->src_format, cfg->src_width_vir, cfg->src_height_vir);
+    size_t dstfrmsize = get_dst_frm_size(cfg->dst_fmt, cfg->dst_width_vir, cfg->dst_height_vir);
+    size_t dstfrmsize_c = cfg->dst_c_width_vir * cfg->dst_c_height_vir * 3;
+    MppBuffer srcbuf;
+    MppBuffer dstbuf;
+    MppBuffer dstbuf_c;
+    MppBuffer histbuf;
+    MppBuffer histbuf_l;
+    MppBuffer histbuf_g;
+    RK_U8 *psrc = NULL;
+    RK_U8 *pdst = NULL;
+    RK_U8 *pdst_c = NULL;
+    RK_U8 *phist = NULL;
+    RK_U8 *phist_l = NULL;
+    RK_U8 *phist_g = NULL;
+    RK_S32 fdsrc = -1;
+    RK_S32 fddst = -1;
+    RK_S32 fddst_c = -1;
+    RK_S32 fdhist = -1;
+    struct vdpp_api_params params;
+    RK_U32 is_vdpp2 = (mpp_get_soc_type() == ROCKCHIP_SOC_RK3576);
+    RK_U32 yuv_out_diff = (cfg->yuv_out_diff && is_vdpp2);
+
+    VdppImg imgsrc;
+    VdppImg imgdst;
+    VdppImg imgdst_c;
+
+    RK_U32 local_hist_size  = RKVOP_PQ_PREPROCESS_HIST_SIZE_VERI * RKVOP_PQ_PREPROCESS_HIST_SIZE_HORI *
+                              RKVOP_PQ_PREPROCESS_LOCAL_HIST_BIN_NUMS * sizeof(RK_U32);
+    RK_U32 global_hist_size = RKVOP_PQ_PREPROCESS_GLOBAL_HIST_BIN_NUMS * sizeof(RK_U32);
+
+    mpp_assert(vdpp);
+    MppBufferGroup memGroup;
+    MPP_RET ret = MPP_NOK;
+    RK_U32 cnt = 0;
+    DataCrc checkcrc;
+
+    memset(&checkcrc, 0, sizeof(checkcrc));
+    checkcrc.sum = mpp_malloc(RK_ULONG, 512);
+
+    ret = mpp_buffer_group_get_internal(&memGroup, MPP_BUFFER_TYPE_DRM);
+    if (MPP_OK != ret) {
+        mpp_err("memGroup mpp_buffer_group_get failed\n");
+        mpp_assert(0);
+    }
+
+    mpp_log("src w:h [%d:%d] stride [%d:%d] require buf %d",
+            cfg->src_width, cfg->src_height, cfg->src_width_vir, cfg->src_height_vir, srcfrmsize);
+    mpp_log("dst w:h [%d:%d] stride [%d:%d] require buf %d",
+            cfg->dst_width, cfg->dst_height, cfg->dst_width_vir, cfg->dst_height_vir, dstfrmsize);
+    mpp_buffer_get(memGroup, &srcbuf, srcfrmsize);
+    mpp_buffer_get(memGroup, &dstbuf, dstfrmsize);
+    mpp_buffer_get(memGroup, &histbuf, DCI_HIST_SIZE);
+    mpp_assert(srcbuf && dstbuf && histbuf);
+
+    mpp_buffer_get(memGroup, &histbuf_l, local_hist_size);
+    mpp_buffer_get(memGroup, &histbuf_g, global_hist_size);
+    mpp_assert(histbuf_l && histbuf_g);
+
+    psrc = mpp_buffer_get_ptr(srcbuf);
+    pdst = mpp_buffer_get_ptr(dstbuf);
+    phist = mpp_buffer_get_ptr(histbuf);
+    phist_l = mpp_buffer_get_ptr(histbuf_l);
+    phist_g = mpp_buffer_get_ptr(histbuf_g);
+
+    fdsrc = mpp_buffer_get_fd(srcbuf);
+    fddst = mpp_buffer_get_fd(dstbuf);
+    fdhist = mpp_buffer_get_fd(histbuf);
+
+    if (yuv_out_diff) {
+        mpp_log("dst chroma w:h [%d:%d] stride [%d:%d] require buf %d",
+                cfg->dst_c_width, cfg->dst_c_height, cfg->dst_c_width_vir, cfg->dst_c_height_vir, dstfrmsize_c);
+
+        mpp_buffer_get(memGroup, &dstbuf_c, dstfrmsize_c);
+        mpp_assert(dstbuf_c);
+
+        pdst_c = mpp_buffer_get_ptr(dstbuf_c);
+        fddst_c = mpp_buffer_get_fd(dstbuf_c);
+    }
+
+    vdpp->ops->init(&vdpp->priv);
+
+    /* use default dmsr and zme params */
+    /* set common params */
+    if (is_vdpp2) {
+        params.ptype = VDPP_PARAM_TYPE_COM2;
+        memset(&params.param, 0, sizeof(union vdpp_api_content));
+        params.param.com2.sfmt = cfg->src_format;
+        params.param.com2.src_width = cfg->src_width;
+        params.param.com2.src_height = cfg->src_height;
+        params.param.com2.src_width_vir = cfg->src_width_vir;
+        params.param.com2.src_height_vir = cfg->src_height_vir;
+        params.param.com2.sswap = cfg->src_swa;
+        params.param.com2.dfmt = cfg->dst_fmt;
+        params.param.com2.dst_width = cfg->dst_width;
+        params.param.com2.dst_height = cfg->dst_height;
+        params.param.com2.dst_width_vir = cfg->dst_width_vir;
+        params.param.com2.dst_height_vir = cfg->dst_height_vir;
+        if (yuv_out_diff) {
+            params.param.com2.yuv_out_diff = yuv_out_diff;
+            params.param.com2.dst_c_width = cfg->dst_c_width;
+            params.param.com2.dst_c_height = cfg->dst_c_height;
+            params.param.com2.dst_c_width_vir = cfg->dst_c_width_vir;
+            params.param.com2.dst_c_height_vir = cfg->dst_c_height_vir;
+        }
+        params.param.com2.dswap = cfg->dst_swa;
+        params.param.com2.hist_mode_en = cfg->hist_mode_en;
+        params.param.com2.cfg_set = cfg->cfg_set;
+        vdpp->ops->control(vdpp->priv, VDPP_CMD_SET_COM2_CFG, &params);
+    } else {
+        params.ptype = VDPP_PARAM_TYPE_COM;
+        memset(&params.param, 0, sizeof(union vdpp_api_content));
+        params.param.com.src_width = cfg->src_width;
+        params.param.com.src_height = cfg->src_height;
+        params.param.com.sswap = cfg->src_swa;
+        params.param.com.dfmt = cfg->dst_fmt;
+        params.param.com.dst_width = cfg->dst_width;
+        params.param.com.dst_height = cfg->dst_height;
+        params.param.com.dswap = cfg->dst_swa;
+        vdpp->ops->control(vdpp->priv, VDPP_CMD_SET_COM_CFG, &params);
+    }
+
+    {
+        RK_S32 cap = vdpp->ops->check_cap(vdpp->priv);
+
+        mpp_log("vdpp cap %d\n", cap);
+    }
+
+    while (1) {
+        if (srcfrmsize > fread(psrc, 1, srcfrmsize, cfg->fp_src)) {
+            mpp_log("source exhaused\n");
+            break;
+        }
+        if (cnt >= cfg->frame_num)
+            break;
+
+        /* notice the order of the input frames */
+        vdpp_test_set_img(vdpp, cfg->src_width_vir, cfg->src_height_vir,
+                          &imgsrc, fdsrc, VDPP_CMD_SET_SRC);
+        vdpp_test_set_img(vdpp, cfg->dst_width_vir, cfg->dst_height_vir,
+                          &imgdst, fddst, VDPP_CMD_SET_DST);
+        if (yuv_out_diff)
+            vdpp_test_set_img(vdpp, cfg->dst_c_width_vir, cfg->dst_c_height_vir,
+                              &imgdst_c, fddst_c, VDPP_CMD_SET_DST_C);
+
+        if (is_vdpp2)
+            vdpp->ops->control(vdpp->priv, VDPP_CMD_SET_HIST_FD, &fdhist);
+
+        memset(pdst, 0, dstfrmsize);
+        memset(phist, 0, DCI_HIST_SIZE);
+
+        if (vdpp->ops->control(vdpp->priv, VDPP_CMD_RUN_SYNC, NULL)) {
+            mpp_err("found vdpp run error, exit!\n");
+            break;
+        }
+
+        cnt++;
+
+        if (cfg->fp_dst) {
+            if (dstfrmsize > fwrite(pdst, 1, dstfrmsize, cfg->fp_dst)) {
+                mpp_err("destination dump failed, errno %d %s\n", errno, strerror(errno));
+                break;
+            }
+        }
+
+        if (yuv_out_diff && cfg->fp_dst_c) {
+            if (dstfrmsize_c > fwrite(pdst_c, 1, dstfrmsize_c, cfg->fp_dst_c)) {
+                mpp_err("chroma dump failed, errno %d %s\n", errno, strerror(errno));
+                break;
+            }
+        }
+
+        if (cfg->fp_hist) {
+            if (DCI_HIST_SIZE > fwrite(phist, 1, DCI_HIST_SIZE, cfg->fp_hist)) {
+                mpp_err("packed hist dump err\n");
+                break;
+            }
+        }
+
+        memset(phist_l, 0, local_hist_size);
+        memset(phist_g, 0, global_hist_size);
+
+        dci_hist_info_parser(phist, (RK_U32 *)phist_l, (RK_U32 *)phist_g);
+
+        if (cfg->fp_hist_l) {
+            if (local_hist_size > fwrite(phist_l, 1, local_hist_size, cfg->fp_hist_l)) {
+                mpp_err("local hist dump err\n");
+                break;
+            }
+        }
+        if (cfg->fp_hist_g) {
+            if (global_hist_size > fwrite(phist_g, 1, global_hist_size, cfg->fp_hist_g)) {
+                mpp_err("global hist dump err\n");
+                break;
+            }
+        }
+
+        if (cfg->fp_slt) {
+            if (pdst && !cfg->hist_mode_en) {
+                calc_data_crc(pdst, dstfrmsize, &checkcrc);
+                write_data_crc(cfg->fp_slt, &checkcrc);
+
+            }
+
+            if (pdst_c && yuv_out_diff && !cfg->hist_mode_en) {
+                calc_data_crc(pdst_c, dstfrmsize_c, &checkcrc);
+                write_data_crc(cfg->fp_slt, &checkcrc);
+
+            }
+
+            if (phist) {
+                calc_data_crc(phist, DCI_HIST_SIZE, &checkcrc);
+                write_data_crc(cfg->fp_slt, &checkcrc);
+            }
+        }
+
+    }
+
+    mpp_buffer_put(srcbuf);
+    mpp_buffer_put(dstbuf);
+    mpp_buffer_put(histbuf);
+    if (histbuf_l)
+        mpp_buffer_put(histbuf_l);
+    if (histbuf_g)
+        mpp_buffer_put(histbuf_g);
+    if (yuv_out_diff)
+        mpp_buffer_put(dstbuf_c);
+
+    MPP_FREE(checkcrc.sum);
+
+    if (memGroup) {
+        mpp_buffer_group_put(memGroup);
+        memGroup = NULL;
+    }
+
+    vdpp->ops->deinit(vdpp->priv);
+
+    rockchip_vdpp_api_release_ctx(vdpp);
+}
+
+extern char *optarg;
+extern int   opterr;
+
+int32_t main(int32_t argc, char **argv)
+{
+    VdppTestCfg cfg;
+    int32_t ch;
+    int32_t option_index = 0;
+
+    if (argc < 2) {
+        vdpp_test_help();
+        return 0;
+    }
+
+    memset(&cfg, 0, sizeof(cfg));
+    cfg.src_swa = VDPP_YUV_SWAP_SP_UV;
+    cfg.dst_fmt = VDPP_FMT_YUV444;
+    cfg.dst_swa = VDPP_YUV_SWAP_SP_UV;
+    cfg.hist_mode_en = 0;
+
+    /* get options */
+    opterr = 0;
+    /* not recommended if not familiar with HW */
+    static struct option long_options[] = {
+        {"wi_vir",     required_argument, 0,  0 },
+        {"hi_vir",     required_argument, 0,  0 },
+        {"wo_vir",     required_argument, 0,  0 },
+        {"ho_vir",     required_argument, 0,  0 },
+        {"wo_uv",      required_argument, 0,  0 },
+        {"ho_uv",      required_argument, 0,  0 },
+        {"wo_uv_vir",  required_argument, 0,  0 },
+        {"ho_uv_vir",  required_argument, 0,  0 },
+        {"diff",       required_argument, 0,  0 },
+        {"cfg_set",    required_argument, 0,  0 },
+        {"hist_l",     required_argument, 0,  0 },
+        {"hist_g",     required_argument, 0,  0 },
+        {"slt",        required_argument, 0,  0 },
+        { 0,           0,                 0,  0 },
+    };
+
+    while ((ch = getopt_long_only(argc, argv, "w:h:f:s:i:W:H:F:S:o:O:n:m:Y:", long_options, &option_index)) != -1) {
+        switch (ch) {
+        case 0: {
+            switch (option_index) {
+            case 0 : {
+                cfg.src_width_vir = atoi(optarg);
+            } break;
+            case 1 : {
+                cfg.src_height_vir = atoi(optarg);
+            } break;
+            case 2 : {
+                cfg.dst_width_vir = atoi(optarg);
+            } break;
+            case 3 : {
+                cfg.dst_height_vir = atoi(optarg);
+            } break;
+            case 4 : {
+                cfg.dst_c_width = atoi(optarg);
+            } break;
+            case 5 : {
+                cfg.dst_c_height = atoi(optarg);
+            } break;
+            case 6 : {
+                cfg.dst_c_width_vir = atoi(optarg);
+            } break;
+            case 7 : {
+                cfg.dst_c_height_vir = atoi(optarg);
+            } break;
+            case 8 : {
+                cfg.yuv_out_diff = atoi(optarg);
+            } break;
+            case 9 : {
+                cfg.cfg_set = strtol(optarg, NULL, 0);
+            } break;
+            case 10 : {
+                mpp_log("local hist name: %s\n", optarg);
+                strncpy(cfg.hist_l_url, optarg, sizeof(cfg.hist_l_url) - 1);
+                cfg.fp_hist_l = fopen(cfg.hist_l_url, "w+b");
+            } break;
+            case 11 : {
+                mpp_log("global hist name: %s\n", optarg);
+                strncpy(cfg.hist_g_url, optarg, sizeof(cfg.hist_g_url) - 1);
+                cfg.fp_hist_g = fopen(cfg.hist_g_url, "w+b");
+            } break;
+            case 12 : {
+                mpp_log("verify file: %s\n", optarg);
+                strncpy(cfg.slt_url, optarg, sizeof(cfg.slt_url) - 1);
+                cfg.fp_slt = fopen(cfg.slt_url, "w+b");
+            } break;
+            default : {
+            } break;
+            }
+            mpp_log("%s: %s", long_options[option_index].name, optarg);
+
+        } break;
+        case 'w': {
+            cfg.src_width = atoi(optarg);
+        } break;
+        case 'h': {
+            cfg.src_height = atoi(optarg);
+        } break;
+        case 'f': {
+            cfg.src_format = atoi(optarg);
+        } break;
+        case 's': {
+            cfg.src_swa = atoi(optarg);
+        } break;
+        case 'i': {
+            mpp_log("input filename: %s\n", optarg);
+            strncpy(cfg.src_url, optarg, sizeof(cfg.src_url) - 1);
+            cfg.fp_src = fopen(cfg.src_url, "rb");
+        } break;
+        case 'W': {
+            cfg.dst_width = atoi(optarg);
+        } break;
+        case 'H': {
+            cfg.dst_height = atoi(optarg);
+        } break;
+        case 'F': {
+            cfg.dst_fmt = str_to_vdpp_fmt(optarg);
+        } break;
+        case 'S': {
+            cfg.dst_swa = atoi(optarg);
+        } break;
+        case 'o': {
+            mpp_log("output filename: %s\n", optarg);
+            strncpy(cfg.dst_url, optarg, sizeof(cfg.dst_url) - 1);
+            cfg.fp_dst = fopen(cfg.dst_url, "w+b");
+        } break;
+        case 'O': {
+            mpp_log("output chroma filename: %s\n", optarg);
+            strncpy(cfg.dst_c_url, optarg, sizeof(cfg.dst_c_url) - 1);
+            cfg.fp_dst_c = fopen(cfg.dst_c_url, "w+b");
+        } break;
+        case 'n': {
+            cfg.frame_num = atoi(optarg);
+        } break;
+        case 'm': {
+            cfg.hist_mode_en = atoi(optarg);
+        } break;
+        case 'Y': {
+            mpp_log("output hist: %s\n", optarg);
+            strncpy(cfg.hist_url, optarg, sizeof(cfg.hist_url) - 1);
+            cfg.fp_hist = fopen(cfg.hist_url, "w+b");
+        } break;
+        default: {
+        } break;
+        }
+    }
+
+    /* set default vir stride */
+    if (!cfg.src_width_vir)
+        cfg.src_width_vir = MPP_ALIGN(cfg.src_width, 16);
+    if (!cfg.src_height_vir)
+        cfg.src_height_vir = MPP_ALIGN(cfg.src_height, 8);
+    if (!cfg.dst_width)
+        cfg.dst_width = cfg.src_width;
+    if (!cfg.dst_height)
+        cfg.dst_height = cfg.src_height;
+    if (!cfg.dst_width_vir)
+        cfg.dst_width_vir = MPP_ALIGN(cfg.dst_width, 16);
+    if (!cfg.dst_height_vir)
+        cfg.dst_height_vir = MPP_ALIGN(cfg.dst_height, 2);
+    if (cfg.yuv_out_diff) {
+        if (!cfg.dst_c_width)
+            cfg.dst_c_width = cfg.dst_width;
+        if (!cfg.dst_c_width_vir)
+            cfg.dst_c_width_vir = MPP_ALIGN(cfg.dst_c_width, 16);
+        if (!cfg.dst_c_height)
+            cfg.dst_c_height = cfg.dst_height;
+        if (!cfg.dst_c_height_vir)
+            cfg.dst_c_height_vir = MPP_ALIGN(cfg.dst_c_height, 2);
+    }
+    if (check_input_cmd(&cfg)) {
+        mpp_err("failed to pass cmd line check\n");
+        vdpp_test_help();
+        return -1;
+    }
+
+    vdpp_test(&cfg);
+
+    if (cfg.fp_src) {
+        fclose(cfg.fp_src);
+        cfg.fp_src = NULL;
+    }
+
+    if (cfg.fp_dst) {
+        fclose(cfg.fp_dst);
+        cfg.fp_dst = NULL;
+    }
+
+    if (cfg.fp_dst_c) {
+        fclose(cfg.fp_dst_c);
+        cfg.fp_dst_c = NULL;
+    }
+
+    if (cfg.fp_hist) {
+        fclose(cfg.fp_hist);
+        cfg.fp_hist = NULL;
+    }
+
+    if (cfg.fp_hist_l) {
+        fclose(cfg.fp_hist_l);
+        cfg.fp_hist_l = NULL;
+    }
+
+    if (cfg.fp_hist_g) {
+        fclose(cfg.fp_hist_g);
+        cfg.fp_hist_g = NULL;
+    }
+
+    if (cfg.fp_slt) {
+        fclose(cfg.fp_slt);
+        cfg.fp_slt = NULL;
+    }
+
+    return 0;
+}
diff --git a/mpp/vproc/vdpp/vdpp.c b/mpp/vproc/vdpp/vdpp.c
new file mode 100644
index 000000000..7666e4471
--- /dev/null
+++ b/mpp/vproc/vdpp/vdpp.c
@@ -0,0 +1,542 @@
+/* SPDX-License-Identifier: Apache-2.0 OR MIT */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#define MODULE_TAG "vdpp"
+
+#include <sys/ioctl.h>
+#include <errno.h>
+
+#include "mpp_buffer.h"
+#include "mpp_env.h"
+#include "mpp_service.h"
+#include "mpp_platform.h"
+
+#include "vdpp.h"
+
+#define VDPP_MODE_MIN_WIDTH   (128)
+#define VDPP_MODE_MIN_HEIGHT  (128)
+
+RK_U32 vdpp_debug = 0;
+
+static MPP_RET vdpp_params_to_reg(struct vdpp_params* src_params, struct vdpp_api_ctx *ctx)
+{
+    struct vdpp_reg *dst_reg = &ctx->reg;
+    struct zme_params *zme_params = &src_params->zme_params;
+
+    memset(dst_reg, 0, sizeof(*dst_reg));
+
+    /* 1. set reg::common */
+    dst_reg->common.reg0.sw_vdpp_frm_en = 1;
+
+    /* 0x0004(reg1), TODO: add debug function */
+    dst_reg->common.reg1.sw_vdpp_src_fmt = VDPP_FMT_YUV420;
+    dst_reg->common.reg1.sw_vdpp_src_yuv_swap = src_params->src_yuv_swap;
+    dst_reg->common.reg1.sw_vdpp_dst_fmt = src_params->dst_fmt;
+    dst_reg->common.reg1.sw_vdpp_dst_yuv_swap = src_params->dst_yuv_swap;
+    dst_reg->common.reg1.sw_vdpp_dbmsr_en = src_params->dmsr_params.dmsr_enable;
+
+    /* 0x0008(reg2) */
+    dst_reg->common.reg2.sw_vdpp_working_mode = VDPP_WORK_MODE_VEP;
+
+    /* 0x000C ~ 0x001C(reg3 ~ reg7), skip */
+    dst_reg->common.reg4.sw_vdpp_clk_on = 1;
+    dst_reg->common.reg4.sw_md_clk_on = 1;
+    dst_reg->common.reg4.sw_dect_clk_on = 1;
+    dst_reg->common.reg4.sw_me_clk_on = 1;
+    dst_reg->common.reg4.sw_mc_clk_on = 1;
+    dst_reg->common.reg4.sw_eedi_clk_on = 1;
+    dst_reg->common.reg4.sw_ble_clk_on = 1;
+    dst_reg->common.reg4.sw_out_clk_on = 1;
+    dst_reg->common.reg4.sw_ctrl_clk_on = 1;
+    dst_reg->common.reg4.sw_ram_clk_on = 1;
+    dst_reg->common.reg4.sw_dma_clk_on = 1;
+    dst_reg->common.reg4.sw_reg_clk_on = 1;
+
+    /* 0x0020(reg8) */
+    dst_reg->common.reg8.sw_vdpp_frm_done_en = 1;
+    dst_reg->common.reg8.sw_vdpp_osd_max_en = 1;
+    dst_reg->common.reg8.sw_vdpp_bus_error_en = 1;
+    dst_reg->common.reg8.sw_vdpp_timeout_int_en = 1;
+    dst_reg->common.reg8.sw_vdpp_config_error_en = 1;
+    /* 0x0024 ~ 0x002C(reg9 ~ reg11), skip */
+    {
+        RK_U32 src_right_redundant = src_params->src_width % 16 == 0 ? 0 : 16 - src_params->src_width % 16;
+        RK_U32 src_down_redundant  = src_params->src_height % 8 == 0 ? 0 : 8 - src_params->src_height % 8;
+        RK_U32 dst_right_redundant = src_params->dst_width % 16 == 0 ? 0 : 16 - src_params->dst_width % 16;
+        /* 0x0030(reg12) */
+        dst_reg->common.reg12.sw_vdpp_src_vir_y_stride = (src_params->src_width + src_right_redundant + 3) / 4;
+
+        /* 0x0034(reg13) */
+        dst_reg->common.reg13.sw_vdpp_dst_vir_y_stride = (src_params->dst_width + dst_right_redundant + 3) / 4;
+
+        /* 0x0038(reg14) */
+        dst_reg->common.reg14.sw_vdpp_src_pic_width = src_params->src_width + src_right_redundant - 1;
+        dst_reg->common.reg14.sw_vdpp_src_right_redundant = src_right_redundant;
+        dst_reg->common.reg14.sw_vdpp_src_pic_height = src_params->src_height + src_down_redundant - 1;
+        dst_reg->common.reg14.sw_vdpp_src_down_redundant = src_down_redundant;
+
+        /* 0x003C(reg15) */
+        dst_reg->common.reg15.sw_vdpp_dst_pic_width = src_params->dst_width + dst_right_redundant - 1;
+        dst_reg->common.reg15.sw_vdpp_dst_right_redundant = dst_right_redundant;
+        dst_reg->common.reg15.sw_vdpp_dst_pic_height = src_params->dst_height - 1;
+    }
+    /* 0x0040 ~ 0x005C(reg16 ~ reg23), skip */
+    dst_reg->common.reg20.sw_vdpp_timeout_en = 1;
+    dst_reg->common.reg20.sw_vdpp_timeout_cnt = 0x8FFFFFF;
+
+    /* 0x0060(reg24) */
+    dst_reg->common.reg24.sw_vdpp_src_addr_y = src_params->src.y;
+
+    /* 0x0064(reg25) */
+    dst_reg->common.reg25.sw_vdpp_src_addr_uv = src_params->src.cbcr;
+
+    /* 0x0068(reg26) */
+    dst_reg->common.reg26.sw_vdpp_dst_addr_y = src_params->dst.y;
+
+    /* 0x006C(reg27) */
+    dst_reg->common.reg27.sw_vdpp_dst_addr_uv = src_params->dst.cbcr;
+
+    set_dmsr_to_vdpp_reg(&src_params->dmsr_params, &ctx->dmsr);
+
+    zme_params->src_width = src_params->src_width;
+    zme_params->src_height = src_params->src_height;
+    zme_params->dst_width = src_params->dst_width;
+    zme_params->dst_height = src_params->dst_height;
+    zme_params->dst_fmt = src_params->dst_fmt;
+    set_zme_to_vdpp_reg(zme_params, &ctx->zme);
+
+    return MPP_OK;
+}
+
+static void vdpp_set_default_dmsr_param(struct dmsr_params* p_dmsr_param)
+{
+    p_dmsr_param->dmsr_enable = 1;
+    p_dmsr_param->dmsr_str_pri_y = 10;
+    p_dmsr_param->dmsr_str_sec_y = 4;
+    p_dmsr_param->dmsr_dumping_y = 6;
+    p_dmsr_param->dmsr_wgt_pri_gain_even_1 = 12;
+    p_dmsr_param->dmsr_wgt_pri_gain_even_2 = 12;
+    p_dmsr_param->dmsr_wgt_pri_gain_odd_1 = 8;
+    p_dmsr_param->dmsr_wgt_pri_gain_odd_2 = 16;
+    p_dmsr_param->dmsr_wgt_sec_gain = 5;
+    p_dmsr_param->dmsr_blk_flat_th = 20;
+    p_dmsr_param->dmsr_contrast_to_conf_map_x0 = 1680;
+    p_dmsr_param->dmsr_contrast_to_conf_map_x1 = 6720;
+    p_dmsr_param->dmsr_contrast_to_conf_map_y0 = 0;
+    p_dmsr_param->dmsr_contrast_to_conf_map_y1 = 65535;
+    p_dmsr_param->dmsr_diff_core_th0 = 2;
+    p_dmsr_param->dmsr_diff_core_th1 = 5;
+    p_dmsr_param->dmsr_diff_core_wgt0 = 16;
+    p_dmsr_param->dmsr_diff_core_wgt1 = 12;
+    p_dmsr_param->dmsr_diff_core_wgt2 = 8;
+    p_dmsr_param->dmsr_edge_th_low_arr[0] = 30;
+    p_dmsr_param->dmsr_edge_th_low_arr[1] = 10;
+    p_dmsr_param->dmsr_edge_th_low_arr[2] = 0;
+    p_dmsr_param->dmsr_edge_th_low_arr[3] = 0;
+    p_dmsr_param->dmsr_edge_th_low_arr[4] = 0;
+    p_dmsr_param->dmsr_edge_th_low_arr[5] = 0;
+    p_dmsr_param->dmsr_edge_th_low_arr[6] = 0;
+    p_dmsr_param->dmsr_edge_th_high_arr[0] = 60;
+    p_dmsr_param->dmsr_edge_th_high_arr[1] = 40;
+    p_dmsr_param->dmsr_edge_th_high_arr[2] = 20;
+    p_dmsr_param->dmsr_edge_th_high_arr[3] = 10;
+    p_dmsr_param->dmsr_edge_th_high_arr[4] = 10;
+    p_dmsr_param->dmsr_edge_th_high_arr[5] = 10;
+    p_dmsr_param->dmsr_edge_th_high_arr[6] = 10;
+}
+
+static MPP_RET vdpp_set_default_param(struct vdpp_params *param)
+{
+    /* src_fmt only NV12 supported */
+    param->src_yuv_swap = VDPP_YUV_SWAP_SP_UV;
+    param->dst_fmt = VDPP_FMT_YUV444;
+    param->dst_yuv_swap = VDPP_YUV_SWAP_SP_UV;
+    param->src_width = 1920;
+    param->src_height = 1080;
+    param->dst_width = 1920;
+    param->dst_height = 1080;
+
+
+    vdpp_set_default_dmsr_param(&param->dmsr_params);
+    vdpp_set_default_zme_param(&param->zme_params);
+
+    return MPP_OK;
+}
+
+MPP_RET vdpp_init(VdppCtx *ictx)
+{
+    MPP_RET ret;
+    MppReqV1 mpp_req;
+    RK_U32 client_data = VDPP_CLIENT_TYPE;
+    struct vdpp_api_ctx *ctx = NULL;
+
+    if (NULL == *ictx) {
+        mpp_err_f("found NULL input vdpp ctx %p\n", *ictx);
+        return MPP_ERR_NULL_PTR;
+    }
+
+    ctx = *ictx;
+
+    mpp_env_get_u32("vdpp_debug", &vdpp_debug, 0);
+
+    ctx->fd = open("/dev/mpp_service", O_RDWR | O_CLOEXEC);
+    if (ctx->fd < 0) {
+        mpp_err("can NOT find device /dev/vdpp\n");
+        return MPP_NOK;
+    }
+
+    mpp_req.cmd = MPP_CMD_INIT_CLIENT_TYPE;
+    mpp_req.flag = 0;
+    mpp_req.size = sizeof(client_data);
+    mpp_req.data_ptr = REQ_DATA_PTR(&client_data);
+
+    memset(&ctx->params, 0, sizeof(struct vdpp_params));
+    /* set default parameters */
+    vdpp_set_default_param(&ctx->params);
+
+    ret = (RK_S32)ioctl(ctx->fd, MPP_IOC_CFG_V1, &mpp_req);
+    if (ret) {
+        mpp_err("ioctl set_client failed\n");
+        return MPP_NOK;
+    }
+
+    return MPP_OK;
+}
+
+MPP_RET vdpp_deinit(VdppCtx ictx)
+{
+    struct vdpp_api_ctx *ctx = NULL;
+
+    if (NULL == ictx) {
+        mpp_err_f("found NULL input vdpp ctx %p\n", ictx);
+        return MPP_ERR_NULL_PTR;
+    }
+
+    ctx = ictx;
+
+    if (ctx->fd >= 0) {
+        close(ctx->fd);
+        ctx->fd = -1;
+    }
+
+    return MPP_OK;
+}
+
+static MPP_RET vdpp_set_param(struct vdpp_api_ctx *ctx,
+                              union vdpp_api_content *param,
+                              enum VDPP_PARAM_TYPE type)
+{
+    MPP_RET ret = MPP_OK;
+
+    switch (type) {
+    case VDPP_PARAM_TYPE_COM :
+        ctx->params.src_yuv_swap = param->com.sswap;
+        ctx->params.dst_fmt = param->com.dfmt;
+        ctx->params.dst_yuv_swap = param->com.dswap;
+        ctx->params.src_width = param->com.src_width;
+        ctx->params.src_height = param->com.src_height;
+        ctx->params.dst_width = param->com.dst_width;
+        ctx->params.dst_height = param->com.dst_height;
+        break;
+
+    case VDPP_PARAM_TYPE_DMSR :
+        memcpy(&ctx->params.dmsr_params, &param->dmsr, sizeof(struct dmsr_params));
+        break;
+
+    case VDPP_PARAM_TYPE_ZME_COM :
+        ctx->params.zme_params.zme_bypass_en = param->zme.bypass_enable;
+        ctx->params.zme_params.zme_dering_enable = param->zme.dering_enable;
+        ctx->params.zme_params.zme_dering_sen_0 = param->zme.dering_sen_0;
+        ctx->params.zme_params.zme_dering_sen_1 = param->zme.dering_sen_1;
+        ctx->params.zme_params.zme_dering_blend_alpha = param->zme.dering_blend_alpha;
+        ctx->params.zme_params.zme_dering_blend_beta = param->zme.dering_blend_beta;
+        break;
+
+    case VDPP_PARAM_TYPE_ZME_COEFF :
+        if (param->zme.tap8_coeff != NULL)
+            ctx->params.zme_params.zme_tap8_coeff = param->zme.tap8_coeff;
+        if (param->zme.tap6_coeff != NULL)
+            ctx->params.zme_params.zme_tap6_coeff = param->zme.tap6_coeff;
+        break;
+
+    default:
+        break;
+    }
+
+    return ret;
+}
+
+static RK_S32 check_cap(struct vdpp_params *params)
+{
+    RK_S32 ret_cap = VDPP_CAP_UNSUPPORTED;
+    RK_U32 vep_mode_check = 0;
+
+    if (NULL == params) {
+        VDPP_DBG(VDPP_DBG_CHECK, "found null pointer params\n");
+        return VDPP_CAP_UNSUPPORTED;
+    }
+
+    if ((params->src_height < VDPP_MODE_MIN_HEIGHT) ||
+        (params->src_width < VDPP_MODE_MIN_WIDTH)) {
+        VDPP_DBG(VDPP_DBG_CHECK, "vep src unsupported img_w %d img_h %d\n",
+                 params->src_height, params->src_width);
+        vep_mode_check++;
+    }
+
+    if ((params->dst_height < VDPP_MODE_MIN_HEIGHT) ||
+        (params->dst_width < VDPP_MODE_MIN_WIDTH)) {
+        VDPP_DBG(VDPP_DBG_CHECK, "vep dst unsupported img_w %d img_h %d\n",
+                 params->dst_height, params->dst_width);
+        vep_mode_check++;
+    }
+
+    if ((params->src_width & 1) || (params->src_height & 1) ||
+        (params->dst_width & 1) || (params->dst_height & 1)) {
+        VDPP_DBG(VDPP_DBG_CHECK, "vep only support img_w/h_vld 2pix align\n");
+        VDPP_DBG(VDPP_DBG_CHECK, "vep unsupported img_w_i %d img_h_i %d img_w_o %d img_h_o %d\n",
+                 params->src_width, params->src_height, params->dst_width, params->dst_height);
+        vep_mode_check++;
+    }
+
+    if (!vep_mode_check) {
+        ret_cap |= VDPP_CAP_VEP;
+        VDPP_DBG(VDPP_DBG_INT, "vdpp support mode: VDPP_CAP_VEP\n");
+    }
+
+    return ret_cap;
+}
+
+static MPP_RET vdpp_start(struct vdpp_api_ctx *ctx)
+{
+    MPP_RET ret;
+    RegOffsetInfo reg_off[2];
+    MppReqV1 mpp_req[9];
+    RK_U32 req_cnt = 0;
+    struct vdpp_reg *reg = NULL;
+    struct zme_reg *zme = NULL;
+    RK_S32 ret_cap = VDPP_CAP_UNSUPPORTED;
+
+    if (NULL == ctx) {
+        mpp_err_f("found NULL input vdpp ctx %p\n", ctx);
+        return MPP_ERR_NULL_PTR;
+    }
+
+    ret_cap = check_cap(&ctx->params);
+    if (!(ret_cap & VDPP_CAP_VEP)) {
+        mpp_err_f("found incompat work mode %s cap %d\n",
+                  working_mode_name[VDPP_WORK_MODE_VEP], ret_cap);
+        return MPP_NOK;
+    }
+
+    reg = &ctx->reg;
+    zme = &ctx->zme;
+
+    memset(reg_off, 0, sizeof(reg_off));
+    memset(mpp_req, 0, sizeof(mpp_req));
+    memset(reg, 0, sizeof(*reg));
+
+    vdpp_params_to_reg(&ctx->params, ctx);
+
+    mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_WRITE;
+    mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG;
+    mpp_req[req_cnt].size =  sizeof(zme->yrgb_hor_coe);
+    mpp_req[req_cnt].offset = VDPP_REG_OFF_YRGB_HOR_COE;
+    mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(&zme->yrgb_hor_coe);
+
+    req_cnt++;
+    mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_WRITE;
+    mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG;
+    mpp_req[req_cnt].size =  sizeof(zme->yrgb_ver_coe);
+    mpp_req[req_cnt].offset = VDPP_REG_OFF_YRGB_VER_COE;
+    mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(&zme->yrgb_ver_coe);
+
+    req_cnt++;
+    mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_WRITE;
+    mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG;
+    mpp_req[req_cnt].size =  sizeof(zme->cbcr_hor_coe);
+    mpp_req[req_cnt].offset = VDPP_REG_OFF_CBCR_HOR_COE;
+    mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(&zme->cbcr_hor_coe);
+
+    req_cnt++;
+    mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_WRITE;
+    mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG;
+    mpp_req[req_cnt].size =  sizeof(zme->cbcr_ver_coe);
+    mpp_req[req_cnt].offset = VDPP_REG_OFF_CBCR_VER_COE;
+    mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(&zme->cbcr_ver_coe);
+
+    req_cnt++;
+    mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_WRITE;
+    mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG;
+    mpp_req[req_cnt].size =  sizeof(zme->common);
+    mpp_req[req_cnt].offset = VDPP_REG_OFF_ZME_COMMON;
+    mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(&zme->common);
+
+    req_cnt++;
+    mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_WRITE;
+    mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG;
+    mpp_req[req_cnt].size =  sizeof(ctx->dmsr);
+    mpp_req[req_cnt].offset = VDPP_REG_OFF_DMSR;
+    mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(&ctx->dmsr);
+
+    /* set reg offset */
+    reg_off[0].reg_idx = 25;
+    reg_off[0].offset = ctx->params.src.cbcr_offset;
+    reg_off[1].reg_idx = 27;
+    reg_off[1].offset = ctx->params.dst.cbcr_offset;
+    req_cnt++;
+    mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_ADDR_OFFSET;
+    mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG | MPP_FLAGS_REG_OFFSET_ALONE;
+    mpp_req[req_cnt].size = sizeof(reg_off);
+    mpp_req[req_cnt].offset = 0;
+    mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(reg_off);
+
+    req_cnt++;
+    mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_WRITE;
+    mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG;
+    mpp_req[req_cnt].size =  sizeof(reg->common);
+    mpp_req[req_cnt].offset = 0;
+    mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(&reg->common);
+
+    req_cnt++;
+    mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_READ;
+    mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG | MPP_FLAGS_LAST_MSG;
+    mpp_req[req_cnt].size =  sizeof(reg->common);
+    mpp_req[req_cnt].offset = 0;
+    mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(&reg->common);
+
+    ret = (RK_S32)ioctl(ctx->fd, MPP_IOC_CFG_V1, &mpp_req[0]);
+
+    if (ret) {
+        mpp_err_f("ioctl SET_REG failed ret %d errno %d %s\n",
+                  ret, errno, strerror(errno));
+        ret = errno;
+    }
+
+    return ret;
+}
+
+static MPP_RET vdpp_wait(struct vdpp_api_ctx *ctx)
+{
+    MPP_RET ret;
+    MppReqV1 mpp_req;
+
+    if (NULL == ctx) {
+        mpp_err_f("found NULL input vdpp ctx %p\n", ctx);
+        return MPP_ERR_NULL_PTR;
+    }
+
+    memset(&mpp_req, 0, sizeof(mpp_req));
+    mpp_req.cmd = MPP_CMD_POLL_HW_FINISH;
+    mpp_req.flag |= MPP_FLAGS_LAST_MSG;
+
+    ret = (RK_S32)ioctl(ctx->fd, MPP_IOC_CFG_V1, &mpp_req);
+    if (ret) {
+        mpp_err_f("ioctl POLL_HW_FINISH failed ret %d errno %d %s\n",
+                  ret, errno, strerror(errno));
+    }
+
+    return ret;
+}
+
+static MPP_RET vdpp_done(struct vdpp_api_ctx *ctx)
+{
+    struct vdpp_reg *reg = NULL;
+
+    if (NULL == ctx) {
+        mpp_err_f("found NULL input vdpp ctx %p\n", ctx);
+        return MPP_ERR_NULL_PTR;
+    }
+
+    reg = &ctx->reg;
+
+    VDPP_DBG(VDPP_DBG_INT, "ro_frm_done_sts=%d\n", reg->common.reg10.ro_frm_done_sts);
+    VDPP_DBG(VDPP_DBG_INT, "ro_osd_max_sts=%d\n", reg->common.reg10.ro_osd_max_sts);
+    VDPP_DBG(VDPP_DBG_INT, "ro_bus_error_sts=%d\n", reg->common.reg10.ro_bus_error_sts);
+    VDPP_DBG(VDPP_DBG_INT, "ro_timeout_sts=%d\n", reg->common.reg10.ro_timeout_sts);
+    VDPP_DBG(VDPP_DBG_INT, "ro_config_error_sts=%d\n", reg->common.reg10.ro_timeout_sts);
+
+    if (reg->common.reg8.sw_vdpp_frm_done_en &&
+        !reg->common.reg10.ro_frm_done_sts) {
+        mpp_err_f("run vdpp failed\n");
+        return MPP_NOK;
+    }
+
+    VDPP_DBG(VDPP_DBG_INT, "run vdpp success\n");
+
+    return MPP_OK;
+}
+
+static inline MPP_RET set_addr(struct vdpp_addr *addr, VdppImg *img)
+{
+    if (NULL == addr || NULL == img) {
+        mpp_err_f("found NULL vdpp_addr %p img %p\n", addr, img);
+        return MPP_ERR_NULL_PTR;
+    }
+
+    addr->y = img->mem_addr;
+    addr->cbcr = img->uv_addr;
+    addr->cbcr_offset = img->uv_off;
+
+    return MPP_OK;
+}
+
+MPP_RET vdpp_control(VdppCtx ictx, VdppCmd cmd, void *iparam)
+{
+    struct vdpp_api_ctx *ctx = ictx;
+    MPP_RET ret = MPP_OK;
+
+    if ((NULL == iparam && VDPP_CMD_RUN_SYNC != cmd) ||
+        (NULL == ictx)) {
+        mpp_err_f("found NULL iparam %p cmd %d ctx %p\n", iparam, cmd, ictx);
+        return MPP_ERR_NULL_PTR;
+    }
+
+    switch (cmd) {
+    case VDPP_CMD_SET_COM_CFG:
+    case VDPP_CMD_SET_DMSR_CFG:
+    case VDPP_CMD_SET_ZME_COM_CFG:
+    case VDPP_CMD_SET_ZME_COEFF_CFG: {
+        struct vdpp_api_params *param = (struct vdpp_api_params *)iparam;
+
+        ret = vdpp_set_param(ctx, &param->param, param->ptype);
+        if (ret) {
+            mpp_err_f("set vdpp parameter failed, type %d\n", param->ptype);
+        }
+        break;
+    }
+    case VDPP_CMD_SET_SRC:
+        set_addr(&ctx->params.src, (VdppImg *)iparam);
+        break;
+    case VDPP_CMD_SET_DST:
+        set_addr(&ctx->params.dst, (VdppImg *)iparam);
+        break;
+    case VDPP_CMD_RUN_SYNC:
+        ret = vdpp_start(ctx);
+        if (ret) {
+            mpp_err_f("run vdpp failed\n");
+            return MPP_NOK;
+        }
+
+        vdpp_wait(ctx);
+        vdpp_done(ctx);
+        break;
+    default:
+        ;
+    }
+
+    return ret;
+}
+
+RK_S32 vdpp_check_cap(VdppCtx ictx)
+{
+    struct vdpp_api_ctx *ctx = ictx;
+
+    if (NULL == ictx) {
+        mpp_err_f("found NULL ctx %p\n", ictx);
+        return VDPP_CAP_UNSUPPORTED;
+    }
+
+    return check_cap(&ctx->params);
+}
diff --git a/mpp/vproc/vdpp/vdpp.h b/mpp/vproc/vdpp/vdpp.h
new file mode 100644
index 000000000..04113aaf9
--- /dev/null
+++ b/mpp/vproc/vdpp/vdpp.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: Apache-2.0 OR MIT */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef __VDPP_H__
+#define __VDPP_H__
+
+#include "vdpp_reg.h"
+#include "vdpp_common.h"
+
+/* vdpp log marco */
+#define VDPP_DBG_TRACE             (0x00000001)
+#define VDPP_DBG_INT               (0x00000002)
+#define VDPP_DBG_CHECK             (0x00000004)
+
+extern RK_U32 vdpp_debug;
+
+#define VDPP_DBG(level, fmt, ...)\
+    do {\
+        if (level & vdpp_debug)\
+        { mpp_log(fmt, ## __VA_ARGS__); }\
+    } while (0)
+
+struct vdpp_params {
+    RK_U32 src_yuv_swap;
+    RK_U32 dst_fmt;
+    RK_U32 dst_yuv_swap;
+    RK_U32 src_width;
+    RK_U32 src_height;
+    RK_U32 dst_width;
+    RK_U32 dst_height;
+
+    struct vdpp_addr src; // src frame
+    struct vdpp_addr dst; // dst frame
+
+    struct dmsr_params dmsr_params;
+    struct zme_params zme_params;
+};
+
+struct vdpp_api_ctx {
+    RK_S32 fd;
+    struct vdpp_params params;
+    struct vdpp_reg reg;
+    struct dmsr_reg dmsr;
+    struct zme_reg zme;
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+MPP_RET vdpp_init(VdppCtx *ictx);
+MPP_RET vdpp_deinit(VdppCtx ictx);
+MPP_RET vdpp_control(VdppCtx ictx, VdppCmd cmd, void *iparam);
+RK_S32  vdpp_check_cap(VdppCtx ictx);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/mpp/vproc/vdpp/vdpp2.c b/mpp/vproc/vdpp/vdpp2.c
new file mode 100644
index 000000000..8c699d276
--- /dev/null
+++ b/mpp/vproc/vdpp/vdpp2.c
@@ -0,0 +1,2039 @@
+/* SPDX-License-Identifier: Apache-2.0 OR MIT */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#define MODULE_TAG "vdpp2"
+
+#include <sys/ioctl.h>
+#include <errno.h>
+#include <math.h>
+
+#include "mpp_buffer.h"
+#include "mpp_env.h"
+#include "mpp_service.h"
+#include "mpp_platform.h"
+
+#include "vdpp2.h"
+
+#define VDPP2_VEP_MAX_WIDTH   (1920)
+#define VDPP2_VEP_MAX_HEIGHT  (2048)
+#define VDPP2_HIST_MAX_WIDTH  (4096)
+#define VDPP2_HIST_MAX_HEIGHT (4096)
+#define VDPP2_MODE_MIN_WIDTH  (128)
+#define VDPP2_MODE_MIN_HEIGH  (128)
+
+#define VDPP2_HIST_HSD_DISABLE_LIMIT (1920)
+#define VDPP2_HIST_VSD_DISABLE_LIMIT (1080)
+#define VDPP2_HIST_VSD_MODE_1_LIMIT  (2160)
+
+RK_U32 vdpp2_debug = 0;
+/* default es parameters */
+static RK_S32 diff2conf_lut_x_tmp[9]    = {
+    0, 1024, 2048, 3072, 4096, 6144, 8192, 12288, 65535,
+};
+static RK_S32 diff2conf_lut_y_tmp[9]    = {
+    0, 84, 141, 179, 204, 233, 246, 253, 255,
+};
+/* default sharp parameters */
+static RK_S32 coring_zero_tmp[7]        = {
+    5, 5, 8, 5, 8, 5, 5,
+};
+static RK_S32 coring_thr_tmp[7]         = {
+    40, 40, 40, 24, 26, 30, 26,
+};
+static RK_S32 coring_ratio_tmp[7]       = {
+    1479, 1188, 1024, 1422, 1024, 1024, 1024,
+};
+static RK_S32 gain_pos_tmp[7]           = {
+    128, 256, 512, 256, 512, 256, 256,
+};
+static RK_S32 gain_neg_tmp[7]           = {
+    128, 256, 512, 256, 512, 256, 256,
+};
+static RK_S32 limit_ctrl_pos0_tmp[7]    = {
+    64, 64, 64, 64, 64, 64, 64,
+};
+static RK_S32 limit_ctrl_pos1_tmp[7]    = {
+    120, 120, 120, 120, 120, 120, 120,
+};
+static RK_S32 limit_ctrl_neg0_tmp[7]    = {
+    64, 64, 64, 64, 64, 64, 64,
+};
+static RK_S32 limit_ctrl_neg1_tmp[7]    = {
+    120, 120, 120, 120, 120, 120, 120,
+};
+static RK_S32 limit_ctrl_ratio_tmp[7]   = {
+    128, 128, 128, 128, 128, 128, 128,
+};
+static RK_S32 limit_ctrl_bnd_pos_tmp[7] = {
+    81, 131, 63, 81, 63, 63, 63,
+};
+static RK_S32 limit_ctrl_bnd_neg_tmp[7] = {
+    81, 131, 63, 81, 63, 63, 63,
+};
+static RK_S32 lum_grd_tmp[6]            = {
+    0, 200, 300, 860, 960, 1023
+};
+static RK_S32 lum_val_tmp[6]            = {
+    64, 64, 64, 64, 64, 64,
+};
+static RK_S32 adp_grd_tmp[6]            = {
+    0, 4, 60, 180, 300, 1023,
+};
+static RK_S32 adp_val_tmp[6]            = {
+    64, 64, 64, 64, 64, 64,
+};
+static RK_S32 var_grd_tmp[6]            = {
+    0, 39, 102, 209, 500, 1023,
+};
+static RK_S32 var_val_tmp[6]            = {
+    64, 64, 64, 64, 64, 64,
+};
+static RK_S32 diag_adj_gain_tab_tmp[8]  = {
+    6, 7, 8, 9, 10, 11, 12, 13,
+};
+static RK_S32 roll_tab_pattern0[16]     = {
+    0, 0, 0, 1, 2, 3, 4, 6, 8, 10, 11, 12, 13, 14, 15, 15,
+};
+static RK_S32 roll_tab_pattern1[16]     = {
+    31, 31, 30, 29, 28, 27, 25, 23, 21, 19, 18, 17, 16, 16, 15, 15,
+};
+static RK_S32 roll_tab_pattern2[16]     = {
+    16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16,
+};
+static RK_S32 tex_grd_tmp[6]            = {
+    0, 128, 256, 400, 600, 1023,
+};
+static RK_S32 tex_val_tmp[6]            = {
+    40, 60, 80, 100, 127, 127,
+};
+
+typedef enum VdppDciFmt_e {
+    VDPP_DCI_FMT_RGB888,        // 0
+    VDPP_DCI_FMT_ARGB8888,      // 1
+    VDPP_DCI_FMT_Y_8bit_SP = 4, // 4
+    VDPP_DCI_FMT_Y_10bit_SP,    // 5
+    VDPP_DCI_FMT_BUTT,
+} VdppDciFmt;
+
+typedef struct VdppSrcFmtCfg_t {
+    VdppDciFmt      format;
+    RK_S32          alpha_swap;
+    RK_S32          rbuv_swap;
+} VdppSrcFmtCfg;
+
+static VdppSrcFmtCfg vdpp_src_yuv_cfg[MPP_FMT_YUV_BUTT] = {
+    {   /* MPP_FMT_YUV420SP */
+        .format     = VDPP_DCI_FMT_Y_8bit_SP,
+        .alpha_swap = 0,
+        .rbuv_swap  = 0,
+    },
+    {   /* MPP_FMT_YUV420SP_10BIT */
+        .format     = VDPP_DCI_FMT_Y_10bit_SP,
+        .alpha_swap = 0,
+        .rbuv_swap  = 0,
+    },
+    {   /* MPP_FMT_YUV422SP */
+        .format     = VDPP_DCI_FMT_Y_8bit_SP,
+        .alpha_swap = 0,
+        .rbuv_swap  = 0,
+    },
+    {   /* MPP_FMT_YUV422SP_10BIT */
+        .format     = VDPP_DCI_FMT_Y_10bit_SP,
+        .alpha_swap = 0,
+        .rbuv_swap  = 0,
+    },
+    {   /* MPP_FMT_YUV420P */
+        .format     = VDPP_DCI_FMT_Y_8bit_SP,
+        .alpha_swap = 0,
+        .rbuv_swap  = 0,
+    },
+    {   /* MPP_FMT_YUV420SP_VU   */
+        .format     = VDPP_DCI_FMT_Y_8bit_SP,
+        .alpha_swap = 0,
+        .rbuv_swap  = 1,
+    },
+    {   /* MPP_FMT_YUV422P */
+        .format     = VDPP_DCI_FMT_Y_8bit_SP,
+        .alpha_swap = 0,
+        .rbuv_swap  = 0,
+    },
+    {   /* MPP_FMT_YUV422SP_VU */
+        .format     = VDPP_DCI_FMT_Y_8bit_SP,
+        .alpha_swap = 0,
+        .rbuv_swap  = 1,
+    },
+    {   /* MPP_FMT_YUV422_YUYV */
+        .format     = VDPP_DCI_FMT_BUTT,
+        .alpha_swap = 0,
+        .rbuv_swap  = 0,
+    },
+    {   /* MPP_FMT_YUV422_YVYU */
+        .format     = VDPP_DCI_FMT_BUTT,
+        .alpha_swap = 0,
+        .rbuv_swap  = 1,
+    },
+    {   /* MPP_FMT_YUV422_UYVY */
+        .format     = VDPP_DCI_FMT_BUTT,
+        .alpha_swap = 0,
+        .rbuv_swap  = 0,
+    },
+    {   /* MPP_FMT_YUV422_VYUY */
+        .format     = VDPP_DCI_FMT_BUTT,
+        .alpha_swap = 0,
+        .rbuv_swap  = 1,
+    },
+    {   /* MPP_FMT_YUV400 */
+        .format     = VDPP_DCI_FMT_Y_8bit_SP,
+        .alpha_swap = 0,
+        .rbuv_swap  = 0,
+    },
+    {   /* MPP_FMT_YUV440SP */
+        .format     = VDPP_DCI_FMT_Y_8bit_SP,
+        .alpha_swap = 0,
+        .rbuv_swap  = 0,
+    },
+    {   /* MPP_FMT_YUV411SP */
+        .format     = VDPP_DCI_FMT_Y_8bit_SP,
+        .alpha_swap = 0,
+        .rbuv_swap  = 0,
+    },
+    {   /* MPP_FMT_YUV444SP */
+        .format     = VDPP_DCI_FMT_Y_8bit_SP,
+        .alpha_swap = 0,
+        .rbuv_swap  = 0,
+    },
+    {   /* MPP_FMT_YUV444P */
+        .format     = VDPP_DCI_FMT_Y_8bit_SP,
+        .alpha_swap = 0,
+        .rbuv_swap  = 1,
+    },
+};
+
+static VdppSrcFmtCfg vdpp_src_rgb_cfg[MPP_FMT_RGB_BUTT - MPP_FRAME_FMT_RGB] = {
+    {   /* MPP_FMT_RGB565 */
+        .format     = VDPP_DCI_FMT_BUTT,
+        .alpha_swap = 0,
+        .rbuv_swap  = 1,
+    },
+    {   /* MPP_FMT_BGR565 */
+        .format     = VDPP_DCI_FMT_BUTT,
+        .alpha_swap = 0,
+        .rbuv_swap  = 0,
+    },
+    {   /* MPP_FMT_RGB555 */
+        .format     = VDPP_DCI_FMT_BUTT,
+        .alpha_swap = 0,
+        .rbuv_swap  = 0,
+    },
+    {   /* MPP_FMT_BGR555 */
+        .format     = VDPP_DCI_FMT_BUTT,
+        .alpha_swap = 0,
+        .rbuv_swap  = 0,
+    },
+    {   /* MPP_FMT_RGB444 */
+        .format     = VDPP_DCI_FMT_BUTT,
+        .alpha_swap = 0,
+        .rbuv_swap  = 0,
+    },
+    {   /* MPP_FMT_BGR444 */
+        .format     = VDPP_DCI_FMT_BUTT,
+        .alpha_swap = 0,
+        .rbuv_swap  = 0,
+    },
+    {   /* MPP_FMT_RGB888 */
+        .format     = VDPP_DCI_FMT_RGB888,
+        .alpha_swap = 0,
+        .rbuv_swap  = 0,
+    },
+    {   /* MPP_FMT_BGR888 */
+        .format     = VDPP_DCI_FMT_RGB888,
+        .alpha_swap = 0,
+        .rbuv_swap  = 1,
+    },
+    {   /* MPP_FMT_RGB101010 */
+        .format     = VDPP_DCI_FMT_BUTT,
+        .alpha_swap = 0,
+        .rbuv_swap  = 0,
+    },
+    {   /* MPP_FMT_BGR101010 */
+        .format     = VDPP_DCI_FMT_BUTT,
+        .alpha_swap = 0,
+        .rbuv_swap  = 0,
+    },
+    {   /* MPP_FMT_ARGB8888 */
+        .format     = VDPP_DCI_FMT_ARGB8888,
+        .alpha_swap = 1,
+        .rbuv_swap  = 1,
+    },
+    {   /* MPP_FMT_ABGR8888 */
+        .format     = VDPP_DCI_FMT_ARGB8888,
+        .alpha_swap = 1,
+        .rbuv_swap  = 0,
+    },
+    {   /* MPP_FMT_BGRA8888 */
+        .format     = VDPP_DCI_FMT_ARGB8888,
+        .alpha_swap = 0,
+        .rbuv_swap  = 0,
+    },
+    {   /* MPP_FMT_RGBA8888 */
+        .format     = VDPP_DCI_FMT_ARGB8888,
+        .alpha_swap = 0,
+        .rbuv_swap  = 1,
+    },
+};
+
+static void update_dci_ctl(struct vdpp2_params* src_params)
+{
+    RK_S32 dci_format, dci_alpha_swap, dci_rbuv_swap;
+
+    if (MPP_FRAME_FMT_IS_YUV(src_params->src_fmt)) {
+        dci_format = vdpp_src_yuv_cfg[src_params->src_fmt - MPP_FRAME_FMT_YUV].format;
+        dci_alpha_swap = vdpp_src_yuv_cfg[src_params->src_fmt - MPP_FRAME_FMT_YUV].alpha_swap;
+        dci_rbuv_swap = vdpp_src_yuv_cfg[src_params->src_fmt - MPP_FRAME_FMT_YUV].rbuv_swap;
+    } else if (MPP_FRAME_FMT_IS_RGB(src_params->src_fmt)) {
+        dci_format = vdpp_src_rgb_cfg[src_params->src_fmt - MPP_FRAME_FMT_RGB].format;
+        dci_alpha_swap = vdpp_src_rgb_cfg[src_params->src_fmt - MPP_FRAME_FMT_RGB].alpha_swap;
+        dci_rbuv_swap = vdpp_src_rgb_cfg[src_params->src_fmt - MPP_FRAME_FMT_RGB].rbuv_swap;
+    } else {
+        mpp_err("warning: invalid input format %d", src_params->src_fmt);
+        return;
+    }
+
+    src_params->dci_format = dci_format;
+    src_params->dci_alpha_swap = dci_alpha_swap;
+    src_params->dci_rbuv_swap = dci_rbuv_swap;
+
+    VDPP2_DBG(VDPP2_DBG_TRACE, "input format %d  dci_format %d", src_params->src_fmt, dci_format);
+}
+
+static void set_hist_to_vdpp2_reg(struct vdpp2_params* src_params, struct vdpp2_reg* dst_reg)
+{
+    RK_S32 pic_vir_src_ystride;
+    RK_S32 hsd_sample_num, vsd_sample_num, sw_dci_blk_hsize, sw_dci_blk_vsize;
+    RK_U32 dci_hsd_mode, dci_vsd_mode;
+
+    update_dci_ctl(src_params);
+
+    pic_vir_src_ystride = (src_params->src_width + 3) / 4;
+
+    if (src_params->dci_format == VDPP_DCI_FMT_RGB888) {
+        pic_vir_src_ystride = src_params->src_width_vir * 3 / 4;
+    } else if (src_params->dci_format == VDPP_DCI_FMT_ARGB8888) {
+        pic_vir_src_ystride = src_params->src_width_vir * 4 / 4;
+    } else if (src_params->dci_format == VDPP_DCI_FMT_Y_10bit_SP) { // Y 10bit SP
+        pic_vir_src_ystride = src_params->src_width_vir * 10 / 8 / 4;
+    } else if (src_params->dci_format == VDPP_DCI_FMT_Y_8bit_SP) { // Y 8bit SP
+        pic_vir_src_ystride = src_params->src_width_vir / 4;
+    } else {
+        mpp_err("warning: unsupported dci format %d", src_params->dci_format);
+        return;
+    }
+
+    dci_hsd_mode = (src_params->dci_hsd_mode & 1);
+    dci_vsd_mode = (src_params->dci_vsd_mode & 3);
+
+    /* check vdpp scale down mode for performance optimization */
+    if (!(dci_hsd_mode & VDPP_DCI_HSD_MODE_1) &&
+        (src_params->src_width_vir > VDPP2_HIST_HSD_DISABLE_LIMIT)) {
+        VDPP2_DBG(VDPP2_DBG_INT, "w_vir %d hsd mode %d is optimized as mode 1\n",
+                  src_params->src_width_vir, dci_hsd_mode);
+        dci_hsd_mode = VDPP_DCI_HSD_MODE_1;
+    }
+
+    if (!(dci_vsd_mode & VDPP_DCI_VSD_MODE_1) &&
+        (src_params->src_height_vir > VDPP2_HIST_VSD_DISABLE_LIMIT)) {
+        VDPP2_DBG(VDPP2_DBG_INT, "h_vir %d vsd mode %d is optimized as mode 1\n",
+                  src_params->src_height_vir, dci_vsd_mode);
+        dci_vsd_mode = VDPP_DCI_VSD_MODE_1;
+    }
+
+    if (!(dci_vsd_mode & VDPP_DCI_VSD_MODE_2) &&
+        (src_params->src_height_vir > VDPP2_HIST_VSD_MODE_1_LIMIT)) {
+        VDPP2_DBG(VDPP2_DBG_INT, "h_vir %d vsd mode %d is optimized as mode 2\n",
+                  src_params->src_height_vir, dci_vsd_mode);
+        dci_vsd_mode = VDPP_DCI_VSD_MODE_2;
+    }
+
+    switch (dci_hsd_mode) {
+    case VDPP_DCI_HSD_DISABLE:
+        hsd_sample_num = 2;
+        break;
+    case VDPP_DCI_HSD_MODE_1:
+        hsd_sample_num = 4;
+        break;
+    default:
+        hsd_sample_num = 2;
+        break;
+    }
+
+    switch (dci_vsd_mode) {
+    case VDPP_DCI_VSD_DISABLE:
+        vsd_sample_num = 1;
+        break;
+    case VDPP_DCI_VSD_MODE_1:
+        vsd_sample_num = 2;
+        break;
+    case VDPP_DCI_VSD_MODE_2:
+        vsd_sample_num = 4;
+        break;
+    default:
+        vsd_sample_num = 1;
+        break;
+    }
+
+    if (src_params->src_height < 1080)
+        sw_dci_blk_vsize = src_params->src_height / (16 * vsd_sample_num);
+    else
+        sw_dci_blk_vsize = (src_params->src_height + (16 * vsd_sample_num - 1)) / (16 * vsd_sample_num);
+
+    if (src_params->src_width < 1080)
+        sw_dci_blk_hsize = src_params->src_width / (16 * hsd_sample_num);
+    else
+        sw_dci_blk_hsize = (src_params->src_width + (16 * hsd_sample_num - 1)) / (16 * hsd_sample_num);
+
+    dst_reg->common.reg1.sw_dci_en = src_params->hist_cnt_en;
+
+    dst_reg->dci.reg0.sw_dci_yrgb_addr = src_params->src.y;
+    dst_reg->dci.reg1.sw_dci_yrgb_vir_stride = pic_vir_src_ystride;
+    dst_reg->dci.reg1.sw_dci_yrgb_gather_num = src_params->dci_yrgb_gather_num;
+    dst_reg->dci.reg1.sw_dci_yrgb_gather_en = src_params->dci_yrgb_gather_en;
+    dst_reg->dci.reg2.sw_vdpp_src_pic_width = MPP_ALIGN_DOWN(src_params->src_width, hsd_sample_num) - 1;
+    dst_reg->dci.reg2.sw_vdpp_src_pic_height = MPP_ALIGN_DOWN(src_params->src_height, vsd_sample_num) - 1;
+    dst_reg->dci.reg3.sw_dci_data_format = src_params->dci_format;
+    dst_reg->dci.reg3.sw_dci_csc_range = src_params->dci_csc_range;
+    dst_reg->dci.reg3.sw_dci_vsd_mode = (src_params->working_mode == VDPP_WORK_MODE_VEP)
+                                        ? 0
+                                        : dci_vsd_mode;
+    dst_reg->dci.reg3.sw_dci_hsd_mode = (src_params->working_mode == VDPP_WORK_MODE_VEP)
+                                        ? 0
+                                        : dci_hsd_mode;
+    dst_reg->dci.reg3.sw_dci_alpha_swap = src_params->dci_alpha_swap;
+    dst_reg->dci.reg3.sw_dci_rb_swap = src_params->dci_rbuv_swap;
+    dst_reg->dci.reg3.sw_dci_blk_hsize = sw_dci_blk_hsize;
+    dst_reg->dci.reg3.sw_dci_blk_vsize = sw_dci_blk_vsize;
+    dst_reg->dci.reg4.sw_dci_hist_addr = src_params->hist;
+}
+
+static void update_es_tan(EsParams* p_es_param)
+{
+    RK_U32 angle_lo_th, angle_hi_th;
+
+    angle_lo_th = 23 - p_es_param->es_iAngleDelta - p_es_param->es_iAngleDeltaExtra;
+    angle_hi_th = 23 + p_es_param->es_iAngleDelta;
+
+    p_es_param->es_tan_lo_th = mpp_clip(tan(angle_lo_th * acos(-1) / 180.0) * 512, 0, 511);
+    p_es_param->es_tan_hi_th = mpp_clip(tan(angle_hi_th * acos(-1) / 180.0) * 512, 0, 511);
+}
+
+
+static void set_es_to_vdpp2_reg(struct vdpp2_params* src_params, struct vdpp2_reg* dst_reg)
+{
+    EsParams *p_es_param = &src_params->es_params;
+    RK_U8 diff2conf_lut_k[8] = { 0 };
+    RK_U8 conf_local_mean_th = mpp_clip((256 * (float)p_es_param->es_iWgtLocalTh)
+                                        / p_es_param->es_iWgtGain, 0, 255);
+    RK_S32 i;
+
+    update_es_tan(p_es_param);
+
+    dst_reg->es.reg0.es_enable = p_es_param->es_bEnabledES;
+    dst_reg->es.reg1.dir_th    = p_es_param->es_iGradNoDirTh;
+    dst_reg->es.reg1.flat_th   = p_es_param->es_iGradFlatTh;
+
+    dst_reg->es.reg2.tan_lo_th = p_es_param->es_tan_lo_th;
+    dst_reg->es.reg2.tan_hi_th = p_es_param->es_tan_hi_th;
+
+    dst_reg->es.reg3.ep_chk_en = p_es_param->es_bEndpointCheckEnable;
+    //dst_reg->es.sw_dir_chk.MEM_GAT_EN
+
+    dst_reg->es.reg4.diff_gain0 = p_es_param->es_iK1;
+    dst_reg->es.reg4.diff_limit = p_es_param->es_iDeltaLimit;
+
+    dst_reg->es.reg5.diff_gain1 = p_es_param->es_iK2;
+    dst_reg->es.reg5.lut_x0     = p_es_param->es_iDiff2conf_lut_x[0];
+
+    dst_reg->es.reg6.lut_x1    = p_es_param->es_iDiff2conf_lut_x[1];
+    dst_reg->es.reg6.lut_x2    = p_es_param->es_iDiff2conf_lut_x[2];
+    dst_reg->es.reg7.lut_x3    = p_es_param->es_iDiff2conf_lut_x[3];
+    dst_reg->es.reg7.lut_x4    = p_es_param->es_iDiff2conf_lut_x[4];
+    dst_reg->es.reg8.lut_x5    = p_es_param->es_iDiff2conf_lut_x[5];
+    dst_reg->es.reg8.lut_x6    = p_es_param->es_iDiff2conf_lut_x[6];
+    dst_reg->es.reg9.lut_x7    = p_es_param->es_iDiff2conf_lut_x[7];
+    dst_reg->es.reg9.lut_x8    = p_es_param->es_iDiff2conf_lut_x[8];
+
+    dst_reg->es.reg10.lut_y0    = p_es_param->es_iDiff2conf_lut_y[0];
+    dst_reg->es.reg10.lut_y1    = p_es_param->es_iDiff2conf_lut_y[1];
+    dst_reg->es.reg10.lut_y2    = p_es_param->es_iDiff2conf_lut_y[2];
+    dst_reg->es.reg10.lut_y3    = p_es_param->es_iDiff2conf_lut_y[3];
+    dst_reg->es.reg11.lut_y4    = p_es_param->es_iDiff2conf_lut_y[4];
+    dst_reg->es.reg11.lut_y5    = p_es_param->es_iDiff2conf_lut_y[5];
+    dst_reg->es.reg11.lut_y6    = p_es_param->es_iDiff2conf_lut_y[6];
+    dst_reg->es.reg11.lut_y7    = p_es_param->es_iDiff2conf_lut_y[7];
+    dst_reg->es.reg12.lut_y8    = p_es_param->es_iDiff2conf_lut_y[8];
+
+    for (i = 0; i < 8; i++) {
+        double x0 = p_es_param->es_iDiff2conf_lut_x[i];
+        double x1 = p_es_param->es_iDiff2conf_lut_x[i + 1];
+        double y0 = p_es_param->es_iDiff2conf_lut_y[i];
+        double y1 = p_es_param->es_iDiff2conf_lut_y[i + 1];
+        diff2conf_lut_k[i] = mpp_clip(FLOOR(256 * (y1 - y0) / (x1 - x0)), 0, 255);
+    }
+    dst_reg->es.reg13.lut_k0 = diff2conf_lut_k[0];
+    dst_reg->es.reg13.lut_k1 = diff2conf_lut_k[1];
+    dst_reg->es.reg13.lut_k2 = diff2conf_lut_k[2];
+    dst_reg->es.reg13.lut_k3 = diff2conf_lut_k[3];
+    dst_reg->es.reg14.lut_k4 = diff2conf_lut_k[4];
+    dst_reg->es.reg14.lut_k5 = diff2conf_lut_k[5];
+    dst_reg->es.reg14.lut_k6 = diff2conf_lut_k[6];
+    dst_reg->es.reg14.lut_k7 = diff2conf_lut_k[7];
+
+    dst_reg->es.reg15.wgt_decay = p_es_param->es_iWgtDecay;
+    dst_reg->es.reg15.wgt_gain  = p_es_param->es_iWgtGain;
+
+    dst_reg->es.reg16.conf_mean_th    = conf_local_mean_th;
+    dst_reg->es.reg16.conf_cnt_th     = p_es_param->es_iConfCntTh;
+    dst_reg->es.reg16.low_conf_th     = p_es_param->es_iLowConfTh;
+    dst_reg->es.reg16.low_conf_ratio  = p_es_param->es_iLowConfRatio;
+}
+
+static void set_shp_to_vdpp2_reg(struct vdpp2_params* src_params, struct vdpp2_reg* dst_reg)
+{
+    ShpParams *p_shp_param = &src_params->shp_params;
+    /* Peaking Ctrl sw-process */
+    RK_S32 peaking_ctrl_idx_P0[7] = { 0 };
+    RK_S32 peaking_ctrl_idx_N0[7] = { 0 };
+    RK_S32 peaking_ctrl_idx_P1[7] = { 0 };
+    RK_S32 peaking_ctrl_idx_N1[7] = { 0 };
+    RK_S32 peaking_ctrl_idx_P2[7] = { 0 };
+    RK_S32 peaking_ctrl_idx_N2[7] = { 0 };
+    RK_S32 peaking_ctrl_idx_P3[7] = { 0 };
+    RK_S32 peaking_ctrl_idx_N3[7] = { 0 };
+
+    RK_S32 peaking_ctrl_value_N1[7] = { 0 };
+    RK_S32 peaking_ctrl_value_N2[7] = { 0 };
+    RK_S32 peaking_ctrl_value_N3[7] = { 0 };
+    RK_S32 peaking_ctrl_value_P1[7] = { 0 };
+    RK_S32 peaking_ctrl_value_P2[7] = { 0 };
+    RK_S32 peaking_ctrl_value_P3[7] = { 0 };
+
+    RK_S32 peaking_ctrl_ratio_P01[7] = { 0 };
+    RK_S32 peaking_ctrl_ratio_P12[7] = { 0 };
+    RK_S32 peaking_ctrl_ratio_P23[7] = { 0 };
+    RK_S32 peaking_ctrl_ratio_N01[7] = { 0 };
+    RK_S32 peaking_ctrl_ratio_N12[7] = { 0 };
+    RK_S32 peaking_ctrl_ratio_N23[7] = { 0 };
+
+    RK_S32 global_gain_slp_temp[5] = { 0 };
+    RK_S32 ii;
+    dst_reg->sharp.reg0.sw_sharp_enable            = p_shp_param->sharp_enable;
+    dst_reg->sharp.reg0.sw_lti_enable              = p_shp_param->lti_h_enable || p_shp_param->lti_v_enable;
+    dst_reg->sharp.reg0.sw_cti_enable              = p_shp_param->cti_h_enable;
+    dst_reg->sharp.reg0.sw_peaking_enable          = p_shp_param->peaking_enable;
+    dst_reg->sharp.reg0.sw_peaking_ctrl_enable     = p_shp_param->peaking_coring_enable || p_shp_param->peaking_gain_enable || p_shp_param->peaking_limit_ctrl_enable;
+    dst_reg->sharp.reg0.sw_edge_proc_enable        = p_shp_param->peaking_edge_ctrl_enable;
+    dst_reg->sharp.reg0.sw_shoot_ctrl_enable       = p_shp_param->shootctrl_enable;
+    dst_reg->sharp.reg0.sw_gain_ctrl_enable        = p_shp_param->global_gain_enable;
+    dst_reg->sharp.reg0.sw_color_adj_enable        = p_shp_param->color_ctrl_enable;
+    dst_reg->sharp.reg0.sw_texture_adj_enable      = p_shp_param->tex_adj_enable;
+    dst_reg->sharp.reg0.sw_coloradj_bypass_en      = p_shp_param->sharp_coloradj_bypass_en;
+    dst_reg->sharp.reg0.sw_ink_enable              = 0;
+    dst_reg->sharp.reg0.sw_sharp_redundent_bypass  = 0;
+
+    if ((dst_reg->sharp.reg0.sw_lti_enable == 1) && (p_shp_param->lti_h_enable == 0))
+        p_shp_param->lti_h_gain = 0;
+
+    if ((dst_reg->sharp.reg0.sw_lti_enable == 1) && (p_shp_param->lti_v_enable == 0))
+        p_shp_param->lti_v_gain = 0;
+
+    dst_reg->sharp.reg162.sw_ltih_radius        = p_shp_param->lti_h_radius;
+    dst_reg->sharp.reg162.sw_ltih_slp1          = p_shp_param->lti_h_slope;
+    dst_reg->sharp.reg162.sw_ltih_thr1          = p_shp_param->lti_h_thresold;
+    dst_reg->sharp.reg163.sw_ltih_noisethrneg   = p_shp_param->lti_h_noise_thr_neg;
+    dst_reg->sharp.reg163.sw_ltih_noisethrpos   = p_shp_param->lti_h_noise_thr_pos;
+    dst_reg->sharp.reg163.sw_ltih_tigain        = p_shp_param->lti_h_gain;
+
+    dst_reg->sharp.reg164.sw_ltiv_radius        = p_shp_param->lti_v_radius;
+    dst_reg->sharp.reg164.sw_ltiv_slp1          = p_shp_param->lti_v_slope;
+    dst_reg->sharp.reg164.sw_ltiv_thr1          = p_shp_param->lti_v_thresold;
+    dst_reg->sharp.reg165.sw_ltiv_noisethrneg   = p_shp_param->lti_v_noise_thr_neg;
+    dst_reg->sharp.reg165.sw_ltiv_noisethrpos   = p_shp_param->lti_v_noise_thr_pos;
+    dst_reg->sharp.reg165.sw_ltiv_tigain        = p_shp_param->lti_v_gain;
+
+    dst_reg->sharp.reg166.sw_ctih_radius        = p_shp_param->cti_h_radius;
+    dst_reg->sharp.reg166.sw_ctih_slp1          = p_shp_param->cti_h_slope;
+    dst_reg->sharp.reg166.sw_ctih_thr1          = p_shp_param->cti_h_thresold;
+    dst_reg->sharp.reg167.sw_ctih_noisethrneg   = p_shp_param->cti_h_noise_thr_neg;
+    dst_reg->sharp.reg167.sw_ctih_noisethrpos   = p_shp_param->cti_h_noise_thr_pos;
+    dst_reg->sharp.reg167.sw_ctih_tigain        = p_shp_param->cti_h_gain;
+
+    for (ii = 0; ii < 7; ii++) {
+        RK_S32 coring_ratio, coring_zero, coring_thr, gain_ctrl_pos,
+               gain_ctrl_neg, limit_ctrl_p0, limit_ctrl_p1, limit_ctrl_n0,
+               limit_ctrl_n1, limit_ctrl_ratio;
+        RK_S32 ratio_pos_tmp, ratio_neg_tmp, peaking_ctrl_add_tmp;
+
+        if (p_shp_param->peaking_coring_enable == 1) {
+            coring_ratio    = p_shp_param->peaking_coring_ratio[ii];
+            coring_zero     = p_shp_param->peaking_coring_zero[ii] >> 2;
+            coring_thr      = p_shp_param->peaking_coring_thr[ii] >> 2;
+        } else {
+            coring_ratio    = 1024;
+            coring_zero     = 0;
+            coring_thr      = 0;
+        }
+        if (p_shp_param->peaking_gain_enable == 1) {
+            gain_ctrl_pos   = p_shp_param->peaking_gain_pos[ii];
+            gain_ctrl_neg   = p_shp_param->peaking_gain_neg[ii];
+        } else {
+            gain_ctrl_pos   = 1024;
+            gain_ctrl_neg   = 1024;
+        }
+        if (p_shp_param->peaking_limit_ctrl_enable == 1) {
+            limit_ctrl_p0       = p_shp_param->peaking_limit_ctrl_pos0[ii] >> 2;
+            limit_ctrl_p1       = p_shp_param->peaking_limit_ctrl_pos1[ii] >> 2;
+            limit_ctrl_n0       = p_shp_param->peaking_limit_ctrl_neg0[ii] >> 2;
+            limit_ctrl_n1       = p_shp_param->peaking_limit_ctrl_neg1[ii] >> 2;
+            limit_ctrl_ratio    = p_shp_param->peaking_limit_ctrl_ratio[ii];
+        } else {
+            limit_ctrl_p0       = 255 >> 2;
+            limit_ctrl_p1       = 255 >> 2;
+            limit_ctrl_n0       = 255 >> 2;
+            limit_ctrl_n1       = 255 >> 2;
+            limit_ctrl_ratio    = 1024;
+        }
+
+        peaking_ctrl_idx_P0[ii] =  coring_zero;
+        peaking_ctrl_idx_N0[ii] = -coring_zero;
+        peaking_ctrl_idx_P1[ii] =  coring_thr;
+        peaking_ctrl_idx_N1[ii] = -coring_thr;
+        peaking_ctrl_idx_P2[ii] =  limit_ctrl_p0;
+        peaking_ctrl_idx_N2[ii] = -limit_ctrl_n0;
+        peaking_ctrl_idx_P3[ii] =  limit_ctrl_p1;
+        peaking_ctrl_idx_N3[ii] = -limit_ctrl_n1;
+
+        ratio_pos_tmp = (coring_ratio * gain_ctrl_pos + 512) >> 10;
+        ratio_neg_tmp = (coring_ratio * gain_ctrl_neg + 512) >> 10;
+        peaking_ctrl_value_P1[ii] =  ((ratio_pos_tmp * (coring_thr - coring_zero) + 512) >> 10);
+        peaking_ctrl_value_N1[ii] = -((ratio_neg_tmp * (coring_thr - coring_zero) + 512) >> 10);
+        peaking_ctrl_ratio_P01[ii] = ratio_pos_tmp;
+        peaking_ctrl_ratio_N01[ii] = ratio_neg_tmp;
+
+        peaking_ctrl_ratio_P12[ii] = gain_ctrl_pos;
+        peaking_ctrl_ratio_N12[ii] = gain_ctrl_neg;
+
+        peaking_ctrl_add_tmp = (gain_ctrl_pos * (limit_ctrl_p0 - coring_thr) + 512) >> 10;
+        peaking_ctrl_value_P2[ii] = peaking_ctrl_value_P1[ii] + peaking_ctrl_add_tmp;
+        peaking_ctrl_add_tmp = (gain_ctrl_neg * (limit_ctrl_n0 - coring_thr) + 512) >> 10;
+        peaking_ctrl_value_N2[ii] = peaking_ctrl_value_N1[ii] - peaking_ctrl_add_tmp;
+
+        ratio_pos_tmp = (limit_ctrl_ratio * gain_ctrl_pos + 512) >> 10;
+        ratio_neg_tmp = (limit_ctrl_ratio * gain_ctrl_neg + 512) >> 10;
+
+        peaking_ctrl_add_tmp = (ratio_pos_tmp * (limit_ctrl_p1 - limit_ctrl_p0) + 512) >> 10;
+        peaking_ctrl_value_P3[ii] = peaking_ctrl_value_P2[ii] + peaking_ctrl_add_tmp;
+        peaking_ctrl_add_tmp = (ratio_neg_tmp * (limit_ctrl_n1 - limit_ctrl_n0) + 512) >> 10;
+        peaking_ctrl_value_N3[ii] = peaking_ctrl_value_N2[ii] - peaking_ctrl_add_tmp;
+        peaking_ctrl_ratio_P23[ii] = ratio_pos_tmp;
+        peaking_ctrl_ratio_N23[ii] = ratio_neg_tmp;
+
+        peaking_ctrl_idx_N0[ii] = mpp_clip(peaking_ctrl_idx_N0[ii], -256, 255);
+        peaking_ctrl_idx_N1[ii] = mpp_clip(peaking_ctrl_idx_N1[ii], -256, 255);
+        peaking_ctrl_idx_N2[ii] = mpp_clip(peaking_ctrl_idx_N2[ii], -256, 255);
+        peaking_ctrl_idx_N3[ii] = mpp_clip(peaking_ctrl_idx_N3[ii], -256, 255);
+        peaking_ctrl_idx_P0[ii] = mpp_clip(peaking_ctrl_idx_P0[ii], -256, 255);
+        peaking_ctrl_idx_P1[ii] = mpp_clip(peaking_ctrl_idx_P1[ii], -256, 255);
+        peaking_ctrl_idx_P2[ii] = mpp_clip(peaking_ctrl_idx_P2[ii], -256, 255);
+        peaking_ctrl_idx_P3[ii] = mpp_clip(peaking_ctrl_idx_P3[ii], -256, 255);
+
+        peaking_ctrl_value_N1[ii] = mpp_clip(peaking_ctrl_value_N1[ii], -256, 255);
+        peaking_ctrl_value_N2[ii] = mpp_clip(peaking_ctrl_value_N2[ii], -256, 255);
+        peaking_ctrl_value_N3[ii] = mpp_clip(peaking_ctrl_value_N3[ii], -256, 255);
+        peaking_ctrl_value_P1[ii] = mpp_clip(peaking_ctrl_value_P1[ii], -256, 255);
+        peaking_ctrl_value_P2[ii] = mpp_clip(peaking_ctrl_value_P2[ii], -256, 255);
+        peaking_ctrl_value_P3[ii] = mpp_clip(peaking_ctrl_value_P3[ii], -256, 255);
+
+        peaking_ctrl_ratio_P01[ii] = mpp_clip(peaking_ctrl_ratio_P01[ii], 0, 4095);
+        peaking_ctrl_ratio_P12[ii] = mpp_clip(peaking_ctrl_ratio_P12[ii], 0, 4095);
+        peaking_ctrl_ratio_P23[ii] = mpp_clip(peaking_ctrl_ratio_P23[ii], 0, 4095);
+        peaking_ctrl_ratio_N01[ii] = mpp_clip(peaking_ctrl_ratio_N01[ii], 0, 4095);
+        peaking_ctrl_ratio_N12[ii] = mpp_clip(peaking_ctrl_ratio_N12[ii], 0, 4095);
+        peaking_ctrl_ratio_N23[ii] = mpp_clip(peaking_ctrl_ratio_N23[ii], 0, 4095);
+    }
+
+    dst_reg->sharp.reg12.sw_peaking0_idx_n0       = peaking_ctrl_idx_N0[0];
+    dst_reg->sharp.reg12.sw_peaking0_idx_n1       = peaking_ctrl_idx_N1[0];
+    dst_reg->sharp.reg13.sw_peaking0_idx_n2       = peaking_ctrl_idx_N2[0];
+    dst_reg->sharp.reg13.sw_peaking0_idx_n3       = peaking_ctrl_idx_N3[0];
+    dst_reg->sharp.reg14.sw_peaking0_idx_p0       = peaking_ctrl_idx_P0[0];
+    dst_reg->sharp.reg14.sw_peaking0_idx_p1       = peaking_ctrl_idx_P1[0];
+    dst_reg->sharp.reg15.sw_peaking0_idx_p2       = peaking_ctrl_idx_P2[0];
+    dst_reg->sharp.reg15.sw_peaking0_idx_p3       = peaking_ctrl_idx_P3[0];
+    dst_reg->sharp.reg16.sw_peaking0_value_n1     = peaking_ctrl_value_N1[0];
+    dst_reg->sharp.reg16.sw_peaking0_value_n2     = peaking_ctrl_value_N2[0];
+    dst_reg->sharp.reg17.sw_peaking0_value_n3     = peaking_ctrl_value_N3[0];
+    dst_reg->sharp.reg17.sw_peaking0_value_p1     = peaking_ctrl_value_P1[0];
+    dst_reg->sharp.reg18.sw_peaking0_value_p2     = peaking_ctrl_value_P2[0];
+    dst_reg->sharp.reg18.sw_peaking0_value_p3     = peaking_ctrl_value_P3[0];
+    dst_reg->sharp.reg19.sw_peaking0_ratio_n01    = peaking_ctrl_ratio_N01[0];
+    dst_reg->sharp.reg19.sw_peaking0_ratio_n12    = peaking_ctrl_ratio_N12[0];
+    dst_reg->sharp.reg20.sw_peaking0_ratio_n23    = peaking_ctrl_ratio_N23[0];
+    dst_reg->sharp.reg20.sw_peaking0_ratio_p01    = peaking_ctrl_ratio_P01[0];
+    dst_reg->sharp.reg21.sw_peaking0_ratio_p12    = peaking_ctrl_ratio_P12[0];
+    dst_reg->sharp.reg21.sw_peaking0_ratio_p23    = peaking_ctrl_ratio_P23[0];
+
+    dst_reg->sharp.reg23.sw_peaking1_idx_n0       = peaking_ctrl_idx_N0[1];
+    dst_reg->sharp.reg23.sw_peaking1_idx_n1       = peaking_ctrl_idx_N1[1];
+    dst_reg->sharp.reg24.sw_peaking1_idx_n2       = peaking_ctrl_idx_N2[1];
+    dst_reg->sharp.reg24.sw_peaking1_idx_n3       = peaking_ctrl_idx_N3[1];
+    dst_reg->sharp.reg25.sw_peaking1_idx_p0       = peaking_ctrl_idx_P0[1];
+    dst_reg->sharp.reg25.sw_peaking1_idx_p1       = peaking_ctrl_idx_P1[1];
+    dst_reg->sharp.reg26.sw_peaking1_idx_p2       = peaking_ctrl_idx_P2[1];
+    dst_reg->sharp.reg26.sw_peaking1_idx_p3       = peaking_ctrl_idx_P3[1];
+    dst_reg->sharp.reg27.sw_peaking1_value_n1     = peaking_ctrl_value_N1[1];
+    dst_reg->sharp.reg27.sw_peaking1_value_n2     = peaking_ctrl_value_N2[1];
+    dst_reg->sharp.reg28.sw_peaking1_value_n3     = peaking_ctrl_value_N3[1];
+    dst_reg->sharp.reg28.sw_peaking1_value_p1     = peaking_ctrl_value_P1[1];
+    dst_reg->sharp.reg29.sw_peaking1_value_p2     = peaking_ctrl_value_P2[1];
+    dst_reg->sharp.reg29.sw_peaking1_value_p3     = peaking_ctrl_value_P3[1];
+    dst_reg->sharp.reg30.sw_peaking1_ratio_n01    = peaking_ctrl_ratio_N01[1];
+    dst_reg->sharp.reg30.sw_peaking1_ratio_n12    = peaking_ctrl_ratio_N12[1];
+    dst_reg->sharp.reg31.sw_peaking1_ratio_n23    = peaking_ctrl_ratio_N23[1];
+    dst_reg->sharp.reg31.sw_peaking1_ratio_p01    = peaking_ctrl_ratio_P01[1];
+    dst_reg->sharp.reg32.sw_peaking1_ratio_p12    = peaking_ctrl_ratio_P12[1];
+    dst_reg->sharp.reg32.sw_peaking1_ratio_p23    = peaking_ctrl_ratio_P23[1];
+
+    dst_reg->sharp.reg34.sw_peaking2_idx_n0       = peaking_ctrl_idx_N0[2];
+    dst_reg->sharp.reg34.sw_peaking2_idx_n1       = peaking_ctrl_idx_N1[2];
+    dst_reg->sharp.reg35.sw_peaking2_idx_n2       = peaking_ctrl_idx_N2[2];
+    dst_reg->sharp.reg35.sw_peaking2_idx_n3       = peaking_ctrl_idx_N3[2];
+    dst_reg->sharp.reg36.sw_peaking2_idx_p0       = peaking_ctrl_idx_P0[2];
+    dst_reg->sharp.reg36.sw_peaking2_idx_p1       = peaking_ctrl_idx_P1[2];
+    dst_reg->sharp.reg37.sw_peaking2_idx_p2       = peaking_ctrl_idx_P2[2];
+    dst_reg->sharp.reg37.sw_peaking2_idx_p3       = peaking_ctrl_idx_P3[2];
+    dst_reg->sharp.reg38.sw_peaking2_value_n1     = peaking_ctrl_value_N1[2];
+    dst_reg->sharp.reg38.sw_peaking2_value_n2     = peaking_ctrl_value_N2[2];
+    dst_reg->sharp.reg39.sw_peaking2_value_n3     = peaking_ctrl_value_N3[2];
+    dst_reg->sharp.reg39.sw_peaking2_value_p1     = peaking_ctrl_value_P1[2];
+    dst_reg->sharp.reg40.sw_peaking2_value_p2     = peaking_ctrl_value_P2[2];
+    dst_reg->sharp.reg40.sw_peaking2_value_p3     = peaking_ctrl_value_P3[2];
+    dst_reg->sharp.reg41.sw_peaking2_ratio_n01    = peaking_ctrl_ratio_N01[2];
+    dst_reg->sharp.reg41.sw_peaking2_ratio_n12    = peaking_ctrl_ratio_N12[2];
+    dst_reg->sharp.reg42.sw_peaking2_ratio_n23    = peaking_ctrl_ratio_N23[2];
+    dst_reg->sharp.reg42.sw_peaking2_ratio_p01    = peaking_ctrl_ratio_P01[2];
+    dst_reg->sharp.reg43.sw_peaking2_ratio_p12    = peaking_ctrl_ratio_P12[2];
+    dst_reg->sharp.reg43.sw_peaking2_ratio_p23    = peaking_ctrl_ratio_P23[2];
+
+    dst_reg->sharp.reg45.sw_peaking3_idx_n0       = peaking_ctrl_idx_N0[3];
+    dst_reg->sharp.reg45.sw_peaking3_idx_n1       = peaking_ctrl_idx_N1[3];
+    dst_reg->sharp.reg46.sw_peaking3_idx_n2       = peaking_ctrl_idx_N2[3];
+    dst_reg->sharp.reg46.sw_peaking3_idx_n3       = peaking_ctrl_idx_N3[3];
+    dst_reg->sharp.reg47.sw_peaking3_idx_p0       = peaking_ctrl_idx_P0[3];
+    dst_reg->sharp.reg47.sw_peaking3_idx_p1       = peaking_ctrl_idx_P1[3];
+    dst_reg->sharp.reg48.sw_peaking3_idx_p2       = peaking_ctrl_idx_P2[3];
+    dst_reg->sharp.reg48.sw_peaking3_idx_p3       = peaking_ctrl_idx_P3[3];
+    dst_reg->sharp.reg49.sw_peaking3_value_n1     = peaking_ctrl_value_N1[3];
+    dst_reg->sharp.reg49.sw_peaking3_value_n2     = peaking_ctrl_value_N2[3];
+    dst_reg->sharp.reg50.sw_peaking3_value_n3     = peaking_ctrl_value_N3[3];
+    dst_reg->sharp.reg50.sw_peaking3_value_p1     = peaking_ctrl_value_P1[3];
+    dst_reg->sharp.reg51.sw_peaking3_value_p2     = peaking_ctrl_value_P2[3];
+    dst_reg->sharp.reg51.sw_peaking3_value_p3     = peaking_ctrl_value_P3[3];
+    dst_reg->sharp.reg52.sw_peaking3_ratio_n01    = peaking_ctrl_ratio_N01[3];
+    dst_reg->sharp.reg52.sw_peaking3_ratio_n12    = peaking_ctrl_ratio_N12[3];
+    dst_reg->sharp.reg53.sw_peaking3_ratio_n23    = peaking_ctrl_ratio_N23[3];
+    dst_reg->sharp.reg53.sw_peaking3_ratio_p01    = peaking_ctrl_ratio_P01[3];
+    dst_reg->sharp.reg54.sw_peaking3_ratio_p12    = peaking_ctrl_ratio_P12[3];
+    dst_reg->sharp.reg54.sw_peaking3_ratio_p23    = peaking_ctrl_ratio_P23[3];
+
+    dst_reg->sharp.reg56.sw_peaking4_idx_n0       = peaking_ctrl_idx_N0[4];
+    dst_reg->sharp.reg56.sw_peaking4_idx_n1       = peaking_ctrl_idx_N1[4];
+    dst_reg->sharp.reg57.sw_peaking4_idx_n2       = peaking_ctrl_idx_N2[4];
+    dst_reg->sharp.reg57.sw_peaking4_idx_n3       = peaking_ctrl_idx_N3[4];
+    dst_reg->sharp.reg58.sw_peaking4_idx_p0       = peaking_ctrl_idx_P0[4];
+    dst_reg->sharp.reg58.sw_peaking4_idx_p1       = peaking_ctrl_idx_P1[4];
+    dst_reg->sharp.reg59.sw_peaking4_idx_p2       = peaking_ctrl_idx_P2[4];
+    dst_reg->sharp.reg59.sw_peaking4_idx_p3       = peaking_ctrl_idx_P3[4];
+    dst_reg->sharp.reg60.sw_peaking4_value_n1     = peaking_ctrl_value_N1[4];
+    dst_reg->sharp.reg60.sw_peaking4_value_n2     = peaking_ctrl_value_N2[4];
+    dst_reg->sharp.reg61.sw_peaking4_value_n3     = peaking_ctrl_value_N3[4];
+    dst_reg->sharp.reg61.sw_peaking4_value_p1     = peaking_ctrl_value_P1[4];
+    dst_reg->sharp.reg62.sw_peaking4_value_p2     = peaking_ctrl_value_P2[4];
+    dst_reg->sharp.reg62.sw_peaking4_value_p3     = peaking_ctrl_value_P3[4];
+    dst_reg->sharp.reg63.sw_peaking4_ratio_n01    = peaking_ctrl_ratio_N01[4];
+    dst_reg->sharp.reg63.sw_peaking4_ratio_n12    = peaking_ctrl_ratio_N12[4];
+    dst_reg->sharp.reg64.sw_peaking4_ratio_n23    = peaking_ctrl_ratio_N23[4];
+    dst_reg->sharp.reg64.sw_peaking4_ratio_p01    = peaking_ctrl_ratio_P01[4];
+    dst_reg->sharp.reg65.sw_peaking4_ratio_p12    = peaking_ctrl_ratio_P12[4];
+    dst_reg->sharp.reg65.sw_peaking4_ratio_p23    = peaking_ctrl_ratio_P23[4];
+
+    dst_reg->sharp.reg67.sw_peaking5_idx_n0       = peaking_ctrl_idx_N0[5];
+    dst_reg->sharp.reg67.sw_peaking5_idx_n1       = peaking_ctrl_idx_N1[5];
+    dst_reg->sharp.reg68.sw_peaking5_idx_n2       = peaking_ctrl_idx_N2[5];
+    dst_reg->sharp.reg68.sw_peaking5_idx_n3       = peaking_ctrl_idx_N3[5];
+    dst_reg->sharp.reg69.sw_peaking5_idx_p0       = peaking_ctrl_idx_P0[5];
+    dst_reg->sharp.reg69.sw_peaking5_idx_p1       = peaking_ctrl_idx_P1[5];
+    dst_reg->sharp.reg70.sw_peaking5_idx_p2       = peaking_ctrl_idx_P2[5];
+    dst_reg->sharp.reg70.sw_peaking5_idx_p3       = peaking_ctrl_idx_P3[5];
+    dst_reg->sharp.reg71.sw_peaking5_value_n1     = peaking_ctrl_value_N1[5];
+    dst_reg->sharp.reg71.sw_peaking5_value_n2     = peaking_ctrl_value_N2[5];
+    dst_reg->sharp.reg72.sw_peaking5_value_n3     = peaking_ctrl_value_N3[5];
+    dst_reg->sharp.reg72.sw_peaking5_value_p1     = peaking_ctrl_value_P1[5];
+    dst_reg->sharp.reg73.sw_peaking5_value_p2     = peaking_ctrl_value_P2[5];
+    dst_reg->sharp.reg73.sw_peaking5_value_p3     = peaking_ctrl_value_P3[5];
+    dst_reg->sharp.reg74.sw_peaking5_ratio_n01    = peaking_ctrl_ratio_N01[5];
+    dst_reg->sharp.reg74.sw_peaking5_ratio_n12    = peaking_ctrl_ratio_N12[5];
+    dst_reg->sharp.reg75.sw_peaking5_ratio_n23    = peaking_ctrl_ratio_N23[5];
+    dst_reg->sharp.reg75.sw_peaking5_ratio_p01    = peaking_ctrl_ratio_P01[5];
+    dst_reg->sharp.reg76.sw_peaking5_ratio_p12    = peaking_ctrl_ratio_P12[5];
+    dst_reg->sharp.reg76.sw_peaking5_ratio_p23    = peaking_ctrl_ratio_P23[5];
+
+    dst_reg->sharp.reg78.sw_peaking6_idx_n0       = peaking_ctrl_idx_N0[6];
+    dst_reg->sharp.reg78.sw_peaking6_idx_n1       = peaking_ctrl_idx_N1[6];
+    dst_reg->sharp.reg79.sw_peaking6_idx_n2       = peaking_ctrl_idx_N2[6];
+    dst_reg->sharp.reg79.sw_peaking6_idx_n3       = peaking_ctrl_idx_N3[6];
+    dst_reg->sharp.reg80.sw_peaking6_idx_p0       = peaking_ctrl_idx_P0[6];
+    dst_reg->sharp.reg80.sw_peaking6_idx_p1       = peaking_ctrl_idx_P1[6];
+    dst_reg->sharp.reg81.sw_peaking6_idx_p2       = peaking_ctrl_idx_P2[6];
+    dst_reg->sharp.reg81.sw_peaking6_idx_p3       = peaking_ctrl_idx_P3[6];
+    dst_reg->sharp.reg82.sw_peaking6_value_n1     = peaking_ctrl_value_N1[6];
+    dst_reg->sharp.reg82.sw_peaking6_value_n2     = peaking_ctrl_value_N2[6];
+    dst_reg->sharp.reg83.sw_peaking6_value_n3     = peaking_ctrl_value_N3[6];
+    dst_reg->sharp.reg83.sw_peaking6_value_p1     = peaking_ctrl_value_P1[6];
+    dst_reg->sharp.reg84.sw_peaking6_value_p2     = peaking_ctrl_value_P2[6];
+    dst_reg->sharp.reg84.sw_peaking6_value_p3     = peaking_ctrl_value_P3[6];
+    dst_reg->sharp.reg85.sw_peaking6_ratio_n01    = peaking_ctrl_ratio_N01[6];
+    dst_reg->sharp.reg85.sw_peaking6_ratio_n12    = peaking_ctrl_ratio_N12[6];
+    dst_reg->sharp.reg86.sw_peaking6_ratio_n23    = peaking_ctrl_ratio_N23[6];
+    dst_reg->sharp.reg86.sw_peaking6_ratio_p01    = peaking_ctrl_ratio_P01[6];
+    dst_reg->sharp.reg87.sw_peaking6_ratio_p12    = peaking_ctrl_ratio_P12[6];
+    dst_reg->sharp.reg87.sw_peaking6_ratio_p23    = peaking_ctrl_ratio_P23[6];
+
+    dst_reg->sharp.reg2.sw_peaking_v00  = p_shp_param->peaking_filt_core_V0[0];
+    dst_reg->sharp.reg2.sw_peaking_v01  = p_shp_param->peaking_filt_core_V0[1];
+    dst_reg->sharp.reg2.sw_peaking_v02  = p_shp_param->peaking_filt_core_V0[2];
+    dst_reg->sharp.reg2.sw_peaking_v10  = p_shp_param->peaking_filt_core_V1[0];
+    dst_reg->sharp.reg2.sw_peaking_v11  = p_shp_param->peaking_filt_core_V1[1];
+    dst_reg->sharp.reg2.sw_peaking_v12  = p_shp_param->peaking_filt_core_V1[2];
+    dst_reg->sharp.reg3.sw_peaking_v20  = p_shp_param->peaking_filt_core_V2[0];
+    dst_reg->sharp.reg3.sw_peaking_v21  = p_shp_param->peaking_filt_core_V2[1];
+    dst_reg->sharp.reg3.sw_peaking_v22  = p_shp_param->peaking_filt_core_V2[2];
+    dst_reg->sharp.reg3.sw_peaking_usm0 = p_shp_param->peaking_filt_core_USM[0];
+    dst_reg->sharp.reg3.sw_peaking_usm1 = p_shp_param->peaking_filt_core_USM[1];
+    dst_reg->sharp.reg3.sw_peaking_usm2 = p_shp_param->peaking_filt_core_USM[2];
+    dst_reg->sharp.reg3.sw_diag_coef    = p_shp_param->peaking_filter_cfg_diag_enh_coef;
+    dst_reg->sharp.reg4.sw_peaking_h00  = p_shp_param->peaking_filt_core_H0[0];
+    dst_reg->sharp.reg4.sw_peaking_h01  = p_shp_param->peaking_filt_core_H0[1];
+    dst_reg->sharp.reg4.sw_peaking_h02  = p_shp_param->peaking_filt_core_H0[2];
+    dst_reg->sharp.reg6.sw_peaking_h10  = p_shp_param->peaking_filt_core_H1[0];
+    dst_reg->sharp.reg6.sw_peaking_h11  = p_shp_param->peaking_filt_core_H1[1];
+    dst_reg->sharp.reg6.sw_peaking_h12  = p_shp_param->peaking_filt_core_H1[2];
+    dst_reg->sharp.reg8.sw_peaking_h20  = p_shp_param->peaking_filt_core_H2[0];
+    dst_reg->sharp.reg8.sw_peaking_h21  = p_shp_param->peaking_filt_core_H2[1];
+    dst_reg->sharp.reg8.sw_peaking_h22  = p_shp_param->peaking_filt_core_H2[2];
+
+    dst_reg->sharp.reg100.sw_peaking_gain       = p_shp_param->peaking_gain;
+    dst_reg->sharp.reg100.sw_nondir_thr         = p_shp_param->peaking_edge_ctrl_non_dir_thr;
+    dst_reg->sharp.reg100.sw_dir_cmp_ratio      = p_shp_param->peaking_edge_ctrl_dir_cmp_ratio;
+    dst_reg->sharp.reg100.sw_nondir_wgt_ratio   = p_shp_param->peaking_edge_ctrl_non_dir_wgt_ratio;
+    dst_reg->sharp.reg101.sw_nondir_wgt_offset  = p_shp_param->peaking_edge_ctrl_non_dir_wgt_offset;
+    dst_reg->sharp.reg101.sw_dir_cnt_thr        = p_shp_param->peaking_edge_ctrl_dir_cnt_thr;
+    dst_reg->sharp.reg101.sw_dir_cnt_avg        = p_shp_param->peaking_edge_ctrl_dir_cnt_avg;
+    dst_reg->sharp.reg101.sw_dir_cnt_offset     = p_shp_param->peaking_edge_ctrl_dir_cnt_offset;
+    dst_reg->sharp.reg101.sw_diag_dir_thr       = p_shp_param->peaking_edge_ctrl_diag_dir_thr;
+    dst_reg->sharp.reg102.sw_diag_adjgain_tab0  = p_shp_param->peaking_edge_ctrl_diag_adj_gain_tab[0];
+    dst_reg->sharp.reg102.sw_diag_adjgain_tab1  = p_shp_param->peaking_edge_ctrl_diag_adj_gain_tab[1];
+    dst_reg->sharp.reg102.sw_diag_adjgain_tab2  = p_shp_param->peaking_edge_ctrl_diag_adj_gain_tab[2];
+    dst_reg->sharp.reg102.sw_diag_adjgain_tab3  = p_shp_param->peaking_edge_ctrl_diag_adj_gain_tab[3];
+    dst_reg->sharp.reg102.sw_diag_adjgain_tab4  = p_shp_param->peaking_edge_ctrl_diag_adj_gain_tab[4];
+    dst_reg->sharp.reg102.sw_diag_adjgain_tab5  = p_shp_param->peaking_edge_ctrl_diag_adj_gain_tab[5];
+    dst_reg->sharp.reg102.sw_diag_adjgain_tab6  = p_shp_param->peaking_edge_ctrl_diag_adj_gain_tab[6];
+    dst_reg->sharp.reg102.sw_diag_adjgain_tab7  = p_shp_param->peaking_edge_ctrl_diag_adj_gain_tab[7];
+
+    dst_reg->sharp.reg103.sw_edge_alpha_over_non            = p_shp_param->peaking_estc_alpha_over_non;
+    dst_reg->sharp.reg103.sw_edge_alpha_under_non           = p_shp_param->peaking_estc_alpha_under_non;
+    dst_reg->sharp.reg103.sw_edge_alpha_over_unlimit_non    = p_shp_param->peaking_estc_alpha_over_unlimit_non;
+    dst_reg->sharp.reg103.sw_edge_alpha_under_unlimit_non   = p_shp_param->peaking_estc_alpha_under_unlimit_non;
+
+    dst_reg->sharp.reg104.sw_edge_alpha_over_v              = p_shp_param->peaking_estc_alpha_over_v;
+    dst_reg->sharp.reg104.sw_edge_alpha_under_v             = p_shp_param->peaking_estc_alpha_under_v;
+    dst_reg->sharp.reg104.sw_edge_alpha_over_unlimit_v      = p_shp_param->peaking_estc_alpha_over_unlimit_v;
+    dst_reg->sharp.reg104.sw_edge_alpha_under_unlimit_v     = p_shp_param->peaking_estc_alpha_under_unlimit_v;
+
+    dst_reg->sharp.reg105.sw_edge_alpha_over_h              = p_shp_param->peaking_estc_alpha_over_h;
+    dst_reg->sharp.reg105.sw_edge_alpha_under_h             = p_shp_param->peaking_estc_alpha_under_h;
+    dst_reg->sharp.reg105.sw_edge_alpha_over_unlimit_h      = p_shp_param->peaking_estc_alpha_over_unlimit_h;
+    dst_reg->sharp.reg105.sw_edge_alpha_under_unlimit_h     = p_shp_param->peaking_estc_alpha_under_unlimit_h;
+
+    dst_reg->sharp.reg106.sw_edge_alpha_over_d0             = p_shp_param->peaking_estc_alpha_over_d0;
+    dst_reg->sharp.reg106.sw_edge_alpha_under_d0            = p_shp_param->peaking_estc_alpha_under_d0;
+    dst_reg->sharp.reg106.sw_edge_alpha_over_unlimit_d0     = p_shp_param->peaking_estc_alpha_over_unlimit_d0;
+    dst_reg->sharp.reg106.sw_edge_alpha_under_unlimit_d0    = p_shp_param->peaking_estc_alpha_under_unlimit_d0;
+
+    dst_reg->sharp.reg107.sw_edge_alpha_over_d1             = p_shp_param->peaking_estc_alpha_over_d1;
+    dst_reg->sharp.reg107.sw_edge_alpha_under_d1            = p_shp_param->peaking_estc_alpha_under_d1;
+    dst_reg->sharp.reg107.sw_edge_alpha_over_unlimit_d1     = p_shp_param->peaking_estc_alpha_over_unlimit_d1;
+    dst_reg->sharp.reg107.sw_edge_alpha_under_unlimit_d1    = p_shp_param->peaking_estc_alpha_under_unlimit_d1;
+
+    dst_reg->sharp.reg108.sw_edge_delta_offset_non          = p_shp_param->peaking_estc_delta_offset_non;
+    dst_reg->sharp.reg108.sw_edge_delta_offset_v            = p_shp_param->peaking_estc_delta_offset_v;
+    dst_reg->sharp.reg108.sw_edge_delta_offset_h            = p_shp_param->peaking_estc_delta_offset_h;
+    dst_reg->sharp.reg109.sw_edge_delta_offset_d0           = p_shp_param->peaking_estc_delta_offset_d0;
+    dst_reg->sharp.reg109.sw_edge_delta_offset_d1           = p_shp_param->peaking_estc_delta_offset_d1;
+
+    dst_reg->sharp.reg110.sw_shoot_filt_radius            = p_shp_param->shootctrl_filter_radius;
+    dst_reg->sharp.reg110.sw_shoot_delta_offset           = p_shp_param->shootctrl_delta_offset;
+    dst_reg->sharp.reg110.sw_shoot_alpha_over             = p_shp_param->shootctrl_alpha_over;
+    dst_reg->sharp.reg110.sw_shoot_alpha_under            = p_shp_param->shootctrl_alpha_under;
+    dst_reg->sharp.reg111.sw_shoot_alpha_over_unlimit     = p_shp_param->shootctrl_alpha_over_unlimit;
+    dst_reg->sharp.reg111.sw_shoot_alpha_under_unlimit    = p_shp_param->shootctrl_alpha_under_unlimit;
+
+
+    //dst_reg->sharp.reg112.sw_adp_idx0      = p_shp_param->global_gain_adp_grd
+    dst_reg->sharp.reg112.sw_adp_idx0       = p_shp_param->global_gain_adp_grd[1] >> 2;
+    dst_reg->sharp.reg112.sw_adp_idx1       = p_shp_param->global_gain_adp_grd[2] >> 2;
+    dst_reg->sharp.reg112.sw_adp_idx2       = p_shp_param->global_gain_adp_grd[3] >> 2;
+    dst_reg->sharp.reg113.sw_adp_idx3       = p_shp_param->global_gain_adp_grd[4] >> 2;
+    dst_reg->sharp.reg113.sw_adp_gain0  = p_shp_param->global_gain_adp_val[0];
+    dst_reg->sharp.reg113.sw_adp_gain1  = p_shp_param->global_gain_adp_val[1];
+    dst_reg->sharp.reg114.sw_adp_gain2  = p_shp_param->global_gain_adp_val[2];
+    dst_reg->sharp.reg114.sw_adp_gain3  = p_shp_param->global_gain_adp_val[3];
+    dst_reg->sharp.reg114.sw_adp_gain4  = p_shp_param->global_gain_adp_val[4];
+    global_gain_slp_temp[0]  = ROUND(128 * (float)(dst_reg->sharp.reg113.sw_adp_gain1 - dst_reg->sharp.reg113.sw_adp_gain0)
+                                     / MPP_MAX((float)(dst_reg->sharp.reg112.sw_adp_idx0 - 0), 1));
+    global_gain_slp_temp[1]  = ROUND(128 * (float)(dst_reg->sharp.reg114.sw_adp_gain2 - dst_reg->sharp.reg113.sw_adp_gain1)
+                                     / MPP_MAX((float)(dst_reg->sharp.reg112.sw_adp_idx1 - dst_reg->sharp.reg112.sw_adp_idx0), 1));
+    global_gain_slp_temp[2]  = ROUND(128 * (float)(dst_reg->sharp.reg114.sw_adp_gain3 - dst_reg->sharp.reg114.sw_adp_gain2)
+                                     / MPP_MAX((float)(dst_reg->sharp.reg112.sw_adp_idx2 - dst_reg->sharp.reg112.sw_adp_idx1), 1));
+    global_gain_slp_temp[3]  = ROUND(128 * (float)(dst_reg->sharp.reg114.sw_adp_gain4 - dst_reg->sharp.reg114.sw_adp_gain3)
+                                     / MPP_MAX((float)(dst_reg->sharp.reg113.sw_adp_idx3 - dst_reg->sharp.reg112.sw_adp_idx2), 1));
+    global_gain_slp_temp[4]  = ROUND(128 * (float)(p_shp_param->global_gain_adp_val[5] - dst_reg->sharp.reg114.sw_adp_gain4)
+                                     / MPP_MAX((float)(255 - dst_reg->sharp.reg113.sw_adp_idx3), 1));
+    dst_reg->sharp.reg115.sw_adp_slp01     = mpp_clip(global_gain_slp_temp[0], -1024, 1023);
+    dst_reg->sharp.reg115.sw_adp_slp12     = mpp_clip(global_gain_slp_temp[1], -1024, 1023);
+    dst_reg->sharp.reg128.sw_adp_slp23     = mpp_clip(global_gain_slp_temp[2], -1024, 1023);
+    dst_reg->sharp.reg128.sw_adp_slp34     = mpp_clip(global_gain_slp_temp[3], -1024, 1023);
+    dst_reg->sharp.reg129.sw_adp_slp45     = mpp_clip(global_gain_slp_temp[4], -1024, 1023);
+
+    dst_reg->sharp.reg129.sw_var_idx0       = p_shp_param->global_gain_var_grd[1] >> 2;
+    dst_reg->sharp.reg129.sw_var_idx1       = p_shp_param->global_gain_var_grd[2] >> 2;
+    dst_reg->sharp.reg130.sw_var_idx2       = p_shp_param->global_gain_var_grd[3] >> 2;
+    dst_reg->sharp.reg130.sw_var_idx3       = p_shp_param->global_gain_var_grd[4] >> 2;
+    dst_reg->sharp.reg130.sw_var_gain0  = p_shp_param->global_gain_var_val[0];
+    dst_reg->sharp.reg131.sw_var_gain1  = p_shp_param->global_gain_var_val[1];
+    dst_reg->sharp.reg131.sw_var_gain2  = p_shp_param->global_gain_var_val[2];
+    dst_reg->sharp.reg131.sw_var_gain3  = p_shp_param->global_gain_var_val[3];
+    dst_reg->sharp.reg131.sw_var_gain4  = p_shp_param->global_gain_var_val[4];
+    global_gain_slp_temp[0]  = ROUND(128 * (float)(dst_reg->sharp.reg131.sw_var_gain1 - dst_reg->sharp.reg130.sw_var_gain0)
+                                     / MPP_MAX((float)(dst_reg->sharp.reg129.sw_var_idx0 - 0), 1));
+    global_gain_slp_temp[1]  = ROUND(128 * (float)(dst_reg->sharp.reg131.sw_var_gain2 - dst_reg->sharp.reg131.sw_var_gain1)
+                                     / MPP_MAX((float)(dst_reg->sharp.reg129.sw_var_idx1 - dst_reg->sharp.reg129.sw_var_idx0), 1));
+    global_gain_slp_temp[2]  = ROUND(128 * (float)(dst_reg->sharp.reg131.sw_var_gain3 - dst_reg->sharp.reg131.sw_var_gain2)
+                                     / MPP_MAX((float)(dst_reg->sharp.reg130.sw_var_idx2 - dst_reg->sharp.reg129.sw_var_idx1), 1));
+    global_gain_slp_temp[3]  = ROUND(128 * (float)(dst_reg->sharp.reg131.sw_var_gain4 - dst_reg->sharp.reg131.sw_var_gain3)
+                                     / MPP_MAX((float)(dst_reg->sharp.reg130.sw_var_idx3 - dst_reg->sharp.reg130.sw_var_idx2), 1));
+    global_gain_slp_temp[4]  = ROUND(128 * (float)(p_shp_param->global_gain_var_val[5] - dst_reg->sharp.reg131.sw_var_gain4)
+                                     / MPP_MAX((float)(255 - dst_reg->sharp.reg130.sw_var_idx3), 1));
+    dst_reg->sharp.reg132.sw_var_slp01     = mpp_clip(global_gain_slp_temp[0], -1024, 1023);
+    dst_reg->sharp.reg132.sw_var_slp12     = mpp_clip(global_gain_slp_temp[1], -1024, 1023);
+    dst_reg->sharp.reg133.sw_var_slp23     = mpp_clip(global_gain_slp_temp[2], -1024, 1023);
+    dst_reg->sharp.reg133.sw_var_slp34     = mpp_clip(global_gain_slp_temp[3], -1024, 1023);
+    dst_reg->sharp.reg134.sw_var_slp45     = mpp_clip(global_gain_slp_temp[4], -1024, 1023);
+
+    dst_reg->sharp.reg134.sw_lum_select     = p_shp_param->global_gain_lum_mode;
+    dst_reg->sharp.reg134.sw_lum_idx0     = p_shp_param->global_gain_lum_grd[1] >> 2;
+    dst_reg->sharp.reg135.sw_lum_idx1     = p_shp_param->global_gain_lum_grd[2] >> 2;
+    dst_reg->sharp.reg135.sw_lum_idx2     = p_shp_param->global_gain_lum_grd[3] >> 2;
+    dst_reg->sharp.reg135.sw_lum_idx3     = p_shp_param->global_gain_lum_grd[4] >> 2;
+    dst_reg->sharp.reg136.sw_lum_gain0  = p_shp_param->global_gain_lum_val[0];
+    dst_reg->sharp.reg136.sw_lum_gain1  = p_shp_param->global_gain_lum_val[1];
+    dst_reg->sharp.reg136.sw_lum_gain2  = p_shp_param->global_gain_lum_val[2];
+    dst_reg->sharp.reg136.sw_lum_gain3  = p_shp_param->global_gain_lum_val[3];
+    dst_reg->sharp.reg137.sw_lum_gain4  = p_shp_param->global_gain_lum_val[4];
+    global_gain_slp_temp[0]  = ROUND(128 * (float)(dst_reg->sharp.reg136.sw_lum_gain1 - dst_reg->sharp.reg136.sw_lum_gain0)
+                                     / MPP_MAX((float)(dst_reg->sharp.reg134.sw_lum_idx0 - 0), 1));
+    global_gain_slp_temp[1]  = ROUND(128 * (float)(dst_reg->sharp.reg136.sw_lum_gain2 - dst_reg->sharp.reg136.sw_lum_gain1)
+                                     / MPP_MAX((float)(dst_reg->sharp.reg135.sw_lum_idx1 - dst_reg->sharp.reg134.sw_lum_idx0), 1));
+    global_gain_slp_temp[2]  = ROUND(128 * (float)(dst_reg->sharp.reg136.sw_lum_gain3 - dst_reg->sharp.reg136.sw_lum_gain2)
+                                     / MPP_MAX((float)(dst_reg->sharp.reg135.sw_lum_idx2 - dst_reg->sharp.reg135.sw_lum_idx1), 1));
+    global_gain_slp_temp[3]  = ROUND(128 * (float)(dst_reg->sharp.reg137.sw_lum_gain4 - dst_reg->sharp.reg136.sw_lum_gain3)
+                                     / MPP_MAX((float)(dst_reg->sharp.reg135.sw_lum_idx3 - dst_reg->sharp.reg135.sw_lum_idx2), 1));
+    global_gain_slp_temp[4]  = ROUND(128 * (float)(p_shp_param->global_gain_lum_val[5] - dst_reg->sharp.reg137.sw_lum_gain4)
+                                     / MPP_MAX((float)(255 - dst_reg->sharp.reg135.sw_lum_idx3), 1));
+    dst_reg->sharp.reg137.sw_lum_slp01     = mpp_clip(global_gain_slp_temp[0], -1024, 1023);
+    dst_reg->sharp.reg137.sw_lum_slp12     = mpp_clip(global_gain_slp_temp[1], -1024, 1023);
+    dst_reg->sharp.reg138.sw_lum_slp23     = mpp_clip(global_gain_slp_temp[2], -1024, 1023);
+    dst_reg->sharp.reg138.sw_lum_slp34     = mpp_clip(global_gain_slp_temp[3], -1024, 1023);
+    dst_reg->sharp.reg139.sw_lum_slp45     = mpp_clip(global_gain_slp_temp[4], -1024, 1023);
+
+
+    dst_reg->sharp.reg140.sw_adj_point_x0      = p_shp_param->color_ctrl_p0_point_u;
+    dst_reg->sharp.reg140.sw_adj_point_y0      = p_shp_param->color_ctrl_p0_point_v;
+    dst_reg->sharp.reg140.sw_adj_scaling_coef0 = p_shp_param->color_ctrl_p0_scaling_coef;
+    dst_reg->sharp.reg141.sw_coloradj_tab0_0   = p_shp_param->color_ctrl_p0_roll_tab[0];
+    dst_reg->sharp.reg141.sw_coloradj_tab0_1   = p_shp_param->color_ctrl_p0_roll_tab[1];
+    dst_reg->sharp.reg141.sw_coloradj_tab0_2   = p_shp_param->color_ctrl_p0_roll_tab[2];
+    dst_reg->sharp.reg141.sw_coloradj_tab0_3   = p_shp_param->color_ctrl_p0_roll_tab[3];
+    dst_reg->sharp.reg141.sw_coloradj_tab0_4   = p_shp_param->color_ctrl_p0_roll_tab[4];
+    dst_reg->sharp.reg141.sw_coloradj_tab0_5   = p_shp_param->color_ctrl_p0_roll_tab[5];
+    dst_reg->sharp.reg142.sw_coloradj_tab0_6   = p_shp_param->color_ctrl_p0_roll_tab[6];
+    dst_reg->sharp.reg142.sw_coloradj_tab0_7   = p_shp_param->color_ctrl_p0_roll_tab[7];
+    dst_reg->sharp.reg142.sw_coloradj_tab0_8   = p_shp_param->color_ctrl_p0_roll_tab[8];
+    dst_reg->sharp.reg142.sw_coloradj_tab0_9   = p_shp_param->color_ctrl_p0_roll_tab[9];
+    dst_reg->sharp.reg142.sw_coloradj_tab0_10  = p_shp_param->color_ctrl_p0_roll_tab[10];
+    dst_reg->sharp.reg142.sw_coloradj_tab0_11  = p_shp_param->color_ctrl_p0_roll_tab[11];
+    dst_reg->sharp.reg143.sw_coloradj_tab0_12  = p_shp_param->color_ctrl_p0_roll_tab[12];
+    dst_reg->sharp.reg143.sw_coloradj_tab0_13  = p_shp_param->color_ctrl_p0_roll_tab[13];
+    dst_reg->sharp.reg143.sw_coloradj_tab0_14  = p_shp_param->color_ctrl_p0_roll_tab[14];
+    dst_reg->sharp.reg143.sw_coloradj_tab0_15  = p_shp_param->color_ctrl_p0_roll_tab[15];
+
+    dst_reg->sharp.reg144.sw_adj_point_x1      = p_shp_param->color_ctrl_p1_point_u;
+    dst_reg->sharp.reg144.sw_adj_point_y1      = p_shp_param->color_ctrl_p1_point_v;
+    dst_reg->sharp.reg144.sw_adj_scaling_coef1 = p_shp_param->color_ctrl_p1_scaling_coef;
+    dst_reg->sharp.reg145.sw_coloradj_tab1_0   = p_shp_param->color_ctrl_p1_roll_tab[0];
+    dst_reg->sharp.reg145.sw_coloradj_tab1_1   = p_shp_param->color_ctrl_p1_roll_tab[1];
+    dst_reg->sharp.reg145.sw_coloradj_tab1_2   = p_shp_param->color_ctrl_p1_roll_tab[2];
+    dst_reg->sharp.reg145.sw_coloradj_tab1_3   = p_shp_param->color_ctrl_p1_roll_tab[3];
+    dst_reg->sharp.reg145.sw_coloradj_tab1_4   = p_shp_param->color_ctrl_p1_roll_tab[4];
+    dst_reg->sharp.reg145.sw_coloradj_tab1_5   = p_shp_param->color_ctrl_p1_roll_tab[5];
+    dst_reg->sharp.reg146.sw_coloradj_tab1_6   = p_shp_param->color_ctrl_p1_roll_tab[6];
+    dst_reg->sharp.reg146.sw_coloradj_tab1_7   = p_shp_param->color_ctrl_p1_roll_tab[7];
+    dst_reg->sharp.reg146.sw_coloradj_tab1_8   = p_shp_param->color_ctrl_p1_roll_tab[8];
+    dst_reg->sharp.reg146.sw_coloradj_tab1_9   = p_shp_param->color_ctrl_p1_roll_tab[9];
+    dst_reg->sharp.reg146.sw_coloradj_tab1_10  = p_shp_param->color_ctrl_p1_roll_tab[10];
+    dst_reg->sharp.reg146.sw_coloradj_tab1_11  = p_shp_param->color_ctrl_p1_roll_tab[11];
+    dst_reg->sharp.reg147.sw_coloradj_tab1_12  = p_shp_param->color_ctrl_p1_roll_tab[12];
+    dst_reg->sharp.reg147.sw_coloradj_tab1_13  = p_shp_param->color_ctrl_p1_roll_tab[13];
+    dst_reg->sharp.reg147.sw_coloradj_tab1_14  = p_shp_param->color_ctrl_p1_roll_tab[14];
+    dst_reg->sharp.reg147.sw_coloradj_tab1_15  = p_shp_param->color_ctrl_p1_roll_tab[15];
+
+    dst_reg->sharp.reg148.sw_adj_point_x2       = p_shp_param->color_ctrl_p2_point_u;
+    dst_reg->sharp.reg148.sw_adj_point_y2       = p_shp_param->color_ctrl_p2_point_v;
+    dst_reg->sharp.reg148.sw_adj_scaling_coef2  = p_shp_param->color_ctrl_p2_scaling_coef;
+    dst_reg->sharp.reg149.sw_coloradj_tab2_0    = p_shp_param->color_ctrl_p2_roll_tab[0];
+    dst_reg->sharp.reg149.sw_coloradj_tab2_1    = p_shp_param->color_ctrl_p2_roll_tab[1];
+    dst_reg->sharp.reg149.sw_coloradj_tab2_2    = p_shp_param->color_ctrl_p2_roll_tab[2];
+    dst_reg->sharp.reg149.sw_coloradj_tab2_3    = p_shp_param->color_ctrl_p2_roll_tab[3];
+    dst_reg->sharp.reg149.sw_coloradj_tab2_4    = p_shp_param->color_ctrl_p2_roll_tab[4];
+    dst_reg->sharp.reg149.sw_coloradj_tab2_5    = p_shp_param->color_ctrl_p2_roll_tab[5];
+    dst_reg->sharp.reg150.sw_coloradj_tab2_6   = p_shp_param->color_ctrl_p2_roll_tab[6];
+    dst_reg->sharp.reg150.sw_coloradj_tab2_7   = p_shp_param->color_ctrl_p2_roll_tab[7];
+    dst_reg->sharp.reg150.sw_coloradj_tab2_8   = p_shp_param->color_ctrl_p2_roll_tab[8];
+    dst_reg->sharp.reg150.sw_coloradj_tab2_9   = p_shp_param->color_ctrl_p2_roll_tab[9];
+    dst_reg->sharp.reg150.sw_coloradj_tab2_10  = p_shp_param->color_ctrl_p2_roll_tab[10];
+    dst_reg->sharp.reg150.sw_coloradj_tab2_11  = p_shp_param->color_ctrl_p2_roll_tab[11];
+    dst_reg->sharp.reg151.sw_coloradj_tab2_12  = p_shp_param->color_ctrl_p2_roll_tab[12];
+    dst_reg->sharp.reg151.sw_coloradj_tab2_13  = p_shp_param->color_ctrl_p2_roll_tab[13];
+    dst_reg->sharp.reg151.sw_coloradj_tab2_14  = p_shp_param->color_ctrl_p2_roll_tab[14];
+    dst_reg->sharp.reg151.sw_coloradj_tab2_15  = p_shp_param->color_ctrl_p2_roll_tab[15];
+
+    dst_reg->sharp.reg152.sw_adj_point_x3      = p_shp_param->color_ctrl_p3_point_u;
+    dst_reg->sharp.reg152.sw_adj_point_y3      = p_shp_param->color_ctrl_p3_point_v;
+    dst_reg->sharp.reg152.sw_adj_scaling_coef3 = p_shp_param->color_ctrl_p3_scaling_coef;
+    dst_reg->sharp.reg153.sw_coloradj_tab3_0   = p_shp_param->color_ctrl_p3_roll_tab[0];
+    dst_reg->sharp.reg153.sw_coloradj_tab3_1   = p_shp_param->color_ctrl_p3_roll_tab[1];
+    dst_reg->sharp.reg153.sw_coloradj_tab3_2   = p_shp_param->color_ctrl_p3_roll_tab[2];
+    dst_reg->sharp.reg153.sw_coloradj_tab3_3   = p_shp_param->color_ctrl_p3_roll_tab[3];
+    dst_reg->sharp.reg153.sw_coloradj_tab3_4   = p_shp_param->color_ctrl_p3_roll_tab[4];
+    dst_reg->sharp.reg153.sw_coloradj_tab3_5   = p_shp_param->color_ctrl_p3_roll_tab[5];
+    dst_reg->sharp.reg154.sw_coloradj_tab3_6   = p_shp_param->color_ctrl_p3_roll_tab[6];
+    dst_reg->sharp.reg154.sw_coloradj_tab3_7   = p_shp_param->color_ctrl_p3_roll_tab[7];
+    dst_reg->sharp.reg154.sw_coloradj_tab3_8   = p_shp_param->color_ctrl_p3_roll_tab[8];
+    dst_reg->sharp.reg154.sw_coloradj_tab3_9   = p_shp_param->color_ctrl_p3_roll_tab[9];
+    dst_reg->sharp.reg154.sw_coloradj_tab3_10  = p_shp_param->color_ctrl_p3_roll_tab[10];
+    dst_reg->sharp.reg154.sw_coloradj_tab3_11  = p_shp_param->color_ctrl_p3_roll_tab[11];
+    dst_reg->sharp.reg155.sw_coloradj_tab3_12  = p_shp_param->color_ctrl_p3_roll_tab[12];
+    dst_reg->sharp.reg155.sw_coloradj_tab3_13  = p_shp_param->color_ctrl_p3_roll_tab[13];
+    dst_reg->sharp.reg155.sw_coloradj_tab3_14  = p_shp_param->color_ctrl_p3_roll_tab[14];
+    dst_reg->sharp.reg155.sw_coloradj_tab3_15  = p_shp_param->color_ctrl_p3_roll_tab[15];
+
+
+    dst_reg->sharp.reg156.sw_idxmode_select = p_shp_param->tex_adj_mode_select;
+    dst_reg->sharp.reg156.sw_ymode_select   = p_shp_param->tex_adj_y_mode_select;
+    dst_reg->sharp.reg156.sw_tex_idx0        = p_shp_param->tex_adj_grd[1] >> 2;
+    dst_reg->sharp.reg156.sw_tex_idx1       = p_shp_param->tex_adj_grd[2] >> 2;
+    dst_reg->sharp.reg157.sw_tex_idx2       = p_shp_param->tex_adj_grd[3] >> 2;
+    dst_reg->sharp.reg157.sw_tex_idx3       = p_shp_param->tex_adj_grd[4] >> 2;
+    dst_reg->sharp.reg157.sw_tex_gain0      = p_shp_param->tex_adj_val[0];
+    dst_reg->sharp.reg158.sw_tex_gain1      = p_shp_param->tex_adj_val[1];
+    dst_reg->sharp.reg158.sw_tex_gain2      = p_shp_param->tex_adj_val[2];
+    dst_reg->sharp.reg158.sw_tex_gain3      = p_shp_param->tex_adj_val[3];
+    dst_reg->sharp.reg158.sw_tex_gain4      = p_shp_param->tex_adj_val[4];
+    global_gain_slp_temp[0]      = ROUND(128 * (float)(dst_reg->sharp.reg158.sw_tex_gain1 - dst_reg->sharp.reg157.sw_tex_gain0)
+                                         / MPP_MAX((float)(dst_reg->sharp.reg156.sw_tex_idx0 - 0), 1));
+    global_gain_slp_temp[1]      = ROUND(128 * (float)(dst_reg->sharp.reg158.sw_tex_gain2 - dst_reg->sharp.reg158.sw_tex_gain1)
+                                         / MPP_MAX((float)(dst_reg->sharp.reg156.sw_tex_idx1 - dst_reg->sharp.reg156.sw_tex_idx0), 1));
+    global_gain_slp_temp[2]      = ROUND(128 * (float)(dst_reg->sharp.reg158.sw_tex_gain3 - dst_reg->sharp.reg158.sw_tex_gain2)
+                                         / MPP_MAX((float)(dst_reg->sharp.reg157.sw_tex_idx2 - dst_reg->sharp.reg156.sw_tex_idx1), 1));
+    global_gain_slp_temp[3]      = ROUND(128 * (float)(dst_reg->sharp.reg158.sw_tex_gain4 - dst_reg->sharp.reg158.sw_tex_gain3)
+                                         / MPP_MAX((float)(dst_reg->sharp.reg157.sw_tex_idx3 - dst_reg->sharp.reg157.sw_tex_idx2), 1));
+    global_gain_slp_temp[4]      = ROUND(128 * (float)(p_shp_param->tex_adj_val[5] - dst_reg->sharp.reg158.sw_tex_gain4)
+                                         / MPP_MAX((float)(255 - dst_reg->sharp.reg157.sw_tex_idx3), 1));
+    dst_reg->sharp.reg159.sw_tex_slp01      = mpp_clip(global_gain_slp_temp[0], -1024, 1023);
+    dst_reg->sharp.reg159.sw_tex_slp12      = mpp_clip(global_gain_slp_temp[1], -1024, 1023);
+    dst_reg->sharp.reg160.sw_tex_slp23      = mpp_clip(global_gain_slp_temp[2], -1024, 1023);
+    dst_reg->sharp.reg160.sw_tex_slp34      = mpp_clip(global_gain_slp_temp[3], -1024, 1023);
+    dst_reg->sharp.reg161.sw_tex_slp45      = mpp_clip(global_gain_slp_temp[4], -1024, 1023);
+
+}
+
+static MPP_RET vdpp2_params_to_reg(struct vdpp2_params* src_params, struct vdpp2_api_ctx *ctx)
+{
+    struct vdpp2_reg *dst_reg = &ctx->reg;
+    struct zme_params *zme_params = &src_params->zme_params;
+
+    memset(dst_reg, 0, sizeof(*dst_reg));
+
+    dst_reg->common.reg0.sw_vdpp_frm_en = 1;
+
+    /* 0x0004(reg1), TODO: add debug function */
+    dst_reg->common.reg1.sw_vdpp_src_fmt = VDPP_FMT_YUV420;
+    dst_reg->common.reg1.sw_vdpp_src_yuv_swap = src_params->src_yuv_swap;
+
+    if (MPP_FMT_YUV420SP_VU == src_params->src_fmt)
+        dst_reg->common.reg1.sw_vdpp_src_yuv_swap = 1;
+
+    dst_reg->common.reg1.sw_vdpp_dst_fmt = src_params->dst_fmt;
+    dst_reg->common.reg1.sw_vdpp_dst_yuv_swap = src_params->dst_yuv_swap;
+    dst_reg->common.reg1.sw_vdpp_dbmsr_en = (src_params->working_mode == VDPP_WORK_MODE_DCI)
+                                            ? 0
+                                            : src_params->dmsr_params.dmsr_enable;
+
+    /* 0x0008(reg2) */
+    dst_reg->common.reg2.sw_vdpp_working_mode = src_params->working_mode;
+    VDPP2_DBG(VDPP2_DBG_TRACE, "working_mode %d", src_params->working_mode);
+
+    /* 0x000C ~ 0x001C(reg3 ~ reg7), skip */
+    dst_reg->common.reg4.sw_vdpp_clk_on = 1;
+    dst_reg->common.reg4.sw_md_clk_on = 1;
+    dst_reg->common.reg4.sw_dect_clk_on = 1;
+    dst_reg->common.reg4.sw_me_clk_on = 1;
+    dst_reg->common.reg4.sw_mc_clk_on = 1;
+    dst_reg->common.reg4.sw_eedi_clk_on = 1;
+    dst_reg->common.reg4.sw_ble_clk_on = 1;
+    dst_reg->common.reg4.sw_out_clk_on = 1;
+    dst_reg->common.reg4.sw_ctrl_clk_on = 1;
+    dst_reg->common.reg4.sw_ram_clk_on = 1;
+    dst_reg->common.reg4.sw_dma_clk_on = 1;
+    dst_reg->common.reg4.sw_reg_clk_on = 1;
+
+    /* 0x0020(reg8) */
+    dst_reg->common.reg8.sw_vdpp_frm_done_en = 1;
+    dst_reg->common.reg8.sw_vdpp_osd_max_en = 1;
+    dst_reg->common.reg8.sw_vdpp_bus_error_en = 1;
+    dst_reg->common.reg8.sw_vdpp_timeout_int_en = 1;
+    dst_reg->common.reg8.sw_vdpp_config_error_en = 1;
+    /* 0x0024 ~ 0x002C(reg9 ~ reg11), skip */
+    {
+        RK_U32 src_right_redundant = src_params->src_width % 16 == 0 ? 0 : 16 - src_params->src_width % 16;
+        RK_U32 src_down_redundant  = src_params->src_height % 8 == 0 ? 0 : 8 - src_params->src_height % 8;
+        RK_U32 dst_right_redundant = src_params->dst_width % 16 == 0 ? 0 : 16 - src_params->dst_width % 16;
+        /* 0x0030(reg12) */
+        dst_reg->common.reg12.sw_vdpp_src_vir_y_stride = src_params->src_width_vir / 4;
+
+        /* 0x0034(reg13) */
+        dst_reg->common.reg13.sw_vdpp_dst_vir_y_stride = src_params->dst_width_vir / 4;
+
+        /* 0x0038(reg14) */
+        dst_reg->common.reg14.sw_vdpp_src_pic_width = src_params->src_width + src_right_redundant - 1;
+        dst_reg->common.reg14.sw_vdpp_src_right_redundant = src_right_redundant;
+        dst_reg->common.reg14.sw_vdpp_src_pic_height = src_params->src_height + src_down_redundant - 1;
+        dst_reg->common.reg14.sw_vdpp_src_down_redundant = src_down_redundant;
+
+        /* 0x003C(reg15) */
+        dst_reg->common.reg15.sw_vdpp_dst_pic_width = src_params->dst_width + dst_right_redundant - 1;
+        dst_reg->common.reg15.sw_vdpp_dst_right_redundant = dst_right_redundant;
+        dst_reg->common.reg15.sw_vdpp_dst_pic_height = src_params->dst_height - 1;
+    }
+    /* 0x0040 ~ 0x005C(reg16 ~ reg23), skip */
+    dst_reg->common.reg20.sw_vdpp_timeout_en = 1;
+    dst_reg->common.reg20.sw_vdpp_timeout_cnt = 0x8FFFFFF;
+
+    /* 0x0060(reg24) */
+    dst_reg->common.reg24.sw_vdpp_src_addr_y = src_params->src.y;
+
+    /* 0x0064(reg25) */
+    dst_reg->common.reg25.sw_vdpp_src_addr_uv = src_params->src.cbcr;
+
+    /* 0x0068(reg26) */
+    dst_reg->common.reg26.sw_vdpp_dst_addr_y = src_params->dst.y;
+
+    /* 0x006C(reg27) */
+    dst_reg->common.reg27.sw_vdpp_dst_addr_uv = src_params->dst.cbcr;
+
+    if (src_params->yuv_out_diff) {
+        RK_U32 dst_right_redundant_c = src_params->dst_c_width % 16 == 0 ? 0 : 16 - src_params->dst_c_width % 16;
+
+        dst_reg->common.reg1.sw_vdpp_yuvout_diff_en = src_params->yuv_out_diff;
+        dst_reg->common.reg13.sw_vdpp_dst_vir_c_stride = src_params->dst_c_width_vir / 4;
+        /* 0x0040(reg16) */
+        dst_reg->common.reg16.sw_vdpp_dst_pic_width_c = src_params->dst_c_width + dst_right_redundant_c - 1;
+        dst_reg->common.reg16.sw_vdpp_dst_right_redundant_c = dst_right_redundant_c;
+        dst_reg->common.reg16.sw_vdpp_dst_pic_height_c = src_params->dst_c_height - 1;
+
+        dst_reg->common.reg27.sw_vdpp_dst_addr_uv = src_params->dst_c.cbcr;
+    }
+
+    set_dmsr_to_vdpp_reg(&src_params->dmsr_params, &ctx->dmsr);
+    set_hist_to_vdpp2_reg(src_params, dst_reg);
+    set_es_to_vdpp2_reg(src_params, dst_reg);
+    set_shp_to_vdpp2_reg(src_params, dst_reg);
+
+    zme_params->src_width = src_params->src_width;
+    zme_params->src_height = src_params->src_height;
+    zme_params->dst_width = src_params->dst_width;
+    zme_params->dst_height = src_params->dst_height;
+    zme_params->dst_fmt = src_params->dst_fmt;
+    zme_params->yuv_out_diff = src_params->yuv_out_diff;
+    zme_params->dst_c_width = src_params->dst_c_width;
+    zme_params->dst_c_height = src_params->dst_c_height;
+    set_zme_to_vdpp_reg(zme_params, &ctx->zme);
+
+    return MPP_OK;
+}
+
+static void vdpp2_set_default_dmsr_param(struct dmsr_params* p_dmsr_param)
+{
+    p_dmsr_param->dmsr_enable = 1;
+    p_dmsr_param->dmsr_str_pri_y = 10;
+    p_dmsr_param->dmsr_str_sec_y = 4;
+    p_dmsr_param->dmsr_dumping_y = 6;
+    p_dmsr_param->dmsr_wgt_pri_gain_even_1 = 12;
+    p_dmsr_param->dmsr_wgt_pri_gain_even_2 = 12;
+    p_dmsr_param->dmsr_wgt_pri_gain_odd_1 = 8;
+    p_dmsr_param->dmsr_wgt_pri_gain_odd_2 = 16;
+    p_dmsr_param->dmsr_wgt_sec_gain = 5;
+    p_dmsr_param->dmsr_blk_flat_th = 20;
+    p_dmsr_param->dmsr_contrast_to_conf_map_x0 = 1680;
+    p_dmsr_param->dmsr_contrast_to_conf_map_x1 = 6720;
+    p_dmsr_param->dmsr_contrast_to_conf_map_y0 = 0;
+    p_dmsr_param->dmsr_contrast_to_conf_map_y1 = 65535;
+    p_dmsr_param->dmsr_diff_core_th0 = 1;
+    p_dmsr_param->dmsr_diff_core_th1 = 5;
+    p_dmsr_param->dmsr_diff_core_wgt0 = 16;
+    p_dmsr_param->dmsr_diff_core_wgt1 = 16;
+    p_dmsr_param->dmsr_diff_core_wgt2 = 16;
+    p_dmsr_param->dmsr_edge_th_low_arr[0] = 30;
+    p_dmsr_param->dmsr_edge_th_low_arr[1] = 10;
+    p_dmsr_param->dmsr_edge_th_low_arr[2] = 0;
+    p_dmsr_param->dmsr_edge_th_low_arr[3] = 0;
+    p_dmsr_param->dmsr_edge_th_low_arr[4] = 0;
+    p_dmsr_param->dmsr_edge_th_low_arr[5] = 0;
+    p_dmsr_param->dmsr_edge_th_low_arr[6] = 0;
+    p_dmsr_param->dmsr_edge_th_high_arr[0] = 60;
+    p_dmsr_param->dmsr_edge_th_high_arr[1] = 40;
+    p_dmsr_param->dmsr_edge_th_high_arr[2] = 20;
+    p_dmsr_param->dmsr_edge_th_high_arr[3] = 10;
+    p_dmsr_param->dmsr_edge_th_high_arr[4] = 10;
+    p_dmsr_param->dmsr_edge_th_high_arr[5] = 10;
+    p_dmsr_param->dmsr_edge_th_high_arr[6] = 10;
+}
+
+static void vdpp_set_default_es_param(EsParams* p_es_param)
+{
+    p_es_param->es_bEnabledES          = 0;
+    p_es_param->es_iAngleDelta         = 17;
+    p_es_param->es_iAngleDeltaExtra    = 5;
+    p_es_param->es_iGradNoDirTh        = 37;
+    p_es_param->es_iGradFlatTh         = 75;
+    p_es_param->es_iWgtGain            = 128;
+    p_es_param->es_iWgtDecay           = 128;
+    p_es_param->es_iLowConfTh          = 96;
+    p_es_param->es_iLowConfRatio       = 32;
+    p_es_param->es_iConfCntTh          = 4;
+    p_es_param->es_iWgtLocalTh         = 64;
+    p_es_param->es_iK1                 = 4096;
+    p_es_param->es_iK2                 = 7168;
+    p_es_param->es_iDeltaLimit         = 65280;
+    memcpy(&p_es_param->es_iDiff2conf_lut_x[0], &diff2conf_lut_x_tmp[0], sizeof(diff2conf_lut_x_tmp));
+    memcpy(&p_es_param->es_iDiff2conf_lut_y[0], &diff2conf_lut_y_tmp[0], sizeof(diff2conf_lut_y_tmp));
+    p_es_param->es_bEndpointCheckEnable = 1;
+}
+
+static void vdpp_set_default_shp_param(ShpParams* p_shp_param)
+{
+
+    p_shp_param->sharp_enable               = 1;
+    p_shp_param->sharp_coloradj_bypass_en   = 1;
+
+    p_shp_param->lti_h_enable           = 0;
+    p_shp_param->lti_h_radius           = 1;
+    p_shp_param->lti_h_slope            = 100;
+    p_shp_param->lti_h_thresold         = 21;
+    p_shp_param->lti_h_gain             = 8;
+    p_shp_param->lti_h_noise_thr_pos    = 1023;
+    p_shp_param->lti_h_noise_thr_neg    = 1023;
+
+    p_shp_param->lti_v_enable           = 0;
+    p_shp_param->lti_v_radius           = 1;
+    p_shp_param->lti_v_slope            = 100;
+    p_shp_param->lti_v_thresold         = 21;
+    p_shp_param->lti_v_gain             = 8;
+    p_shp_param->lti_v_noise_thr_pos    = 1023;
+    p_shp_param->lti_v_noise_thr_neg    = 1023;
+
+    p_shp_param->cti_h_enable           = 0;
+    p_shp_param->cti_h_radius           = 1;
+    p_shp_param->cti_h_slope            = 100;
+    p_shp_param->cti_h_thresold         = 21;
+    p_shp_param->cti_h_gain             = 8;
+    p_shp_param->cti_h_noise_thr_pos    = 1023;
+    p_shp_param->cti_h_noise_thr_neg    = 1023;
+
+    p_shp_param->peaking_enable         = 1;
+    p_shp_param->peaking_gain           = 196;
+
+    p_shp_param->peaking_coring_enable      = 1;
+    p_shp_param->peaking_limit_ctrl_enable  = 1;
+    p_shp_param->peaking_gain_enable        = 1;
+
+    memcpy(p_shp_param->peaking_coring_zero,    coring_zero_tmp,    sizeof(coring_zero_tmp));
+    memcpy(p_shp_param->peaking_coring_thr,     coring_thr_tmp,     sizeof(coring_thr_tmp));
+    memcpy(p_shp_param->peaking_coring_ratio,   coring_ratio_tmp,   sizeof(coring_ratio_tmp));
+    memcpy(p_shp_param->peaking_gain_pos,   gain_pos_tmp,   sizeof(gain_pos_tmp));
+    memcpy(p_shp_param->peaking_gain_neg,   gain_neg_tmp,   sizeof(gain_neg_tmp));
+    memcpy(p_shp_param->peaking_limit_ctrl_pos0,    limit_ctrl_pos0_tmp,    sizeof(limit_ctrl_pos0_tmp));
+    memcpy(p_shp_param->peaking_limit_ctrl_pos1,    limit_ctrl_pos1_tmp,    sizeof(limit_ctrl_pos1_tmp));
+    memcpy(p_shp_param->peaking_limit_ctrl_neg0,    limit_ctrl_neg0_tmp,    sizeof(limit_ctrl_neg0_tmp));
+    memcpy(p_shp_param->peaking_limit_ctrl_neg1,    limit_ctrl_neg1_tmp,    sizeof(limit_ctrl_neg1_tmp));
+    memcpy(p_shp_param->peaking_limit_ctrl_ratio,   limit_ctrl_ratio_tmp,   sizeof(limit_ctrl_ratio_tmp));
+    memcpy(p_shp_param->peaking_limit_ctrl_bnd_pos, limit_ctrl_bnd_pos_tmp, sizeof(limit_ctrl_bnd_pos_tmp));
+    memcpy(p_shp_param->peaking_limit_ctrl_bnd_neg, limit_ctrl_bnd_neg_tmp, sizeof(limit_ctrl_bnd_neg_tmp));
+
+    p_shp_param->peaking_edge_ctrl_enable               = 1;
+    p_shp_param->peaking_edge_ctrl_non_dir_thr          = 16;
+    p_shp_param->peaking_edge_ctrl_dir_cmp_ratio        = 4;
+    p_shp_param->peaking_edge_ctrl_non_dir_wgt_offset   = 64;
+    p_shp_param->peaking_edge_ctrl_non_dir_wgt_ratio    = 16;
+    p_shp_param->peaking_edge_ctrl_dir_cnt_thr          = 2;
+    p_shp_param->peaking_edge_ctrl_dir_cnt_avg          = 3;
+    p_shp_param->peaking_edge_ctrl_dir_cnt_offset       = 2;
+    p_shp_param->peaking_edge_ctrl_diag_dir_thr         = 16;
+
+    memcpy(p_shp_param->peaking_edge_ctrl_diag_adj_gain_tab, diag_adj_gain_tab_tmp, sizeof(diag_adj_gain_tab_tmp));
+
+    p_shp_param->peaking_estc_enable                    = 1;
+    p_shp_param->peaking_estc_delta_offset_h            = 4;
+    p_shp_param->peaking_estc_alpha_over_h              = 8;
+    p_shp_param->peaking_estc_alpha_under_h             = 16;
+    p_shp_param->peaking_estc_alpha_over_unlimit_h      = 64;
+    p_shp_param->peaking_estc_alpha_under_unlimit_h     = 112;
+    p_shp_param->peaking_estc_delta_offset_v            = 4;
+    p_shp_param->peaking_estc_alpha_over_v              = 8;
+    p_shp_param->peaking_estc_alpha_under_v             = 16;
+    p_shp_param->peaking_estc_alpha_over_unlimit_v      = 64;
+    p_shp_param->peaking_estc_alpha_under_unlimit_v     = 112;
+    p_shp_param->peaking_estc_delta_offset_d0           = 4;
+    p_shp_param->peaking_estc_alpha_over_d0             = 16;
+    p_shp_param->peaking_estc_alpha_under_d0            = 16;
+    p_shp_param->peaking_estc_alpha_over_unlimit_d0     = 96;
+    p_shp_param->peaking_estc_alpha_under_unlimit_d0    = 96;
+    p_shp_param->peaking_estc_delta_offset_d1           = 4;
+    p_shp_param->peaking_estc_alpha_over_d1             = 16;
+    p_shp_param->peaking_estc_alpha_under_d1            = 16;
+    p_shp_param->peaking_estc_alpha_over_unlimit_d1     = 96;
+    p_shp_param->peaking_estc_alpha_under_unlimit_d1    = 96;
+    p_shp_param->peaking_estc_delta_offset_non          = 4;
+    p_shp_param->peaking_estc_alpha_over_non            = 8;
+    p_shp_param->peaking_estc_alpha_under_non           = 8;
+    p_shp_param->peaking_estc_alpha_over_unlimit_non    = 112;
+    p_shp_param->peaking_estc_alpha_under_unlimit_non   = 112;
+    p_shp_param->peaking_filter_cfg_diag_enh_coef       = 6;
+
+    p_shp_param->peaking_filt_core_H0[0]                = 4;
+    p_shp_param->peaking_filt_core_H0[1]                = 16;
+    p_shp_param->peaking_filt_core_H0[2]                = 24;
+    p_shp_param->peaking_filt_core_H1[0]                = -16;
+    p_shp_param->peaking_filt_core_H1[1]                = 0;
+    p_shp_param->peaking_filt_core_H1[2]                = 32;
+    p_shp_param->peaking_filt_core_H2[0]                = 0;
+    p_shp_param->peaking_filt_core_H2[1]                = -16;
+    p_shp_param->peaking_filt_core_H2[2]                = 32;
+    p_shp_param->peaking_filt_core_V0[0]                = 1;
+    p_shp_param->peaking_filt_core_V0[1]                = 4;
+    p_shp_param->peaking_filt_core_V0[2]                = 6;
+    p_shp_param->peaking_filt_core_V1[0]                = -4;
+    p_shp_param->peaking_filt_core_V1[1]                = 0;
+    p_shp_param->peaking_filt_core_V1[2]                = 8;
+    p_shp_param->peaking_filt_core_V2[0]                = 0;
+    p_shp_param->peaking_filt_core_V2[1]                = -4;
+    p_shp_param->peaking_filt_core_V2[2]                = 8;
+    p_shp_param->peaking_filt_core_USM[0]               = 1;
+    p_shp_param->peaking_filt_core_USM[1]               = 4;
+    p_shp_param->peaking_filt_core_USM[2]               = 6;
+
+    p_shp_param->shootctrl_enable               = 1;
+    p_shp_param->shootctrl_filter_radius        = 1;
+    p_shp_param->shootctrl_delta_offset         = 16;
+    p_shp_param->shootctrl_alpha_over           = 8;
+    p_shp_param->shootctrl_alpha_under          = 8;
+    p_shp_param->shootctrl_alpha_over_unlimit   = 112;
+    p_shp_param->shootctrl_alpha_under_unlimit  = 112;
+
+    p_shp_param->global_gain_enable             = 0;
+    p_shp_param->global_gain_lum_mode           = 0;
+
+    memcpy(p_shp_param->global_gain_lum_grd, lum_grd_tmp, sizeof(lum_grd_tmp));
+    memcpy(p_shp_param->global_gain_lum_val, lum_val_tmp, sizeof(lum_val_tmp));
+    memcpy(p_shp_param->global_gain_adp_grd, adp_grd_tmp, sizeof(adp_grd_tmp));
+    memcpy(p_shp_param->global_gain_adp_val, adp_val_tmp, sizeof(adp_val_tmp));
+    memcpy(p_shp_param->global_gain_var_grd, var_grd_tmp, sizeof(var_grd_tmp));
+    memcpy(p_shp_param->global_gain_var_val, var_val_tmp, sizeof(var_val_tmp));
+
+    p_shp_param->color_ctrl_enable              = 0;
+
+    p_shp_param->color_ctrl_p0_scaling_coef     = 1;
+    p_shp_param->color_ctrl_p0_point_u          = 115;
+    p_shp_param->color_ctrl_p0_point_v          = 155;
+    memcpy(p_shp_param->color_ctrl_p0_roll_tab, roll_tab_pattern0, sizeof(roll_tab_pattern0));
+    p_shp_param->color_ctrl_p1_scaling_coef     = 1;
+    p_shp_param->color_ctrl_p1_point_u          = 90;
+    p_shp_param->color_ctrl_p1_point_v          = 120;
+    memcpy(p_shp_param->color_ctrl_p1_roll_tab, roll_tab_pattern1, sizeof(roll_tab_pattern1));
+    p_shp_param->color_ctrl_p2_scaling_coef     = 1;
+    p_shp_param->color_ctrl_p2_point_u          = 128;
+    p_shp_param->color_ctrl_p2_point_v          = 128;
+    memcpy(p_shp_param->color_ctrl_p2_roll_tab, roll_tab_pattern2, sizeof(roll_tab_pattern2));
+    p_shp_param->color_ctrl_p3_scaling_coef     = 1;
+    p_shp_param->color_ctrl_p3_point_u          = 128;
+    p_shp_param->color_ctrl_p3_point_v          = 128;
+    memcpy(p_shp_param->color_ctrl_p3_roll_tab, roll_tab_pattern2, sizeof(roll_tab_pattern2));
+
+    p_shp_param->tex_adj_enable                 = 0;
+    p_shp_param->tex_adj_y_mode_select          = 3;
+    p_shp_param->tex_adj_mode_select            = 0;
+
+    memcpy(p_shp_param->tex_adj_grd, tex_grd_tmp, sizeof(tex_grd_tmp));
+    memcpy(p_shp_param->tex_adj_val, tex_val_tmp, sizeof(tex_val_tmp));
+}
+
+static MPP_RET vdpp2_set_default_param(struct vdpp2_params *param)
+{
+    param->src_fmt = VDPP_FMT_YUV420;
+    param->src_yuv_swap = VDPP_YUV_SWAP_SP_UV;
+    param->dst_fmt = VDPP_FMT_YUV444;
+    param->dst_yuv_swap = VDPP_YUV_SWAP_SP_UV;
+    param->src_width = 1920;
+    param->src_height = 1080;
+    param->dst_width = 1920;
+    param->dst_height = 1080;
+    param->yuv_out_diff = 0;
+    param->working_mode = VDPP_WORK_MODE_VEP;
+
+    vdpp2_set_default_dmsr_param(&param->dmsr_params);
+    vdpp_set_default_es_param(&param->es_params);
+    vdpp_set_default_shp_param(&param->shp_params);
+
+    param->hist_cnt_en   = 1;
+    param->dci_hsd_mode  = VDPP_DCI_HSD_DISABLE;
+    param->dci_vsd_mode  = VDPP_DCI_VSD_DISABLE;
+    param->dci_yrgb_gather_num  = 0;
+    param->dci_yrgb_gather_en  = 0;
+    param->dci_csc_range = VDPP_COLOR_SPACE_LIMIT_RANGE;
+    update_dci_ctl(param);
+
+    vdpp_set_default_zme_param(&param->zme_params);
+
+    return MPP_OK;
+}
+
+MPP_RET vdpp2_init(VdppCtx *ictx)
+{
+    MPP_RET ret;
+    MppReqV1 mpp_req;
+    RK_U32 client_data = VDPP_CLIENT_TYPE;
+    struct vdpp2_api_ctx *ctx = NULL;
+
+    if (NULL == *ictx) {
+        mpp_err_f("found NULL input vdpp2 ctx %p\n", *ictx);
+        return MPP_ERR_NULL_PTR;
+    }
+
+    ctx = *ictx;
+
+    mpp_env_get_u32("vdpp2_debug", &vdpp2_debug, 0);
+
+    ctx->fd = open("/dev/mpp_service", O_RDWR | O_CLOEXEC);
+    if (ctx->fd < 0) {
+        mpp_err("can NOT find device /dev/vdpp\n");
+        return MPP_NOK;
+    }
+
+    mpp_req.cmd = MPP_CMD_INIT_CLIENT_TYPE;
+    mpp_req.flag = 0;
+    mpp_req.size = sizeof(client_data);
+    mpp_req.data_ptr = REQ_DATA_PTR(&client_data);
+
+    memset(&ctx->params, 0, sizeof(struct vdpp2_params));
+    /* set default parameters */
+    vdpp2_set_default_param(&ctx->params);
+
+    ret = (RK_S32)ioctl(ctx->fd, MPP_IOC_CFG_V1, &mpp_req);
+    if (ret) {
+        mpp_err("ioctl set_client failed\n");
+        return MPP_NOK;
+    }
+
+    return MPP_OK;
+}
+
+MPP_RET vdpp2_deinit(VdppCtx ictx)
+{
+    struct vdpp2_api_ctx *ctx = NULL;
+
+    if (NULL == ictx) {
+        mpp_err_f("found NULL input vdpp ctx %p\n", ictx);
+        return MPP_ERR_NULL_PTR;
+    }
+
+    ctx = ictx;
+
+    if (ctx->fd >= 0) {
+        close(ctx->fd);
+        ctx->fd = -1;
+    }
+
+    return MPP_OK;
+}
+
+static MPP_RET vdpp2_set_param(struct vdpp2_api_ctx *ctx,
+                               union vdpp_api_content *param,
+                               enum VDPP_PARAM_TYPE type)
+{
+    RK_U16 mask;
+    RK_U16 cfg_set;
+
+    switch (type) {
+    case VDPP_PARAM_TYPE_COM: // deprecated config
+        ctx->params.hist_cnt_en = 0; // default disable
+
+        ctx->params.src_fmt = VDPP_FMT_YUV420; // default 420
+        ctx->params.src_yuv_swap = param->com.sswap;
+        ctx->params.dst_fmt = param->com.dfmt;
+        ctx->params.dst_yuv_swap = param->com.dswap;
+        ctx->params.src_width = param->com.src_width;
+        ctx->params.src_height = param->com.src_height;
+        ctx->params.dst_width = param->com.dst_width;
+        ctx->params.dst_height = param->com.dst_height;
+
+        ctx->params.dmsr_params.dmsr_enable = 1;
+        ctx->params.es_params.es_bEnabledES = 1;
+        ctx->params.shp_params.sharp_enable = 1;
+        /* set default vir stride */
+        if (!ctx->params.src_width_vir)
+            ctx->params.src_width_vir = MPP_ALIGN(ctx->params.src_width, 16);
+        if (!ctx->params.src_height_vir)
+            ctx->params.src_height_vir = MPP_ALIGN(ctx->params.src_height, 8);
+        if (!ctx->params.dst_width)
+            ctx->params.dst_width = ctx->params.src_width;
+        if (!ctx->params.dst_height)
+            ctx->params.dst_height = ctx->params.src_height;
+        if (!ctx->params.dst_width_vir)
+            ctx->params.dst_width_vir = MPP_ALIGN(ctx->params.dst_width, 16);
+        if (!ctx->params.dst_height_vir)
+            ctx->params.dst_height_vir = MPP_ALIGN(ctx->params.dst_height, 2);
+        /* set default chrome stride */
+        if (!ctx->params.dst_c_width)
+            ctx->params.dst_c_width = ctx->params.dst_width;
+        if (!ctx->params.dst_c_width_vir)
+            ctx->params.dst_c_width_vir = MPP_ALIGN(ctx->params.dst_c_width, 16);
+        if (!ctx->params.dst_c_height)
+            ctx->params.dst_c_height = ctx->params.dst_height;
+        if (!ctx->params.dst_c_height_vir)
+            ctx->params.dst_c_height_vir = MPP_ALIGN(ctx->params.dst_c_height, 2);
+        update_dci_ctl(&ctx->params);
+        break;
+    case VDPP_PARAM_TYPE_DMSR:
+        memcpy(&ctx->params.dmsr_params, &param->dmsr, sizeof(struct dmsr_params));
+        break;
+    case VDPP_PARAM_TYPE_ZME_COM:
+        ctx->params.zme_params.zme_bypass_en = param->zme.bypass_enable;
+        ctx->params.zme_params.zme_dering_enable = param->zme.dering_enable;
+        ctx->params.zme_params.zme_dering_sen_0 = param->zme.dering_sen_0;
+        ctx->params.zme_params.zme_dering_sen_1 = param->zme.dering_sen_1;
+        ctx->params.zme_params.zme_dering_blend_alpha = param->zme.dering_blend_alpha;
+        ctx->params.zme_params.zme_dering_blend_beta = param->zme.dering_blend_beta;
+        break;
+    case VDPP_PARAM_TYPE_ZME_COEFF:
+        if (param->zme.tap8_coeff != NULL)
+            ctx->params.zme_params.zme_tap8_coeff = param->zme.tap8_coeff;
+        if (param->zme.tap6_coeff != NULL)
+            ctx->params.zme_params.zme_tap6_coeff = param->zme.tap6_coeff;
+        break;
+    case VDPP_PARAM_TYPE_COM2:
+        mask = (param->com2.cfg_set >> 16) & 0x7;
+        cfg_set = (param->com2.cfg_set >> 0) & mask;
+
+        ctx->params.src_yuv_swap = param->com2.sswap;
+        ctx->params.src_fmt = param->com2.sfmt;
+        ctx->params.dst_fmt = param->com2.dfmt;
+        ctx->params.dst_yuv_swap = param->com2.dswap;
+        ctx->params.src_width = param->com2.src_width;
+        ctx->params.src_height = param->com2.src_height;
+        ctx->params.src_width_vir = param->com2.src_width_vir;
+        ctx->params.src_height_vir = param->com2.src_height_vir;
+        ctx->params.dst_width = param->com2.dst_width;
+        ctx->params.dst_height = param->com2.dst_height;
+        ctx->params.dst_width_vir = param->com2.dst_width_vir;
+        ctx->params.dst_height_vir = param->com2.dst_height_vir;
+        ctx->params.yuv_out_diff = param->com2.yuv_out_diff;
+        ctx->params.dst_c_width = param->com2.dst_c_width;
+        ctx->params.dst_c_height = param->com2.dst_c_height;
+        ctx->params.dst_c_width_vir = param->com2.dst_c_width_vir;
+        ctx->params.dst_c_height_vir = param->com2.dst_c_height_vir;
+        ctx->params.working_mode = param->com2.hist_mode_en ?
+                                   VDPP_WORK_MODE_DCI : VDPP_WORK_MODE_VEP;
+        if (mask & VDPP_DMSR_EN)
+            ctx->params.dmsr_params.dmsr_enable = (cfg_set & VDPP_DMSR_EN) ? 1 : 0;
+        if (mask & VDPP_ES_EN)
+            ctx->params.es_params.es_bEnabledES = (cfg_set & VDPP_ES_EN) ? 1 : 0;
+        if (mask & VDPP_SHARP_EN)
+            ctx->params.shp_params.sharp_enable = (cfg_set & VDPP_SHARP_EN) ? 1 : 0;
+        update_dci_ctl(&ctx->params);
+        break;
+    case VDPP_PARAM_TYPE_ES:
+        memcpy(&ctx->params.es_params, &param->es, sizeof(EsParams));
+        update_es_tan(&ctx->params.es_params);
+        break;
+    case VDPP_PARAM_TYPE_HIST:
+        ctx->params.hist_cnt_en = param->hist.hist_cnt_en;
+        ctx->params.dci_hsd_mode = param->hist.dci_hsd_mode;
+        ctx->params.dci_vsd_mode = param->hist.dci_vsd_mode;
+        ctx->params.dci_yrgb_gather_num = param->hist.dci_yrgb_gather_num;
+        ctx->params.dci_yrgb_gather_en = param->hist.dci_yrgb_gather_en;
+        ctx->params.dci_csc_range = param->hist.dci_csc_range;
+        update_dci_ctl(&ctx->params);
+        break;
+    case VDPP_PARAM_TYPE_SHARP:
+        memcpy(&ctx->params.shp_params, &param->sharp, sizeof(ShpParams));
+        break;
+    default:
+        break;
+    }
+
+    return MPP_OK;
+}
+
+static RK_S32 check_cap(struct vdpp2_params *params)
+{
+    RK_S32 ret_cap = VDPP_CAP_UNSUPPORTED;
+    RK_U32 vep_mode_check = 0;
+    RK_U32 hist_mode_check = 0;
+
+    if (NULL == params) {
+        VDPP2_DBG(VDPP2_DBG_CHECK, "found null pointer params\n");
+        return VDPP_CAP_UNSUPPORTED;
+    }
+
+    if (params->src_height_vir < params->src_height ||
+        params->src_width_vir < params->src_width) {
+        VDPP2_DBG(VDPP2_DBG_CHECK, "invalid src img_w %d img_h %d img_w_vir %d img_h_vir %d\n",
+                  params->src_width, params->src_height,
+                  params->src_width_vir, params->src_height_vir);
+        return VDPP_CAP_UNSUPPORTED;
+    }
+
+    if ((params->src_fmt != MPP_FMT_YUV420SP) &&
+        (params->src_fmt != MPP_FMT_YUV420SP_VU)) {
+        VDPP2_DBG(VDPP2_DBG_CHECK, "vep only support nv12 or nv21\n");
+        vep_mode_check++;
+    }
+
+    if ((params->src_height_vir > VDPP2_VEP_MAX_HEIGHT) ||
+        (params->src_width_vir > VDPP2_VEP_MAX_WIDTH) ||
+        (params->src_height < VDPP2_MODE_MIN_HEIGH) ||
+        (params->src_width < VDPP2_MODE_MIN_WIDTH) ||
+        (params->src_height_vir < VDPP2_MODE_MIN_HEIGH) ||
+        (params->src_width_vir < VDPP2_MODE_MIN_WIDTH)) {
+        VDPP2_DBG(VDPP2_DBG_CHECK, "vep unsupported src img_w %d img_h %d img_w_vir %d img_h_vir %d\n",
+                  params->src_width, params->src_height,
+                  params->src_width_vir, params->src_height_vir);
+        vep_mode_check++;
+    }
+
+    if ((params->dst_height_vir > VDPP2_VEP_MAX_HEIGHT) ||
+        (params->dst_width_vir > VDPP2_VEP_MAX_WIDTH) ||
+        (params->dst_height < VDPP2_MODE_MIN_HEIGH) ||
+        (params->dst_width < VDPP2_MODE_MIN_WIDTH) ||
+        (params->dst_height_vir < VDPP2_MODE_MIN_HEIGH) ||
+        (params->dst_width_vir < VDPP2_MODE_MIN_WIDTH) ||
+        (params->dst_height_vir < params->dst_height) ||
+        (params->dst_width_vir < params->dst_width)) {
+        VDPP2_DBG(VDPP2_DBG_CHECK, "vep unsupported dst img_w %d img_h %d img_w_vir %d img_h_vir %d\n",
+                  params->dst_width, params->dst_height,
+                  params->dst_width_vir, params->dst_height_vir);
+        vep_mode_check++;
+    }
+
+    if ((params->src_width_vir & 0xf) || (params->dst_width_vir & 0xf)) {
+        VDPP2_DBG(VDPP2_DBG_CHECK, "vep only support img_w_i/o_vir 16Byte align\n");
+        VDPP2_DBG(VDPP2_DBG_CHECK, "vep unsupported src img_w_vir %d dst img_w_vir %d\n",
+                  params->src_width_vir, params->dst_width_vir);
+        vep_mode_check++;
+    }
+
+    if (params->src_height_vir & 0x7) {
+        VDPP2_DBG(VDPP2_DBG_CHECK, "vep only support img_h_in_vir 8pix align\n");
+        VDPP2_DBG(VDPP2_DBG_CHECK, "vep unsupported src img_h_vir %d\n", params->src_height_vir);
+        vep_mode_check++;
+    }
+
+    if (params->dst_height_vir & 0x1) {
+        VDPP2_DBG(VDPP2_DBG_CHECK, "vep only support img_h_out_vir 2pix align\n");
+        VDPP2_DBG(VDPP2_DBG_CHECK, "vep unsupported dst img_h_vir %d\n", params->dst_height_vir);
+        vep_mode_check++;
+    }
+
+    if ((params->src_width & 1) || (params->src_height & 1) ||
+        (params->dst_width & 1) || (params->dst_height & 1)) {
+        VDPP2_DBG(VDPP2_DBG_CHECK, "vep only support img_w/h_vld 2pix align\n");
+        VDPP2_DBG(VDPP2_DBG_CHECK, "vep unsupported img_w_i %d img_h_i %d img_w_o %d img_h_o %d\n",
+                  params->src_width, params->src_height, params->dst_width, params->dst_height);
+        vep_mode_check++;
+    }
+
+    if (params->yuv_out_diff) {
+        if ((params->dst_c_height_vir > VDPP2_VEP_MAX_HEIGHT) ||
+            (params->dst_c_width_vir > VDPP2_VEP_MAX_WIDTH) ||
+            (params->dst_c_height < VDPP2_MODE_MIN_HEIGH) ||
+            (params->dst_c_width < VDPP2_MODE_MIN_WIDTH) ||
+            (params->dst_c_height_vir < VDPP2_MODE_MIN_HEIGH) ||
+            (params->dst_c_width_vir < VDPP2_MODE_MIN_WIDTH) ||
+            (params->dst_c_height_vir < params->dst_c_height) ||
+            (params->dst_c_width_vir < params->dst_c_width)) {
+            VDPP2_DBG(VDPP2_DBG_CHECK, "vep unsupported dst_c img_w %d img_h %d img_w_vir %d img_h_vir %d\n",
+                      params->dst_c_width, params->dst_c_height,
+                      params->dst_c_width_vir, params->dst_c_height_vir);
+            vep_mode_check++;
+        }
+
+        if (params->dst_c_width_vir & 0xf) {
+            VDPP2_DBG(VDPP2_DBG_CHECK, "vep only support img_w_c_out_vir 16Byte align\n");
+            VDPP2_DBG(VDPP2_DBG_CHECK, "vep unsupported dst img_w_c_vir %d\n", params->dst_c_width_vir);
+            vep_mode_check++;
+        }
+
+        if (params->dst_c_height_vir & 0x1) {
+            VDPP2_DBG(VDPP2_DBG_CHECK, "vep only support img_h_c_out_vir 2pix align\n");
+            VDPP2_DBG(VDPP2_DBG_CHECK, "vep unsupported dst img_h_vir %d\n", params->dst_c_height_vir);
+            vep_mode_check++;
+        }
+
+        if ((params->dst_c_width & 1) || (params->dst_c_height & 1)) {
+            VDPP2_DBG(VDPP2_DBG_CHECK, "vep only support img_c_w/h_vld 2pix align\n");
+            VDPP2_DBG(VDPP2_DBG_CHECK, "vep unsupported img_w_o %d img_h_o %d\n",
+                      params->dst_c_width, params->dst_c_height);
+            vep_mode_check++;
+        }
+    }
+
+    if ((params->src_height_vir > VDPP2_HIST_MAX_HEIGHT) ||
+        (params->src_width_vir > VDPP2_HIST_MAX_WIDTH) ||
+        (params->src_height < VDPP2_MODE_MIN_HEIGH) ||
+        (params->src_width < VDPP2_MODE_MIN_WIDTH)) {
+        VDPP2_DBG(VDPP2_DBG_CHECK, "dci unsupported src img_w %d img_h %d img_w_vir %d img_h_vir %d\n",
+                  params->src_width, params->src_height,
+                  params->src_width_vir, params->src_height_vir);
+        hist_mode_check++;
+    }
+
+    /* 10 bit input */
+    if ((params->src_fmt == MPP_FMT_YUV420SP_10BIT) ||
+        (params->src_fmt == MPP_FMT_YUV422SP_10BIT) ||
+        (params->src_fmt == MPP_FMT_YUV444SP_10BIT)) {
+        if (params->src_width_vir & 0xf) {
+            VDPP2_DBG(VDPP2_DBG_CHECK, "dci Y-10bit input only support img_w_in_vir 16Byte align\n");
+            hist_mode_check++;
+        }
+    } else {
+        if (params->src_width_vir & 0x3) {
+            VDPP2_DBG(VDPP2_DBG_CHECK, "dci only support img_w_in_vir 4Byte align\n");
+            hist_mode_check++;
+        }
+    }
+
+    VDPP2_DBG(VDPP2_DBG_INT, "vdpp2 src img resolution: w-%d-%d, h-%d-%d\n",
+              params->src_width, params->src_width_vir,
+              params->src_height, params->src_height_vir);
+    VDPP2_DBG(VDPP2_DBG_INT, "vdpp2 dst img resolution: w-%d-%d, h-%d-%d\n",
+              params->dst_width, params->dst_width_vir,
+              params->dst_height, params->dst_height_vir);
+
+    if (!vep_mode_check) {
+        ret_cap |= VDPP_CAP_VEP;
+        VDPP2_DBG(VDPP2_DBG_INT, "vdpp2 support mode: VDPP_CAP_VEP\n");
+    }
+
+    if (!hist_mode_check) {
+        VDPP2_DBG(VDPP2_DBG_INT, "vdpp2 support mode: VDPP_CAP_HIST\n");
+        ret_cap |= VDPP_CAP_HIST;
+    }
+
+    return ret_cap;
+}
+
+MPP_RET vdpp2_start(struct vdpp2_api_ctx *ctx)
+{
+    MPP_RET ret;
+    RegOffsetInfo reg_off[2];
+    MppReqV1 mpp_req[12];
+    RK_U32 req_cnt = 0;
+    struct vdpp2_reg *reg = NULL;
+    struct zme_reg *zme = NULL;
+    RK_S32 ret_cap = VDPP_CAP_UNSUPPORTED;
+    RK_S32 work_mode;
+
+    if (NULL == ctx) {
+        mpp_err_f("found NULL input vdpp2 ctx %p\n", ctx);
+        return MPP_ERR_NULL_PTR;
+    }
+
+    work_mode = ctx->params.working_mode;
+    ret_cap = check_cap(&ctx->params);
+    if ((!(ret_cap & VDPP_CAP_VEP) && (VDPP_WORK_MODE_VEP == work_mode)) ||
+        (!(ret_cap & VDPP_CAP_HIST) && (VDPP_WORK_MODE_DCI == work_mode))) {
+        mpp_err_f("found incompat work mode %d %s, cap %d\n", work_mode,
+                  working_mode_name[work_mode & 3], ret_cap);
+        return MPP_NOK;
+    }
+
+    reg = &ctx->reg;
+    zme = &ctx->zme;
+
+    memset(reg_off, 0, sizeof(reg_off));
+    memset(mpp_req, 0, sizeof(mpp_req));
+    memset(reg, 0, sizeof(*reg));
+
+    vdpp2_params_to_reg(&ctx->params, ctx);
+
+    mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_WRITE;
+    mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG;
+    mpp_req[req_cnt].size =  sizeof(zme->yrgb_hor_coe);
+    mpp_req[req_cnt].offset = VDPP_REG_OFF_YRGB_HOR_COE;
+    mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(&zme->yrgb_hor_coe);
+
+    req_cnt++;
+    mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_WRITE;
+    mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG;
+    mpp_req[req_cnt].size =  sizeof(zme->yrgb_ver_coe);
+    mpp_req[req_cnt].offset = VDPP_REG_OFF_YRGB_VER_COE;
+    mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(&zme->yrgb_ver_coe);
+
+    req_cnt++;
+    mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_WRITE;
+    mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG;
+    mpp_req[req_cnt].size =  sizeof(zme->cbcr_hor_coe);
+    mpp_req[req_cnt].offset = VDPP_REG_OFF_CBCR_HOR_COE;
+    mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(&zme->cbcr_hor_coe);
+
+    req_cnt++;
+    mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_WRITE;
+    mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG;
+    mpp_req[req_cnt].size =  sizeof(zme->cbcr_ver_coe);
+    mpp_req[req_cnt].offset = VDPP_REG_OFF_CBCR_VER_COE;
+    mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(&zme->cbcr_ver_coe);
+
+    req_cnt++;
+    mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_WRITE;
+    mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG;
+    mpp_req[req_cnt].size =  sizeof(zme->common);
+    mpp_req[req_cnt].offset = VDPP_REG_OFF_ZME_COMMON;
+    mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(&zme->common);
+
+    req_cnt++;
+    mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_WRITE;
+    mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG;
+    mpp_req[req_cnt].size =  sizeof(ctx->dmsr);
+    mpp_req[req_cnt].offset = VDPP_REG_OFF_DMSR;
+    mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(&ctx->dmsr);
+
+    req_cnt++;
+    mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_WRITE;
+    mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG;
+    mpp_req[req_cnt].size =  sizeof(reg->dci);
+    mpp_req[req_cnt].offset = VDPP_REG_OFF_DCI;
+    mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(&reg->dci);
+
+    req_cnt++;
+    mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_WRITE;
+    mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG;
+    mpp_req[req_cnt].size =  sizeof(reg->es);
+    mpp_req[req_cnt].offset = VDPP_REG_OFF_ES;
+    mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(&reg->es);
+
+    req_cnt++;
+    mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_WRITE;
+    mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG;
+    mpp_req[req_cnt].size =  sizeof(reg->sharp);
+    mpp_req[req_cnt].offset = VDPP_REG_OFF_SHARP;
+    mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(&reg->sharp);
+
+    /* set reg offset */
+    reg_off[0].reg_idx = 25;
+    reg_off[0].offset = ctx->params.src.cbcr_offset;
+    reg_off[1].reg_idx = 27;
+
+    if (!ctx->params.yuv_out_diff)
+        reg_off[1].offset = ctx->params.dst.cbcr_offset;
+    else
+        reg_off[1].offset = ctx->params.dst_c.cbcr_offset;
+    req_cnt++;
+    mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_ADDR_OFFSET;
+    mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG | MPP_FLAGS_REG_OFFSET_ALONE;
+    mpp_req[req_cnt].size = sizeof(reg_off);
+    mpp_req[req_cnt].offset = 0;
+    mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(reg_off);
+
+    req_cnt++;
+    mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_WRITE;
+    mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG;
+    mpp_req[req_cnt].size =  sizeof(reg->common);
+    mpp_req[req_cnt].offset = 0;
+    mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(&reg->common);
+
+    req_cnt++;
+    mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_READ;
+    mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG | MPP_FLAGS_LAST_MSG;
+    mpp_req[req_cnt].size =  sizeof(reg->common);
+    mpp_req[req_cnt].offset = 0;
+    mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(&reg->common);
+
+    ret = (RK_S32)ioctl(ctx->fd, MPP_IOC_CFG_V1, &mpp_req[0]);
+
+    if (ret) {
+        mpp_err_f("ioctl SET_REG failed ret %d errno %d %s\n",
+                  ret, errno, strerror(errno));
+        ret = errno;
+    }
+
+    return ret;
+}
+
+static MPP_RET vdpp2_wait(struct vdpp2_api_ctx *ctx)
+{
+    MPP_RET ret;
+    MppReqV1 mpp_req;
+
+    if (NULL == ctx) {
+        mpp_err_f("found NULL input vdpp ctx %p\n", ctx);
+        return MPP_ERR_NULL_PTR;
+    }
+
+    memset(&mpp_req, 0, sizeof(mpp_req));
+    mpp_req.cmd = MPP_CMD_POLL_HW_FINISH;
+    mpp_req.flag |= MPP_FLAGS_LAST_MSG;
+
+    ret = (RK_S32)ioctl(ctx->fd, MPP_IOC_CFG_V1, &mpp_req);
+    if (ret) {
+        mpp_err_f("ioctl POLL_HW_FINISH failed ret %d errno %d %s\n",
+                  ret, errno, strerror(errno));
+    }
+
+    return ret;
+}
+
+static MPP_RET vdpp2_done(struct vdpp2_api_ctx *ctx)
+{
+    struct vdpp2_reg *reg = &ctx->reg;
+
+    if (NULL == ctx) {
+        mpp_err_f("found NULL input vdpp ctx %p\n", ctx);
+        return MPP_ERR_NULL_PTR;
+    }
+
+    reg = &ctx->reg;
+
+    VDPP2_DBG(VDPP2_DBG_INT, "ro_frm_done_sts=%d\n", reg->common.reg10.ro_frm_done_sts);
+    VDPP2_DBG(VDPP2_DBG_INT, "ro_osd_max_sts=%d\n", reg->common.reg10.ro_osd_max_sts);
+    VDPP2_DBG(VDPP2_DBG_INT, "ro_bus_error_sts=%d\n", reg->common.reg10.ro_bus_error_sts);
+    VDPP2_DBG(VDPP2_DBG_INT, "ro_timeout_sts=%d\n", reg->common.reg10.ro_timeout_sts);
+    VDPP2_DBG(VDPP2_DBG_INT, "ro_config_error_sts=%d\n", reg->common.reg10.ro_timeout_sts);
+
+    if (reg->common.reg8.sw_vdpp_frm_done_en &&
+        !reg->common.reg10.ro_frm_done_sts) {
+        mpp_err_f("run vdpp failed\n");
+        return MPP_NOK;
+    }
+
+    VDPP2_DBG(VDPP2_DBG_INT, "run vdpp success\n");
+
+    return MPP_OK;
+}
+
+static inline MPP_RET set_addr(struct vdpp_addr *addr, VdppImg *img)
+{
+    addr->y = img->mem_addr;
+    addr->cbcr = img->uv_addr;
+    addr->cbcr_offset = img->uv_off;
+
+    return MPP_OK;
+}
+
+MPP_RET vdpp2_control(VdppCtx ictx, VdppCmd cmd, void *iparam)
+{
+    struct vdpp2_api_ctx *ctx = ictx;
+    MPP_RET ret = MPP_OK;
+
+    if ((NULL == iparam && VDPP_CMD_RUN_SYNC != cmd) ||
+        (NULL == ictx)) {
+        mpp_err_f("found NULL iparam %p cmd %d ctx %p\n", iparam, cmd, ictx);
+        return MPP_ERR_NULL_PTR;
+    }
+
+    switch (cmd) {
+    case VDPP_CMD_SET_COM_CFG:
+    case VDPP_CMD_SET_DMSR_CFG:
+    case VDPP_CMD_SET_ZME_COM_CFG:
+    case VDPP_CMD_SET_ZME_COEFF_CFG:
+    case VDPP_CMD_SET_COM2_CFG:
+    case VDPP_CMD_SET_ES:
+    case VDPP_CMD_SET_DCI_HIST:
+    case VDPP_CMD_SET_SHARP: {
+        struct vdpp_api_params *param = (struct vdpp_api_params *)iparam;
+
+        ret = vdpp2_set_param(ctx, &param->param, param->ptype);
+        if (ret) {
+            mpp_err_f("set vdpp parameter failed, type %d\n", param->ptype);
+        }
+        break;
+    }
+    case VDPP_CMD_SET_SRC:
+        set_addr(&ctx->params.src, (VdppImg *)iparam);
+        break;
+    case VDPP_CMD_SET_DST:
+        set_addr(&ctx->params.dst, (VdppImg *)iparam);
+        break;
+    case VDPP_CMD_SET_DST_C:
+        set_addr(&ctx->params.dst_c, (VdppImg *)iparam);
+        break;
+    case VDPP_CMD_SET_HIST_FD:
+        ctx->params.hist = *(RK_S32 *)iparam;
+        break;
+    case VDPP_CMD_RUN_SYNC:
+        ret = vdpp2_start(ctx);
+        if (ret) {
+            mpp_err_f("run vdpp failed\n");
+            return MPP_NOK;
+        }
+
+        vdpp2_wait(ctx);
+        vdpp2_done(ctx);
+        break;
+    default:
+        ;
+    }
+
+    return ret;
+}
+
+RK_S32 vdpp2_check_cap(VdppCtx ictx)
+{
+    struct vdpp2_api_ctx *ctx = ictx;
+
+    if (NULL == ictx) {
+        mpp_err_f("found NULL ctx %p\n", ictx);
+        return VDPP_CAP_UNSUPPORTED;
+    }
+
+    return check_cap(&ctx->params);
+}
diff --git a/mpp/vproc/vdpp/vdpp2.h b/mpp/vproc/vdpp/vdpp2.h
new file mode 100644
index 000000000..b64318a65
--- /dev/null
+++ b/mpp/vproc/vdpp/vdpp2.h
@@ -0,0 +1,254 @@
+/* SPDX-License-Identifier: Apache-2.0 OR MIT */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef __VDPP2_H__
+#define __VDPP2_H__
+
+#include "vdpp2_reg.h"
+#include "vdpp_common.h"
+
+/* vdpp log marco */
+#define VDPP2_DBG_TRACE             (0x00000001)
+#define VDPP2_DBG_INT               (0x00000002)
+#define VDPP2_DBG_CHECK             (0x00000004)
+
+extern RK_U32 vdpp2_debug;
+
+#define VDPP2_DBG(level, fmt, ...)\
+do {\
+    if (level & vdpp2_debug)\
+    { mpp_log(fmt, ## __VA_ARGS__); }\
+} while (0)
+
+typedef struct ShpParams_t {
+    RK_S32 sharp_enable;
+    RK_S32 sharp_coloradj_bypass_en;
+
+    RK_S32 lti_h_enable;
+    RK_S32 lti_h_radius;
+    RK_S32 lti_h_slope;
+    RK_S32 lti_h_thresold;
+    RK_S32 lti_h_gain;
+    RK_S32 lti_h_noise_thr_pos;
+    RK_S32 lti_h_noise_thr_neg;
+
+    RK_S32 lti_v_enable;
+    RK_S32 lti_v_radius;
+    RK_S32 lti_v_slope;
+    RK_S32 lti_v_thresold;
+    RK_S32 lti_v_gain;
+    RK_S32 lti_v_noise_thr_pos;
+    RK_S32 lti_v_noise_thr_neg;
+
+    RK_S32 cti_h_enable;
+    RK_S32 cti_h_radius;
+    RK_S32 cti_h_slope;
+    RK_S32 cti_h_thresold;
+    RK_S32 cti_h_gain;
+    RK_S32 cti_h_noise_thr_pos;
+    RK_S32 cti_h_noise_thr_neg;
+
+    RK_S32 peaking_enable;
+    RK_S32 peaking_gain;
+
+    RK_S32 peaking_coring_enable;
+    RK_S32 peaking_coring_zero[8];
+    RK_S32 peaking_coring_thr[8];
+    RK_S32 peaking_coring_ratio[8];
+
+    RK_S32 peaking_gain_enable;
+    RK_S32 peaking_gain_pos[8];
+    RK_S32 peaking_gain_neg[8];
+
+    RK_S32 peaking_limit_ctrl_enable;
+    RK_S32 peaking_limit_ctrl_pos0[8];
+    RK_S32 peaking_limit_ctrl_pos1[8];
+    RK_S32 peaking_limit_ctrl_neg0[8];
+    RK_S32 peaking_limit_ctrl_neg1[8];
+    RK_S32 peaking_limit_ctrl_ratio[8];
+    RK_S32 peaking_limit_ctrl_bnd_pos[8];
+    RK_S32 peaking_limit_ctrl_bnd_neg[8];
+
+    RK_S32 peaking_edge_ctrl_enable;
+    RK_S32 peaking_edge_ctrl_non_dir_thr;
+    RK_S32 peaking_edge_ctrl_dir_cmp_ratio;
+    RK_S32 peaking_edge_ctrl_non_dir_wgt_offset;
+    RK_S32 peaking_edge_ctrl_non_dir_wgt_ratio;
+    RK_S32 peaking_edge_ctrl_dir_cnt_thr;
+    RK_S32 peaking_edge_ctrl_dir_cnt_avg;
+    RK_S32 peaking_edge_ctrl_dir_cnt_offset;
+    RK_S32 peaking_edge_ctrl_diag_dir_thr;
+    RK_S32 peaking_edge_ctrl_diag_adj_gain_tab[8];
+
+    RK_S32 peaking_estc_enable;
+    RK_S32 peaking_estc_delta_offset_h;
+    RK_S32 peaking_estc_alpha_over_h;
+    RK_S32 peaking_estc_alpha_under_h;
+    RK_S32 peaking_estc_alpha_over_unlimit_h;
+    RK_S32 peaking_estc_alpha_under_unlimit_h;
+    RK_S32 peaking_estc_delta_offset_v;
+    RK_S32 peaking_estc_alpha_over_v;
+    RK_S32 peaking_estc_alpha_under_v;
+    RK_S32 peaking_estc_alpha_over_unlimit_v;
+    RK_S32 peaking_estc_alpha_under_unlimit_v;
+    RK_S32 peaking_estc_delta_offset_d0;
+    RK_S32 peaking_estc_alpha_over_d0;
+    RK_S32 peaking_estc_alpha_under_d0;
+    RK_S32 peaking_estc_alpha_over_unlimit_d0;
+    RK_S32 peaking_estc_alpha_under_unlimit_d0;
+    RK_S32 peaking_estc_delta_offset_d1;
+    RK_S32 peaking_estc_alpha_over_d1;
+    RK_S32 peaking_estc_alpha_under_d1;
+    RK_S32 peaking_estc_alpha_over_unlimit_d1;
+    RK_S32 peaking_estc_alpha_under_unlimit_d1;
+    RK_S32 peaking_estc_delta_offset_non;
+    RK_S32 peaking_estc_alpha_over_non;
+    RK_S32 peaking_estc_alpha_under_non;
+    RK_S32 peaking_estc_alpha_over_unlimit_non;
+    RK_S32 peaking_estc_alpha_under_unlimit_non;
+    RK_S32 peaking_filter_cfg_diag_enh_coef;
+
+    RK_S32 peaking_filt_core_H0[6];
+    RK_S32 peaking_filt_core_H1[6];
+    RK_S32 peaking_filt_core_H2[6];
+    RK_S32 peaking_filt_core_H3[6];
+    RK_S32 peaking_filt_core_V0[3];
+    RK_S32 peaking_filt_core_V1[3];
+    RK_S32 peaking_filt_core_V2[3];
+    RK_S32 peaking_filt_core_USM[3];
+
+    RK_S32 shootctrl_enable;
+    RK_S32 shootctrl_filter_radius;
+    RK_S32 shootctrl_delta_offset;
+    RK_S32 shootctrl_alpha_over;
+    RK_S32 shootctrl_alpha_under;
+    RK_S32 shootctrl_alpha_over_unlimit;
+    RK_S32 shootctrl_alpha_under_unlimit;
+
+    RK_S32 global_gain_enable;
+    RK_S32 global_gain_lum_mode;
+    RK_S32 global_gain_lum_grd[6];
+    RK_S32 global_gain_lum_val[6];
+    RK_S32 global_gain_adp_grd[6];
+    RK_S32 global_gain_adp_val[6];
+    RK_S32 global_gain_var_grd[6];
+    RK_S32 global_gain_var_val[6];
+
+    RK_S32 color_ctrl_enable;
+
+    RK_S32 color_ctrl_p0_scaling_coef;
+    RK_S32 color_ctrl_p0_point_u;
+    RK_S32 color_ctrl_p0_point_v;
+    RK_S32 color_ctrl_p0_roll_tab[16];
+
+    RK_S32 color_ctrl_p1_scaling_coef;
+    RK_S32 color_ctrl_p1_point_u;
+    RK_S32 color_ctrl_p1_point_v;
+    RK_S32 color_ctrl_p1_roll_tab[16];
+
+    RK_S32 color_ctrl_p2_scaling_coef;
+    RK_S32 color_ctrl_p2_point_u;
+    RK_S32 color_ctrl_p2_point_v;
+    RK_S32 color_ctrl_p2_roll_tab[16];
+
+    RK_S32 color_ctrl_p3_scaling_coef;
+    RK_S32 color_ctrl_p3_point_u;
+    RK_S32 color_ctrl_p3_point_v;
+    RK_S32 color_ctrl_p3_roll_tab[16];
+
+    RK_S32 tex_adj_enable;
+    RK_S32 tex_adj_y_mode_select;
+    RK_S32 tex_adj_mode_select;
+    RK_S32 tex_adj_grd[6];
+    RK_S32 tex_adj_val[6];
+} ShpParams;
+
+typedef struct EsParams_t {
+    RK_U32 es_bEnabledES;
+    RK_U32 es_iAngleDelta;
+    RK_U32 es_iAngleDeltaExtra;
+    RK_U32 es_iGradNoDirTh;
+    RK_U32 es_iGradFlatTh;
+    RK_U32 es_iWgtGain;
+    RK_U32 es_iWgtDecay;
+    RK_U32 es_iLowConfTh;
+    RK_U32 es_iLowConfRatio;
+    RK_U32 es_iConfCntTh;
+    RK_U32 es_iWgtLocalTh;
+    RK_U32 es_iK1;
+    RK_U32 es_iK2;
+    RK_U32 es_iDeltaLimit;
+    RK_U32 es_iDiff2conf_lut_x[9];
+    RK_U32 es_iDiff2conf_lut_y[9];
+    RK_U32 es_bEndpointCheckEnable;
+    RK_U32 es_tan_hi_th;
+    RK_U32 es_tan_lo_th;
+} EsParams;
+
+struct vdpp2_params {
+    RK_U32 src_fmt;
+    RK_U32 src_yuv_swap;
+    RK_U32 dst_fmt;
+    RK_U32 dst_yuv_swap;
+    RK_U32 src_width;
+    RK_U32 src_height;
+    RK_U32 src_width_vir;
+    RK_U32 src_height_vir;
+    RK_U32 dst_width;
+    RK_U32 dst_height;
+    RK_U32 dst_width_vir;
+    RK_U32 dst_height_vir;
+    RK_U32 yuv_out_diff;
+    RK_U32 dst_c_width;
+    RK_U32 dst_c_height;
+    RK_U32 dst_c_width_vir;
+    RK_U32 dst_c_height_vir;
+    RK_U32 working_mode;    // 2 - VDPP, 3 - DCI HIST
+
+    struct vdpp_addr src;   // src frame
+    struct vdpp_addr dst;   // dst frame
+    struct vdpp_addr dst_c; // dst chroma
+
+    RK_S32 hist;            // dci hist fd
+
+    struct dmsr_params dmsr_params;
+    struct zme_params zme_params;
+    /* vdpp2 new feature */
+    EsParams   es_params;
+    ShpParams  shp_params;
+
+    RK_U32 hist_cnt_en;
+    RK_U32 dci_hsd_mode;
+    RK_U32 dci_vsd_mode;
+    RK_U32 dci_yrgb_gather_num;
+    RK_U32 dci_yrgb_gather_en;
+    RK_S32 dci_format;
+    RK_S32 dci_alpha_swap;
+    RK_S32 dci_rbuv_swap;
+    RK_S32 dci_csc_range;
+};
+
+struct vdpp2_api_ctx {
+    RK_S32 fd;
+    struct vdpp2_params params;
+    struct vdpp2_reg reg;
+    struct dmsr_reg dmsr;
+    struct zme_reg zme;
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+MPP_RET vdpp2_init(VdppCtx *ictx);
+MPP_RET vdpp2_deinit(VdppCtx ictx);
+MPP_RET vdpp2_control(VdppCtx ictx, VdppCmd cmd, void *iparam);
+RK_S32  vdpp2_check_cap(VdppCtx ictx);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/mpp/vproc/vdpp/vdpp2_reg.h b/mpp/vproc/vdpp/vdpp2_reg.h
new file mode 100644
index 000000000..8dccb9d27
--- /dev/null
+++ b/mpp/vproc/vdpp/vdpp2_reg.h
@@ -0,0 +1,1347 @@
+/* SPDX-License-Identifier: Apache-2.0 OR MIT */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef __VDPP2_REG_H__
+#define __VDPP2_REG_H__
+
+#include "rk_type.h"
+
+#define VDPP_REG_OFF_DMSR               (0x80)
+#define VDPP_REG_OFF_DCI                (0xE0)
+#define VDPP_REG_OFF_ES                 (0x0100)
+#define VDPP_REG_OFF_SHARP              (0x0200)
+#define VDPP_REG_OFF_YRGB_HOR_COE       (0x2000)
+#define VDPP_REG_OFF_YRGB_VER_COE       (0x2200)
+#define VDPP_REG_OFF_CBCR_HOR_COE       (0x2400)
+#define VDPP_REG_OFF_CBCR_VER_COE       (0x2600)
+#define VDPP_REG_OFF_ZME_COMMON         (0x2800)
+
+struct vdpp2_reg {
+    struct {
+
+        struct {
+            RK_U32 sw_vdpp_frm_en       : 1;
+        } reg0;         // 0x0000
+
+        struct {
+            RK_U32 sw_vdpp_src_fmt      : 2;
+            RK_U32 sw_reserved_1        : 2;
+            RK_U32 sw_vdpp_src_yuv_swap : 2;
+            RK_U32 sw_reserved_2        : 2;
+            RK_U32 sw_vdpp_dst_fmt      : 2;
+            RK_U32 sw_vdpp_yuvout_diff_en       : 1;
+            RK_U32 sw_reserved_3        : 1;
+            RK_U32 sw_vdpp_dst_yuv_swap : 2;
+            RK_U32 sw_reserved_4        : 2;
+            RK_U32 sw_vdpp_debug_data_en: 1;
+            RK_U32 sw_reserved_5        : 3;
+            RK_U32 sw_vdpp_rst_protect_dis      : 1;
+            RK_U32 sys_vdpp_sreset_p    : 1;
+            RK_U32 sw_vdpp_init_dis     : 1;
+            RK_U32 sw_reserved_6        : 1;
+            RK_U32 sw_vdpp_dbmsr_en     : 1;
+            RK_U32 sw_dci_en            : 1;
+        } reg1;         // 0x0004
+
+        struct {
+            RK_U32 sw_vdpp_working_mode : 2;
+        } reg2;         // 0x0008
+
+        struct {
+            RK_U32 sw_vdpp_arqos_en     : 1;
+            RK_U32 sw_vdpp_awqos_en     : 1;
+            RK_U32 sw_reserved_1        : 2;
+            RK_U32 sw_ar_mmu_qos3       : 4;
+        } reg3;         // 0x000C
+
+        struct {
+            RK_U32 sw_vdpp_clk_on       : 1;
+            RK_U32 sw_md_clk_on         : 1;
+            RK_U32 sw_dect_clk_on       : 1;
+            RK_U32 sw_me_clk_on         : 1;
+            RK_U32 sw_mc_clk_on         : 1;
+            RK_U32 sw_eedi_clk_on       : 1;
+            RK_U32 sw_ble_clk_on        : 1;
+            RK_U32 sw_out_clk_on        : 1;
+            RK_U32 sw_ctrl_clk_on       : 1;
+            RK_U32 sw_ram_clk_on        : 1;
+            RK_U32 sw_dma_clk_on        : 1;
+            RK_U32 sw_reg_clk_on        : 1;
+        } reg4;         // 0x0010
+
+        struct {
+            RK_U32 ro_arst_finish_done  : 1;
+        } reg5;         // 0x0014
+
+        struct {
+            RK_U32 sw_ar_y_qos1         : 4;
+            RK_U32 sw_ar_y_qos2         : 4;
+            RK_U32 sw_ar_uv_qos1        : 4;
+            RK_U32 sw_ar_uv_qos2        : 4;
+        } reg6;         // 0x0018
+
+        struct {
+            RK_U32 sw_aw_id7_qos        : 4;
+            RK_U32 sw_aw_id8_qos        : 4;
+            RK_U32 sw_aw_id9_qos        : 4;
+            RK_U32 sw_aw_id10_qos       : 4;
+        } reg7;         // 0x001c
+
+        struct {
+            RK_U32 sw_vdpp_frm_done_en  : 1;
+            RK_U32 sw_vdpp_osd_max_en   : 1;
+            RK_U32 sw_reserved_1        : 2;
+            RK_U32 sw_vdpp_bus_error_en : 1;
+            RK_U32 sw_vdpp_timeout_int_en       : 1;
+            RK_U32 sw_vdpp_config_error_en      : 1;
+        } reg8;         // 0x0020
+
+        struct {
+            RK_U32 sw_vdpp_frm_done_clr : 1;
+            RK_U32 sw_vdpp_osd_max_clr  : 1;
+            RK_U32 sw_reserved_1        : 2;
+            RK_U32 sw_vdpp_bus_error_clr: 1;
+            RK_U32 sw_vdpp_timeout_int_clr      : 1;
+            RK_U32 sw_vdpp_config_error_clr     : 1;
+        } reg9;        // 0x0024
+
+        struct {
+            RK_U32 ro_frm_done_sts      : 1;
+            RK_U32 ro_osd_max_sts       : 1;
+            RK_U32 sw_reserved_1        : 2;
+            RK_U32 ro_bus_error_sts     : 1;
+            RK_U32 ro_timeout_sts       : 1;
+            RK_U32 ro_config_error_sts  : 1;
+        } reg10;        // 0x0028, read only
+
+        struct {
+            RK_U32 ro_frm_done_raw      : 1;
+            RK_U32 ro_osd_max_raw       : 1;
+            RK_U32 sw_reserved_1        : 2;
+            RK_U32 ro_bus_error_raw     : 1;
+            RK_U32 ro_timeout_raw       : 1;
+            RK_U32 ro_config_error_raw  : 1;
+        } reg11;        // 0x002C, read only
+
+        struct {
+            RK_U32 sw_vdpp_src_vir_y_stride     : 16;
+        } reg12;         // 0x0030
+
+        struct {
+            RK_U32 sw_vdpp_dst_vir_y_stride     : 16;
+            RK_U32 sw_vdpp_dst_vir_c_stride     : 16;
+        } reg13;         // 0x0034
+
+        struct {
+            RK_U32 sw_vdpp_src_pic_width        : 11;
+            RK_U32 sw_reserved_1        : 1;
+            RK_U32 sw_vdpp_src_right_redundant  : 4;
+            RK_U32 sw_vdpp_src_pic_height       : 11;
+            RK_U32 sw_reserved_2        : 1;
+            RK_U32 sw_vdpp_src_down_redundant   : 3;
+        } reg14;         // 0x0038
+
+        struct {
+            RK_U32 sw_vdpp_dst_pic_width        : 11;
+            RK_U32 sw_reserved_1        : 1;
+            RK_U32 sw_vdpp_dst_right_redundant  : 4;
+            RK_U32 sw_vdpp_dst_pic_height       : 11;
+        } reg15;         // 0x003C
+
+        struct {
+            RK_U32 sw_vdpp_dst_pic_width_c      : 11;
+            RK_U32 reserved1                    : 1;
+            RK_U32 sw_vdpp_dst_right_redundant_c: 4;
+            RK_U32 sw_vdpp_dst_pic_height_c     : 11;
+        } reg16;         // 0x0040
+
+        RK_U32 reg17;    // 0x0044
+        RK_U32 reg18;    // 0x0048
+        RK_U32 reg19;    // 0x004C
+
+        struct {
+            RK_U32 sw_vdpp_timeout_cnt  : 31;
+            RK_U32 sw_vdpp_timeout_en   : 1;
+        } reg20;         // 0x0050
+
+        struct {
+            RK_U32 svnbuild     : 20;
+            RK_U32 minor        : 8;
+            RK_U32 major        : 4;
+        } reg21;         // 0x0054
+
+        struct {
+            RK_U32 dbg_frm_cnt  : 16;
+        } reg22;         // 0x0058
+
+        RK_U32 reg23;    // 0x005C
+
+        struct {
+            RK_U32 sw_vdpp_src_addr_y   : 32;
+        } reg24;         // 0x0060
+
+        struct {
+            RK_U32 sw_vdpp_src_addr_uv  : 32;
+        } reg25;         // 0x0064
+
+        struct {
+            RK_U32 sw_vdpp_dst_addr_y   : 32;
+        } reg26;         // 0x0068
+
+        struct {
+            RK_U32 sw_vdpp_dst_addr_uv  : 32;
+        } reg27;         // 0x006C
+
+    } common;            // offset: 0x1000
+
+    struct {
+        struct {
+            RK_U32 sw_dci_yrgb_addr     : 32;
+        } reg0;          // 0x00E0
+
+        struct {
+            RK_U32 sw_dci_yrgb_vir_stride       : 16;
+            RK_U32 sw_dci_yrgb_gather_num       : 4;
+            RK_U32 sw_dci_yrgb_gather_en: 1;
+        } reg1;          // 0x00E4
+
+        struct {
+            RK_U32 sw_vdpp_src_pic_width: 12;
+            RK_U32 reserved1            : 4;
+            RK_U32 sw_vdpp_src_pic_height       : 12;
+        } reg2;          // 0x00E8
+
+        struct {
+            RK_U32 sw_dci_data_format   : 3;
+            RK_U32 sw_dci_csc_range     : 1;
+            RK_U32 sw_dci_vsd_mode      : 2;
+            RK_U32 sw_dci_hsd_mode      : 1;
+            RK_U32 sw_dci_alpha_swap    : 1;
+            RK_U32 sw_dci_rb_swap       : 1;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_dci_blk_hsize     : 8;
+            RK_U32 sw_dci_blk_vsize     : 8;
+        } reg3;          // 0x00EC
+
+        struct {
+            RK_U32 sw_dci_hist_addr     : 32;
+        } reg4;          // 0x00F0
+
+    } dci;               // offset: 0x10E0
+
+    RK_U32 reg_5_7[3];
+
+    struct {
+        struct {
+            RK_U32 es_enable         : 1;
+        } reg0;          // 0x0100
+
+        struct {
+            RK_U32 flat_th           : 8;
+            RK_U32 dir_th            : 8;
+        } reg1;          // 0x0104
+
+        struct {
+            RK_U32 tan_hi_th         : 9;
+            RK_U32 reserved1         : 7;
+            RK_U32 tan_lo_th         : 9;
+        } reg2;          // 0x0108
+
+        struct {
+            RK_U32 ep_chk_en         : 1;
+            RK_U32 reserved1         : 7;
+            RK_U32 mem_gat_en        : 1;
+        } reg3;          // 0x010C
+
+        struct {
+            RK_U32 diff_gain0        : 16;
+            RK_U32 diff_limit        : 16;
+        } reg4;          // 0x0110
+
+        struct {
+            RK_U32 lut_x0            : 16;
+            RK_U32 diff_gain1        : 16;
+        } reg5;          // 0x0114
+
+        struct {
+            RK_U32 lut_x2            : 16;
+            RK_U32 lut_x1            : 16;
+        } reg6;          // 0x0118
+
+        struct {
+            RK_U32 lut_x4            : 16;
+            RK_U32 lut_x3            : 16;
+        } reg7;          // 0x011C
+
+        struct {
+            RK_U32 lut_x6            : 16;
+            RK_U32 lut_x5            : 16;
+        } reg8;          // 0x0120
+
+        struct {
+            RK_U32 lut_x8            : 16;
+            RK_U32 lut_x7            : 16;
+        } reg9;          // 0x0124
+
+        struct {
+            RK_U32 lut_y0            : 8;
+            RK_U32 lut_y1            : 8;
+            RK_U32 lut_y2            : 8;
+            RK_U32 lut_y3            : 8;
+        } reg10;         // 0x0128
+
+        struct {
+            RK_U32 lut_y4            : 8;
+            RK_U32 lut_y5            : 8;
+            RK_U32 lut_y6            : 8;
+            RK_U32 lut_y7            : 8;
+        } reg11;         // 0x012C
+
+        struct {
+            RK_U32 lut_y8            : 8;
+        } reg12;         // 0x0130
+
+        struct {
+            RK_U32 lut_k0            : 8;
+            RK_U32 lut_k1            : 8;
+            RK_U32 lut_k2            : 8;
+            RK_U32 lut_k3            : 8;
+        } reg13;         // 0x0134
+
+        struct {
+            RK_U32 lut_k4            : 8;
+            RK_U32 lut_k5            : 8;
+            RK_U32 lut_k6            : 8;
+            RK_U32 lut_k7            : 8;
+        } reg14;         // 0x0138
+
+        struct {
+            RK_U32 wgt_decay         : 8;
+            RK_U32 wgt_gain          : 8;
+        } reg15;         // 0x013C
+
+        struct {
+            RK_U32 conf_mean_th      : 8;
+            RK_U32 conf_cnt_th       : 4;
+            RK_U32 reserved1         : 4;
+            RK_U32 low_conf_ratio    : 8;
+            RK_U32 low_conf_th       : 8;
+        } reg16;         // 0x0140
+
+        struct {
+            RK_U32 ink_en            : 1;
+            RK_U32 reserved1         : 3;
+            RK_U32 ink_mode          : 4;
+        } reg17;         // 0x0144
+
+        RK_U32 reg_18_27[10];
+
+        struct {
+            RK_U32 in_rdy            : 1;
+            RK_U32 reserved1         : 3;
+            RK_U32 mem_in_vsync      : 1;
+            RK_U32 reserved2         : 3;
+            RK_U32 in_hsync          : 1;
+            RK_U32 reserved3         : 3;
+            RK_U32 in_vld            : 1;
+            RK_U32 reserved4         : 3;
+            RK_U32 mem_in_line_cnt   : 11;
+        } reg28;         // 0x0170
+
+        struct {
+            RK_U32 in_pix            : 16;
+            RK_U32 in_dir            : 6;
+            RK_U32 reserved1         : 2;
+            RK_U32 in_flat           : 2;
+        } reg29;         // 0x0174
+
+        struct {
+            RK_U32 out_rdy           : 1;
+            RK_U32 reserved1         : 3;
+            RK_U32 out_vsync         : 1;
+            RK_U32 reserved2         : 3;
+            RK_U32 out_hsync         : 1;
+            RK_U32 reserved3         : 3;
+            RK_U32 out_vld           : 1;
+            RK_U32 reserved4         : 3;
+            RK_U32 out_line_cnt      : 11;
+        } reg30;         // 0x0178
+
+        struct {
+            RK_U32 out_pix           : 16;
+        } reg31;         // 0x017C
+
+    } es;                // offset: 0x1100
+
+    RK_U32 reg_32_63[32];
+
+    struct {
+        struct {
+            RK_U32 sw_sharp_enable      : 1;
+            RK_U32 sw_lti_enable        : 1;
+            RK_U32 sw_cti_enable        : 1;
+            RK_U32 sw_peaking_enable    : 1;
+            RK_U32 sw_peaking_ctrl_enable       : 1;
+            RK_U32 reserved1            : 1;
+            RK_U32 sw_edge_proc_enable  : 1;
+            RK_U32 sw_shoot_ctrl_enable : 1;
+            RK_U32 sw_gain_ctrl_enable  : 1;
+            RK_U32 sw_color_adj_enable  : 1;
+            RK_U32 sw_texture_adj_enable: 1;
+            RK_U32 sw_coloradj_bypass_en: 1;
+            RK_U32 sw_ink_enable        : 1;
+            RK_U32 sw_sharp_redundent_bypass    : 1;
+        } reg0;          // 0x0200
+
+        struct {
+            RK_U32 sw_mem_gating_en     : 1;
+            RK_U32 sw_lti_gating_en     : 1;
+            RK_U32 sw_cti_gating_en     : 1;
+            RK_U32 sw_peaking_gating_en : 1;
+            RK_U32 sw_peaking_ctrl_gating_en    : 1;
+            RK_U32 reserved1            : 1;
+            RK_U32 sw_edge_proc_gating_en       : 1;
+            RK_U32 sw_shoot_ctrl_gating_en      : 1;
+            RK_U32 sw_gain_ctrl_gating_en       : 1;
+            RK_U32 sw_color_adj_gating_en       : 1;
+            RK_U32 sw_texture_adj_gating_en     : 1;
+        } reg1;          // 0x0204
+
+        struct {
+            RK_U32 sw_peaking_v00       : 4;
+            RK_U32 sw_peaking_v01       : 4;
+            RK_U32 sw_peaking_v02       : 4;
+            RK_U32 sw_peaking_v10       : 4;
+            RK_U32 sw_peaking_v11       : 4;
+            RK_U32 sw_peaking_v12       : 4;
+        } reg2;          // 0x0208
+
+        struct {
+            RK_U32 sw_peaking_v20       : 4;
+            RK_U32 sw_peaking_v21       : 4;
+            RK_U32 sw_peaking_v22       : 4;
+            RK_U32 sw_peaking_usm0      : 4;
+            RK_U32 sw_peaking_usm1      : 4;
+            RK_U32 sw_peaking_usm2      : 4;
+            RK_U32 sw_diag_coef         : 3;
+        } reg3;          // 0x020C
+
+        struct {
+            RK_U32 sw_peaking_h00       : 6;
+            RK_U32 reserved1            : 2;
+            RK_U32 sw_peaking_h01       : 6;
+            RK_U32 reserved2            : 2;
+            RK_U32 sw_peaking_h02       : 6;
+        } reg4;          // 0x0210
+
+        RK_U32 reg5;
+
+        struct {
+            RK_U32 sw_peaking_h10       : 6;
+            RK_U32 reserved1            : 2;
+            RK_U32 sw_peaking_h11       : 6;
+            RK_U32 reserved2            : 2;
+            RK_U32 sw_peaking_h12       : 6;
+        } reg6;          // 0x0218
+
+        RK_U32 reg7;
+
+        struct {
+            RK_U32 sw_peaking_h20       : 6;
+            RK_U32 reserved1            : 2;
+            RK_U32 sw_peaking_h21       : 6;
+            RK_U32 reserved2            : 2;
+            RK_U32 sw_peaking_h22       : 6;
+        } reg8;          // 0x0220
+
+        RK_U32 reg_9_11[3];
+
+        struct {
+            RK_U32 sw_peaking0_idx_n0   : 9;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_peaking0_idx_n1   : 9;
+        } reg12;         // 0x0230
+
+        struct {
+            RK_U32 sw_peaking0_idx_n2   : 9;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_peaking0_idx_n3   : 9;
+        } reg13;         // 0x0234
+
+        struct {
+            RK_U32 sw_peaking0_idx_p0   : 9;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_peaking0_idx_p1   : 9;
+        } reg14;         // 0x0238
+
+        struct {
+            RK_U32 sw_peaking0_idx_p2   : 9;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_peaking0_idx_p3   : 9;
+        } reg15;         // 0x023C
+
+        struct {
+            RK_U32 sw_peaking0_value_n1 : 9;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_peaking0_value_n2 : 9;
+        } reg16;         // 0x0240
+
+        struct {
+            RK_U32 sw_peaking0_value_n3 : 9;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_peaking0_value_p1 : 9;
+        } reg17;         // 0x0244
+
+        struct {
+            RK_U32 sw_peaking0_value_p2 : 9;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_peaking0_value_p3 : 9;
+        } reg18;         // 0x0248
+
+        struct {
+            RK_U32 sw_peaking0_ratio_n01: 12;
+            RK_U32 reserved1            : 4;
+            RK_U32 sw_peaking0_ratio_n12: 12;
+        } reg19;         // 0x024C
+
+        struct {
+            RK_U32 sw_peaking0_ratio_n23: 12;
+            RK_U32 reserved1            : 4;
+            RK_U32 sw_peaking0_ratio_p01: 12;
+        } reg20;         // 0x0250
+
+        struct {
+            RK_U32 sw_peaking0_ratio_p12: 12;
+            RK_U32 sw_peaking0_ratio_p23: 12;
+        } reg21;         // 0x0254
+
+        RK_U32 reg22;
+
+        struct {
+            RK_U32 sw_peaking1_idx_n0   : 9;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_peaking1_idx_n1   : 9;
+        } reg23;         // 0x025C
+
+        struct {
+            RK_U32 sw_peaking1_idx_n2   : 9;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_peaking1_idx_n3   : 9;
+        } reg24;         // 0x0260
+
+        struct {
+            RK_U32 sw_peaking1_idx_p0   : 9;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_peaking1_idx_p1   : 9;
+        } reg25;         // 0x0264
+
+        struct {
+            RK_U32 sw_peaking1_idx_p2   : 9;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_peaking1_idx_p3   : 9;
+        } reg26;         // 0x0268
+
+        struct {
+            RK_U32 sw_peaking1_value_n1 : 9;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_peaking1_value_n2 : 9;
+        } reg27;         // 0x026C
+
+        struct {
+            RK_U32 sw_peaking1_value_n3 : 9;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_peaking1_value_p1 : 9;
+        } reg28;         // 0x0270
+
+        struct {
+            RK_U32 sw_peaking1_value_p2 : 9;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_peaking1_value_p3 : 9;
+        } reg29;         // 0x0274
+
+        struct {
+            RK_U32 sw_peaking1_ratio_n01: 12;
+            RK_U32 reserved1            : 4;
+            RK_U32 sw_peaking1_ratio_n12: 12;
+        } reg30;         // 0x0278
+
+        struct {
+            RK_U32 sw_peaking1_ratio_n23: 12;
+            RK_U32 reserved1            : 4;
+            RK_U32 sw_peaking1_ratio_p01: 12;
+        } reg31;         // 0x027C
+
+        struct {
+            RK_U32 sw_peaking1_ratio_p12: 12;
+            RK_U32 sw_peaking1_ratio_p23: 12;
+        } reg32;         // 0x0280
+
+        RK_U32 reg33;
+
+        struct {
+            RK_U32 sw_peaking2_idx_n0   : 9;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_peaking2_idx_n1   : 9;
+        } reg34;         // 0x0288
+
+        struct {
+            RK_U32 sw_peaking2_idx_n2   : 9;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_peaking2_idx_n3   : 9;
+        } reg35;         // 0x028C
+
+        struct {
+            RK_U32 sw_peaking2_idx_p0   : 9;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_peaking2_idx_p1   : 9;
+        } reg36;         // 0x0290
+
+        struct {
+            RK_U32 sw_peaking2_idx_p2   : 9;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_peaking2_idx_p3   : 9;
+        } reg37;         // 0x0294
+
+        struct {
+            RK_U32 sw_peaking2_value_n1 : 9;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_peaking2_value_n2 : 9;
+        } reg38;         // 0x0298
+
+        struct {
+            RK_U32 sw_peaking2_value_n3 : 9;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_peaking2_value_p1 : 9;
+        } reg39;         // 0x029C
+
+        struct {
+            RK_U32 sw_peaking2_value_p2 : 9;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_peaking2_value_p3 : 9;
+        } reg40;         // 0x02A0
+
+        struct {
+            RK_U32 sw_peaking2_ratio_n01: 12;
+            RK_U32 reserved1            : 4;
+            RK_U32 sw_peaking2_ratio_n12: 12;
+        } reg41;         // 0x02A4
+
+        struct {
+            RK_U32 sw_peaking2_ratio_n23: 12;
+            RK_U32 reserved1            : 4;
+            RK_U32 sw_peaking2_ratio_p01: 12;
+        } reg42;         // 0x02A8
+
+        struct {
+            RK_U32 sw_peaking2_ratio_p12: 12;
+            RK_U32 sw_peaking2_ratio_p23: 12;
+        } reg43;         // 0x02AC
+
+        RK_U32 reg44;
+
+        struct {
+            RK_U32 sw_peaking3_idx_n0   : 9;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_peaking3_idx_n1   : 9;
+        } reg45;         // 0x02B4
+
+        struct {
+            RK_U32 sw_peaking3_idx_n2   : 9;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_peaking3_idx_n3   : 9;
+        } reg46;         // 0x02B8
+
+        struct {
+            RK_U32 sw_peaking3_idx_p0   : 9;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_peaking3_idx_p1   : 9;
+        } reg47;         // 0x02BC
+
+        struct {
+            RK_U32 sw_peaking3_idx_p2   : 9;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_peaking3_idx_p3   : 9;
+        } reg48;         // 0x02C0
+
+        struct {
+            RK_U32 sw_peaking3_value_n1 : 9;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_peaking3_value_n2 : 9;
+        } reg49;         // 0x02C4
+
+        struct {
+            RK_U32 sw_peaking3_value_n3 : 9;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_peaking3_value_p1 : 9;
+        } reg50;         // 0x02C8
+
+        struct {
+            RK_U32 sw_peaking3_value_p2 : 9;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_peaking3_value_p3 : 9;
+        } reg51;         // 0x02CC
+
+        struct {
+            RK_U32 sw_peaking3_ratio_n01: 12;
+            RK_U32 reserved1            : 4;
+            RK_U32 sw_peaking3_ratio_n12: 12;
+        } reg52;         // 0x02D0
+
+        struct {
+            RK_U32 sw_peaking3_ratio_n23: 12;
+            RK_U32 reserved1            : 4;
+            RK_U32 sw_peaking3_ratio_p01: 12;
+        } reg53;         // 0x02D4
+
+        struct {
+            RK_U32 sw_peaking3_ratio_p12: 12;
+            RK_U32 sw_peaking3_ratio_p23: 12;
+        } reg54;         // 0x02D8
+
+        RK_U32 reg55;
+
+        struct {
+            RK_U32 sw_peaking4_idx_n0   : 9;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_peaking4_idx_n1   : 9;
+        } reg56;         // 0x02E0
+
+        struct {
+            RK_U32 sw_peaking4_idx_n2   : 9;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_peaking4_idx_n3   : 9;
+        } reg57;         // 0x02E4
+
+        struct {
+            RK_U32 sw_peaking4_idx_p0   : 9;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_peaking4_idx_p1   : 9;
+        } reg58;         // 0x02E8
+
+        struct {
+            RK_U32 sw_peaking4_idx_p2   : 9;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_peaking4_idx_p3   : 9;
+        } reg59;         // 0x02EC
+
+        struct {
+            RK_U32 sw_peaking4_value_n1 : 9;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_peaking4_value_n2 : 9;
+        } reg60;         // 0x02F0
+
+        struct {
+            RK_U32 sw_peaking4_value_n3 : 9;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_peaking4_value_p1 : 9;
+        } reg61;         // 0x02F4
+
+        struct {
+            RK_U32 sw_peaking4_value_p2 : 9;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_peaking4_value_p3 : 9;
+        } reg62;         // 0x02F8
+
+        struct {
+            RK_U32 sw_peaking4_ratio_n01: 12;
+            RK_U32 reserved1            : 4;
+            RK_U32 sw_peaking4_ratio_n12: 12;
+        } reg63;         // 0x02FC
+
+        struct {
+            RK_U32 sw_peaking4_ratio_n23: 12;
+            RK_U32 reserved1            : 4;
+            RK_U32 sw_peaking4_ratio_p01: 12;
+        } reg64;         // 0x0300
+
+        struct {
+            RK_U32 sw_peaking4_ratio_p12: 12;
+            RK_U32 sw_peaking4_ratio_p23: 12;
+        } reg65;         // 0x0304
+
+        RK_U32 reg66;
+
+        struct {
+            RK_U32 sw_peaking5_idx_n0   : 9;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_peaking5_idx_n1   : 9;
+        } reg67;         // 0x030C
+
+        struct {
+            RK_U32 sw_peaking5_idx_n2   : 9;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_peaking5_idx_n3   : 9;
+        } reg68;         // 0x0310
+
+        struct {
+            RK_U32 sw_peaking5_idx_p0   : 9;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_peaking5_idx_p1   : 9;
+        } reg69;         // 0x0314
+
+        struct {
+            RK_U32 sw_peaking5_idx_p2   : 9;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_peaking5_idx_p3   : 9;
+        } reg70;         // 0x0318
+
+        struct {
+            RK_U32 sw_peaking5_value_n1 : 9;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_peaking5_value_n2 : 9;
+        } reg71;         // 0x031C
+
+        struct {
+            RK_U32 sw_peaking5_value_n3 : 9;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_peaking5_value_p1 : 9;
+        } reg72;         // 0x0320
+
+        struct {
+            RK_U32 sw_peaking5_value_p2 : 9;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_peaking5_value_p3 : 9;
+        } reg73;         // 0x0324
+
+        struct {
+            RK_U32 sw_peaking5_ratio_n01: 12;
+            RK_U32 reserved1            : 4;
+            RK_U32 sw_peaking5_ratio_n12: 12;
+        } reg74;         // 0x0328
+
+        struct {
+            RK_U32 sw_peaking5_ratio_n23: 12;
+            RK_U32 reserved1            : 4;
+            RK_U32 sw_peaking5_ratio_p01: 12;
+        } reg75;         // 0x032C
+
+        struct {
+            RK_U32 sw_peaking5_ratio_p12: 12;
+            RK_U32 sw_peaking5_ratio_p23: 12;
+        } reg76;         // 0x0330
+
+        RK_U32 reg77;
+
+        struct {
+            RK_U32 sw_peaking6_idx_n0   : 12;
+            RK_U32 reserved1            : 4;
+            RK_U32 sw_peaking6_idx_n1   : 12;
+        } reg78;         // 0x0338
+
+        struct {
+            RK_U32 sw_peaking6_idx_n2   : 9;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_peaking6_idx_n3   : 9;
+        } reg79;         // 0x033C
+
+        struct {
+            RK_U32 sw_peaking6_idx_p0   : 9;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_peaking6_idx_p1   : 9;
+        } reg80;         // 0x0340
+
+        struct {
+            RK_U32 sw_peaking6_idx_p2   : 9;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_peaking6_idx_p3   : 9;
+        } reg81;         // 0x0344
+
+        struct {
+            RK_U32 sw_peaking6_value_n1 : 9;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_peaking6_value_n2 : 9;
+        } reg82;         // 0x0348
+
+        struct {
+            RK_U32 sw_peaking6_value_n3 : 9;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_peaking6_value_p1 : 9;
+        } reg83;         // 0x034C
+
+        struct {
+            RK_U32 sw_peaking6_value_p2 : 9;
+            RK_U32 reserved1            : 7;
+            RK_U32 sw_peaking6_value_p3 : 9;
+        } reg84;         // 0x0350
+
+        struct {
+            RK_U32 sw_peaking6_ratio_n01: 12;
+            RK_U32 reserved1            : 4;
+            RK_U32 sw_peaking6_ratio_n12: 12;
+        } reg85;         // 0x0354
+
+        struct {
+            RK_U32 sw_peaking6_ratio_n23: 12;
+            RK_U32 reserved1            : 4;
+            RK_U32 sw_peaking6_ratio_p01: 12;
+        } reg86;         // 0x0358
+
+        struct {
+            RK_U32 sw_peaking6_ratio_p12: 12;
+            RK_U32 sw_peaking6_ratio_p23: 12;
+        } reg87;         // 0x035C
+
+        RK_U32 reg_88_99[12];
+
+        struct {
+            RK_U32 sw_peaking_gain      : 10;
+            RK_U32 reserved1            : 2;
+            RK_U32 sw_nondir_thr        : 7;
+            RK_U32 reserved2            : 1;
+            RK_U32 sw_dir_cmp_ratio     : 4;
+            RK_U32 sw_nondir_wgt_ratio  : 5;
+        } reg100;        // 0x0390
+
+        struct {
+            RK_U32 sw_nondir_wgt_offset : 8;
+            RK_U32 sw_dir_cnt_thr       : 4;
+            RK_U32 sw_dir_cnt_avg       : 3;
+            RK_U32 reserved1            : 1;
+            RK_U32 sw_dir_cnt_offset    : 4;
+            RK_U32 sw_diag_dir_thr      : 7;
+        } reg101;        // 0x0394
+
+        struct {
+            RK_U32 sw_diag_adjgain_tab0 : 4;
+            RK_U32 sw_diag_adjgain_tab1 : 4;
+            RK_U32 sw_diag_adjgain_tab2 : 4;
+            RK_U32 sw_diag_adjgain_tab3 : 4;
+            RK_U32 sw_diag_adjgain_tab4 : 4;
+            RK_U32 sw_diag_adjgain_tab5 : 4;
+            RK_U32 sw_diag_adjgain_tab6 : 4;
+            RK_U32 sw_diag_adjgain_tab7 : 4;
+        } reg102;        // 0x0398
+
+        struct {
+            RK_U32 sw_edge_alpha_over_non       : 7;
+            RK_U32 reserved1            : 1;
+            RK_U32 sw_edge_alpha_under_non      : 7;
+            RK_U32 reserved2            : 1;
+            RK_U32 sw_edge_alpha_over_unlimit_non       : 7;
+            RK_U32 reserved3            : 1;
+            RK_U32 sw_edge_alpha_under_unlimit_non      : 7;
+        } reg103;        // 0x039C
+
+        struct {
+            RK_U32 sw_edge_alpha_over_v : 7;
+            RK_U32 reserved1            : 1;
+            RK_U32 sw_edge_alpha_under_v: 7;
+            RK_U32 reserved2            : 1;
+            RK_U32 sw_edge_alpha_over_unlimit_v : 7;
+            RK_U32 reserved3            : 1;
+            RK_U32 sw_edge_alpha_under_unlimit_v: 7;
+        } reg104;        // 0x03A0
+
+        struct {
+            RK_U32 sw_edge_alpha_over_h : 7;
+            RK_U32 reserved1            : 1;
+            RK_U32 sw_edge_alpha_under_h: 7;
+            RK_U32 reserved2            : 1;
+            RK_U32 sw_edge_alpha_over_unlimit_h : 7;
+            RK_U32 reserved3            : 1;
+            RK_U32 sw_edge_alpha_under_unlimit_h: 7;
+        } reg105;        // 0x03A4
+
+        struct {
+            RK_U32 sw_edge_alpha_over_d0: 7;
+            RK_U32 reserved1            : 1;
+            RK_U32 sw_edge_alpha_under_d0       : 7;
+            RK_U32 reserved2            : 1;
+            RK_U32 sw_edge_alpha_over_unlimit_d0: 7;
+            RK_U32 reserved3            : 1;
+            RK_U32 sw_edge_alpha_under_unlimit_d0       : 7;
+        } reg106;        // 0x03A8
+
+        struct {
+            RK_U32 sw_edge_alpha_over_d1: 7;
+            RK_U32 reserved1            : 1;
+            RK_U32 sw_edge_alpha_under_d1       : 7;
+            RK_U32 reserved2            : 1;
+            RK_U32 sw_edge_alpha_over_unlimit_d1: 7;
+            RK_U32 reserved3            : 1;
+            RK_U32 sw_edge_alpha_under_unlimit_d1       : 7;
+        } reg107;        // 0x03AC
+
+        struct {
+            RK_U32 sw_edge_delta_offset_non     : 8;
+            RK_U32 sw_edge_delta_offset_v       : 8;
+            RK_U32 sw_edge_delta_offset_h       : 8;
+        } reg108;        // 0x03B0
+
+        struct {
+            RK_U32 sw_edge_delta_offset_d0      : 8;
+            RK_U32 sw_edge_delta_offset_d1      : 8;
+        } reg109;        // 0x03B4
+
+        struct {
+            RK_U32 sw_shoot_filt_radius : 1;
+            RK_U32 reserved1            : 3;
+            RK_U32 sw_shoot_delta_offset: 8;
+            RK_U32 sw_shoot_alpha_over  : 7;
+            RK_U32 reserved2            : 1;
+            RK_U32 sw_shoot_alpha_under : 7;
+        } reg110;        // 0x03B8
+
+        struct {
+            RK_U32 sw_shoot_alpha_over_unlimit  : 7;
+            RK_U32 reserved1            : 1;
+            RK_U32 sw_shoot_alpha_under_unlimit : 7;
+        } reg111;        // 0x03BC
+
+        struct {
+            RK_U32 sw_adp_idx0          : 8;
+            RK_U32 reserved1            : 2;
+            RK_U32 sw_adp_idx1          : 8;
+            RK_U32 reserved2            : 2;
+            RK_U32 sw_adp_idx2          : 8;
+        } reg112;        // 0x03C0
+
+        struct {
+            RK_U32 sw_adp_idx3          : 8;
+            RK_U32 reserved1            : 4;
+            RK_U32 sw_adp_gain0         : 7;
+            RK_U32 reserved2            : 1;
+            RK_U32 sw_adp_gain1         : 7;
+        } reg113;        // 0x03C4
+
+        struct {
+            RK_U32 sw_adp_gain2         : 7;
+            RK_U32 reserved1            : 1;
+            RK_U32 sw_adp_gain3         : 7;
+            RK_U32 reserved2            : 1;
+            RK_U32 sw_adp_gain4         : 7;
+        } reg114;        // 0x03C8
+
+        struct {
+            RK_U32 sw_adp_slp01         : 11;
+            RK_U32 reserved1            : 1;
+            RK_U32 sw_adp_slp12         : 11;
+        } reg115;        // 0x03CC
+
+        RK_U32 reg_116_127[12];
+
+        struct {
+            RK_U32 sw_adp_slp23         : 11;
+            RK_U32 reserved1            : 1;
+            RK_U32 sw_adp_slp34         : 11;
+        } reg128;        // 0x0400
+
+        struct {
+            RK_U32 sw_adp_slp45         : 11;
+            RK_U32 sw_var_idx0          : 8;
+            RK_U32 reserved1            : 2;
+            RK_U32 sw_var_idx1          : 8;
+        } reg129;        // 0x0404
+
+        struct {
+            RK_U32 sw_var_idx2          : 8;
+            RK_U32 reserved1            : 4;
+            RK_U32 sw_var_idx3          : 8;
+            RK_U32 reserved2            : 4;
+            RK_U32 sw_var_gain0         : 7;
+        } reg130;        // 0x0408
+
+        struct {
+            RK_U32 sw_var_gain1         : 7;
+            RK_U32 reserved1            : 1;
+            RK_U32 sw_var_gain2         : 7;
+            RK_U32 reserved2            : 1;
+            RK_U32 sw_var_gain3         : 7;
+            RK_U32 reserved3            : 1;
+            RK_U32 sw_var_gain4         : 7;
+        } reg131;        // 0x040C
+
+        struct {
+            RK_U32 sw_var_slp01         : 11;
+            RK_U32 reserved1            : 1;
+            RK_U32 sw_var_slp12         : 11;
+        } reg132;        // 0x0410
+
+        struct {
+            RK_U32 sw_var_slp23         : 11;
+            RK_U32 reserved1            : 1;
+            RK_U32 sw_var_slp34         : 11;
+        } reg133;        // 0x0414
+
+        struct {
+            RK_U32 sw_var_slp45         : 11;
+            RK_U32 reserved1            : 5;
+            RK_U32 sw_lum_select        : 2;
+            RK_U32 reserved2            : 2;
+            RK_U32 sw_lum_idx0          : 8;
+        } reg134;        // 0x0418
+
+        struct {
+            RK_U32 sw_lum_idx1          : 8;
+            RK_U32 reserved1            : 2;
+            RK_U32 sw_lum_idx2          : 8;
+            RK_U32 reserved2            : 2;
+            RK_U32 sw_lum_idx3          : 8;
+        } reg135;        // 0x041C
+
+        struct {
+            RK_U32 sw_lum_gain0         : 7;
+            RK_U32 reserved1            : 1;
+            RK_U32 sw_lum_gain1         : 7;
+            RK_U32 reserved2            : 1;
+            RK_U32 sw_lum_gain2         : 7;
+            RK_U32 reserved3            : 1;
+            RK_U32 sw_lum_gain3         : 7;
+        } reg136;        // 0x0420
+
+        struct {
+            RK_U32 sw_lum_gain4         : 7;
+            RK_U32 reserved1            : 1;
+            RK_U32 sw_lum_slp01         : 11;
+            RK_U32 reserved2            : 1;
+            RK_U32 sw_lum_slp12         : 11;
+        } reg137;        // 0x0424
+
+        struct {
+            RK_U32 sw_lum_slp23         : 11;
+            RK_U32 reserved1            : 1;
+            RK_U32 sw_lum_slp34         : 11;
+        } reg138;        // 0x0428
+
+        struct {
+            RK_U32 sw_lum_slp45         : 11;
+        } reg139;        // 0x042C
+
+        struct {
+            RK_U32 sw_adj_point_x0      : 8;
+            RK_U32 reserved1            : 4;
+            RK_U32 sw_adj_point_y0      : 8;
+            RK_U32 reserved2            : 4;
+            RK_U32 sw_adj_scaling_coef0 : 3;
+        } reg140;        // 0x0430
+
+        struct {
+            RK_U32 sw_coloradj_tab0_0   : 5;
+            RK_U32 sw_coloradj_tab0_1   : 5;
+            RK_U32 sw_coloradj_tab0_2   : 5;
+            RK_U32 sw_coloradj_tab0_3   : 5;
+            RK_U32 sw_coloradj_tab0_4   : 5;
+            RK_U32 sw_coloradj_tab0_5   : 5;
+        } reg141;        // 0x0434
+
+        struct {
+            RK_U32 sw_coloradj_tab0_6   : 5;
+            RK_U32 sw_coloradj_tab0_7   : 5;
+            RK_U32 sw_coloradj_tab0_8   : 5;
+            RK_U32 sw_coloradj_tab0_9   : 5;
+            RK_U32 sw_coloradj_tab0_10  : 5;
+            RK_U32 sw_coloradj_tab0_11  : 5;
+        } reg142;        // 0x0438
+
+        struct {
+            RK_U32 sw_coloradj_tab0_12  : 5;
+            RK_U32 sw_coloradj_tab0_13  : 5;
+            RK_U32 sw_coloradj_tab0_14  : 5;
+            RK_U32 sw_coloradj_tab0_15  : 5;
+        } reg143;        // 0x043C
+
+        struct {
+            RK_U32 sw_adj_point_x1      : 8;
+            RK_U32 reserved1            : 4;
+            RK_U32 sw_adj_point_y1      : 8;
+            RK_U32 reserved2            : 4;
+            RK_U32 sw_adj_scaling_coef1 : 3;
+        } reg144;        // 0x0440
+
+        struct {
+            RK_U32 sw_coloradj_tab1_0   : 5;
+            RK_U32 sw_coloradj_tab1_1   : 5;
+            RK_U32 sw_coloradj_tab1_2   : 5;
+            RK_U32 sw_coloradj_tab1_3   : 5;
+            RK_U32 sw_coloradj_tab1_4   : 5;
+            RK_U32 sw_coloradj_tab1_5   : 5;
+        } reg145;        // 0x0444
+
+        struct {
+            RK_U32 sw_coloradj_tab1_6   : 5;
+            RK_U32 sw_coloradj_tab1_7   : 5;
+            RK_U32 sw_coloradj_tab1_8   : 5;
+            RK_U32 sw_coloradj_tab1_9   : 5;
+            RK_U32 sw_coloradj_tab1_10  : 5;
+            RK_U32 sw_coloradj_tab1_11  : 5;
+        } reg146;        // 0x0448
+
+        struct {
+            RK_U32 sw_coloradj_tab1_12  : 5;
+            RK_U32 sw_coloradj_tab1_13  : 5;
+            RK_U32 sw_coloradj_tab1_14  : 5;
+            RK_U32 sw_coloradj_tab1_15  : 5;
+        } reg147;        // 0x044C
+
+        struct {
+            RK_U32 sw_adj_point_x2      : 8;
+            RK_U32 reserved1            : 4;
+            RK_U32 sw_adj_point_y2      : 8;
+            RK_U32 reserved2            : 4;
+            RK_U32 sw_adj_scaling_coef2 : 3;
+        } reg148;        // 0x0450
+
+        struct {
+            RK_U32 sw_coloradj_tab2_0   : 5;
+            RK_U32 sw_coloradj_tab2_1   : 5;
+            RK_U32 sw_coloradj_tab2_2   : 5;
+            RK_U32 sw_coloradj_tab2_3   : 5;
+            RK_U32 sw_coloradj_tab2_4   : 5;
+            RK_U32 sw_coloradj_tab2_5   : 5;
+        } reg149;        // 0x0454
+
+        struct {
+            RK_U32 sw_coloradj_tab2_6   : 5;
+            RK_U32 sw_coloradj_tab2_7   : 5;
+            RK_U32 sw_coloradj_tab2_8   : 5;
+            RK_U32 sw_coloradj_tab2_9   : 5;
+            RK_U32 sw_coloradj_tab2_10  : 5;
+            RK_U32 sw_coloradj_tab2_11  : 5;
+        } reg150;        // 0x0458
+
+        struct {
+            RK_U32 sw_coloradj_tab2_12  : 5;
+            RK_U32 sw_coloradj_tab2_13  : 5;
+            RK_U32 sw_coloradj_tab2_14  : 5;
+            RK_U32 sw_coloradj_tab2_15  : 5;
+        } reg151;        // 0x045C
+
+        struct {
+            RK_U32 sw_adj_point_x3      : 8;
+            RK_U32 reserved1            : 4;
+            RK_U32 sw_adj_point_y3      : 8;
+            RK_U32 reserved2            : 4;
+            RK_U32 sw_adj_scaling_coef3 : 3;
+        } reg152;        // 0x0460
+
+        struct {
+            RK_U32 sw_coloradj_tab3_0   : 5;
+            RK_U32 sw_coloradj_tab3_1   : 5;
+            RK_U32 sw_coloradj_tab3_2   : 5;
+            RK_U32 sw_coloradj_tab3_3   : 5;
+            RK_U32 sw_coloradj_tab3_4   : 5;
+            RK_U32 sw_coloradj_tab3_5   : 5;
+        } reg153;        // 0x0464
+
+        struct {
+            RK_U32 sw_coloradj_tab3_6   : 5;
+            RK_U32 sw_coloradj_tab3_7   : 5;
+            RK_U32 sw_coloradj_tab3_8   : 5;
+            RK_U32 sw_coloradj_tab3_9   : 5;
+            RK_U32 sw_coloradj_tab3_10  : 5;
+            RK_U32 sw_coloradj_tab3_11  : 5;
+        } reg154;        // 0x0468
+
+        struct {
+            RK_U32 sw_coloradj_tab3_12  : 5;
+            RK_U32 sw_coloradj_tab3_13  : 5;
+            RK_U32 sw_coloradj_tab3_14  : 5;
+            RK_U32 sw_coloradj_tab3_15  : 5;
+        } reg155;        // 0x046C
+
+        struct {
+            RK_U32 sw_idxmode_select    : 1;
+            RK_U32 sw_ymode_select      : 2;
+            RK_U32 reserved1            : 1;
+            RK_U32 sw_tex_idx0          : 8;
+            RK_U32 reserved2            : 4;
+            RK_U32 sw_tex_idx1          : 8;
+        } reg156;        // 0x0470
+
+        struct {
+            RK_U32 sw_tex_idx2          : 8;
+            RK_U32 reserved1            : 4;
+            RK_U32 sw_tex_idx3          : 8;
+            RK_U32 reserved2            : 4;
+            RK_U32 sw_tex_gain0         : 7;
+        } reg157;        // 0x0474
+
+        struct {
+            RK_U32 sw_tex_gain1         : 7;
+            RK_U32 reserved1            : 1;
+            RK_U32 sw_tex_gain2         : 7;
+            RK_U32 reserved2            : 1;
+            RK_U32 sw_tex_gain3         : 7;
+            RK_U32 reserved3            : 1;
+            RK_U32 sw_tex_gain4         : 7;
+        } reg158;        // 0x0478
+
+        struct {
+            RK_U32 sw_tex_slp01         : 11;
+            RK_U32 reserved1            : 1;
+            RK_U32 sw_tex_slp12         : 11;
+        } reg159;        // 0x047C
+
+        struct {
+            RK_U32 sw_tex_slp23         : 11;
+            RK_U32 reserved1            : 1;
+            RK_U32 sw_tex_slp34         : 11;
+        } reg160;        // 0x0480
+
+        struct {
+            RK_U32 sw_tex_slp45         : 11;
+        } reg161;        // 0x0484
+
+        struct {
+            RK_U32 sw_ltih_radius       : 1;
+            RK_U32 reserved1            : 3;
+            RK_U32 sw_ltih_slp1         : 9;
+            RK_U32 reserved2            : 3;
+            RK_U32 sw_ltih_thr1         : 9;
+        } reg162;        // 0x0488
+
+        struct {
+            RK_U32 sw_ltih_noisethrneg  : 10;
+            RK_U32 reserved1            : 2;
+            RK_U32 sw_ltih_noisethrpos  : 10;
+            RK_U32 reserved2            : 2;
+            RK_U32 sw_ltih_tigain       : 5;
+        } reg163;        // 0x048C
+
+        struct {
+            RK_U32 sw_ltiv_radius       : 1;
+            RK_U32 reserved1            : 3;
+            RK_U32 sw_ltiv_slp1         : 9;
+            RK_U32 reserved2            : 3;
+            RK_U32 sw_ltiv_thr1         : 9;
+        } reg164;        // 0x0490
+
+        struct {
+            RK_U32 sw_ltiv_noisethrneg  : 10;
+            RK_U32 reserved1            : 2;
+            RK_U32 sw_ltiv_noisethrpos  : 10;
+            RK_U32 reserved2            : 2;
+            RK_U32 sw_ltiv_tigain       : 5;
+        } reg165;        // 0x0494
+
+        struct {
+            RK_U32 sw_ctih_radius       : 1;
+            RK_U32 reserved1            : 3;
+            RK_U32 sw_ctih_slp1         : 9;
+            RK_U32 reserved2            : 3;
+            RK_U32 sw_ctih_thr1         : 9;
+        } reg166;        // 0x0498
+
+        struct {
+            RK_U32 sw_ctih_noisethrneg  : 10;
+            RK_U32 reserved1            : 2;
+            RK_U32 sw_ctih_noisethrpos  : 10;
+            RK_U32 reserved2            : 2;
+            RK_U32 sw_ctih_tigain       : 5;
+        } reg167;        // 0x049C
+
+        RK_U32 reg_168_169[2];
+
+        struct {
+            RK_U32 sw_ink_mode          : 4;
+        } reg170;        // 0x04A8
+
+        RK_U32 reg171;
+
+    } sharp;             // offset: 0x1200
+
+};
+
+#endif
diff --git a/mpp/vproc/vdpp/vdpp_api.c b/mpp/vproc/vdpp/vdpp_api.c
new file mode 100644
index 000000000..59595e452
--- /dev/null
+++ b/mpp/vproc/vdpp/vdpp_api.c
@@ -0,0 +1,119 @@
+/* SPDX-License-Identifier: Apache-2.0 OR MIT */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#include "mpp_soc.h"
+#include "mpp_mem.h"
+
+#include "vdpp_api.h"
+#include "vdpp.h"
+#include "vdpp2.h"
+
+vdpp_com_ctx *rockchip_vdpp_api_alloc_ctx(void)
+{
+    vdpp_com_ctx *com_ctx = mpp_calloc(vdpp_com_ctx, 1);
+    vdpp_com_ops *ops = mpp_calloc(vdpp_com_ops, 1);
+    VdppCtx ctx = NULL;
+
+    if (NULL == com_ctx || NULL == ops) {
+        mpp_err_f("failed to calloc com_ctx %p ops %p\n", com_ctx, ops);
+        goto __ERR;
+    }
+
+    if (mpp_get_soc_type() == ROCKCHIP_SOC_RK3576) {
+        ops->init = vdpp2_init;
+        ops->deinit = vdpp2_deinit;
+        ops->control = vdpp2_control;
+        ops->check_cap = vdpp2_check_cap;
+
+        ctx = mpp_calloc(struct vdpp2_api_ctx, 1);
+    } else {
+        ops->init = vdpp_init;
+        ops->deinit = vdpp_deinit;
+        ops->control = vdpp_control;
+        ops->check_cap = vdpp_check_cap;
+
+        ctx = mpp_calloc(struct vdpp_api_ctx, 1);
+    }
+
+    if (NULL == ctx) {
+        mpp_err_f("failed to calloc vdpp_api_ctx %p\n", ctx);
+        goto __ERR;
+    }
+
+    com_ctx->ops = ops;
+    com_ctx->priv = ctx;
+
+    return com_ctx;
+
+__ERR:
+    MPP_FREE(com_ctx);
+    MPP_FREE(ops);
+    MPP_FREE(ctx);
+    return NULL;
+}
+
+void rockchip_vdpp_api_release_ctx(vdpp_com_ctx *com_ctx)
+{
+    if (NULL == com_ctx)
+        return;
+
+    MPP_FREE(com_ctx->ops);
+    MPP_FREE(com_ctx->priv);
+    MPP_FREE(com_ctx);
+}
+
+MPP_RET dci_hist_info_parser(RK_U8* p_pack_hist_addr, RK_U32* p_hist_local, RK_U32* p_hist_global)
+{
+    RK_U32 hw_hist_idx = 0;
+    RK_U32 idx;
+
+    if (NULL == p_pack_hist_addr || NULL == p_hist_local || NULL == p_hist_global) {
+        mpp_err_f("found NULL ptr, pack_hist %p hist_local %p hist_global %p\n",  p_pack_hist_addr, p_hist_local, p_hist_global);
+        return MPP_ERR_NULL_PTR;
+    }
+
+    /* Hist packed (10240 byte) -> unpacked (local: 16 * 16 * 16 * U32 + global: 256 * U32) */
+    for (idx = 0; idx < RKVOP_PQ_PREPROCESS_HIST_SIZE_VERI * RKVOP_PQ_PREPROCESS_HIST_SIZE_HORI * RKVOP_PQ_PREPROCESS_LOCAL_HIST_BIN_NUMS; idx = idx + 4) {
+        RK_U32 tmp0_u18, tmp1_u18, tmp2_u18, tmp3_u18;
+        RK_U32 tmp0_u8, tmp1_u8, tmp2_u8, tmp3_u8, tmp4_u8, tmp5_u8, tmp6_u8, tmp7_u8, tmp8_u8;
+
+        tmp0_u8 = *(p_pack_hist_addr + hw_hist_idx + 0);
+        tmp1_u8 = *(p_pack_hist_addr + hw_hist_idx + 1);
+        tmp2_u8 = *(p_pack_hist_addr + hw_hist_idx + 2);
+        tmp3_u8 = *(p_pack_hist_addr + hw_hist_idx + 3);
+        tmp4_u8 = *(p_pack_hist_addr + hw_hist_idx + 4);
+        tmp5_u8 = *(p_pack_hist_addr + hw_hist_idx + 5);
+        tmp6_u8 = *(p_pack_hist_addr + hw_hist_idx + 6);
+        tmp7_u8 = *(p_pack_hist_addr + hw_hist_idx + 7);
+        tmp8_u8 = *(p_pack_hist_addr + hw_hist_idx + 8);
+
+        tmp0_u18 = ((tmp2_u8 & ((1 << 2) - 1)) << 16) + (tmp1_u8 << 8) + tmp0_u8;
+        tmp1_u18 = ((tmp4_u8 & ((1 << 4) - 1)) << 14) + (tmp3_u8 << 6) + (tmp2_u8 >> 2);
+        tmp2_u18 = ((tmp6_u8 & ((1 << 6) - 1)) << 12) + (tmp5_u8 << 4) + (tmp4_u8 >> 4);
+        tmp3_u18 = (tmp8_u8 << 10) + (tmp7_u8 << 2) + (tmp6_u8 >> 6);
+
+        *(p_hist_local + idx + 0) = tmp0_u18;
+        *(p_hist_local + idx + 1) = tmp1_u18;
+        *(p_hist_local + idx + 2) = tmp2_u18;
+        *(p_hist_local + idx + 3) = tmp3_u18;
+        hw_hist_idx += 9;
+    }
+
+    for (idx = 0; idx < RKVOP_PQ_PREPROCESS_GLOBAL_HIST_BIN_NUMS; idx++) {
+        RK_U32 tmp0_u8, tmp1_u8, tmp2_u8, tmp3_u8;
+        RK_U32 tmp_u32;
+
+        tmp0_u8 = *(p_pack_hist_addr + hw_hist_idx + 0);
+        tmp1_u8 = *(p_pack_hist_addr + hw_hist_idx + 1);
+        tmp2_u8 = *(p_pack_hist_addr + hw_hist_idx + 2);
+        tmp3_u8 = *(p_pack_hist_addr + hw_hist_idx + 3);
+
+        tmp_u32 = (tmp3_u8 << 24) + (tmp2_u8 << 16) + (tmp1_u8 << 8) + tmp0_u8;
+        *(p_hist_global + idx + 0) = tmp_u32;
+        hw_hist_idx += 4;
+    }
+
+    return MPP_OK;
+}
diff --git a/mpp/vproc/vdpp/vdpp_common.c b/mpp/vproc/vdpp/vdpp_common.c
new file mode 100644
index 000000000..eb26f7e46
--- /dev/null
+++ b/mpp/vproc/vdpp/vdpp_common.c
@@ -0,0 +1,1197 @@
+/* SPDX-License-Identifier: Apache-2.0 OR MIT */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#define MODULE_TAG "vdpp_common"
+
+#include "vdpp_common.h"
+
+const char *working_mode_name[] = {
+    NULL,
+    NULL,
+    "VEP MODE",
+    "DCI HIST MODE",
+};
+
+#define VDPP_SET_ZME_COEF(index, row, col) \
+    do { \
+        zme->yrgb_hor_coe.reg##index.yrgb_hor_coe##row##_##col = \
+        yrgb_scl_info.xscl_zme_coe[row][col]; \
+        zme->yrgb_ver_coe.reg##index.yrgb_ver_coe##row##_##col = \
+        yrgb_scl_info.yscl_zme_coe[row][col]; \
+        zme->cbcr_hor_coe.reg##index.cbcr_hor_coe##row##_##col = \
+        cbcr_scl_info.xscl_zme_coe[row][col]; \
+        zme->cbcr_ver_coe.reg##index.cbcr_ver_coe##row##_##col = \
+        cbcr_scl_info.yscl_zme_coe[row][col]; \
+    } while (0);
+
+static RK_U16 vdpp_scale_threshold[] = {
+    2667, 2000, 1500, 1000, 833, 700, 500, 330, 250,
+};
+
+static RK_S16 g_zme_tap8_coeff[11][17][8] = {
+//>=2.667
+    {
+        {   4, -12,  20, 488,  20, -12,   4,   0},
+        {   4,  -8,   8, 484,  36, -16,   4,   0},
+        {   4,  -4,  -4, 476,  52, -20,   8,   0},
+        {   0,   0, -16, 480,  68, -28,   8,   0},
+        {   0,   4, -24, 472,  84, -32,   8,   0},
+        {   0,   4, -36, 468, 100, -36,  12,   0},
+        {   0,   8, -44, 456, 120, -40,  12,   0},
+        {   0,  12, -52, 448, 136, -44,  12,   0},
+        {   0,  12, -56, 436, 156, -48,  16,  -4},
+        {  -4,  16, -60, 424, 176, -52,  16,  -4},
+        {  -4,  16, -64, 412, 196, -56,  16,  -4},
+        {  -4,  16, -68, 400, 216, -60,  16,  -4},
+        {  -4,  20, -72, 380, 236, -64,  20,  -4},
+        {  -4,  20, -72, 364, 256, -68,  20,  -4},
+        {  -4,  20, -72, 348, 272, -68,  20,  -4},
+        {  -4,  20, -72, 332, 292, -72,  20,  -4},
+        {  -4,  20, -72, 312, 312, -72,  20,  -4},
+    },
+//>=2
+    {
+        {   8, -24,  44, 456,  44, -24,   8,   0},
+        {   8, -20,  28, 460,  56, -28,   8,   0},
+        {   8, -16,  16, 452,  72, -32,  12,   0},
+        {   4, -12,   8, 448,  88, -36,  12,   0},
+        {   4,  -8,  -4, 444, 104, -40,  12,   0},
+        {   4,  -8, -16, 444, 120, -44,  12,   0},
+        {   4,  -4, -24, 432, 136, -48,  16,   0},
+        {   4,   0, -32, 428, 152, -52,  16,  -4},
+        {   0,   4, -40, 424, 168, -56,  16,  -4},
+        {   0,   4, -44, 412, 188, -60,  16,  -4},
+        {   0,   8, -52, 400, 204, -60,  16,  -4},
+        {   0,   8, -56, 388, 224, -64,  16,  -4},
+        {   0,  12, -60, 372, 240, -64,  16,  -4},
+        {   0,  12, -64, 356, 264, -68,  16,  -4},
+        {   0,  12, -64, 340, 280, -68,  16,  -4},
+        {   0,  16, -68, 324, 296, -68,  16,  -4},
+        {   0,  16, -68, 308, 308, -68,  16,   0},
+    },
+//>=1.5
+    {
+        {  12, -32,  64, 424,  64, -32,  12,   0},
+        {   8, -32,  52, 432,  76, -36,  12,   0},
+        {   8, -28,  40, 432,  88, -40,  12,   0},
+        {   8, -24,  28, 428, 104, -44,  12,   0},
+        {   8, -20,  16, 424, 120, -48,  12,   0},
+        {   8, -16,   8, 416, 132, -48,  12,   0},
+        {   4, -16,  -4, 420, 148, -52,  12,   0},
+        {   4, -12, -12, 412, 164, -56,  12,   0},
+        {   4,  -8, -20, 400, 180, -56,  12,   0},
+        {   4,  -4, -28, 388, 196, -56,  12,   0},
+        {   4,  -4, -32, 380, 212, -60,  12,   0},
+        {   4,   0, -40, 368, 228, -60,  12,   0},
+        {   4,   0, -44, 356, 244, -60,  12,   0},
+        {   0,   4, -48, 344, 260, -60,  12,   0},
+        {   0,   4, -52, 332, 276, -60,  12,   0},
+        {   0,   8, -56, 320, 292, -60,   8,   0},
+        {   0,   8, -56, 304, 304, -56,   8,   0},
+    },
+//>1
+    {
+        {  12, -40,  84, 400,  84, -40,  12,   0},
+        {  12, -40,  72, 404,  96, -44,  12,   0},
+        {  12, -36,  60, 404, 108, -48,  12,   0},
+        {   8, -32,  48, 404, 120, -48,  12,   0},
+        {   8, -32,  36, 404, 136, -52,  12,   0},
+        {   8, -28,  28, 396, 148, -52,  12,   0},
+        {   8, -24,  16, 392, 160, -52,  12,   0},
+        {   8, -20,   8, 384, 176, -56,  12,   0},
+        {   8, -20,   0, 384, 188, -56,   8,   0},
+        {   8, -16,  -8, 372, 204, -56,   8,   0},
+        {   8, -12, -16, 364, 216, -56,   8,   0},
+        {   4, -12, -20, 356, 232, -56,   8,   0},
+        {   4,  -8, -28, 348, 244, -56,   8,   0},
+        {   4,  -8, -32, 332, 264, -52,   4,   0},
+        {   4,  -4, -36, 324, 272, -52,   4,   0},
+        {   4,   0, -40, 312, 280, -48,   0,   4},
+        {   4,   0, -44, 296, 296, -44,   0,   4},
+    },
+//==1
+    {
+        { 0,  0,  0,   511, 0,   0,   0,  0 },
+        { -1, 3,  -12, 511, 14,  -4,  1,  0 },
+        { -2, 6,  -23, 509, 28,  -8,  2,  0 },
+        { -2, 9,  -33, 503, 44,  -12, 3,  0 },
+        { -3, 11, -41, 496, 61,  -16, 4,  0 },
+        { -3, 13, -48, 488, 79,  -21, 5,  -1 },
+        { -3, 14, -54, 477, 98,  -25, 7,  -2 },
+        { -4, 16, -59, 465, 118, -30, 8,  -2 },
+        { -4, 17, -63, 451, 138, -35, 9,  -1 },
+        { -4, 18, -66, 437, 158, -39, 10, -2 },
+        { -4, 18, -68, 421, 180, -44, 11, -2 },
+        { -4, 18, -69, 404, 201, -48, 13, -3 },
+        { -4, 18, -70, 386, 222, -52, 14, -2 },
+        { -4, 18, -70, 368, 244, -56, 15, -3 },
+        { -4, 18, -69, 348, 265, -59, 16, -3 },
+        { -4, 18, -67, 329, 286, -63, 16, -3 },
+        { -3, 17, -65, 307, 307, -65, 17, -3 },
+    },
+//>=0.833
+    {
+        { -16, 0,   145, 254, 145, 0,  -16, 0 },
+        { -16, -2,  140, 253, 151, 3,  -17, 0 },
+        { -15, -5,  135, 253, 157, 5,  -18, 0 },
+        { -14, -7,  129, 252, 162, 8,  -18, 0 },
+        { -13, -9,  123, 252, 167, 11, -19, 0 },
+        { -13, -11, 118, 250, 172, 15, -19, 0 },
+        { -12, -12, 112, 250, 177, 18, -20, -1 },
+        { -11, -14, 107, 247, 183, 21, -20, -1 },
+        { -10, -15, 101, 245, 188, 25, -21, -1 },
+        { -9,  -16, 96,  243, 192, 29, -21, -2 },
+        { -8,  -18, 90,  242, 197, 33, -22, -2 },
+        { -8,  -19, 85,  239, 202, 37, -22, -2 },
+        { -7,  -19, 80,  236, 206, 41, -22, -3 },
+        { -7,  -20, 75,  233, 210, 46, -22, -3 },
+        { -6,  -21, 69,  230, 215, 50, -22, -3 },
+        { -5,  -21, 65,  226, 219, 55, -22, -5 },
+        { -5,  -21, 60,  222, 222, 60, -21, -5 },
+    },
+//>=0.7
+    {
+        { -16, 0,   145, 254, 145, 0,  -16, 0 },
+        { -16, -2,  140, 253, 151, 3,  -17, 0 },
+        { -15, -5,  135, 253, 157, 5,  -18, 0 },
+        { -14, -7,  129, 252, 162, 8,  -18, 0 },
+        { -13, -9,  123, 252, 167, 11, -19, 0 },
+        { -13, -11, 118, 250, 172, 15, -19, 0 },
+        { -12, -12, 112, 250, 177, 18, -20, -1 },
+        { -11, -14, 107, 247, 183, 21, -20, -1 },
+        { -10, -15, 101, 245, 188, 25, -21, -1 },
+        { -9,  -16, 96,  243, 192, 29, -21, -2 },
+        { -8,  -18, 90,  242, 197, 33, -22, -2 },
+        { -8,  -19, 85,  239, 202, 37, -22, -2 },
+        { -7,  -19, 80,  236, 206, 41, -22, -3 },
+        { -7,  -20, 75,  233, 210, 46, -22, -3 },
+        { -6,  -21, 69,  230, 215, 50, -22, -3 },
+        { -5,  -21, 65,  226, 219, 55, -22, -5 },
+        { -5,  -21, 60,  222, 222, 60, -21, -5 },
+    },
+//>=0.5
+    {
+        { -16, 0,   145, 254, 145, 0,  -16, 0 },
+        { -16, -2,  140, 253, 151, 3,  -17, 0 },
+        { -15, -5,  135, 253, 157, 5,  -18, 0 },
+        { -14, -7,  129, 252, 162, 8,  -18, 0 },
+        { -13, -9,  123, 252, 167, 11, -19, 0 },
+        { -13, -11, 118, 250, 172, 15, -19, 0 },
+        { -12, -12, 112, 250, 177, 18, -20, -1 },
+        { -11, -14, 107, 247, 183, 21, -20, -1 },
+        { -10, -15, 101, 245, 188, 25, -21, -1 },
+        { -9,  -16, 96,  243, 192, 29, -21, -2 },
+        { -8,  -18, 90,  242, 197, 33, -22, -2 },
+        { -8,  -19, 85,  239, 202, 37, -22, -2 },
+        { -7,  -19, 80,  236, 206, 41, -22, -3 },
+        { -7,  -20, 75,  233, 210, 46, -22, -3 },
+        { -6,  -21, 69,  230, 215, 50, -22, -3 },
+        { -5,  -21, 65,  226, 219, 55, -22, -5 },
+        { -5,  -21, 60,  222, 222, 60, -21, -5 },
+    },
+//>=0.33
+    {
+        { -18, 18,  144, 226, 144, 19, -17, -4 },
+        { -17, 16,  139, 226, 148, 21, -17, -4 },
+        { -17, 13,  135, 227, 153, 24, -18, -5 },
+        { -17, 11,  131, 226, 157, 27, -18, -5 },
+        { -17, 9,   126, 225, 161, 30, -17, -5 },
+        { -16, 6,   122, 225, 165, 33, -17, -6 },
+        { -16, 4,   118, 224, 169, 37, -17, -7 },
+        { -16, 2,   113, 224, 173, 40, -17, -7 },
+        { -15, 0,   109, 222, 177, 43, -17, -7 },
+        { -15, -1,  104, 220, 181, 47, -16, -8 },
+        { -14, -3,  100, 218, 185, 51, -16, -9 },
+        { -14, -5,  96,  217, 188, 54, -15, -9 },
+        { -14, -6,  91,  214, 192, 58, -14, -9 },
+        { -13, -7,  87,  212, 195, 62, -14, -10 },
+        { -13, -9,  83,  210, 198, 66, -13, -10 },
+        { -12, -10, 79,  207, 201, 70, -12, -11 },
+        { -12, -11, 74,  205, 205, 74, -11, -12 },
+    },
+//>=0.25
+    {
+        { 14, 66, 113, 133, 113, 66, 14, -7 },
+        { 12, 65, 112, 133, 114, 68, 15, -7 },
+        { 11, 63, 111, 132, 115, 70, 17, -7 },
+        { 10, 62, 110, 132, 116, 71, 18, -7 },
+        { 8,  60, 108, 132, 118, 73, 20, -7 },
+        { 7,  58, 107, 132, 119, 75, 21, -7 },
+        { 6,  56, 106, 132, 120, 76, 23, -7 },
+        { 5,  55, 105, 131, 121, 78, 24, -7 },
+        { 4,  53, 103, 131, 122, 80, 26, -7 },
+        { 3,  51, 102, 131, 122, 81, 28, -6 },
+        { 2,  50, 101, 130, 123, 83, 29, -6 },
+        { 1,  48, 99,  131, 124, 84, 31, -6 },
+        { 0,  46, 98,  129, 125, 86, 33, -5 },
+        { -1, 45, 97,  128, 126, 88, 34, -5 },
+        { -2, 43, 95,  130, 126, 89, 36, -5 },
+        { -3, 41, 94,  128, 127, 91, 38, -4 },
+        { -3, 39, 92,  128, 128, 92, 39, -3 },
+    },
+//others
+    {
+        { 39, 69, 93, 102, 93, 69, 39, 8 },
+        { 38, 68, 92, 102, 93, 70, 40, 9 },
+        { 37, 67, 91, 102, 93, 71, 41, 10 },
+        { 36, 66, 91, 101, 94, 71, 42, 11 },
+        { 35, 65, 90, 102, 94, 72, 43, 11 },
+        { 34, 64, 89, 102, 94, 73, 44, 12 },
+        { 33, 63, 88, 101, 95, 74, 45, 13 },
+        { 32, 62, 88, 100, 95, 75, 46, 14 },
+        { 31, 62, 87, 100, 95, 75, 47, 15 },
+        { 30, 61, 86, 99,  96, 76, 48, 16 },
+        { 29, 60, 86, 98,  96, 77, 49, 17 },
+        { 28, 59, 85, 98,  96, 78, 50, 18 },
+        { 27, 58, 84, 99,  97, 78, 50, 19 },
+        { 26, 57, 83, 99,  97, 79, 51, 20 },
+        { 25, 56, 83, 98,  97, 80, 52, 21 },
+        { 24, 55, 82, 97,  98, 81, 53, 22 },
+        { 23, 54, 81, 98,  98, 81, 54, 23 },
+    }
+};
+
+static RK_S16 g_zme_tap6_coeff[11][17][8] = {
+//>=2.667
+    {
+        { -12,  20, 492,  20, -12,   4,   0,   0},
+        {  -8,   8, 488,  36, -16,   4,   0,   0},
+        {  -4,  -4, 488,  48, -20,   4,   0,   0},
+        {   0, -16, 484,  64, -24,   4,   0,   0},
+        {   0, -24, 476,  80, -28,   8,   0,   0},
+        {   4, -32, 464, 100, -32,   8,   0,   0},
+        {   8, -40, 456, 116, -36,   8,   0,   0},
+        {   8, -48, 448, 136, -40,   8,   0,   0},
+        {  12, -52, 436, 152, -44,   8,   0,   0},
+        {  12, -60, 424, 172, -48,  12,   0,   0},
+        {  12, -64, 412, 192, -52,  12,   0,   0},
+        {  16, -64, 392, 212, -56,  12,   0,   0},
+        {  16, -68, 380, 232, -60,  12,   0,   0},
+        {  16, -68, 360, 248, -60,  16,   0,   0},
+        {  16, -68, 344, 268, -64,  16,   0,   0},
+        {  16, -68, 328, 288, -68,  16,   0,   0},
+        {  16, -68, 308, 308, -68,  16,   0,   0},
+    },
+//>=2
+    {
+        { -20,  40, 468,  40, -20,   4,   0,   0},
+        { -16,  28, 464,  56, -24,   4,   0,   0},
+        { -16,  16, 464,  68, -28,   8,   0,   0},
+        { -12,   4, 460,  84, -32,   8,   0,   0},
+        {  -8,  -4, 452, 100, -36,   8,   0,   0},
+        {  -4, -12, 444, 116, -40,   8,   0,   0},
+        {  -4, -24, 440, 136, -44,   8,   0,   0},
+        {   0, -32, 432, 152, -48,   8,   0,   0},
+        {   0, -36, 416, 168, -48,  12,   0,   0},
+        {   4, -44, 408, 184, -52,  12,   0,   0},
+        {   4, -48, 400, 200, -56,  12,   0,   0},
+        {   8, -52, 380, 220, -56,  12,   0,   0},
+        {   8, -56, 372, 236, -60,  12,   0,   0},
+        {   8, -60, 356, 256, -60,  12,   0,   0},
+        {  12, -60, 340, 268, -60,  12,   0,   0},
+        {  12, -60, 324, 288, -64,  12,   0,   0},
+        {  12, -64, 308, 308, -64,  12,   0,   0},
+    },
+//>=1.5
+    {
+        { -28,  60, 440,  60, -28,   8,   0,   0},
+        { -28,  48, 440,  76, -32,   8,   0,   0},
+        { -24,  36, 440,  88, -36,   8,   0,   0},
+        { -20,  28, 432, 104, -40,   8,   0,   0},
+        { -16,  16, 428, 116, -40,   8,   0,   0},
+        { -16,   4, 428, 132, -44,   8,   0,   0},
+        { -12,  -4, 420, 148, -48,   8,   0,   0},
+        {  -8, -12, 408, 164, -48,   8,   0,   0},
+        {  -8, -20, 404, 180, -52,   8,   0,   0},
+        {  -4, -24, 388, 196, -52,   8,   0,   0},
+        {  -4, -32, 384, 212, -56,   8,   0,   0},
+        {   0, -36, 372, 224, -56,   8,   0,   0},
+        {   0, -40, 360, 240, -56,   8,   0,   0},
+        {   4, -44, 344, 256, -56,   8,   0,   0},
+        {   4, -48, 332, 272, -56,   8,   0,   0},
+        {   4, -52, 316, 292, -56,   8,   0,   0},
+        {   8, -52, 300, 300, -52,   8,   0,   0},
+    },
+//>1
+    {
+        { -36,  80, 420,  80, -36,   4,   0,   0},
+        { -32,  68, 412,  92, -36,   8,   0,   0},
+        { -28,  56, 412, 104, -40,   8,   0,   0},
+        { -28,  44, 412, 116, -40,   8,   0,   0},
+        { -24,  36, 404, 132, -44,   8,   0,   0},
+        { -24,  24, 404, 144, -44,   8,   0,   0},
+        { -20,  16, 396, 160, -48,   8,   0,   0},
+        { -16,   8, 388, 172, -48,   8,   0,   0},
+        { -16,   0, 380, 188, -48,   8,   0,   0},
+        { -12,  -8, 376, 200, -48,   4,   0,   0},
+        { -12, -12, 364, 216, -48,   4,   0,   0},
+        {  -8, -20, 356, 228, -48,   4,   0,   0},
+        {  -8, -24, 344, 244, -48,   4,   0,   0},
+        {  -4, -32, 332, 260, -48,   4,   0,   0},
+        {  -4, -36, 320, 272, -44,   4,   0,   0},
+        {   0, -40, 308, 288, -44,   0,   0,   0},
+        {   0, -40, 296, 296, -40,   0,   0,   0},
+    },
+//==1
+    {
+        {  0,   0, 511,   0,   0,  0, 0, 0 },
+        { 3,   -12,  511,  13,   -3,   0, 0, 0 },
+        { 6,   -22,  507,  28,   -7,   0, 0, 0 },
+        { 8,   -32,  502,  44,   -11,  1, 0, 0 },
+        { 10,  -40,  495,  61,   -15,  1, 0, 0 },
+        { 11,  -47,  486,  79,   -19,  2, 0, 0 },
+        { 12,  -53,  476,  98,   -24,  3, 0, 0 },
+        { 13,  -58,  464,  117,  -28,  4, 0, 0 },
+        { 14,  -62,  451,  137,  -33,  5, 0, 0 },
+        { 15,  -65,  437,  157,  -38,  6, 0, 0 },
+        { 15,  -67,  420,  179,  -42,  7, 0, 0 },
+        { 15,  -68,  404,  200,  -46,  7, 0, 0 },
+        { 14,  -68,  386,  221,  -50,  9, 0, 0 },
+        { 14,  -68,  367,  243,  -54,  10, 0, 0 },
+        { 14,  -67,  348,  264,  -58,  11, 0, 0 },
+        { 13,  -66,  328,  286,  -61,  12, 0, 0 },
+        { 13,  -63,  306,  306,  -63,  13, 0, 0 },
+    },
+//>=0.833
+    {
+        { -31, 104, 362, 104, -31, 4,  0, 0 },
+        { -30, 94,  362, 114, -32, 4,  0, 0 },
+        { -29, 84,  361, 125, -32, 3,  0, 0 },
+        { -28, 75,  359, 136, -33, 3,  0, 0 },
+        { -27, 66,  356, 147, -33, 3,  0, 0 },
+        { -25, 57,  353, 158, -33, 2,  0, 0 },
+        { -24, 49,  349, 169, -33, 2,  0, 0 },
+        { -22, 41,  344, 180, -32, 1,  0, 0 },
+        { -20, 33,  339, 191, -31, 0,  0, 0 },
+        { -19, 26,  333, 203, -30, -1, 0, 0 },
+        { -17, 19,  327, 214, -29, -2, 0, 0 },
+        { -16, 13,  320, 225, -27, -3, 0, 0 },
+        { -14, 7,   312, 236, -25, -4, 0, 0 },
+        { -13, 1,   305, 246, -22, -5, 0, 0 },
+        { -11, -4,  295, 257, -19, -6, 0, 0 },
+        { -10, -8,  286, 267, -16, -7, 0, 0 },
+        { -9,  -12, 277, 277, -12, -9, 0, 0 },
+    },
+//>=0.7
+    {
+        { -31, 104, 362, 104, -31, 4,  0, 0 },
+        { -30, 94,  362, 114, -32, 4,  0, 0 },
+        { -29, 84,  361, 125, -32, 3,  0, 0 },
+        { -28, 75,  359, 136, -33, 3,  0, 0 },
+        { -27, 66,  356, 147, -33, 3,  0, 0 },
+        { -25, 57,  353, 158, -33, 2,  0, 0 },
+        { -24, 49,  349, 169, -33, 2,  0, 0 },
+        { -22, 41,  344, 180, -32, 1,  0, 0 },
+        { -20, 33,  339, 191, -31, 0,  0, 0 },
+        { -19, 26,  333, 203, -30, -1, 0, 0 },
+        { -17, 19,  327, 214, -29, -2, 0, 0 },
+        { -16, 13,  320, 225, -27, -3, 0, 0 },
+        { -14, 7,   312, 236, -25, -4, 0, 0 },
+        { -13, 1,   305, 246, -22, -5, 0, 0 },
+        { -11, -4,  295, 257, -19, -6, 0, 0 },
+        { -10, -8,  286, 267, -16, -7, 0, 0 },
+        { -9,  -12, 277, 277, -12, -9, 0, 0 },
+    },
+//>=0.5
+    {
+        { -20, 130, 297, 130, -20, -5,  0, 0 },
+        { -21, 122, 298, 138, -19, -6,  0, 0 },
+        { -22, 115, 297, 146, -17, -7,  0, 0 },
+        { -22, 108, 296, 153, -16, -7,  0, 0 },
+        { -23, 101, 295, 161, -14, -8,  0, 0 },
+        { -23, 93,  294, 169, -12, -9,  0, 0 },
+        { -24, 87,  292, 177, -10, -10, 0, 0 },
+        { -24, 80,  289, 185, -7,  -11, 0, 0 },
+        { -24, 73,  286, 193, -4,  -12, 0, 0 },
+        { -23, 66,  283, 200, -1,  -13, 0, 0 },
+        { -23, 60,  279, 208, 2,   -14, 0, 0 },
+        { -23, 54,  276, 215, 5,   -15, 0, 0 },
+        { -22, 48,  271, 222, 9,   -16, 0, 0 },
+        { -21, 42,  266, 229, 13,  -17, 0, 0 },
+        { -21, 37,  261, 236, 17,  -18, 0, 0 },
+        { -21, 32,  255, 242, 22,  -18, 0, 0 },
+        { -20, 27,  249, 249, 27,  -20, 0, 0 },
+    },
+//>=0.33
+    {
+        { 16, 136, 217, 136, 16, -9,  0, 0 },
+        { 13, 132, 217, 141, 18, -9,  0, 0 },
+        { 11, 128, 217, 145, 21, -10, 0, 0 },
+        { 9,  124, 216, 149, 24, -10, 0, 0 },
+        { 7,  119, 216, 153, 27, -10, 0, 0 },
+        { 5,  115, 216, 157, 30, -11, 0, 0 },
+        { 3,  111, 215, 161, 33, -11, 0, 0 },
+        { 1,  107, 214, 165, 36, -11, 0, 0 },
+        { 0,  102, 213, 169, 39, -11, 0, 0 },
+        { -2, 98,  211, 173, 43, -11, 0, 0 },
+        { -3, 94,  209, 177, 46, -11, 0, 0 },
+        { -4, 90,  207, 180, 50, -11, 0, 0 },
+        { -5, 85,  206, 184, 53, -11, 0, 0 },
+        { -6, 81,  203, 187, 57, -10, 0, 0 },
+        { -7, 77,  201, 190, 61, -10, 0, 0 },
+        { -8, 73,  198, 193, 65, -9,  0, 0 },
+        { -9, 69,  196, 196, 69, -9,  0, 0 },
+    },
+//>=0.25
+    {
+        { 66, 115, 138, 115, 66, 12, 0, 0 },
+        { 64, 114, 136, 116, 68, 14, 0, 0 },
+        { 63, 113, 134, 117, 70, 15, 0, 0 },
+        { 61, 111, 135, 118, 71, 16, 0, 0 },
+        { 59, 110, 133, 119, 73, 18, 0, 0 },
+        { 57, 108, 134, 120, 74, 19, 0, 0 },
+        { 55, 107, 133, 121, 76, 20, 0, 0 },
+        { 53, 105, 133, 121, 78, 22, 0, 0 },
+        { 51, 104, 133, 122, 79, 23, 0, 0 },
+        { 49, 102, 132, 123, 81, 25, 0, 0 },
+        { 47, 101, 132, 124, 82, 26, 0, 0 },
+        { 45, 99,  131, 125, 84, 28, 0, 0 },
+        { 44, 98,  130, 125, 85, 30, 0, 0 },
+        { 42, 96,  130, 126, 87, 31, 0, 0 },
+        { 40, 95,  128, 127, 89, 33, 0, 0 },
+        { 38, 93,  129, 127, 90, 35, 0, 0 },
+        { 36, 92,  128, 128, 92, 36, 0, 0 },
+    },
+//others
+    {
+        { 80, 105, 116, 105, 80, 26, 0, 0 },
+        { 79, 104, 115, 105, 81, 28, 0, 0 },
+        { 77, 103, 116, 106, 81, 29, 0, 0 },
+        { 76, 102, 115, 106, 82, 31, 0, 0 },
+        { 74, 101, 115, 106, 83, 33, 0, 0 },
+        { 73, 100, 114, 106, 84, 35, 0, 0 },
+        { 71, 99,  114, 107, 84, 37, 0, 0 },
+        { 70, 98,  113, 107, 85, 39, 0, 0 },
+        { 68, 98,  113, 107, 86, 40, 0, 0 },
+        { 67, 97,  112, 108, 86, 42, 0, 0 },
+        { 65, 96,  112, 108, 87, 44, 0, 0 },
+        { 63, 95,  112, 108, 88, 46, 0, 0 },
+        { 62, 94,  112, 108, 88, 48, 0, 0 },
+        { 60, 93,  111, 109, 89, 50, 0, 0 },
+        { 58, 93,  111, 109, 90, 51, 0, 0 },
+        { 57, 92,  110, 110, 90, 53, 0, 0 },
+        { 55, 91,  110, 110, 91, 55, 0, 0 },
+    }
+};
+
+static MPP_RET calc_scl_factor(struct zme_params* src_params, scl_info *p_scl_info, RK_U8 bypass_en)
+{
+    RK_U16 act_width  = p_scl_info->act_width;
+    RK_U16 dsp_width  = p_scl_info->dsp_width;
+
+    RK_U16 act_height = p_scl_info->act_height;
+    RK_U16 dsp_height = p_scl_info->dsp_height;
+
+    RK_U8  xsd_en     = 0;
+    RK_U8  xsu_en     = 0;
+    RK_U8  xscl_mode  = p_scl_info->xscl_mode;
+    RK_U16 xscl_factor;
+    RK_U8  xscl_offset = 0;
+
+    RK_U8  ysd_en     = 0;
+    RK_U8  ysu_en     = 0;
+    RK_U8  yscl_mode  = p_scl_info->yscl_mode;
+    RK_U16 yscl_factor;
+    RK_U8  yscl_offset = 0;
+
+    RK_U8  xavg_en    = 0;
+    RK_U8  xgt_en     = 0;
+    RK_U8  xgt_mode   = 0;
+
+    RK_U8  yavg_en    = 0;
+    RK_U8  ygt_en     = 0;
+    RK_U8  ygt_mode   = 0;
+
+    RK_U32 f_xscl_factor_t;
+    RK_U32 f_yscl_factor_t;
+    RK_U32 f_xscl_factor_t1;
+    RK_U32 f_yscl_factor_t1;
+
+    if (act_width >= dsp_width * 14) {
+        act_width = act_width / 4;
+        xgt_en     = 1;
+        xgt_mode   = 3;
+    } else if (act_width >= dsp_width * 7) {
+        act_width = act_width / 2;
+        xgt_en     = 1;
+        xgt_mode   = 1;
+    }
+
+    if (act_width > dsp_width) {
+        xsd_en     = 1;
+        xsu_en     = 0;
+        xscl_factor = GET_SCALE_FACTOR_DN(act_width, dsp_width);
+    } else if (act_width < dsp_width) {
+        xsd_en     = 0;
+        xsu_en     = 1;
+        xscl_factor = GET_SCALE_FACTOR_UP(act_width, dsp_width);
+    } else {
+        xsd_en     = 0;
+        xsu_en     = 0;
+        xscl_factor = 1 << 12;
+    }
+
+    if (yscl_mode <= SCL_BIL) {
+        if (act_height > dsp_height * 4) {
+            ygt_en   = 1;
+            ygt_mode = 1;
+            act_height = act_height / 4;
+        } else if (act_height > dsp_height * 2) {
+            ygt_en   = 1;
+            ygt_mode = 0;
+            act_height = act_height / 2;
+        } else {
+            ygt_en   = 0;
+            ygt_mode = 0;
+        }
+    }
+
+    if (yscl_mode == SCL_MPH) {
+        if (act_height >= dsp_height * 6) {
+            ygt_en = 1;
+            ygt_mode = 3;
+        }
+    }
+
+    if (act_height > dsp_height) {
+        ysd_en     = 1;
+        ysu_en     = 0;
+        yscl_factor = GET_SCALE_FACTOR_DN(act_height, dsp_height);
+    } else if (act_height < dsp_height) {
+        ysd_en     = 0;
+        ysu_en     = 1;
+        yscl_factor = GET_SCALE_FACTOR_UP(act_height, dsp_height);
+    } else {
+        ysd_en     = 0;
+        ysu_en     = 0;
+        yscl_factor = 1 << 12;
+    }
+
+    if (xsu_en == 1) {
+        f_xscl_factor_t = (1 << 16) * act_width / dsp_width;
+        f_xscl_factor_t1 = 1000 * (1 << 16) / f_xscl_factor_t;
+    } else {
+        f_xscl_factor_t = (1 << 12) * act_width / dsp_width;
+        f_xscl_factor_t1 = 1000 * (1 << 12) / f_xscl_factor_t;
+    }
+
+    if (ysu_en == 1) {
+        f_yscl_factor_t = (1 << 16) * act_height / dsp_height;
+        f_yscl_factor_t1 = 1000 * (1 << 16) / f_yscl_factor_t;
+    } else {
+        f_yscl_factor_t = (1 << 12) * act_height / dsp_height;
+        f_yscl_factor_t1 = 1000 * (1 << 12) / f_yscl_factor_t;
+    }
+
+    if (f_xscl_factor_t1 >= vdpp_scale_threshold[0])
+        p_scl_info->xscl_zme_coe = src_params->zme_tap8_coeff[0];
+    else if (f_xscl_factor_t1 >= vdpp_scale_threshold[1])
+        p_scl_info->xscl_zme_coe = src_params->zme_tap8_coeff[1];
+    else if (f_xscl_factor_t1 >= vdpp_scale_threshold[2])
+        p_scl_info->xscl_zme_coe = src_params->zme_tap8_coeff[2];
+    else if (f_xscl_factor_t1 > vdpp_scale_threshold[3])
+        p_scl_info->xscl_zme_coe = src_params->zme_tap8_coeff[3];
+    else if (f_xscl_factor_t1 == vdpp_scale_threshold[3])
+        p_scl_info->xscl_zme_coe = src_params->zme_tap8_coeff[4];
+    else if (f_xscl_factor_t1 >= vdpp_scale_threshold[4])
+        p_scl_info->xscl_zme_coe = src_params->zme_tap8_coeff[5];
+    else if (f_xscl_factor_t1 >= vdpp_scale_threshold[5])
+        p_scl_info->xscl_zme_coe = src_params->zme_tap8_coeff[6];
+    else if (f_xscl_factor_t1 >= vdpp_scale_threshold[6])
+        p_scl_info->xscl_zme_coe = src_params->zme_tap8_coeff[7];
+    else if (f_xscl_factor_t1 >= vdpp_scale_threshold[7])
+        p_scl_info->xscl_zme_coe = src_params->zme_tap8_coeff[8];
+    else if (f_xscl_factor_t1 >= vdpp_scale_threshold[8])
+        p_scl_info->xscl_zme_coe = src_params->zme_tap8_coeff[9];
+    else
+        p_scl_info->xscl_zme_coe = src_params->zme_tap8_coeff[10];
+
+    if (f_yscl_factor_t1 >= vdpp_scale_threshold[0])
+        p_scl_info->yscl_zme_coe = src_params->zme_tap6_coeff[0];
+    else if (f_yscl_factor_t1 >= vdpp_scale_threshold[1])
+        p_scl_info->yscl_zme_coe = src_params->zme_tap6_coeff[1];
+    else if (f_yscl_factor_t1 >= vdpp_scale_threshold[2])
+        p_scl_info->yscl_zme_coe = src_params->zme_tap6_coeff[2];
+    else if (f_yscl_factor_t1 > vdpp_scale_threshold[3])
+        p_scl_info->yscl_zme_coe = src_params->zme_tap6_coeff[3];
+    else if (f_yscl_factor_t1 == vdpp_scale_threshold[3])
+        p_scl_info->yscl_zme_coe = src_params->zme_tap6_coeff[4];
+    else if (f_yscl_factor_t1 >= vdpp_scale_threshold[4])
+        p_scl_info->yscl_zme_coe = src_params->zme_tap6_coeff[5];
+    else if (f_yscl_factor_t1 >= vdpp_scale_threshold[5])
+        p_scl_info->yscl_zme_coe = src_params->zme_tap6_coeff[6];
+    else if (f_yscl_factor_t1 >= vdpp_scale_threshold[6])
+        p_scl_info->yscl_zme_coe = src_params->zme_tap6_coeff[7];
+    else if (f_yscl_factor_t1 >= vdpp_scale_threshold[7])
+        p_scl_info->yscl_zme_coe = src_params->zme_tap6_coeff[8];
+    else if (f_yscl_factor_t1 >= vdpp_scale_threshold[8])
+        p_scl_info->yscl_zme_coe = src_params->zme_tap6_coeff[9];
+    else
+        p_scl_info->yscl_zme_coe = src_params->zme_tap6_coeff[10];
+
+    p_scl_info->xsd_en     = xsd_en;
+    p_scl_info->xsu_en     = xsu_en;
+    p_scl_info->xscl_mode  = xscl_mode;
+    p_scl_info->xscl_factor = xscl_factor;
+    p_scl_info->xscl_offset = xscl_offset;
+
+    p_scl_info->ysd_en     = ysd_en;
+    p_scl_info->ysu_en     = ysu_en;
+    p_scl_info->yscl_mode  = yscl_mode;
+    p_scl_info->yscl_factor = yscl_factor;
+    p_scl_info->yscl_offset = yscl_offset;
+
+    p_scl_info->xavg_en    = xavg_en;
+    p_scl_info->xgt_en     = xgt_en;
+    p_scl_info->xgt_mode   = xgt_mode;
+
+    p_scl_info->yavg_en    = yavg_en;
+    p_scl_info->ygt_en     = ygt_en;
+    p_scl_info->ygt_mode   = ygt_mode;
+
+    if (bypass_en) {
+        p_scl_info->xsd_bypass = !xsd_en;
+        p_scl_info->xsu_bypass = !xsu_en;
+        p_scl_info->ys_bypass = !(ysd_en || ysu_en);
+    } else {
+        p_scl_info->xsd_bypass = 0;
+        p_scl_info->xsu_bypass = 0;
+        p_scl_info->ys_bypass = 0;
+    }
+    return MPP_OK;
+}
+
+void set_dmsr_to_vdpp_reg(struct dmsr_params* p_dmsr_param, struct dmsr_reg* dmsr)
+{
+    /* 0x0080(reg0) */
+    dmsr->reg0.sw_dmsr_edge_low_thre_0 = p_dmsr_param->dmsr_edge_th_low_arr[0];
+    dmsr->reg0.sw_dmsr_edge_high_thre_0 = p_dmsr_param->dmsr_edge_th_high_arr[0];
+
+    /* 0x0084(reg1) */
+    dmsr->reg1.sw_dmsr_edge_low_thre_1 = p_dmsr_param->dmsr_edge_th_low_arr[1];
+    dmsr->reg1.sw_dmsr_edge_high_thre_1 = p_dmsr_param->dmsr_edge_th_high_arr[1];
+
+    /* 0x0088(reg2) */
+    dmsr->reg2.sw_dmsr_edge_low_thre_2 = p_dmsr_param->dmsr_edge_th_low_arr[2];
+    dmsr->reg2.sw_dmsr_edge_high_thre_2 = p_dmsr_param->dmsr_edge_th_high_arr[2];
+
+    /* 0x008C(reg3) */
+    dmsr->reg3.sw_dmsr_edge_low_thre_3 = p_dmsr_param->dmsr_edge_th_low_arr[3];
+    dmsr->reg3.sw_dmsr_edge_high_thre_3 = p_dmsr_param->dmsr_edge_th_high_arr[3];
+
+    /* 0x0090(reg4) */
+    dmsr->reg4.sw_dmsr_edge_low_thre_4 = p_dmsr_param->dmsr_edge_th_low_arr[4];
+    dmsr->reg4.sw_dmsr_edge_high_thre_4 = p_dmsr_param->dmsr_edge_th_high_arr[4];
+
+    /* 0x0094(reg5) */
+    dmsr->reg5.sw_dmsr_edge_low_thre_5 = p_dmsr_param->dmsr_edge_th_low_arr[5];
+    dmsr->reg5.sw_dmsr_edge_high_thre_5 = p_dmsr_param->dmsr_edge_th_high_arr[5];
+
+    /* 0x0098(reg6) */
+    dmsr->reg6.sw_dmsr_edge_low_thre_6 = p_dmsr_param->dmsr_edge_th_low_arr[6];
+    dmsr->reg6.sw_dmsr_edge_high_thre_6 = p_dmsr_param->dmsr_edge_th_high_arr[6];
+    {
+        RK_U16 adj_mapping_k[7];
+        RK_U16 tmp_diff;
+        RK_U16 i;
+        RK_U16 contrast2conf_mapping_k;
+        RK_U32 tmp_diff_y, tmp_diff_x;
+
+        for (i = 0; i < 7; i++) {
+            tmp_diff =  p_dmsr_param->dmsr_edge_th_high_arr[i] - p_dmsr_param->dmsr_edge_th_low_arr[i];
+            adj_mapping_k[i] = (65535 / MPP_MAX(1, tmp_diff));
+        }
+        tmp_diff_y = p_dmsr_param->dmsr_contrast_to_conf_map_y1 - p_dmsr_param->dmsr_contrast_to_conf_map_y0;
+        tmp_diff_x = MPP_MAX(p_dmsr_param->dmsr_contrast_to_conf_map_x1 - p_dmsr_param->dmsr_contrast_to_conf_map_x0, 1);
+
+        contrast2conf_mapping_k = mpp_clip(256 * tmp_diff_y / tmp_diff_x, 0, 65535);
+        /* 0x009C(reg7) */
+        dmsr->reg7.sw_dmsr_edge_k_0 = adj_mapping_k[0];
+        dmsr->reg7.sw_dmsr_edge_k_1 = adj_mapping_k[1];
+
+        /* 0x00A0(reg8) */
+        dmsr->reg8.sw_dmsr_edge_k_2 = adj_mapping_k[2];
+        dmsr->reg8.sw_dmsr_edge_k_3 = adj_mapping_k[3];
+
+        /* 0x00A4(reg9) */
+        dmsr->reg9.sw_dmsr_edge_k_4 = adj_mapping_k[4];
+        dmsr->reg9.sw_dmsr_edge_k_5 = adj_mapping_k[5];
+
+        /* 0x00A8(reg10) */
+        dmsr->reg10.sw_dmsr_edge_k_6 = adj_mapping_k[6];
+        dmsr->reg10.sw_dmsr_dir_contrast_conf_f = contrast2conf_mapping_k;
+    }
+    /* 0x00AC(reg11) */
+    dmsr->reg11.sw_dmsr_dir_contrast_conf_x0 = p_dmsr_param->dmsr_contrast_to_conf_map_x0;
+    dmsr->reg11.sw_dmsr_dir_contrast_conf_x1 = p_dmsr_param->dmsr_contrast_to_conf_map_x1;
+
+    /* 0x00B0(reg12) */
+    dmsr->reg12.sw_dmsr_dir_contrast_conf_y0 = p_dmsr_param->dmsr_contrast_to_conf_map_y0;
+    dmsr->reg12.sw_dmsr_dir_contrast_conf_y1 = p_dmsr_param->dmsr_contrast_to_conf_map_y1;
+
+    /* 0x00B4(reg13) */
+    dmsr->reg13.sw_dmsr_var_th = p_dmsr_param->dmsr_blk_flat_th;
+
+    /* 0x00B8(reg14) */
+    dmsr->reg14.sw_dmsr_diff_coring_th0 = p_dmsr_param->dmsr_diff_core_th0;
+    dmsr->reg14.sw_dmsr_diff_coring_th1 = p_dmsr_param->dmsr_diff_core_th1;
+
+    /* 0x00BC(reg15) */
+    dmsr->reg15.sw_dmsr_diff_coring_wgt0 = p_dmsr_param->dmsr_diff_core_wgt0;
+    dmsr->reg15.sw_dmsr_diff_coring_wgt1 = p_dmsr_param->dmsr_diff_core_wgt1;
+    dmsr->reg15.sw_dmsr_diff_coring_wgt2 = p_dmsr_param->dmsr_diff_core_wgt2;
+    {
+        RK_U16 diff_coring_y0 = p_dmsr_param->dmsr_diff_core_th0 * p_dmsr_param->dmsr_diff_core_wgt0;
+        RK_U16 diff_coring_y1 = ((p_dmsr_param->dmsr_diff_core_th1 - p_dmsr_param->dmsr_diff_core_th0) * p_dmsr_param->dmsr_diff_core_wgt1) + diff_coring_y0;
+        /* 0x00C0(reg16) */
+        dmsr->reg16.sw_dmsr_diff_coring_y0 = diff_coring_y0;
+        dmsr->reg16.sw_dmsr_diff_coring_y1 = diff_coring_y1;
+    }
+    /* 0x00C4(reg17) */
+    dmsr->reg17.sw_dmsr_wgt_pri_gain_1_odd = p_dmsr_param->dmsr_wgt_pri_gain_odd_1;
+    dmsr->reg17.sw_dmsr_wgt_pri_gain_1_even = p_dmsr_param->dmsr_wgt_pri_gain_even_1;
+    dmsr->reg17.sw_dmsr_wgt_pri_gain_2_odd = p_dmsr_param->dmsr_wgt_pri_gain_odd_2;
+    dmsr->reg17.sw_dmsr_wgt_pri_gain_2_even = p_dmsr_param->dmsr_wgt_pri_gain_even_2;
+
+    /* 0x00C8(reg18) */
+    dmsr->reg18.sw_dmsr_wgt_sec_gain_1 = p_dmsr_param->dmsr_wgt_sec_gain;
+    dmsr->reg18.sw_dmsr_wgt_sec_gain_2 = p_dmsr_param->dmsr_wgt_sec_gain * 2;
+
+    /* 0x00CC(reg19) */
+    dmsr->reg19.sw_dmsr_strength_pri = p_dmsr_param->dmsr_str_pri_y;
+    dmsr->reg19.sw_dmsr_strength_sec = p_dmsr_param->dmsr_str_sec_y;
+    dmsr->reg19.sw_dmsr_dump = p_dmsr_param->dmsr_dumping_y;
+}
+
+void vdpp_set_default_zme_param(struct zme_params* param)
+{
+    param->zme_bypass_en = 1;
+    param->zme_dering_enable = 1;
+    param->zme_dering_sen_0 = 16;
+    param->zme_dering_sen_1 = 4;
+    param->zme_dering_blend_alpha = 16;
+    param->zme_dering_blend_beta = 13;
+    param->zme_tap8_coeff = g_zme_tap8_coeff;
+    param->zme_tap6_coeff = g_zme_tap6_coeff;
+}
+
+
+void set_zme_to_vdpp_reg(struct zme_params *zme_params, struct zme_reg *zme)
+{
+    /* 0x00D0(reg20), debug settings, skip */
+    /* 3. set reg::zme */
+    /* 3.1 set reg::zme::common */
+    enum ZME_FMT zme_format_in = FMT_YCbCr420_888;
+    scl_info yrgb_scl_info = {0};
+    scl_info cbcr_scl_info = {0};
+
+    yrgb_scl_info.act_width = zme_params->src_width;
+    yrgb_scl_info.act_height = zme_params->src_height;
+    yrgb_scl_info.dsp_width = zme_params->dst_width;
+    yrgb_scl_info.dsp_height = zme_params->dst_height;
+    yrgb_scl_info.xscl_mode = SCL_MPH;
+    yrgb_scl_info.yscl_mode = SCL_MPH;
+    yrgb_scl_info.dering_en = zme_params->zme_dering_enable;
+    calc_scl_factor(zme_params, &yrgb_scl_info, zme_params->zme_bypass_en);
+
+    if (zme_format_in == FMT_YCbCr420_888) {
+        cbcr_scl_info.act_width = zme_params->src_width / 2;
+        cbcr_scl_info.act_height = zme_params->src_height / 2;
+    } else {
+        /* only support yuv420 as input */
+    }
+
+    if (zme_params->dst_fmt == VDPP_FMT_YUV444) {
+        if (!zme_params->yuv_out_diff) {
+            cbcr_scl_info.dsp_width = zme_params->dst_width;
+            cbcr_scl_info.dsp_height = zme_params->dst_height;
+        } else {
+            cbcr_scl_info.dsp_width = zme_params->dst_c_width;
+            cbcr_scl_info.dsp_height = zme_params->dst_c_height;
+        }
+    } else if (zme_params->dst_fmt == VDPP_FMT_YUV420) {
+        if (!zme_params->yuv_out_diff) {
+            cbcr_scl_info.dsp_width = zme_params->dst_width / 2;
+            cbcr_scl_info.dsp_height = zme_params->dst_height / 2;
+        } else {
+            cbcr_scl_info.dsp_width = zme_params->dst_c_width / 2;
+            cbcr_scl_info.dsp_height = zme_params->dst_c_height / 2;
+        }
+    } else {
+        /* not supported */
+    }
+    cbcr_scl_info.xscl_mode = SCL_MPH;
+    cbcr_scl_info.yscl_mode = SCL_MPH;
+    cbcr_scl_info.dering_en = zme_params->zme_dering_enable;
+    calc_scl_factor(zme_params, &cbcr_scl_info, zme_params->zme_bypass_en);
+
+    /* 0x0800(reg0) */
+    zme->common.reg0.bypass_en = 0;
+    zme->common.reg0.align_en = 0;
+    zme->common.reg0.format_in = FMT_YCbCr420_888;
+    if (zme_params->dst_fmt == VDPP_FMT_YUV444)
+        zme->common.reg0.format_out = FMT_YCbCr444_888;
+    else
+        zme->common.reg0.format_out = FMT_YCbCr420_888;
+    zme->common.reg0.auto_gating_en = 1;
+
+    /* 0x0804 ~ 0x0808(reg1 ~ reg2), skip */
+
+    /* 0x080C(reg3), not used */
+    zme->common.reg3.vir_width = zme_params->src_width;
+    zme->common.reg3.vir_height = zme_params->src_height;
+
+    /* 0x0810(reg4) */
+    zme->common.reg4.yrgb_xsd_en = yrgb_scl_info.xsd_en;
+    zme->common.reg4.yrgb_xsu_en = yrgb_scl_info.xsu_en;
+    zme->common.reg4.yrgb_scl_mode = yrgb_scl_info.xscl_mode;
+    zme->common.reg4.yrgb_ysd_en = yrgb_scl_info.ysd_en;
+    zme->common.reg4.yrgb_ysu_en = yrgb_scl_info.ysu_en;
+    zme->common.reg4.yrgb_yscl_mode = yrgb_scl_info.yscl_mode;
+    zme->common.reg4.yrgb_dering_en = yrgb_scl_info.dering_en;
+    zme->common.reg4.yrgb_gt_en = yrgb_scl_info.ygt_en;
+    zme->common.reg4.yrgb_gt_mode = yrgb_scl_info.ygt_mode;
+    zme->common.reg4.yrgb_xgt_en = yrgb_scl_info.xgt_en;
+    zme->common.reg4.yrgb_xgt_mode = yrgb_scl_info.xgt_mode;
+    zme->common.reg4.yrgb_xsd_bypass = yrgb_scl_info.xsd_bypass;
+    zme->common.reg4.yrgb_ys_bypass = yrgb_scl_info.ys_bypass;
+    zme->common.reg4.yrgb_xsu_bypass = yrgb_scl_info.xsu_bypass;
+
+    /* 0x0814(reg5) */
+    zme->common.reg5.yrgb_src_width = yrgb_scl_info.act_width - 1;
+    zme->common.reg5.yrgb_src_height = yrgb_scl_info.act_height - 1;
+
+    /* 0x0818(reg6) */
+    zme->common.reg6.yrgb_dst_width = yrgb_scl_info.dsp_width - 1;
+    zme->common.reg6.yrgb_dst_height = yrgb_scl_info.dsp_height - 1;
+
+    /* 0x081C(reg7) */
+    zme->common.reg7.yrgb_dering_sen0 = zme_params->zme_dering_sen_0;
+    zme->common.reg7.yrgb_dering_sen1 = zme_params->zme_dering_sen_1;
+    zme->common.reg7.yrgb_dering_alpha = zme_params->zme_dering_blend_alpha;
+    zme->common.reg7.yrgb_dering_delta = zme_params->zme_dering_blend_beta;
+
+    /* 0x0820(reg8) */
+    zme->common.reg8.yrgb_xscl_factor = yrgb_scl_info.xscl_factor;
+    zme->common.reg8.yrgb_xscl_offset = yrgb_scl_info.xscl_offset;
+
+    /* 0x0824(reg9) */
+    zme->common.reg9.yrgb_yscl_factor = yrgb_scl_info.yscl_factor;
+    zme->common.reg9.yrgb_yscl_offset = yrgb_scl_info.yscl_offset;
+
+    /* 0x0828 ~ 0x082C(reg10 ~ reg11), skip */
+
+    /* 0x0830(reg12) */
+    zme->common.reg12.cbcr_xsd_en = cbcr_scl_info.xsd_en;
+    zme->common.reg12.cbcr_xsu_en = cbcr_scl_info.xsu_en;
+    zme->common.reg12.cbcr_scl_mode = cbcr_scl_info.xscl_mode;
+    zme->common.reg12.cbcr_ysd_en = cbcr_scl_info.ysd_en;
+    zme->common.reg12.cbcr_ysu_en = cbcr_scl_info.ysu_en;
+    zme->common.reg12.cbcr_yscl_mode = cbcr_scl_info.yscl_mode;
+    zme->common.reg12.cbcr_dering_en = cbcr_scl_info.dering_en;
+    zme->common.reg12.cbcr_gt_en = cbcr_scl_info.ygt_en;
+    zme->common.reg12.cbcr_gt_mode = cbcr_scl_info.ygt_mode;
+    zme->common.reg12.cbcr_xgt_en = cbcr_scl_info.xgt_en;
+    zme->common.reg12.cbcr_xgt_mode = cbcr_scl_info.xgt_mode;
+    zme->common.reg12.cbcr_xsd_bypass = cbcr_scl_info.xsd_bypass;
+    zme->common.reg12.cbcr_ys_bypass = cbcr_scl_info.ys_bypass;
+    zme->common.reg12.cbcr_xsu_bypass = cbcr_scl_info.xsu_bypass;
+
+    /* 0x0834(reg13) */
+    zme->common.reg13.cbcr_src_width = cbcr_scl_info.act_width - 1;
+    zme->common.reg13.cbcr_src_height = cbcr_scl_info.act_height - 1;
+
+    /* 0x0838(reg14) */
+    zme->common.reg14.cbcr_dst_width = cbcr_scl_info.dsp_width - 1;
+    zme->common.reg14.cbcr_dst_height = cbcr_scl_info.dsp_height - 1;
+
+    /* 0x083C(reg15) */
+    zme->common.reg15.cbcr_dering_sen0 = zme_params->zme_dering_sen_0;
+    zme->common.reg15.cbcr_dering_sen1 = zme_params->zme_dering_sen_1;
+    zme->common.reg15.cbcr_dering_alpha = zme_params->zme_dering_blend_alpha;
+    zme->common.reg15.cbcr_dering_delta = zme_params->zme_dering_blend_beta;
+
+    /* 0x0840(reg16) */
+    zme->common.reg16.cbcr_xscl_factor = cbcr_scl_info.xscl_factor;
+    zme->common.reg16.cbcr_xscl_offset = cbcr_scl_info.xscl_offset;
+
+    /* 0x0844(reg17) */
+    zme->common.reg17.cbcr_yscl_factor = cbcr_scl_info.yscl_factor;
+    zme->common.reg17.cbcr_yscl_offset = cbcr_scl_info.yscl_offset;
+
+    /* 3.2 set reg::zme::coef */
+    /* 0x0000(reg0) */
+    VDPP_SET_ZME_COEF(0, 0, 0);
+    VDPP_SET_ZME_COEF(0, 0, 1);
+
+    /* 0x0004(reg1) */
+    VDPP_SET_ZME_COEF(1, 0, 2);
+    VDPP_SET_ZME_COEF(1, 0, 3);
+
+    /* 0x0008(reg2) */
+    VDPP_SET_ZME_COEF(2, 0, 4);
+    VDPP_SET_ZME_COEF(2, 0, 5);
+
+    /* 0x000c(reg3) */
+    VDPP_SET_ZME_COEF(3, 0, 6);
+    VDPP_SET_ZME_COEF(3, 0, 7);
+
+    /* 0x0010(reg4) */
+    VDPP_SET_ZME_COEF(4, 1, 0);
+    VDPP_SET_ZME_COEF(4, 1, 1);
+
+    /* 0x0014(reg5) */
+    VDPP_SET_ZME_COEF(5, 1, 2);
+    VDPP_SET_ZME_COEF(5, 1, 3);
+
+    /* 0x0018(reg6) */
+    VDPP_SET_ZME_COEF(6, 1, 4);
+    VDPP_SET_ZME_COEF(6, 1, 5);
+
+    /* 0x001c(reg7) */
+    VDPP_SET_ZME_COEF(7, 1, 6);
+    VDPP_SET_ZME_COEF(7, 1, 7);
+
+    /* 0x0020(reg8) */
+    VDPP_SET_ZME_COEF(8, 2, 0);
+    VDPP_SET_ZME_COEF(8, 2, 1);
+
+    /* 0x0024(reg9) */
+    VDPP_SET_ZME_COEF(9, 2, 2);
+    VDPP_SET_ZME_COEF(9, 2, 3);
+
+    /* 0x0028(reg10) */
+    VDPP_SET_ZME_COEF(10, 2, 4);
+    VDPP_SET_ZME_COEF(10, 2, 5);
+
+    /* 0x002c(reg11) */
+    VDPP_SET_ZME_COEF(11, 2, 6);
+    VDPP_SET_ZME_COEF(11, 2, 7);
+
+    /* 0x0030(reg12) */
+    VDPP_SET_ZME_COEF(12, 3, 0);
+    VDPP_SET_ZME_COEF(12, 3, 1);
+
+    /* 0x0034(reg13) */
+    VDPP_SET_ZME_COEF(13, 3, 2);
+    VDPP_SET_ZME_COEF(13, 3, 3);
+
+    /* 0x0038(reg14) */
+    VDPP_SET_ZME_COEF(14, 3, 4);
+    VDPP_SET_ZME_COEF(14, 3, 5);
+
+    /* 0x003c(reg15) */
+    VDPP_SET_ZME_COEF(15, 3, 6);
+    VDPP_SET_ZME_COEF(15, 3, 7);
+
+    /* 0x0040(reg16) */
+    VDPP_SET_ZME_COEF(16, 4, 0);
+    VDPP_SET_ZME_COEF(16, 4, 1);
+
+    /* 0x0044(reg17) */
+    VDPP_SET_ZME_COEF(17, 4, 2);
+    VDPP_SET_ZME_COEF(17, 4, 3);
+
+    /* 0x0048(reg18) */
+    VDPP_SET_ZME_COEF(18, 4, 4);
+    VDPP_SET_ZME_COEF(18, 4, 5);
+
+    /* 0x004c(reg19) */
+    VDPP_SET_ZME_COEF(19, 4, 6);
+    VDPP_SET_ZME_COEF(19, 4, 7);
+
+    /* 0x0050(reg20) */
+    VDPP_SET_ZME_COEF(20, 5, 0);
+    VDPP_SET_ZME_COEF(20, 5, 1);
+
+    /* 0x0054(reg21) */
+    VDPP_SET_ZME_COEF(21, 5, 2);
+    VDPP_SET_ZME_COEF(21, 5, 3);
+
+    /* 0x0058(reg22) */
+    VDPP_SET_ZME_COEF(22, 5, 4);
+    VDPP_SET_ZME_COEF(22, 5, 5);
+
+    /* 0x005c(reg23) */
+    VDPP_SET_ZME_COEF(23, 5, 6);
+    VDPP_SET_ZME_COEF(23, 5, 7);
+
+    /* 0x0060(reg24) */
+    VDPP_SET_ZME_COEF(24, 6, 0);
+    VDPP_SET_ZME_COEF(24, 6, 1);
+
+    /* 0x0064(reg25) */
+    VDPP_SET_ZME_COEF(25, 6, 2);
+    VDPP_SET_ZME_COEF(25, 6, 3);
+
+    /* 0x0068(reg26) */
+    VDPP_SET_ZME_COEF(26, 6, 4);
+    VDPP_SET_ZME_COEF(26, 6, 5);
+
+    /* 0x006c(reg27) */
+    VDPP_SET_ZME_COEF(27, 6, 6);
+    VDPP_SET_ZME_COEF(27, 6, 7);
+
+    /* 0x0070(reg28) */
+    VDPP_SET_ZME_COEF(28, 7, 0);
+    VDPP_SET_ZME_COEF(28, 7, 1);
+
+    /* 0x0074(reg29) */
+    VDPP_SET_ZME_COEF(29, 7, 2);
+    VDPP_SET_ZME_COEF(29, 7, 3);
+
+    /* 0x0078(reg30) */
+    VDPP_SET_ZME_COEF(30, 7, 4);
+    VDPP_SET_ZME_COEF(30, 7, 5);
+
+    /* 0x007c(reg31) */
+    VDPP_SET_ZME_COEF(31, 7, 6);
+    VDPP_SET_ZME_COEF(31, 7, 7);
+
+    /* 0x0080(reg32) */
+    VDPP_SET_ZME_COEF(32, 8, 0);
+    VDPP_SET_ZME_COEF(32, 8, 1);
+
+    /* 0x0084(reg33) */
+    VDPP_SET_ZME_COEF(33, 8, 2);
+    VDPP_SET_ZME_COEF(33, 8, 3);
+
+    /* 0x0088(reg34) */
+    VDPP_SET_ZME_COEF(34, 8, 4);
+    VDPP_SET_ZME_COEF(34, 8, 5);
+
+    /* 0x008c(reg35) */
+    VDPP_SET_ZME_COEF(35, 8, 6);
+    VDPP_SET_ZME_COEF(35, 8, 7);
+
+    /* 0x0090(reg36) */
+    VDPP_SET_ZME_COEF(36, 9, 0);
+    VDPP_SET_ZME_COEF(36, 9, 1);
+
+    /* 0x0094(reg37) */
+    VDPP_SET_ZME_COEF(37, 9, 2);
+    VDPP_SET_ZME_COEF(37, 9, 3);
+
+    /* 0x0098(reg38) */
+    VDPP_SET_ZME_COEF(38, 9, 4);
+    VDPP_SET_ZME_COEF(38, 9, 5);
+
+    /* 0x009c(reg39) */
+    VDPP_SET_ZME_COEF(39, 9, 6);
+    VDPP_SET_ZME_COEF(39, 9, 7);
+
+    /* 0x00a0(reg40) */
+    VDPP_SET_ZME_COEF(40, 10, 0);
+    VDPP_SET_ZME_COEF(40, 10, 1);
+
+    /* 0x00a4(reg41) */
+    VDPP_SET_ZME_COEF(41, 10, 2);
+    VDPP_SET_ZME_COEF(41, 10, 3);
+
+    /* 0x00a8(reg42) */
+    VDPP_SET_ZME_COEF(42, 10, 4);
+    VDPP_SET_ZME_COEF(42, 10, 5);
+
+    /* 0x00ac(reg43) */
+    VDPP_SET_ZME_COEF(43, 10, 6);
+    VDPP_SET_ZME_COEF(43, 10, 7);
+
+    /* 0x00b0(reg44) */
+    VDPP_SET_ZME_COEF(44, 11, 0);
+    VDPP_SET_ZME_COEF(44, 11, 1);
+
+    /* 0x00b4(reg45) */
+    VDPP_SET_ZME_COEF(45, 11, 2);
+    VDPP_SET_ZME_COEF(45, 11, 3);
+
+    /* 0x00b8(reg46) */
+    VDPP_SET_ZME_COEF(46, 11, 4);
+    VDPP_SET_ZME_COEF(46, 11, 5);
+
+    /* 0x00bc(reg47) */
+    VDPP_SET_ZME_COEF(47, 11, 6);
+    VDPP_SET_ZME_COEF(47, 11, 7);
+
+    /* 0x00c0(reg48) */
+    VDPP_SET_ZME_COEF(48, 12, 0);
+    VDPP_SET_ZME_COEF(48, 12, 1);
+
+    /* 0x00c4(reg49) */
+    VDPP_SET_ZME_COEF(49, 12, 2);
+    VDPP_SET_ZME_COEF(49, 12, 3);
+
+    /* 0x00c8(reg50) */
+    VDPP_SET_ZME_COEF(50, 12, 4);
+    VDPP_SET_ZME_COEF(50, 12, 5);
+
+    /* 0x00cc(reg51) */
+    VDPP_SET_ZME_COEF(51, 12, 6);
+    VDPP_SET_ZME_COEF(51, 12, 7);
+
+    /* 0x00d0(reg52) */
+    VDPP_SET_ZME_COEF(52, 13, 0);
+    VDPP_SET_ZME_COEF(52, 13, 1);
+
+    /* 0x00d4(reg53) */
+    VDPP_SET_ZME_COEF(53, 13, 2);
+    VDPP_SET_ZME_COEF(53, 13, 3);
+
+    /* 0x00d8(reg54) */
+    VDPP_SET_ZME_COEF(54, 13, 4);
+    VDPP_SET_ZME_COEF(54, 13, 5);
+
+    /* 0x00dc(reg55) */
+    VDPP_SET_ZME_COEF(55, 13, 6);
+    VDPP_SET_ZME_COEF(55, 13, 7);
+
+    /* 0x00e0(reg56) */
+    VDPP_SET_ZME_COEF(56, 14, 0);
+    VDPP_SET_ZME_COEF(56, 14, 1);
+
+    /* 0x00e4(reg57) */
+    VDPP_SET_ZME_COEF(57, 14, 2);
+    VDPP_SET_ZME_COEF(57, 14, 3);
+
+    /* 0x00e8(reg58) */
+    VDPP_SET_ZME_COEF(58, 14, 4);
+    VDPP_SET_ZME_COEF(58, 14, 5);
+
+    /* 0x00ec(reg59) */
+    VDPP_SET_ZME_COEF(59, 14, 6);
+    VDPP_SET_ZME_COEF(59, 14, 7);
+
+    /* 0x00f0(reg60) */
+    VDPP_SET_ZME_COEF(60, 15, 0);
+    VDPP_SET_ZME_COEF(60, 15, 1);
+
+    /* 0x00f4(reg61) */
+    VDPP_SET_ZME_COEF(61, 15, 2);
+    VDPP_SET_ZME_COEF(61, 15, 3);
+
+    /* 0x00f8(reg62) */
+    VDPP_SET_ZME_COEF(62, 15, 4);
+    VDPP_SET_ZME_COEF(62, 15, 5);
+
+    /* 0x00fc(reg63) */
+    VDPP_SET_ZME_COEF(63, 15, 6);
+    VDPP_SET_ZME_COEF(63, 15, 7);
+
+    /* 0x0100(reg64) */
+    VDPP_SET_ZME_COEF(64, 16, 0);
+    VDPP_SET_ZME_COEF(64, 16, 1);
+
+    /* 0x0104(reg65) */
+    VDPP_SET_ZME_COEF(65, 16, 2);
+    VDPP_SET_ZME_COEF(65, 16, 3);
+
+    /* 0x0108(reg66) */
+    VDPP_SET_ZME_COEF(66, 16, 4);
+    VDPP_SET_ZME_COEF(66, 16, 5);
+
+    /* 0x010c(reg67) */
+    VDPP_SET_ZME_COEF(67, 16, 6);
+    VDPP_SET_ZME_COEF(67, 16, 7);
+
+}
diff --git a/mpp/vproc/vdpp/vdpp_common.h b/mpp/vproc/vdpp/vdpp_common.h
new file mode 100644
index 000000000..1d206c429
--- /dev/null
+++ b/mpp/vproc/vdpp/vdpp_common.h
@@ -0,0 +1,1769 @@
+/* SPDX-License-Identifier: Apache-2.0 OR MIT */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef __VDPP_COMMON_H__
+#define __VDPP_COMMON_H__
+
+#include <string.h>
+
+#include "rk_type.h"
+#include "mpp_err.h"
+#include "mpp_common.h"
+#include "vdpp_api.h"
+
+/* marco define */
+#define VDPP_TILE_W_MAX     (120)
+#define VDPP_TILE_H_MAX     (480)
+
+#define SCALE_FACTOR_DN_FIXPOINT_SHIFT    (12)
+#define SCALE_FACTOR_UP_FIXPOINT_SHIFT    (16)
+#define GET_SCALE_FACTOR_DN(src,dst)      ((((src) - 1) << SCALE_FACTOR_DN_FIXPOINT_SHIFT)  / ((dst) - 1))
+#define GET_SCALE_FACTOR_UP(src,dst)      ((((src) - 1) << SCALE_FACTOR_UP_FIXPOINT_SHIFT)  / ((dst) - 1))
+
+extern const char *working_mode_name[];
+
+enum ZME_FMT {
+    FMT_YCbCr420_888    = 4,
+    FMT_YCbCr444_888    = 6,
+};
+
+enum {
+    SCL_NEI = 0,
+    SCL_BIL = 1,
+    SCL_BIC = 2,
+    SCL_MPH = 3,
+};
+
+struct dmsr_params {
+    bool   dmsr_enable;
+    RK_U32 dmsr_str_pri_y;
+    RK_U32 dmsr_str_sec_y;
+    RK_U32 dmsr_dumping_y;
+    RK_U32 dmsr_wgt_pri_gain_even_1;
+    RK_U32 dmsr_wgt_pri_gain_even_2;
+    RK_U32 dmsr_wgt_pri_gain_odd_1;
+    RK_U32 dmsr_wgt_pri_gain_odd_2;
+    RK_U32 dmsr_wgt_sec_gain;
+    RK_U32 dmsr_blk_flat_th;
+    RK_U32 dmsr_contrast_to_conf_map_x0;
+    RK_U32 dmsr_contrast_to_conf_map_x1;
+    RK_U32 dmsr_contrast_to_conf_map_y0;
+    RK_U32 dmsr_contrast_to_conf_map_y1;
+    RK_U32 dmsr_diff_core_th0;
+    RK_U32 dmsr_diff_core_th1;
+    RK_U32 dmsr_diff_core_wgt0;
+    RK_U32 dmsr_diff_core_wgt1;
+    RK_U32 dmsr_diff_core_wgt2;
+    RK_U32 dmsr_edge_th_low_arr[7];
+    RK_U32 dmsr_edge_th_high_arr[7];
+};
+
+struct dmsr_reg {
+
+    struct {
+        RK_U32 sw_dmsr_edge_low_thre_0      : 16;
+        RK_U32 sw_dmsr_edge_high_thre_0     : 16;
+    } reg0;         /* 0x0080 */
+
+    struct {
+        RK_U32 sw_dmsr_edge_low_thre_1      : 16;
+        RK_U32 sw_dmsr_edge_high_thre_1     : 16;
+    } reg1;         /* 0x0084 */
+
+    struct {
+        RK_U32 sw_dmsr_edge_low_thre_2      : 16;
+        RK_U32 sw_dmsr_edge_high_thre_2     : 16;
+    } reg2;         /* 0x0088 */
+
+    struct {
+        RK_U32 sw_dmsr_edge_low_thre_3      : 16;
+        RK_U32 sw_dmsr_edge_high_thre_3     : 16;
+    } reg3;         /* 0x008C */
+
+    struct {
+        RK_U32 sw_dmsr_edge_low_thre_4      : 16;
+        RK_U32 sw_dmsr_edge_high_thre_4     : 16;
+    } reg4;         /* 0x0090 */
+
+    struct {
+        RK_U32 sw_dmsr_edge_low_thre_5      : 16;
+        RK_U32 sw_dmsr_edge_high_thre_5     : 16;
+    } reg5;         /* 0x0094 */
+
+    struct {
+        RK_U32 sw_dmsr_edge_low_thre_6      : 16;
+        RK_U32 sw_dmsr_edge_high_thre_6     : 16;
+    } reg6;         /* 0x0098 */
+
+    struct {
+        RK_U32 sw_dmsr_edge_k_0     : 16;
+        RK_U32 sw_dmsr_edge_k_1     : 16;
+    } reg7;         /* 0x009C */
+
+    struct {
+        RK_U32 sw_dmsr_edge_k_2     : 16;
+        RK_U32 sw_dmsr_edge_k_3     : 16;
+    } reg8;         /* 0x00A0 */
+
+    struct {
+        RK_U32 sw_dmsr_edge_k_4     : 16;
+        RK_U32 sw_dmsr_edge_k_5     : 16;
+    } reg9;         /* 0x00A4 */
+
+    struct {
+        RK_U32 sw_dmsr_edge_k_6     : 16;
+        RK_U32 sw_dmsr_dir_contrast_conf_f  : 16;
+    } reg10;         /* 0x00A8 */
+
+    struct {
+        RK_U32 sw_dmsr_dir_contrast_conf_x0 : 16;
+        RK_U32 sw_dmsr_dir_contrast_conf_x1  : 16;
+    } reg11;         /* 0x00AC */
+
+    struct {
+        RK_U32 sw_dmsr_dir_contrast_conf_y0 : 16;
+        RK_U32 sw_dmsr_dir_contrast_conf_y1 : 16;
+    } reg12;         /* 0x00B0 */
+
+    struct {
+        RK_U32 sw_dmsr_var_th       : 16;
+    } reg13;         /* 0x00B4 */
+
+    struct {
+        RK_U32 sw_dmsr_diff_coring_th0      : 8;
+        RK_U32 sw_dmsr_diff_coring_th1      : 8;
+    } reg14;         /* 0x00B8 */
+
+    struct {
+        RK_U32 sw_dmsr_diff_coring_wgt0     : 6;
+        RK_U32 sw_reserved_1        : 2;
+        RK_U32 sw_dmsr_diff_coring_wgt1     : 6;
+        RK_U32 sw_reserved_2        : 2;
+        RK_U32 sw_dmsr_diff_coring_wgt2     : 6;
+    } reg15;         /* 0x00BC */
+
+    struct {
+        RK_U32 sw_dmsr_diff_coring_y0      : 14;
+        RK_U32 sw_reserved_1        : 2;
+        RK_U32 sw_dmsr_diff_coring_y1      : 14;
+        RK_U32 sw_reserved_2        : 2;
+    } reg16;         /* 0x00C0 */
+
+    struct {
+        RK_U32 sw_dmsr_wgt_pri_gain_1_odd   : 6;
+        RK_U32 sw_reserved_1        : 2;
+        RK_U32 sw_dmsr_wgt_pri_gain_1_even  : 6;
+        RK_U32 sw_reserved_2        : 2;
+        RK_U32 sw_dmsr_wgt_pri_gain_2_odd   : 6;
+        RK_U32 sw_reserved_3        : 2;
+        RK_U32 sw_dmsr_wgt_pri_gain_2_even  : 6;
+    } reg17;         /* 0x00C4 */
+
+    struct {
+        RK_U32 sw_dmsr_wgt_sec_gain_1       : 6;
+        RK_U32 sw_reserved_1        : 2;
+        RK_U32 sw_dmsr_wgt_sec_gain_2       : 6;
+    } reg18;         /* 0x00C8 */
+
+    struct {
+        RK_U32 sw_dmsr_strength_pri : 5;
+        RK_U32 sw_reserved_1        : 3;
+        RK_U32 sw_dmsr_strength_sec : 5;
+        RK_U32 sw_reserved_2        : 3;
+        RK_U32 sw_dmsr_dump         : 4;
+    } reg19;         /* 0x00CC */
+
+    struct {
+        RK_U32 sw_dmsr_obv_point_h  : 12;
+        RK_U32 sw_dmsr_obv_point_v  : 12;
+        RK_U32 sw_dmsr_obv_enable   : 1;
+        RK_U32 sw_dmsr_obv_mode     : 1;
+    } reg20;         /* 0x00D0 */
+};               /* offset: 0x1080 */
+
+
+typedef struct {
+    RK_U16 act_width;
+    RK_U16 dsp_width;
+
+    RK_U16 act_height;
+    RK_U16 dsp_height;
+
+    RK_U8  dering_en;
+
+    RK_U8  xsd_en;
+    RK_U8  xsu_en;
+    RK_U8  xsd_bypass;
+    RK_U8  xsu_bypass;
+    RK_U8  xscl_mode;
+    RK_U16 xscl_factor;
+    RK_U8  xscl_offset;
+
+    RK_U8  ysd_en;
+    RK_U8  ysu_en;
+    RK_U8  ys_bypass;
+    RK_U8  yscl_mode;
+    RK_U16 yscl_factor;
+    RK_U8  yscl_offset;
+
+    RK_U8  xavg_en;
+    RK_U8  xgt_en;
+    RK_U8  xgt_mode;
+
+    RK_U8  yavg_en;
+    RK_U8  ygt_en;
+    RK_U8  ygt_mode;
+
+    RK_S16 (*xscl_zme_coe)[8];
+    RK_S16 (*yscl_zme_coe)[8];
+} scl_info;
+
+typedef struct FdTransInfo_t {
+    RK_U32        reg_idx;
+    RK_U32        offset;
+} RegOffsetInfo;
+
+struct vdpp_addr {
+    RK_U32 y;
+    RK_U32 cbcr;
+    RK_U32 cbcr_offset;
+};
+
+struct zme_params {
+    RK_U32 zme_bypass_en;
+    RK_U32 zme_dering_enable;
+    RK_U32 zme_dering_sen_0;
+    RK_U32 zme_dering_sen_1;
+    RK_U32 zme_dering_blend_alpha;
+    RK_U32 zme_dering_blend_beta;
+    RK_S16 (*zme_tap8_coeff)[17][8];
+    RK_S16 (*zme_tap6_coeff)[17][8];
+
+    /* for scl_info */
+    RK_U32 src_width;
+    RK_U32 src_height;
+    RK_U32 dst_width;
+    RK_U32 dst_height;
+    RK_U32 dst_fmt;
+    /* 3576 feature */
+    RK_U32 yuv_out_diff;
+    RK_U32 dst_c_width;
+    RK_U32 dst_c_height;
+};
+
+
+struct zme_reg {
+    struct {
+        struct {
+            RK_U32 yrgb_hor_coe0_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe0_1  : 10;
+        } reg0;         /* 0x0000 */
+        struct {
+            RK_U32 yrgb_hor_coe0_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe0_3  : 10;
+        } reg1;         /* 0x0004 */
+        struct {
+            RK_U32 yrgb_hor_coe0_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe0_5  : 10;
+        } reg2;         /* 0x0008 */
+        struct {
+            RK_U32 yrgb_hor_coe0_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe0_7  : 10;
+        } reg3;         /* 0x000c */
+        struct {
+            RK_U32 yrgb_hor_coe1_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe1_1  : 10;
+        } reg4;         /* 0x0010 */
+        struct {
+            RK_U32 yrgb_hor_coe1_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe1_3  : 10;
+        } reg5;         /* 0x0014 */
+        struct {
+            RK_U32 yrgb_hor_coe1_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe1_5  : 10;
+        } reg6;         /* 0x0018 */
+        struct {
+            RK_U32 yrgb_hor_coe1_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe1_7  : 10;
+        } reg7;         /* 0x001c */
+        struct {
+            RK_U32 yrgb_hor_coe2_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe2_1  : 10;
+        } reg8;         /* 0x0020 */
+        struct {
+            RK_U32 yrgb_hor_coe2_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe2_3  : 10;
+        } reg9;         /* 0x0024 */
+        struct {
+            RK_U32 yrgb_hor_coe2_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe2_5  : 10;
+        } reg10;         /* 0x0028 */
+        struct {
+            RK_U32 yrgb_hor_coe2_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe2_7  : 10;
+        } reg11;         /* 0x002c */
+        struct {
+            RK_U32 yrgb_hor_coe3_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe3_1  : 10;
+        } reg12;         /* 0x0030 */
+        struct {
+            RK_U32 yrgb_hor_coe3_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe3_3  : 10;
+        } reg13;         /* 0x0034 */
+        struct {
+            RK_U32 yrgb_hor_coe3_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe3_5  : 10;
+        } reg14;         /* 0x0038 */
+        struct {
+            RK_U32 yrgb_hor_coe3_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe3_7  : 10;
+        } reg15;         /* 0x003c */
+        struct {
+            RK_U32 yrgb_hor_coe4_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe4_1  : 10;
+        } reg16;         /* 0x0040 */
+        struct {
+            RK_U32 yrgb_hor_coe4_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe4_3  : 10;
+        } reg17;         /* 0x0044 */
+        struct {
+            RK_U32 yrgb_hor_coe4_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe4_5  : 10;
+        } reg18;         /* 0x0048 */
+        struct {
+            RK_U32 yrgb_hor_coe4_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe4_7  : 10;
+        } reg19;         /* 0x004c */
+        struct {
+            RK_U32 yrgb_hor_coe5_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe5_1  : 10;
+        } reg20;         /* 0x0050 */
+        struct {
+            RK_U32 yrgb_hor_coe5_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe5_3  : 10;
+        } reg21;         /* 0x0054 */
+        struct {
+            RK_U32 yrgb_hor_coe5_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe5_5  : 10;
+        } reg22;         /* 0x0058 */
+        struct {
+            RK_U32 yrgb_hor_coe5_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe5_7  : 10;
+        } reg23;         /* 0x005c */
+        struct {
+            RK_U32 yrgb_hor_coe6_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe6_1  : 10;
+        } reg24;         /* 0x0060 */
+        struct {
+            RK_U32 yrgb_hor_coe6_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe6_3  : 10;
+        } reg25;         /* 0x0064 */
+        struct {
+            RK_U32 yrgb_hor_coe6_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe6_5  : 10;
+        } reg26;         /* 0x0068 */
+        struct {
+            RK_U32 yrgb_hor_coe6_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe6_7  : 10;
+        } reg27;         /* 0x006c */
+        struct {
+            RK_U32 yrgb_hor_coe7_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe7_1  : 10;
+        } reg28;         /* 0x0070 */
+        struct {
+            RK_U32 yrgb_hor_coe7_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe7_3  : 10;
+        } reg29;         /* 0x0074 */
+        struct {
+            RK_U32 yrgb_hor_coe7_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe7_5  : 10;
+        } reg30;         /* 0x0078 */
+        struct {
+            RK_U32 yrgb_hor_coe7_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe7_7  : 10;
+        } reg31;         /* 0x007c */
+        struct {
+            RK_U32 yrgb_hor_coe8_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe8_1  : 10;
+        } reg32;         /* 0x0080 */
+        struct {
+            RK_U32 yrgb_hor_coe8_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe8_3  : 10;
+        } reg33;         /* 0x0084 */
+        struct {
+            RK_U32 yrgb_hor_coe8_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe8_5  : 10;
+        } reg34;         /* 0x0088 */
+        struct {
+            RK_U32 yrgb_hor_coe8_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe8_7  : 10;
+        } reg35;         /* 0x008c */
+        struct {
+            RK_U32 yrgb_hor_coe9_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe9_1  : 10;
+        } reg36;         /* 0x0090 */
+        struct {
+            RK_U32 yrgb_hor_coe9_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe9_3  : 10;
+        } reg37;         /* 0x0094 */
+        struct {
+            RK_U32 yrgb_hor_coe9_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe9_5  : 10;
+        } reg38;         /* 0x0098 */
+        struct {
+            RK_U32 yrgb_hor_coe9_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe9_7  : 10;
+        } reg39;         /* 0x009c */
+        struct {
+            RK_U32 yrgb_hor_coe10_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe10_1  : 10;
+        } reg40;         /* 0x00a0 */
+        struct {
+            RK_U32 yrgb_hor_coe10_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe10_3  : 10;
+        } reg41;         /* 0x00a4 */
+        struct {
+            RK_U32 yrgb_hor_coe10_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe10_5  : 10;
+        } reg42;         /* 0x00a8 */
+        struct {
+            RK_U32 yrgb_hor_coe10_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe10_7  : 10;
+        } reg43;         /* 0x00ac */
+        struct {
+            RK_U32 yrgb_hor_coe11_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe11_1  : 10;
+        } reg44;         /* 0x00b0 */
+        struct {
+            RK_U32 yrgb_hor_coe11_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe11_3  : 10;
+        } reg45;         /* 0x00b4 */
+        struct {
+            RK_U32 yrgb_hor_coe11_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe11_5  : 10;
+        } reg46;         /* 0x00b8 */
+        struct {
+            RK_U32 yrgb_hor_coe11_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe11_7  : 10;
+        } reg47;         /* 0x00bc */
+        struct {
+            RK_U32 yrgb_hor_coe12_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe12_1  : 10;
+        } reg48;         /* 0x00c0 */
+        struct {
+            RK_U32 yrgb_hor_coe12_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe12_3  : 10;
+        } reg49;         /* 0x00c4 */
+        struct {
+            RK_U32 yrgb_hor_coe12_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe12_5  : 10;
+        } reg50;         /* 0x00c8 */
+        struct {
+            RK_U32 yrgb_hor_coe12_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe12_7  : 10;
+        } reg51;         /* 0x00cc */
+        struct {
+            RK_U32 yrgb_hor_coe13_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe13_1  : 10;
+        } reg52;         /* 0x00d0 */
+        struct {
+            RK_U32 yrgb_hor_coe13_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe13_3  : 10;
+        } reg53;         /* 0x00d4 */
+        struct {
+            RK_U32 yrgb_hor_coe13_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe13_5  : 10;
+        } reg54;         /* 0x00d8 */
+        struct {
+            RK_U32 yrgb_hor_coe13_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe13_7  : 10;
+        } reg55;         /* 0x00dc */
+        struct {
+            RK_U32 yrgb_hor_coe14_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe14_1  : 10;
+        } reg56;         /* 0x00e0 */
+        struct {
+            RK_U32 yrgb_hor_coe14_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe14_3  : 10;
+        } reg57;         /* 0x00e4 */
+        struct {
+            RK_U32 yrgb_hor_coe14_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe14_5  : 10;
+        } reg58;         /* 0x00e8 */
+        struct {
+            RK_U32 yrgb_hor_coe14_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe14_7  : 10;
+        } reg59;         /* 0x00ec */
+        struct {
+            RK_U32 yrgb_hor_coe15_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe15_1  : 10;
+        } reg60;         /* 0x00f0 */
+        struct {
+            RK_U32 yrgb_hor_coe15_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe15_3  : 10;
+        } reg61;         /* 0x00f4 */
+        struct {
+            RK_U32 yrgb_hor_coe15_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe15_5  : 10;
+        } reg62;         /* 0x00f8 */
+        struct {
+            RK_U32 yrgb_hor_coe15_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe15_7  : 10;
+        } reg63;         /* 0x00fc */
+        struct {
+            RK_U32 yrgb_hor_coe16_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe16_1  : 10;
+        } reg64;         /* 0x0100 */
+        struct {
+            RK_U32 yrgb_hor_coe16_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe16_3  : 10;
+        } reg65;         /* 0x0104 */
+        struct {
+            RK_U32 yrgb_hor_coe16_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe16_5  : 10;
+        } reg66;         /* 0x0108 */
+        struct {
+            RK_U32 yrgb_hor_coe16_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_hor_coe16_7  : 10;
+        } reg67;         /* 0x010c */
+
+    } yrgb_hor_coe;
+
+    struct {
+        struct {
+            RK_U32 yrgb_ver_coe0_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe0_1  : 10;
+        } reg0;         /* 0x0200 */
+        struct {
+            RK_U32 yrgb_ver_coe0_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe0_3  : 10;
+        } reg1;         /* 0x0204 */
+        struct {
+            RK_U32 yrgb_ver_coe0_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe0_5  : 10;
+        } reg2;         /* 0x0208 */
+        struct {
+            RK_U32 yrgb_ver_coe0_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe0_7  : 10;
+        } reg3;         /* 0x020c */
+        struct {
+            RK_U32 yrgb_ver_coe1_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe1_1  : 10;
+        } reg4;         /* 0x0210 */
+        struct {
+            RK_U32 yrgb_ver_coe1_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe1_3  : 10;
+        } reg5;         /* 0x0214 */
+        struct {
+            RK_U32 yrgb_ver_coe1_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe1_5  : 10;
+        } reg6;         /* 0x0218 */
+        struct {
+            RK_U32 yrgb_ver_coe1_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe1_7  : 10;
+        } reg7;         /* 0x021c */
+        struct {
+            RK_U32 yrgb_ver_coe2_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe2_1  : 10;
+        } reg8;         /* 0x0220 */
+        struct {
+            RK_U32 yrgb_ver_coe2_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe2_3  : 10;
+        } reg9;         /* 0x0224 */
+        struct {
+            RK_U32 yrgb_ver_coe2_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe2_5  : 10;
+        } reg10;         /* 0x0228 */
+        struct {
+            RK_U32 yrgb_ver_coe2_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe2_7  : 10;
+        } reg11;         /* 0x022c */
+        struct {
+            RK_U32 yrgb_ver_coe3_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe3_1  : 10;
+        } reg12;         /* 0x0230 */
+        struct {
+            RK_U32 yrgb_ver_coe3_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe3_3  : 10;
+        } reg13;         /* 0x0234 */
+        struct {
+            RK_U32 yrgb_ver_coe3_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe3_5  : 10;
+        } reg14;         /* 0x0238 */
+        struct {
+            RK_U32 yrgb_ver_coe3_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe3_7  : 10;
+        } reg15;         /* 0x023c */
+        struct {
+            RK_U32 yrgb_ver_coe4_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe4_1  : 10;
+        } reg16;         /* 0x0240 */
+        struct {
+            RK_U32 yrgb_ver_coe4_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe4_3  : 10;
+        } reg17;         /* 0x0244 */
+        struct {
+            RK_U32 yrgb_ver_coe4_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe4_5  : 10;
+        } reg18;         /* 0x0248 */
+        struct {
+            RK_U32 yrgb_ver_coe4_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe4_7  : 10;
+        } reg19;         /* 0x024c */
+        struct {
+            RK_U32 yrgb_ver_coe5_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe5_1  : 10;
+        } reg20;         /* 0x0250 */
+        struct {
+            RK_U32 yrgb_ver_coe5_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe5_3  : 10;
+        } reg21;         /* 0x0254 */
+        struct {
+            RK_U32 yrgb_ver_coe5_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe5_5  : 10;
+        } reg22;         /* 0x0258 */
+        struct {
+            RK_U32 yrgb_ver_coe5_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe5_7  : 10;
+        } reg23;         /* 0x025c */
+        struct {
+            RK_U32 yrgb_ver_coe6_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe6_1  : 10;
+        } reg24;         /* 0x0260 */
+        struct {
+            RK_U32 yrgb_ver_coe6_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe6_3  : 10;
+        } reg25;         /* 0x0264 */
+        struct {
+            RK_U32 yrgb_ver_coe6_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe6_5  : 10;
+        } reg26;         /* 0x0268 */
+        struct {
+            RK_U32 yrgb_ver_coe6_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe6_7  : 10;
+        } reg27;         /* 0x026c */
+        struct {
+            RK_U32 yrgb_ver_coe7_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe7_1  : 10;
+        } reg28;         /* 0x0270 */
+        struct {
+            RK_U32 yrgb_ver_coe7_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe7_3  : 10;
+        } reg29;         /* 0x0274 */
+        struct {
+            RK_U32 yrgb_ver_coe7_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe7_5  : 10;
+        } reg30;         /* 0x0278 */
+        struct {
+            RK_U32 yrgb_ver_coe7_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe7_7  : 10;
+        } reg31;         /* 0x027c */
+        struct {
+            RK_U32 yrgb_ver_coe8_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe8_1  : 10;
+        } reg32;         /* 0x0280 */
+        struct {
+            RK_U32 yrgb_ver_coe8_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe8_3  : 10;
+        } reg33;         /* 0x0284 */
+        struct {
+            RK_U32 yrgb_ver_coe8_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe8_5  : 10;
+        } reg34;         /* 0x0288 */
+        struct {
+            RK_U32 yrgb_ver_coe8_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe8_7  : 10;
+        } reg35;         /* 0x028c */
+        struct {
+            RK_U32 yrgb_ver_coe9_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe9_1  : 10;
+        } reg36;         /* 0x0290 */
+        struct {
+            RK_U32 yrgb_ver_coe9_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe9_3  : 10;
+        } reg37;         /* 0x0294 */
+        struct {
+            RK_U32 yrgb_ver_coe9_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe9_5  : 10;
+        } reg38;         /* 0x0298 */
+        struct {
+            RK_U32 yrgb_ver_coe9_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe9_7  : 10;
+        } reg39;         /* 0x029c */
+        struct {
+            RK_U32 yrgb_ver_coe10_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe10_1  : 10;
+        } reg40;         /* 0x02a0 */
+        struct {
+            RK_U32 yrgb_ver_coe10_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe10_3  : 10;
+        } reg41;         /* 0x02a4 */
+        struct {
+            RK_U32 yrgb_ver_coe10_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe10_5  : 10;
+        } reg42;         /* 0x02a8 */
+        struct {
+            RK_U32 yrgb_ver_coe10_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe10_7  : 10;
+        } reg43;         /* 0x02ac */
+        struct {
+            RK_U32 yrgb_ver_coe11_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe11_1  : 10;
+        } reg44;         /* 0x02b0 */
+        struct {
+            RK_U32 yrgb_ver_coe11_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe11_3  : 10;
+        } reg45;         /* 0x02b4 */
+        struct {
+            RK_U32 yrgb_ver_coe11_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe11_5  : 10;
+        } reg46;         /* 0x02b8 */
+        struct {
+            RK_U32 yrgb_ver_coe11_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe11_7  : 10;
+        } reg47;         /* 0x02bc */
+        struct {
+            RK_U32 yrgb_ver_coe12_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe12_1  : 10;
+        } reg48;         /* 0x02c0 */
+        struct {
+            RK_U32 yrgb_ver_coe12_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe12_3  : 10;
+        } reg49;         /* 0x02c4 */
+        struct {
+            RK_U32 yrgb_ver_coe12_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe12_5  : 10;
+        } reg50;         /* 0x02c8 */
+        struct {
+            RK_U32 yrgb_ver_coe12_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe12_7  : 10;
+        } reg51;         /* 0x02cc */
+        struct {
+            RK_U32 yrgb_ver_coe13_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe13_1  : 10;
+        } reg52;         /* 0x02d0 */
+        struct {
+            RK_U32 yrgb_ver_coe13_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe13_3  : 10;
+        } reg53;         /* 0x02d4 */
+        struct {
+            RK_U32 yrgb_ver_coe13_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe13_5  : 10;
+        } reg54;         /* 0x02d8 */
+        struct {
+            RK_U32 yrgb_ver_coe13_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe13_7  : 10;
+        } reg55;         /* 0x02dc */
+        struct {
+            RK_U32 yrgb_ver_coe14_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe14_1  : 10;
+        } reg56;         /* 0x02e0 */
+        struct {
+            RK_U32 yrgb_ver_coe14_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe14_3  : 10;
+        } reg57;         /* 0x02e4 */
+        struct {
+            RK_U32 yrgb_ver_coe14_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe14_5  : 10;
+        } reg58;         /* 0x02e8 */
+        struct {
+            RK_U32 yrgb_ver_coe14_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe14_7  : 10;
+        } reg59;         /* 0x02ec */
+        struct {
+            RK_U32 yrgb_ver_coe15_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe15_1  : 10;
+        } reg60;         /* 0x02f0 */
+        struct {
+            RK_U32 yrgb_ver_coe15_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe15_3  : 10;
+        } reg61;         /* 0x02f4 */
+        struct {
+            RK_U32 yrgb_ver_coe15_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe15_5  : 10;
+        } reg62;         /* 0x02f8 */
+        struct {
+            RK_U32 yrgb_ver_coe15_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe15_7  : 10;
+        } reg63;         /* 0x02fc */
+        struct {
+            RK_U32 yrgb_ver_coe16_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe16_1  : 10;
+        } reg64;         /* 0x0300 */
+        struct {
+            RK_U32 yrgb_ver_coe16_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe16_3  : 10;
+        } reg65;         /* 0x0304 */
+        struct {
+            RK_U32 yrgb_ver_coe16_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe16_5  : 10;
+        } reg66;         /* 0x0308 */
+        struct {
+            RK_U32 yrgb_ver_coe16_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 yrgb_ver_coe16_7  : 10;
+        } reg67;         /* 0x030c */
+
+    } yrgb_ver_coe;
+
+    struct {
+        struct {
+            RK_U32 cbcr_hor_coe0_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe0_1  : 10;
+        } reg0;         /* 0x0400 */
+        struct {
+            RK_U32 cbcr_hor_coe0_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe0_3  : 10;
+        } reg1;         /* 0x0404 */
+        struct {
+            RK_U32 cbcr_hor_coe0_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe0_5  : 10;
+        } reg2;         /* 0x0408 */
+        struct {
+            RK_U32 cbcr_hor_coe0_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe0_7  : 10;
+        } reg3;         /* 0x040c */
+        struct {
+            RK_U32 cbcr_hor_coe1_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe1_1  : 10;
+        } reg4;         /* 0x0410 */
+        struct {
+            RK_U32 cbcr_hor_coe1_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe1_3  : 10;
+        } reg5;         /* 0x0414 */
+        struct {
+            RK_U32 cbcr_hor_coe1_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe1_5  : 10;
+        } reg6;         /* 0x0418 */
+        struct {
+            RK_U32 cbcr_hor_coe1_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe1_7  : 10;
+        } reg7;         /* 0x041c */
+        struct {
+            RK_U32 cbcr_hor_coe2_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe2_1  : 10;
+        } reg8;         /* 0x0420 */
+        struct {
+            RK_U32 cbcr_hor_coe2_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe2_3  : 10;
+        } reg9;         /* 0x0424 */
+        struct {
+            RK_U32 cbcr_hor_coe2_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe2_5  : 10;
+        } reg10;         /* 0x0428 */
+        struct {
+            RK_U32 cbcr_hor_coe2_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe2_7  : 10;
+        } reg11;         /* 0x042c */
+        struct {
+            RK_U32 cbcr_hor_coe3_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe3_1  : 10;
+        } reg12;         /* 0x0430 */
+        struct {
+            RK_U32 cbcr_hor_coe3_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe3_3  : 10;
+        } reg13;         /* 0x0434 */
+        struct {
+            RK_U32 cbcr_hor_coe3_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe3_5  : 10;
+        } reg14;         /* 0x0438 */
+        struct {
+            RK_U32 cbcr_hor_coe3_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe3_7  : 10;
+        } reg15;         /* 0x043c */
+        struct {
+            RK_U32 cbcr_hor_coe4_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe4_1  : 10;
+        } reg16;         /* 0x0440 */
+        struct {
+            RK_U32 cbcr_hor_coe4_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe4_3  : 10;
+        } reg17;         /* 0x0444 */
+        struct {
+            RK_U32 cbcr_hor_coe4_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe4_5  : 10;
+        } reg18;         /* 0x0448 */
+        struct {
+            RK_U32 cbcr_hor_coe4_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe4_7  : 10;
+        } reg19;         /* 0x044c */
+        struct {
+            RK_U32 cbcr_hor_coe5_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe5_1  : 10;
+        } reg20;         /* 0x0450 */
+        struct {
+            RK_U32 cbcr_hor_coe5_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe5_3  : 10;
+        } reg21;         /* 0x0454 */
+        struct {
+            RK_U32 cbcr_hor_coe5_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe5_5  : 10;
+        } reg22;         /* 0x0458 */
+        struct {
+            RK_U32 cbcr_hor_coe5_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe5_7  : 10;
+        } reg23;         /* 0x045c */
+        struct {
+            RK_U32 cbcr_hor_coe6_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe6_1  : 10;
+        } reg24;         /* 0x0460 */
+        struct {
+            RK_U32 cbcr_hor_coe6_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe6_3  : 10;
+        } reg25;         /* 0x0464 */
+        struct {
+            RK_U32 cbcr_hor_coe6_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe6_5  : 10;
+        } reg26;         /* 0x0468 */
+        struct {
+            RK_U32 cbcr_hor_coe6_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe6_7  : 10;
+        } reg27;         /* 0x046c */
+        struct {
+            RK_U32 cbcr_hor_coe7_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe7_1  : 10;
+        } reg28;         /* 0x0470 */
+        struct {
+            RK_U32 cbcr_hor_coe7_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe7_3  : 10;
+        } reg29;         /* 0x0474 */
+        struct {
+            RK_U32 cbcr_hor_coe7_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe7_5  : 10;
+        } reg30;         /* 0x0478 */
+        struct {
+            RK_U32 cbcr_hor_coe7_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe7_7  : 10;
+        } reg31;         /* 0x047c */
+        struct {
+            RK_U32 cbcr_hor_coe8_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe8_1  : 10;
+        } reg32;         /* 0x0480 */
+        struct {
+            RK_U32 cbcr_hor_coe8_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe8_3  : 10;
+        } reg33;         /* 0x0484 */
+        struct {
+            RK_U32 cbcr_hor_coe8_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe8_5  : 10;
+        } reg34;         /* 0x0488 */
+        struct {
+            RK_U32 cbcr_hor_coe8_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe8_7  : 10;
+        } reg35;         /* 0x048c */
+        struct {
+            RK_U32 cbcr_hor_coe9_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe9_1  : 10;
+        } reg36;         /* 0x0490 */
+        struct {
+            RK_U32 cbcr_hor_coe9_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe9_3  : 10;
+        } reg37;         /* 0x0494 */
+        struct {
+            RK_U32 cbcr_hor_coe9_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe9_5  : 10;
+        } reg38;         /* 0x0498 */
+        struct {
+            RK_U32 cbcr_hor_coe9_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe9_7  : 10;
+        } reg39;         /* 0x049c */
+        struct {
+            RK_U32 cbcr_hor_coe10_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe10_1  : 10;
+        } reg40;         /* 0x04a0 */
+        struct {
+            RK_U32 cbcr_hor_coe10_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe10_3  : 10;
+        } reg41;         /* 0x04a4 */
+        struct {
+            RK_U32 cbcr_hor_coe10_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe10_5  : 10;
+        } reg42;         /* 0x04a8 */
+        struct {
+            RK_U32 cbcr_hor_coe10_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe10_7  : 10;
+        } reg43;         /* 0x04ac */
+        struct {
+            RK_U32 cbcr_hor_coe11_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe11_1  : 10;
+        } reg44;         /* 0x04b0 */
+        struct {
+            RK_U32 cbcr_hor_coe11_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe11_3  : 10;
+        } reg45;         /* 0x04b4 */
+        struct {
+            RK_U32 cbcr_hor_coe11_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe11_5  : 10;
+        } reg46;         /* 0x04b8 */
+        struct {
+            RK_U32 cbcr_hor_coe11_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe11_7  : 10;
+        } reg47;         /* 0x04bc */
+        struct {
+            RK_U32 cbcr_hor_coe12_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe12_1  : 10;
+        } reg48;         /* 0x04c0 */
+        struct {
+            RK_U32 cbcr_hor_coe12_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe12_3  : 10;
+        } reg49;         /* 0x04c4 */
+        struct {
+            RK_U32 cbcr_hor_coe12_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe12_5  : 10;
+        } reg50;         /* 0x04c8 */
+        struct {
+            RK_U32 cbcr_hor_coe12_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe12_7  : 10;
+        } reg51;         /* 0x04cc */
+        struct {
+            RK_U32 cbcr_hor_coe13_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe13_1  : 10;
+        } reg52;         /* 0x04d0 */
+        struct {
+            RK_U32 cbcr_hor_coe13_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe13_3  : 10;
+        } reg53;         /* 0x04d4 */
+        struct {
+            RK_U32 cbcr_hor_coe13_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe13_5  : 10;
+        } reg54;         /* 0x04d8 */
+        struct {
+            RK_U32 cbcr_hor_coe13_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe13_7  : 10;
+        } reg55;         /* 0x04dc */
+        struct {
+            RK_U32 cbcr_hor_coe14_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe14_1  : 10;
+        } reg56;         /* 0x04e0 */
+        struct {
+            RK_U32 cbcr_hor_coe14_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe14_3  : 10;
+        } reg57;         /* 0x04e4 */
+        struct {
+            RK_U32 cbcr_hor_coe14_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe14_5  : 10;
+        } reg58;         /* 0x04e8 */
+        struct {
+            RK_U32 cbcr_hor_coe14_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe14_7  : 10;
+        } reg59;         /* 0x04ec */
+        struct {
+            RK_U32 cbcr_hor_coe15_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe15_1  : 10;
+        } reg60;         /* 0x04f0 */
+        struct {
+            RK_U32 cbcr_hor_coe15_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe15_3  : 10;
+        } reg61;         /* 0x04f4 */
+        struct {
+            RK_U32 cbcr_hor_coe15_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe15_5  : 10;
+        } reg62;         /* 0x04f8 */
+        struct {
+            RK_U32 cbcr_hor_coe15_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe15_7  : 10;
+        } reg63;         /* 0x04fc */
+        struct {
+            RK_U32 cbcr_hor_coe16_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe16_1  : 10;
+        } reg64;         /* 0x0500 */
+        struct {
+            RK_U32 cbcr_hor_coe16_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe16_3  : 10;
+        } reg65;         /* 0x0504 */
+        struct {
+            RK_U32 cbcr_hor_coe16_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe16_5  : 10;
+        } reg66;         /* 0x0508 */
+        struct {
+            RK_U32 cbcr_hor_coe16_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_hor_coe16_7  : 10;
+        } reg67;         /* 0x050c */
+
+    } cbcr_hor_coe;
+
+    struct {
+        struct {
+            RK_U32 cbcr_ver_coe0_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe0_1  : 10;
+        } reg0;         /* 0x0600 */
+        struct {
+            RK_U32 cbcr_ver_coe0_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe0_3  : 10;
+        } reg1;         /* 0x0604 */
+        struct {
+            RK_U32 cbcr_ver_coe0_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe0_5  : 10;
+        } reg2;         /* 0x0608 */
+        struct {
+            RK_U32 cbcr_ver_coe0_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe0_7  : 10;
+        } reg3;         /* 0x060c */
+        struct {
+            RK_U32 cbcr_ver_coe1_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe1_1  : 10;
+        } reg4;         /* 0x0610 */
+        struct {
+            RK_U32 cbcr_ver_coe1_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe1_3  : 10;
+        } reg5;         /* 0x0614 */
+        struct {
+            RK_U32 cbcr_ver_coe1_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe1_5  : 10;
+        } reg6;         /* 0x0618 */
+        struct {
+            RK_U32 cbcr_ver_coe1_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe1_7  : 10;
+        } reg7;         /* 0x061c */
+        struct {
+            RK_U32 cbcr_ver_coe2_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe2_1  : 10;
+        } reg8;         /* 0x0620 */
+        struct {
+            RK_U32 cbcr_ver_coe2_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe2_3  : 10;
+        } reg9;         /* 0x0624 */
+        struct {
+            RK_U32 cbcr_ver_coe2_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe2_5  : 10;
+        } reg10;         /* 0x0628 */
+        struct {
+            RK_U32 cbcr_ver_coe2_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe2_7  : 10;
+        } reg11;         /* 0x062c */
+        struct {
+            RK_U32 cbcr_ver_coe3_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe3_1  : 10;
+        } reg12;         /* 0x0630 */
+        struct {
+            RK_U32 cbcr_ver_coe3_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe3_3  : 10;
+        } reg13;         /* 0x0634 */
+        struct {
+            RK_U32 cbcr_ver_coe3_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe3_5  : 10;
+        } reg14;         /* 0x0638 */
+        struct {
+            RK_U32 cbcr_ver_coe3_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe3_7  : 10;
+        } reg15;         /* 0x063c */
+        struct {
+            RK_U32 cbcr_ver_coe4_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe4_1  : 10;
+        } reg16;         /* 0x0640 */
+        struct {
+            RK_U32 cbcr_ver_coe4_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe4_3  : 10;
+        } reg17;         /* 0x0644 */
+        struct {
+            RK_U32 cbcr_ver_coe4_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe4_5  : 10;
+        } reg18;         /* 0x0648 */
+        struct {
+            RK_U32 cbcr_ver_coe4_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe4_7  : 10;
+        } reg19;         /* 0x064c */
+        struct {
+            RK_U32 cbcr_ver_coe5_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe5_1  : 10;
+        } reg20;         /* 0x0650 */
+        struct {
+            RK_U32 cbcr_ver_coe5_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe5_3  : 10;
+        } reg21;         /* 0x0654 */
+        struct {
+            RK_U32 cbcr_ver_coe5_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe5_5  : 10;
+        } reg22;         /* 0x0658 */
+        struct {
+            RK_U32 cbcr_ver_coe5_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe5_7  : 10;
+        } reg23;         /* 0x065c */
+        struct {
+            RK_U32 cbcr_ver_coe6_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe6_1  : 10;
+        } reg24;         /* 0x0660 */
+        struct {
+            RK_U32 cbcr_ver_coe6_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe6_3  : 10;
+        } reg25;         /* 0x0664 */
+        struct {
+            RK_U32 cbcr_ver_coe6_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe6_5  : 10;
+        } reg26;         /* 0x0668 */
+        struct {
+            RK_U32 cbcr_ver_coe6_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe6_7  : 10;
+        } reg27;         /* 0x066c */
+        struct {
+            RK_U32 cbcr_ver_coe7_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe7_1  : 10;
+        } reg28;         /* 0x0670 */
+        struct {
+            RK_U32 cbcr_ver_coe7_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe7_3  : 10;
+        } reg29;         /* 0x0674 */
+        struct {
+            RK_U32 cbcr_ver_coe7_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe7_5  : 10;
+        } reg30;         /* 0x0678 */
+        struct {
+            RK_U32 cbcr_ver_coe7_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe7_7  : 10;
+        } reg31;         /* 0x067c */
+        struct {
+            RK_U32 cbcr_ver_coe8_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe8_1  : 10;
+        } reg32;         /* 0x0680 */
+        struct {
+            RK_U32 cbcr_ver_coe8_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe8_3  : 10;
+        } reg33;         /* 0x0684 */
+        struct {
+            RK_U32 cbcr_ver_coe8_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe8_5  : 10;
+        } reg34;         /* 0x0688 */
+        struct {
+            RK_U32 cbcr_ver_coe8_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe8_7  : 10;
+        } reg35;         /* 0x068c */
+        struct {
+            RK_U32 cbcr_ver_coe9_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe9_1  : 10;
+        } reg36;         /* 0x0690 */
+        struct {
+            RK_U32 cbcr_ver_coe9_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe9_3  : 10;
+        } reg37;         /* 0x0694 */
+        struct {
+            RK_U32 cbcr_ver_coe9_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe9_5  : 10;
+        } reg38;         /* 0x0698 */
+        struct {
+            RK_U32 cbcr_ver_coe9_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe9_7  : 10;
+        } reg39;         /* 0x069c */
+        struct {
+            RK_U32 cbcr_ver_coe10_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe10_1  : 10;
+        } reg40;         /* 0x06a0 */
+        struct {
+            RK_U32 cbcr_ver_coe10_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe10_3  : 10;
+        } reg41;         /* 0x06a4 */
+        struct {
+            RK_U32 cbcr_ver_coe10_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe10_5  : 10;
+        } reg42;         /* 0x06a8 */
+        struct {
+            RK_U32 cbcr_ver_coe10_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe10_7  : 10;
+        } reg43;         /* 0x06ac */
+        struct {
+            RK_U32 cbcr_ver_coe11_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe11_1  : 10;
+        } reg44;         /* 0x06b0 */
+        struct {
+            RK_U32 cbcr_ver_coe11_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe11_3  : 10;
+        } reg45;         /* 0x06b4 */
+        struct {
+            RK_U32 cbcr_ver_coe11_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe11_5  : 10;
+        } reg46;         /* 0x06b8 */
+        struct {
+            RK_U32 cbcr_ver_coe11_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe11_7  : 10;
+        } reg47;         /* 0x06bc */
+        struct {
+            RK_U32 cbcr_ver_coe12_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe12_1  : 10;
+        } reg48;         /* 0x06c0 */
+        struct {
+            RK_U32 cbcr_ver_coe12_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe12_3  : 10;
+        } reg49;         /* 0x06c4 */
+        struct {
+            RK_U32 cbcr_ver_coe12_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe12_5  : 10;
+        } reg50;         /* 0x06c8 */
+        struct {
+            RK_U32 cbcr_ver_coe12_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe12_7  : 10;
+        } reg51;         /* 0x06cc */
+        struct {
+            RK_U32 cbcr_ver_coe13_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe13_1  : 10;
+        } reg52;         /* 0x06d0 */
+        struct {
+            RK_U32 cbcr_ver_coe13_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe13_3  : 10;
+        } reg53;         /* 0x06d4 */
+        struct {
+            RK_U32 cbcr_ver_coe13_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe13_5  : 10;
+        } reg54;         /* 0x06d8 */
+        struct {
+            RK_U32 cbcr_ver_coe13_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe13_7  : 10;
+        } reg55;         /* 0x06dc */
+        struct {
+            RK_U32 cbcr_ver_coe14_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe14_1  : 10;
+        } reg56;         /* 0x06e0 */
+        struct {
+            RK_U32 cbcr_ver_coe14_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe14_3  : 10;
+        } reg57;         /* 0x06e4 */
+        struct {
+            RK_U32 cbcr_ver_coe14_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe14_5  : 10;
+        } reg58;         /* 0x06e8 */
+        struct {
+            RK_U32 cbcr_ver_coe14_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe14_7  : 10;
+        } reg59;         /* 0x06ec */
+        struct {
+            RK_U32 cbcr_ver_coe15_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe15_1  : 10;
+        } reg60;         /* 0x06f0 */
+        struct {
+            RK_U32 cbcr_ver_coe15_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe15_3  : 10;
+        } reg61;         /* 0x06f4 */
+        struct {
+            RK_U32 cbcr_ver_coe15_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe15_5  : 10;
+        } reg62;         /* 0x06f8 */
+        struct {
+            RK_U32 cbcr_ver_coe15_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe15_7  : 10;
+        } reg63;         /* 0x06fc */
+        struct {
+            RK_U32 cbcr_ver_coe16_0  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe16_1  : 10;
+        } reg64;         /* 0x0700 */
+        struct {
+            RK_U32 cbcr_ver_coe16_2  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe16_3  : 10;
+        } reg65;         /* 0x0704 */
+        struct {
+            RK_U32 cbcr_ver_coe16_4  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe16_5  : 10;
+        } reg66;         /* 0x0708 */
+        struct {
+            RK_U32 cbcr_ver_coe16_6  : 10;
+            RK_U32 sw_reserved_1    : 6;
+            RK_U32 cbcr_ver_coe16_7  : 10;
+        } reg67;         /* 0x070c */
+
+    } cbcr_ver_coe;
+
+    struct {
+        struct {
+            RK_U32 bypass_en        : 1;
+            RK_U32 align_en         : 1;
+            RK_U32 reserved_1       : 2;
+            RK_U32 format_in        : 4;
+            RK_U32 format_out       : 4;
+            RK_U32 reserved_2       : 19;
+            RK_U32 auto_gating_en   : 1;
+        } reg0;         /* 0x0800 */
+
+        RK_U32 reg1;    /* 0x0804 */
+        RK_U32 reg2;    /* 0x0808 */
+
+        struct {
+            RK_U32 vir_width        : 16;
+            RK_U32 vir_height       : 16;
+        } reg3;         /* 0x080C */
+
+        struct {
+            RK_U32 yrgb_xsd_en      : 1;
+            RK_U32 yrgb_xsu_en      : 1;
+            RK_U32 yrgb_scl_mode    : 2;
+            RK_U32 yrgb_ysd_en      : 1;
+            RK_U32 yrgb_ysu_en      : 1;
+            RK_U32 yrgb_yscl_mode   : 2;
+            RK_U32 yrgb_dering_en   : 1;
+            RK_U32 yrgb_gt_en       : 1;
+            RK_U32 yrgb_gt_mode     : 2;
+            RK_U32 yrgb_xgt_en      : 1;
+            RK_U32 reserved_1       : 1;
+            RK_U32 yrgb_xgt_mode    : 2;
+            RK_U32 yrgb_xsd_bypass  : 1;
+            RK_U32 yrgb_ys_bypass   : 1;
+            RK_U32 yrgb_xsu_bypass  : 1;
+        } reg4;         /* 0x0810 */
+
+        struct {
+            RK_U32 yrgb_src_width   : 16;
+            RK_U32 yrgb_src_height  : 16;
+        } reg5;         /* 0x0814 */
+
+        struct {
+            RK_U32 yrgb_dst_width   : 16;
+            RK_U32 yrgb_dst_height  : 16;
+        } reg6;         /* 0x0818 */
+
+        struct {
+            RK_U32 yrgb_dering_sen0 : 5;
+            RK_U32 reserved_1       : 3;
+            RK_U32 yrgb_dering_sen1 : 5;
+            RK_U32 reserved_2       : 3;
+            RK_U32 yrgb_dering_alpha: 5;
+            RK_U32 reserved_3       : 3;
+            RK_U32 yrgb_dering_delta: 5;
+        } reg7;         /* 0x081C */
+
+        struct {
+            RK_U32 yrgb_xscl_factor : 16;
+            RK_U32 yrgb_xscl_offset : 16;
+        } reg8;         /* 0x0820 */
+
+        struct {
+            RK_U32 yrgb_yscl_factor : 16;
+            RK_U32 yrgb_yscl_offset : 16;
+        } reg9;         /* 0x0824 */
+
+        RK_U32 reg10;   /* 0x0828 */
+        RK_U32 reg11;   /* 0x082C */
+
+        struct {
+            RK_U32 cbcr_xsd_en      : 1;
+            RK_U32 cbcr_xsu_en      : 1;
+            RK_U32 cbcr_scl_mode    : 2;
+            RK_U32 cbcr_ysd_en      : 1;
+            RK_U32 cbcr_ysu_en      : 1;
+            RK_U32 cbcr_yscl_mode   : 2;
+            RK_U32 cbcr_dering_en   : 1;
+            RK_U32 cbcr_gt_en       : 1;
+            RK_U32 cbcr_gt_mode     : 2;
+            RK_U32 cbcr_xgt_en      : 1;
+            RK_U32 reserved_1       : 1;
+            RK_U32 cbcr_xgt_mode    : 2;
+            RK_U32 cbcr_xsd_bypass  : 1;
+            RK_U32 cbcr_ys_bypass   : 1;
+            RK_U32 cbcr_xsu_bypass  : 1;
+        } reg12;         /* 0x0830 */
+
+        struct {
+            RK_U32 cbcr_src_width   : 16;
+            RK_U32 cbcr_src_height  : 16;
+        } reg13;         /* 0x0834 */
+
+        struct {
+            RK_U32 cbcr_dst_width   : 16;
+            RK_U32 cbcr_dst_height  : 16;
+        } reg14;         /* 0x0838 */
+
+        struct {
+            RK_U32 cbcr_dering_sen0 : 5;
+            RK_U32 reserved_1       : 3;
+            RK_U32 cbcr_dering_sen1 : 5;
+            RK_U32 reserved_2       : 3;
+            RK_U32 cbcr_dering_alpha: 5;
+            RK_U32 reserved_3       : 3;
+            RK_U32 cbcr_dering_delta: 5;
+        } reg15;         /* 0x083C */
+
+        struct {
+            RK_U32 cbcr_xscl_factor : 16;
+            RK_U32 cbcr_xscl_offset : 16;
+        } reg16;         /* 0x0840 */
+
+        struct {
+            RK_U32 cbcr_yscl_factor : 16;
+            RK_U32 cbcr_yscl_offset : 16;
+        } reg17;         /* 0x0844 */
+
+    } common;
+
+};               /* offset: 0x2000 */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void set_dmsr_to_vdpp_reg(struct dmsr_params* p_dmsr_param, struct dmsr_reg* dmsr);
+
+void vdpp_set_default_zme_param(struct zme_params* param);
+void set_zme_to_vdpp_reg(struct zme_params *zme_params, struct zme_reg *zme);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/mpp/vproc/vdpp/vdpp_reg.h b/mpp/vproc/vdpp/vdpp_reg.h
new file mode 100644
index 000000000..a2d248d8c
--- /dev/null
+++ b/mpp/vproc/vdpp/vdpp_reg.h
@@ -0,0 +1,174 @@
+/* SPDX-License-Identifier: Apache-2.0 OR MIT */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef __VDPP_REG_H__
+#define __VDPP_REG_H__
+
+#include "rk_type.h"
+
+#define VDPP_REG_OFF_DMSR               (0x80)
+#define VDPP_REG_OFF_YRGB_HOR_COE       (0x2000)
+#define VDPP_REG_OFF_YRGB_VER_COE       (0x2200)
+#define VDPP_REG_OFF_CBCR_HOR_COE       (0x2400)
+#define VDPP_REG_OFF_CBCR_VER_COE       (0x2600)
+#define VDPP_REG_OFF_ZME_COMMON         (0x2800)
+
+struct vdpp_reg {
+    struct {
+
+        struct {
+            RK_U32 sw_vdpp_frm_en       : 1;
+        } reg0;         // 0x0000
+
+        struct {
+            RK_U32 sw_vdpp_src_fmt      : 2;
+            RK_U32 sw_reserved_1        : 2;
+            RK_U32 sw_vdpp_src_yuv_swap : 2;
+            RK_U32 sw_reserved_2        : 2;
+            RK_U32 sw_vdpp_dst_fmt      : 2;
+            RK_U32 sw_reserved_3        : 2;
+            RK_U32 sw_vdpp_dst_yuv_swap : 2;
+            RK_U32 sw_reserved_4        : 2;
+            RK_U32 sw_vdpp_debug_data_en: 1;
+            RK_U32 sw_reserved_5        : 3;
+            RK_U32 sw_vdpp_rst_protect_dis      : 1;
+            RK_U32 sys_vdpp_sreset_p    : 1;
+            RK_U32 sw_vdpp_init_dis     : 1;
+            RK_U32 sw_reserved_6        : 1;
+            RK_U32 sw_vdpp_dbmsr_en     : 1;
+        } reg1;         // 0x0004
+
+        struct {
+            RK_U32 sw_vdpp_working_mode : 2;
+        } reg2;         // 0x0008
+
+        RK_U32 reg3;    // 0x000C
+
+        struct {
+            RK_U32 sw_vdpp_clk_on       : 1;
+            RK_U32 sw_md_clk_on         : 1;
+            RK_U32 sw_dect_clk_on       : 1;
+            RK_U32 sw_me_clk_on         : 1;
+            RK_U32 sw_mc_clk_on         : 1;
+            RK_U32 sw_eedi_clk_on       : 1;
+            RK_U32 sw_ble_clk_on        : 1;
+            RK_U32 sw_out_clk_on        : 1;
+            RK_U32 sw_ctrl_clk_on       : 1;
+            RK_U32 sw_ram_clk_on        : 1;
+            RK_U32 sw_dma_clk_on        : 1;
+            RK_U32 sw_reg_clk_on        : 1;
+        } reg4;         // 0x0010
+
+        struct {
+            RK_U32 ro_arst_finish_done  : 1;
+        } reg5;         // 0x0014
+
+        RK_U32 reg6;    // 0x0018
+        RK_U32 reg7;    // 0x001c
+
+        struct {
+            RK_U32 sw_vdpp_frm_done_en  : 1;
+            RK_U32 sw_vdpp_osd_max_en   : 1;
+            RK_U32 sw_reserved_1        : 2;
+            RK_U32 sw_vdpp_bus_error_en : 1;
+            RK_U32 sw_vdpp_timeout_int_en       : 1;
+            RK_U32 sw_vdpp_config_error_en      : 1;
+        } reg8;         // 0x0020
+
+        struct {
+            RK_U32 sw_vdpp_frm_done_clr : 1;
+            RK_U32 sw_vdpp_osd_max_clr  : 1;
+            RK_U32 sw_reserved_1        : 2;
+            RK_U32 sw_vdpp_bus_error_clr: 1;
+            RK_U32 sw_vdpp_timeout_int_clr      : 1;
+            RK_U32 sw_vdpp_config_error_clr     : 1;
+        } reg9;        // 0x0024
+
+        struct {
+            RK_U32 ro_frm_done_sts      : 1;
+            RK_U32 ro_osd_max_sts       : 1;
+            RK_U32 sw_reserved_1        : 2;
+            RK_U32 ro_bus_error_sts     : 1;
+            RK_U32 ro_timeout_sts       : 1;
+            RK_U32 ro_config_error_sts  : 1;
+        } reg10;        // 0x0028, read only
+
+        struct {
+            RK_U32 ro_frm_done_raw      : 1;
+            RK_U32 ro_osd_max_raw       : 1;
+            RK_U32 sw_reserved_1        : 2;
+            RK_U32 ro_bus_error_raw     : 1;
+            RK_U32 ro_timeout_raw       : 1;
+            RK_U32 ro_config_error_raw  : 1;
+        } reg11;        // 0x002C, read only
+
+        struct {
+            RK_U32 sw_vdpp_src_vir_y_stride     : 16;
+        } reg12;         // 0x0030
+
+        struct {
+            RK_U32 sw_vdpp_dst_vir_y_stride     : 16;
+        } reg13;         // 0x0034
+
+        struct {
+            RK_U32 sw_vdpp_src_pic_width        : 11;
+            RK_U32 sw_reserved_1        : 1;
+            RK_U32 sw_vdpp_src_right_redundant  : 4;
+            RK_U32 sw_vdpp_src_pic_height       : 11;
+            RK_U32 sw_reserved_2        : 1;
+            RK_U32 sw_vdpp_src_down_redundant   : 3;
+        } reg14;         // 0x0038
+
+        struct {
+            RK_U32 sw_vdpp_dst_pic_width        : 11;
+            RK_U32 sw_reserved_1        : 1;
+            RK_U32 sw_vdpp_dst_right_redundant  : 4;
+            RK_U32 sw_vdpp_dst_pic_height       : 11;
+        } reg15;         // 0x003C
+
+        RK_U32 reg16;    // 0x0040
+        RK_U32 reg17;    // 0x0044
+        RK_U32 reg18;    // 0x0048
+        RK_U32 reg19;    // 0x004C
+
+        struct {
+            RK_U32 sw_vdpp_timeout_cnt  : 31;
+            RK_U32 sw_vdpp_timeout_en   : 1;
+        } reg20;         // 0x0050
+
+        struct {
+            RK_U32 svnbuild     : 20;
+            RK_U32 minor        : 8;
+            RK_U32 major        : 4;
+        } reg21;         // 0x0054
+
+        struct {
+            RK_U32 dbg_frm_cnt  : 16;
+        } reg22;         // 0x0058
+
+        RK_U32 reg23;    // 0x005C
+
+        struct {
+            RK_U32 sw_vdpp_src_addr_y   : 32;
+        } reg24;         // 0x0060
+
+        struct {
+            RK_U32 sw_vdpp_src_addr_uv  : 32;
+        } reg25;         // 0x0064
+
+        struct {
+            RK_U32 sw_vdpp_dst_addr_y   : 32;
+        } reg26;         // 0x0068
+
+        struct {
+            RK_U32 sw_vdpp_dst_addr_uv  : 32;
+        } reg27;         // 0x006C
+
+    } common;            // offset: 0x1000
+    RK_U32 reg_common_28_31[4];
+
+};
+
+#endif
diff --git a/osal/allocator/allocator_drm.c b/osal/allocator/allocator_drm.c
index 9bed02fa1..415dc9bbb 100644
--- a/osal/allocator/allocator_drm.c
+++ b/osal/allocator/allocator_drm.c
@@ -69,7 +69,11 @@ typedef struct {
     RK_U32  flags;
 } allocator_ctx_drm;
 
-static const char *dev_drm = "/dev/dri/card0";
+/* use renderD128 first to avoid GKI kernel permission issue */
+static const char *dev_drm[] = {
+    "/dev/dri/renderD128",
+    "/dev/dri/card0",
+};
 
 static RK_U32 to_rockchip_gem_mem_flag(RK_U32 flags)
 {
@@ -164,8 +168,9 @@ static int drm_free(int fd, RK_U32 handle)
 
 static MPP_RET os_allocator_drm_open(void **ctx, size_t alignment, MppAllocFlagType flags)
 {
-    RK_S32 fd;
     allocator_ctx_drm *p;
+    RK_S32 fd;
+    RK_S32 i;
 
     if (NULL == ctx) {
         mpp_err_f("does not accept NULL input\n");
@@ -176,9 +181,17 @@ static MPP_RET os_allocator_drm_open(void **ctx, size_t alignment, MppAllocFlagT
 
     mpp_env_get_u32("drm_debug", &drm_debug, 0);
 
-    fd = open(dev_drm, O_RDWR | O_CLOEXEC);
+    for (i = 0; i < (RK_S32)MPP_ARRAY_ELEMS(dev_drm); i++) {
+        fd = open(dev_drm[i], O_RDWR | O_CLOEXEC);
+        if (fd > 0)
+            break;
+    }
+
     if (fd < 0) {
-        mpp_err_f("open %s failed!\n", dev_drm);
+        mpp_err_f("open all drm device failed.\n");
+        mpp_err("Please check the following device path and access permission:\n");
+        for (i = 0; i < (RK_S32)MPP_ARRAY_ELEMS(dev_drm); i++)
+            mpp_err("%s\n", dev_drm[i]);
         return MPP_ERR_UNKNOW;
     }
 
diff --git a/osal/allocator/allocator_ext_dma.c b/osal/allocator/allocator_ext_dma.c
index b3aeb1024..482470aef 100644
--- a/osal/allocator/allocator_ext_dma.c
+++ b/osal/allocator/allocator_ext_dma.c
@@ -19,6 +19,7 @@
 
 #include "mpp_mem.h"
 #include "mpp_debug.h"
+#include "mpp_common.h"
 
 #include "allocator_ext_dma.h"
 
@@ -87,6 +88,7 @@ static MPP_RET allocator_ext_dma_import(void *ctx, MppBufferInfo *info)
 static MPP_RET allocator_ext_dma_mmap(void *ctx, MppBufferInfo *info)
 {
     void *ptr = NULL;
+    int flags = 0;
     unsigned long offset = 0L;
     mpp_assert(ctx);
     mpp_assert(info->size);
@@ -99,8 +101,11 @@ static MPP_RET allocator_ext_dma_mmap(void *ctx, MppBufferInfo *info)
      * It is insecure to access the first memory page,
      * usually system doesn't allow this behavior.
      */
-    ptr = mmap(NULL, info->size, PROT_READ | PROT_WRITE,
-               MAP_SHARED, info->fd, offset);
+    flags = PROT_READ;
+    if (fcntl(info->fd, F_GETFL) & O_RDWR)
+        flags |= PROT_WRITE;
+
+    ptr = mmap(NULL, info->size, flags, MAP_SHARED, info->fd, offset);
     if (ptr == MAP_FAILED)
         return MPP_ERR_NULL_PTR;
 
diff --git a/osal/driver/inc/mpp_device_debug.h b/osal/driver/inc/mpp_device_debug.h
index 1f018e0b1..951dabce0 100644
--- a/osal/driver/inc/mpp_device_debug.h
+++ b/osal/driver/inc/mpp_device_debug.h
@@ -25,6 +25,7 @@
 #define MPP_DEVICE_DBG_REG                  (0x00000010)
 #define MPP_DEVICE_DBG_TIME                 (0x00000020)
 #define MPP_DEVICE_DBG_MSG                  (0x00000040)
+#define MPP_DEVICE_DBG_BUF                  (0x00000080)
 
 #define mpp_dev_dbg(flag, fmt, ...)         _mpp_dbg(mpp_device_debug, flag, fmt, ## __VA_ARGS__)
 #define mpp_dev_dbg_f(flag, fmt, ...)       _mpp_dbg_f(mpp_device_debug, flag, fmt, ## __VA_ARGS__)
@@ -35,6 +36,7 @@
 #define mpp_dev_dbg_reg(fmt, ...)           mpp_dev_dbg(MPP_DEVICE_DBG_REG, fmt, ## __VA_ARGS__)
 #define mpp_dev_dbg_time(fmt, ...)          mpp_dev_dbg(MPP_DEVICE_DBG_TIME, fmt, ## __VA_ARGS__)
 #define mpp_dev_dbg_msg(fmt, ...)           mpp_dev_dbg(MPP_DEVICE_DBG_MSG, fmt, ## __VA_ARGS__)
+#define mpp_dev_dbg_buf(fmt, ...)           mpp_dev_dbg(MPP_DEVICE_DBG_BUF, fmt, ## __VA_ARGS__)
 
 extern RK_U32 mpp_device_debug;
 
diff --git a/osal/driver/inc/mpp_service_impl.h b/osal/driver/inc/mpp_service_impl.h
index 063df4e0e..a8e4c9edf 100644
--- a/osal/driver/inc/mpp_service_impl.h
+++ b/osal/driver/inc/mpp_service_impl.h
@@ -17,6 +17,8 @@
 #ifndef __MPP_SERVICE_IMPL_H__
 #define __MPP_SERVICE_IMPL_H__
 
+#include "mpp_list.h"
+
 #include "mpp_device.h"
 #include "mpp_service.h"
 
@@ -66,6 +68,9 @@ typedef struct MppDevMppService_t {
     RK_U32          support_set_info;
     RK_U32          support_set_rcb_info;
     RK_U32          support_hw_irq;
+
+    pthread_mutex_t     lock_bufs;
+    struct list_head    list_bufs;
 } MppDevMppService;
 
 #ifdef  __cplusplus
diff --git a/osal/driver/mpp_device.c b/osal/driver/mpp_device.c
index 0f46fd4ed..54cb1302c 100644
--- a/osal/driver/mpp_device.c
+++ b/osal/driver/mpp_device.c
@@ -166,6 +166,22 @@ MPP_RET mpp_dev_ioctl(MppDev ctx, RK_S32 cmd, void *param)
         if (api->set_err_ref_hack)
             ret = api->set_err_ref_hack(impl_ctx, param);
     } break;
+    case MPP_DEV_LOCK_MAP : {
+        if (api->lock_map)
+            ret = api->lock_map(impl_ctx);
+    } break;
+    case MPP_DEV_UNLOCK_MAP : {
+        if (api->unlock_map)
+            ret = api->unlock_map(impl_ctx);
+    } break;
+    case MPP_DEV_ATTACH_FD : {
+        if (api->attach_fd)
+            ret = api->attach_fd(impl_ctx, param);
+    } break;
+    case MPP_DEV_DETACH_FD : {
+        if (api->detach_fd)
+            ret = api->detach_fd(impl_ctx, param);
+    } break;
     case MPP_DEV_CMD_SEND : {
         if (api->cmd_send)
             ret = api->cmd_send(impl_ctx);
diff --git a/osal/driver/mpp_service.c b/osal/driver/mpp_service.c
index 000f2539e..726efcf21 100644
--- a/osal/driver/mpp_service.c
+++ b/osal/driver/mpp_service.c
@@ -261,6 +261,49 @@ RcbInfo *mpp_service_next_rcb_info(MppDevMppService *p)
     return info;
 }
 
+static MPP_RET mpp_service_ioc_attach_fd(MppDevBufMapNode *node)
+{
+    MppReqV1 mpp_req;
+    RK_S32 fd = node->buf_fd;
+    MPP_RET ret;
+
+    mpp_req.cmd = MPP_CMD_TRANS_FD_TO_IOVA;
+    mpp_req.flag = MPP_FLAGS_LAST_MSG;
+    mpp_req.size = sizeof(RK_U32);
+    mpp_req.offset = 0;
+    mpp_req.data_ptr = REQ_DATA_PTR(&fd);
+
+    ret = mpp_service_ioctl_request(node->dev_fd, &mpp_req);
+    if (ret) {
+        mpp_err_f("failed ret %d errno %d %s\n", ret, errno, strerror(errno));
+        node->iova = (RK_U32)(-1);
+    } else {
+        node->iova = (RK_U32)fd;
+    }
+
+    return ret;
+}
+
+static MPP_RET mpp_service_ioc_detach_fd(MppDevBufMapNode *node)
+{
+    RK_S32 fd = node->buf_fd;
+    MppReqV1 mpp_req;
+    MPP_RET ret;
+
+    mpp_req.cmd = MPP_CMD_RELEASE_FD;
+    mpp_req.flag = MPP_FLAGS_LAST_MSG;
+    mpp_req.size = sizeof(RK_U32);
+    mpp_req.offset = 0;
+    mpp_req.data_ptr = REQ_DATA_PTR(&fd);
+
+    ret = mpp_service_ioctl_request(node->dev_fd, &mpp_req);
+    if (ret) {
+        mpp_err_f("failed ret %d errno %d %s\n", ret, errno, strerror(errno));
+    }
+    node->iova = (RK_U32)(-1);
+    return ret;
+}
+
 MPP_RET mpp_service_init(void *ctx, MppClientType type)
 {
     MppDevMppService *p = (MppDevMppService *)ctx;
@@ -282,8 +325,10 @@ MPP_RET mpp_service_init(void *ctx, MppClientType type)
     if (MPP_OK == mpp_service_check_cmd_valid(MPP_CMD_SEND_CODEC_INFO, p->cap))
         p->support_set_info = 1;
     if (MPP_OK == mpp_service_check_cmd_valid(MPP_CMD_SET_RCB_INFO, p->cap)) {
-        p->support_set_rcb_info = 1;
-        mpp_env_get_u32("disable_rcb_info", &p->support_set_rcb_info, 1);
+        RK_U32 disable_rcb_info = 0;
+
+        mpp_env_get_u32("disable_rcb_info", &disable_rcb_info, 0);
+        p->support_set_rcb_info = !disable_rcb_info;
     }
     if (MPP_OK == mpp_service_check_cmd_valid(MPP_CMD_POLL_HW_IRQ, p->cap))
         p->support_hw_irq = 1;
@@ -324,12 +369,42 @@ MPP_RET mpp_service_init(void *ctx, MppClientType type)
     p->rcb_pos = 0;
     p->rcb_count = 0;
 
+    INIT_LIST_HEAD(&p->list_bufs);
+    {
+        pthread_mutexattr_t attr;
+        pthread_mutexattr_init(&attr);
+        pthread_mutexattr_settype(&attr, PTHREAD_MUTEX_RECURSIVE);
+        pthread_mutex_init(&p->lock_bufs, &attr);
+        pthread_mutexattr_destroy(&attr);
+    }
     return ret;
 }
 
 MPP_RET mpp_service_deinit(void *ctx)
 {
     MppDevMppService *p = (MppDevMppService *)ctx;
+    MppDevBufMapNode *pos, *n;
+
+    pthread_mutex_lock(&p->lock_bufs);
+    list_for_each_entry_safe(pos, n, &p->list_bufs, MppDevBufMapNode, list_dev) {
+        pthread_mutex_t *lock_buf = pos->lock_buf;
+
+        mpp_assert(pos->lock_buf && pos->lock_dev);
+        mpp_assert(pos->lock_dev == &p->lock_bufs);
+
+        pthread_mutex_lock(lock_buf);
+
+        list_del_init(&pos->list_dev);
+        list_del_init(&pos->list_buf);
+        pos->lock_buf = NULL;
+        pos->lock_dev = NULL;
+        mpp_service_ioc_detach_fd(pos);
+        mpp_mem_pool_put_f(__FUNCTION__, pos->pool, pos);
+
+        pthread_mutex_unlock(lock_buf);
+    }
+    pthread_mutex_unlock(&p->lock_bufs);
+    pthread_mutex_destroy(&p->lock_bufs);
 
     if (p->batch_io)
         mpp_server_detach(p);
@@ -572,6 +647,73 @@ MPP_RET mpp_service_set_err_ref_hack(void *ctx, RK_U32 *enable)
     return mpp_service_ioctl_request(p->client, &mpp_req);
 }
 
+MPP_RET mpp_service_lock_map(void *ctx)
+{
+    MppDevMppService *p = (MppDevMppService *)ctx;
+
+    mpp_dev_dbg_buf("dev %d lock mapping\n", p->client);
+    pthread_mutex_lock(&p->lock_bufs);
+    return MPP_OK;
+}
+
+MPP_RET mpp_service_unlock_map(void *ctx)
+{
+    MppDevMppService *p = (MppDevMppService *)ctx;
+
+    mpp_dev_dbg_buf("dev %d unlock mapping\n", p->client);
+    pthread_mutex_unlock(&p->lock_bufs);
+    return MPP_OK;
+}
+
+MPP_RET mpp_service_attach_fd(void *ctx, MppDevBufMapNode *node)
+{
+    MppDevMppService *p = (MppDevMppService *)ctx;
+    MPP_RET ret;
+
+    mpp_assert(node->buffer);
+    mpp_assert(node->lock_buf);
+    mpp_assert(node->buf_fd >= 0);
+
+    node->lock_dev = &p->lock_bufs;
+    node->dev_fd = p->client;
+    ret = mpp_service_ioc_attach_fd(node);
+    if (ret) {
+        node->lock_dev = NULL;
+        node->dev_fd = -1;
+        list_del_init(&node->list_dev);
+    } else {
+        list_add_tail(&node->list_dev, &p->list_bufs);
+    }
+
+    mpp_dev_dbg_buf("node %p dev %d attach fd %d iova %x\n",
+                    node, node->dev_fd, node->buf_fd, node->iova);
+
+    return ret;
+}
+
+MPP_RET mpp_service_detach_fd(void *ctx, MppDevBufMapNode *node)
+{
+    MppDevMppService *p = (MppDevMppService *)ctx;
+    MPP_RET ret;
+
+    mpp_assert(node->buffer);
+    mpp_assert(node->lock_buf);
+    mpp_assert(node->buf_fd >= 0);
+    mpp_assert(node->dev_fd >= 0);
+    mpp_assert(node->lock_dev == &p->lock_bufs);
+
+    mpp_dev_dbg_buf("node %p dev %d detach fd %d iova %x\n",
+                    node, node->dev_fd, node->buf_fd, node->iova);
+
+    ret = mpp_service_ioc_detach_fd(node);
+    node->dev = NULL;
+    node->dev_fd = -1;
+    node->lock_dev = NULL;
+    list_del_init(&node->list_dev);
+
+    return ret;
+}
+
 MPP_RET mpp_service_cmd_send(void *ctx)
 {
     MPP_RET ret = MPP_OK;
@@ -714,6 +856,10 @@ const MppDevApi mpp_service_api = {
     mpp_service_rcb_info,
     mpp_service_set_info,
     mpp_service_set_err_ref_hack,
+    mpp_service_lock_map,
+    mpp_service_unlock_map,
+    mpp_service_attach_fd,
+    mpp_service_detach_fd,
     mpp_service_cmd_send,
     mpp_service_cmd_poll,
 };
diff --git a/osal/driver/vcodec_service.c b/osal/driver/vcodec_service.c
index 5c7561e3e..2064e2bad 100644
--- a/osal/driver/vcodec_service.c
+++ b/osal/driver/vcodec_service.c
@@ -129,6 +129,10 @@ static const char *mpp_jpegd_dev[] = {
     "/dev/mpp_service",
 };
 
+static const char *mpp_jpege_dev[] = {
+    "/dev/mpp_service",
+};
+
 #define mpp_find_device(dev) _mpp_find_device(dev, MPP_ARRAY_ELEMS(dev))
 
 static const char *_mpp_find_device(const char **dev, RK_U32 size)
@@ -393,6 +397,19 @@ const char *mpp_get_vcodec_dev_name(MppCtxType type, MppCodingType coding)
                 dev = NULL;
         }
     } break;
+    case ROCKCHIP_SOC_RK3576 : {
+        if (type == MPP_CTX_DEC) {
+            if (coding == MPP_VIDEO_CodingMJPEG)
+                dev = mpp_find_device(mpp_jpegd_dev);
+            else
+                dev = mpp_find_device(mpp_rkvdec_dev);
+        } else if (type == MPP_CTX_ENC) {
+            if (coding == MPP_VIDEO_CodingMJPEG)
+                dev = mpp_find_device(mpp_jpege_dev);
+            else
+                dev = mpp_find_device(mpp_rkvenc_dev);
+        }
+    } break;
     default : {
         /* default case for unknown compatible  */
         RK_U32 vcodec_type = mpp_get_vcodec_type();
@@ -471,7 +488,10 @@ MPP_RET vcodec_service_init(void *ctx, MppClientType type)
     case VPU_CLIENT_VDPU1_PP : {
         name = mpp_find_device(mpp_vpu_dev);
         client_type = VPU_DEC_PP;
-        reg_size = VDPU1_PP_REGISTERS;
+        if (ROCKCHIP_SOC_RK3036 == mpp_get_soc_type())
+            reg_size = VDPU1_REGISTERS;
+        else
+            reg_size = VDPU1_PP_REGISTERS;
     } break;
     case VPU_CLIENT_VDPU2_PP : {
         name = mpp_find_device(mpp_vpu_dev);
@@ -598,7 +618,7 @@ MPP_RET vcodec_service_reg_rd(void *ctx, MppDevRegRdCfg *cfg)
     return MPP_OK;
 }
 
-MPP_RET vcodec_service_fd_trans(void *ctx, MppDevRegOffsetCfg *cfg)
+MPP_RET vcodec_service_reg_offset(void *ctx, MppDevRegOffsetCfg *cfg)
 {
     if (cfg->offset) {
         MppDevVcodecService *p = (MppDevVcodecService *)ctx;
@@ -707,11 +727,15 @@ const MppDevApi vcodec_service_api = {
     NULL,
     vcodec_service_reg_wr,
     vcodec_service_reg_rd,
-    vcodec_service_fd_trans,
+    vcodec_service_reg_offset,
     NULL,
     NULL,
     vcodec_service_set_info,
     NULL,
+    NULL,
+    NULL,
+    NULL,
+    NULL,
     vcodec_service_cmd_send,
     vcodec_service_cmd_poll,
 };
diff --git a/osal/inc/mpp_common.h b/osal/inc/mpp_common.h
index 60a0b20fd..0ca67e257 100644
--- a/osal/inc/mpp_common.h
+++ b/osal/inc/mpp_common.h
@@ -44,6 +44,8 @@
 #define MPP_ALIGN_GEN(x, a)     (((x)+(a)-1)/(a)*(a))
 #define MPP_VSWAP(a, b)         { a ^= b; b ^= a; a ^= b; }
 
+#define MPP_GENMASK(h, l) (((1ULL << ((h) + 1)) - 1) & ~((1ULL << (l)) - 1))
+
 #define MPP_RB16(x)  ((((const RK_U8*)(x))[0] << 8) | ((const RK_U8*)(x))[1])
 #define MPP_WB16(p, d) do { \
         ((RK_U8*)(p))[1] = (d); \
@@ -216,7 +218,20 @@ static __inline RK_U32 mpp_is_32bit()
 static __inline RK_S32 mpp_dup(RK_S32 fd)
 {
     /* avoid stdin / stdout / stderr so start from 3 */
+#ifdef F_DUPFD_CLOEXEC
     return fcntl(fd, F_DUPFD_CLOEXEC, 3);
+#else
+    RK_S32 new_fd = -1;
+
+    new_fd = fcntl(fd, F_DUPFD, 3);
+    if (new_fd == -1)
+        return -1;
+
+    if (fcntl(new_fd, F_SETFD, FD_CLOEXEC) == -1)
+        return -1;
+
+    return new_fd;
+#endif
 }
 
 RK_S32 axb_div_c(RK_S32 a, RK_S32 b, RK_S32 c);
@@ -224,6 +239,7 @@ RK_U32 mpp_align_16(RK_U32 val);
 RK_U32 mpp_align_64(RK_U32 val);
 RK_U32 mpp_align_128(RK_U32 val);
 RK_U32 mpp_align_256_odd(RK_U32 val);
+RK_U32 mpp_align_128_odd_plus_64(RK_U32 val);
 
 #ifdef __cplusplus
 }
diff --git a/osal/inc/mpp_dev_defs.h b/osal/inc/mpp_dev_defs.h
index 3a4862188..171d0fe4c 100644
--- a/osal/inc/mpp_dev_defs.h
+++ b/osal/inc/mpp_dev_defs.h
@@ -38,13 +38,20 @@ typedef enum MppClientType_e {
     VPU_CLIENT_VEPU1        = 17,   /* 0x00020000 */
     VPU_CLIENT_VEPU2        = 18,   /* 0x00040000 */
     VPU_CLIENT_VEPU2_JPEG   = 19,   /* 0x00080000 */
+    VPU_CLIENT_JPEG_ENC     = 20,   /* 0x00100000 */
+
     VPU_CLIENT_VEPU22       = 24,   /* 0x01000000 */
 
     IEP_CLIENT_TYPE         = 28,   /* 0x10000000 */
+    VDPP_CLIENT_TYPE        = 29,   /* 0x20000000 */
 
     VPU_CLIENT_BUTT,
 } MppClientType;
 
+#define CLIENT_TYPE_MASK_DEC    0x0000ffff
+#define CLIENT_TYPE_MASK_ENC    0x0fff0000
+#define CLIENT_TYPE_MASK_VPROC  0xf0000000
+
 /* RK combined codec */
 #define HAVE_VDPU1          (1 << VPU_CLIENT_VDPU1)         /* 0x00000001 */
 #define HAVE_VDPU2          (1 << VPU_CLIENT_VDPU2)         /* 0x00000002 */
@@ -61,10 +68,13 @@ typedef enum MppClientType_e {
 #define HAVE_VEPU1          (1 << VPU_CLIENT_VEPU1)         /* 0x00020000 */
 #define HAVE_VEPU2          (1 << VPU_CLIENT_VEPU2)         /* 0x00040000 */
 #define HAVE_VEPU2_JPEG     (1 << VPU_CLIENT_VEPU2_JPEG)    /* 0x00080000 */
+#define HAVE_JPEG_ENC       (1 << VPU_CLIENT_JPEG_ENC)      /* 0x00100000 */
 /* External encoder */
 #define HAVE_VEPU22         (1 << VPU_CLIENT_VEPU22)        /* 0x01000000 */
 /* RK Image Enhance Processor for deinterlacing */
 #define HAVE_IEP            (1 << IEP_CLIENT_TYPE)          /* 0x10000000 */
+/* RK Image Enhance Processor for dispaly */
+#define HAVE_VDPP           (1 << VDPP_CLIENT_TYPE)         /* 0x20000000 */
 
 /* Platform image process hardware feature */
 #define HAVE_IPP            (0x00000001)
diff --git a/osal/inc/mpp_device.h b/osal/inc/mpp_device.h
index 8ed36a0ae..70c7021fd 100644
--- a/osal/inc/mpp_device.h
+++ b/osal/inc/mpp_device.h
@@ -18,9 +18,16 @@
 #define __MPP_DEVICE_H__
 
 #include "mpp_err.h"
+#include "mpp_list.h"
+#include "mpp_mem_pool.h"
+
 #include "mpp_dev_defs.h"
 #include "mpp_callback.h"
 
+#define MPP_MAX_REG_TRANS_NUM   80
+
+typedef void* MppDev;
+
 typedef enum MppDevIoctlCmd_e {
     /* device batch mode config */
     MPP_DEV_BATCH_ON,
@@ -36,6 +43,10 @@ typedef enum MppDevIoctlCmd_e {
     MPP_DEV_RCB_INFO,
     MPP_DEV_SET_INFO,
     MPP_DEV_SET_ERR_REF_HACK,
+    MPP_DEV_LOCK_MAP,
+    MPP_DEV_UNLOCK_MAP,
+    MPP_DEV_ATTACH_FD,
+    MPP_DEV_DETACH_FD,
 
     MPP_DEV_CMD_SEND,
     MPP_DEV_CMD_POLL,
@@ -100,6 +111,22 @@ typedef struct MppDevPollCfg_t {
     MppDevPollEncSliceInfo slice_info[];
 } MppDevPollCfg;
 
+typedef struct MppDevBufMapNode_t {
+    /* data write by buffer function */
+    struct list_head    list_buf;
+    pthread_mutex_t     *lock_buf;
+    MppBuffer           buffer;
+    MppDev              dev;
+    MppMemPool          pool;
+    RK_S32              buf_fd;
+
+    /* data write by device function */
+    struct list_head    list_dev;
+    pthread_mutex_t     *lock_dev;
+    RK_S32              dev_fd;
+    RK_U32              iova;
+} MppDevBufMapNode;
+
 typedef struct MppDevApi_t {
     const char  *name;
     RK_U32      ctx_size;
@@ -121,6 +148,12 @@ typedef struct MppDevApi_t {
     MPP_RET     (*set_info)(void *ctx, MppDevInfoCfg *cfg);
     MPP_RET     (*set_err_ref_hack)(void *ctx, RK_U32 *enable);
 
+    /* buffer attach / detach */
+    MPP_RET     (*lock_map)(void *ctx);
+    MPP_RET     (*unlock_map)(void *ctx);
+    MPP_RET     (*attach_fd)(void *ctx, MppDevBufMapNode *node);
+    MPP_RET     (*detach_fd)(void *ctx, MppDevBufMapNode *node);
+
     /* send cmd to hardware */
     MPP_RET     (*cmd_send)(void *ctx);
 
@@ -128,8 +161,6 @@ typedef struct MppDevApi_t {
     MPP_RET     (*cmd_poll)(void *ctx, MppDevPollCfg *cfg);
 } MppDevApi;
 
-typedef void* MppDev;
-
 #ifdef __cplusplus
 extern "C" {
 #endif
diff --git a/osal/inc/mpp_mem.h b/osal/inc/mpp_mem.h
index d4de019e0..a8f36d6e8 100644
--- a/osal/inc/mpp_mem.h
+++ b/osal/inc/mpp_mem.h
@@ -31,15 +31,18 @@
 #define mpp_malloc_size(type, size)  \
     (type*)mpp_osal_malloc(__FUNCTION__, size)
 
-#define mpp_calloc_size(type, size)  \
-    (type*)mpp_osal_calloc(__FUNCTION__, size)
-
 #define mpp_calloc(type, count)  \
     (type*)mpp_osal_calloc(__FUNCTION__, sizeof(type) * (count))
 
+#define mpp_calloc_size(type, size)  \
+    (type*)mpp_osal_calloc(__FUNCTION__, size)
+
 #define mpp_realloc(ptr, type, count) \
     (type*)mpp_osal_realloc(__FUNCTION__, ptr, sizeof(type) * (count))
 
+#define mpp_realloc_size(ptr, type, size) \
+    (type*)mpp_osal_realloc(__FUNCTION__, ptr, size)
+
 #define mpp_free(ptr) \
     mpp_osal_free(__FUNCTION__, ptr)
 
diff --git a/osal/inc/mpp_soc.h b/osal/inc/mpp_soc.h
index 9ae9f143a..c629809b9 100644
--- a/osal/inc/mpp_soc.h
+++ b/osal/inc/mpp_soc.h
@@ -46,6 +46,7 @@ typedef enum RockchipSocType_e {
     ROCKCHIP_SOC_RK3588,
     ROCKCHIP_SOC_RK3528,
     ROCKCHIP_SOC_RK3562,
+    ROCKCHIP_SOC_RK3576,
     ROCKCHIP_SOC_BUTT,
 } RockchipSocType;
 
@@ -87,7 +88,7 @@ typedef struct {
     const RockchipSocType   soc_type;
     const RK_U32            vcodec_type;
 
-    /* Max 4 decoder cap */
+    /* Max 6 decoder cap */
     const MppDecHwCap       *dec_caps[6];
     /* Max 4 encoder cap */
     const MppEncHwCap       *enc_caps[4];
@@ -102,6 +103,7 @@ RockchipSocType mpp_get_soc_type(void);
 
 const MppSocInfo *mpp_get_soc_info(void);
 RK_U32 mpp_check_soc_cap(MppCtxType type, MppCodingType coding);
+const MppDecHwCap* mpp_get_dec_hw_info_by_client_type(MppClientType client_type);
 
 #ifdef __cplusplus
 }
diff --git a/osal/inc/mpp_thread.h b/osal/inc/mpp_thread.h
index 19688cb36..3c3550ce0 100644
--- a/osal/inc/mpp_thread.h
+++ b/osal/inc/mpp_thread.h
@@ -89,17 +89,17 @@ class Mutex
     public:
         inline Autolock(Mutex* mutex, RK_U32 enable = 1) :
             mEnabled(enable),
-            mLock(*mutex) {
-            if (mEnabled)
-                mLock.lock();
+            mLock(mutex) {
+            if (mLock && mEnabled)
+                mLock->lock();
         }
         inline ~Autolock() {
-            if (mEnabled)
-                mLock.unlock();
+            if (mLock && mEnabled)
+                mLock->unlock();
         }
     private:
         RK_S32 mEnabled;
-        Mutex& mLock;
+        Mutex *mLock;
     };
 
 private:
diff --git a/osal/mpp_allocator.cpp b/osal/mpp_allocator.cpp
index 8d18835d0..a570883c3 100644
--- a/osal/mpp_allocator.cpp
+++ b/osal/mpp_allocator.cpp
@@ -175,6 +175,8 @@ MPP_RET mpp_allocator_get(MppAllocator *allocator, MppAllocatorApi **api,
         } break;
         case MPP_BUFFER_TYPE_DMA_HEAP: {
             p->os_api = (mpp_rt_allcator_is_valid(MPP_BUFFER_TYPE_DMA_HEAP)) ? allocator_dma_heap :
+                        (mpp_rt_allcator_is_valid(MPP_BUFFER_TYPE_DRM)) ? allocator_drm :
+                        (mpp_rt_allcator_is_valid(MPP_BUFFER_TYPE_ION)) ? allocator_ion :
                         allocator_std;
         } break;
         default : {
diff --git a/osal/mpp_common.cpp b/osal/mpp_common.cpp
index ae612ee67..06254c875 100644
--- a/osal/mpp_common.cpp
+++ b/osal/mpp_common.cpp
@@ -126,3 +126,12 @@ RK_U32 mpp_align_256_odd(RK_U32 val)
 {
     return MPP_ALIGN(val, 256) | 256;
 }
+
+RK_U32 mpp_align_128_odd_plus_64(RK_U32 val)
+{
+    val = MPP_ALIGN(val, 64);
+    if (((val - 64) % 256 == 128))
+        return val;
+    else
+        return ((MPP_ALIGN(val, 128) | 128) + 64);
+}
diff --git a/osal/mpp_mem.cpp b/osal/mpp_mem.cpp
index 6c5f0c274..23a4cdcd0 100644
--- a/osal/mpp_mem.cpp
+++ b/osal/mpp_mem.cpp
@@ -51,7 +51,7 @@
     do { \
         if (!(cond)) { \
             mpp_err("found mpp_mem assert failed, start dumping:\n"); \
-            service.dump(__FUNCTION__); \
+            MppMemService::get_inst()->dump(__FUNCTION__); \
             mpp_assert(cond); \
         } \
     } while (0)
@@ -93,9 +93,10 @@ typedef struct MppMemLog_s {
 class MppMemService
 {
 public:
-    // avoid any unwanted function
-    MppMemService();
-    ~MppMemService();
+    static MppMemService *get_inst() {
+        static MppMemService instance;
+        return &instance;
+    }
 
     void    add_node(const char *caller, void *ptr, size_t size);
     /*
@@ -121,10 +122,16 @@ class MppMemService
     RK_U32  total_now(void) { return m_total_size; }
     RK_U32  total_max(void) { return m_total_max; }
 
-    Mutex       lock;
+    Mutex       *m_lock;
     RK_U32      debug;
 
 private:
+    // avoid any unwanted function
+    MppMemService();
+    ~MppMemService();
+    MppMemService(const MppMemService &);
+    MppMemService &operator=(const MppMemService &);
+
     // data for node record and delay free check
     RK_S32      nodes_max;
     RK_S32      nodes_idx;
@@ -145,13 +152,8 @@ class MppMemService
     MppMemLog   *logs;
     RK_U32      m_total_size;
     RK_U32      m_total_max;
-
-    MppMemService(const MppMemService &);
-    MppMemService &operator=(const MppMemService &);
 };
 
-static MppMemService service;
-
 static const char *ops2str[MEM_OPS_BUTT] = {
     "malloc",
     "realloc",
@@ -213,6 +215,8 @@ MppMemService::MppMemService()
 {
     mpp_env_get_u32("mpp_mem_debug", &debug, 0);
 
+    m_lock = new Mutex();
+
     // add more flag if debug enabled
     if (debug)
         debug |= MEM_DEBUG_EN;
@@ -247,7 +251,7 @@ MppMemService::MppMemService()
 MppMemService::~MppMemService()
 {
     if (debug & MEM_DEBUG_EN) {
-        AutoMutex auto_lock(&lock);
+        AutoMutex auto_lock(m_lock);
 
         RK_S32 i = 0;
         MppMemNode *node = nodes;
@@ -296,6 +300,11 @@ MppMemService::~MppMemService()
         os_free(frees);
         os_free(logs);
     }
+
+    if (m_lock) {
+        delete m_lock;
+        m_lock = NULL;
+    }
 }
 
 void MppMemService::add_node(const char *caller, void *ptr, size_t size)
@@ -561,9 +570,10 @@ void MppMemService::reset_node(const char *caller, void *ptr, void *ret, size_t
 void MppMemService::add_log(MppMemOps ops, const char *caller,
                             void *ptr, void *ret, size_t size_0, size_t size_1)
 {
+    MppMemService *srv = MppMemService::get_inst();
     MppMemLog *log = &logs[log_idx];
 
-    if (service.debug & MEM_RUNTIME_LOG)
+    if (srv->debug & MEM_RUNTIME_LOG)
         mpp_log("%-7s ptr %010p %010p size %8u %8u at %s\n",
                 ops2str[ops], ptr, ret, size_0, size_1, caller);
 
@@ -639,7 +649,8 @@ void MppMemService::dump(const char *caller)
 
 void *mpp_osal_malloc(const char *caller, size_t size)
 {
-    RK_U32 debug = service.debug;
+    MppMemService *srv = MppMemService::get_inst();
+    RK_U32 debug = srv->debug;
     size_t size_align = MEM_ALIGNED(size);
     size_t size_real = (debug & MEM_EXT_ROOM) ? (size_align + 2 * MEM_ALIGN) :
                        (size_align);
@@ -648,8 +659,8 @@ void *mpp_osal_malloc(const char *caller, size_t size)
     os_malloc(&ptr, MEM_ALIGN, size_real);
 
     if (debug) {
-        AutoMutex auto_lock(&service.lock);
-        service.add_log(MEM_MALLOC, caller, NULL, ptr, size, size_real);
+        AutoMutex auto_lock(srv->m_lock);
+        srv->add_log(MEM_MALLOC, caller, NULL, ptr, size, size_real);
 
         if (ptr) {
             if (debug & MEM_EXT_ROOM) {
@@ -657,7 +668,7 @@ void *mpp_osal_malloc(const char *caller, size_t size)
                 set_mem_ext_room(ptr, size);
             }
 
-            service.add_node(caller, ptr, size);
+            srv->add_node(caller, ptr, size);
         }
     }
 
@@ -674,7 +685,8 @@ void *mpp_osal_calloc(const char *caller, size_t size)
 
 void *mpp_osal_realloc(const char *caller, void *ptr, size_t size)
 {
-    RK_U32 debug = service.debug;
+    MppMemService *srv = MppMemService::get_inst();
+    RK_U32 debug = srv->debug;
     void *ret;
 
     if (NULL == ptr)
@@ -696,15 +708,15 @@ void *mpp_osal_realloc(const char *caller, void *ptr, size_t size)
         // if realloc fail the original buffer will be kept the same.
         mpp_err("mpp_realloc ptr %p to size %d failed\n", ptr, size);
     } else {
-        AutoMutex auto_lock(&service.lock);
+        AutoMutex auto_lock(srv->m_lock);
 
         // if realloc success reset the node and record
         if (debug) {
             void *ret_ptr = (debug & MEM_EXT_ROOM) ?
                             ((RK_U8 *)ret + MEM_ALIGN) : (ret);
 
-            service.reset_node(caller, ptr, ret_ptr, size);
-            service.add_log(MEM_REALLOC, caller, ptr, ret_ptr, size, size_real);
+            srv->reset_node(caller, ptr, ret_ptr, size);
+            srv->add_log(MEM_REALLOC, caller, ptr, ret_ptr, size, size_real);
             ret = ret_ptr;
         }
     }
@@ -714,7 +726,9 @@ void *mpp_osal_realloc(const char *caller, void *ptr, size_t size)
 
 void mpp_osal_free(const char *caller, void *ptr)
 {
-    RK_U32 debug = service.debug;
+    MppMemService *srv = MppMemService::get_inst();
+    RK_U32 debug = srv->debug;
+
     if (NULL == ptr)
         return;
 
@@ -725,40 +739,46 @@ void mpp_osal_free(const char *caller, void *ptr)
 
     size_t size = 0;
 
-    AutoMutex auto_lock(&service.lock);
+    AutoMutex auto_lock(srv->m_lock);
     if (debug & MEM_POISON) {
         // NODE: keep this node and  delete delay node
-        void *ret = service.delay_del_node(caller, ptr, &size);
+        void *ret = srv->delay_del_node(caller, ptr, &size);
         if (ret)
             os_free((RK_U8 *)ret - MEM_ALIGN);
 
-        service.add_log(MEM_FREE_DELAY, caller, ptr, ret, size, 0);
+        srv->add_log(MEM_FREE_DELAY, caller, ptr, ret, size, 0);
     } else {
         void *ptr_real = (RK_U8 *)ptr - MEM_HEAD_ROOM(debug);
         // NODE: delete node and return size here
-        service.del_node(caller, ptr, &size);
-        service.chk_mem(caller, ptr, size);
+        srv->del_node(caller, ptr, &size);
+        srv->chk_mem(caller, ptr, size);
         os_free(ptr_real);
-        service.add_log(MEM_FREE, caller, ptr, ptr_real, size, 0);
+        srv->add_log(MEM_FREE, caller, ptr, ptr_real, size, 0);
     }
 }
 
 /* dump memory status */
 void mpp_show_mem_status()
 {
-    AutoMutex auto_lock(&service.lock);
-    if (service.debug & MEM_DEBUG_EN)
-        service.dump(__FUNCTION__);
+    MppMemService *srv = MppMemService::get_inst();
+    AutoMutex auto_lock(srv->m_lock);
+
+    if (srv->debug & MEM_DEBUG_EN)
+        srv->dump(__FUNCTION__);
 }
 
 RK_U32 mpp_mem_total_now()
 {
-    AutoMutex auto_lock(&service.lock);
-    return service.total_now();
+    MppMemService *srv = MppMemService::get_inst();
+    AutoMutex auto_lock(srv->m_lock);
+
+    return srv->total_now();
 }
 
 RK_U32 mpp_mem_total_max()
 {
-    AutoMutex auto_lock(&service.lock);
-    return service.total_max();
+    MppMemService *srv = MppMemService::get_inst();
+    AutoMutex auto_lock(srv->m_lock);
+
+    return srv->total_max();
 }
diff --git a/osal/mpp_platform.cpp b/osal/mpp_platform.cpp
index d10af369f..050bc2c6b 100644
--- a/osal/mpp_platform.cpp
+++ b/osal/mpp_platform.cpp
@@ -133,10 +133,37 @@ MppPlatformService::MppPlatformService()
     if (mpp_get_mpp_service_name()) {
         ioctl_version = IOCTL_MPP_SERVICE_V1;
         check_mpp_service_cap(&vcodec_type, hw_ids, cap);
+        mpp_dbg_platform("vcodec_type from kernel 0x%08x, vs from soc info 0x%08x\n",
+                         vcodec_type, soc_info->vcodec_type);
     }
     kernel_version = check_kernel_version();
-    if (!vcodec_type)
+    if (!vcodec_type) {
         vcodec_type = soc_info->vcodec_type;
+    } else {
+        // Compare kernel result with soc infomation.
+        RK_U32 diff_type = vcodec_type ^ soc_info->vcodec_type;
+        RK_U32 i;
+
+        for (i = 0; i <= VPU_CLIENT_VEPU22; i++) {
+            RK_U32 mask = 1 << i;
+
+            if (diff_type & mask) {
+                MppClientType client_type = (MppClientType) i;
+
+                mpp_dbg_platform("confliction found at client_type %d\n", client_type);
+
+                if (soc_info->vcodec_type & mask) {
+                    mpp_err("client %d driver is not ready!\n", client_type);
+                } else {
+                    mpp_dbg_platform("client %d driver is ready but not declared!\n", client_type);
+                    if (client_type == VPU_CLIENT_VDPU2_PP)
+                        vcodec_type &= ~mask;
+                }
+            }
+        }
+
+        mpp_dbg_platform("vcode_type 0x%08x\n", vcodec_type);
+    }
 }
 
 RK_U32 MppPlatformService::get_hw_id(RK_S32 client_type)
diff --git a/osal/mpp_runtime.cpp b/osal/mpp_runtime.cpp
index c23799635..079463e8d 100644
--- a/osal/mpp_runtime.cpp
+++ b/osal/mpp_runtime.cpp
@@ -85,7 +85,9 @@ MppRuntimeService::MppRuntimeService()
 
     allocator_valid[MPP_BUFFER_TYPE_NORMAL] = 1;
     allocator_valid[MPP_BUFFER_TYPE_ION] = !access("/dev/ion", F_OK | R_OK | W_OK);
-    allocator_valid[MPP_BUFFER_TYPE_DRM] = !access("/dev/dri/card0", F_OK | R_OK | W_OK);
+    allocator_valid[MPP_BUFFER_TYPE_DRM] =
+        !access("/dev/dri/renderD128", F_OK | R_OK | W_OK) ||
+        !access("/dev/dri/card0", F_OK | R_OK | W_OK);
     allocator_valid[MPP_BUFFER_TYPE_DMA_HEAP] = !access("/dev/dma_heap", F_OK | R_OK);
 
     if (!allocator_valid[MPP_BUFFER_TYPE_ION] &&
diff --git a/osal/mpp_soc.cpp b/osal/mpp_soc.cpp
index 5bda863e2..a91ef86b8 100644
--- a/osal/mpp_soc.cpp
+++ b/osal/mpp_soc.cpp
@@ -59,6 +59,7 @@
 #define CAP_CODING_VDPU341_LITE (HAVE_AVC|HAVE_HEVC)
 #define CAP_CODING_VDPU381      (HAVE_AVC|HAVE_HEVC|HAVE_VP9|HAVE_AVS2)
 #define CAP_CODING_VDPU382      (HAVE_AVC|HAVE_HEVC|HAVE_AVS2)
+#define CAP_CODING_VDPU383      (HAVE_AVC|HAVE_HEVC|HAVE_VP9|HAVE_AVS2|HAVE_AV1)
 
 #define CAP_CODING_VEPU1        (HAVE_AVC|HAVE_MJPEG|HAVE_VP8)
 #define CAP_CODING_VEPU_LITE    (HAVE_AVC|HAVE_MJPEG)
@@ -409,6 +410,24 @@ static const MppDecHwCap vdpu382_lite = {
     .reserved           = 0,
 };
 
+static const MppDecHwCap vdpu383 = {
+    .cap_coding         = CAP_CODING_VDPU383,
+    .type               = VPU_CLIENT_RKVDEC,
+    .cap_fbc            = 2,
+    .cap_4k             = 1,
+    .cap_8k             = 1,
+    .cap_colmv_compress = 1,
+    .cap_hw_h265_rps    = 1,
+    .cap_hw_vp9_prob    = 1,
+    .cap_jpg_pp_out     = 0,
+    .cap_10bit          = 1,
+    .cap_down_scale     = 1,
+    .cap_lmt_linebuf    = 0,
+    .cap_core_num       = 1,
+    .cap_hw_jpg_fix     = 0,
+    .reserved           = 0,
+};
+
 static const MppDecHwCap avspd = {
     .cap_coding         = CAP_CODING_AVSPD,
     .type               = VPU_CLIENT_AVSPLUS_DEC,
@@ -509,7 +528,7 @@ static const MppEncHwCap vepu2_no_jpeg = {
 
 static const MppEncHwCap vepu2_jpeg = {
     .cap_coding         = HAVE_MJPEG,
-    .type               = VPU_CLIENT_VEPU2_JPEG,
+    .type               = VPU_CLIENT_VEPU2,
     .cap_fbc            = 0,
     .cap_4k             = 0,
     .cap_8k             = 0,
@@ -518,6 +537,17 @@ static const MppEncHwCap vepu2_jpeg = {
     .reserved           = 0,
 };
 
+static const MppEncHwCap vepu2_jpeg_enhanced = {
+    .cap_coding         = HAVE_MJPEG,
+    .type               = VPU_CLIENT_VEPU2_JPEG,
+    .cap_fbc            = 0,
+    .cap_4k             = 1,
+    .cap_8k             = 0,
+    .cap_hw_osd         = 0,
+    .cap_hw_roi         = 0,
+    .reserved           = 0,
+};
+
 static const MppEncHwCap vepu22 = {
     .cap_coding         = CAP_CODING_HEVC,
     .type               = VPU_CLIENT_VEPU22,
@@ -597,6 +627,28 @@ static const MppEncHwCap vepu540c_no_hevc = {
     .reserved           = 0,
 };
 
+static const MppEncHwCap vepu510 = {
+    .cap_coding         = CAP_CODING_VEPU54X,
+    .type               = VPU_CLIENT_RKVENC,
+    .cap_fbc            = 0,
+    .cap_4k             = 1,
+    .cap_8k             = 1,
+    .cap_hw_osd         = 0,
+    .cap_hw_roi         = 1,
+    .reserved           = 0,
+};
+
+static const MppEncHwCap rkjpege_vpu720 = {
+    .cap_coding         = HAVE_MJPEG,
+    .type               = VPU_CLIENT_JPEG_ENC,
+    .cap_fbc            = 0,
+    .cap_4k             = 1,
+    .cap_8k             = 1,
+    .cap_hw_osd         = 0,
+    .cap_hw_roi         = 0,
+    .reserved           = 0,
+};
+
 /*
  * NOTE:
  * vpu1 = vdpu1 + vepu1
@@ -765,7 +817,7 @@ static const MppSocInfo mpp_soc_infos[] = {
          */
         "rv1109",
         ROCKCHIP_SOC_RV1109,
-        HAVE_VDPU2 | HAVE_VEPU2_JPEG | HAVE_RKVDEC | HAVE_RKVENC,
+        HAVE_VDPU2 | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_RKVENC,
         {   &vdpu2_jpeg_fix, &vdpu341_lite, NULL, NULL, NULL, NULL, },
         {   &vepu2_jpeg, &vepu541, NULL, NULL, },
     },
@@ -777,7 +829,7 @@ static const MppSocInfo mpp_soc_infos[] = {
          */
         "rv1126",
         ROCKCHIP_SOC_RV1126,
-        HAVE_VDPU2 | HAVE_VEPU2_JPEG | HAVE_RKVDEC | HAVE_RKVENC,
+        HAVE_VDPU2 | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_RKVENC,
         {   &vdpu2_jpeg_fix, &vdpu341_lite, NULL, NULL, NULL, NULL, },
         {   &vepu2_jpeg, &vepu541, NULL, NULL, },
     },
@@ -863,7 +915,7 @@ static const MppSocInfo mpp_soc_infos[] = {
         HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_RKVENC |
         HAVE_JPEG_DEC | HAVE_AV1DEC | HAVE_AVSDEC | HAVE_VEPU2_JPEG,
         {   &vdpu38x, &rkjpegd, &vdpu2, &vdpu2_jpeg_pp_fix, &av1d, &avspd},
-        {   &vepu58x, &vepu2, &vepu2_jpeg, NULL, },
+        {   &vepu58x, &vepu2, &vepu2_jpeg_enhanced, NULL, },
     },
     {   /*
          * rk3528a has codec:
@@ -903,6 +955,18 @@ static const MppSocInfo mpp_soc_infos[] = {
         {   &vdpu382_lite, &rkjpegd, NULL, NULL, NULL, NULL, },
         {   &vepu540c_no_hevc, NULL, NULL, NULL, },
     },
+    {   /*
+         * rk3576 has codec:
+         * 1 - RK H.264/H.265/VP9/AVS2/AV1 8K decoder
+         * 2 - RK H.264/H.265 8K encoder
+         * 3 - RK jpeg decoder/encoder
+         */
+        "rk3576",
+        ROCKCHIP_SOC_RK3576,
+        HAVE_RKVDEC | HAVE_RKVENC | HAVE_JPEG_DEC | HAVE_JPEG_ENC,
+        {   &vdpu383, &rkjpegd, NULL, NULL, NULL, NULL},
+        {   &vepu510, &rkjpege_vpu720, NULL, NULL},
+    },
 };
 
 static const MppSocInfo mpp_soc_default = {
@@ -1020,7 +1084,8 @@ MppSocService::MppSocService()
 
     mpp_dbg_platform("coding caps: dec %08x enc %08x\n",
                      dec_coding_cap, enc_coding_cap);
-    mpp_dbg_platform("vcodec type: %08x\n", soc_info->vcodec_type);
+    mpp_dbg_platform("vcodec type from cap: %08x, from soc_info %08x\n",
+                     vcodec_type, soc_info->vcodec_type);
     mpp_assert(soc_info->vcodec_type == vcodec_type);
 }
 
@@ -1082,3 +1147,19 @@ RK_U32 mpp_check_soc_cap(MppCtxType type, MppCodingType coding)
 
     return is_valid_cap_coding(cap, coding);
 }
+
+const MppDecHwCap* mpp_get_dec_hw_info_by_client_type(MppClientType client_type)
+{
+    const MppDecHwCap* hw_info = NULL;
+    const MppSocInfo *info = mpp_get_soc_info();
+    RK_U32 i = 0;
+
+    for (i = 0; i < MPP_ARRAY_ELEMS(info->dec_caps); i++) {
+        if (info->dec_caps[i] && info->dec_caps[i]->type == client_type) {
+            hw_info = info->dec_caps[i];
+            break;
+        }
+    }
+
+    return hw_info;
+}
diff --git a/osal/osal_2str.c b/osal/osal_2str.c
index ff7406b95..4de11e479 100644
--- a/osal/osal_2str.c
+++ b/osal/osal_2str.c
@@ -44,8 +44,8 @@ const char *strof_client_type(MppClientType type)
         /* VPU_CLIENT_VEPU1         */  "vepu1",
         /* VPU_CLIENT_VEPU2         */  "vepu2",
         /* VPU_CLIENT_VEPU2_JPEG    */  "vepu2_jpeg",
-        /* 20 ~ 23 */
-        /* VPU_CLIENT_BUTT          */  NULL,
+        /* VPU_CLIENT_JPEG_ENC      */  "rkjpege",
+        /* 21 ~ 23 */
         /* VPU_CLIENT_BUTT          */  NULL,
         /* VPU_CLIENT_BUTT          */  NULL,
         /* VPU_CLIENT_BUTT          */  NULL,
diff --git a/osal/test/mpp_platform_test.c b/osal/test/mpp_platform_test.c
index f27a7eaa1..e3c9f19d7 100644
--- a/osal/test/mpp_platform_test.c
+++ b/osal/test/mpp_platform_test.c
@@ -62,6 +62,9 @@ int main()
     if (vcodec_type & HAVE_JPEG_DEC)
         mpp_log("found rk jpeg decoder\n");
 
+    if (vcodec_type & HAVE_JPEG_ENC)
+        mpp_log("found rk jpeg encoder\n");
+
     if (vcodec_type & HAVE_RKVENC)
         mpp_log("found rkvenc encoder\n");
 
diff --git a/pkgconfig/rockchip_mpp.pc.cmake b/pkgconfig/rockchip_mpp.pc.cmake
index 9fe4d84d4..75cc2cf2b 100644
--- a/pkgconfig/rockchip_mpp.pc.cmake
+++ b/pkgconfig/rockchip_mpp.pc.cmake
@@ -6,7 +6,7 @@ includedir=${prefix}/@CMAKE_INSTALL_INCLUDEDIR@
 Name: rockchip_mpp
 Description: Rockchip Media Process Platform
 Requires.private:
-Version: 1.3.8
+Version: 1.3.9
 Libs: -L${libdir} -lrockchip_mpp
 Libs.private:
 Cflags: -I${includedir}
diff --git a/pkgconfig/rockchip_vpu.pc.cmake b/pkgconfig/rockchip_vpu.pc.cmake
index 85e689e8a..f5e7d634c 100644
--- a/pkgconfig/rockchip_vpu.pc.cmake
+++ b/pkgconfig/rockchip_vpu.pc.cmake
@@ -6,7 +6,7 @@ includedir=${prefix}/@CMAKE_INSTALL_INCLUDEDIR@
 Name: rockchip_vpu
 Description: Rockchip Media Process Platform (Legacy)
 Requires.private:
-Version: 0.3.0
+Version: 0.3.1
 Libs: -L${libdir} -lrockchip_vpu
 Libs.private:
 Cflags: -I${includedir}
diff --git a/readme.txt b/readme.txt
index 22e9f633b..edf7684e4 100644
--- a/readme.txt
+++ b/readme.txt
@@ -37,6 +37,7 @@ NOTE:
 4. you can get demo about mpp applied to linux and android.
      Liunx : https://github.com/WainDing/mpp_linux_cpp
              https://github.com/MUZLATAN/ffmpeg_rtsp_mpp
+             https://github.com/nyanmisaka/ffmpeg-rockchip
      Android : https://github.com/c-xh/RKMediaCodecDemo
 5. offical github: https://github.com/rockchip-linux/mpp
    develop github: https://github.com/HermanChen/mpp
diff --git a/test/mpi_enc_mt_test.cpp b/test/mpi_enc_mt_test.cpp
index 55b714ada..826cf6581 100644
--- a/test/mpi_enc_mt_test.cpp
+++ b/test/mpi_enc_mt_test.cpp
@@ -328,10 +328,10 @@ MPP_RET test_mt_cfg_setup(MpiEncMtCtxInfo *info)
     /* fix input / output frame rate */
     mpp_enc_cfg_set_s32(cfg, "rc:fps_in_flex", p->fps_in_flex);
     mpp_enc_cfg_set_s32(cfg, "rc:fps_in_num", p->fps_in_num);
-    mpp_enc_cfg_set_s32(cfg, "rc:fps_in_denorm", p->fps_in_den);
+    mpp_enc_cfg_set_s32(cfg, "rc:fps_in_denom", p->fps_in_den);
     mpp_enc_cfg_set_s32(cfg, "rc:fps_out_flex", p->fps_out_flex);
     mpp_enc_cfg_set_s32(cfg, "rc:fps_out_num", p->fps_out_num);
-    mpp_enc_cfg_set_s32(cfg, "rc:fps_out_denorm", p->fps_out_den);
+    mpp_enc_cfg_set_s32(cfg, "rc:fps_out_denom", p->fps_out_den);
 
     /* drop frame or not when bitrate overflow */
     mpp_enc_cfg_set_u32(cfg, "rc:drop_mode", MPP_ENC_RC_DROP_FRM_DISABLED);
@@ -710,6 +710,10 @@ void *enc_test_input(void *arg)
                     rewind(p->fp_input);
                     p->frm_eos = 0;
                     mpp_log_q(quiet, "chn %d loop times %d\n", chn, ++p->loop_times);
+                    if (buffer) {
+                        AutoMutex autolock(list_buf->mutex());
+                        list_buf->add_at_tail(&buffer, sizeof(buffer));
+                    }
                     continue;
                 }
                 mpp_log_q(quiet, "chn %d found last frame. feof %d\n", chn, feof(p->fp_input));
diff --git a/test/mpi_enc_test.c b/test/mpi_enc_test.c
index af77a9758..a2d9fcc20 100644
--- a/test/mpi_enc_test.c
+++ b/test/mpi_enc_test.c
@@ -28,6 +28,7 @@
 #include "mpp_time.h"
 #include "mpp_debug.h"
 #include "mpp_common.h"
+#include "mpp_soc.h"
 
 #include "utils.h"
 #include "mpi_enc_utils.h"
@@ -35,6 +36,16 @@
 #include "mpp_enc_roi_utils.h"
 #include "mpp_rc_api.h"
 
+static RK_S32 aq_thd_smart[16] = {
+    1,  3,  3,  3,  3,  3,  5,  5,
+    8,  8,  8, 15, 15, 20, 25, 28
+};
+
+static RK_S32 aq_step_smart[16] = {
+    -8, -7, -6, -5, -4, -3, -2, -1,
+    0,  1,  2,  3,  4,  6,  8, 10
+};
+
 typedef struct {
     // base flow context
     MppCtx ctx;
@@ -118,7 +129,13 @@ typedef struct {
     RK_S32 gop_len;
     RK_S32 vi_len;
     RK_S32 scene_mode;
-
+    RK_S32 cu_qp_delta_depth;
+    RK_S32 anti_flicker_str;
+    RK_S32 atr_str_i;
+    RK_S32 atr_str_p;
+    RK_S32 atl_str;
+    RK_S32 sao_str_i;
+    RK_S32 sao_str_p;
     RK_S64 first_frm;
     RK_S64 first_pkt;
 } MpiEncTestData;
@@ -143,6 +160,44 @@ typedef struct {
     MpiEncMultiCtxRet   ret;        // return of encoder
 } MpiEncMultiCtxInfo;
 
+static RK_S32 aq_thd[16] = {
+    0,  0,  0,  0,
+    3,  3,  5,  5,
+    8,  8,  8,  15,
+    15, 20, 25, 25
+};
+
+static RK_S32 aq_step_i_ipc[16] = {
+    -8, -7, -6, -5,
+    -4, -3, -2, -1,
+    0,  1,  2,  3,
+    5,  7,  7,  8,
+};
+
+static RK_S32 aq_step_p_ipc[16] = {
+    -8, -7, -6, -5,
+    -4, -2, -1, -1,
+    0,  2,  3,  4,
+    6,  8,  9,  10,
+};
+
+static RK_S32 get_mdinfo_size(MpiEncTestData *p, MppCodingType type)
+{
+    RockchipSocType soc_type = mpp_get_soc_type();
+    RK_S32 md_size;
+    RK_U32 w = p->hor_stride, h = p->ver_stride;
+
+    if (soc_type == ROCKCHIP_SOC_RK3588) {
+        md_size = (MPP_ALIGN(w, 64) >> 6) * (MPP_ALIGN(h, 64) >> 6) * 32;
+    } else {
+        md_size = (MPP_VIDEO_CodingHEVC == type) ?
+                  (MPP_ALIGN(w, 32) >> 5) * (MPP_ALIGN(h, 32) >> 5) * 16 :
+                  (MPP_ALIGN(w, 64) >> 6) * (MPP_ALIGN(h, 16) >> 4) * 16;
+    }
+
+    return md_size;
+}
+
 MPP_RET test_ctx_init(MpiEncMultiCtxInfo *info)
 {
     MpiEncTestArgs *cmd = info->cmd;
@@ -170,7 +225,6 @@ MPP_RET test_ctx_init(MpiEncMultiCtxInfo *info)
     p->gop_mode     = cmd->gop_mode;
     p->gop_len      = cmd->gop_len;
     p->vi_len       = cmd->vi_len;
-
     p->fps_in_flex  = cmd->fps_in_flex;
     p->fps_in_den   = cmd->fps_in_den;
     p->fps_in_num   = cmd->fps_in_num;
@@ -178,11 +232,14 @@ MPP_RET test_ctx_init(MpiEncMultiCtxInfo *info)
     p->fps_out_den  = cmd->fps_out_den;
     p->fps_out_num  = cmd->fps_out_num;
     p->scene_mode   = cmd->scene_mode;
-    p->mdinfo_size  = (MPP_VIDEO_CodingHEVC == cmd->type) ?
-                      (MPP_ALIGN(p->hor_stride, 32) >> 5) *
-                      (MPP_ALIGN(p->ver_stride, 32) >> 5) * 16 :
-                      (MPP_ALIGN(p->hor_stride, 64) >> 6) *
-                      (MPP_ALIGN(p->ver_stride, 16) >> 4) * 16;
+    p->cu_qp_delta_depth = cmd->cu_qp_delta_depth;
+    p->anti_flicker_str = cmd->anti_flicker_str;
+    p->atr_str_i = cmd->atr_str_i;
+    p->atr_str_p = cmd->atr_str_p;
+    p->atl_str = cmd->atl_str;
+    p->sao_str_i = cmd->sao_str_i;
+    p->sao_str_p = cmd->sao_str_p;
+    p->mdinfo_size  = get_mdinfo_size(p, cmd->type);
 
     if (cmd->file_input) {
         if (!strncmp(cmd->file_input, "/dev/video", 10)) {
@@ -301,7 +358,6 @@ MPP_RET test_mpp_enc_cfg_setup(MpiEncMultiCtxInfo *info)
     RK_U32 flip;
     RK_U32 gop_mode = p->gop_mode;
     MppEncRefCfg ref = NULL;
-
     /* setup default parameter */
     if (p->fps_in_den == 0)
         p->fps_in_den = 1;
@@ -315,23 +371,57 @@ MPP_RET test_mpp_enc_cfg_setup(MpiEncMultiCtxInfo *info)
     if (!p->bps)
         p->bps = p->width * p->height / 8 * (p->fps_out_num / p->fps_out_den);
 
+    if (cmd->rc_mode == MPP_ENC_RC_MODE_SMTRC) {
+        mpp_enc_cfg_set_st(cfg, "hw:aq_thrd_i", aq_thd_smart);
+        mpp_enc_cfg_set_st(cfg, "hw:aq_thrd_p", aq_thd_smart);
+        mpp_enc_cfg_set_st(cfg, "hw:aq_step_i", aq_step_smart);
+        mpp_enc_cfg_set_st(cfg, "hw:aq_step_p", aq_step_smart);
+    } else {
+        mpp_enc_cfg_set_st(cfg, "hw:aq_thrd_i", aq_thd);
+        mpp_enc_cfg_set_st(cfg, "hw:aq_thrd_p", aq_thd);
+        mpp_enc_cfg_set_st(cfg, "hw:aq_step_i", aq_step_i_ipc);
+        mpp_enc_cfg_set_st(cfg, "hw:aq_step_p", aq_step_p_ipc);
+    }
+
+    mpp_enc_cfg_set_s32(cfg, "rc:max_reenc_times", 0);
+    mpp_enc_cfg_set_s32(cfg, "rc:cu_qp_delta_depth", p->cu_qp_delta_depth);
+    mpp_enc_cfg_set_s32(cfg, "tune:anti_flicker_str", p->anti_flicker_str);
+    mpp_enc_cfg_set_s32(cfg, "tune:atr_str_i", p->atr_str_i);
+    mpp_enc_cfg_set_s32(cfg, "tune:atr_str_p", p->atr_str_p);
+    mpp_enc_cfg_set_s32(cfg, "tune:atl_str", p->atl_str);
+    mpp_enc_cfg_set_s32(cfg, "tune:sao_str_i", p->sao_str_i);
+    mpp_enc_cfg_set_s32(cfg, "tune:sao_str_p", p->sao_str_p);
+
     mpp_enc_cfg_set_s32(cfg, "tune:scene_mode", p->scene_mode);
+    mpp_enc_cfg_set_s32(cfg, "tune:deblur_en", cmd->deblur_en);
+    mpp_enc_cfg_set_s32(cfg, "tune:deblur_str", cmd->deblur_str);
+    mpp_enc_cfg_set_s32(cfg, "tune:rc_container", cmd->rc_container);
+    mpp_enc_cfg_set_s32(cfg, "tune:vmaf_opt", 0);
+    mpp_enc_cfg_set_s32(cfg, "hw:qbias_en", 1);
+    mpp_enc_cfg_set_s32(cfg, "hw:qbias_i", cmd->bias_i);
+    mpp_enc_cfg_set_s32(cfg, "hw:qbias_p", cmd->bias_p);
+    mpp_enc_cfg_set_s32(cfg, "hw:skip_bias_en", 0);
+    mpp_enc_cfg_set_s32(cfg, "hw:skip_bias", 4);
+    mpp_enc_cfg_set_s32(cfg, "hw:skip_sad", 8);
 
     mpp_enc_cfg_set_s32(cfg, "prep:width", p->width);
     mpp_enc_cfg_set_s32(cfg, "prep:height", p->height);
     mpp_enc_cfg_set_s32(cfg, "prep:hor_stride", p->hor_stride);
     mpp_enc_cfg_set_s32(cfg, "prep:ver_stride", p->ver_stride);
     mpp_enc_cfg_set_s32(cfg, "prep:format", p->fmt);
+    mpp_enc_cfg_set_s32(cfg, "prep:range", MPP_FRAME_RANGE_JPEG);
 
     mpp_enc_cfg_set_s32(cfg, "rc:mode", p->rc_mode);
+    mpp_enc_cfg_set_u32(cfg, "rc:max_reenc_times", 0);
+    mpp_enc_cfg_set_u32(cfg, "rc:super_mode", 0);
 
     /* fix input / output frame rate */
     mpp_enc_cfg_set_s32(cfg, "rc:fps_in_flex", p->fps_in_flex);
     mpp_enc_cfg_set_s32(cfg, "rc:fps_in_num", p->fps_in_num);
-    mpp_enc_cfg_set_s32(cfg, "rc:fps_in_denorm", p->fps_in_den);
+    mpp_enc_cfg_set_s32(cfg, "rc:fps_in_denom", p->fps_in_den);
     mpp_enc_cfg_set_s32(cfg, "rc:fps_out_flex", p->fps_out_flex);
     mpp_enc_cfg_set_s32(cfg, "rc:fps_out_num", p->fps_out_num);
-    mpp_enc_cfg_set_s32(cfg, "rc:fps_out_denorm", p->fps_out_den);
+    mpp_enc_cfg_set_s32(cfg, "rc:fps_out_denom", p->fps_out_den);
 
     /* drop frame or not when bitrate overflow */
     mpp_enc_cfg_set_u32(cfg, "rc:drop_mode", MPP_ENC_RC_DROP_FRM_DISABLED);
@@ -383,7 +473,8 @@ MPP_RET test_mpp_enc_cfg_setup(MpiEncMultiCtxInfo *info)
         } break;
         case MPP_ENC_RC_MODE_CBR :
         case MPP_ENC_RC_MODE_VBR :
-        case MPP_ENC_RC_MODE_AVBR : {
+        case MPP_ENC_RC_MODE_AVBR :
+        case MPP_ENC_RC_MODE_SMTRC : {
             mpp_enc_cfg_set_s32(cfg, "rc:qp_init", cmd->qp_init ? cmd->qp_init : -1);
             mpp_enc_cfg_set_s32(cfg, "rc:qp_max", cmd->qp_max ? cmd->qp_max : 51);
             mpp_enc_cfg_set_s32(cfg, "rc:qp_min", cmd->qp_min ? cmd->qp_min : 10);
@@ -391,9 +482,9 @@ MPP_RET test_mpp_enc_cfg_setup(MpiEncMultiCtxInfo *info)
             mpp_enc_cfg_set_s32(cfg, "rc:qp_min_i", cmd->qp_min_i ? cmd->qp_min_i : 10);
             mpp_enc_cfg_set_s32(cfg, "rc:qp_ip", 2);
             mpp_enc_cfg_set_s32(cfg, "rc:fqp_min_i", cmd->fqp_min_i ? cmd->fqp_min_i : 10);
-            mpp_enc_cfg_set_s32(cfg, "rc:fqp_max_i", cmd->fqp_max_i ? cmd->fqp_max_i : 51);
+            mpp_enc_cfg_set_s32(cfg, "rc:fqp_max_i", cmd->fqp_max_i ? cmd->fqp_max_i : 45);
             mpp_enc_cfg_set_s32(cfg, "rc:fqp_min_p", cmd->fqp_min_p ? cmd->fqp_min_p : 10);
-            mpp_enc_cfg_set_s32(cfg, "rc:fqp_max_p", cmd->fqp_max_p ? cmd->fqp_max_p : 51);
+            mpp_enc_cfg_set_s32(cfg, "rc:fqp_max_p", cmd->fqp_max_p ? cmd->fqp_max_p : 45);
         } break;
         default : {
             mpp_err_f("unsupport encoder rc mode %d\n", p->rc_mode);
@@ -486,7 +577,6 @@ MPP_RET test_mpp_enc_cfg_setup(MpiEncMultiCtxInfo *info)
     mpp_enc_cfg_set_s32(cfg, "rc:gop", p->gop_len ? p->gop_len : p->fps_out_num * 2);
 
     mpp_env_get_u32("gop_mode", &gop_mode, gop_mode);
-
     if (gop_mode) {
         mpp_enc_ref_cfg_init(&ref);
 
@@ -504,6 +594,19 @@ MPP_RET test_mpp_enc_cfg_setup(MpiEncMultiCtxInfo *info)
         goto RET;
     }
 
+    if (cmd->type == MPP_VIDEO_CodingAVC || cmd->type == MPP_VIDEO_CodingHEVC) {
+        RcApiBrief rc_api_brief;
+        rc_api_brief.type = cmd->type;
+        rc_api_brief.name = (cmd->rc_mode == MPP_ENC_RC_MODE_SMTRC) ?
+                            "smart" : "default";
+
+        ret = mpi->control(ctx, MPP_ENC_SET_RC_API_CURRENT, &rc_api_brief);
+        if (ret) {
+            mpp_err("mpi control enc set rc api failed ret %d\n", ret);
+            goto RET;
+        }
+    }
+
     if (ref)
         mpp_enc_ref_cfg_deinit(&ref);
 
@@ -511,7 +614,7 @@ MPP_RET test_mpp_enc_cfg_setup(MpiEncMultiCtxInfo *info)
     {
         RK_U32 sei_mode;
 
-        mpp_env_get_u32("sei_mode", &sei_mode, MPP_ENC_SEI_MODE_ONE_FRAME);
+        mpp_env_get_u32("sei_mode", &sei_mode, MPP_ENC_SEI_MODE_DISABLE);
         p->sei_mode = sei_mode;
         ret = mpi->control(ctx, MPP_ENC_SET_SEI_CFG, &p->sei_mode);
         if (ret) {
@@ -603,7 +706,7 @@ MPP_RET test_mpp_run(MpiEncMultiCtxInfo *info)
             if (ret == MPP_NOK || feof(p->fp_input)) {
                 p->frm_eos = 1;
 
-                if (p->frame_num < 0 || p->frame_count < p->frame_num) {
+                if (p->frame_num < 0) {
                     clearerr(p->fp_input);
                     rewind(p->fp_input);
                     p->frm_eos = 0;
@@ -814,7 +917,8 @@ MPP_RET test_mpp_run(MpiEncMultiCtxInfo *info)
                     meta = mpp_packet_get_meta(packet);
                     RK_S32 temporal_id = 0;
                     RK_S32 lt_idx = -1;
-                    RK_S32 avg_qp = -1;
+                    RK_S32 avg_qp = -1, bps_rt = -1;
+                    RK_S32 use_lt_idx = -1;
 
                     if (MPP_OK == mpp_meta_get_s32(meta, KEY_TEMPORAL_ID, &temporal_id))
                         log_len += snprintf(log_buf + log_len, log_size - log_len,
@@ -826,7 +930,14 @@ MPP_RET test_mpp_run(MpiEncMultiCtxInfo *info)
 
                     if (MPP_OK == mpp_meta_get_s32(meta, KEY_ENC_AVERAGE_QP, &avg_qp))
                         log_len += snprintf(log_buf + log_len, log_size - log_len,
-                                            " qp %d", avg_qp);
+                                            " qp %2d", avg_qp);
+
+                    if (MPP_OK == mpp_meta_get_s32(meta, KEY_ENC_BPS_RT, &bps_rt))
+                        log_len += snprintf(log_buf + log_len, log_size - log_len,
+                                            " bps_rt %d", bps_rt);
+
+                    if (MPP_OK == mpp_meta_get_s32(meta, KEY_ENC_USE_LTR, &use_lt_idx))
+                        log_len += snprintf(log_buf + log_len, log_size - log_len, " vi");
                 }
 
                 mpp_log_q(quiet, "chn %d %s\n", chn, log_buf);
diff --git a/test/mpi_rc2_test.c b/test/mpi_rc2_test.c
index 26f7328d3..c9b1c6946 100644
--- a/test/mpi_rc2_test.c
+++ b/test/mpi_rc2_test.c
@@ -73,7 +73,6 @@ typedef struct {
 
     /* 2. encoder data */
     MppBufferGroup  pkt_grp;
-    MppBuffer       enc_pkt_buf;
     MppPacket       enc_pkt;
 
     MppEncRcCfg     rc_cfg;
@@ -431,8 +430,8 @@ static MPP_RET mpi_rc_enc_init(MpiRc2TestCtx *ctx)
     enc_mpi = ctx->enc_mpi;
     enc_ctx = ctx->enc_ctx;
 
-    rc_cfg->fps_in_denorm = 1;
-    rc_cfg->fps_out_denorm = 1;
+    rc_cfg->fps_in_denom = 1;
+    rc_cfg->fps_out_denom = 1;
     rc_cfg->fps_in_num = 30;
     rc_cfg->fps_out_num = 30;
     rc_cfg->fps_in_flex = 0;
@@ -495,10 +494,10 @@ static MPP_RET mpi_rc_enc_init(MpiRc2TestCtx *ctx)
     /* fix input / output frame rate */
     mpp_enc_cfg_set_s32(cfg, "rc:fps_in_flex", rc_cfg->fps_in_flex);
     mpp_enc_cfg_set_s32(cfg, "rc:fps_in_num", rc_cfg->fps_in_num);
-    mpp_enc_cfg_set_s32(cfg, "rc:fps_in_denorm",  rc_cfg->fps_in_denorm);
+    mpp_enc_cfg_set_s32(cfg, "rc:fps_in_denom",  rc_cfg->fps_in_denom);
     mpp_enc_cfg_set_s32(cfg, "rc:fps_out_flex", rc_cfg->fps_out_flex);
     mpp_enc_cfg_set_s32(cfg, "rc:fps_out_num",  rc_cfg->fps_out_num);
-    mpp_enc_cfg_set_s32(cfg, "rc:fps_out_denorm", rc_cfg->fps_out_denorm);
+    mpp_enc_cfg_set_s32(cfg, "rc:fps_out_denom", rc_cfg->fps_out_denom);
     mpp_enc_cfg_set_s32(cfg, "rc:gop", enc_cmd->gop_len ? enc_cmd->gop_len : 30 * 2);
 
     /* drop frame or not when bitrate overflow */
@@ -855,6 +854,19 @@ static MPP_RET mpi_rc_enc(MpiRc2TestCtx *ctx)
                     if (ctx->file.fp_enc_out)
                         fwrite(ptr, 1, len, ctx->file.fp_enc_out);
 
+                    /* check post packet first */
+                    if (len > ctx->dec_in_buf_post_size) {
+                        RK_U32 buf_size = MPP_ALIGN(len, SZ_4K);
+
+                        ctx->dec_in_buf_post = mpp_realloc(ctx->dec_in_buf_post, RK_U8, buf_size);
+                        ctx->dec_in_buf_post_size = buf_size;
+
+                        mpp_packet_set_data(ctx->dec_pkt_post, ctx->dec_in_buf_post);
+                        mpp_packet_set_size(ctx->dec_pkt_post, buf_size);
+                        mpp_packet_set_pos(ctx->dec_pkt_post, ctx->dec_in_buf_post);
+                        mpp_packet_set_length(ctx->dec_pkt_post, 0);
+                    }
+
                     /* decode one frame */
                     // write packet to dec input
                     mpp_packet_write(ctx->dec_pkt_post, 0, ptr, len);
@@ -916,12 +928,6 @@ static MPP_RET mpi_rc_buffer_init(MpiRc2TestCtx *ctx)
         goto RET;
     }
 
-    ret = mpp_buffer_get(ctx->pkt_grp, &ctx->enc_pkt_buf, packet_size);
-    if (ret) {
-        mpp_err("failed to get buffer for input frame ret %d\n", ret);
-        goto RET;
-    }
-
     ctx->dec_in_buf_post = mpp_calloc(RK_U8, packet_size);
     if (NULL == ctx->dec_in_buf_post) {
         mpp_err("mpi_dec_test malloc input stream buffer failed\n");
@@ -940,11 +946,6 @@ static MPP_RET mpi_rc_buffer_init(MpiRc2TestCtx *ctx)
     ctx->dec_ctx_post = NULL;
     MPP_FREE(ctx->dec_in_buf_post);
 
-    if (ctx->enc_pkt_buf) {
-        mpp_buffer_put(ctx->enc_pkt_buf);
-        ctx->enc_pkt_buf = NULL;
-    }
-
     if (ctx->pkt_grp) {
         mpp_buffer_group_put(ctx->pkt_grp);
         ctx->pkt_grp = NULL;
@@ -1078,11 +1079,6 @@ static MPP_RET mpi_rc_codec(MpiRc2TestCtx *ctx)
         ctx->enc_ctx = NULL;
     }
 
-    if (ctx->enc_pkt_buf) {
-        mpp_buffer_put(ctx->enc_pkt_buf);
-        ctx->enc_pkt_buf = NULL;
-    }
-
     if (ctx->pkt_grp) {
         mpp_buffer_group_put(ctx->pkt_grp);
         ctx->pkt_grp = NULL;
diff --git a/utils/mpi_dec_utils.c b/utils/mpi_dec_utils.c
index c78b761dd..a921ff171 100644
--- a/utils/mpi_dec_utils.c
+++ b/utils/mpi_dec_utils.c
@@ -696,7 +696,7 @@ RK_S32 mpi_dec_test_cmd_init(MpiDecTestCmd* cmd, int argc, char **argv)
 
     mpp_opt_init(&opts);
     /* should change node count when option increases */
-    mpp_opt_setup(opts, cmd, 35, dec_opt_cnt);
+    mpp_opt_setup(opts, cmd);
 
     for (i = 0; i < dec_opt_cnt; i++)
         mpp_opt_add(opts, &dec_opts[i]);
diff --git a/utils/mpi_enc_utils.c b/utils/mpi_enc_utils.c
index 9d525f356..af5e8ea19 100644
--- a/utils/mpi_enc_utils.c
+++ b/utils/mpi_enc_utils.c
@@ -292,7 +292,7 @@ RK_S32 mpi_enc_opt_rc(void *ctx, const char *next)
     }
 
     mpp_err("invalid rate control usage -rc rc_mode\n");
-    mpp_err("rc_mode 0:vbr 1:cbr 2:avbr 3:cvbr 4:fixqp\n");
+    mpp_err("rc_mode 0:vbr 1:cbr 2:fixqp 3:avbr 4:smtrc\n");
     return 0;
 }
 
@@ -488,6 +488,46 @@ RK_S32 mpi_enc_opt_sm(void *ctx, const char *next)
     return 0;
 }
 
+RK_S32 mpi_enc_opt_qpdd(void *ctx, const char *next)
+{
+    MpiEncTestArgs *cmd = (MpiEncTestArgs *)ctx;
+
+    if (next) {
+        cmd->cu_qp_delta_depth = atoi(next);
+        return 1;
+    }
+
+    mpp_err("invalid cu_qp_delta_depth\n");
+    return 0;
+}
+
+RK_S32 mpi_enc_opt_dbe(void *ctx, const char *next)
+{
+    MpiEncTestArgs *cmd = (MpiEncTestArgs *)ctx;
+
+    if (next) {
+        cmd->deblur_en = atoi(next);
+        return 1;
+    }
+
+    mpp_err("invalid deblur en\n");
+    return 0;
+}
+
+RK_S32 mpi_enc_opt_dbs(void *ctx, const char *next)
+{
+    MpiEncTestArgs *cmd = (MpiEncTestArgs *)ctx;
+
+    if (next) {
+        cmd->deblur_str = atoi(next);
+        return 1;
+    }
+
+    mpp_err("invalid deblur str\n");
+
+    return 0;
+}
+
 RK_S32 mpi_enc_opt_help(void *ctx, const char *next)
 {
     (void)ctx;
@@ -495,6 +535,123 @@ RK_S32 mpi_enc_opt_help(void *ctx, const char *next)
     return -1;
 }
 
+RK_S32 mpi_enc_opt_atf(void *ctx, const char *next)
+{
+    MpiEncTestArgs *cmd = (MpiEncTestArgs *)ctx;
+
+    if (next) {
+        cmd->anti_flicker_str = atoi(next);
+        return 1;
+    }
+
+    mpp_err("invalid cu_qp_delta_depth\n");
+    return 0;
+}
+
+RK_S32 mpi_enc_opt_atl(void *ctx, const char *next)
+{
+    MpiEncTestArgs *cmd = (MpiEncTestArgs *)ctx;
+
+    if (next) {
+        cmd->atl_str = atoi(next);
+        return 1;
+    }
+
+    mpp_err("invalid atl_str\n");
+    return 0;
+}
+
+RK_S32 mpi_enc_opt_atr_i(void *ctx, const char *next)
+{
+    MpiEncTestArgs *cmd = (MpiEncTestArgs *)ctx;
+
+    if (next) {
+        cmd->atr_str_i = atoi(next);
+        return 1;
+    }
+
+    mpp_err("invalid atr_str_i\n");
+    return 0;
+}
+
+RK_S32 mpi_enc_opt_atr_p(void *ctx, const char *next)
+{
+    MpiEncTestArgs *cmd = (MpiEncTestArgs *)ctx;
+
+    if (next) {
+        cmd->atr_str_p = atoi(next);
+        return 1;
+    }
+
+    mpp_err("invalid atr_str_p\n");
+    return 0;
+}
+
+RK_S32 mpi_enc_opt_sao_i(void *ctx, const char *next)
+{
+    MpiEncTestArgs *cmd = (MpiEncTestArgs *)ctx;
+
+    if (next) {
+        cmd->sao_str_i = atoi(next);
+        return 1;
+    }
+
+    mpp_err("invalid sao_str_i\n");
+    return 0;
+}
+
+RK_S32 mpi_enc_opt_sao_p(void *ctx, const char *next)
+{
+    MpiEncTestArgs *cmd = (MpiEncTestArgs *)ctx;
+
+    if (next) {
+        cmd->sao_str_p = atoi(next);
+        return 1;
+    }
+
+    mpp_err("invalid sao_str_p\n");
+    return 0;
+}
+
+RK_S32 mpi_enc_opt_bc(void *ctx, const char *next)
+{
+    MpiEncTestArgs *cmd = (MpiEncTestArgs *)ctx;
+
+    if (next) {
+        cmd->rc_container = atoi(next);
+        return 1;
+    }
+
+    mpp_err("invalid bitrate container\n");
+    return 0;
+}
+
+RK_S32 mpi_enc_opt_bias_i(void *ctx, const char *next)
+{
+    MpiEncTestArgs *cmd = (MpiEncTestArgs *)ctx;
+
+    if (next) {
+        cmd->bias_i = atoi(next);
+        return 1;
+    }
+
+    mpp_err("invalid bias i\n");
+    return 0;
+}
+
+RK_S32 mpi_enc_opt_bias_p(void *ctx, const char *next)
+{
+    MpiEncTestArgs *cmd = (MpiEncTestArgs *)ctx;
+
+    if (next) {
+        cmd->bias_p = atoi(next);
+        return 1;
+    }
+
+    mpp_err("invalid bias p\n");
+    return 0;
+}
+
 static MppOptInfo enc_opts[] = {
     {"i",       "input_file",           "input frame file",                         mpi_enc_opt_i},
     {"o",       "output_file",          "output encoded bitstream file",            mpi_enc_opt_o},
@@ -507,17 +664,29 @@ static MppOptInfo enc_opts[] = {
     {"tsrc",    "source type",          "input file source coding type",            mpi_enc_opt_tsrc},
     {"n",       "max frame number",     "max encoding frame number",                mpi_enc_opt_n},
     {"g",       "gop reference mode",   "gop_mode:gop_len:vi_len",                  mpi_enc_opt_g},
-    {"rc",      "rate control mode",    "set rc_mode, 0:vbr 1:cbr 2:fixqp 3:avbr",  mpi_enc_opt_rc},
+    {"rc",      "rate control mode",    "rc_mode, 0:vbr 1:cbr 2:fixqp 3:avbr 4:smtrc", mpi_enc_opt_rc},
     {"bps",     "bps target:min:max",   "set tareget:min:max bps",                  mpi_enc_opt_bps},
     {"fps",     "in/output fps",        "set input and output frame rate",          mpi_enc_opt_fps},
     {"qc",      "quality control",      "set qp_init:min:max:min_i:max_i",          mpi_enc_opt_qc},
-    {"fqc",     "frm quality control",  "set fqp min_i:max_i:min_p:max_p",          mpi_enc_opt_fqc},
+    {"fqc",     "frame quality control", "set fqp min_i:max_i:min_p:max_p",         mpi_enc_opt_fqc},
     {"s",       "instance_nb",          "number of instances",                      mpi_enc_opt_s},
     {"v",       "trace option",         "q - quiet f - show fps",                   mpi_enc_opt_v},
     {"l",       "loop count",           "loop encoding times for each frame",       mpi_enc_opt_l},
     {"ini",     "ini file",             "encoder extra ini config file",            mpi_enc_opt_ini},
     {"slt",     "slt file",             "slt verify data file",                     mpi_enc_opt_slt},
     {"sm",      "scene mode",           "scene_mode, 0:default 1:ipc",              mpi_enc_opt_sm},
+    {"qpdd",    "cu_qp_delta_depth",    "cu_qp_delta_depth, 0:1:2",                 mpi_enc_opt_qpdd},
+    {"dbe",     "deblur enable",        "deblur_en or qpmap_en, 0:close 1:open",           mpi_enc_opt_dbe},
+    {"dbs",     "deblur strength",      "deblur_str 0~3: hw + sw scheme; 4~7: hw scheme",  mpi_enc_opt_dbs},
+    {"atf",     "anti_flicker_str",     "anti_flicker_str, 0:off 1 2 3",            mpi_enc_opt_atf},
+    {"atl",     "atl_str",              "atl_str, 0:off 1 open",                    mpi_enc_opt_atl},
+    {"atr_i",   "atr_str_i",            "atr_str_i, 0:off 1 2 3",                   mpi_enc_opt_atr_i},
+    {"atr_p",   "atr_str_p",            "atr_str_p, 0:off 1 2 3",                   mpi_enc_opt_atr_p},
+    {"sao_i",   "sao_str_i",            "sao_str_i, 0:off 1 2 3",                   mpi_enc_opt_sao_i},
+    {"sao_p",   "sao_str_p",            "sao_str_p, 0:off 1 2 3",                   mpi_enc_opt_sao_p},
+    {"bc",      "bitrate container",    "rc_container, 0:off 1:weak 2:strong",      mpi_enc_opt_bc},
+    {"ibias",   "bias i",               "bias_i",                                   mpi_enc_opt_bias_i},
+    {"pbias",   "bias p",               "bias_p",                                   mpi_enc_opt_bias_p}
 };
 
 static RK_U32 enc_opt_cnt = MPP_ARRAY_ELEMS(enc_opts);
@@ -590,16 +759,14 @@ MPP_RET mpi_enc_test_cmd_update_by_args(MpiEncTestArgs* cmd, int argc, char **ar
 
     mpp_opt_init(&opts);
     /* should change node count when option increases */
-    mpp_opt_setup(opts, cmd, 71, enc_opt_cnt);
+    mpp_opt_setup(opts, cmd);
 
     for (i = 0; i < enc_opt_cnt; i++)
         mpp_opt_add(opts, &enc_opts[i]);
 
     /* mark option end */
     mpp_opt_add(opts, NULL);
-
     ret = mpp_opt_parse(opts, argc, argv);
-
     /* check essential parameter */
     if (cmd->type <= MPP_VIDEO_CodingAutoDetect) {
         mpp_err("invalid type %d\n", cmd->type);
@@ -613,7 +780,7 @@ MPP_RET mpi_enc_test_cmd_update_by_args(MpiEncTestArgs* cmd, int argc, char **ar
     if (!cmd->hor_stride)
         cmd->hor_stride = mpi_enc_width_default_stride(cmd->width, cmd->format);
     if (!cmd->ver_stride)
-        cmd->ver_stride = cmd->height;
+        cmd->ver_stride = MPP_ALIGN(cmd->height, 2);
 
     if (cmd->type_src == MPP_VIDEO_CodingUnused) {
         if (cmd->width <= 0 || cmd->height <= 0 ||
diff --git a/utils/mpi_enc_utils.h b/utils/mpi_enc_utils.h
index baa133b20..7169bc378 100644
--- a/utils/mpi_enc_utils.h
+++ b/utils/mpi_enc_utils.h
@@ -76,6 +76,24 @@ typedef struct MpiEncTestArgs_t {
 
     /* -sm scene_mode */
     RK_S32              scene_mode;
+    RK_S32              rc_container;
+    RK_S32              bias_i;
+    RK_S32              bias_p;
+
+    /* -qpdd cu_qp_delta_depth */
+    RK_S32              cu_qp_delta_depth;
+    RK_S32              anti_flicker_str;
+    RK_S32              atr_str_i;
+    RK_S32              atr_str_p;
+    RK_S32              atl_str;
+    RK_S32              sao_str_i;
+    RK_S32              sao_str_p;
+
+    /* -dbe deblur enable flag
+     * -dbs deblur strength
+     */
+    RK_S32              deblur_en;
+    RK_S32              deblur_str;
 
     /* -v q runtime log disable flag */
     RK_U32              quiet;
diff --git a/utils/mpp_enc_roi_utils.c b/utils/mpp_enc_roi_utils.c
index 9b529f23d..bf1bb68f0 100644
--- a/utils/mpp_enc_roi_utils.c
+++ b/utils/mpp_enc_roi_utils.c
@@ -673,13 +673,15 @@ MPP_RET mpp_enc_roi_init(MppEncRoiCtx *ctx, RK_U32 w, RK_U32 h, MppCodingType ty
     case ROI_TYPE_1 : {
         RK_S32 mb_w = MPP_ALIGN(impl->w, 16) / 16;
         RK_S32 mb_h = MPP_ALIGN(impl->h, 16) / 16;
+        RK_U32 ctu_w = MPP_ALIGN(impl->w, 64) / 64;
+        RK_U32 ctu_h  = MPP_ALIGN(impl->w, 64) / 64;
         RK_S32 stride_h = MPP_ALIGN(mb_w, 4);
         RK_S32 stride_v = MPP_ALIGN(mb_h, 4);
 
         mpp_log("set to vepu54x roi generation\n");
 
         impl->base_cfg_size = stride_h * stride_v * sizeof(Vepu541RoiCfg);
-        mpp_buffer_group_get_internal(&impl->roi_grp, MPP_BUFFER_TYPE_ION);
+        mpp_buffer_group_get_internal(&impl->roi_grp, MPP_BUFFER_TYPE_ION | MPP_BUFFER_FLAGS_CACHABLE);
 
         mpp_buffer_get(impl->roi_grp, &impl->roi_cfg.base_cfg_buf, impl->base_cfg_size);
         if (!impl->roi_cfg.base_cfg_buf) {
@@ -690,7 +692,14 @@ MPP_RET mpp_enc_roi_init(MppEncRoiCtx *ctx, RK_U32 w, RK_U32 h, MppCodingType ty
         /* create tmp buffer for hevc */
         if (type == MPP_VIDEO_CodingHEVC) {
             impl->tmp = mpp_malloc(Vepu541RoiCfg, stride_h * stride_v);
-            if (!impl->tmp)
+            impl->cu_map  = mpp_calloc(RK_U8, ctu_w * ctu_h);
+            impl->cu_size = ctu_w * ctu_h;
+            if (!impl->tmp || !impl->cu_map)
+                goto done;
+        } else {
+            impl->cu_map   = mpp_calloc(RK_U8, mb_w * mb_h);
+            impl->cu_size  = mb_w * mb_h;
+            if (!impl->cu_map)
                 goto done;
         }
 
@@ -722,7 +731,7 @@ MPP_RET mpp_enc_roi_init(MppEncRoiCtx *ctx, RK_U32 w, RK_U32 h, MppCodingType ty
         mpp_log("set to vepu58x roi generation\n");
 
         impl->roi_cfg.roi_qp_en = 1;
-        mpp_buffer_group_get_internal(&impl->roi_grp, MPP_BUFFER_TYPE_ION);
+        mpp_buffer_group_get_internal(&impl->roi_grp, MPP_BUFFER_TYPE_ION | MPP_BUFFER_FLAGS_CACHABLE);
         mpp_buffer_get(impl->roi_grp, &impl->roi_cfg.base_cfg_buf, impl->base_cfg_size);
         if (!impl->roi_cfg.base_cfg_buf) {
             goto done;
@@ -852,6 +861,7 @@ MPP_RET mpp_enc_roi_setup_meta(MppEncRoiCtx ctx, MppMeta meta)
         }
 
         mpp_meta_set_ptr(meta, KEY_ROI_DATA2, (void*)&impl->roi_cfg);
+        mpp_buffer_sync_ro_end(impl->roi_cfg.base_cfg_buf);
     } break;
     case ROI_TYPE_2 : {
         gen_vepu54x_roi(impl, impl->tmp);
@@ -868,6 +878,8 @@ MPP_RET mpp_enc_roi_setup_meta(MppEncRoiCtx ctx, MppMeta meta)
         }
 
         mpp_meta_set_ptr(meta, KEY_ROI_DATA2, (void*)&impl->roi_cfg);
+        mpp_buffer_sync_ro_end(impl->roi_cfg.base_cfg_buf);
+        mpp_buffer_sync_ro_end(impl->roi_cfg.qp_cfg_buf);
     } break;
     case ROI_TYPE_LEGACY : {
         MppEncROIRegion *region = impl->legacy_roi_region;
diff --git a/utils/mpp_opt.c b/utils/mpp_opt.c
index 3c37cf3df..05d03e513 100644
--- a/utils/mpp_opt.c
+++ b/utils/mpp_opt.c
@@ -55,23 +55,19 @@ MPP_RET mpp_opt_deinit(MppOpt opt)
     return MPP_OK;
 }
 
-MPP_RET mpp_opt_setup(MppOpt opt, void *ctx, RK_S32 node_cnt, RK_S32 opt_cnt)
+MPP_RET mpp_opt_setup(MppOpt opt, void *ctx)
 {
     MppOptImpl *impl = (MppOptImpl *)opt;
 
     if (NULL == impl)
         return MPP_NOK;
 
-    mpp_trie_init(&impl->trie, node_cnt, opt_cnt);
+    mpp_trie_init(&impl->trie, sizeof(MppOptInfo));
     if (impl->trie) {
         impl->ctx = ctx;
-        impl->node_cnt = node_cnt;
-        impl->info_cnt = opt_cnt;
         return MPP_OK;
     }
 
-    mpp_err_f("failed to setup node %d opt %d\n", node_cnt, opt_cnt);
-
     return MPP_NOK;
 }
 
@@ -82,18 +78,10 @@ MPP_RET mpp_opt_add(MppOpt opt, MppOptInfo *info)
     if (NULL == impl || NULL == impl->trie)
         return MPP_NOK;
 
-    if (NULL == info) {
-        RK_S32 node_cnt = mpp_trie_get_node_count(impl->trie);
-        RK_S32 info_cnt = mpp_trie_get_info_count(impl->trie);
-
-        if (impl->node_cnt != node_cnt || impl->info_cnt != info_cnt)
-            mpp_log("setup:real node %d:%d info %d:%d\n",
-                    impl->node_cnt, node_cnt, impl->info_cnt, info_cnt);
-
-        return MPP_OK;
-    }
+    if (NULL == info)
+        return mpp_trie_add_info(impl->trie, NULL, NULL);
 
-    return mpp_trie_add_info(impl->trie, &info->name);
+    return mpp_trie_add_info(impl->trie, info->name, info);
 }
 
 MPP_RET mpp_opt_parse(MppOpt opt, int argc, char **argv)
@@ -117,15 +105,15 @@ MPP_RET mpp_opt_parse(MppOpt opt, int argc, char **argv)
 
         if (opts[0] == '-' && opts[1] != '\0') {
             MppOptInfo *info = NULL;
-            const char **name = mpp_trie_get_info(impl->trie, opts + 1);
+            MppTrieInfo *node = mpp_trie_get_info(impl->trie, opts + 1);
             RK_S32 step = 0;
 
-            if (NULL == name) {
+            if (NULL == node) {
                 mpp_err("invalid option %s\n", opts + 1);
                 continue;
             }
 
-            info = container_of(name, MppOptInfo, name);
+            info = node->ctx;
             if (info->proc)
                 step = info->proc(impl->ctx, next);
 
diff --git a/utils/mpp_opt.h b/utils/mpp_opt.h
index 24946d778..b0d405b4a 100644
--- a/utils/mpp_opt.h
+++ b/utils/mpp_opt.h
@@ -41,7 +41,7 @@ extern "C" {
 MPP_RET mpp_opt_init(MppOpt *opt);
 MPP_RET mpp_opt_deinit(MppOpt opt);
 
-MPP_RET mpp_opt_setup(MppOpt opt, void *ctx, RK_S32 node_cnt, RK_S32 opt_cnt);
+MPP_RET mpp_opt_setup(MppOpt opt, void *ctx);
 /* Add NULL info to mark end of options */
 MPP_RET mpp_opt_add(MppOpt opt, MppOptInfo *info);
 
diff --git a/utils/utils.c b/utils/utils.c
index cecc28e31..d5f2ccfbc 100644
--- a/utils/utils.c
+++ b/utils/utils.c
@@ -44,6 +44,21 @@ void _show_options(int count, OptionInfo *options)
     }
 }
 
+static void rearrange_pix(RK_U8 *tmp_line, RK_U8 *base, RK_U32 n)
+{
+    RK_U16 * pix = (RK_U16 *)(tmp_line + n * 16);
+    RK_U16 * base_u16 = (RK_U16 *)(base + n * 10);
+
+    pix[0] =  base_u16[0] & 0x03FF;
+    pix[1] = (base_u16[0] & 0xFC00) >> 10 | (base_u16[1] & 0x000F) << 6;
+    pix[2] = (base_u16[1] & 0x3FF0) >> 4;
+    pix[3] = (base_u16[1] & 0xC000) >> 14 | (base_u16[2] & 0x00FF) << 2;
+    pix[4] = (base_u16[2] & 0xFF00) >> 8  | (base_u16[3] & 0x0003) << 8;
+    pix[5] = (base_u16[3] & 0x0FFC) >> 2;
+    pix[6] = (base_u16[3] & 0xF000) >> 12 | (base_u16[4] & 0x003F) << 4;
+    pix[7] = (base_u16[4] & 0xFFC0) >> 6;
+}
+
 void dump_mpp_frame_to_file(MppFrame frame, FILE *fp)
 {
     RK_U32 width    = 0;
@@ -137,37 +152,15 @@ void dump_mpp_frame_to_file(MppFrame frame, FILE *fp)
         }
 
         for (i = 0; i < height; i++, base_y += h_stride) {
-            for (k = 0; k < width / 8; k++) {
-                RK_U16 *pix = (RK_U16 *)(tmp_line + k * 16);
-                RK_U16 *base_u16 = (RK_U16 *)(base_y + k * 10);
-
-                pix[0] =  base_u16[0] & 0x03FF;
-                pix[1] = (base_u16[0] & 0xFC00) >> 10 | (base_u16[1] & 0x000F) << 6;
-                pix[2] = (base_u16[1] & 0x3FF0) >> 4;
-                pix[3] = (base_u16[1] & 0xC000) >> 14 | (base_u16[2] & 0x00FF) << 2;
-                pix[4] = (base_u16[2] & 0xFF00) >> 8  | (base_u16[3] & 0x0003) << 8;
-                pix[5] = (base_u16[3] & 0x0FFC) >> 2;
-                pix[6] = (base_u16[3] & 0xF000) >> 12 | (base_u16[4] & 0x003F) << 4;
-                pix[7] = (base_u16[4] & 0xFFC0) >> 6;
-            }
-            fwrite(tmp_line, width * sizeof(RK_U16) , 1, fp);
+            for (k = 0; k < MPP_ALIGN(width, 8) / 8; k++)
+                rearrange_pix(tmp_line, base_y, k);
+            fwrite(tmp_line, width * sizeof(RK_U16), 1, fp);
         }
 
         for (i = 0; i < height / 2; i++, base_c += h_stride) {
-            for (k = 0; k < (width / 8); k++) {
-                RK_U16 *pix = (RK_U16 *)(tmp_line + k * 16);
-                RK_U16 *base_u16 = (RK_U16 *)(base_c + k * 10);
-
-                pix[0] = base_u16[0] & 0x03FF;
-                pix[1] = (base_u16[0] & 0xFC00) >> 10 | (base_u16[1] & 0x000F) << 6;
-                pix[2] = (base_u16[1] & 0x3FF0) >> 4;
-                pix[3] = (base_u16[1] & 0xC000) >> 14 | (base_u16[2] & 0x00FF) << 2;
-                pix[4] = (base_u16[2] & 0xFF00) >> 8  | (base_u16[3] & 0x0003) << 8;
-                pix[5] = (base_u16[3] & 0x0FFC) >> 2;
-                pix[6] = (base_u16[3] & 0xF000) >> 12 | (base_u16[4] & 0x003F) << 4;
-                pix[7] = (base_u16[4] & 0xFFC0) >> 6;
-            }
-            fwrite(tmp_line, width * sizeof(RK_U16) , 1, fp);
+            for (k = 0; k < MPP_ALIGN(width, 8) / 8; k++)
+                rearrange_pix(tmp_line, base_c, k);
+            fwrite(tmp_line, width * sizeof(RK_U16), 1, fp);
         }
 
         MPP_FREE(tmp_line);
@@ -219,6 +212,10 @@ void dump_mpp_frame_to_file(MppFrame frame, FILE *fp)
 
         mpp_free(tmp);
     } break;
+    case MPP_FMT_YUV422_YUYV:
+    case MPP_FMT_YUV422_YVYU:
+    case MPP_FMT_YUV422_UYVY:
+    case MPP_FMT_YUV422_VYUY:
     case MPP_FMT_RGB565:
     case MPP_FMT_BGR565:
     case MPP_FMT_RGB555:
@@ -542,6 +539,7 @@ MPP_RET read_image(RK_U8 *buf, FILE *fp, RK_U32 width, RK_U32 height,
     }
 
     switch (fmt & MPP_FRAME_FMT_MASK) {
+    case MPP_FMT_YUV420SP_VU:
     case MPP_FMT_YUV420SP : {
         for (row = 0; row < height; row++) {
             read_size = fread(buf_y + row * hor_stride, 1, width, fp);
@@ -551,6 +549,8 @@ MPP_RET read_image(RK_U8 *buf, FILE *fp, RK_U32 width, RK_U32 height,
             }
         }
 
+        height = MPP_ALIGN(height, 2);
+        width = MPP_ALIGN(width, 2);
         for (row = 0; row < height / 2; row++) {
             read_size = fread(buf_u + row * hor_stride, 1, width, fp);
             if (read_size != width) {
@@ -568,6 +568,8 @@ MPP_RET read_image(RK_U8 *buf, FILE *fp, RK_U32 width, RK_U32 height,
             }
         }
 
+        width = MPP_ALIGN(width, 2);
+        height = MPP_ALIGN(height, 2);
         for (row = 0; row < height / 2; row++) {
             read_size = fread(buf_u + row * hor_stride / 2, 1, width / 2, fp);
             if (read_size != width / 2) {
@@ -594,6 +596,7 @@ MPP_RET read_image(RK_U8 *buf, FILE *fp, RK_U32 width, RK_U32 height,
     } break;
     case MPP_FMT_YUV422P :
     case MPP_FMT_YUV422SP :
+    case MPP_FMT_YUV422SP_VU:
     case MPP_FMT_BGR444 :
     case MPP_FMT_RGB444 :
     case MPP_FMT_RGB555 :