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Describe the feature you'd like
The question is whether we can disable interrupts during times that we write to the shift register so that the wifi module is buffered.
AC:
Make a separate branch for testing this and DO NOT MERGE, since it's highly experimental/theorectical
The text was updated successfully, but these errors were encountered:
for writing to shift register, disable interrupts, Keep CS pin high until we write, then we set it low, write to it then set CS pin high and re-enable interrupts for shift register.
We just need some chip select (GPIO 9, pin 21), SCK, MOSI, MISO
Describe the feature you'd like
The question is whether we can disable interrupts during times that we write to the shift register so that the wifi module is buffered.
AC:
The text was updated successfully, but these errors were encountered: