nor8_v1.v

// Copyright (C) 2020  Intel Corporation. All rights reserved.
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// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
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// to the terms and conditions of the Intel Program License 
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
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// PROGRAM		"Quartus Prime"
// VERSION		"Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
// CREATED		"Thu Dec 31 23:25:09 2020"

module nor8_v1(
	A,
	Z
);


input wire	[7:0] A;
output wire	Z;





assign	Z = ~(A[0] | A[2] | A[1] | A[3] | A[5] | A[4] | A[6] | A[7]);


endmodule