mux2_1_1.v

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// PROGRAM		"Quartus Prime"
// VERSION		"Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
// CREATED		"Thu Dec 31 23:17:00 2020"

module mux2_1_1(
	A,
	B,
	SEL,
	Z
);


input wire	A;
input wire	B;
input wire	SEL;
output wire	Z;

wire	SYNTHESIZED_WIRE_0;
wire	SYNTHESIZED_WIRE_1;
wire	SYNTHESIZED_WIRE_2;




assign	SYNTHESIZED_WIRE_2 = A & SYNTHESIZED_WIRE_0;

assign	SYNTHESIZED_WIRE_1 = SEL & B;

assign	SYNTHESIZED_WIRE_0 =  ~SEL;

assign	Z = SYNTHESIZED_WIRE_1 | SYNTHESIZED_WIRE_2;


endmodule