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I am working on Vivado 2021.1 and modified the tcl script so as to create the hardware projects in the said version. The XSA generation was successful and the applications were also built on Vitis 2021.1
First issue I am facing is while building the APP0 it shows error due to multiple reference to variables - time_start, time_delta & t. I am able to build the APP1 successfully though and proceeded with it only while running the ntw app on Cortex A53-0 while APP1 on Cortex A53-1.
Second issue is while running the application on ZCU102 board, I got the menu on the serial terminal and I set the core =1 and initialized the polynomial and also was able to print the polynomial. But after this I am not clear about what flow to follow - will it be direct "Execute code" or will it be "Send polynomial to FPGA" and then "Read polynomial from FPGA" etc. In any case my application is getting stuck in the function "send_eth_data_all" in this line - "while( (read_reg((UINTPTR)(core_config + 1)) & 0x00000001) == 0);"
I also tried with ILA on interfacor 1 module to see the states but the done_read is always high and done_write goes low when I run the "Send polynomial to FPGA command" and s00_axis_tvalid signal is never going high.
Could you please explain the data flow and code flow along with the expected behavior?
The text was updated successfully, but these errors were encountered:
It has been years since we worked on that project, and I do not remember everything well, or I do not have the setup to test it myself right now. We moved on with newer projects.
Apparently, we used Vivado 2018, hence did not work with Vitis or .xsa. The flow on the software side might have changed, requiring an adaptation, but I cannot guide you to it. I guess, you should make sure that the communication between processors works; if needed you can set the shared memory region correctly, maybe through the linker script.
Normally, you should see a menu on the serial terminal, with which you can set and send polynomials to given memories in the hardware. You can send a single command to the hardware, for example a move operation. If you send a polynomial to memory 1, you can move it to memory 5 and then read the polynomial from memory 5. You can have an execute code command which executes a set of commands for the multiplication. It should expect the input polynomials should be at specific memories, and yield the output polynomial at another. I guess, you can figure out those from code.c.
Hi Furkan,
I am working on Vivado 2021.1 and modified the tcl script so as to create the hardware projects in the said version. The XSA generation was successful and the applications were also built on Vitis 2021.1
First issue I am facing is while building the APP0 it shows error due to multiple reference to variables - time_start, time_delta & t. I am able to build the APP1 successfully though and proceeded with it only while running the ntw app on Cortex A53-0 while APP1 on Cortex A53-1.
Second issue is while running the application on ZCU102 board, I got the menu on the serial terminal and I set the core =1 and initialized the polynomial and also was able to print the polynomial. But after this I am not clear about what flow to follow - will it be direct "Execute code" or will it be "Send polynomial to FPGA" and then "Read polynomial from FPGA" etc. In any case my application is getting stuck in the function "send_eth_data_all" in this line - "while( (read_reg((UINTPTR)(core_config + 1)) & 0x00000001) == 0);"
I also tried with ILA on interfacor 1 module to see the states but the done_read is always high and done_write goes low when I run the "Send polynomial to FPGA command" and s00_axis_tvalid signal is never going high.
Could you please explain the data flow and code flow along with the expected behavior?
The text was updated successfully, but these errors were encountered: