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Copy path19_T2.asm
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19_T2.asm
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#include<p18f45k22.inc>
; CONFIG1H
CONFIG FOSC = INTIO67 ; Oscillator Selection bits (Internal oscillator block)
CONFIG PLLCFG = OFF ; 4X PLL Enable (Oscillator used directly)
CONFIG PRICLKEN = OFF ; Primary clock enable bit (Primary clock can be disabled by software)
CONFIG FCMEN = OFF ; Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
CONFIG IESO = OFF ; Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)
; CONFIG2L
CONFIG PWRTEN = OFF ; Power-up Timer Enable bit (Power up timer disabled)
CONFIG BOREN = OFF ; Brown-out Reset Enable bits (Brown-out Reset disabled in hardware and software)
CONFIG BORV = 190 ; Brown Out Reset Voltage bits (VBOR set to 1.90 V nominal)
; CONFIG2H
CONFIG WDTEN = OFF ; Watchdog Timer Enable bits (Watch dog timer is always disabled. SWDTEN has no effect.)
CONFIG WDTPS = 32768 ; Watchdog Timer Postscale Select bits (1:32768)
; CONFIG3H
CONFIG CCP2MX = PORTC1 ; CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
CONFIG PBADEN = OFF ; PORTB A/D Enable bit (PORTB<5:0> pins are configured as digital I/O on Reset)
CONFIG CCP3MX = PORTE0 ; P3A/CCP3 Mux bit (P3A/CCP3 input/output is mulitplexed with RE0)
CONFIG HFOFST = ON ; HFINTOSC Fast Start-up (HFINTOSC output and ready status are not delayed by the oscillator stable status)
CONFIG T3CMX = PORTC0 ; Timer3 Clock input mux bit (T3CKI is on RC0)
CONFIG P2BMX = PORTD2 ; ECCP2 B output mux bit (P2B is on RD2)
CONFIG MCLRE = INTMCLR ; MCLR Pin Enable bit (RE3 input pin enabled; MCLR disabled)
; CONFIG4L
CONFIG STVREN = OFF ; Stack Full/Underflow Reset Enable bit (Stack full/underflow will not cause Reset)
CONFIG LVP = OFF ; Single-Supply ICSP Enable bit (Single-Supply ICSP disabled)
CONFIG XINST = OFF ; Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))
; CONFIG5L
CONFIG CP0 = OFF ; Code Protection Block 0 (Block 0 (000800-001FFFh) not code-protected)
CONFIG CP1 = OFF ; Code Protection Block 1 (Block 1 (002000-003FFFh) not code-protected)
CONFIG CP2 = OFF ; Code Protection Block 2 (Block 2 (004000-005FFFh) not code-protected)
CONFIG CP3 = OFF ; Code Protection Block 3 (Block 3 (006000-007FFFh) not code-protected)
; CONFIG5H
CONFIG CPB = OFF ; Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected)
CONFIG CPD = OFF ; Data EEPROM Code Protection bit (Data EEPROM not code-protected)
; CONFIG6L
CONFIG WRT0 = OFF ; Write Protection Block 0 (Block 0 (000800-001FFFh) not write-protected)
CONFIG WRT1 = OFF ; Write Protection Block 1 (Block 1 (002000-003FFFh) not write-protected)
CONFIG WRT2 = OFF ; Write Protection Block 2 (Block 2 (004000-005FFFh) not write-protected)
CONFIG WRT3 = OFF ; Write Protection Block 3 (Block 3 (006000-007FFFh) not write-protected)
; CONFIG6H
CONFIG WRTC = OFF ; Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
CONFIG WRTB = OFF ; Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected)
CONFIG WRTD = OFF ; Data EEPROM Write Protection bit (Data EEPROM not write-protected)
; CONFIG7L
CONFIG EBTR0 = OFF ; Table Read Protection Block 0 (Block 0 (000800-001FFFh) not protected from table reads executed in other blocks)
CONFIG EBTR1 = OFF ; Table Read Protection Block 1 (Block 1 (002000-003FFFh) not protected from table reads executed in other blocks)
CONFIG EBTR2 = OFF ; Table Read Protection Block 2 (Block 2 (004000-005FFFh) not protected from table reads executed in other blocks)
CONFIG EBTR3 = OFF
; Table Read Protection Block 3 (Block 3 (006000-007FFFh) not protected from table reads executed in other blocks)
; CONFIG7H
CONFIG EBTRB = OFF ; Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks)
main:
movlw 0 ; w = 0
addwf 0x250,W ; se suma w= w+i
addwf 0x251,W ; Se suma: w = w+j
MOVWF 0x05A ; j = j + i
here:
goto here
end