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msm8937.dtsi
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/*
* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "skeleton64.dtsi"
#include <dt-bindings/clock/msm-clocks-8952.h>
#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>
/ {
model = "Qualcomm Technologies, Inc. MSM8937";
compatible = "qcom,msm8937";
qcom,msm-id = <294 0x0>;
interrupt-parent = <&intc>;
chosen {
bootargs = "sched_enable_hmp=1";
};
firmware: firmware {
android {
compatible = "android,firmware";
fstab {
compatible = "android,fstab";
vendor {
compatible = "android,vendor";
dev = "/dev/block/platform/soc/7824900.sdhci/by-name/vendor";
type = "ext4";
mnt_flags = "ro,barrier=1,discard";
fsmgr_flags = "wait";
status = "ok";
};
system {
compatible = "android,system";
dev = "/dev/block/platform/soc/7824900.sdhci/by-name/system";
type = "ext4";
mnt_flags = "ro,barrier=1,discard";
fsmgr_flags = "wait";
status = "ok";
};
};
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
pstore_mem: pstore_region@0 {
compatible = "removed-dma-pool";
no-map-fixup;
reg = <0x0 0x9FF00000 0x0 0x100000>;
};
other_ext_mem: other_ext_region@0 {
compatible = "removed-dma-pool";
no-map;
//TINNO BEGIN
//DATE20171103, Modified For ELAN FP By qiao.li,IAAO-141
reg = <0x0 0x84A00000 0x0 0x1E00000>;
//TINNO END
};
modem_mem: modem_region@0 {
compatible = "removed-dma-pool";
no-map;
reg = <0x0 0x86800000 0x0 0x5000000>;
};
adsp_fw_mem: adsp_fw_region@0 {
compatible = "removed-dma-pool";
no-map;
reg = <0x0 0x8b800000 0x0 0x1100000>;
};
wcnss_fw_mem: wcnss_fw_region@0 {
compatible = "removed-dma-pool";
no-map;
reg = <0x0 0x8c900000 0x0 0x700000>;
};
venus_mem: venus_region@0 {
compatible = "shared-dma-pool";
reusable;
alloc-ranges = <0x0 0x80000000 0x0 0x10000000>;
alignment = <0 0x400000>;
size = <0 0x0800000>;
};
secure_mem: secure_region@0 {
compatible = "shared-dma-pool";
reusable;
alignment = <0 0x400000>;
size = <0 0x7000000>;
};
qseecom_mem: qseecom_region@0 {
compatible = "shared-dma-pool";
reusable;
alignment = <0 0x400000>;
size = <0 0x1000000>;
};
adsp_mem: adsp_region@0 {
compatible = "shared-dma-pool";
reusable;
alignment = <0 0x400000>;
size = <0 0x400000>;
};
cont_splash_mem: splash_region@83000000 {
reg = <0x0 0x90000000 0x0 0x1400000>;
};
};
aliases {
/* smdtty devices */
smd1 = &smdtty_apps_fm;
smd2 = &smdtty_apps_riva_bt_acl;
smd3 = &smdtty_apps_riva_bt_cmd;
smd4 = &smdtty_mbalbridge;
smd5 = &smdtty_apps_riva_ant_cmd;
smd6 = &smdtty_apps_riva_ant_data;
smd7 = &smdtty_data1;
smd8 = &smdtty_data4;
smd11 = &smdtty_data11;
smd21 = &smdtty_data21;
smd36 = &smdtty_loopback;
i2c2 = &i2c_2;
//i2c5 = &i2c_5;
spi3 = &spi_3;
sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
sdhc2 = &sdhc_2; /* SDC2 for SD card */
i2c3 = &i2c_3;
};
soc: soc { };
};
#include "msm8937-pinctrl.dtsi"
#include "msm8937-cpu.dtsi"
#include "msm8937-gpu.dtsi"
#include "msm8937-ion.dtsi"
#include "msm-arm-smmu-8937.dtsi"
#include "msm8937-coresight.dtsi"
#include "msm8937-bus.dtsi"
#include "msm8937-smp2p.dtsi"
#include "msm8937-pm.dtsi"
#include "msm8937-iommu-domains.dtsi"
#include "msm8937-vidc.dtsi"
&soc {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0x0b000000 0x1000>,
<0x0b002000 0x1000>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <1 2 0xff08>,
<1 3 0xff08>,
<1 4 0xff08>,
<1 1 0xff08>;
clock-frequency = <19200000>;
};
timer@b120000 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "arm,armv7-timer-mem";
reg = <0xb120000 0x1000>;
clock-frequency = <19200000>;
frame@b121000 {
frame-number = <0>;
interrupts = <0 8 0x4>,
<0 7 0x4>;
reg = <0xb121000 0x1000>,
<0xb122000 0x1000>;
};
frame@b123000 {
frame-number = <1>;
interrupts = <0 9 0x4>;
reg = <0xb123000 0x1000>;
status = "disabled";
};
frame@b124000 {
frame-number = <2>;
interrupts = <0 10 0x4>;
reg = <0xb124000 0x1000>;
status = "disabled";
};
frame@b125000 {
frame-number = <3>;
interrupts = <0 11 0x4>;
reg = <0xb125000 0x1000>;
status = "disabled";
};
frame@b126000 {
frame-number = <4>;
interrupts = <0 12 0x4>;
reg = <0xb126000 0x1000>;
status = "disabled";
};
frame@b127000 {
frame-number = <5>;
interrupts = <0 13 0x4>;
reg = <0xb127000 0x1000>;
status = "disabled";
};
frame@b128000 {
frame-number = <6>;
interrupts = <0 14 0x4>;
reg = <0xb128000 0x1000>;
status = "disabled";
};
};
qcom,rmtfs_sharedmem@00000000 {
compatible = "qcom,sharedmem-uio";
reg = <0x00000000 0x00180000>;
reg-names = "rmtfs";
qcom,client-id = <0x00000001>;
};
restart@4ab000 {
compatible = "qcom,pshold";
reg = <0x4ab000 0x4>,
<0x193d100 0x4>;
reg-names = "pshold-base", "tcsr-boot-misc-detect";
};
qcom,mpm2-sleep-counter@4a3000 {
compatible = "qcom,mpm2-sleep-counter";
reg = <0x4a3000 0x1000>;
clock-frequency = <32768>;
};
cpu-pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <1 7 0xff00>;
};
qcom,sps {
compatible = "qcom,msm_sps_4k";
qcom,pipe-attr-ee;
};
tsens: tsens@4a8000 {
compatible = "qcom,msm8937-tsens";
reg = <0x4a8000 0x2000>,
<0xa4000 0x1000>;
reg-names = "tsens_physical", "tsens_eeprom_physical";
interrupts = <0 184 0>;
interrupt-names = "tsens-upper-lower";
qcom,sensors = <11>;
qcom,slope = <3200 3200 3200 3200 3200 3200 3200 3200 3200
3200 3200>;
qcom,sensor-id = <0 1 2 3 4 5 6 7 8 9 10>;
qcom,valid-status-check;
qcom,temp1-offset = <1 (-9) (-6) (-4) 0 (-3) (-2) 0 2 (-2)
(-3)>;
qcom,temp2-offset = <0 10 (-1) 5 (-2) (-9) (-13) 1 1 0 2>;
};
slim_msm: slim@c140000{
cell-index = <1>;
compatible = "qcom,slim-ngd";
reg = <0xc140000 0x2c000>,
<0xc104000 0x2a000>;
reg-names = "slimbus_physical", "slimbus_bam_physical";
interrupts = <0 163 0>, <0 180 0>;
interrupt-names = "slimbus_irq", "slimbus_bam_irq";
qcom,apps-ch-pipes = <0x600000>;
qcom,ea-pc = <0x230>;
status = "disabled";
};
qcom,sensor-information {
compatible = "qcom,sensor-information";
sensor_information0: qcom,sensor-information-0 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor0";
};
sensor_information1: qcom,sensor-information-1 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor1";
};
sensor_information2: qcom,sensor-information-2 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor2";
qcom,alias-name = "pop_mem";
};
sensor_information3: qcom,sensor-information-3 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor3";
};
sensor_information4: qcom,sensor-information-4 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor4";
qcom,alias-name = "L2_cache_1";
};
sensor_information5: qcom,sensor-information-5 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor5";
};
sensor_information6: qcom,sensor-information-6 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor6";
};
sensor_information7: qcom,sensor-information-7 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor7";
};
sensor_information8: qcom,sensor-information-8 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor8";
};
sensor_information9: qcom,sensor-information-9 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor9";
};
sensor_information10: qcom,sensor-information-10 {
qcom,sensor-type = "tsens";
qcom,sensor-name = "tsens_tz_sensor10";
qcom,alias-name = "gpu";
};
sensor_information11: qcom,sensor-information-11 {
qcom,sensor-type = "adc";
qcom,sensor-name = "pa_therm0";
};
sensor_information12: qcom,sensor-information-12 {
qcom,sensor-type = "adc";
qcom,sensor-name = "pa_therm1";
};
sensor_information13: qcom,sensor-information-13 {
qcom,sensor-type = "adc";
qcom,sensor-name = "xo_therm";
};
sensor_information14: qcom,sensor-information-14 {
qcom,sensor-type = "adc";
qcom,sensor-name = "xo_therm_buf";
};
sensor_information15: qcom,sensor-information-15 {
qcom,sensor-type = "adc";
qcom,sensor-name = "case_therm";
};
sensor_information16: qcom,sensor-information-16 {
qcom,sensor-type = "alarm";
qcom,sensor-name = "pm8937_tz";
qcom,scaling-factor = <1000>;
};
};
mitigation_profile0: qcom,limit_info-0 {
qcom,temperature-sensor = <&sensor_information5>;
qcom,boot-frequency-mitigate;
qcom,hotplug-mitigation-enable;
qcom,emergency-frequency-mitigate;
};
mitigation_profile1: qcom,limit_info-1 {
qcom,temperature-sensor = <&sensor_information6>;
qcom,boot-frequency-mitigate;
qcom,hotplug-mitigation-enable;
qcom,emergency-frequency-mitigate;
};
mitigation_profile2: qcom,limit_info-2 {
qcom,temperature-sensor = <&sensor_information7>;
qcom,boot-frequency-mitigate;
qcom,hotplug-mitigation-enable;
qcom,emergency-frequency-mitigate;
};
mitigation_profile3: qcom,limit_info-3 {
qcom,temperature-sensor = <&sensor_information8>;
qcom,boot-frequency-mitigate;
qcom,hotplug-mitigation-enable;
qcom,emergency-frequency-mitigate;
};
mitigation_profile4: qcom,limit_info-4 {
qcom,temperature-sensor = <&sensor_information9>;
qcom,boot-frequency-mitigate;
qcom,hotplug-mitigation-enable;
qcom,emergency-frequency-mitigate;
};
qcom,msm-thermal {
compatible = "qcom,msm-thermal";
qcom,sensor-id = <5>;
qcom,poll-ms = <250>;
qcom,limit-temp = <60>;
qcom,temp-hysteresis = <10>;
qcom,freq-step = <2>;
qcom,core-limit-temp = <80>;
qcom,core-temp-hysteresis = <10>;
qcom,hotplug-temp = <105>;
qcom,hotplug-temp-hysteresis = <15>;
qcom,freq-mitigation-temp = <105>;
qcom,freq-mitigation-temp-hysteresis = <15>;
qcom,freq-mitigation-value = <400000>;
qcom,online-hotplug-core;
qcom,synchronous-cluster-id = <0 1>;
qcom,synchronous-cluster-map = <1 4 &CPU0 &CPU1 &CPU2 &CPU3>,
<0 4 &CPU4 &CPU5 &CPU6 &CPU7>;
qcom,disable-cx-phase-ctrl;
qcom,disable-gfx-phase-ctrl;
qcom,disable-vdd-mx;
qcom,disable-psm;
qcom,disable-ocr;
qcom,vdd-restriction-temp = <5>;
qcom,vdd-restriction-temp-hysteresis = <10>;
vdd-dig-supply = <&pm8937_s2_floor_level>;
qcom,vdd-dig-rstr {
qcom,vdd-rstr-reg = "vdd-dig";
qcom,levels = <RPM_SMD_REGULATOR_LEVEL_NOM_PLUS
RPM_SMD_REGULATOR_LEVEL_TURBO
RPM_SMD_REGULATOR_LEVEL_TURBO>;
qcom,min-level = <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
};
msm_thermal_freq: qcom,vdd-apps-rstr {
qcom,vdd-rstr-reg = "vdd-apps";
qcom,levels = <900000>;
qcom,freq-req;
};
};
qcom,bcl {
compatible = "qcom,bcl";
qcom,bcl-enable;
qcom,bcl-framework-interface;
qcom,bcl-freq-control-list = <&CPU0 &CPU1 &CPU2 &CPU3
&CPU4 &CPU5 &CPU6 &CPU7>;
qcom,bcl-hotplug-list = <&CPU2 &CPU3>;
//qcom,bcl-soc-hotplug-list = <&CPU0 &CPU1 &CPU2 &CPU3>;
qcom,bcl-soc-hotplug-list = <&CPU2 &CPU3>;
qcom,ibat-monitor {
qcom,low-threshold-uamp = <3400000>;
qcom,high-threshold-uamp = <4200000>;
//qcom,mitigation-freq-khz = <998400>;
qcom,mitigation-freq-khz = <1401000>;
qcom,vph-high-threshold-uv = <3500000>;
qcom,vph-low-threshold-uv = <3200000>;
qcom,soc-low-threshold = <10>;
qcom,thermal-handle = <&msm_thermal_freq>;
};
};
blsp1_uart2: serial@78b0000 {
compatible = "qcom,msm-lsuart-v14";
reg = <0x78b0000 0x200>;
interrupts = <0 108 0>;
status = "disabled";
clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>,
<&clock_gcc clk_gcc_blsp1_ahb_clk>;
clock-names = "core_clk", "iface_clk";
};
dma_blsp1: qcom,sps-dma@7884000 { /* BLSP1 */
#dma-cells = <4>;
compatible = "qcom,sps-dma";
reg = <0x7884000 0x1f000>;
interrupts = <0 238 0>;
qcom,summing-threshold = <10>;
};
dma_blsp2: qcom,sps-dma@7ac4000 { /* BLSP2 */
#dma-cells = <4>;
compatible = "qcom,sps-dma";
reg = <0x7ac4000 0x1f000>;
interrupts = <0 239 0>;
qcom,summing-threshold = <10>;
};
i2c_2: i2c@78b6000 { /* BLSP1 QUP2 */
compatible = "qcom,i2c-msm-v2";
#address-cells = <1>;
#size-cells = <0>;
reg-names = "qup_phys_addr";
reg = <0x78b6000 0x600>;
interrupt-names = "qup_irq";
interrupts = <0 96 0>;
qcom,clk-freq-out = <400000>;
qcom,clk-freq-in = <19200000>;
clock-names = "iface_clk", "core_clk";
clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
<&clock_gcc clk_gcc_blsp1_qup2_i2c_apps_clk>;
pinctrl-names = "i2c_active", "i2c_sleep";
pinctrl-0 = <&i2c_2_active>;
pinctrl-1 = <&i2c_2_sleep>;
qcom,noise-rjct-scl = <0>;
qcom,noise-rjct-sda = <0>;
qcom,master-id = <86>;
dmas = <&dma_blsp1 6 64 0x20000020 0x20>,
<&dma_blsp1 7 32 0x20000020 0x20>;
dma-names = "tx", "rx";
pericom-type-c@1d {
compatible = "pericom,usb-type-c";
reg = <0x1d>;
vdd_io-supply = <&pm8937_l5>;
interrupt-parent = <&tlmm>;
interrupts = <97 2>; /* TLMM 97, TRIGGER_FALLING */
pericom,enb-gpio = <&tlmm 131 0x1>; /* active low */
pinctrl-names = "default";
pinctrl-0 = <&usbc_int_default>;
};
/* DSI_TO_HDMI I2C configuration */
adv7533@39 {
compatible = "adv7533";
reg = <0x39>;
instance_id = <0>;
adi,video-mode = <3>; /* 3 = 1080p */
adi,main-addr = <0x39>;
adi,cec-dsi-addr = <0x3C>;
adi,enable-audio;
pinctrl-names = "pmx_adv7533_active",
"pmx_adv7533_suspend";
pinctrl-0 = <&adv7533_int_active>;
pinctrl-1 = <&adv7533_int_suspend>;
adi,irq-gpio = <&tlmm 126 0x2002>;
hpd-5v-en-supply = <&adv_vreg>;
qcom,supply-names = "hpd-5v-en";
qcom,min-voltage-level = <0>;
qcom,max-voltage-level = <0>;
qcom,enable-load = <0>;
qcom,disable-load = <0>;
};
};
i2c_3: i2c@78b7000 { /* BLSP1 QUP3 */
compatible = "qcom,i2c-msm-v2";
#address-cells = <1>;
#size-cells = <0>;
reg-names = "qup_phys_addr";
reg = <0x78b7000 0x600>;
interrupt-names = "qup_irq";
interrupts = <0 97 0>;
qcom,clk-freq-out = <400000>;
qcom,clk-freq-in = <19200000>;
clock-names = "iface_clk", "core_clk";
clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
<&clock_gcc clk_gcc_blsp1_qup3_i2c_apps_clk>;
pinctrl-names = "i2c_active", "i2c_sleep";
pinctrl-0 = <&i2c_3_active>;
pinctrl-1 = <&i2c_3_sleep>;
qcom,noise-rjct-scl = <0>;
qcom,noise-rjct-sda = <0>;
qcom,master-id = <86>;
dmas = <&dma_blsp1 8 64 0x20000020 0x20>,
<&dma_blsp1 9 32 0x20000020 0x20>;
dma-names = "tx", "rx";
// status = "disabled";
};
i2c_5: i2c@7af5000 { /* BLSP2 QUP1 */
compatible = "qcom,i2c-msm-v2";
#address-cells = <1>;
#size-cells = <0>;
reg-names = "qup_phys_addr";
reg = <0x7af5000 0x600>;
interrupt-names = "qup_irq";
interrupts = <0 299 0>;
qcom,clk-freq-out = <400000>;
qcom,clk-freq-in = <19200000>;
clock-names = "iface_clk", "core_clk";
clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>,
<&clock_gcc clk_gcc_blsp2_qup1_i2c_apps_clk>;
pinctrl-names = "i2c_active", "i2c_sleep";
pinctrl-0 = <&i2c_5_active>;
pinctrl-1 = <&i2c_5_sleep>;
qcom,noise-rjct-scl = <0>;
qcom,noise-rjct-sda = <0>;
qcom,master-id = <84>;
dmas = <&dma_blsp2 4 64 0x20000020 0x20>,
<&dma_blsp2 5 32 0x20000020 0x20>;
dma-names = "tx", "rx";
};
spi_3: spi@78b7000 { /* BLSP1 QUP3 */
compatible = "qcom,spi-qup-v2";
#address-cells = <1>;
#size-cells = <0>;
reg-names = "spi_physical", "spi_bam_physical";
reg = <0x78b7000 0x600>,
<0x7884000 0x1f000>;
interrupt-names = "spi_irq", "spi_bam_irq";
interrupts = <0 97 0>, <0 238 0>;
spi-max-frequency = <19200000>;
pinctrl-names = "spi_default", "spi_sleep";
pinctrl-0 = <&spi3_default &spi3_cs0_active>;
pinctrl-1 = <&spi3_sleep &spi3_cs0_sleep>;
clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
<&clock_gcc clk_gcc_blsp1_qup3_spi_apps_clk>;
clock-names = "iface_clk", "core_clk";
qcom,infinite-mode = <0>;
qcom,use-bam;
qcom,use-pinctrl;
qcom,ver-reg-exists;
qcom,bam-consumer-pipe-index = <8>;
qcom,bam-producer-pipe-index = <9>;
qcom,master-id = <86>;
status = "disabled";
};
clock_gcc: qcom,gcc@1800000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "qcom,gcc-8937";
reg = <0x1800000 0x80000>,
<0xb016000 0x00040>,
<0xb116000 0x00040>,
<0x00a6018 0x00004>;
reg-names = "cc_base", "apcs_c1_base",
"apcs_c0_base", "efuse";
vdd_dig-supply = <&pm8937_s2_level>;
vdd_sr2_dig-supply = <&pm8937_s2_level_ao>;
vdd_sr2_pll-supply = <&pm8937_l7_ao>;
vdd_hf_dig-supply = <&pm8937_s2_level_ao>;
vdd_hf_pll-supply = <&pm8937_l7_ao>;
#clock-cells = <1>;
ranges;
qcom,spm@0 {
compatible = "qcom,gcc-spm-8937";
reg = <0x0b111200 0x100>,
<0x0b011200 0x100>;
reg-names = "spm_c0_base", "spm_c1_base";
};
};
clock_debug: qcom,cc-debug@1874000 {
compatible = "qcom,cc-debug-8937";
reg = <0x1874000 0x4>,
<0xb11101c 0x8>;
reg-names = "cc_base", "meas";
#clock-cells = <1>;
};
clock_gcc_mdss: qcom,gcc-mdss@1800000 {
compatible = "qcom,gcc-mdss-8937";
clocks = <&mdss_dsi0_pll clk_dsi_pll0_pixel_clk_src>,
<&mdss_dsi0_pll clk_dsi_pll0_byte_clk_src>,
<&mdss_dsi1_pll clk_dsi_pll1_pixel_clk_src>,
<&mdss_dsi1_pll clk_dsi_pll1_byte_clk_src>;
clock-names = "pixel_src", "byte_src", "pclk1_src",
"byte1_src";
#clock-cells = <1>;
};
clock_cpu: qcom,cpu-clock-8939@b111050 {
compatible = "qcom,cpu-clock-8939";
reg = <0xb011050 0x8>,
<0xb111050 0x8>,
<0xb1d1050 0x8>,
<0x00a412c 0x8>;
reg-names = "apcs-c1-rcg-base", "apcs-c0-rcg-base",
"apcs-cci-rcg-base", "efuse";
vdd-c0-supply = <&apc_vreg_corner>;
vdd-c1-supply = <&apc_vreg_corner>;
vdd-cci-supply = <&apc_vreg_corner>;
clocks = <&clock_gcc clk_gpll0_ao_clk_src>,
<&clock_gcc clk_a53ss_c0_pll>,
<&clock_gcc clk_gpll0_ao_clk_src>,
<&clock_gcc clk_a53ss_c1_pll>,
<&clock_gcc clk_gpll0_ao_clk_src>,
<&clock_gcc clk_gpll0_ao_clk_src>;
clock-names = "clk-c0-4", "clk-c0-5",
"clk-c1-4", "clk-c1-5",
"clk-cci-4", "clk-cci-2";
qcom,speed0-bin-v0-c0 =
< 0 0>,
< 768000000 1>,
< 902400000 2>,
< 998400000 4>,
< 1094400000 6>;
qcom,speed0-bin-v0-c1 =
< 0 0>,
< 960000000 1>,
< 1094400000 2>,
< 1248000000 4>,
< 1344000000 5>,
< 1401000000 6>;
qcom,speed0-bin-v0-cci =
< 0 0>,
< 400000000 1>,
< 533333333 3>;
qcom,speed1-bin-v0-c0 =
< 0 0>,
< 768000000 1>,
< 902400000 2>,
< 998400000 4>,
< 1094400000 6>,
< 1209600000 7>;
qcom,speed1-bin-v0-c1 =
< 0 0>,
< 960000000 1>,
< 1094400000 2>,
< 1248000000 4>,
< 1344000000 5>,
< 1401000000 6>,
< 1497600000 7>;
qcom,speed1-bin-v0-cci =
< 0 0>,
< 400000000 1>,
< 533333333 3>;
qcom,speed2-bin-v0-c0 =
< 0 0>,
< 768000000 1>,
< 902400000 2>,
< 998400000 3>;
qcom,speed2-bin-v0-c1 =
< 0 0>,
< 960000000 1>,
< 1094400000 2>,
< 1209600000 3>;
qcom,speed2-bin-v0-cci =
< 0 0>,
< 400000000 1>,
< 533333333 3>;
#clock-cells = <1>;
};
msm_cpufreq: qcom,msm-cpufreq {
compatible = "qcom,msm-cpufreq";
clock-names = "l2_clk", "cpu0_clk", "cpu1_clk", "cpu2_clk",
"cpu3_clk", "cpu4_clk", "cpu5_clk",
"cpu6_clk", "cpu7_clk";
clocks = <&clock_cpu clk_cci_clk>,
<&clock_cpu clk_a53_bc_clk>,
<&clock_cpu clk_a53_bc_clk>,
<&clock_cpu clk_a53_bc_clk>,
<&clock_cpu clk_a53_bc_clk>,
<&clock_cpu clk_a53_lc_clk>,
<&clock_cpu clk_a53_lc_clk>,
<&clock_cpu clk_a53_lc_clk>,
<&clock_cpu clk_a53_lc_clk>;
qcom,governor-per-policy;
qcom,cpufreq-table-0 =
< 960000 >,
< 1094400 >,
< 1209600 >,
< 1248000 >,
< 1344000 >,
< 1401000 >,
< 1497600 >;
qcom,cpufreq-table-4 =
< 768000 >,
< 902400 >,
< 998400 >,
< 1094400 >,
< 1209600 >;
};
cci_cache: qcom,cci {
compatible = "devfreq-simple-dev";
clock-names = "devfreq_clk";
clocks = <&clock_cpu clk_cci_clk>;
governor = "cpufreq";
freq-tbl-khz =
< 400000 >,
< 533333 >;
};
cpubw: qcom,cpubw {
compatible = "qcom,devbw";
governor = "cpufreq";
qcom,src-dst-ports = <1 512>;
qcom,active-only;
qcom,bw-tbl =
< 769 /* 100.8 MHz */ >,
< 1611 /* 211.2 MHz */ >,
< 2124 /* 278.4 MHz */ >,
< 2929 /* 384 MHz */ >, /* SVS */
< 4101 /* 537.6 MHz */ >,
< 4248 /* 556.8 MHz */ >,
< 5053 /* 662.4 MHz */ >, /* SVS+ */
< 5712 /* 748.8 MHz */ >, /* NOM */
< 6152 /* 806.4 MHz */ >, /* NOM+ */
< 7031 /* 921.6 MHz */ >; /* TURBO */
};
qcom,cpu-bwmon {
compatible = "qcom,bimc-bwmon2";
reg = <0x408000 0x300>, <0x401000 0x200>;
reg-names = "base", "global_base";
interrupts = <0 183 4>;
qcom,mport = <0>;
qcom,target-dev = <&cpubw>;
};
mincpubw: qcom,mincpubw {
compatible = "qcom,devbw";
governor = "cpufreq";
qcom,src-dst-ports = <1 512>;
qcom,active-only;
qcom,bw-tbl =
< 769 /* 100.8 MHz */ >,
< 1611 /* 211.2 MHz */ >,
< 2124 /* 278.4 MHz */ >,
< 2929 /* 384 MHz */ >, /* SVS */
< 4101 /* 537.6 MHz */ >,
< 4248 /* 556.8 MHz */ >,
< 5053 /* 662.4 MHz */ >, /* SVS+ */
< 5712 /* 748.8 MHz */ >, /* NOM */
< 6152 /* 806.4 MHz */ >, /* NOM+ */
< 7031 /* 921.6 MHz */ >; /* TURBO */
};
devfreq-cpufreq {
cpubw-cpufreq {
target-dev = <&cpubw>;
cpu-to-dev-map-0 =
< 998400 2929 >, /* SVS */
< 1094400 5053 >, /* NOM */
< 1248000 5712 >, /* NOM+ */
< 1344000 7031 >,
< 1497600 7031 >; /* TURBO */
cpu-to-dev-map-4 =
< 806400 2929 >, /* SVS */
< 902400 5053 >, /* NOM */
< 998400 6152 >, /* NOM+ */
< 1209600 7031 >; /* TURBO */
};
cci-cpufreq {
target-dev = <&cci_cache>;
cpu-to-dev-map-0 =
< 998400 400000 >, /* SVS */
< 1094400 400000 >, /* NOM */
< 1248000 533333 >, /* NOM+ */
< 1344000 533333 >,
< 1497600 533333 >; /* TURBO */
cpu-to-dev-map-4 =
< 806400 400000 >, /* SVS */
< 902400 400000 >, /* NOM */
< 998400 533333 >, /* NOM+ */
< 1209600 533333 >; /* TURBO */
};
mincpubw-cpufreq {
target-dev = <&mincpubw>;
cpu-to-dev-map-0 =
< 1094400 2929 >,
< 1497600 4248 >;
cpu-to-dev-map-4 =
< 998400 2929 >,
< 1209600 4248 >;
};
};
blsp2_uart1: uart@7aef000 {
compatible = "qcom,msm-hsuart-v14";
reg = <0x7aef000 0x200>,
<0x7ac4000 0x1f000>;
reg-names = "core_mem", "bam_mem";
interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
#address-cells = <0>;
interrupt-parent = <&blsp2_uart1>;
interrupts = <0 1 2>;
#interrupt-cells = <1>;
interrupt-map-mask = <0xffffffff>;
interrupt-map = <0 &intc 0 306 0
1 &intc 0 239 0
2 &tlmm 17 0>;
qcom,inject-rx-on-wakeup;
qcom,rx-char-to-inject = <0xfd>;
qcom,bam-tx-ep-pipe-index = <0>;
qcom,bam-rx-ep-pipe-index = <1>;
qcom,master-id = <84>;
clock-names = "core_clk", "iface_clk";
clocks = <&clock_gcc clk_gcc_blsp2_uart1_apps_clk>,
<&clock_gcc clk_gcc_blsp2_ahb_clk>;
pinctrl-names = "sleep", "default";
pinctrl-0 = <&blsp2_uart1_sleep>;
pinctrl-1 = <&blsp2_uart1_active>;
qcom,msm-bus,name = "blsp2_uart1";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<84 512 0 0>,
<84 512 500 800>;
status = "disabled";
};
dcc: dcc@b3000 {
compatible = "qcom,dcc";
reg = <0xb3000 0x1000>,
<0xb4000 0x2000>;
reg-names = "dcc-base", "dcc-ram-base";
clocks = <&clock_gcc clk_gcc_dcc_clk>;
clock-names = "dcc_clk";
qcom,save-reg;
};
qcom,ipc-spinlock@1905000 {
compatible = "qcom,ipc-spinlock-sfpb";
reg = <0x1905000 0x8000>;
qcom,num-locks = <8>;
};
qcom,smem@86300000 {
compatible = "qcom,smem";
reg = <0x86300000 0x100000>,
<0xb011008 0x4>,
<0x60000 0x8000>,
<0x193d000 0x8>;
reg-names = "smem", "irq-reg-base", "aux-mem1",
"smem_targ_info_reg";
qcom,mpu-enabled;
qcom,smd-modem {
compatible = "qcom,smd";
qcom,smd-edge = <0>;
qcom,smd-irq-offset = <0x0>;
qcom,smd-irq-bitmask = <0x1000>;
interrupts = <0 25 1>;
label = "modem";
qcom,not-loadable;
};
qcom,smsm-modem {
compatible = "qcom,smsm";
qcom,smsm-edge = <0>;
qcom,smsm-irq-offset = <0x0>;
qcom,smsm-irq-bitmask = <0x2000>;
interrupts = <0 26 1>;
};
qcom,smd-wcnss {
compatible = "qcom,smd";
qcom,smd-edge = <6>;
qcom,smd-irq-offset = <0x0>;
qcom,smd-irq-bitmask = <0x20000>;