From ff6fab64f4f4e3b667bc6e6342781b95ea1f828f Mon Sep 17 00:00:00 2001
From: GthiN <90790575+GthiN89@users.noreply.github.com>
Date: Sat, 13 Jul 2024 08:09:10 +0200
Subject: [PATCH] score counter
---
.gitignore | 11 +
Nanoid20K.gprj.user | 2 +-
impl/gwsynthesis/Nanoid20K.log | 27 +-
impl/gwsynthesis/Nanoid20K.vg | 12855 ++++++++++-------
impl/gwsynthesis/Nanoid20K_syn.rpt.html | 410 +-
impl/gwsynthesis/Nanoid20K_syn_resource.html | 10 +-
impl/gwsynthesis/Nanoid20K_syn_rsc.xml | 6 +-
impl/pnr/Nanoid20K.db | Bin 25960 -> 34080 bytes
impl/pnr/Nanoid20K.log | 2 +-
impl/pnr/Nanoid20K.pin.html | 2 +-
impl/pnr/Nanoid20K.power.html | 48 +-
impl/pnr/Nanoid20K.rpt.html | 32 +-
impl/pnr/Nanoid20K.rpt.txt | 28 +-
impl/pnr/Nanoid20K.timing_paths | 1303 +-
impl/pnr/Nanoid20K_tr_content.html | 7572 +++++-----
impl/pnr/ao_0.bin | Bin 907418 -> 907418 bytes
impl/pnr/ao_0.binx | Bin 907956 -> 907956 bytes
impl/pnr/ao_0.fs | 942 +-
src/game_loop.v | 264 +
19 files changed, 13881 insertions(+), 9633 deletions(-)
create mode 100644 .gitignore
diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..31e0c13
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,11 @@
+
+img/Pictures/Camera Roll/desktop.ini
+img/Pictures/desktop.ini
+img/Pictures/IMG_20240711_161743_991.jpg
+img/Pictures/New folder/1.PNG
+img/Pictures/New folder/2.PNG
+img/Pictures/New folder/3.PNG
+img/Pictures/New folder/4.PNG
+img/Pictures/New folder/5.PNG
+img/Pictures/Saved Pictures/desktop.ini
+img/Pictures/SnĂmek obrazovky 2024-07-01 081158.png
diff --git a/Nanoid20K.gprj.user b/Nanoid20K.gprj.user
index 15ef245..a37023c 100644
--- a/Nanoid20K.gprj.user
+++ b/Nanoid20K.gprj.user
@@ -20,5 +20,5 @@
- 000000ff00000001fd0000000200000000000001000000029ffc0200000001fc000000370000029f0000009301000016fa000000020200000004fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000006200fffffffb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000005e00fffffffb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000007c00fffffffb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff000000000000000000000003000007800000010bfc0100000001fc0000000000000780000000a100fffffffa000000000100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000005100fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff000000a100ffffff0000067c0000029f00000004000000040000000800000008fc000000010000000200000004000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e00450064006900740100000099ffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c00730100000153ffffffff0000000000000000ffffffff0100000201ffffffff0000000000000000
+ 000000ff00000001fd0000000200000000000001000000029ffc0200000001fc000000370000029f0000009301000016fa000000010200000004fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000006200fffffffb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000005e00fffffffb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000007c00fffffffb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff000000000000000000000003000007800000010bfc0100000001fc0000000000000780000000a100fffffffa000000000100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000005100fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff000000a100ffffff0000067c0000029f00000004000000040000000800000008fc000000010000000200000004000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e00450064006900740100000099ffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c00730100000153ffffffff0000000000000000ffffffff0100000201ffffffff0000000000000000
diff --git a/impl/gwsynthesis/Nanoid20K.log b/impl/gwsynthesis/Nanoid20K.log
index 5347cad..39731c6 100644
--- a/impl/gwsynthesis/Nanoid20K.log
+++ b/impl/gwsynthesis/Nanoid20K.log
@@ -6,14 +6,18 @@ Analyzing Verilog file 'C:\Users\Petr\Documents\FPGA\Graphic 2\framebuffer\1\Nan
Analyzing Verilog file 'C:\Users\Petr\Documents\FPGA\Graphic 2\framebuffer\1\Nanoid20K\src\game_top.v'
Undeclared symbol 'PLL_CLKFX', assumed default net type 'wire'("C:\Users\Petr\Documents\FPGA\Graphic 2\framebuffer\1\Nanoid20K\src\game_top.v":63)
Analyzing Verilog file 'C:\Users\Petr\Documents\FPGA\Graphic 2\framebuffer\1\Nanoid20K\src\game_loop.v'
-WARN (EX2987) : Variable 'bx_min' must explicitly be declared as automatic or static("C:\Users\Petr\Documents\FPGA\Graphic 2\framebuffer\1\Nanoid20K\src\game_loop.v":118)
-WARN (EX2987) : Variable 'bx_max' must explicitly be declared as automatic or static("C:\Users\Petr\Documents\FPGA\Graphic 2\framebuffer\1\Nanoid20K\src\game_loop.v":119)
-WARN (EX2987) : Variable 'by_min' must explicitly be declared as automatic or static("C:\Users\Petr\Documents\FPGA\Graphic 2\framebuffer\1\Nanoid20K\src\game_loop.v":120)
-WARN (EX2987) : Variable 'by_max' must explicitly be declared as automatic or static("C:\Users\Petr\Documents\FPGA\Graphic 2\framebuffer\1\Nanoid20K\src\game_loop.v":121)
-WARN (EX2987) : Variable 'bx_min' must explicitly be declared as automatic or static("C:\Users\Petr\Documents\FPGA\Graphic 2\framebuffer\1\Nanoid20K\src\game_loop.v":149)
-WARN (EX2987) : Variable 'bx_max' must explicitly be declared as automatic or static("C:\Users\Petr\Documents\FPGA\Graphic 2\framebuffer\1\Nanoid20K\src\game_loop.v":150)
-WARN (EX2987) : Variable 'by_min' must explicitly be declared as automatic or static("C:\Users\Petr\Documents\FPGA\Graphic 2\framebuffer\1\Nanoid20K\src\game_loop.v":151)
-WARN (EX2987) : Variable 'by_max' must explicitly be declared as automatic or static("C:\Users\Petr\Documents\FPGA\Graphic 2\framebuffer\1\Nanoid20K\src\game_loop.v":152)
+WARN (EX2987) : Variable 'bx_min' must explicitly be declared as automatic or static("C:\Users\Petr\Documents\FPGA\Graphic 2\framebuffer\1\Nanoid20K\src\game_loop.v":125)
+WARN (EX2987) : Variable 'bx_max' must explicitly be declared as automatic or static("C:\Users\Petr\Documents\FPGA\Graphic 2\framebuffer\1\Nanoid20K\src\game_loop.v":126)
+WARN (EX2987) : Variable 'by_min' must explicitly be declared as automatic or static("C:\Users\Petr\Documents\FPGA\Graphic 2\framebuffer\1\Nanoid20K\src\game_loop.v":127)
+WARN (EX2987) : Variable 'by_max' must explicitly be declared as automatic or static("C:\Users\Petr\Documents\FPGA\Graphic 2\framebuffer\1\Nanoid20K\src\game_loop.v":128)
+WARN (EX2987) : Variable 'bx_min' must explicitly be declared as automatic or static("C:\Users\Petr\Documents\FPGA\Graphic 2\framebuffer\1\Nanoid20K\src\game_loop.v":157)
+WARN (EX2987) : Variable 'bx_max' must explicitly be declared as automatic or static("C:\Users\Petr\Documents\FPGA\Graphic 2\framebuffer\1\Nanoid20K\src\game_loop.v":158)
+WARN (EX2987) : Variable 'by_min' must explicitly be declared as automatic or static("C:\Users\Petr\Documents\FPGA\Graphic 2\framebuffer\1\Nanoid20K\src\game_loop.v":159)
+WARN (EX2987) : Variable 'by_max' must explicitly be declared as automatic or static("C:\Users\Petr\Documents\FPGA\Graphic 2\framebuffer\1\Nanoid20K\src\game_loop.v":160)
+WARN (EX2987) : Variable 'scaled_sx' must explicitly be declared as automatic or static("C:\Users\Petr\Documents\FPGA\Graphic 2\framebuffer\1\Nanoid20K\src\game_loop.v":405)
+WARN (EX2987) : Variable 'scaled_sy' must explicitly be declared as automatic or static("C:\Users\Petr\Documents\FPGA\Graphic 2\framebuffer\1\Nanoid20K\src\game_loop.v":406)
+WARN (EX2987) : Variable 'scaled_sx' must explicitly be declared as automatic or static("C:\Users\Petr\Documents\FPGA\Graphic 2\framebuffer\1\Nanoid20K\src\game_loop.v":412)
+WARN (EX2987) : Variable 'scaled_sy' must explicitly be declared as automatic or static("C:\Users\Petr\Documents\FPGA\Graphic 2\framebuffer\1\Nanoid20K\src\game_loop.v":413)
Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9_x64\IDE\data\ipcores\GAO_LITE\GW_AO_0\gw_ao_mem_ctrl.v'
Analyzing included file 'C:\Users\Petr\Documents\FPGA\Graphic 2\framebuffer\1\Nanoid20K\impl\gwsynthesis\RTL_GAO\ao_0\gw_ao_top_define.v'("C:\Gowin\Gowin_V1.9.9_x64\IDE\data\ipcores\GAO_LITE\GW_AO_0\gw_ao_mem_ctrl.v":133)
Back to file 'C:\Gowin\Gowin_V1.9.9_x64\IDE\data\ipcores\GAO_LITE\GW_AO_0\gw_ao_mem_ctrl.v'("C:\Gowin\Gowin_V1.9.9_x64\IDE\data\ipcores\GAO_LITE\GW_AO_0\gw_ao_mem_ctrl.v":133)
@@ -39,9 +43,10 @@ WARN (EX3791) : Expression size 32 truncated to fit in target size 16("C:\Users
WARN (EX3670) : Actual bit length 10 differs from formal bit length 16 for port 'sx'("C:\Users\Petr\Documents\FPGA\Graphic 2\framebuffer\1\Nanoid20K\src\game_top.v":27)
WARN (EX3670) : Actual bit length 10 differs from formal bit length 16 for port 'sy'("C:\Users\Petr\Documents\FPGA\Graphic 2\framebuffer\1\Nanoid20K\src\game_top.v":28)
Compiling module 'game_loop'("C:\Users\Petr\Documents\FPGA\Graphic 2\framebuffer\1\Nanoid20K\src\game_loop.v":1)
-WARN (EX3780) : Using initial value of 'qs' since it is never assigned("C:\Users\Petr\Documents\FPGA\Graphic 2\framebuffer\1\Nanoid20K\src\game_loop.v":41)
-WARN (EX3780) : Using initial value of 'qy' since it is never assigned("C:\Users\Petr\Documents\FPGA\Graphic 2\framebuffer\1\Nanoid20K\src\game_loop.v":55)
-WARN (EX3791) : Expression size 2 truncated to fit in target size 1("C:\Users\Petr\Documents\FPGA\Graphic 2\framebuffer\1\Nanoid20K\src\game_loop.v":16)
+WARN (EX3780) : Using initial value of 'qs' since it is never assigned("C:\Users\Petr\Documents\FPGA\Graphic 2\framebuffer\1\Nanoid20K\src\game_loop.v":45)
+WARN (EX3780) : Using initial value of 'qy' since it is never assigned("C:\Users\Petr\Documents\FPGA\Graphic 2\framebuffer\1\Nanoid20K\src\game_loop.v":62)
+WARN (EX3791) : Expression size 2 truncated to fit in target size 1("C:\Users\Petr\Documents\FPGA\Graphic 2\framebuffer\1\Nanoid20K\src\game_loop.v":20)
+WARN (EX3791) : Expression size 9 truncated to fit in target size 8("C:\Users\Petr\Documents\FPGA\Graphic 2\framebuffer\1\Nanoid20K\src\game_loop.v":132)
Compiling module 'DVI_TX_Top'("C:\Users\Petr\Documents\FPGA\Graphic 2\framebuffer\1\Nanoid20K\src\dvi_tx\dvi_tx.v":1044)
Compiling module '**'("C:\Users\Petr\Documents\FPGA\Graphic 2\framebuffer\1\Nanoid20K\src\dvi_tx\dvi_tx.v":0)
Compiling module '**'("C:\Users\Petr\Documents\FPGA\Graphic 2\framebuffer\1\Nanoid20K\src\dvi_tx\dvi_tx.v":0)
diff --git a/impl/gwsynthesis/Nanoid20K.vg b/impl/gwsynthesis/Nanoid20K.vg
index 374e080..7b0f788 100644
--- a/impl/gwsynthesis/Nanoid20K.vg
+++ b/impl/gwsynthesis/Nanoid20K.vg
@@ -1,7 +1,7 @@
//
//Written by GowinSynthesis
//Tool Version "V1.9.9 (64-bit)"
-//Sat Jul 13 06:44:52 2024
+//Sat Jul 13 08:05:23 2024
//Source file index table:
//file0 "\C:/Users/Petr/Documents/FPGA/Graphic\ 2/framebuffer/1/Nanoid20K/src/display480p.v"
@@ -25,74 +25,77 @@
`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
`pragma protect key_block
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+GCRVSHSArIpkt/UgvRUzYBTZBpbDwwDoNGwW/w==
-`pragma protect encoding=(enctype="base64", line_length=76, bytes=3216)
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=3408)
`pragma protect data_keyowner="default-ip-vendor"
`pragma protect data_keyname="default-ip-key"
`pragma protect data_method="aes128-cfb"
`pragma protect data_block
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`pragma protect end_protected
`pragma protect begin_protected
`pragma protect version="2.3"
@@ -104,1406 +107,1386 @@ Izv0fif9cqiHcHjaKDl5JGrecnTTIU4a
`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
`pragma protect key_block
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+8WyLW/TJ8HlogMv8R98f3IvLz5Nd8F05Yl6iMg==
-`pragma protect encoding=(enctype="base64", line_length=76, bytes=79168)
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=77984)
`pragma protect data_keyowner="default-ip-vendor"
`pragma protect data_keyname="default-ip-key"
`pragma protect data_method="aes128-cfb"
`pragma protect data_block
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+NphHfyOAV+OYCUJw4xsyi5R6hiDq0jnomsuFeuN4Ife3K+bUl545LOexQqjKRacif/iTWeWONu2z
+QG7YG/4Mkm1gzs31ABfIF39teyI299Rsjj/0h4vrnZCGgF8g5kGs2k47ZkZYkVL1W4VOAIVwq0RD
+OxBKDx6YOJJ6iuas8psYWIltdwioPsDaX3n+4N42XLO2YLlVjLxFtzRcTm6FCRTKwvj3vMtjl/Ti
+JdRwY9b0/x3/mCCex+auw0mJ7uWaUT8MGGdK0g1Kzf6JcatCC5yxe9OI6L/3WY2lHIr1HThenn4E
+lohkgetLm7t83Jyvh9Zyc7iqFCXfys4vytWrat8xgiaCR56ZORzI/8AtTXGKEPVAVtAk7cL9aSZD
+YocCGRnyEU/dG8CIqxptnXLptwT0H+LWVnP8dX6hMC9BvTDzlxbC7LbQC9J1Lj7ZnT/GrcxJ2v7r
+C4wlkPUFGWXBx63wuCM/dXEhga8X6VibcfyJ1GLplJZkfJgjN3yT/hNQ4RjQ7Qzm8RdC953lwYto
+rE9838zlZuCsyp1LOo+1Q1waS4pFk++Bi1qb1WKKrJy+3tSoSTMaWnJzpduaFEapTEHXPNHk9g22
+Sjyx4oHL7dkl2BDXH5vpzu46GxrwiRWxyLG905mZ7VIb0EqA1SofQiy+hil6Ru08r+h8OGfL7jQD
+XHBirEDZ/LCqfdaUF2UdIdi04S+BjhrwZwIH7Q3yhtWV7oTTPhvu2Ow1SFWsQn9468VOcXo3PNdC
+856kHgciccU=
`pragma protect end_protected
module gw_gao (
tms_pad_i,
@@ -1538,9 +1521,10 @@ wire shift_dr_capture_dr;
wire pause_dr;
wire enable_er1;
wire enable_er2;
+wire n33_5;
wire n33_6;
wire n12_6;
-wire n639_5;
+wire n639_7;
wire [5:0] control0;
wire [4:2] control0_0;
wire [3:0] module_id_reg;
@@ -1568,7 +1552,7 @@ wire GND;
.tck_pad_i(tck_i_c),
.tms_pad_i(tms_i_c),
.tdi_pad_i(tdi_i_c),
- .tdo_er1_i(n639_5),
+ .tdo_er1_i(n639_7),
.tdo_er2_i(GND),
.tdo_pad_o(tdo_o_c),
.tck_o(control0[0]),
@@ -1590,6 +1574,7 @@ wire GND;
.control0_0(control0[0]),
.control0_5(control0[5]),
.module_state(module_state[2:0]),
+ .n33_5(n33_5),
.n33_6(n33_6),
.n12_6(n12_6),
.control0_2(control0_0[2]),
@@ -1601,6 +1586,7 @@ wire GND;
.clk_d(clk_d),
.shift_dr_capture_dr(shift_dr_capture_dr),
.n33_6(n33_6),
+ .n33_5(n33_5),
.de_Z(de_Z),
.control0_2(control0_0[2]),
.control0_4(control0_0[4]),
@@ -1610,7 +1596,7 @@ wire GND;
.blue_Z(blue_Z[7]),
.green_Z(green_Z[7]),
.red_Z(red_Z[7]),
- .n639_5(n639_5),
+ .n639_7(n639_7),
.module_state(module_state[2:0])
);
VCC VCC_cZ (
@@ -1644,6 +1630,7 @@ wire n13_4;
wire frame_4;
wire n132_4;
wire n45_14;
+wire n45_15;
wire n73_8;
wire n73_9;
wire n73_10;
@@ -1651,17 +1638,17 @@ wire n73_11;
wire n14_5;
wire n14_6;
wire n13_5;
-wire n13_6;
wire frame_5;
wire n132_5;
wire n132_6;
-wire n45_15;
+wire n45_16;
+wire n45_17;
+wire n45_18;
wire n14_7;
-wire n14_8;
-wire n14_9;
-wire n13_7;
-wire n13_8;
wire n132_7;
+wire n132_8;
+wire n132_9;
+wire n14_8;
wire n114_2;
wire n114_3;
wire n113_2;
@@ -1729,13 +1716,14 @@ wire [15:0] x;
wire [15:0] y;
wire VCC;
wire GND;
- LUT3 n45_s10 (
+ LUT4 n45_s10 (
.F(n45_13),
- .I0(x[2]),
- .I1(x[3]),
- .I2(n45_14)
+ .I0(x[4]),
+ .I1(n45_14),
+ .I2(x[5]),
+ .I3(n45_15)
);
-defparam n45_s10.INIT=8'h10;
+defparam n45_s10.INIT=16'h4000;
LUT4 n73_s4 (
.F(n73_7),
.I0(n73_8),
@@ -1755,80 +1743,84 @@ defparam n14_s1.INIT=16'h7FFF;
LUT2 n13_s1 (
.F(n13_4),
.I0(n13_5),
- .I1(n13_6)
+ .I1(n45_15)
);
defparam n13_s1.INIT=4'hB;
LUT4 frame_s2 (
.F(frame_4),
- .I0(y[2]),
- .I1(y[3]),
- .I2(n14_6),
- .I3(frame_5)
+ .I0(frame_5),
+ .I1(y[0]),
+ .I2(y[1]),
+ .I3(n14_6)
);
-defparam frame_s2.INIT=16'hEFFF;
+defparam frame_s2.INIT=16'h7FFF;
LUT4 n132_s1 (
.F(n132_4),
- .I0(y[9]),
- .I1(y[8]),
- .I2(n132_5),
+ .I0(n132_5),
+ .I1(y[0]),
+ .I2(n73_7),
.I3(n132_6)
);
-defparam n132_s1.INIT=16'h4000;
- LUT4 n45_s11 (
+defparam n132_s1.INIT=16'h8000;
+ LUT3 n45_s11 (
.F(n45_14),
- .I0(x[0]),
- .I1(x[1]),
- .I2(n45_15),
- .I3(n13_6)
+ .I0(x[7]),
+ .I1(x[6]),
+ .I2(n45_16)
+);
+defparam n45_s11.INIT=8'h40;
+ LUT4 n45_s12 (
+ .F(n45_15),
+ .I0(n45_17),
+ .I1(x[12]),
+ .I2(x[13]),
+ .I3(n45_18)
);
-defparam n45_s11.INIT=16'h1000;
+defparam n45_s12.INIT=16'h8000;
LUT4 n73_s5 (
.F(n73_8),
- .I0(x[12]),
- .I1(x[13]),
- .I2(x[14]),
- .I3(x[15])
+ .I0(x[8]),
+ .I1(x[10]),
+ .I2(x[11]),
+ .I3(x[9])
);
-defparam n73_s5.INIT=16'h0001;
+defparam n73_s5.INIT=16'h0100;
LUT4 n73_s6 (
.F(n73_9),
- .I0(x[0]),
- .I1(x[1]),
- .I2(x[2]),
- .I3(x[3])
-);
-defparam n73_s6.INIT=16'h8000;
- LUT4 n73_s7 (
- .F(n73_10),
.I0(x[7]),
.I1(x[5]),
.I2(x[6]),
.I3(x[4])
);
-defparam n73_s7.INIT=16'h4000;
+defparam n73_s6.INIT=16'h4000;
+ LUT4 n73_s7 (
+ .F(n73_10),
+ .I0(x[12]),
+ .I1(x[13]),
+ .I2(x[14]),
+ .I3(x[15])
+);
+defparam n73_s7.INIT=16'h0001;
LUT4 n73_s8 (
.F(n73_11),
- .I0(x[8]),
- .I1(x[10]),
- .I2(x[11]),
- .I3(x[9])
+ .I0(x[0]),
+ .I1(x[1]),
+ .I2(x[2]),
+ .I3(x[3])
);
-defparam n73_s8.INIT=16'h0100;
- LUT3 n14_s2 (
+defparam n73_s8.INIT=16'h8000;
+ LUT2 n14_s2 (
.F(n14_5),
.I0(y[0]),
- .I1(y[1]),
- .I2(n14_7)
+ .I1(y[1])
);
-defparam n14_s2.INIT=8'h60;
- LUT4 n14_s3 (
+defparam n14_s2.INIT=4'h6;
+ LUT2 n14_s3 (
.F(n14_6),
- .I0(n14_8),
- .I1(y[12]),
- .I2(y[13]),
- .I3(n14_9)
+ .I0(n132_6),
+ .I1(n14_7)
);
-defparam n14_s3.INIT=16'h8000;
+defparam n14_s3.INIT=4'h8;
LUT4 n13_s2 (
.F(n13_5),
.I0(x[6]),
@@ -1837,88 +1829,88 @@ defparam n14_s3.INIT=16'h8000;
.I3(x[7])
);
defparam n13_s2.INIT=16'hA87F;
- LUT4 n13_s3 (
- .F(n13_6),
- .I0(n13_7),
- .I1(x[12]),
- .I2(x[13]),
- .I3(n13_8)
-);
-defparam n13_s3.INIT=16'h8000;
- LUT3 frame_s3 (
+ LUT2 frame_s3 (
.F(frame_5),
- .I0(y[0]),
- .I1(y[1]),
- .I2(n14_7)
+ .I0(y[2]),
+ .I1(y[3])
);
-defparam frame_s3.INIT=8'h80;
- LUT3 n132_s2 (
+defparam frame_s3.INIT=4'h1;
+ LUT4 n132_s2 (
.F(n132_5),
- .I0(y[10]),
- .I1(y[11]),
- .I2(n73_7)
+ .I0(y[15]),
+ .I1(y[1]),
+ .I2(n132_7),
+ .I3(n132_8)
);
-defparam n132_s2.INIT=8'h10;
+defparam n132_s2.INIT=16'h4000;
LUT4 n132_s3 (
.F(n132_6),
- .I0(n132_7),
- .I1(y[2]),
- .I2(y[3]),
- .I3(frame_5)
-);
-defparam n132_s3.INIT=16'h8000;
- LUT4 n45_s12 (
- .F(n45_15),
- .I0(x[4]),
- .I1(x[7]),
- .I2(x[6]),
- .I3(x[5])
-);
-defparam n45_s12.INIT=16'h1000;
- LUT4 n14_s4 (
- .F(n14_7),
.I0(y[5]),
.I1(y[4]),
- .I2(y[6]),
- .I3(y[7])
+ .I2(n132_9),
+ .I3(y[6])
);
-defparam n14_s4.INIT=16'h4000;
- LUT2 n14_s5 (
- .F(n14_8),
- .I0(y[14]),
- .I1(y[15])
-);
-defparam n14_s5.INIT=4'h8;
- LUT4 n14_s6 (
- .F(n14_9),
- .I0(y[8]),
- .I1(y[9]),
- .I2(y[10]),
- .I3(y[11])
+defparam n132_s3.INIT=16'h4000;
+ LUT4 n45_s13 (
+ .F(n45_16),
+ .I0(x[0]),
+ .I1(x[1]),
+ .I2(x[2]),
+ .I3(x[3])
);
-defparam n14_s6.INIT=16'h8000;
- LUT2 n13_s4 (
- .F(n13_7),
+defparam n45_s13.INIT=16'h0001;
+ LUT2 n45_s14 (
+ .F(n45_17),
.I0(x[14]),
.I1(x[15])
);
-defparam n13_s4.INIT=4'h8;
- LUT4 n13_s5 (
- .F(n13_8),
+defparam n45_s14.INIT=4'h8;
+ LUT4 n45_s15 (
+ .F(n45_18),
.I0(x[8]),
.I1(x[9]),
.I2(x[10]),
.I3(x[11])
);
-defparam n13_s5.INIT=16'h8000;
+defparam n45_s15.INIT=16'h8000;
+ LUT4 n14_s4 (
+ .F(n14_7),
+ .I0(n14_8),
+ .I1(y[9]),
+ .I2(y[10]),
+ .I3(y[11])
+);
+defparam n14_s4.INIT=16'h8000;
LUT4 n132_s4 (
.F(n132_7),
+ .I0(y[11]),
+ .I1(y[12]),
+ .I2(y[13]),
+ .I3(y[14])
+);
+defparam n132_s4.INIT=16'h0001;
+ LUT4 n132_s5 (
+ .F(n132_8),
+ .I0(y[9]),
+ .I1(y[10]),
+ .I2(y[2]),
+ .I3(y[3])
+);
+defparam n132_s5.INIT=16'h1000;
+ LUT2 n132_s6 (
+ .F(n132_9),
+ .I0(y[7]),
+ .I1(y[8])
+);
+defparam n132_s6.INIT=4'h8;
+ LUT4 n14_s5 (
+ .F(n14_8),
.I0(y[12]),
.I1(y[13]),
.I2(y[14]),
.I3(y[15])
);
-defparam n132_s4.INIT=16'h0001;
+defparam n14_s5.INIT=16'h8000;
DFF vsync_s0 (
.Q(vsync_Z),
.D(n14_4),
@@ -2540,8 +2532,8 @@ defparam n165_s.ALU_MODE=0;
endmodule /* display_480p */
module game_loop (
clk_d,
- btn2_d,
frame_Z,
+ btn2_d,
btn1_d,
sx_Z,
sy_Z,
@@ -2551,14 +2543,34 @@ module game_loop (
)
;
input clk_d;
-input btn2_d;
input frame_Z;
+input btn2_d;
input btn1_d;
input [9:0] sx_Z;
input [9:0] sy_Z;
output [7:7] red_Z;
output [7:7] green_Z;
output [7:7] blue_Z;
+wire n7273_13;
+wire n7273_14;
+wire n7274_13;
+wire n7274_14;
+wire n7275_13;
+wire n7275_14;
+wire n7276_10;
+wire n7276_11;
+wire n7278_13;
+wire n7278_14;
+wire n7422_13;
+wire n7422_14;
+wire n7423_13;
+wire n7423_14;
+wire n7424_13;
+wire n7424_14;
+wire n7425_10;
+wire n7425_11;
+wire n7427_13;
+wire n7427_14;
wire n48_3;
wire n187_3;
wire n190_3;
@@ -2568,372 +2580,668 @@ wire n315_4;
wire n316_4;
wire n317_5;
wire n319_4;
-wire n3294_6;
-wire n9048_3;
-wire n9049_3;
-wire n9050_3;
-wire n9052_3;
-wire n9053_3;
-wire n9054_3;
-wire n9055_3;
-wire n9056_3;
-wire n9059_3;
-wire n9060_3;
-wire n9061_3;
-wire n9062_3;
-wire n9064_3;
-wire n9065_3;
-wire n11097_3;
-wire n11074_3;
+wire n3744_6;
+wire n3735_3;
+wire n3737_3;
+wire n3738_3;
+wire n3739_3;
+wire n3741_3;
+wire n10654_3;
+wire n10655_3;
+wire n10656_3;
+wire n10658_3;
+wire n10659_3;
+wire n10660_3;
+wire n10661_3;
+wire n10662_3;
+wire n10664_3;
+wire n10665_3;
+wire n10666_3;
+wire n10667_3;
+wire n10668_3;
+wire n10669_3;
+wire n10670_3;
+wire n10671_3;
+wire n12765_3;
+wire n6878_4;
+wire n6880_4;
+wire n6885_4;
+wire n6888_5;
+wire n6895_6;
+wire n6911_3;
+wire n6919_3;
+wire n6925_3;
+wire n6937_3;
+wire n6939_3;
+wire n6941_3;
+wire n6948_3;
+wire n6950_3;
+wire n6954_3;
+wire n7059_6;
+wire n7061_6;
+wire n7066_6;
+wire n7069_5;
+wire n7076_4;
+wire n7106_3;
+wire n7110_3;
+wire n7118_3;
+wire n7120_3;
+wire n7122_3;
+wire n7129_3;
+wire n7131_3;
+wire n7135_3;
+wire n12742_3;
+wire n7052;
+wire n7053;
+wire n7054;
+wire n7055;
+wire n7056;
+wire n6906_5;
+wire n6909_5;
+wire n6944_5;
+wire n6946_5;
+wire n6952_5;
+wire n6958_5;
+wire n6964_5;
+wire n6972_5;
+wire n7087_5;
+wire n7125_5;
+wire n7127_5;
+wire n7133_5;
+wire n7139_5;
+wire n7141_5;
+wire n7273_17;
+wire n7274_17;
+wire n7278_17;
+wire n7422_17;
+wire n7423_17;
+wire n7427_17;
wire qxb_9_6;
wire square_6;
wire ball_6;
+wire score_area_2_6;
wire qx_9_6;
wire qyb_6_5;
-wire n3741_33;
+wire n4207_33;
+wire n6847;
+wire n7272_106;
+wire n7421_101;
wire qdy_7;
-wire n3710_46;
-wire n367_8;
+wire n4176_46;
wire n366_7;
wire n365_7;
wire n364_7;
wire n362_7;
wire n358_8;
-wire n3881_5;
+wire n7427_19;
+wire n7423_19;
+wire n7422_19;
+wire n7278_19;
+wire n7274_19;
+wire n7273_19;
+wire n7585_5;
+wire n4347_5;
wire n161_6;
wire n160_6;
wire n159_6;
-wire n155_6;
-wire n154_6;
+wire n155_19;
+wire n154_8;
+wire n6843;
+wire n7569_5;
+wire n7553_5;
+wire n6846;
+wire n6845;
wire n48_4;
wire n48_5;
wire n187_4;
wire n187_5;
wire n190_4;
-wire n190_5;
wire n190_6;
wire n191_4;
wire n191_5;
wire n192_4;
wire n192_5;
wire n315_5;
+wire n315_6;
wire n316_5;
wire n316_6;
-wire n316_7;
wire n317_6;
+wire n317_7;
wire n317_8;
-wire n319_5;
+wire n317_9;
wire n319_6;
-wire n3294_7;
-wire n3294_8;
-wire n3294_9;
-wire n9048_4;
-wire n9048_5;
-wire n9049_4;
-wire n9049_5;
-wire n9050_4;
-wire n9051_4;
-wire n9053_4;
-wire n9054_4;
-wire n9055_4;
-wire n9056_4;
-wire n9057_4;
-wire n9059_4;
-wire n9060_4;
-wire n9061_4;
-wire n9064_4;
-wire n9065_4;
-wire n11097_4;
-wire n11097_5;
-wire n11097_6;
-wire n11097_7;
-wire qxb_9_7;
+wire n319_7;
+wire n3744_7;
+wire n3744_8;
+wire n3744_9;
+wire n3735_4;
+wire n3735_5;
+wire n3735_6;
+wire n3735_7;
+wire n3737_4;
+wire n3737_6;
+wire n3737_7;
+wire n3738_4;
+wire n3739_4;
+wire n3739_6;
+wire n3739_7;
+wire n3741_4;
+wire n3741_5;
+wire n3741_6;
+wire n10654_4;
+wire n10657_4;
+wire n10658_4;
+wire n10659_4;
+wire n10660_4;
+wire n10661_4;
+wire n10662_4;
+wire n10663_4;
+wire n10665_4;
+wire n10666_4;
+wire n10667_4;
+wire n10667_5;
+wire n10668_4;
+wire n10669_4;
+wire n10670_4;
+wire n10671_4;
+wire n12765_4;
+wire n12765_5;
+wire n12765_6;
+wire n12765_7;
+wire n6878_5;
+wire n6925_4;
+wire n6941_4;
+wire n6948_4;
+wire n6950_4;
+wire n7059_7;
+wire n7076_5;
+wire n7106_4;
+wire n7122_4;
+wire n7129_4;
+wire n7131_4;
+wire n7054_20;
+wire n7054_21;
+wire n7055_29;
+wire n7055_30;
+wire n7055_31;
+wire n7056_32;
+wire n6944_6;
+wire n6952_6;
+wire n6958_6;
+wire n7125_6;
wire square_7;
-wire square_10;
-wire ball_7;
+wire square_8;
+wire square_9;
wire ball_8;
wire ball_9;
+wire score_area_1_7;
+wire score_area_1_8;
wire qx_9_7;
wire qdx_7;
-wire n3741_34;
-wire n3741_35;
-wire qdy_8;
-wire qdy_9;
-wire n3710_47;
+wire qyb_9_7;
+wire n4207_34;
+wire n4207_35;
+wire n4207_36;
+wire n4207_37;
+wire n6847_11;
+wire n7272_108;
+wire n7272_109;
+wire n7421_102;
+wire n4176_47;
wire n367_9;
wire n365_8;
wire n364_8;
wire n362_8;
wire n358_9;
-wire n3881_6;
+wire n4347_6;
wire n160_7;
wire n159_7;
-wire n155_7;
+wire n155_20;
+wire n6843_22;
+wire n6846_12;
+wire n6846_13;
+wire n6846_14;
+wire n6845_12;
wire n187_6;
+wire n187_7;
wire n190_7;
wire n190_8;
wire n190_9;
wire n191_6;
-wire n316_8;
-wire n317_9;
+wire n315_7;
+wire n316_7;
wire n317_10;
-wire n319_7;
-wire n3294_10;
-wire n3294_11;
-wire n3294_12;
-wire n3294_13;
-wire n3294_14;
-wire n3294_15;
-wire n3294_16;
-wire n9048_6;
-wire n9048_7;
-wire n9048_8;
-wire n9049_6;
-wire n9049_7;
-wire n9049_8;
-wire n9049_9;
-wire n9049_10;
-wire n9050_6;
-wire n9050_7;
-wire n9051_5;
-wire n9052_5;
-wire n9053_5;
-wire n9053_6;
-wire n9054_5;
-wire n9054_6;
-wire n9059_5;
-wire n9061_5;
-wire n11097_8;
-wire n11097_9;
-wire n11097_10;
-wire n11097_13;
-wire n11097_14;
-wire n11097_15;
-wire n11097_16;
-wire n11097_17;
-wire n11097_18;
-wire n11097_19;
-wire n11097_20;
+wire n3744_10;
+wire n3744_12;
+wire n3744_13;
+wire n3744_14;
+wire n3744_17;
+wire n3735_8;
+wire n3735_12;
+wire n3735_13;
+wire n3735_14;
+wire n3735_17;
+wire n3735_18;
+wire n3737_10;
+wire n3737_14;
+wire n3737_15;
+wire n3737_16;
+wire n3738_5;
+wire n3738_6;
+wire n3738_7;
+wire n3739_8;
+wire n3739_10;
+wire n3739_12;
+wire n3739_13;
+wire n3739_14;
+wire n3739_15;
+wire n3741_8;
+wire n3741_11;
+wire n3741_12;
+wire n3741_13;
+wire n3741_14;
+wire n10654_5;
+wire n10657_5;
+wire n10658_5;
+wire n10658_6;
+wire n10659_5;
+wire n10660_5;
+wire n10661_6;
+wire n10664_5;
+wire n10667_6;
+wire n10667_7;
+wire n10669_5;
+wire n10669_6;
+wire n10669_7;
+wire n12765_8;
+wire n12765_9;
+wire n12765_10;
+wire n12765_11;
+wire n12765_12;
+wire n12765_13;
+wire n12765_14;
+wire n12765_15;
+wire n12765_16;
+wire n12765_17;
+wire n12765_18;
+wire n12765_19;
+wire n7054_22;
+wire n7055_32;
+wire n7055_33;
+wire n7055_34;
+wire n7056_33;
+wire square_10;
wire square_11;
wire square_12;
wire square_13;
+wire ball_11;
+wire ball_14;
+wire ball_15;
+wire score_area_1_9;
+wire qx_9_8;
+wire qyb_9_8;
+wire n4207_38;
+wire n4207_40;
+wire n7272_110;
+wire n7272_111;
+wire n7272_112;
+wire n7272_113;
+wire n7272_114;
+wire n7421_103;
+wire n7421_104;
+wire n4347_7;
+wire n4347_8;
+wire n4347_9;
+wire n155_21;
+wire n6843_23;
+wire n6843_24;
+wire n6846_15;
+wire n6846_16;
+wire n6846_17;
+wire n6846_18;
+wire n6846_19;
+wire n190_10;
+wire n315_9;
+wire n3744_18;
+wire n3744_19;
+wire n3744_20;
+wire n3744_21;
+wire n3744_22;
+wire n3744_23;
+wire n3744_24;
+wire n3744_25;
+wire n3744_27;
+wire n3735_19;
+wire n3735_20;
+wire n3735_23;
+wire n3735_24;
+wire n3735_26;
+wire n3735_27;
+wire n3735_28;
+wire n3735_31;
+wire n3735_32;
+wire n3737_17;
+wire n3737_18;
+wire n3737_20;
+wire n3737_21;
+wire n3737_22;
+wire n3738_8;
+wire n3739_16;
+wire n3739_17;
+wire n3741_15;
+wire n3741_16;
+wire n3741_17;
+wire n3741_19;
+wire n3741_20;
+wire n3741_21;
+wire n3741_22;
+wire n3741_23;
+wire n10654_7;
+wire n10654_8;
+wire n10658_7;
+wire n10658_8;
+wire n10658_9;
+wire n10659_7;
+wire n10659_8;
+wire n10660_6;
+wire n10660_7;
+wire n10661_7;
+wire n10661_8;
+wire n10669_8;
+wire n10669_9;
+wire n12765_20;
+wire n12765_21;
+wire n12765_22;
+wire n12765_23;
+wire n12765_24;
+wire n12765_25;
+wire n12765_26;
+wire n12765_27;
+wire n7055_35;
+wire n7055_36;
wire square_14;
wire square_15;
wire square_16;
-wire ball_10;
-wire ball_11;
-wire ball_12;
-wire ball_13;
-wire qx_9_8;
-wire n3741_36;
-wire n3741_37;
-wire n3741_38;
-wire n3741_39;
-wire qdy_10;
-wire n3710_48;
-wire n3881_7;
-wire n155_8;
-wire n192_7;
-wire n316_9;
-wire n3294_17;
-wire n3294_18;
-wire n3294_19;
-wire n3294_20;
-wire n3294_22;
-wire n3294_23;
-wire n3294_24;
-wire n3294_25;
-wire n3294_26;
-wire n3294_27;
-wire n3294_28;
-wire n3294_29;
-wire n3294_30;
-wire n3294_31;
-wire n3294_32;
-wire n3294_33;
-wire n3294_34;
-wire n3294_35;
-wire n9048_9;
-wire n9048_10;
-wire n9049_11;
-wire n9050_8;
-wire n9050_9;
-wire n9051_6;
-wire n9052_6;
-wire n9052_7;
-wire n9052_8;
-wire n9053_7;
-wire n9053_8;
-wire n9054_7;
-wire n9054_8;
-wire n9059_6;
-wire n11097_21;
-wire n11097_22;
-wire n11097_23;
-wire n11097_24;
-wire n11097_25;
-wire n11097_26;
-wire n11097_27;
-wire n11097_28;
-wire n11097_29;
-wire n11097_30;
-wire n11097_31;
-wire n11097_32;
-wire n11097_33;
wire square_17;
+wire square_18;
+wire square_19;
wire square_20;
wire square_21;
-wire ball_14;
-wire n3741_41;
-wire n3741_42;
-wire n3741_43;
-wire n3741_45;
-wire n3741_46;
-wire n3881_8;
-wire n3294_36;
-wire n3294_37;
-wire n3294_38;
-wire n3294_40;
-wire n3294_41;
-wire n3294_42;
-wire n3294_44;
-wire n3294_45;
-wire n3294_46;
-wire n3294_47;
-wire n9050_10;
-wire n9051_7;
-wire n9052_9;
-wire n9052_10;
-wire n11097_34;
-wire n11097_35;
-wire n11097_36;
-wire n11097_37;
-wire n11097_38;
-wire n11097_39;
-wire n11097_40;
-wire square_22;
-wire square_23;
-wire ball_15;
wire ball_16;
wire ball_17;
-wire n3741_48;
-wire n3881_9;
-wire n3294_48;
-wire n3294_49;
-wire n3294_50;
-wire n3294_51;
-wire n3294_52;
-wire n11097_41;
-wire n11097_42;
-wire n11097_43;
-wire n11097_44;
-wire n11097_45;
-wire n11097_46;
-wire square_24;
+wire ball_18;
wire ball_19;
-wire ball_20;
-wire n3741_49;
-wire n3294_54;
-wire n3294_55;
-wire n3294_56;
-wire n3294_57;
-wire n11097_47;
-wire square_25;
wire ball_21;
-wire ball_22;
-wire n3741_51;
-wire n3294_60;
-wire n3294_62;
-wire n9052_12;
-wire n9057_6;
-wire square_27;
-wire n11097_49;
-wire n11097_51;
+wire score_area_1_10;
+wire n4207_41;
+wire n4207_42;
+wire n4207_43;
+wire n7272_115;
+wire n7272_116;
+wire n7272_117;
+wire n7272_118;
+wire n7421_105;
+wire n7421_106;
+wire n7421_107;
+wire n7421_108;
+wire n7421_109;
+wire n6843_25;
+wire n6843_26;
+wire n6846_20;
+wire n6846_21;
+wire n6846_22;
+wire n6846_23;
+wire n190_11;
+wire n3744_28;
+wire n3744_30;
+wire n3744_31;
+wire n3744_32;
+wire n3744_33;
+wire n3744_34;
+wire n3744_35;
+wire n3744_36;
+wire n3735_33;
+wire n3735_34;
+wire n3735_35;
+wire n3735_36;
+wire n3735_37;
+wire n3741_24;
+wire n12765_28;
+wire n12765_29;
+wire n12765_30;
+wire n12765_31;
+wire n12765_33;
+wire n12765_34;
+wire n12765_35;
+wire square_22;
+wire square_23;
+wire square_24;
+wire ball_23;
wire ball_24;
-wire n192_9;
-wire square_29;
-wire n9050_12;
-wire n9063_5;
-wire n9051_9;
+wire ball_25;
+wire n4207_49;
+wire n4207_50;
+wire n4207_51;
+wire n4207_54;
+wire n7272_119;
+wire n7272_120;
+wire n7421_110;
+wire n7421_111;
+wire n7421_112;
+wire n7421_113;
+wire n6846_24;
+wire n3744_37;
+wire n3744_38;
+wire n3744_39;
+wire n3744_40;
+wire n3744_42;
+wire n3744_43;
+wire n3744_44;
+wire n3744_45;
+wire n3744_46;
+wire n3744_47;
+wire n3735_38;
+wire n12765_38;
+wire n12765_39;
+wire n12765_40;
+wire n12765_41;
+wire square_27;
+wire square_28;
+wire square_30;
+wire ball_26;
+wire ball_27;
+wire n4207_55;
+wire n4207_56;
+wire n4207_57;
+wire n4207_58;
+wire n4207_59;
+wire n3744_48;
+wire n3744_49;
+wire n3744_51;
+wire n3744_52;
+wire n12765_42;
+wire n12765_43;
wire square_31;
-wire n3294_64;
+wire square_32;
wire square_33;
-wire n9058_5;
-wire n3741_53;
-wire n3741_55;
-wire n3741_57;
-wire n3741_59;
-wire n315_8;
-wire n317_12;
+wire square_34;
+wire ball_30;
+wire n4207_60;
+wire n4207_61;
+wire n4207_62;
+wire n3744_53;
+wire n3744_54;
+wire square_35;
+wire square_36;
+wire square_37;
+wire ball_31;
+wire ball_32;
+wire n4207_63;
+wire n4207_64;
+wire n4207_65;
+wire n3744_55;
+wire n3744_56;
+wire ball_33;
+wire ball_35;
+wire n3735_40;
+wire n3744_58;
+wire n3736_5;
+wire n3735_42;
+wire n3739_20;
+wire n10654_10;
+wire n3741_26;
+wire n3738_11;
+wire n4207_68;
+wire n6927_5;
+wire n6960_7;
+wire n7108_5;
+wire n3744_60;
+wire n10661_10;
+wire n10663_6;
+wire n10664_7;
+wire n155_24;
+wire n4207_70;
+wire n3744_62;
+wire n3735_44;
+wire n3737_24;
+wire n3735_46;
+wire n3741_28;
+wire n3735_48;
+wire n317_13;
+wire n315_11;
+wire n3744_64;
+wire n4207_72;
+wire n6923_7;
+wire n6929_5;
+wire n7066_9;
+wire score_area_1_12;
+wire ball_37;
+wire ball_39;
+wire ball_41;
+wire n190_13;
+wire n191_9;
+wire n3741_30;
+wire n319_9;
+wire n4207_74;
+wire n4207_76;
+wire n6913_7;
+wire n6905_7;
+wire n6970_7;
+wire n6962_7;
+wire n6921_7;
+wire n367_11;
+wire n7102_7;
+wire n4207_78;
+wire n4176_50;
+wire n7272_122;
+wire n12765_45;
+wire n12765_47;
+wire n12765_49;
+wire n3744_66;
+wire square_39;
+wire n3735_50;
+wire n3735_52;
+wire n3735_54;
+wire n3737_26;
+wire n3737_28;
+wire n7143_9;
+wire n7092_6;
+wire n7145_7;
+wire n7104_7;
+wire n7086_7;
+wire n7090_7;
+wire n7100_5;
wire n162_9;
-wire n3294_66;
+wire square_41;
+wire ball_43;
+wire n10659_10;
+wire n3737_30;
+wire n3739_22;
+wire n3737_32;
+wire n3737_34;
+wire n3737_36;
+wire n3739_24;
+wire n3744_68;
wire n48_1_4;
wire n197_12;
+wire ball_47;
+wire ball_48;
+wire n10655_6;
+wire n3740_5;
+wire n4207_80;
+wire n4207_82;
+wire n7151_9;
+wire n7153_7;
+wire n10657_7;
+wire n3742_5;
+wire qdy_10;
+wire ball_50;
+wire n7092_8;
+wire n7094_7;
+wire square_43;
wire qdy;
wire square;
wire ball;
wire brick;
+wire score_area_1;
+wire score_area_2;
wire qdx;
-wire n3696_21_SUM;
-wire n3696_24;
-wire n3696_22_SUM;
-wire n3696_26;
-wire n3696_23_SUM;
-wire n3696_28;
-wire n3696_24_SUM;
-wire n3696_30;
-wire n3696_25_SUM;
-wire n3696_32;
-wire n3696_26_SUM;
-wire n3696_34;
-wire n3696_27_SUM;
-wire n3696_36;
-wire n3696_28_SUM;
-wire n3696_38;
-wire n3696_29_SUM;
-wire n3696_40;
-wire n3696_30_SUM;
-wire n3696_42;
-wire n3714_21_SUM;
-wire n3714_24;
-wire n3714_22_SUM;
-wire n3714_26;
-wire n3714_23_SUM;
-wire n3714_28;
-wire n3714_24_SUM;
-wire n3714_30;
-wire n3714_25_SUM;
-wire n3714_32;
-wire n3714_26_SUM;
-wire n3714_34;
-wire n3714_27_SUM;
-wire n3714_36;
-wire n3714_28_SUM;
-wire n3714_38;
-wire n3714_29_SUM;
-wire n3714_40;
-wire n3714_30_SUM;
-wire n3714_42;
-wire n3728_21_SUM;
-wire n3728_24;
-wire n3728_22_SUM;
-wire n3728_26;
-wire n3728_23_SUM;
-wire n3728_28;
-wire n3728_24_SUM;
-wire n3728_30;
-wire n3728_25_SUM;
-wire n3728_32;
-wire n3728_26_SUM;
-wire n3728_34;
-wire n3728_27_SUM;
-wire n3728_36;
-wire n3728_28_SUM;
-wire n3728_38;
-wire n3728_29_SUM;
-wire n3728_40;
-wire n3728_30_SUM;
-wire n3728_42;
+wire n4162_21_SUM;
+wire n4162_24;
+wire n4162_22_SUM;
+wire n4162_26;
+wire n4162_23_SUM;
+wire n4162_28;
+wire n4162_24_SUM;
+wire n4162_30;
+wire n4162_25_SUM;
+wire n4162_32;
+wire n4162_26_SUM;
+wire n4162_34;
+wire n4162_27_SUM;
+wire n4162_36;
+wire n4162_28_SUM;
+wire n4162_38;
+wire n4162_29_SUM;
+wire n4162_40;
+wire n4162_30_SUM;
+wire n4162_42;
+wire n4180_21_SUM;
+wire n4180_24;
+wire n4180_22_SUM;
+wire n4180_26;
+wire n4180_23_SUM;
+wire n4180_28;
+wire n4180_24_SUM;
+wire n4180_30;
+wire n4180_25_SUM;
+wire n4180_32;
+wire n4180_26_SUM;
+wire n4180_34;
+wire n4180_27_SUM;
+wire n4180_36;
+wire n4180_28_SUM;
+wire n4180_38;
+wire n4180_29_SUM;
+wire n4180_40;
+wire n4194_21_SUM;
+wire n4194_24;
+wire n4194_22_SUM;
+wire n4194_26;
+wire n4194_23_SUM;
+wire n4194_28;
+wire n4194_24_SUM;
+wire n4194_30;
+wire n4194_25_SUM;
+wire n4194_32;
+wire n4194_26_SUM;
+wire n4194_34;
+wire n4194_27_SUM;
+wire n4194_36;
+wire n4194_28_SUM;
+wire n4194_38;
+wire n4194_29_SUM;
+wire n4194_40;
wire n83_2;
wire n83_1_1;
wire n82_2;
@@ -2954,12 +3262,190 @@ wire n75_2;
wire n75_1_1;
wire n74_2;
wire n74_1_0_COUT;
+wire n7272_84;
+wire n7272_86;
+wire n7272_88;
+wire n7272_90;
+wire n7272_92;
+wire n7421_79;
+wire n7421_81;
+wire n7421_83;
+wire n7421_85;
+wire n7421_87;
+wire n7272_94;
+wire n7272_96;
+wire n7272_98;
+wire n7421_89;
+wire n7421_91;
+wire n7421_93;
+wire n7272_100;
+wire n7272_102;
+wire n7272_104;
+wire n7421_95;
+wire n7421_97;
+wire n7421_99;
+wire n6848;
wire [9:0] qx;
wire [9:0] qxb;
wire [9:0] qyb;
+wire [7:0] score_counter;
+wire [6:1] \score[6] ;
+wire [6:1] \score[5] ;
+wire [6:4] \score[4] ;
+wire [6:1] \score[3] ;
+wire [6:1] \score[2] ;
+wire [6:1] \score[1] ;
+wire [6:6] \score[0] ;
+wire [6:1] \score_1[6] ;
+wire [6:1] \score_1[5] ;
+wire [6:4] \score_1[4] ;
+wire [6:1] \score_1[3] ;
+wire [6:1] \score_1[2] ;
+wire [6:1] \score_1[1] ;
+wire [6:6] \score_1[0] ;
wire [17:0] bricks_active;
wire VCC;
wire GND;
+ LUT3 n7272_s98 (
+ .F(n7273_13),
+ .I0(\score_1[0] [6]),
+ .I1(\score_1[1] [6]),
+ .I2(sy_Z[1])
+);
+defparam n7272_s98.INIT=8'hCA;
+ LUT3 n7272_s99 (
+ .F(n7273_14),
+ .I0(\score_1[2] [6]),
+ .I1(\score_1[3] [6]),
+ .I2(sy_Z[1])
+);
+defparam n7272_s99.INIT=8'hCA;
+ LUT3 n7272_s100 (
+ .F(n7274_13),
+ .I0(\score_1[1] [6]),
+ .I1(\score_1[1] [5]),
+ .I2(sy_Z[1])
+);
+defparam n7272_s100.INIT=8'hCA;
+ LUT3 n7272_s101 (
+ .F(n7274_14),
+ .I0(\score_1[2] [5]),
+ .I1(\score_1[3] [5]),
+ .I2(sy_Z[1])
+);
+defparam n7272_s101.INIT=8'hCA;
+ LUT3 n7272_s102 (
+ .F(n7275_13),
+ .I0(\score_1[1] [5]),
+ .I1(\score_1[1] [4]),
+ .I2(sy_Z[1])
+);
+defparam n7272_s102.INIT=8'hCA;
+ LUT3 n7272_s103 (
+ .F(n7275_14),
+ .I0(\score_1[2] [4]),
+ .I1(\score_1[3] [4]),
+ .I2(sy_Z[1])
+);
+defparam n7272_s103.INIT=8'hCA;
+ LUT3 n7272_s104 (
+ .F(n7276_10),
+ .I0(\score_1[6] [4]),
+ .I1(\score_1[1] [4]),
+ .I2(sy_Z[1])
+);
+defparam n7272_s104.INIT=8'hCA;
+ LUT3 n7272_s105 (
+ .F(n7276_11),
+ .I0(\score_1[2] [4]),
+ .I1(\score_1[3] [3]),
+ .I2(sy_Z[1])
+);
+defparam n7272_s105.INIT=8'hCA;
+ LUT3 n7272_s106 (
+ .F(n7278_13),
+ .I0(\score_1[0] [6]),
+ .I1(\score_1[1] [1]),
+ .I2(sy_Z[1])
+);
+defparam n7272_s106.INIT=8'hCA;
+ LUT3 n7272_s107 (
+ .F(n7278_14),
+ .I0(\score_1[2] [1]),
+ .I1(\score_1[3] [1]),
+ .I2(sy_Z[1])
+);
+defparam n7272_s107.INIT=8'hCA;
+ LUT3 n7421_s91 (
+ .F(n7422_13),
+ .I0(\score[0] [6]),
+ .I1(\score[1] [6]),
+ .I2(sy_Z[1])
+);
+defparam n7421_s91.INIT=8'hCA;
+ LUT3 n7421_s92 (
+ .F(n7422_14),
+ .I0(\score[2] [6]),
+ .I1(\score[3] [6]),
+ .I2(sy_Z[1])
+);
+defparam n7421_s92.INIT=8'hCA;
+ LUT3 n7421_s93 (
+ .F(n7423_13),
+ .I0(\score[1] [6]),
+ .I1(\score[1] [5]),
+ .I2(sy_Z[1])
+);
+defparam n7421_s93.INIT=8'hCA;
+ LUT3 n7421_s94 (
+ .F(n7423_14),
+ .I0(\score[2] [5]),
+ .I1(\score[3] [5]),
+ .I2(sy_Z[1])
+);
+defparam n7421_s94.INIT=8'hCA;
+ LUT3 n7421_s95 (
+ .F(n7424_13),
+ .I0(\score[1] [5]),
+ .I1(\score[1] [4]),
+ .I2(sy_Z[1])
+);
+defparam n7421_s95.INIT=8'hCA;
+ LUT3 n7421_s96 (
+ .F(n7424_14),
+ .I0(\score[2] [4]),
+ .I1(\score[3] [4]),
+ .I2(sy_Z[1])
+);
+defparam n7421_s96.INIT=8'hCA;
+ LUT3 n7421_s97 (
+ .F(n7425_10),
+ .I0(\score[6] [4]),
+ .I1(\score[1] [4]),
+ .I2(sy_Z[1])
+);
+defparam n7421_s97.INIT=8'hCA;
+ LUT3 n7421_s98 (
+ .F(n7425_11),
+ .I0(\score[2] [4]),
+ .I1(\score[3] [3]),
+ .I2(sy_Z[1])
+);
+defparam n7421_s98.INIT=8'hCA;
+ LUT3 n7421_s99 (
+ .F(n7427_13),
+ .I0(\score[0] [6]),
+ .I1(\score[1] [1]),
+ .I2(sy_Z[1])
+);
+defparam n7421_s99.INIT=8'hCA;
+ LUT3 n7421_s100 (
+ .F(n7427_14),
+ .I0(\score[2] [1]),
+ .I1(\score[3] [1]),
+ .I2(sy_Z[1])
+);
+defparam n7421_s100.INIT=8'hCA;
LUT4 n48_s0 (
.F(n48_3),
.I0(n48_4),
@@ -2971,212 +3457,619 @@ defparam n48_s0.INIT=16'h4F00;
LUT4 n187_s0 (
.F(n187_3),
.I0(n187_4),
- .I1(qxb[8]),
- .I2(n187_5),
- .I3(qxb[9])
+ .I1(qxb[9]),
+ .I2(qxb[8]),
+ .I3(n187_5)
);
-defparam n187_s0.INIT=16'hFD04;
+defparam n187_s0.INIT=16'hE0EC;
LUT4 n190_s0 (
.F(n190_3),
.I0(n190_4),
- .I1(n190_5),
- .I2(n190_6),
- .I3(qdx)
+ .I1(qxb[6]),
+ .I2(n190_13),
+ .I3(n190_6)
);
-defparam n190_s0.INIT=16'h0777;
+defparam n190_s0.INIT=16'h007D;
LUT4 n191_s0 (
.F(n191_3),
- .I0(n190_5),
- .I1(qxb[5]),
- .I2(n191_4),
- .I3(n191_5)
+ .I0(n191_4),
+ .I1(qdx),
+ .I2(n191_5),
+ .I3(n190_4)
);
-defparam n191_s0.INIT=16'h007D;
+defparam n191_s0.INIT=16'hB0BB;
LUT4 n192_s0 (
.F(n192_3),
- .I0(n192_4),
- .I1(n190_5),
- .I2(n192_5),
- .I3(qxb[4])
+ .I0(n190_4),
+ .I1(qxb[4]),
+ .I2(n192_4),
+ .I3(n192_5)
);
-defparam n192_s0.INIT=16'h07B0;
+defparam n192_s0.INIT=16'h007D;
LUT4 n315_s1 (
.F(n315_4),
- .I0(qyb[9]),
- .I1(qdy),
- .I2(n315_5),
- .I3(qyb[8])
+ .I0(qdy),
+ .I1(n315_5),
+ .I2(qyb[8]),
+ .I3(n315_6)
);
-defparam n315_s1.INIT=16'h3FA3;
+defparam n315_s1.INIT=16'h13F1;
LUT4 n316_s1 (
.F(n316_4),
.I0(n316_5),
- .I1(qdy),
- .I2(n316_6),
- .I3(n316_7)
+ .I1(n316_6),
+ .I2(qdy),
+ .I3(qyb[7])
);
-defparam n316_s1.INIT=16'h3F40;
+defparam n316_s1.INIT=16'h3545;
LUT4 n317_s2 (
.F(n317_5),
.I0(n317_6),
- .I1(qdy),
- .I2(n317_12),
- .I3(n317_8)
+ .I1(n317_7),
+ .I2(n317_8),
+ .I3(n317_9)
);
-defparam n317_s2.INIT=16'h7077;
+defparam n317_s2.INIT=16'hF7F8;
LUT4 n319_s1 (
.F(n319_4),
- .I0(n317_8),
- .I1(qyb[4]),
- .I2(n319_5),
- .I3(n319_6)
-);
-defparam n319_s1.INIT=16'h007D;
- LUT4 n3294_s3 (
- .F(n3294_6),
- .I0(n3294_7),
- .I1(n3294_8),
- .I2(n3294_9),
+ .I0(n319_9),
+ .I1(qdy),
+ .I2(n319_6),
+ .I3(n319_7)
+);
+defparam n319_s1.INIT=16'h403F;
+ LUT4 n3744_s3 (
+ .F(n3744_6),
+ .I0(n3744_7),
+ .I1(n3744_8),
+ .I2(n3744_9),
.I3(qdy)
);
-defparam n3294_s3.INIT=16'h00BF;
- LUT3 n9048_s0 (
- .F(n9048_3),
+defparam n3744_s3.INIT=16'h00BF;
+ LUT4 n3735_s0 (
+ .F(n3735_3),
+ .I0(n3735_4),
+ .I1(n3735_5),
+ .I2(n3735_6),
+ .I3(n3735_7)
+);
+defparam n3735_s0.INIT=16'h25C3;
+ LUT4 n3737_s0 (
+ .F(n3737_3),
+ .I0(n3737_4),
+ .I1(n3737_28),
+ .I2(n3737_6),
+ .I3(n3737_7)
+);
+defparam n3737_s0.INIT=16'h0EF1;
+ LUT4 n3738_s0 (
+ .F(n3738_3),
+ .I0(n3737_6),
+ .I1(n3737_4),
+ .I2(n3737_28),
+ .I3(n3738_4)
+);
+defparam n3738_s0.INIT=16'h6996;
+ LUT4 n3739_s0 (
+ .F(n3739_3),
+ .I0(n3739_4),
+ .I1(n3739_20),
+ .I2(n3739_6),
+ .I3(n3739_7)
+);
+defparam n3739_s0.INIT=16'h07D2;
+ LUT4 n3741_s0 (
+ .F(n3741_3),
+ .I0(n3741_4),
+ .I1(n3741_5),
+ .I2(n3741_6),
+ .I3(n3741_28)
+);
+defparam n3741_s0.INIT=16'h5AC3;
+ LUT2 n10654_s0 (
+ .F(n10654_3),
.I0(frame_Z),
- .I1(n9048_4),
- .I2(n9048_5)
+ .I1(n10654_4)
);
-defparam n9048_s0.INIT=8'h08;
- LUT4 n9049_s0 (
- .F(n9049_3),
- .I0(bricks_active[16]),
- .I1(frame_Z),
- .I2(n9049_4),
- .I3(n9049_5)
-);
-defparam n9049_s0.INIT=16'h8000;
- LUT4 n9050_s0 (
- .F(n9050_3),
- .I0(bricks_active[15]),
- .I1(n9049_5),
- .I2(n9050_4),
- .I3(n9050_12)
-);
-defparam n9050_s0.INIT=16'h8000;
- LUT3 n9052_s0 (
- .F(n9052_3),
- .I0(bricks_active[13]),
- .I1(n9049_5),
- .I2(n9052_12)
-);
-defparam n9052_s0.INIT=8'h80;
- LUT3 n9053_s0 (
- .F(n9053_3),
+defparam n10654_s0.INIT=4'h8;
+ LUT2 n10655_s0 (
+ .F(n10655_3),
.I0(frame_Z),
- .I1(n9053_4),
- .I2(n9049_5)
+ .I1(n10655_6)
);
-defparam n9053_s0.INIT=8'h80;
- LUT3 n9054_s0 (
- .F(n9054_3),
+defparam n10655_s0.INIT=4'h8;
+ LUT2 n10656_s0 (
+ .F(n10656_3),
.I0(frame_Z),
- .I1(n9048_5),
- .I2(n9054_4)
+ .I1(n3741_4)
);
-defparam n9054_s0.INIT=8'h20;
- LUT4 n9055_s0 (
- .F(n9055_3),
- .I0(bricks_active[10]),
- .I1(frame_Z),
- .I2(n9049_4),
- .I3(n9055_4)
-);
-defparam n9055_s0.INIT=16'h8000;
- LUT2 n9056_s0 (
- .F(n9056_3),
- .I0(n9056_4),
- .I1(n9050_12)
-);
-defparam n9056_s0.INIT=4'h8;
- LUT2 n9059_s0 (
- .F(n9059_3),
+defparam n10656_s0.INIT=4'h8;
+ LUT2 n10658_s0 (
+ .F(n10658_3),
+ .I0(frame_Z),
+ .I1(n10658_4)
+);
+defparam n10658_s0.INIT=4'h8;
+ LUT2 n10659_s0 (
+ .F(n10659_3),
+ .I0(frame_Z),
+ .I1(n10659_4)
+);
+defparam n10659_s0.INIT=4'h8;
+ LUT2 n10660_s0 (
+ .F(n10660_3),
+ .I0(frame_Z),
+ .I1(n10660_4)
+);
+defparam n10660_s0.INIT=4'h8;
+ LUT2 n10661_s0 (
+ .F(n10661_3),
.I0(frame_Z),
- .I1(n9059_4)
+ .I1(n10661_4)
);
-defparam n9059_s0.INIT=4'h8;
- LUT3 n9060_s0 (
- .F(n9060_3),
+defparam n10661_s0.INIT=4'h8;
+ LUT2 n10662_s0 (
+ .F(n10662_3),
.I0(frame_Z),
- .I1(n9060_4),
- .I2(n9048_5)
+ .I1(n10662_4)
);
-defparam n9060_s0.INIT=8'h08;
- LUT4 n9061_s0 (
- .F(n9061_3),
+defparam n10662_s0.INIT=4'h8;
+ LUT2 n10664_s0 (
+ .F(n10664_3),
+ .I0(frame_Z),
+ .I1(n10664_7)
+);
+defparam n10664_s0.INIT=4'h8;
+ LUT2 n10665_s0 (
+ .F(n10665_3),
+ .I0(frame_Z),
+ .I1(n10665_4)
+);
+defparam n10665_s0.INIT=4'h8;
+ LUT2 n10666_s0 (
+ .F(n10666_3),
+ .I0(frame_Z),
+ .I1(n10666_4)
+);
+defparam n10666_s0.INIT=4'h8;
+ LUT4 n10667_s0 (
+ .F(n10667_3),
.I0(bricks_active[4]),
.I1(frame_Z),
- .I2(n9049_4),
- .I3(n9061_4)
-);
-defparam n9061_s0.INIT=16'h8000;
- LUT4 n9062_s0 (
- .F(n9062_3),
- .I0(bricks_active[3]),
- .I1(n9061_4),
- .I2(n9050_4),
- .I3(n9050_12)
-);
-defparam n9062_s0.INIT=16'h8000;
- LUT2 n9064_s0 (
- .F(n9064_3),
- .I0(n9064_4),
- .I1(n9052_12)
-);
-defparam n9064_s0.INIT=4'h8;
- LUT2 n9065_s0 (
- .F(n9065_3),
+ .I2(n10667_4),
+ .I3(n10667_5)
+);
+defparam n10667_s0.INIT=16'h8000;
+ LUT2 n10668_s0 (
+ .F(n10668_3),
+ .I0(frame_Z),
+ .I1(n10668_4)
+);
+defparam n10668_s0.INIT=4'h8;
+ LUT2 n10669_s0 (
+ .F(n10669_3),
+ .I0(frame_Z),
+ .I1(n10669_4)
+);
+defparam n10669_s0.INIT=4'h8;
+ LUT2 n10670_s0 (
+ .F(n10670_3),
+ .I0(frame_Z),
+ .I1(n10670_4)
+);
+defparam n10670_s0.INIT=4'h8;
+ LUT2 n10671_s0 (
+ .F(n10671_3),
.I0(frame_Z),
- .I1(n9065_4)
-);
-defparam n9065_s0.INIT=4'h8;
- LUT4 n11097_s0 (
- .F(n11097_3),
- .I0(n11097_4),
- .I1(n11097_5),
- .I2(n11097_6),
- .I3(n11097_7)
-);
-defparam n11097_s0.INIT=16'hFFF4;
- LUT2 n11074_s0 (
- .F(n11074_3),
- .I0(square),
- .I1(ball)
-);
-defparam n11074_s0.INIT=4'hE;
- LUT4 qxb_9_s2 (
+ .I1(n10671_4)
+);
+defparam n10671_s0.INIT=4'h8;
+ LUT4 n12765_s0 (
+ .F(n12765_3),
+ .I0(n12765_4),
+ .I1(n12765_5),
+ .I2(n12765_6),
+ .I3(n12765_7)
+);
+defparam n12765_s0.INIT=16'hFFF4;
+ LUT4 n6878_s1 (
+ .F(n6878_4),
+ .I0(n6847),
+ .I1(n6846),
+ .I2(n6848),
+ .I3(n6878_5)
+);
+defparam n6878_s1.INIT=16'h1000;
+ LUT4 n6880_s1 (
+ .F(n6880_4),
+ .I0(n6848),
+ .I1(n6846),
+ .I2(n6847),
+ .I3(n6878_5)
+);
+defparam n6880_s1.INIT=16'h1000;
+ LUT4 n6885_s1 (
+ .F(n6885_4),
+ .I0(n6848),
+ .I1(n6847),
+ .I2(n6846),
+ .I3(n6878_5)
+);
+defparam n6885_s1.INIT=16'h1000;
+ LUT4 n6888_s2 (
+ .F(n6888_5),
+ .I0(n6847),
+ .I1(n6848),
+ .I2(n6846),
+ .I3(n6878_5)
+);
+defparam n6888_s2.INIT=16'h4000;
+ LUT4 n6895_s3 (
+ .F(n6895_6),
+ .I0(n6848),
+ .I1(n6847),
+ .I2(n6846),
+ .I3(n6878_5)
+);
+defparam n6895_s3.INIT=16'h8000;
+ LUT3 n6911_s0 (
+ .F(n6911_3),
+ .I0(n6878_4),
+ .I1(n6880_4),
+ .I2(n6885_4)
+);
+defparam n6911_s0.INIT=8'hFE;
+ LUT3 n6919_s0 (
+ .F(n6919_3),
+ .I0(n6878_4),
+ .I1(n6885_4),
+ .I2(n6895_6)
+);
+defparam n6919_s0.INIT=8'hFE;
+ LUT2 n6925_s0 (
+ .F(n6925_3),
+ .I0(n6848),
+ .I1(n6925_4)
+);
+defparam n6925_s0.INIT=4'h4;
+ LUT4 n6937_s0 (
+ .F(n6937_3),
+ .I0(n6846),
+ .I1(n6847),
+ .I2(n6848),
+ .I3(n6878_5)
+);
+defparam n6937_s0.INIT=16'h0B00;
+ LUT3 n6939_s0 (
+ .F(n6939_3),
+ .I0(n6845),
+ .I1(n6848),
+ .I2(n6925_4)
+);
+defparam n6939_s0.INIT=8'hB0;
+ LUT2 n6941_s0 (
+ .F(n6941_3),
+ .I0(n6941_4),
+ .I1(n6843)
+);
+defparam n6941_s0.INIT=4'h1;
+ LUT3 n6948_s0 (
+ .F(n6948_3),
+ .I0(n6948_4),
+ .I1(n6847),
+ .I2(n6843)
+);
+defparam n6948_s0.INIT=8'h01;
+ LUT2 n6950_s0 (
+ .F(n6950_3),
+ .I0(n6950_4),
+ .I1(n6843)
+);
+defparam n6950_s0.INIT=4'h1;
+ LUT4 n6954_s0 (
+ .F(n6954_3),
+ .I0(n6846),
+ .I1(n6848),
+ .I2(n6847),
+ .I3(n6878_5)
+);
+defparam n6954_s0.INIT=16'h0E00;
+ LUT4 n7059_s3 (
+ .F(n7059_6),
+ .I0(n7056),
+ .I1(n7052),
+ .I2(n7055),
+ .I3(n7059_7)
+);
+defparam n7059_s3.INIT=16'h1000;
+ LUT4 n7061_s3 (
+ .F(n7061_6),
+ .I0(n7055),
+ .I1(n7052),
+ .I2(n7056),
+ .I3(n7059_7)
+);
+defparam n7061_s3.INIT=16'h1000;
+ LUT2 n7066_s3 (
+ .F(n7066_6),
+ .I0(n7056),
+ .I1(n7066_9)
+);
+defparam n7066_s3.INIT=4'h8;
+ LUT2 n7069_s2 (
+ .F(n7069_5),
+ .I0(n7056),
+ .I1(n7066_9)
+);
+defparam n7069_s2.INIT=4'h4;
+ LUT3 n7076_s1 (
+ .F(n7076_4),
+ .I0(n7056),
+ .I1(n7055),
+ .I2(n7076_5)
+);
+defparam n7076_s1.INIT=8'h10;
+ LUT2 n7106_s0 (
+ .F(n7106_3),
+ .I0(n7056),
+ .I1(n7106_4)
+);
+defparam n7106_s0.INIT=4'h8;
+ LUT3 n7110_s0 (
+ .F(n7110_3),
+ .I0(n7061_6),
+ .I1(n7076_4),
+ .I2(n7092_6)
+);
+defparam n7110_s0.INIT=8'hEF;
+ LUT3 n7118_s0 (
+ .F(n7118_3),
+ .I0(n7053),
+ .I1(n7056),
+ .I2(n7106_4)
+);
+defparam n7118_s0.INIT=8'h80;
+ LUT3 n7120_s0 (
+ .F(n7120_3),
+ .I0(n7053),
+ .I1(n7056),
+ .I2(n7106_4)
+);
+defparam n7120_s0.INIT=8'hD0;
+ LUT2 n7122_s0 (
+ .F(n7122_3),
+ .I0(n7122_4),
+ .I1(n7052)
+);
+defparam n7122_s0.INIT=4'h1;
+ LUT3 n7129_s0 (
+ .F(n7129_3),
+ .I0(n7129_4),
+ .I1(n7052),
+ .I2(n7055)
+);
+defparam n7129_s0.INIT=8'h10;
+ LUT2 n7131_s0 (
+ .F(n7131_3),
+ .I0(n7131_4),
+ .I1(n7052)
+);
+defparam n7131_s0.INIT=4'h1;
+ LUT2 n7135_s0 (
+ .F(n7135_3),
+ .I0(n7059_6),
+ .I1(n7066_9)
+);
+defparam n7135_s0.INIT=4'hE;
+ LUT2 n12742_s0 (
+ .F(n12742_3),
+ .I0(ball),
+ .I1(square)
+);
+defparam n12742_s0.INIT=4'hE;
+ LUT3 n7052_s10 (
+ .F(n7052),
+ .I0(score_counter[5]),
+ .I1(score_counter[6]),
+ .I2(score_counter[7])
+);
+defparam n7052_s10.INIT=8'hE0;
+ LUT4 n7053_s12 (
+ .F(n7053),
+ .I0(score_counter[4]),
+ .I1(score_counter[7]),
+ .I2(score_counter[5]),
+ .I3(score_counter[6])
+);
+defparam n7053_s12.INIT=16'h4DF3;
+ LUT4 n7054_s12 (
+ .F(n7054),
+ .I0(n7054_20),
+ .I1(score_counter[7]),
+ .I2(score_counter[5]),
+ .I3(n7054_21)
+);
+defparam n7054_s12.INIT=16'hEB28;
+ LUT4 n7055_s19 (
+ .F(n7055),
+ .I0(score_counter[2]),
+ .I1(n7055_29),
+ .I2(n7055_30),
+ .I3(n7055_31)
+);
+defparam n7055_s19.INIT=16'h00F1;
+ LUT4 n7056_s20 (
+ .F(n7056),
+ .I0(n7055),
+ .I1(n7055_31),
+ .I2(n7055_30),
+ .I3(n7056_32)
+);
+defparam n7056_s20.INIT=16'hA300;
+ LUT4 n6906_s1 (
+ .F(n6906_5),
+ .I0(n6846),
+ .I1(n6847),
+ .I2(n6845),
+ .I3(n6843)
+);
+defparam n6906_s1.INIT=16'h001F;
+ LUT2 n6909_s1 (
+ .F(n6909_5),
+ .I0(n6895_6),
+ .I1(n6906_5)
+);
+defparam n6909_s1.INIT=4'h4;
+ LUT2 n6944_s1 (
+ .F(n6944_5),
+ .I0(n6944_6),
+ .I1(n6843)
+);
+defparam n6944_s1.INIT=4'h2;
+ LUT2 n6946_s1 (
+ .F(n6946_5),
+ .I0(n6878_4),
+ .I1(n6906_5)
+);
+defparam n6946_s1.INIT=4'h4;
+ LUT2 n6952_s1 (
+ .F(n6952_5),
+ .I0(n6843),
+ .I1(n6952_6)
+);
+defparam n6952_s1.INIT=4'h4;
+ LUT2 n6958_s1 (
+ .F(n6958_5),
+ .I0(n6843),
+ .I1(n6958_6)
+);
+defparam n6958_s1.INIT=4'h4;
+ LUT2 n6964_s1 (
+ .F(n6964_5),
+ .I0(n6885_4),
+ .I1(n6906_5)
+);
+defparam n6964_s1.INIT=4'h4;
+ LUT2 n6972_s1 (
+ .F(n6972_5),
+ .I0(n6954_3),
+ .I1(n6906_5)
+);
+defparam n6972_s1.INIT=4'h4;
+ LUT4 n7087_s1 (
+ .F(n7087_5),
+ .I0(n7054),
+ .I1(n7055),
+ .I2(n7053),
+ .I3(n7052)
+);
+defparam n7087_s1.INIT=16'h00F8;
+ LUT2 n7125_s1 (
+ .F(n7125_5),
+ .I0(n7052),
+ .I1(n7125_6)
+);
+defparam n7125_s1.INIT=4'h1;
+ LUT2 n7127_s1 (
+ .F(n7127_5),
+ .I0(n7059_6),
+ .I1(n7087_5)
+);
+defparam n7127_s1.INIT=4'h4;
+ LUT4 n7133_s1 (
+ .F(n7133_5),
+ .I0(n7059_7),
+ .I1(n7055),
+ .I2(n7056),
+ .I3(n7106_4)
+);
+defparam n7133_s1.INIT=16'hF400;
+ LUT4 n7139_s1 (
+ .F(n7139_5),
+ .I0(n7055),
+ .I1(n7076_5),
+ .I2(n7056),
+ .I3(n7127_5)
+);
+defparam n7139_s1.INIT=16'hBF00;
+ LUT2 n7141_s1 (
+ .F(n7141_5),
+ .I0(n7066_9),
+ .I1(n7139_5)
+);
+defparam n7141_s1.INIT=4'h4;
+ LUT3 n7272_s108 (
+ .F(n7273_17),
+ .I0(\score_1[5] [6]),
+ .I1(\score_1[4] [6]),
+ .I2(sy_Z[1])
+);
+defparam n7272_s108.INIT=8'hAC;
+ LUT3 n7272_s110 (
+ .F(n7274_17),
+ .I0(\score_1[4] [5]),
+ .I1(\score_1[5] [6]),
+ .I2(sy_Z[1])
+);
+defparam n7272_s110.INIT=8'hCA;
+ LUT3 n7272_s112 (
+ .F(n7278_17),
+ .I0(\score_1[5] [2]),
+ .I1(\score_1[5] [1]),
+ .I2(sy_Z[1])
+);
+defparam n7272_s112.INIT=8'hCA;
+ LUT3 n7421_s101 (
+ .F(n7422_17),
+ .I0(\score[4] [6]),
+ .I1(\score[5] [6]),
+ .I2(sy_Z[1])
+);
+defparam n7421_s101.INIT=8'hCA;
+ LUT3 n7421_s103 (
+ .F(n7423_17),
+ .I0(\score[4] [5]),
+ .I1(\score[5] [6]),
+ .I2(sy_Z[1])
+);
+defparam n7421_s103.INIT=8'hCA;
+ LUT3 n7421_s105 (
+ .F(n7427_17),
+ .I0(\score[5] [2]),
+ .I1(\score[5] [1]),
+ .I2(sy_Z[1])
+);
+defparam n7421_s105.INIT=8'hCA;
+ LUT3 qxb_9_s2 (
.F(qxb_9_6),
- .I0(n3294_7),
- .I1(n317_8),
- .I2(qxb_9_7),
- .I3(frame_Z)
+ .I0(n3744_7),
+ .I1(frame_Z),
+ .I2(qyb_6_5)
);
-defparam qxb_9_s2.INIT=16'hBF00;
+defparam qxb_9_s2.INIT=8'hC8;
LUT4 square_s2 (
.F(square_6),
.I0(square_7),
- .I1(square_31),
- .I2(square_27),
- .I3(square_10)
+ .I1(sx_Z[9]),
+ .I2(square_8),
+ .I3(square_9)
);
-defparam square_s2.INIT=16'h0EFF;
+defparam square_s2.INIT=16'hE8FF;
LUT4 ball_s2 (
.F(ball_6),
- .I0(ball_7),
+ .I0(ball_35),
.I1(ball_8),
.I2(ball_9),
- .I3(n3714_42)
+ .I3(ball_47)
);
-defparam ball_s2.INIT=16'h4FFF;
+defparam ball_s2.INIT=16'h8EFF;
+ LUT3 score_area_2_s2 (
+ .F(score_area_2_6),
+ .I0(sx_Z[5]),
+ .I1(sx_Z[4]),
+ .I2(score_area_1_8)
+);
+defparam score_area_2_s2.INIT=8'hBF;
LUT4 qx_9_s2 (
.F(qx_9_6),
.I0(qx_9_7),
@@ -3187,86 +4080,144 @@ defparam ball_s2.INIT=16'h4FFF;
defparam qx_9_s2.INIT=16'hF400;
LUT4 qyb_9_s2 (
.F(qyb_6_5),
- .I0(n3294_7),
- .I1(qxb_9_7),
- .I2(n317_8),
+ .I0(qdy),
+ .I1(qyb_9_7),
+ .I2(n3744_8),
.I3(frame_Z)
);
-defparam qyb_9_s2.INIT=16'h1F00;
- LUT4 n3741_s26 (
- .F(n3741_33),
- .I0(n3741_34),
- .I1(qyb[9]),
- .I2(n3741_35),
- .I3(sy_Z[9])
-);
-defparam n3741_s26.INIT=16'hD4FD;
+defparam qyb_9_s2.INIT=16'hEF00;
+ LUT4 n4207_s26 (
+ .F(n4207_33),
+ .I0(n4207_34),
+ .I1(n4207_35),
+ .I2(n4207_36),
+ .I3(n4207_37)
+);
+defparam n4207_s26.INIT=16'hEEE0;
+ LUT2 n6847_s5 (
+ .F(n6847),
+ .I0(n6847_11),
+ .I1(score_counter[0])
+);
+defparam n6847_s5.INIT=4'h6;
+ LUT4 n7272_s76 (
+ .F(n7272_106),
+ .I0(n7272_122),
+ .I1(\score_1[6] [4]),
+ .I2(n7272_108),
+ .I3(n7272_109)
+);
+defparam n7272_s76.INIT=16'hFFF8;
+ LUT3 n7421_s72 (
+ .F(n7421_101),
+ .I0(n7272_122),
+ .I1(\score[6] [4]),
+ .I2(n7421_102)
+);
+defparam n7421_s72.INIT=8'h8F;
LUT4 qdy_s3 (
.F(qdy_7),
- .I0(n3294_7),
- .I1(n3294_9),
- .I2(qdy_8),
- .I3(qdy_9)
-);
-defparam qdy_s3.INIT=16'hBF00;
- LUT4 n3710_s33 (
- .F(n3710_46),
- .I0(n3710_47),
+ .I0(qyb_9_7),
+ .I1(qdy),
+ .I2(qdy_10),
+ .I3(frame_Z)
+);
+defparam qdy_s3.INIT=16'h1F00;
+ LUT4 n4176_s33 (
+ .F(n4176_46),
+ .I0(n4176_47),
.I1(sy_Z[8]),
.I2(sy_Z[7]),
.I3(sy_Z[9])
);
-defparam n3710_s33.INIT=16'h00BF;
- LUT2 n367_s4 (
- .F(n367_8),
- .I0(qyb[0]),
- .I1(n367_9)
-);
-defparam n367_s4.INIT=4'h1;
+defparam n4176_s33.INIT=16'h00BF;
LUT4 n366_s3 (
.F(n366_7),
- .I0(n367_9),
- .I1(qdy),
- .I2(qyb[0]),
- .I3(qyb[1])
+ .I0(qdy),
+ .I1(qyb[0]),
+ .I2(qyb[1]),
+ .I3(n367_9)
);
-defparam n366_s3.INIT=16'h4114;
+defparam n366_s3.INIT=16'h9600;
LUT3 n365_s3 (
.F(n365_7),
- .I0(n367_9),
- .I1(n365_8),
- .I2(qyb[2])
+ .I0(n365_8),
+ .I1(qyb[2]),
+ .I2(n367_9)
);
-defparam n365_s3.INIT=8'h14;
+defparam n365_s3.INIT=8'h60;
LUT3 n364_s3 (
.F(n364_7),
- .I0(n367_9),
+ .I0(n364_8),
.I1(qyb[3]),
- .I2(n364_8)
+ .I2(n367_9)
);
-defparam n364_s3.INIT=8'h41;
+defparam n364_s3.INIT=8'h90;
LUT3 n362_s3 (
.F(n362_7),
- .I0(n367_9),
+ .I0(n362_8),
.I1(qyb[5]),
- .I2(n362_8)
+ .I2(n367_9)
);
-defparam n362_s3.INIT=8'h41;
- LUT4 n358_s4 (
+defparam n362_s3.INIT=8'h90;
+ LUT3 n358_s4 (
.F(n358_8),
- .I0(qyb[7]),
- .I1(qyb[8]),
- .I2(n316_6),
- .I3(n358_9)
+ .I0(n358_9),
+ .I1(qdy),
+ .I2(qyb[9])
);
-defparam n358_s4.INIT=16'hEF00;
- LUT3 n3881_s1 (
- .F(n3881_5),
+defparam n358_s4.INIT=8'h40;
+ LUT2 n7421_s106 (
+ .F(n7427_19),
+ .I0(sy_Z[1]),
+ .I1(\score[6] [1])
+);
+defparam n7421_s106.INIT=4'h4;
+ LUT2 n7421_s104 (
+ .F(n7423_19),
+ .I0(sy_Z[1]),
+ .I1(\score[6] [5])
+);
+defparam n7421_s104.INIT=4'h4;
+ LUT2 n7421_s102 (
+ .F(n7422_19),
+ .I0(sy_Z[1]),
+ .I1(\score[6] [6])
+);
+defparam n7421_s102.INIT=4'h4;
+ LUT2 n7272_s113 (
+ .F(n7278_19),
+ .I0(sy_Z[1]),
+ .I1(\score_1[6] [1])
+);
+defparam n7272_s113.INIT=4'h4;
+ LUT2 n7272_s111 (
+ .F(n7274_19),
+ .I0(sy_Z[1]),
+ .I1(\score_1[6] [5])
+);
+defparam n7272_s111.INIT=4'h4;
+ LUT2 n7272_s109 (
+ .F(n7273_19),
+ .I0(sy_Z[1]),
+ .I1(\score_1[6] [6])
+);
+defparam n7272_s109.INIT=4'h4;
+ LUT4 n7585_s1 (
+ .F(n7585_5),
+ .I0(score_area_2),
+ .I1(score_area_1),
+ .I2(ball),
+ .I3(brick)
+);
+defparam n7585_s1.INIT=16'h000E;
+ LUT3 n4347_s1 (
+ .F(n4347_5),
.I0(bricks_active[0]),
- .I1(n11097_5),
- .I2(n3881_6)
+ .I1(n12765_5),
+ .I2(n4347_6)
);
-defparam n3881_s1.INIT=8'h80;
+defparam n4347_s1.INIT=8'h80;
LUT4 n161_s2 (
.F(n161_6),
.I0(qdx_7),
@@ -3289,22 +4240,59 @@ defparam n160_s2.INIT=8'h14;
.I2(n159_7)
);
defparam n159_s2.INIT=8'h41;
- LUT4 n155_s2 (
- .F(n155_6),
- .I0(n155_7),
- .I1(n187_4),
- .I2(qdx_7),
- .I3(qxb[7])
+ LUT3 n155_s2 (
+ .F(n155_19),
+ .I0(qdx_7),
+ .I1(qxb[7]),
+ .I2(n155_20)
);
-defparam n155_s2.INIT=16'h010E;
+defparam n155_s2.INIT=8'h41;
LUT4 n154_s2 (
- .F(n154_6),
- .I0(qdx),
- .I1(qxb[9]),
- .I2(qxb[8]),
- .I3(n187_5)
+ .F(n154_8),
+ .I0(n187_5),
+ .I1(n187_4),
+ .I2(qdx_7),
+ .I3(qxb[8])
);
-defparam n154_s2.INIT=16'hB009;
+defparam n154_s2.INIT=16'h010E;
+ LUT3 n6843_s16 (
+ .F(n6843),
+ .I0(score_counter[1]),
+ .I1(n6843_22),
+ .I2(n6845)
+);
+defparam n6843_s16.INIT=8'h60;
+ LUT4 n7569_s1 (
+ .F(n7569_5),
+ .I0(score_area_1),
+ .I1(score_area_2),
+ .I2(brick),
+ .I3(ball)
+);
+defparam n7569_s1.INIT=16'hFF0E;
+ LUT3 n7553_s1 (
+ .F(n7553_5),
+ .I0(brick),
+ .I1(score_area_1),
+ .I2(score_area_2)
+);
+defparam n7553_s1.INIT=8'hFE;
+ LUT4 n6846_s5 (
+ .F(n6846),
+ .I0(score_counter[0]),
+ .I1(n6846_12),
+ .I2(n6846_13),
+ .I3(n6846_14)
+);
+defparam n6846_s5.INIT=16'h53B4;
+ LUT4 n6845_s5 (
+ .F(n6845),
+ .I0(n6845_12),
+ .I1(n6846_14),
+ .I2(n6843_22),
+ .I3(n6846_12)
+);
+defparam n6845_s5.INIT=16'h48B4;
LUT4 n48_s1 (
.F(n48_4),
.I0(qx[2]),
@@ -3321,59 +4309,52 @@ defparam n48_s1.INIT=16'hF800;
.I3(qx[8])
);
defparam n48_s2.INIT=16'h0001;
- LUT4 n187_s1 (
+ LUT3 n187_s1 (
.F(n187_4),
- .I0(qxb[5]),
- .I1(qxb[6]),
- .I2(qdx),
- .I3(n187_6)
+ .I0(qdx),
+ .I1(n192_4),
+ .I2(n187_6)
);
-defparam n187_s1.INIT=16'h1000;
- LUT3 n187_s2 (
+defparam n187_s1.INIT=8'h40;
+ LUT4 n187_s2 (
.F(n187_5),
- .I0(n187_4),
+ .I0(qxb[6]),
.I1(qxb[7]),
- .I2(n155_7)
+ .I2(qdx),
+ .I3(n187_7)
);
-defparam n187_s2.INIT=8'h1D;
+defparam n187_s2.INIT=16'h1000;
LUT4 n190_s1 (
.F(n190_4),
- .I0(qxb[4]),
- .I1(qxb[5]),
- .I2(n192_4),
- .I3(qxb[6])
-);
-defparam n190_s1.INIT=16'h807F;
- LUT4 n190_s2 (
- .F(n190_5),
.I0(n190_7),
- .I1(n190_8),
+ .I1(qxb[7]),
.I2(qxb[9]),
.I3(qdx)
);
-defparam n190_s2.INIT=16'h004F;
+defparam n190_s1.INIT=16'h0017;
LUT4 n190_s3 (
.F(n190_6),
.I0(n190_9),
- .I1(qxb[5]),
- .I2(n187_6),
- .I3(qxb[6])
+ .I1(qxb[6]),
+ .I2(n187_7),
+ .I3(qdx)
);
-defparam n190_s3.INIT=16'h30EF;
- LUT2 n191_s1 (
+defparam n190_s3.INIT=16'hE300;
+ LUT4 n191_s1 (
.F(n191_4),
.I0(qxb[4]),
- .I1(n192_4)
+ .I1(n191_6),
+ .I2(n191_9),
+ .I3(qxb[5])
);
-defparam n191_s1.INIT=4'h8;
- LUT4 n191_s2 (
+defparam n191_s1.INIT=16'h0B04;
+ LUT3 n191_s2 (
.F(n191_5),
- .I0(n191_6),
- .I1(qxb[5]),
- .I2(n187_6),
- .I3(qdx)
-);
-defparam n191_s2.INIT=16'hE300;
+ .I0(qxb[4]),
+ .I1(n192_4),
+ .I2(qxb[5])
+);
+defparam n191_s2.INIT=8'h78;
LUT4 n192_s1 (
.F(n192_4),
.I0(qxb[1]),
@@ -3384,290 +4365,576 @@ defparam n191_s2.INIT=16'hE300;
defparam n192_s1.INIT=16'hF800;
LUT4 n192_s2 (
.F(n192_5),
- .I0(n191_6),
+ .I0(n191_9),
.I1(qxb[4]),
- .I2(n192_9),
+ .I2(n191_6),
.I3(qdx)
);
-defparam n192_s2.INIT=16'hD033;
- LUT4 n315_s2 (
+defparam n192_s2.INIT=16'hE300;
+ LUT3 n315_s2 (
.F(n315_5),
- .I0(n315_8),
- .I1(n316_6),
- .I2(qdy),
- .I3(qyb[7])
+ .I0(qyb[7]),
+ .I1(n315_7),
+ .I2(qyb[9])
+);
+defparam n315_s2.INIT=8'h07;
+ LUT4 n315_s3 (
+ .F(n315_6),
+ .I0(qyb[7]),
+ .I1(qdy),
+ .I2(n319_6),
+ .I3(n315_11)
);
-defparam n315_s2.INIT=16'h05CF;
- LUT2 n316_s2 (
+defparam n315_s3.INIT=16'h4000;
+ LUT4 n316_s2 (
.F(n316_5),
- .I0(qyb[8]),
- .I1(qyb[9])
+ .I0(qdy),
+ .I1(qyb[7]),
+ .I2(n315_7),
+ .I3(n3744_8)
);
-defparam n316_s2.INIT=4'h1;
- LUT3 n316_s3 (
+defparam n316_s2.INIT=16'hC100;
+ LUT4 n316_s3 (
.F(n316_6),
- .I0(qyb[5]),
- .I1(qyb[6]),
- .I2(n316_8)
-);
-defparam n316_s3.INIT=8'h10;
- LUT4 n316_s4 (
- .F(n316_7),
- .I0(qdy),
- .I1(n315_8),
- .I2(n3294_8),
- .I3(qyb[7])
+ .I0(n316_7),
+ .I1(qyb[7]),
+ .I2(n315_11),
+ .I3(n319_6)
);
-defparam n316_s4.INIT=16'hBF45;
- LUT4 n317_s3 (
+defparam n316_s3.INIT=16'hD000;
+ LUT2 n317_s3 (
.F(n317_6),
- .I0(n317_9),
- .I1(qyb[5]),
- .I2(n316_8),
- .I3(qyb[6])
+ .I0(qyb[4]),
+ .I1(qyb[5])
+);
+defparam n317_s3.INIT=4'h8;
+ LUT4 n317_s4 (
+ .F(n317_7),
+ .I0(n317_10),
+ .I1(qyb[2]),
+ .I2(qdy),
+ .I3(qyb[3])
);
-defparam n317_s3.INIT=16'h30EF;
+defparam n317_s4.INIT=16'h0E00;
LUT2 n317_s5 (
.F(n317_8),
.I0(qdy),
- .I1(n3294_8)
+ .I1(n3744_8)
+);
+defparam n317_s5.INIT=4'h1;
+ LUT4 n317_s6 (
+ .F(n317_9),
+ .I0(n316_7),
+ .I1(qyb[7]),
+ .I2(qyb[6]),
+ .I3(n317_13)
);
-defparam n317_s5.INIT=4'h4;
- LUT4 n319_s2 (
- .F(n319_5),
+defparam n317_s6.INIT=16'h0DF0;
+ LUT4 n319_s3 (
+ .F(n319_6),
.I0(qyb[1]),
.I1(qyb[0]),
.I2(qyb[2]),
.I3(qyb[3])
);
-defparam n319_s2.INIT=16'hF800;
- LUT4 n319_s3 (
- .F(n319_6),
- .I0(n316_6),
- .I1(n317_9),
- .I2(n319_7),
- .I3(qdy)
-);
-defparam n319_s3.INIT=16'hF800;
- LUT4 n3294_s4 (
- .F(n3294_7),
- .I0(n3294_10),
- .I1(n3294_11),
- .I2(n3294_12),
- .I3(n3294_13)
-);
-defparam n3294_s4.INIT=16'h0B00;
- LUT4 n3294_s5 (
- .F(n3294_8),
- .I0(qyb[6]),
- .I1(qyb[7]),
- .I2(n3294_14),
+defparam n319_s3.INIT=16'h001F;
+ LUT4 n319_s4 (
+ .F(n319_7),
+ .I0(qdy),
+ .I1(n3744_8),
+ .I2(qyb[4]),
+ .I3(n317_7)
+);
+defparam n319_s4.INIT=16'hE00E;
+ LUT3 n3744_s4 (
+ .F(n3744_7),
+ .I0(n3744_10),
+ .I1(n3744_64),
+ .I2(n3744_12)
+);
+defparam n3744_s4.INIT=8'h40;
+ LUT4 n3744_s5 (
+ .F(n3744_8),
+ .I0(n3744_13),
+ .I1(qyb[6]),
+ .I2(n3744_14),
.I3(qyb[9])
);
-defparam n3294_s5.INIT=16'h007F;
- LUT2 n3294_s6 (
- .F(n3294_9),
- .I0(n3294_15),
- .I1(n3294_16)
-);
-defparam n3294_s6.INIT=4'h8;
- LUT3 n9048_s1 (
- .F(n9048_4),
- .I0(n9048_6),
- .I1(n9049_5),
- .I2(bricks_active[17])
-);
-defparam n9048_s1.INIT=8'h40;
- LUT3 n9048_s2 (
- .F(n9048_5),
- .I0(n9048_7),
- .I1(n9048_8),
- .I2(qxb[9])
+defparam n3744_s5.INIT=16'h00BF;
+ LUT4 n3744_s6 (
+ .F(n3744_9),
+ .I0(n3744_68),
+ .I1(n3741_5),
+ .I2(n3744_58),
+ .I3(n3744_17)
+);
+defparam n3744_s6.INIT=16'h4000;
+ LUT3 n3735_s1 (
+ .F(n3735_4),
+ .I0(n3735_8),
+ .I1(n3735_46),
+ .I2(n3735_48)
+);
+defparam n3735_s1.INIT=8'h40;
+ LUT3 n3735_s2 (
+ .F(n3735_5),
+ .I0(n3737_7),
+ .I1(n3735_42),
+ .I2(n3735_46)
+);
+defparam n3735_s2.INIT=8'h40;
+ LUT4 n3735_s3 (
+ .F(n3735_6),
+ .I0(score_counter[7]),
+ .I1(n3735_12),
+ .I2(n3735_13),
+ .I3(n3735_14)
+);
+defparam n3735_s3.INIT=16'h9669;
+ LUT4 n3735_s4 (
+ .F(n3735_7),
+ .I0(n3735_54),
+ .I1(n3735_40),
+ .I2(n3735_17),
+ .I3(n3735_18)
+);
+defparam n3735_s4.INIT=16'h6996;
+ LUT3 n3737_s1 (
+ .F(n3737_4),
+ .I0(n3737_36),
+ .I1(n3737_34),
+ .I2(score_counter[3])
+);
+defparam n3737_s1.INIT=8'hE0;
+ LUT4 n3737_s3 (
+ .F(n3737_6),
+ .I0(n3739_7),
+ .I1(n3737_32),
+ .I2(n3737_26),
+ .I3(n3737_24)
+);
+defparam n3737_s3.INIT=16'h0B74;
+ LUT4 n3737_s4 (
+ .F(n3737_7),
+ .I0(n3737_14),
+ .I1(n3737_24),
+ .I2(n3737_15),
+ .I3(n3737_16)
+);
+defparam n3737_s4.INIT=16'h4EB1;
+ LUT4 n3738_s1 (
+ .F(n3738_4),
+ .I0(n3738_5),
+ .I1(n3738_6),
+ .I2(score_counter[3]),
+ .I3(n3738_7)
+);
+defparam n3738_s1.INIT=16'h001F;
+ LUT4 n3739_s1 (
+ .F(n3739_4),
+ .I0(n3739_8),
+ .I1(n3735_48),
+ .I2(n3739_22),
+ .I3(n3739_10)
+);
+defparam n3739_s1.INIT=16'h1EE1;
+ LUT2 n3739_s3 (
+ .F(n3739_6),
+ .I0(score_counter[3]),
+ .I1(n3739_12)
+);
+defparam n3739_s3.INIT=4'h9;
+ LUT3 n3739_s4 (
+ .F(n3739_7),
+ .I0(n3739_13),
+ .I1(n3739_14),
+ .I2(n3739_15)
+);
+defparam n3739_s4.INIT=8'hB4;
+ LUT4 n3741_s1 (
+ .F(n3741_4),
+ .I0(n3741_8),
+ .I1(n3741_30),
+ .I2(bricks_active[15]),
+ .I3(n3741_26)
+);
+defparam n3741_s1.INIT=16'h4000;
+ LUT2 n3741_s2 (
+ .F(n3741_5),
+ .I0(n10654_4),
+ .I1(n10655_6)
+);
+defparam n3741_s2.INIT=4'h1;
+ LUT4 n3741_s3 (
+ .F(n3741_6),
+ .I0(n3741_11),
+ .I1(n3739_13),
+ .I2(n3741_12),
+ .I3(n3741_13)
+);
+defparam n3741_s3.INIT=16'h6996;
+ LUT4 n10654_s1 (
+ .F(n10654_4),
+ .I0(n10654_5),
+ .I1(n3741_30),
+ .I2(bricks_active[17]),
+ .I3(n10654_10)
+);
+defparam n10654_s1.INIT=16'hC080;
+ LUT3 n10657_s1 (
+ .F(n10657_4),
+ .I0(bricks_active[14]),
+ .I1(n3741_30),
+ .I2(n10657_5)
+);
+defparam n10657_s1.INIT=8'h80;
+ LUT4 n10658_s1 (
+ .F(n10658_4),
+ .I0(n10658_5),
+ .I1(n10658_6),
+ .I2(bricks_active[13]),
+ .I3(n3741_30)
);
-defparam n9048_s2.INIT=8'h35;
- LUT4 n9049_s1 (
- .F(n9049_4),
- .I0(n9049_6),
- .I1(qxb[7]),
+defparam n10658_s1.INIT=16'hE000;
+ LUT4 n10659_s1 (
+ .F(n10659_4),
+ .I0(bricks_active[12]),
+ .I1(n3741_30),
+ .I2(n10659_5),
+ .I3(n10659_10)
+);
+defparam n10659_s1.INIT=16'h0080;
+ LUT4 n10660_s1 (
+ .F(n10660_4),
+ .I0(n10654_5),
+ .I1(bricks_active[11]),
+ .I2(n10660_5),
+ .I3(n10654_10)
+);
+defparam n10660_s1.INIT=16'hC080;
+ LUT4 n10661_s1 (
+ .F(n10661_4),
+ .I0(bricks_active[10]),
+ .I1(n10660_5),
+ .I2(n10661_10),
+ .I3(n10661_6)
+);
+defparam n10661_s1.INIT=16'h8000;
+ LUT4 n10662_s1 (
+ .F(n10662_4),
+ .I0(n3741_8),
+ .I1(bricks_active[9]),
+ .I2(n3741_26),
+ .I3(n10660_5)
+);
+defparam n10662_s1.INIT=16'h4000;
+ LUT3 n10663_s1 (
+ .F(n10663_4),
+ .I0(bricks_active[8]),
+ .I1(n10660_5),
+ .I2(n10657_5)
+);
+defparam n10663_s1.INIT=8'h80;
+ LUT4 n10665_s1 (
+ .F(n10665_4),
+ .I0(bricks_active[6]),
+ .I1(n10660_5),
+ .I2(n10659_5),
+ .I3(n10659_10)
+);
+defparam n10665_s1.INIT=16'h0080;
+ LUT4 n10666_s1 (
+ .F(n10666_4),
+ .I0(n10654_5),
+ .I1(n10654_10),
+ .I2(bricks_active[5]),
+ .I3(n10667_4)
+);
+defparam n10666_s1.INIT=16'hE000;
+ LUT2 n10667_s1 (
+ .F(n10667_4),
+ .I0(n10667_6),
+ .I1(n10667_7)
+);
+defparam n10667_s1.INIT=4'h8;
+ LUT2 n10667_s2 (
+ .F(n10667_5),
+ .I0(n10661_10),
+ .I1(n10661_6)
+);
+defparam n10667_s2.INIT=4'h8;
+ LUT4 n10668_s1 (
+ .F(n10668_4),
+ .I0(n3741_8),
+ .I1(n10667_4),
+ .I2(bricks_active[3]),
+ .I3(n3741_26)
+);
+defparam n10668_s1.INIT=16'h4000;
+ LUT4 n10669_s1 (
+ .F(n10669_4),
+ .I0(n10669_5),
+ .I1(n10669_6),
.I2(qxb[8]),
- .I3(n9049_7)
-);
-defparam n9049_s1.INIT=16'h8000;
- LUT4 n9049_s2 (
- .F(n9049_5),
- .I0(n9049_8),
- .I1(n9049_9),
- .I2(n9049_10),
- .I3(n316_5)
-);
-defparam n9049_s2.INIT=16'hF800;
- LUT4 n9050_s1 (
- .F(n9050_4),
- .I0(qxb[7]),
- .I1(n9050_6),
- .I2(qxb[9]),
- .I3(qxb[8])
+ .I3(n10669_7)
);
-defparam n9050_s1.INIT=16'h0D00;
- LUT2 n9051_s1 (
- .F(n9051_4),
- .I0(frame_Z),
- .I1(n9051_5)
-);
-defparam n9051_s1.INIT=4'h8;
- LUT3 n9053_s1 (
- .F(n9053_4),
- .I0(n9053_5),
- .I1(bricks_active[12]),
- .I2(n9053_6)
-);
-defparam n9053_s1.INIT=8'h40;
- LUT4 n9054_s1 (
- .F(n9054_4),
- .I0(n9054_5),
- .I1(n9048_6),
- .I2(n9054_6),
- .I3(bricks_active[11])
-);
-defparam n9054_s1.INIT=16'h1000;
- LUT2 n9055_s1 (
- .F(n9055_4),
- .I0(n9054_5),
- .I1(n9054_6)
-);
-defparam n9055_s1.INIT=4'h4;
- LUT4 n9056_s1 (
- .F(n9056_4),
- .I0(n9054_5),
- .I1(n9050_4),
- .I2(bricks_active[9]),
- .I3(n9054_6)
-);
-defparam n9056_s1.INIT=16'h4000;
- LUT3 n9057_s1 (
- .F(n9057_4),
- .I0(n9054_5),
- .I1(bricks_active[8]),
- .I2(n9054_6)
-);
-defparam n9057_s1.INIT=8'h40;
- LUT4 n9059_s1 (
- .F(n9059_4),
- .I0(n9053_5),
- .I1(n9054_5),
- .I2(n9053_6),
- .I3(n9059_5)
-);
-defparam n9059_s1.INIT=16'h1000;
- LUT3 n9060_s1 (
- .F(n9060_4),
- .I0(n9048_6),
- .I1(n9061_4),
- .I2(bricks_active[5])
-);
-defparam n9060_s1.INIT=8'h40;
- LUT3 n9061_s1 (
- .F(n9061_4),
- .I0(qyb[6]),
- .I1(n317_9),
- .I2(n9061_5)
+defparam n10669_s1.INIT=16'hCA00;
+ LUT4 n10670_s1 (
+ .F(n10670_4),
+ .I0(n10658_5),
+ .I1(n10658_6),
+ .I2(bricks_active[1]),
+ .I3(n10667_4)
);
-defparam n9061_s1.INIT=8'h40;
- LUT4 n9064_s1 (
- .F(n9064_4),
- .I0(qyb[6]),
- .I1(bricks_active[1]),
- .I2(n317_9),
- .I3(n9061_5)
-);
-defparam n9064_s1.INIT=16'h4000;
- LUT4 n9065_s1 (
- .F(n9065_4),
- .I0(n9053_5),
+defparam n10670_s1.INIT=16'hE000;
+ LUT4 n10671_s1 (
+ .F(n10671_4),
+ .I0(n10659_10),
.I1(bricks_active[0]),
- .I2(n9053_6),
- .I3(n9061_4)
+ .I2(n10667_4),
+ .I3(n10659_5)
);
-defparam n9065_s1.INIT=16'h4000;
- LUT4 n11097_s1 (
- .F(n11097_4),
- .I0(n11097_8),
- .I1(bricks_active[4]),
- .I2(n11097_9),
- .I3(n11097_10)
+defparam n10671_s1.INIT=16'h4000;
+ LUT4 n12765_s1 (
+ .F(n12765_4),
+ .I0(n12765_8),
+ .I1(bricks_active[3]),
+ .I2(n12765_9),
+ .I3(n12765_10)
);
-defparam n11097_s1.INIT=16'h7000;
- LUT4 n11097_s2 (
- .F(n11097_5),
+defparam n12765_s1.INIT=16'h7000;
+ LUT4 n12765_s2 (
+ .F(n12765_5),
.I0(sy_Z[6]),
.I1(sy_Z[7]),
- .I2(n11097_49),
- .I3(n11097_51)
-);
-defparam n11097_s2.INIT=16'h0100;
- LUT4 n11097_s3 (
- .F(n11097_6),
- .I0(n11097_13),
- .I1(n11097_14),
- .I2(n11097_15),
- .I3(n11097_16)
-);
-defparam n11097_s3.INIT=16'h7F00;
- LUT4 n11097_s4 (
- .F(n11097_7),
- .I0(n11097_17),
- .I1(n11097_18),
- .I2(n11097_19),
- .I3(n11097_20)
-);
-defparam n11097_s4.INIT=16'h7F00;
- LUT4 qxb_9_s3 (
- .F(qxb_9_7),
- .I0(qyb[6]),
- .I1(qyb[5]),
- .I2(qyb[7]),
- .I3(qyb[8])
-);
-defparam qxb_9_s3.INIT=16'hE000;
+ .I2(n12765_11),
+ .I3(n12765_12)
+);
+defparam n12765_s2.INIT=16'h0100;
+ LUT4 n12765_s3 (
+ .F(n12765_6),
+ .I0(n12765_13),
+ .I1(n12765_14),
+ .I2(n12765_15),
+ .I3(n12765_16)
+);
+defparam n12765_s3.INIT=16'h7F00;
+ LUT4 n12765_s4 (
+ .F(n12765_7),
+ .I0(n12765_17),
+ .I1(n12765_18),
+ .I2(sy_Z[7]),
+ .I3(n12765_19)
+);
+defparam n12765_s4.INIT=16'h1000;
+ LUT2 n6878_s2 (
+ .F(n6878_5),
+ .I0(n6845),
+ .I1(n6843)
+);
+defparam n6878_s2.INIT=4'h1;
+ LUT4 n6925_s1 (
+ .F(n6925_4),
+ .I0(n6845),
+ .I1(n6847),
+ .I2(n6843),
+ .I3(n6846)
+);
+defparam n6925_s1.INIT=16'h0503;
+ LUT4 n6941_s1 (
+ .F(n6941_4),
+ .I0(n6848),
+ .I1(n6847),
+ .I2(n6845),
+ .I3(n6846)
+);
+defparam n6941_s1.INIT=16'hFBC5;
+ LUT3 n6948_s1 (
+ .F(n6948_4),
+ .I0(n6846),
+ .I1(n6845),
+ .I2(n6848)
+);
+defparam n6948_s1.INIT=8'h9E;
+ LUT4 n6950_s1 (
+ .F(n6950_4),
+ .I0(n6845),
+ .I1(n6848),
+ .I2(n6847),
+ .I3(n6846)
+);
+defparam n6950_s1.INIT=16'hEBF4;
+ LUT2 n7059_s4 (
+ .F(n7059_7),
+ .I0(n7054),
+ .I1(n7053)
+);
+defparam n7059_s4.INIT=4'h8;
+ LUT3 n7076_s2 (
+ .F(n7076_5),
+ .I0(n7054),
+ .I1(n7052),
+ .I2(n7053)
+);
+defparam n7076_s2.INIT=8'h10;
+ LUT4 n7106_s1 (
+ .F(n7106_4),
+ .I0(n7053),
+ .I1(n7055),
+ .I2(n7052),
+ .I3(n7054)
+);
+defparam n7106_s1.INIT=16'h0C0A;
+ LUT4 n7122_s1 (
+ .F(n7122_4),
+ .I0(n7055),
+ .I1(n7056),
+ .I2(n7054),
+ .I3(n7053)
+);
+defparam n7122_s1.INIT=16'hCB5F;
+ LUT3 n7129_s1 (
+ .F(n7129_4),
+ .I0(n7056),
+ .I1(n7054),
+ .I2(n7053)
+);
+defparam n7129_s1.INIT=8'h6B;
+ LUT4 n7131_s1 (
+ .F(n7131_4),
+ .I0(n7056),
+ .I1(n7053),
+ .I2(n7054),
+ .I3(n7055)
+);
+defparam n7131_s1.INIT=16'h4BF7;
+ LUT4 n7054_s13 (
+ .F(n7054_20),
+ .I0(score_counter[6]),
+ .I1(n7053),
+ .I2(score_counter[7]),
+ .I3(n7054_22)
+);
+defparam n7054_s13.INIT=16'hEF00;
+ LUT4 n7054_s14 (
+ .F(n7054_21),
+ .I0(score_counter[5]),
+ .I1(score_counter[4]),
+ .I2(score_counter[7]),
+ .I3(score_counter[6])
+);
+defparam n7054_s14.INIT=16'hDEBF;
+ LUT2 n7055_s20 (
+ .F(n7055_29),
+ .I0(score_counter[3]),
+ .I1(n7054)
+);
+defparam n7055_s20.INIT=4'h9;
+ LUT4 n7055_s21 (
+ .F(n7055_30),
+ .I0(n7054_21),
+ .I1(n7054),
+ .I2(score_counter[3]),
+ .I3(n7055_32)
+);
+defparam n7055_s21.INIT=16'hFA03;
+ LUT3 n7055_s22 (
+ .F(n7055_31),
+ .I0(n7055_33),
+ .I1(n7055_34),
+ .I2(score_counter[7])
+);
+defparam n7055_s22.INIT=8'h35;
+ LUT4 n7056_s21 (
+ .F(n7056_32),
+ .I0(score_counter[2]),
+ .I1(n7055_30),
+ .I2(n7056_33),
+ .I3(n7055_29)
+);
+defparam n7056_s21.INIT=16'hF0EE;
+ LUT4 n6944_s2 (
+ .F(n6944_6),
+ .I0(n6848),
+ .I1(n6845),
+ .I2(n6847),
+ .I3(n6846)
+);
+defparam n6944_s2.INIT=16'h313E;
+ LUT4 n6952_s2 (
+ .F(n6952_6),
+ .I0(n6848),
+ .I1(n6847),
+ .I2(n6846),
+ .I3(n6845)
+);
+defparam n6952_s2.INIT=16'h0371;
+ LUT4 n6958_s2 (
+ .F(n6958_6),
+ .I0(n6848),
+ .I1(n6845),
+ .I2(n6847),
+ .I3(n6846)
+);
+defparam n6958_s2.INIT=16'h233D;
+ LUT4 n7125_s2 (
+ .F(n7125_6),
+ .I0(n7056),
+ .I1(n7055),
+ .I2(n7054),
+ .I3(n7053)
+);
+defparam n7125_s2.INIT=16'h843F;
LUT3 square_s3 (
.F(square_7),
- .I0(square_11),
- .I1(square_12),
- .I2(square_13)
-);
-defparam square_s3.INIT=8'hB0;
- LUT4 square_s6 (
- .F(square_10),
- .I0(square_15),
+ .I0(square_10),
.I1(qx[9]),
- .I2(sx_Z[9]),
- .I3(square_16)
+ .I2(square_11)
);
-defparam square_s6.INIT=16'hEF00;
- LUT4 ball_s3 (
- .F(ball_7),
- .I0(sx_Z[7]),
- .I1(ball_10),
- .I2(ball_11),
- .I3(ball_12)
+defparam square_s3.INIT=8'h23;
+ LUT4 square_s4 (
+ .F(square_8),
+ .I0(square_12),
+ .I1(qx[8]),
+ .I2(square_10),
+ .I3(square_11)
+);
+defparam square_s4.INIT=16'h00F1;
+ LUT4 square_s5 (
+ .F(square_9),
+ .I0(sy_Z[7]),
+ .I1(square_13),
+ .I2(sy_Z[9]),
+ .I3(n4162_42)
);
-defparam ball_s3.INIT=16'h004D;
- LUT4 ball_s4 (
+defparam square_s5.INIT=16'hF800;
+ LUT2 ball_s4 (
.F(ball_8),
.I0(qxb[9]),
- .I1(n9048_7),
- .I2(sx_Z[9]),
- .I3(ball_13)
+ .I1(sx_Z[9])
);
-defparam ball_s4.INIT=16'h0071;
- LUT4 ball_s5 (
+defparam ball_s4.INIT=4'h4;
+ LUT3 ball_s5 (
.F(ball_9),
- .I0(qxb[9]),
- .I1(n9048_7),
- .I2(sx_Z[9]),
- .I3(n3728_42)
+ .I0(ball_14),
+ .I1(qxb[8]),
+ .I2(ball_15)
+);
+defparam ball_s5.INIT=8'h0E;
+ LUT2 score_area_1_s3 (
+ .F(score_area_1_7),
+ .I0(sx_Z[4]),
+ .I1(sx_Z[5])
+);
+defparam score_area_1_s3.INIT=4'h1;
+ LUT4 score_area_1_s4 (
+ .F(score_area_1_8),
+ .I0(sy_Z[7]),
+ .I1(sy_Z[8]),
+ .I2(sy_Z[9]),
+ .I3(score_area_1_9)
);
-defparam ball_s5.INIT=16'hEF00;
+defparam score_area_1_s4.INIT=16'h0100;
LUT4 qx_9_s3 (
.F(qx_9_7),
.I0(qx[3]),
@@ -3678,56 +4945,94 @@ defparam ball_s5.INIT=16'hEF00;
defparam qx_9_s3.INIT=16'h1000;
LUT3 qdx_s3 (
.F(qdx_7),
- .I0(n191_6),
+ .I0(n191_9),
.I1(qdx),
- .I2(n190_5)
+ .I2(n190_4)
);
defparam qdx_s3.INIT=8'h0B;
- LUT4 n3741_s27 (
- .F(n3741_34),
- .I0(n3741_36),
- .I1(n3741_37),
- .I2(n3741_38),
- .I3(n3741_39)
-);
-defparam n3741_s27.INIT=16'h001F;
- LUT3 n3741_s28 (
- .F(n3741_35),
- .I0(qyb[7]),
- .I1(qyb[8]),
- .I2(n3741_59)
+ LUT4 qyb_9_s3 (
+ .F(qyb_9_7),
+ .I0(n3744_10),
+ .I1(n3744_64),
+ .I2(n3744_12),
+ .I3(qyb_9_8)
+);
+defparam qyb_9_s3.INIT=16'hBF00;
+ LUT4 n4207_s27 (
+ .F(n4207_34),
+ .I0(sy_Z[9]),
+ .I1(qyb[9]),
+ .I2(qyb[8]),
+ .I3(n4207_38)
);
-defparam n3741_s28.INIT=8'h80;
- LUT3 qdy_s4 (
- .F(qdy_8),
- .I0(qdy),
+defparam n4207_s27.INIT=16'hD4DD;
+ LUT3 n4207_s28 (
+ .F(n4207_35),
+ .I0(sy_Z[8]),
+ .I1(qyb[7]),
+ .I2(n4207_70)
+);
+defparam n4207_s28.INIT=8'h40;
+ LUT2 n4207_s29 (
+ .F(n4207_36),
+ .I0(n4207_38),
+ .I1(qyb[8])
+);
+defparam n4207_s29.INIT=4'h4;
+ LUT4 n4207_s30 (
+ .F(n4207_37),
+ .I0(sy_Z[9]),
.I1(qyb[9]),
- .I2(qxb_9_7)
+ .I2(n4207_40),
+ .I3(sy_Z[8])
);
-defparam qdy_s4.INIT=8'h01;
- LUT4 qdy_s5 (
- .F(qdy_9),
- .I0(qdy_10),
- .I1(n3294_15),
- .I2(n3294_16),
- .I3(frame_Z)
+defparam n4207_s30.INIT=16'hD4DD;
+ LUT4 n6847_s6 (
+ .F(n6847_11),
+ .I0(n6846_14),
+ .I1(n6846_12),
+ .I2(n6843_22),
+ .I3(score_counter[1])
+);
+defparam n6847_s6.INIT=16'h3FC8;
+ LUT4 n7272_s78 (
+ .F(n7272_108),
+ .I0(n7272_112),
+ .I1(sx_Z[1]),
+ .I2(sx_Z[3]),
+ .I3(n7272_113)
+);
+defparam n7272_s78.INIT=16'h0070;
+ LUT4 n7272_s79 (
+ .F(n7272_109),
+ .I0(n7272_100),
+ .I1(sx_Z[2]),
+ .I2(sx_Z[3]),
+ .I3(n7272_114)
+);
+defparam n7272_s79.INIT=16'h0E00;
+ LUT4 n7421_s73 (
+ .F(n7421_102),
+ .I0(sx_Z[1]),
+ .I1(sx_Z[3]),
+ .I2(n7421_103),
+ .I3(n7421_104)
);
-defparam qdy_s5.INIT=16'h7F00;
- LUT3 n3710_s34 (
- .F(n3710_47),
- .I0(n3710_48),
+defparam n7421_s73.INIT=16'h7F00;
+ LUT3 n4176_s34 (
+ .F(n4176_47),
+ .I0(n4176_50),
.I1(sy_Z[5]),
.I2(sy_Z[6])
);
-defparam n3710_s34.INIT=8'h0B;
- LUT4 n367_s5 (
+defparam n4176_s34.INIT=8'h0B;
+ LUT3 n367_s5 (
.F(n367_9),
- .I0(n316_6),
- .I1(n317_9),
- .I2(qdy),
- .I3(n317_8)
+ .I0(n3744_8),
+ .I1(qdy),
+ .I2(n319_9)
);
-defparam n367_s5.INIT=16'h008F;
+defparam n367_s5.INIT=8'h0E;
LUT3 n365_s4 (
.F(n365_8),
.I0(qdy),
@@ -3745,26 +5050,28 @@ defparam n365_s4.INIT=8'hBD;
defparam n364_s4.INIT=16'hE007;
LUT4 n362_s4 (
.F(n362_8),
- .I0(qyb[4]),
- .I1(n319_5),
- .I2(n316_8),
- .I3(qdy)
+ .I0(n319_6),
+ .I1(qdy),
+ .I2(n317_7),
+ .I3(qyb[4])
);
defparam n362_s4.INIT=16'h0F77;
- LUT2 n358_s5 (
+ LUT4 n358_s5 (
.F(n358_9),
- .I0(qdy),
- .I1(qyb[9])
-);
-defparam n358_s5.INIT=4'h8;
- LUT4 n3881_s2 (
- .F(n3881_6),
- .I0(sx_Z[7]),
- .I1(sx_Z[8]),
- .I2(sx_Z[9]),
- .I3(n3881_7)
+ .I0(qyb[7]),
+ .I1(qyb[8]),
+ .I2(n319_6),
+ .I3(n315_11)
+);
+defparam n358_s5.INIT=16'h1000;
+ LUT4 n4347_s2 (
+ .F(n4347_6),
+ .I0(n4347_7),
+ .I1(n4347_8),
+ .I2(sx_Z[6]),
+ .I3(n4347_9)
);
-defparam n3881_s2.INIT=16'h0100;
+defparam n4347_s2.INIT=16'hBC00;
LUT3 n160_s3 (
.F(n160_7),
.I0(qdx),
@@ -3780,33 +5087,83 @@ defparam n160_s3.INIT=8'hBD;
.I3(qxb[2])
);
defparam n159_s3.INIT=16'hE007;
- LUT3 n155_s3 (
- .F(n155_7),
- .I0(qdx),
- .I1(n192_4),
- .I2(n155_8)
+ LUT4 n155_s3 (
+ .F(n155_20),
+ .I0(n192_4),
+ .I1(n155_21),
+ .I2(n155_24),
+ .I3(qdx)
);
-defparam n155_s3.INIT=8'h40;
- LUT2 n187_s3 (
+defparam n155_s3.INIT=16'h0F77;
+ LUT4 n6843_s17 (
+ .F(n6843_22),
+ .I0(n6843_23),
+ .I1(n6843_24),
+ .I2(score_counter[6]),
+ .I3(n6846_14)
+);
+defparam n6843_s17.INIT=16'h2221;
+ LUT4 n6846_s6 (
+ .F(n6846_12),
+ .I0(n6846_15),
+ .I1(n6846_16),
+ .I2(n6846_17),
+ .I3(score_counter[7])
+);
+defparam n6846_s6.INIT=16'h0C0A;
+ LUT4 n6846_s7 (
+ .F(n6846_13),
+ .I0(score_counter[0]),
+ .I1(score_counter[1]),
+ .I2(n6843_22),
+ .I3(n6846_12)
+);
+defparam n6846_s7.INIT=16'hBD88;
+ LUT4 n6846_s8 (
+ .F(n6846_14),
+ .I0(n6846_18),
+ .I1(score_counter[4]),
+ .I2(score_counter[2]),
+ .I3(n6846_19)
+);
+defparam n6846_s8.INIT=16'h007D;
+ LUT4 n6845_s6 (
+ .F(n6845_12),
+ .I0(n6843_22),
+ .I1(n6846_12),
+ .I2(score_counter[1]),
+ .I3(score_counter[0])
+);
+defparam n6845_s6.INIT=16'hBCC0;
+ LUT4 n187_s3 (
.F(n187_6),
.I0(qxb[4]),
- .I1(n192_9)
+ .I1(qxb[5]),
+ .I2(qxb[6]),
+ .I3(qxb[7])
+);
+defparam n187_s3.INIT=16'h8000;
+ LUT3 n187_s4 (
+ .F(n187_7),
+ .I0(qxb[4]),
+ .I1(qxb[5]),
+ .I2(n191_6)
);
-defparam n187_s3.INIT=4'h4;
+defparam n187_s4.INIT=8'h10;
LUT4 n190_s4 (
.F(n190_7),
- .I0(n192_4),
- .I1(qxb[4]),
- .I2(qxb[6]),
- .I3(qxb[5])
+ .I0(qxb[8]),
+ .I1(ball_43),
+ .I2(n190_10),
+ .I3(qxb[7])
);
-defparam n190_s4.INIT=16'hE000;
+defparam n190_s4.INIT=16'h80FE;
LUT2 n190_s5 (
.F(n190_8),
- .I0(qxb[7]),
- .I1(qxb[8])
+ .I0(qxb[4]),
+ .I1(qxb[5])
);
-defparam n190_s5.INIT=4'h1;
+defparam n190_s5.INIT=4'h8;
LUT3 n190_s6 (
.F(n190_9),
.I0(qxb[7]),
@@ -3816,392 +5173,543 @@ defparam n190_s5.INIT=4'h1;
defparam n190_s6.INIT=8'h01;
LUT4 n191_s3 (
.F(n191_6),
- .I0(qxb[5]),
- .I1(qxb[6]),
- .I2(n187_6),
- .I3(n190_9)
+ .I0(qxb[1]),
+ .I1(qxb[0]),
+ .I2(qxb[2]),
+ .I3(qxb[3])
);
-defparam n191_s3.INIT=16'h1000;
- LUT4 n316_s5 (
- .F(n316_8),
- .I0(n316_9),
+defparam n191_s3.INIT=16'h001F;
+ LUT4 n315_s4 (
+ .F(n315_7),
+ .I0(n317_10),
.I1(qyb[2]),
- .I2(qyb[3]),
- .I3(qyb[4])
+ .I2(n315_9),
+ .I3(n317_6)
);
-defparam n316_s5.INIT=16'h000B;
- LUT3 n317_s6 (
- .F(n317_9),
- .I0(qyb[7]),
- .I1(qyb[8]),
- .I2(qyb[9])
+defparam n315_s4.INIT=16'hE000;
+ LUT2 n316_s4 (
+ .F(n316_7),
+ .I0(qyb[8]),
+ .I1(qyb[9])
);
-defparam n317_s6.INIT=8'h01;
+defparam n316_s4.INIT=4'h1;
LUT2 n317_s7 (
.F(n317_10),
- .I0(qyb[4]),
- .I1(qyb[5])
+ .I0(qyb[0]),
+ .I1(qyb[1])
);
defparam n317_s7.INIT=4'h8;
- LUT4 n319_s4 (
- .F(n319_7),
- .I0(n316_9),
- .I1(qyb[2]),
- .I2(qyb[3]),
- .I3(qyb[4])
-);
-defparam n319_s4.INIT=16'h0BF4;
- LUT4 n3294_s7 (
- .F(n3294_10),
- .I0(qxb[6]),
- .I1(n3294_17),
- .I2(n3294_18),
- .I3(n3294_19)
-);
-defparam n3294_s7.INIT=16'h004D;
- LUT4 n3294_s8 (
- .F(n3294_11),
- .I0(qxb[7]),
- .I1(n3294_20),
- .I2(qxb[8]),
- .I3(square_14)
-);
-defparam n3294_s8.INIT=16'h0BB0;
- LUT4 n3294_s9 (
- .F(n3294_12),
- .I0(n3294_64),
- .I1(n3294_22),
- .I2(n3294_23),
- .I3(n3294_24)
-);
-defparam n3294_s9.INIT=16'h004F;
- LUT4 n3294_s10 (
- .F(n3294_13),
- .I0(qx[9]),
- .I1(n3294_25),
- .I2(n3294_26),
- .I3(n3294_27)
+ LUT4 n3744_s7 (
+ .F(n3744_10),
+ .I0(qx[8]),
+ .I1(n3744_18),
+ .I2(n3744_19),
+ .I3(n3744_20)
);
-defparam n3294_s10.INIT=16'h0B00;
- LUT3 n3294_s11 (
- .F(n3294_14),
- .I0(qyb[5]),
- .I1(qyb[4]),
- .I2(qyb[8])
+defparam n3744_s7.INIT=16'h8E00;
+ LUT4 n3744_s9 (
+ .F(n3744_12),
+ .I0(square_11),
+ .I1(qx[9]),
+ .I2(n3744_22),
+ .I3(qxb[9])
);
-defparam n3294_s11.INIT=8'hE0;
- LUT4 n3294_s12 (
- .F(n3294_15),
- .I0(n3294_28),
- .I1(n3294_29),
- .I2(n3294_30),
- .I3(n3294_31)
-);
-defparam n3294_s12.INIT=16'h0001;
- LUT4 n3294_s13 (
- .F(n3294_16),
- .I0(n3294_32),
- .I1(n3294_33),
- .I2(n3294_34),
- .I3(n3294_35)
-);
-defparam n3294_s13.INIT=16'h1000;
- LUT4 n9048_s3 (
- .F(n9048_6),
- .I0(n192_7),
- .I1(qxb[2]),
- .I2(qxb[3]),
- .I3(n155_8)
+defparam n3744_s9.INIT=16'hCAFC;
+ LUT2 n3744_s10 (
+ .F(n3744_13),
+ .I0(qyb[4]),
+ .I1(qyb[5])
);
-defparam n9048_s3.INIT=16'h0B00;
- LUT4 n9048_s4 (
- .F(n9048_7),
- .I0(n9048_9),
- .I1(qxb[8]),
- .I2(n155_8),
- .I3(qxb[7])
+defparam n3744_s10.INIT=4'h1;
+ LUT2 n3744_s11 (
+ .F(n3744_14),
+ .I0(qyb[7]),
+ .I1(qyb[8])
+);
+defparam n3744_s11.INIT=4'h8;
+ LUT3 n3744_s14 (
+ .F(n3744_17),
+ .I0(n10668_4),
+ .I1(n3744_27),
+ .I2(n10669_4)
+);
+defparam n3744_s14.INIT=8'h01;
+ LUT4 n3735_s5 (
+ .F(n3735_8),
+ .I0(score_counter[4]),
+ .I1(n3735_19),
+ .I2(score_counter[5]),
+ .I3(n3735_20)
+);
+defparam n3735_s5.INIT=16'hA5C3;
+ LUT4 n3735_s9 (
+ .F(n3735_12),
+ .I0(n3735_33),
+ .I1(n3735_40),
+ .I2(n3735_52),
+ .I3(n3735_23)
+);
+defparam n3735_s9.INIT=16'h00DF;
+ LUT3 n3735_s10 (
+ .F(n3735_13),
+ .I0(n3737_4),
+ .I1(n3735_24),
+ .I2(n3735_50)
+);
+defparam n3735_s10.INIT=8'h13;
+ LUT4 n3735_s11 (
+ .F(n3735_14),
+ .I0(n3735_26),
+ .I1(n3735_40),
+ .I2(n3735_27),
+ .I3(score_counter[6])
+);
+defparam n3735_s11.INIT=16'hAC00;
+ LUT4 n3735_s14 (
+ .F(n3735_17),
+ .I0(n3735_31),
+ .I1(n3737_6),
+ .I2(score_counter[3]),
+ .I3(score_counter[5])
+);
+defparam n3735_s14.INIT=16'h1000;
+ LUT4 n3735_s15 (
+ .F(n3735_18),
+ .I0(n3735_32),
+ .I1(n3739_6),
+ .I2(n3739_22),
+ .I3(n3735_26)
+);
+defparam n3735_s15.INIT=16'h0100;
+ LUT2 n3737_s7 (
+ .F(n3737_10),
+ .I0(score_counter[3]),
+ .I1(score_counter[2])
+);
+defparam n3737_s7.INIT=4'h8;
+ LUT4 n3737_s11 (
+ .F(n3737_14),
+ .I0(n3739_7),
+ .I1(n3737_30),
+ .I2(n3737_20),
+ .I3(n3737_21)
+);
+defparam n3737_s11.INIT=16'hBF00;
+ LUT3 n3737_s12 (
+ .F(n3737_15),
+ .I0(n3737_24),
+ .I1(n3739_7),
+ .I2(n3737_22)
+);
+defparam n3737_s12.INIT=8'h10;
+ LUT3 n3737_s13 (
+ .F(n3737_16),
+ .I0(n3735_20),
+ .I1(n3735_28),
+ .I2(n3735_8)
+);
+defparam n3737_s13.INIT=8'hB4;
+ LUT4 n3738_s2 (
+ .F(n3738_5),
+ .I0(n3737_17),
+ .I1(n10663_4),
+ .I2(n3738_8),
+ .I3(n3739_7)
+);
+defparam n3738_s2.INIT=16'h00F8;
+ LUT4 n3738_s3 (
+ .F(n3738_6),
+ .I0(score_counter[2]),
+ .I1(n3744_27),
+ .I2(n3739_13),
+ .I3(score_counter[0])
+);
+defparam n3738_s3.INIT=16'h0800;
+ LUT3 n3738_s4 (
+ .F(n3738_7),
+ .I0(n3738_11),
+ .I1(n10666_4),
+ .I2(n3735_33)
+);
+defparam n3738_s4.INIT=8'hE0;
+ LUT3 n3739_s5 (
+ .F(n3739_8),
+ .I0(n3741_14),
+ .I1(n10659_4),
+ .I2(score_counter[1])
+);
+defparam n3739_s5.INIT=8'h80;
+ LUT4 n3739_s7 (
+ .F(n3739_10),
+ .I0(n10655_6),
+ .I1(n3741_4),
+ .I2(n3741_6),
+ .I3(n3741_14)
+);
+defparam n3739_s7.INIT=16'hE000;
+ LUT4 n3739_s9 (
+ .F(n3739_12),
+ .I0(n3739_13),
+ .I1(n3739_14),
+ .I2(score_counter[2]),
+ .I3(n3739_15)
+);
+defparam n3739_s9.INIT=16'hF040;
+ LUT4 n3739_s10 (
+ .F(n3739_13),
+ .I0(n3739_17),
+ .I1(n10667_4),
+ .I2(n10659_5),
+ .I3(score_counter[1])
+);
+defparam n3739_s10.INIT=16'h807F;
+ LUT4 n3739_s11 (
+ .F(n3739_14),
+ .I0(n3744_27),
+ .I1(n10669_4),
+ .I2(n10668_4),
+ .I3(score_counter[0])
+);
+defparam n3739_s11.INIT=16'hFE00;
+ LUT4 n3739_s12 (
+ .F(n3739_15),
+ .I0(n3744_24),
+ .I1(n3744_23),
+ .I2(n3739_24),
+ .I3(score_counter[2])
+);
+defparam n3739_s12.INIT=16'hE01F;
+ LUT4 n3741_s5 (
+ .F(n3741_8),
+ .I0(n190_8),
+ .I1(n3741_15),
+ .I2(qxb[7]),
+ .I3(qxb[6])
);
-defparam n9048_s4.INIT=16'h4000;
- LUT4 n9048_s5 (
- .F(n9048_8),
+defparam n3741_s5.INIT=16'h000D;
+ LUT3 n3741_s8 (
+ .F(n3741_11),
+ .I0(n10658_4),
+ .I1(n3741_19),
+ .I2(n10657_4)
+);
+defparam n3741_s8.INIT=8'hB2;
+ LUT4 n3741_s9 (
+ .F(n3741_12),
+ .I0(n3741_20),
+ .I1(n3744_17),
+ .I2(score_counter[0]),
+ .I3(n3741_21)
+);
+defparam n3741_s9.INIT=16'h008F;
+ LUT4 n3741_s10 (
+ .F(n3741_13),
+ .I0(n10659_4),
+ .I1(n3741_22),
+ .I2(n3741_23),
+ .I3(n3741_19)
+);
+defparam n3741_s10.INIT=16'h00FB;
+ LUT3 n3741_s11 (
+ .F(n3741_14),
+ .I0(n3744_68),
+ .I1(n3744_27),
+ .I2(n3741_19)
+);
+defparam n3741_s11.INIT=8'hE1;
+ LUT4 n10654_s2 (
+ .F(n10654_5),
.I0(qxb[4]),
- .I1(n9048_10),
- .I2(qxb[6]),
- .I3(n190_8)
-);
-defparam n9048_s5.INIT=16'h4F00;
- LUT4 n9049_s3 (
- .F(n9049_6),
- .I0(qxb[9]),
- .I1(qxb[5]),
+ .I1(n10654_7),
.I2(qxb[6]),
- .I3(qxb[4])
+ .I3(n10654_8)
);
-defparam n9049_s3.INIT=16'h1554;
- LUT4 n9049_s4 (
- .F(n9049_7),
- .I0(qxb[0]),
- .I1(n9049_11),
- .I2(qxb[5]),
- .I3(qxb[6])
-);
-defparam n9049_s4.INIT=16'hDFF3;
- LUT2 n9049_s5 (
- .F(n9049_8),
- .I0(qyb[5]),
- .I1(qyb[6])
-);
-defparam n9049_s5.INIT=4'h8;
- LUT4 n9049_s6 (
- .F(n9049_9),
- .I0(qyb[2]),
- .I1(qyb[3]),
- .I2(qyb[7]),
- .I3(qyb[4])
-);
-defparam n9049_s6.INIT=16'h0E00;
- LUT3 n9049_s7 (
- .F(n9049_10),
- .I0(qyb[5]),
- .I1(qyb[6]),
- .I2(qyb[7])
+defparam n10654_s2.INIT=16'h4F00;
+ LUT4 n10657_s2 (
+ .F(n10657_5),
+ .I0(n10669_5),
+ .I1(n10669_6),
+ .I2(qxb[9]),
+ .I3(qxb[8])
);
-defparam n9049_s7.INIT=8'h10;
- LUT3 n9050_s3 (
- .F(n9050_6),
- .I0(qxb[4]),
- .I1(qxb[5]),
- .I2(qxb[6])
+defparam n10657_s2.INIT=16'h0C0A;
+ LUT4 n10658_s2 (
+ .F(n10658_5),
+ .I0(qxb[5]),
+ .I1(n10658_7),
+ .I2(qxb[6]),
+ .I3(n10658_8)
);
-defparam n9050_s3.INIT=8'h01;
- LUT3 n9050_s4 (
- .F(n9050_7),
- .I0(n9050_8),
- .I1(n9050_9),
- .I2(ball_11)
-);
-defparam n9050_s4.INIT=8'hE0;
- LUT4 n9051_s2 (
- .F(n9051_5),
- .I0(n9050_9),
- .I1(qxb[7]),
- .I2(qxb[9]),
- .I3(n9051_6)
-);
-defparam n9051_s2.INIT=16'h000E;
- LUT3 n9052_s2 (
- .F(n9052_5),
- .I0(n9052_6),
- .I1(n9052_7),
- .I2(n9052_8)
-);
-defparam n9052_s2.INIT=8'h20;
- LUT4 n9053_s2 (
- .F(n9053_5),
+defparam n10658_s2.INIT=16'h1F00;
+ LUT4 n10658_s3 (
+ .F(n10658_6),
.I0(qxb[3]),
- .I1(qxb[2]),
- .I2(n9053_7),
- .I3(n155_8)
+ .I1(n190_9),
+ .I2(n155_21),
+ .I3(n10658_9)
);
-defparam n9053_s2.INIT=16'hFE00;
- LUT4 n9053_s3 (
- .F(n9053_6),
+defparam n10658_s3.INIT=16'h0080;
+ LUT4 n10659_s2 (
+ .F(n10659_5),
.I0(qxb[5]),
.I1(qxb[6]),
- .I2(n9053_8),
+ .I2(n10659_7),
.I3(n190_9)
);
-defparam n9053_s3.INIT=16'hFE00;
- LUT4 n9054_s2 (
- .F(n9054_5),
- .I0(qyb[1]),
- .I1(qyb[3]),
- .I2(qyb[4]),
- .I3(n9054_7)
+defparam n10659_s2.INIT=16'hFE00;
+ LUT4 n10660_s2 (
+ .F(n10660_5),
+ .I0(n10660_6),
+ .I1(qyb[4]),
+ .I2(qyb[5]),
+ .I3(n10660_7)
);
-defparam n9054_s2.INIT=16'h0100;
- LUT4 n9054_s3 (
- .F(n9054_6),
- .I0(n317_10),
- .I1(n9054_8),
- .I2(n317_9),
- .I3(qyb[6])
+defparam n10660_s2.INIT=16'h2D00;
+ LUT4 n10661_s3 (
+ .F(n10661_6),
+ .I0(n10661_7),
+ .I1(n10661_8),
+ .I2(qxb[5]),
+ .I3(qxb[6])
);
-defparam n9054_s3.INIT=16'h1000;
- LUT4 n9059_s2 (
- .F(n9059_5),
- .I0(n317_10),
- .I1(n9054_8),
- .I2(n317_9),
- .I3(n9059_6)
+defparam n10661_s3.INIT=16'h3FFA;
+ LUT3 n10664_s2 (
+ .F(n10664_5),
+ .I0(n10658_5),
+ .I1(n10658_6),
+ .I2(bricks_active[7])
+);
+defparam n10664_s2.INIT=8'hE0;
+ LUT4 n10667_s3 (
+ .F(n10667_6),
+ .I0(qyb[6]),
+ .I1(qyb[7]),
+ .I2(qyb[8]),
+ .I3(qyb[9])
);
-defparam n9059_s2.INIT=16'h1000;
- LUT4 n9061_s2 (
- .F(n9061_5),
+defparam n10667_s3.INIT=16'h0001;
+ LUT4 n10667_s4 (
+ .F(n10667_7),
.I0(qyb[3]),
.I1(qyb[2]),
.I2(qyb[5]),
.I3(qyb[4])
);
-defparam n9061_s2.INIT=16'h7FF0;
- LUT4 n11097_s5 (
- .F(n11097_8),
- .I0(sx_Z[9]),
- .I1(n11097_21),
- .I2(sx_Z[7]),
- .I3(sx_Z[8])
-);
-defparam n11097_s5.INIT=16'h4000;
- LUT4 n11097_s6 (
- .F(n11097_9),
- .I0(n11097_22),
- .I1(bricks_active[5]),
- .I2(bricks_active[1]),
- .I3(n11097_23)
+defparam n10667_s4.INIT=16'h7FF0;
+ LUT4 n10669_s2 (
+ .F(n10669_5),
+ .I0(qxb[5]),
+ .I1(n10669_8),
+ .I2(qxb[6]),
+ .I3(qxb[7])
);
-defparam n11097_s6.INIT=16'h0777;
- LUT4 n11097_s7 (
- .F(n11097_10),
- .I0(n11097_24),
- .I1(bricks_active[3]),
- .I2(bricks_active[2]),
- .I3(n11097_25)
+defparam n10669_s2.INIT=16'hE000;
+ LUT4 n10669_s3 (
+ .F(n10669_6),
+ .I0(n10669_9),
+ .I1(n190_8),
+ .I2(qxb[6]),
+ .I3(qxb[7])
);
-defparam n11097_s7.INIT=16'h0777;
- LUT4 n11097_s10 (
- .F(n11097_13),
- .I0(n11097_24),
- .I1(bricks_active[9]),
- .I2(bricks_active[8]),
- .I3(n11097_25)
+defparam n10669_s3.INIT=16'h000B;
+ LUT4 n10669_s4 (
+ .F(n10669_7),
+ .I0(qxb[9]),
+ .I1(bricks_active[2]),
+ .I2(n10667_6),
+ .I3(n10667_7)
);
-defparam n11097_s10.INIT=16'h0777;
- LUT4 n11097_s11 (
- .F(n11097_14),
- .I0(n11097_23),
- .I1(bricks_active[7]),
- .I2(bricks_active[6]),
- .I3(n3881_6)
+defparam n10669_s4.INIT=16'h4000;
+ LUT3 n12765_s5 (
+ .F(n12765_8),
+ .I0(sx_Z[9]),
+ .I1(n12765_20),
+ .I2(sx_Z[8])
+);
+defparam n12765_s5.INIT=8'h10;
+ LUT4 n12765_s6 (
+ .F(n12765_9),
+ .I0(n12765_21),
+ .I1(bricks_active[5]),
+ .I2(bricks_active[1]),
+ .I3(n12765_22)
+);
+defparam n12765_s6.INIT=16'h0777;
+ LUT4 n12765_s7 (
+ .F(n12765_10),
+ .I0(n12765_23),
+ .I1(bricks_active[4]),
+ .I2(n12765_24),
+ .I3(bricks_active[2])
+);
+defparam n12765_s7.INIT=16'h7077;
+ LUT4 n12765_s8 (
+ .F(n12765_11),
+ .I0(sy_Z[1]),
+ .I1(sy_Z[4]),
+ .I2(n7272_111),
+ .I3(sy_Z[5])
+);
+defparam n12765_s8.INIT=16'hC07F;
+ LUT2 n12765_s9 (
+ .F(n12765_12),
+ .I0(sy_Z[8]),
+ .I1(sy_Z[9])
);
-defparam n11097_s11.INIT=16'h0777;
- LUT4 n11097_s12 (
- .F(n11097_15),
- .I0(n11097_22),
+defparam n12765_s9.INIT=4'h1;
+ LUT4 n12765_s10 (
+ .F(n12765_13),
+ .I0(n12765_23),
+ .I1(bricks_active[10]),
+ .I2(n12765_24),
+ .I3(bricks_active[8])
+);
+defparam n12765_s10.INIT=16'h7077;
+ LUT4 n12765_s11 (
+ .F(n12765_14),
+ .I0(n12765_21),
.I1(bricks_active[11]),
- .I2(bricks_active[10]),
- .I3(n11097_8)
+ .I2(bricks_active[7]),
+ .I3(n12765_22)
);
-defparam n11097_s12.INIT=16'h0777;
- LUT4 n11097_s13 (
- .F(n11097_16),
- .I0(sy_Z[7]),
- .I1(sy_Z[6]),
- .I2(n11097_30),
- .I3(n11097_29)
+defparam n12765_s11.INIT=16'h0777;
+ LUT4 n12765_s12 (
+ .F(n12765_15),
+ .I0(n12765_8),
+ .I1(bricks_active[9]),
+ .I2(bricks_active[6]),
+ .I3(n4347_6)
);
-defparam n11097_s13.INIT=16'h0400;
- LUT4 n11097_s14 (
- .F(n11097_17),
- .I0(bricks_active[12]),
- .I1(n3881_6),
- .I2(n11097_31),
- .I3(n11097_32)
-);
-defparam n11097_s14.INIT=16'h0777;
- LUT4 n11097_s15 (
- .F(n11097_18),
- .I0(n11097_22),
- .I1(bricks_active[17]),
- .I2(bricks_active[14]),
- .I3(n11097_25)
+defparam n12765_s12.INIT=16'h0777;
+ LUT4 n12765_s13 (
+ .F(n12765_16),
+ .I0(n4176_50),
+ .I1(sy_Z[4]),
+ .I2(sy_Z[5]),
+ .I3(n12765_25)
);
-defparam n11097_s15.INIT=16'h0777;
- LUT4 n11097_s16 (
- .F(n11097_19),
- .I0(n11097_8),
- .I1(bricks_active[16]),
- .I2(bricks_active[15]),
- .I3(n11097_24)
+defparam n12765_s13.INIT=16'hAC00;
+ LUT4 n12765_s14 (
+ .F(n12765_17),
+ .I0(sy_Z[1]),
+ .I1(sy_Z[2]),
+ .I2(sy_Z[3]),
+ .I3(sy_Z[4])
);
-defparam n11097_s16.INIT=16'h0777;
- LUT4 n11097_s17 (
- .F(n11097_20),
- .I0(n11097_33),
- .I1(sy_Z[7]),
- .I2(n11097_27),
- .I3(n11097_29)
+defparam n12765_s14.INIT=16'h0001;
+ LUT4 n12765_s15 (
+ .F(n12765_18),
+ .I0(n12765_8),
+ .I1(bricks_active[15]),
+ .I2(n12765_26),
+ .I3(n12765_27)
+);
+defparam n12765_s15.INIT=16'h7000;
+ LUT4 n12765_s16 (
+ .F(n12765_19),
+ .I0(sy_Z[5]),
+ .I1(sy_Z[6]),
+ .I2(sy_Z[8]),
+ .I3(sy_Z[9])
+);
+defparam n12765_s16.INIT=16'h0001;
+ LUT3 n7054_s15 (
+ .F(n7054_22),
+ .I0(score_counter[4]),
+ .I1(score_counter[3]),
+ .I2(n7053)
+);
+defparam n7054_s15.INIT=8'h17;
+ LUT2 n7055_s23 (
+ .F(n7055_32),
+ .I0(score_counter[4]),
+ .I1(n7053)
+);
+defparam n7055_s23.INIT=4'h6;
+ LUT4 n7055_s24 (
+ .F(n7055_33),
+ .I0(score_counter[5]),
+ .I1(n7053),
+ .I2(score_counter[3]),
+ .I3(n7055_35)
+);
+defparam n7055_s24.INIT=16'hF7AC;
+ LUT4 n7055_s25 (
+ .F(n7055_34),
+ .I0(score_counter[4]),
+ .I1(score_counter[6]),
+ .I2(score_counter[5]),
+ .I3(n7055_36)
+);
+defparam n7055_s25.INIT=16'hF8B7;
+ LUT3 n7056_s22 (
+ .F(n7056_33),
+ .I0(score_counter[2]),
+ .I1(score_counter[1]),
+ .I2(n7055)
+);
+defparam n7056_s22.INIT=8'h17;
+ LUT4 square_s6 (
+ .F(square_10),
+ .I0(square_14),
+ .I1(square_15),
+ .I2(square_16),
+ .I3(square_17)
);
-defparam n11097_s17.INIT=16'h4000;
- LUT4 square_s7 (
+defparam square_s6.INIT=16'hF100;
+ LUT3 square_s7 (
.F(square_11),
- .I0(square_17),
- .I1(sx_Z[5]),
- .I2(square_33),
- .I3(square_29)
+ .I0(square_18),
+ .I1(qx[8]),
+ .I2(qx[7])
);
-defparam square_s7.INIT=16'h008E;
+defparam square_s7.INIT=8'h40;
LUT4 square_s8 (
.F(square_12),
- .I0(sx_Z[7]),
- .I1(n3294_20),
- .I2(n3294_18),
- .I3(sx_Z[6])
+ .I0(square_14),
+ .I1(square_19),
+ .I2(square_15),
+ .I3(square_20)
);
-defparam square_s8.INIT=16'h0DDD;
+defparam square_s8.INIT=16'hFB00;
LUT4 square_s9 (
.F(square_13),
- .I0(sx_Z[8]),
- .I1(square_14),
- .I2(sx_Z[7]),
- .I3(n3294_20)
-);
-defparam square_s9.INIT=16'hE0EE;
- LUT2 square_s10 (
- .F(square_14),
- .I0(qx[8]),
- .I1(square_20)
-);
-defparam square_s10.INIT=4'h9;
- LUT2 square_s11 (
- .F(square_15),
- .I0(qx[8]),
- .I1(square_20)
-);
-defparam square_s11.INIT=4'h8;
- LUT4 square_s12 (
- .F(square_16),
- .I0(n11097_49),
- .I1(square_21),
- .I2(sy_Z[9]),
- .I3(n3696_42)
-);
-defparam square_s12.INIT=16'hF400;
- LUT3 ball_s6 (
- .F(ball_10),
- .I0(sx_Z[6]),
- .I1(n9050_9),
- .I2(ball_14)
+ .I0(sy_Z[6]),
+ .I1(sy_Z[5]),
+ .I2(square_21),
+ .I3(sy_Z[8])
);
-defparam ball_s6.INIT=8'h17;
- LUT3 ball_s7 (
+defparam square_s9.INIT=16'hFE00;
+ LUT2 ball_s7 (
.F(ball_11),
- .I0(n9048_9),
- .I1(n155_8),
- .I2(qxb[7])
-);
-defparam ball_s7.INIT=8'h4B;
- LUT2 ball_s8 (
- .F(ball_12),
- .I0(n9052_6),
- .I1(sx_Z[8])
+ .I0(qxb[7]),
+ .I1(qxb[8])
);
-defparam ball_s8.INIT=4'h8;
- LUT2 ball_s9 (
- .F(ball_13),
+defparam ball_s7.INIT=4'h8;
+ LUT4 ball_s10 (
+ .F(ball_14),
.I0(sx_Z[8]),
- .I1(n9052_6)
+ .I1(ball_16),
+ .I2(ball_17),
+ .I3(ball_18)
);
-defparam ball_s9.INIT=4'h1;
+defparam ball_s10.INIT=16'hF400;
+ LUT4 ball_s11 (
+ .F(ball_15),
+ .I0(ball_19),
+ .I1(ball_17),
+ .I2(ball_50),
+ .I3(ball_21)
+);
+defparam ball_s11.INIT=16'h0305;
+ LUT4 score_area_1_s5 (
+ .F(score_area_1_9),
+ .I0(sx_Z[6]),
+ .I1(sy_Z[4]),
+ .I2(score_area_1_10),
+ .I3(n4347_9)
+);
+defparam score_area_1_s5.INIT=16'h1000;
LUT4 qx_9_s4 (
.F(qx_9_8),
.I0(qx[1]),
@@ -4210,1075 +5718,2148 @@ defparam ball_s9.INIT=4'h1;
.I3(qx[9])
);
defparam qx_9_s4.INIT=16'h001F;
- LUT4 n3741_s29 (
- .F(n3741_36),
- .I0(sy_Z[5]),
- .I1(n3741_41),
- .I2(n3741_42),
- .I3(n3741_43)
-);
-defparam n3741_s29.INIT=16'h0017;
- LUT4 n3741_s30 (
- .F(n3741_37),
- .I0(sy_Z[6]),
- .I1(qyb[6]),
- .I2(n3741_57),
- .I3(n3741_45)
-);
-defparam n3741_s30.INIT=16'hD43F;
- LUT4 n3741_s31 (
- .F(n3741_38),
- .I0(n3741_46),
- .I1(sy_Z[7]),
- .I2(qyb[8]),
- .I3(sy_Z[8])
+ LUT4 qyb_9_s4 (
+ .F(qyb_9_8),
+ .I0(qyb[6]),
+ .I1(qyb[5]),
+ .I2(n3744_14),
+ .I3(qyb[9])
);
-defparam n3741_s31.INIT=16'h6177;
- LUT4 n3741_s32 (
- .F(n3741_39),
+defparam qyb_9_s4.INIT=16'h001F;
+ LUT4 n4207_s31 (
+ .F(n4207_38),
+ .I0(n4207_41),
+ .I1(n4207_42),
+ .I2(n4207_43),
+ .I3(n4207_82)
+);
+defparam n4207_s31.INIT=16'h004F;
+ LUT2 n4207_s33 (
+ .F(n4207_40),
.I0(qyb[7]),
- .I1(n3741_59),
- .I2(sy_Z[8]),
- .I3(qyb[8])
+ .I1(n4207_70)
);
-defparam n3741_s32.INIT=16'h0708;
- LUT3 qdy_s6 (
- .F(qdy_10),
- .I0(n317_9),
- .I1(n316_6),
- .I2(qdy)
+defparam n4207_s33.INIT=4'h8;
+ LUT3 n7272_s80 (
+ .F(n7272_110),
+ .I0(sx_Z[1]),
+ .I1(sx_Z[2]),
+ .I2(sx_Z[3])
);
-defparam qdy_s6.INIT=8'h70;
- LUT4 n3710_s35 (
- .F(n3710_48),
+defparam n7272_s80.INIT=8'hE7;
+ LUT2 n7272_s81 (
+ .F(n7272_111),
.I0(sy_Z[2]),
- .I1(sy_Z[3]),
- .I2(sy_Z[1]),
- .I3(sy_Z[4])
+ .I1(sy_Z[3])
+);
+defparam n7272_s81.INIT=4'h8;
+ LUT3 n7272_s82 (
+ .F(n7272_112),
+ .I0(n7272_115),
+ .I1(n7272_116),
+ .I2(sy_Z[3])
+);
+defparam n7272_s82.INIT=8'hCA;
+ LUT4 n7272_s83 (
+ .F(n7272_113),
+ .I0(n7272_104),
+ .I1(n7272_117),
+ .I2(sx_Z[1]),
+ .I3(sx_Z[2])
);
-defparam n3710_s35.INIT=16'h007F;
- LUT4 n3881_s3 (
- .F(n3881_7),
- .I0(n3881_8),
- .I1(sx_Z[5]),
+defparam n7272_s83.INIT=16'hF50C;
+ LUT4 n7272_s84 (
+ .F(n7272_114),
+ .I0(n7272_118),
+ .I1(n7272_102),
+ .I2(sx_Z[2]),
+ .I3(sx_Z[1])
+);
+defparam n7272_s84.INIT=16'h5FC0;
+ LUT4 n7421_s74 (
+ .F(n7421_103),
+ .I0(n7421_105),
+ .I1(n7421_106),
+ .I2(sx_Z[2]),
+ .I3(sy_Z[3])
+);
+defparam n7421_s74.INIT=16'h0305;
+ LUT4 n7421_s75 (
+ .F(n7421_104),
+ .I0(n7421_107),
+ .I1(n7421_108),
+ .I2(n7421_109),
+ .I3(sx_Z[3])
+);
+defparam n7421_s75.INIT=16'h0FBB;
+ LUT4 n4347_s3 (
+ .F(n4347_7),
+ .I0(sx_Z[1]),
+ .I1(sx_Z[0]),
+ .I2(sx_Z[3]),
+ .I3(sx_Z[2])
+);
+defparam n4347_s3.INIT=16'h0007;
+ LUT4 n4347_s4 (
+ .F(n4347_8),
+ .I0(sx_Z[6]),
+ .I1(sx_Z[3]),
.I2(sx_Z[4]),
- .I3(sx_Z[6])
+ .I3(sx_Z[5])
);
-defparam n3881_s3.INIT=16'hBFC4;
+defparam n4347_s4.INIT=16'hF400;
+ LUT3 n4347_s5 (
+ .F(n4347_9),
+ .I0(sx_Z[7]),
+ .I1(sx_Z[8]),
+ .I2(sx_Z[9])
+);
+defparam n4347_s5.INIT=8'h01;
LUT3 n155_s4 (
- .F(n155_8),
+ .F(n155_21),
.I0(qxb[4]),
.I1(qxb[5]),
.I2(qxb[6])
);
defparam n155_s4.INIT=8'h80;
- LUT2 n192_s4 (
- .F(n192_7),
- .I0(qxb[0]),
- .I1(qxb[1])
-);
-defparam n192_s4.INIT=4'h1;
- LUT2 n316_s6 (
- .F(n316_9),
- .I0(qyb[0]),
- .I1(qyb[1])
-);
-defparam n316_s6.INIT=4'h1;
- LUT3 n3294_s14 (
- .F(n3294_17),
- .I0(n3294_36),
- .I1(qxb[5]),
- .I2(square_33)
+ LUT4 n6843_s18 (
+ .F(n6843_23),
+ .I0(n6843_25),
+ .I1(score_counter[5]),
+ .I2(score_counter[7]),
+ .I3(score_counter[3])
+);
+defparam n6843_s18.INIT=16'hB66D;
+ LUT4 n6843_s19 (
+ .F(n6843_24),
+ .I0(score_counter[7]),
+ .I1(n6843_26),
+ .I2(score_counter[5]),
+ .I3(score_counter[4])
+);
+defparam n6843_s19.INIT=16'h4000;
+ LUT4 n6846_s9 (
+ .F(n6846_15),
+ .I0(score_counter[2]),
+ .I1(score_counter[4]),
+ .I2(score_counter[6]),
+ .I3(n6846_20)
+);
+defparam n6846_s9.INIT=16'hFB2F;
+ LUT4 n6846_s10 (
+ .F(n6846_16),
+ .I0(score_counter[6]),
+ .I1(score_counter[5]),
+ .I2(score_counter[3]),
+ .I3(n6843_25)
+);
+defparam n6846_s10.INIT=16'h7CEF;
+ LUT4 n6846_s11 (
+ .F(n6846_17),
+ .I0(n6846_21),
+ .I1(score_counter[4]),
+ .I2(score_counter[7]),
+ .I3(score_counter[2])
+);
+defparam n6846_s11.INIT=16'h0140;
+ LUT4 n6846_s12 (
+ .F(n6846_18),
+ .I0(score_counter[7]),
+ .I1(score_counter[5]),
+ .I2(score_counter[3]),
+ .I3(score_counter[6])
+);
+defparam n6846_s12.INIT=16'hDB04;
+ LUT4 n6846_s13 (
+ .F(n6846_19),
+ .I0(n6843_24),
+ .I1(n6846_22),
+ .I2(n6846_23),
+ .I3(score_counter[6])
+);
+defparam n6846_s13.INIT=16'hEE0F;
+ LUT4 n190_s7 (
+ .F(n190_10),
+ .I0(n192_4),
+ .I1(n10669_9),
+ .I2(qxb[4]),
+ .I3(n190_11)
);
-defparam n3294_s14.INIT=8'hB2;
- LUT3 n3294_s15 (
- .F(n3294_18),
- .I0(qx[5]),
- .I1(n3294_37),
- .I2(qx[6])
+defparam n190_s7.INIT=16'hCA00;
+ LUT2 n315_s6 (
+ .F(n315_9),
+ .I0(qyb[3]),
+ .I1(qyb[6])
);
-defparam n3294_s15.INIT=8'h1E;
- LUT2 n3294_s16 (
- .F(n3294_19),
+defparam n315_s6.INIT=4'h8;
+ LUT3 n3744_s15 (
+ .F(n3744_18),
.I0(qxb[7]),
- .I1(n3294_20)
+ .I1(ball_43),
+ .I2(qxb[8])
);
-defparam n3294_s16.INIT=4'h2;
- LUT4 n3294_s17 (
- .F(n3294_20),
- .I0(qx[5]),
- .I1(qx[6]),
- .I2(n3294_37),
- .I3(qx[7])
+defparam n3744_s15.INIT=8'h87;
+ LUT4 n3744_s16 (
+ .F(n3744_19),
+ .I0(qx[7]),
+ .I1(n3744_28),
+ .I2(ball_43),
+ .I3(qxb[7])
);
-defparam n3294_s17.INIT=16'h01FE;
- LUT4 n3294_s19 (
- .F(n3294_22),
- .I0(qx[6]),
- .I1(n3294_38),
- .I2(n3294_62),
- .I3(n9050_9)
+defparam n3744_s16.INIT=16'h4DD4;
+ LUT3 n3744_s17 (
+ .F(n3744_20),
+ .I0(qx[9]),
+ .I1(qxb[9]),
+ .I2(n3744_60)
);
-defparam n3294_s19.INIT=16'hFEA8;
- LUT4 n3294_s20 (
- .F(n3294_23),
+defparam n3744_s17.INIT=8'h2B;
+ LUT4 n3744_s18 (
+ .F(n3744_21),
.I0(qxb[9]),
- .I1(n9048_7),
+ .I1(n3744_60),
.I2(qx[9]),
- .I3(n3294_40)
-);
-defparam n3294_s20.INIT=16'hEF00;
- LUT4 n3294_s21 (
- .F(n3294_24),
- .I0(n3294_41),
- .I1(qxb[9]),
- .I2(n9048_7),
- .I3(qx[9])
-);
-defparam n3294_s21.INIT=16'hE8FE;
- LUT4 n3294_s22 (
- .F(n3294_25),
- .I0(qxb[8]),
- .I1(qx[8]),
- .I2(square_20),
- .I3(qxb[9])
-);
-defparam n3294_s22.INIT=16'hBF02;
- LUT4 n3294_s23 (
- .F(n3294_26),
- .I0(qx[8]),
- .I1(square_20),
- .I2(qxb[9]),
- .I3(qxb[8])
-);
-defparam n3294_s23.INIT=16'h1000;
- LUT4 n3294_s24 (
- .F(n3294_27),
- .I0(n9054_8),
- .I1(qyb[0]),
- .I2(qyb[7]),
- .I3(n3294_42)
+ .I3(n3744_30)
+);
+defparam n3744_s18.INIT=16'h00EF;
+ LUT4 n3744_s19 (
+ .F(n3744_22),
+ .I0(n3744_31),
+ .I1(n3744_32),
+ .I2(n3744_33),
+ .I3(n3744_34)
+);
+defparam n3744_s19.INIT=16'h3500;
+ LUT3 n3744_s20 (
+ .F(n3744_23),
+ .I0(n10658_5),
+ .I1(n10658_6),
+ .I2(bricks_active[1])
+);
+defparam n3744_s20.INIT=8'hE0;
+ LUT4 n3744_s21 (
+ .F(n3744_24),
+ .I0(n10659_8),
+ .I1(n155_21),
+ .I2(bricks_active[0]),
+ .I3(n10659_5)
+);
+defparam n3744_s21.INIT=16'hB000;
+ LUT4 n3744_s22 (
+ .F(n3744_25),
+ .I0(n3744_35),
+ .I1(n10657_5),
+ .I2(n3741_4),
+ .I3(n3744_36)
+);
+defparam n3744_s22.INIT=16'h0B00;
+ LUT4 n3744_s24 (
+ .F(n3744_27),
+ .I0(bricks_active[4]),
+ .I1(n10667_4),
+ .I2(n10661_10),
+ .I3(n10661_6)
+);
+defparam n3744_s24.INIT=16'h8000;
+ LUT2 n3735_s16 (
+ .F(n3735_19),
+ .I0(n10669_4),
+ .I1(n3735_33)
+);
+defparam n3735_s16.INIT=4'h8;
+ LUT3 n3735_s17 (
+ .F(n3735_20),
+ .I0(n3735_33),
+ .I1(n10670_4),
+ .I2(n3735_34)
+);
+defparam n3735_s17.INIT=8'h78;
+ LUT4 n3735_s20 (
+ .F(n3735_23),
+ .I0(n3739_7),
+ .I1(n3737_30),
+ .I2(n3737_20),
+ .I3(n3735_50)
+);
+defparam n3735_s20.INIT=16'h4000;
+ LUT4 n3735_s21 (
+ .F(n3735_24),
+ .I0(n3739_7),
+ .I1(n3737_22),
+ .I2(n3735_35),
+ .I3(n3735_50)
+);
+defparam n3735_s21.INIT=16'hF400;
+ LUT2 n3735_s23 (
+ .F(n3735_26),
+ .I0(score_counter[5]),
+ .I1(n3735_34)
+);
+defparam n3735_s23.INIT=4'h2;
+ LUT3 n3735_s24 (
+ .F(n3735_27),
+ .I0(n3738_6),
+ .I1(score_counter[3]),
+ .I2(n3737_18)
+);
+defparam n3735_s24.INIT=8'hD8;
+ LUT4 n3735_s25 (
+ .F(n3735_28),
+ .I0(n3739_13),
+ .I1(n3735_36),
+ .I2(n3738_6),
+ .I3(score_counter[3])
+);
+defparam n3735_s25.INIT=16'hF400;
+ LUT3 n3735_s28 (
+ .F(n3735_31),
+ .I0(n3738_8),
+ .I1(n3739_7),
+ .I2(n3737_36)
+);
+defparam n3735_s28.INIT=8'h0D;
+ LUT3 n3735_s29 (
+ .F(n3735_32),
+ .I0(n3737_34),
+ .I1(score_counter[1]),
+ .I2(n3741_11)
+);
+defparam n3735_s29.INIT=8'h15;
+ LUT2 n3737_s14 (
+ .F(n3737_17),
+ .I0(score_counter[1]),
+ .I1(score_counter[0])
+);
+defparam n3737_s14.INIT=4'h8;
+ LUT4 n3737_s15 (
+ .F(n3737_18),
+ .I0(score_counter[0]),
+ .I1(n10668_4),
+ .I2(n3737_10),
+ .I3(n3739_13)
+);
+defparam n3737_s15.INIT=16'h0080;
+ LUT4 n3737_s17 (
+ .F(n3737_20),
+ .I0(bricks_active[8]),
+ .I1(n10657_5),
+ .I2(n10664_5),
+ .I3(n10660_5)
+);
+defparam n3737_s17.INIT=16'hF800;
+ LUT4 n3737_s18 (
+ .F(n3737_21),
+ .I0(n3737_17),
+ .I1(n10665_4),
+ .I2(n3737_10),
+ .I3(n3735_35)
+);
+defparam n3737_s18.INIT=16'h007F;
+ LUT4 n3737_s19 (
+ .F(n3737_22),
+ .I0(score_counter[3]),
+ .I1(score_counter[0]),
+ .I2(n10661_4),
+ .I3(n3739_13)
+);
+defparam n3737_s19.INIT=16'h0080;
+ LUT3 n3738_s5 (
+ .F(n3738_8),
+ .I0(score_counter[0]),
+ .I1(n10661_4),
+ .I2(n3739_13)
+);
+defparam n3738_s5.INIT=8'h08;
+ LUT3 n3739_s13 (
+ .F(n3739_16),
+ .I0(n3744_36),
+ .I1(n10663_4),
+ .I2(n3741_23)
+);
+defparam n3739_s13.INIT=8'h02;
+ LUT4 n3739_s14 (
+ .F(n3739_17),
+ .I0(n10659_8),
+ .I1(n155_21),
+ .I2(bricks_active[0]),
+ .I3(score_counter[0])
+);
+defparam n3739_s14.INIT=16'hB000;
+ LUT4 n3741_s12 (
+ .F(n3741_15),
+ .I0(qxb[1]),
+ .I1(qxb[0]),
+ .I2(qxb[2]),
+ .I3(qxb[3])
);
-defparam n3294_s24.INIT=16'h7000;
- LUT4 n3294_s25 (
- .F(n3294_28),
- .I0(n9049_4),
- .I1(bricks_active[16]),
- .I2(n9053_4),
- .I3(n9049_5)
+defparam n3741_s12.INIT=16'h007F;
+ LUT4 n3741_s13 (
+ .F(n3741_16),
+ .I0(n3741_24),
+ .I1(qyb[7]),
+ .I2(qyb[6]),
+ .I3(qyb[5])
);
-defparam n3294_s25.INIT=16'hF800;
- LUT4 n3294_s26 (
- .F(n3294_29),
- .I0(bricks_active[10]),
- .I1(n9055_4),
- .I2(n3294_66),
- .I3(n9049_4)
-);
-defparam n3294_s26.INIT=16'hF800;
- LUT3 n3294_s27 (
- .F(n3294_30),
- .I0(n3294_44),
- .I1(n9050_7),
- .I2(n9050_4)
-);
-defparam n3294_s27.INIT=8'h10;
- LUT4 n3294_s28 (
- .F(n3294_31),
- .I0(bricks_active[7]),
- .I1(n9055_4),
- .I2(n3294_45),
- .I3(n9052_5)
-);
-defparam n3294_s28.INIT=16'hF800;
- LUT4 n3294_s29 (
- .F(n3294_32),
- .I0(n9060_4),
- .I1(n9048_4),
- .I2(n9054_4),
- .I3(n9048_5)
-);
-defparam n3294_s29.INIT=16'h00FE;
- LUT3 n3294_s30 (
- .F(n3294_33),
- .I0(n9057_4),
- .I1(n3294_46),
- .I2(n9051_5)
-);
-defparam n3294_s30.INIT=8'hB0;
- LUT2 n3294_s31 (
- .F(n3294_34),
- .I0(n3294_47),
- .I1(n9065_4)
-);
-defparam n3294_s31.INIT=4'h1;
- LUT3 n3294_s32 (
- .F(n3294_35),
- .I0(n9056_4),
- .I1(n9050_7),
- .I2(n9059_4)
-);
-defparam n3294_s32.INIT=8'h0D;
- LUT4 n9048_s6 (
- .F(n9048_9),
- .I0(qxb[0]),
- .I1(qxb[1]),
- .I2(qxb[3]),
- .I3(qxb[2])
+defparam n3741_s13.INIT=16'hDFF3;
+ LUT4 n3741_s14 (
+ .F(n3741_17),
+ .I0(qxb[5]),
+ .I1(qxb[6]),
+ .I2(qxb[4]),
+ .I3(qxb[7])
);
-defparam n9048_s6.INIT=16'h0001;
- LUT4 n9048_s7 (
- .F(n9048_10),
+defparam n3741_s14.INIT=16'hFE00;
+ LUT3 n3741_s16 (
+ .F(n3741_19),
+ .I0(score_counter[0]),
+ .I1(n10668_4),
+ .I2(n10669_4)
+);
+defparam n3741_s16.INIT=8'h69;
+ LUT4 n3741_s17 (
+ .F(n3741_20),
+ .I0(n10660_5),
+ .I1(n10657_5),
+ .I2(bricks_active[8]),
+ .I3(n10670_4)
+);
+defparam n3741_s17.INIT=16'h007F;
+ LUT2 n3741_s18 (
+ .F(n3741_21),
+ .I0(score_counter[0]),
+ .I1(n10662_4)
+);
+defparam n3741_s18.INIT=4'h8;
+ LUT2 n3741_s19 (
+ .F(n3741_22),
+ .I0(n10660_4),
+ .I1(n10661_4)
+);
+defparam n3741_s19.INIT=4'h1;
+ LUT4 n3741_s20 (
+ .F(n3741_23),
+ .I0(n10664_5),
+ .I1(n10660_5),
+ .I2(n10666_4),
+ .I3(n10665_4)
+);
+defparam n3741_s20.INIT=16'hFCB8;
+ LUT4 n10654_s4 (
+ .F(n10654_7),
.I0(qxb[3]),
.I1(qxb[1]),
.I2(qxb[2]),
.I3(qxb[5])
);
-defparam n9048_s7.INIT=16'h007F;
- LUT4 n9049_s8 (
- .F(n9049_11),
- .I0(qxb[5]),
- .I1(qxb[3]),
- .I2(qxb[1]),
- .I3(qxb[2])
-);
-defparam n9049_s8.INIT=16'h2BBB;
- LUT4 n9050_s5 (
- .F(n9050_8),
- .I0(qxb[3]),
- .I1(n9050_10),
- .I2(qxb[4]),
- .I3(qxb[5])
-);
-defparam n9050_s5.INIT=16'h4000;
- LUT4 n9050_s6 (
- .F(n9050_9),
- .I0(n9048_9),
- .I1(qxb[4]),
- .I2(qxb[5]),
- .I3(qxb[6])
-);
-defparam n9050_s6.INIT=16'h40BF;
- LUT4 n9051_s3 (
- .F(n9051_6),
- .I0(n9051_7),
+defparam n10654_s4.INIT=16'h007F;
+ LUT3 n10654_s5 (
+ .F(n10654_8),
+ .I0(qxb[7]),
.I1(qxb[8]),
- .I2(qxb[6]),
- .I3(qxb[7])
-);
-defparam n9051_s3.INIT=16'hEFF3;
- LUT4 n9052_s3 (
- .F(n9052_6),
- .I0(n9048_9),
- .I1(qxb[7]),
- .I2(n155_8),
- .I3(qxb[8])
+ .I2(qxb[9])
);
-defparam n9052_s3.INIT=16'h40BF;
- LUT4 n9052_s4 (
- .F(n9052_7),
- .I0(n9051_7),
- .I1(n9052_9),
- .I2(qxb[7]),
- .I3(qxb[6])
+defparam n10654_s5.INIT=8'h10;
+ LUT4 n10658_s4 (
+ .F(n10658_7),
+ .I0(qxb[3]),
+ .I1(qxb[1]),
+ .I2(qxb[2]),
+ .I3(qxb[4])
);
-defparam n9052_s4.INIT=16'hD000;
- LUT4 n9052_s5 (
- .F(n9052_8),
- .I0(qxb[7]),
- .I1(n9052_10),
- .I2(qxb[9]),
- .I3(n155_8)
+defparam n10658_s4.INIT=16'hFE00;
+ LUT3 n10658_s5 (
+ .F(n10658_8),
+ .I0(qxb[8]),
+ .I1(qxb[9]),
+ .I2(qxb[7])
);
-defparam n9052_s5.INIT=16'h0C0A;
- LUT2 n9053_s4 (
- .F(n9053_7),
+defparam n10658_s5.INIT=8'h10;
+ LUT4 n10658_s6 (
+ .F(n10658_9),
.I0(qxb[0]),
- .I1(qxb[1])
+ .I1(qxb[1]),
+ .I2(qxb[2]),
+ .I3(qxb[3])
);
-defparam n9053_s4.INIT=4'h8;
- LUT4 n9053_s5 (
- .F(n9053_8),
+defparam n10658_s6.INIT=16'h01FE;
+ LUT4 n10659_s4 (
+ .F(n10659_7),
.I0(qxb[2]),
.I1(qxb[1]),
.I2(qxb[4]),
.I3(qxb[3])
);
-defparam n9053_s5.INIT=16'hE000;
- LUT2 n9054_s4 (
- .F(n9054_7),
- .I0(qyb[5]),
- .I1(qyb[2])
+defparam n10659_s4.INIT=16'hE000;
+ LUT4 n10659_s5 (
+ .F(n10659_8),
+ .I0(qxb[1]),
+ .I1(qxb[0]),
+ .I2(qxb[3]),
+ .I3(qxb[2])
);
-defparam n9054_s4.INIT=4'h1;
- LUT4 n9054_s5 (
- .F(n9054_8),
+defparam n10659_s5.INIT=16'h0007;
+ LUT4 n10660_s3 (
+ .F(n10660_6),
.I0(qyb[1]),
.I1(qyb[3]),
- .I2(qyb[5]),
- .I3(qyb[2])
+ .I2(qyb[2]),
+ .I3(qyb[5])
);
-defparam n9054_s5.INIT=16'h8000;
- LUT2 n9059_s3 (
- .F(n9059_6),
- .I0(bricks_active[6]),
- .I1(qyb[6])
+defparam n10660_s3.INIT=16'h7F01;
+ LUT4 n10660_s4 (
+ .F(n10660_7),
+ .I0(qyb[7]),
+ .I1(qyb[8]),
+ .I2(qyb[9]),
+ .I3(qyb[6])
);
-defparam n9059_s3.INIT=4'h8;
- LUT4 n11097_s18 (
- .F(n11097_21),
- .I0(n11097_34),
- .I1(sx_Z[4]),
- .I2(sx_Z[5]),
- .I3(sx_Z[6])
+defparam n10660_s4.INIT=16'h0100;
+ LUT4 n10661_s4 (
+ .F(n10661_7),
+ .I0(qxb[1]),
+ .I1(qxb[2]),
+ .I2(qxb[3]),
+ .I3(qxb[4])
+);
+defparam n10661_s4.INIT=16'hF800;
+ LUT4 n10661_s5 (
+ .F(n10661_8),
+ .I0(qxb[0]),
+ .I1(qxb[1]),
+ .I2(qxb[3]),
+ .I3(qxb[2])
+);
+defparam n10661_s5.INIT=16'h8000;
+ LUT2 n10669_s5 (
+ .F(n10669_8),
+ .I0(qxb[3]),
+ .I1(qxb[4])
+);
+defparam n10669_s5.INIT=4'h8;
+ LUT4 n10669_s6 (
+ .F(n10669_9),
+ .I0(qxb[0]),
+ .I1(qxb[1]),
+ .I2(qxb[3]),
+ .I3(qxb[2])
+);
+defparam n10669_s6.INIT=16'h0001;
+ LUT4 n12765_s17 (
+ .F(n12765_20),
+ .I0(n12765_28),
+ .I1(score_area_1_7),
+ .I2(sx_Z[6]),
+ .I3(sx_Z[7])
);
-defparam n11097_s18.INIT=16'h2FD0;
- LUT4 n11097_s19 (
- .F(n11097_22),
+defparam n12765_s17.INIT=16'hF38F;
+ LUT4 n12765_s18 (
+ .F(n12765_21),
.I0(sx_Z[7]),
.I1(sx_Z[8]),
.I2(sx_Z[9]),
- .I3(n11097_35)
+ .I3(n12765_29)
);
-defparam n11097_s19.INIT=16'h1000;
- LUT4 n11097_s20 (
- .F(n11097_23),
+defparam n12765_s18.INIT=16'h1000;
+ LUT4 n12765_s19 (
+ .F(n12765_22),
.I0(sx_Z[8]),
.I1(sx_Z[9]),
- .I2(n11097_31),
- .I3(sx_Z[7])
+ .I2(sx_Z[7]),
+ .I3(n12765_30)
);
-defparam n11097_s20.INIT=16'h1000;
- LUT3 n11097_s21 (
- .F(n11097_24),
- .I0(n11097_36),
+defparam n12765_s19.INIT=16'h1000;
+ LUT4 n12765_s20 (
+ .F(n12765_23),
+ .I0(n12765_31),
.I1(sx_Z[9]),
- .I2(sx_Z[8])
+ .I2(sx_Z[8]),
+ .I3(sx_Z[7])
);
-defparam n11097_s21.INIT=8'h10;
- LUT4 n11097_s22 (
- .F(n11097_25),
- .I0(n11097_37),
- .I1(sx_Z[9]),
- .I2(sx_Z[7]),
- .I3(n11097_38)
+defparam n12765_s20.INIT=16'h2000;
+ LUT4 n12765_s21 (
+ .F(n12765_24),
+ .I0(n12765_49),
+ .I1(n12765_33),
+ .I2(n12765_34),
+ .I3(sx_Z[6])
);
-defparam n11097_s22.INIT=16'h0130;
- LUT4 n11097_s23 (
- .F(n11097_26),
- .I0(sy_Z[1]),
- .I1(sy_Z[2]),
- .I2(sy_Z[3]),
- .I3(sy_Z[4])
+defparam n12765_s21.INIT=16'hBB0F;
+ LUT4 n12765_s22 (
+ .F(n12765_25),
+ .I0(sy_Z[7]),
+ .I1(sy_Z[8]),
+ .I2(sy_Z[9]),
+ .I3(sy_Z[6])
);
-defparam n11097_s23.INIT=16'h8000;
- LUT2 n11097_s24 (
- .F(n11097_27),
- .I0(sy_Z[5]),
- .I1(sy_Z[6])
+defparam n12765_s22.INIT=16'h0100;
+ LUT4 n12765_s23 (
+ .F(n12765_26),
+ .I0(n12765_21),
+ .I1(bricks_active[17]),
+ .I2(bricks_active[13]),
+ .I3(n12765_22)
);
-defparam n11097_s24.INIT=4'h1;
- LUT4 n11097_s25 (
- .F(n11097_28),
- .I0(sy_Z[2]),
- .I1(sy_Z[3]),
- .I2(sy_Z[4]),
- .I3(sy_Z[5])
-);
-defparam n11097_s25.INIT=16'h8000;
- LUT2 n11097_s26 (
- .F(n11097_29),
- .I0(sy_Z[8]),
- .I1(sy_Z[9])
-);
-defparam n11097_s26.INIT=4'h1;
- LUT3 n11097_s27 (
- .F(n11097_30),
- .I0(n3710_48),
- .I1(sy_Z[4]),
- .I2(sy_Z[5])
+defparam n12765_s23.INIT=16'h0777;
+ LUT3 n12765_s24 (
+ .F(n12765_27),
+ .I0(n12765_24),
+ .I1(bricks_active[14]),
+ .I2(n12765_35)
+);
+defparam n12765_s24.INIT=8'hB0;
+ LUT3 n7055_s26 (
+ .F(n7055_35),
+ .I0(score_counter[6]),
+ .I1(score_counter[5]),
+ .I2(score_counter[4])
+);
+defparam n7055_s26.INIT=8'h3D;
+ LUT3 n7055_s27 (
+ .F(n7055_36),
+ .I0(n7053),
+ .I1(score_counter[4]),
+ .I2(score_counter[3])
+);
+defparam n7055_s27.INIT=8'hCA;
+ LUT4 square_s10 (
+ .F(square_14),
+ .I0(square_22),
+ .I1(sx_Z[6]),
+ .I2(square_23),
+ .I3(qx[6])
);
-defparam n11097_s27.INIT=8'h53;
- LUT4 n11097_s28 (
- .F(n11097_31),
- .I0(n11097_39),
- .I1(n11097_40),
- .I2(sx_Z[5]),
- .I3(sx_Z[6])
+defparam square_s10.INIT=16'h1F00;
+ LUT3 square_s11 (
+ .F(square_15),
+ .I0(sx_Z[6]),
+ .I1(square_18),
+ .I2(square_24)
);
-defparam n11097_s28.INIT=16'h03F5;
- LUT4 n11097_s29 (
- .F(n11097_32),
+defparam square_s11.INIT=8'hC5;
+ LUT4 square_s12 (
+ .F(square_16),
.I0(sx_Z[8]),
- .I1(sx_Z[9]),
- .I2(bricks_active[13]),
- .I3(sx_Z[7])
-);
-defparam n11097_s29.INIT=16'h1000;
- LUT4 n11097_s30 (
- .F(n11097_33),
- .I0(sy_Z[1]),
- .I1(sy_Z[2]),
- .I2(sy_Z[3]),
- .I3(sy_Z[4])
+ .I1(square_11),
+ .I2(sx_Z[7]),
+ .I3(square_41)
);
-defparam n11097_s30.INIT=16'h0001;
- LUT3 square_s13 (
+defparam square_s12.INIT=16'hF800;
+ LUT4 square_s13 (
.F(square_17),
- .I0(sx_Z[4]),
- .I1(square_22),
- .I2(square_23)
+ .I0(square_11),
+ .I1(sx_Z[8]),
+ .I2(sx_Z[7]),
+ .I3(square_41)
+);
+defparam square_s13.INIT=16'hEEE0;
+ LUT3 square_s14 (
+ .F(square_18),
+ .I0(qx[5]),
+ .I1(qx[6]),
+ .I2(square_39)
+);
+defparam square_s14.INIT=8'h01;
+ LUT3 square_s15 (
+ .F(square_19),
+ .I0(qx[7]),
+ .I1(sx_Z[7]),
+ .I2(square_18)
);
-defparam square_s13.INIT=8'hE8;
+defparam square_s15.INIT=8'hD4;
LUT4 square_s16 (
.F(square_20),
- .I0(qx[6]),
- .I1(qx[5]),
- .I2(n3294_37),
- .I3(qx[7])
+ .I0(qx[7]),
+ .I1(sx_Z[7]),
+ .I2(square_18),
+ .I3(sx_Z[8])
);
-defparam square_s16.INIT=16'hFE00;
+defparam square_s16.INIT=16'h02BF;
LUT4 square_s17 (
.F(square_21),
- .I0(n11097_27),
- .I1(sy_Z[0]),
- .I2(sy_Z[7]),
- .I3(sy_Z[8])
-);
-defparam square_s17.INIT=16'hD000;
- LUT4 ball_s10 (
- .F(ball_14),
- .I0(sx_Z[5]),
- .I1(ball_15),
- .I2(ball_16),
- .I3(ball_17)
-);
-defparam ball_s10.INIT=16'hFEA8;
- LUT4 n3741_s34 (
- .F(n3741_41),
- .I0(n3741_48),
+ .I0(sy_Z[1]),
.I1(sy_Z[4]),
- .I2(qyb[4]),
- .I3(n3741_55)
+ .I2(sy_Z[0]),
+ .I3(n7272_111)
);
-defparam n3741_s34.INIT=16'h8EE8;
- LUT3 n3741_s35 (
- .F(n3741_42),
- .I0(n3741_55),
- .I1(qyb[4]),
- .I2(qyb[5])
-);
-defparam n3741_s35.INIT=8'h4B;
- LUT3 n3741_s36 (
- .F(n3741_43),
- .I0(qyb[6]),
- .I1(n3741_57),
- .I2(sy_Z[6])
+defparam square_s17.INIT=16'h8000;
+ LUT3 ball_s12 (
+ .F(ball_16),
+ .I0(qxb[7]),
+ .I1(ball_43),
+ .I2(sx_Z[7])
);
-defparam n3741_s36.INIT=8'h90;
- LUT3 n3741_s38 (
- .F(n3741_45),
- .I0(qyb[6]),
- .I1(qyb[7]),
- .I2(sy_Z[7])
+defparam ball_s12.INIT=8'h8E;
+ LUT4 ball_s13 (
+ .F(ball_17),
+ .I0(ball_39),
+ .I1(ball_23),
+ .I2(ball_24),
+ .I3(ball_25)
+);
+defparam ball_s13.INIT=16'h001F;
+ LUT4 ball_s14 (
+ .F(ball_18),
+ .I0(qxb[7]),
+ .I1(ball_43),
+ .I2(sx_Z[7]),
+ .I3(sx_Z[8])
);
-defparam n3741_s38.INIT=8'hD3;
- LUT3 n3741_s39 (
- .F(n3741_46),
- .I0(sy_Z[7]),
- .I1(qyb[7]),
- .I2(n3741_59)
+defparam ball_s14.INIT=16'h08EF;
+ LUT3 ball_s15 (
+ .F(ball_19),
+ .I0(qxb[8]),
+ .I1(qxb[7]),
+ .I2(ball_43)
);
-defparam n3741_s39.INIT=8'h97;
- LUT4 n3881_s4 (
- .F(n3881_8),
- .I0(sx_Z[2]),
- .I1(n3881_9),
- .I2(sx_Z[4]),
- .I3(sx_Z[3])
+defparam ball_s15.INIT=8'h7C;
+ LUT4 ball_s17 (
+ .F(ball_21),
+ .I0(n3744_60),
+ .I1(sx_Z[8]),
+ .I2(ball_19),
+ .I3(sx_Z[7])
);
-defparam n3881_s4.INIT=16'h001F;
- LUT4 n3294_s33 (
- .F(n3294_36),
- .I0(n3294_48),
- .I1(n3294_49),
- .I2(square_22),
- .I3(qxb[4])
+defparam ball_s17.INIT=16'hF007;
+ LUT2 score_area_1_s6 (
+ .F(score_area_1_10),
+ .I0(sy_Z[5]),
+ .I1(sy_Z[6])
);
-defparam n3294_s33.INIT=16'h0EEE;
- LUT3 n3294_s34 (
- .F(n3294_37),
- .I0(qx[2]),
- .I1(qx[3]),
- .I2(qx[4])
-);
-defparam n3294_s34.INIT=8'h80;
- LUT4 n3294_s35 (
- .F(n3294_38),
- .I0(n3294_50),
- .I1(n3294_51),
- .I2(n3294_52),
- .I3(n3294_60)
-);
-defparam n3294_s35.INIT=16'h00F4;
- LUT4 n3294_s37 (
- .F(n3294_40),
- .I0(n9052_6),
- .I1(qx[8]),
- .I2(ball_11),
- .I3(qx[7])
+defparam score_area_1_s6.INIT=4'h1;
+ LUT4 n4207_s34 (
+ .F(n4207_41),
+ .I0(n4207_76),
+ .I1(n4207_72),
+ .I2(n4207_74),
+ .I3(sy_Z[5])
);
-defparam n3294_s37.INIT=16'h0777;
- LUT2 n3294_s38 (
- .F(n3294_41),
- .I0(qx[8]),
- .I1(n9052_6)
+defparam n4207_s34.INIT=16'h00F4;
+ LUT4 n4207_s35 (
+ .F(n4207_42),
+ .I0(n4207_74),
+ .I1(n4207_70),
+ .I2(n4207_49),
+ .I3(n4207_72)
+);
+defparam n4207_s35.INIT=16'h05CF;
+ LUT4 n4207_s36 (
+ .F(n4207_43),
+ .I0(n4207_50),
+ .I1(n4207_51),
+ .I2(qyb[6]),
+ .I3(n4207_80)
+);
+defparam n4207_s36.INIT=16'h00F1;
+ LUT4 n7272_s85 (
+ .F(n7272_115),
+ .I0(n7272_119),
+ .I1(\score_1[3] [2]),
+ .I2(sy_Z[1]),
+ .I3(sy_Z[2])
);
-defparam n3294_s38.INIT=4'h1;
- LUT4 n3294_s39 (
- .F(n3294_42),
- .I0(qyb[9]),
- .I1(qyb[4]),
- .I2(qyb[5]),
- .I3(qyb[8])
+defparam n7272_s85.INIT=16'h3553;
+ LUT4 n7272_s86 (
+ .F(n7272_116),
+ .I0(sy_Z[1]),
+ .I1(\score_1[6] [2]),
+ .I2(\score_1[5] [2]),
+ .I3(sy_Z[2])
);
-defparam n3294_s39.INIT=16'h1400;
- LUT4 n3294_s41 (
- .F(n3294_44),
- .I0(n9049_5),
- .I1(bricks_active[15]),
- .I2(bricks_active[3]),
- .I3(n9061_4)
-);
-defparam n3294_s41.INIT=16'h0777;
- LUT2 n3294_s42 (
- .F(n3294_45),
- .I0(bricks_active[13]),
- .I1(n9049_5)
-);
-defparam n3294_s42.INIT=4'h8;
- LUT4 n3294_s43 (
- .F(n3294_46),
- .I0(n9049_5),
- .I1(bricks_active[14]),
- .I2(bricks_active[2]),
- .I3(n9061_4)
-);
-defparam n3294_s43.INIT=16'h0777;
- LUT4 n3294_s44 (
- .F(n3294_47),
- .I0(n9052_6),
- .I1(n9052_7),
- .I2(n9052_8),
- .I3(n9064_4)
-);
-defparam n3294_s44.INIT=16'h2000;
- LUT3 n9050_s7 (
- .F(n9050_10),
- .I0(qxb[0]),
- .I1(qxb[1]),
- .I2(qxb[2])
+defparam n7272_s86.INIT=16'hBB0F;
+ LUT4 n7272_s87 (
+ .F(n7272_117),
+ .I0(sy_Z[2]),
+ .I1(\score_1[5] [3]),
+ .I2(n7272_90),
+ .I3(sy_Z[3])
);
-defparam n9050_s7.INIT=8'h7E;
- LUT3 n9051_s4 (
- .F(n9051_7),
- .I0(qxb[4]),
- .I1(qxb[3]),
- .I2(qxb[5])
+defparam n7272_s87.INIT=16'hBB0F;
+ LUT4 n7272_s88 (
+ .F(n7272_118),
+ .I0(sy_Z[2]),
+ .I1(n7272_120),
+ .I2(n7272_88),
+ .I3(sy_Z[3])
+);
+defparam n7272_s88.INIT=16'hBB0F;
+ LUT4 n7421_s76 (
+ .F(n7421_105),
+ .I0(n7421_110),
+ .I1(\score[3] [2]),
+ .I2(sy_Z[1]),
+ .I3(sy_Z[2])
);
-defparam n9051_s4.INIT=8'h07;
- LUT3 n9052_s6 (
- .F(n9052_9),
- .I0(qxb[2]),
- .I1(qxb[1]),
- .I2(qxb[4])
+defparam n7421_s76.INIT=16'h3553;
+ LUT4 n7421_s77 (
+ .F(n7421_106),
+ .I0(sy_Z[1]),
+ .I1(\score[6] [2]),
+ .I2(\score[5] [2]),
+ .I3(sy_Z[2])
+);
+defparam n7421_s77.INIT=16'hBB0F;
+ LUT4 n7421_s78 (
+ .F(n7421_107),
+ .I0(n7421_83),
+ .I1(n7421_111),
+ .I2(sy_Z[3]),
+ .I3(n7421_112)
);
-defparam n9052_s6.INIT=8'hE0;
- LUT4 n9052_s7 (
- .F(n9052_10),
- .I0(qxb[1]),
- .I1(qxb[0]),
- .I2(qxb[2]),
- .I3(qxb[3])
+defparam n7421_s78.INIT=16'h3500;
+ LUT4 n7421_s79 (
+ .F(n7421_108),
+ .I0(n7421_95),
+ .I1(n7421_97),
+ .I2(sx_Z[1]),
+ .I3(sx_Z[2])
);
-defparam n9052_s7.INIT=16'hFE00;
- LUT4 n11097_s31 (
- .F(n11097_34),
- .I0(n3881_9),
- .I1(sx_Z[6]),
- .I2(sx_Z[3]),
+defparam n7421_s79.INIT=16'hFCA0;
+ LUT4 n7421_s80 (
+ .F(n7421_109),
+ .I0(n7421_113),
+ .I1(n7421_99),
+ .I2(sx_Z[1]),
.I3(sx_Z[2])
);
-defparam n11097_s31.INIT=16'h4CCF;
- LUT4 n11097_s32 (
- .F(n11097_35),
- .I0(sx_Z[3]),
- .I1(n11097_41),
- .I2(n11097_42),
- .I3(sx_Z[6])
+defparam n7421_s80.INIT=16'h0C05;
+ LUT2 n6843_s20 (
+ .F(n6843_25),
+ .I0(score_counter[4]),
+ .I1(score_counter[2])
+);
+defparam n6843_s20.INIT=4'h4;
+ LUT2 n6843_s21 (
+ .F(n6843_26),
+ .I0(score_counter[3]),
+ .I1(score_counter[2])
+);
+defparam n6843_s21.INIT=4'h1;
+ LUT3 n6846_s14 (
+ .F(n6846_20),
+ .I0(score_counter[6]),
+ .I1(score_counter[5]),
+ .I2(score_counter[3])
+);
+defparam n6846_s14.INIT=8'hE3;
+ LUT3 n6846_s15 (
+ .F(n6846_21),
+ .I0(score_counter[6]),
+ .I1(score_counter[3]),
+ .I2(score_counter[5])
+);
+defparam n6846_s15.INIT=8'hE7;
+ LUT4 n6846_s16 (
+ .F(n6846_22),
+ .I0(score_counter[5]),
+ .I1(score_counter[4]),
+ .I2(score_counter[7]),
+ .I3(n3737_10)
+);
+defparam n6846_s16.INIT=16'h1000;
+ LUT3 n6846_s17 (
+ .F(n6846_23),
+ .I0(n6846_24),
+ .I1(score_counter[2]),
+ .I2(score_counter[4])
+);
+defparam n6846_s17.INIT=8'hE7;
+ LUT2 n190_s8 (
+ .F(n190_11),
+ .I0(qxb[5]),
+ .I1(qxb[6])
+);
+defparam n190_s8.INIT=4'h8;
+ LUT4 n3744_s25 (
+ .F(n3744_28),
+ .I0(n3744_37),
+ .I1(n3744_38),
+ .I2(n3744_39),
+ .I3(n3744_40)
+);
+defparam n3744_s25.INIT=16'hF100;
+ LUT3 n3744_s27 (
+ .F(n3744_30),
+ .I0(n3744_62),
+ .I1(qyb[4]),
+ .I2(qyb[5])
);
-defparam n11097_s32.INIT=16'hC4BF;
- LUT4 n11097_s33 (
- .F(n11097_36),
- .I0(n11097_41),
- .I1(n11097_43),
- .I2(sx_Z[6]),
- .I3(sx_Z[7])
+defparam n3744_s27.INIT=8'hE3;
+ LUT3 n3744_s28 (
+ .F(n3744_31),
+ .I0(n3744_42),
+ .I1(qxb[8]),
+ .I2(qx[8])
);
-defparam n11097_s33.INIT=16'hF5CF;
- LUT3 n11097_s34 (
- .F(n11097_37),
- .I0(n11097_44),
- .I1(sx_Z[4]),
- .I2(sx_Z[5])
+defparam n3744_s28.INIT=8'h4D;
+ LUT3 n3744_s29 (
+ .F(n3744_32),
+ .I0(qxb[7]),
+ .I1(qxb[8]),
+ .I2(square_11)
+);
+defparam n3744_s29.INIT=8'h10;
+ LUT4 n3744_s30 (
+ .F(n3744_33),
+ .I0(n3744_43),
+ .I1(n3744_44),
+ .I2(n3744_45),
+ .I3(n3744_46)
+);
+defparam n3744_s30.INIT=16'h00F1;
+ LUT4 n3744_s31 (
+ .F(n3744_34),
+ .I0(qxb[8]),
+ .I1(qx[8]),
+ .I2(square_18),
+ .I3(n3744_47)
);
-defparam n11097_s34.INIT=8'h40;
- LUT4 n11097_s35 (
- .F(n11097_38),
- .I0(n11097_45),
- .I1(sx_Z[7]),
- .I2(sx_Z[8]),
- .I3(sx_Z[6])
+defparam n3744_s31.INIT=16'h5DCF;
+ LUT4 n3744_s32 (
+ .F(n3744_35),
+ .I0(n3741_30),
+ .I1(bricks_active[14]),
+ .I2(bricks_active[8]),
+ .I3(n10660_5)
+);
+defparam n3744_s32.INIT=16'h0777;
+ LUT3 n3744_s33 (
+ .F(n3744_36),
+ .I0(n10660_4),
+ .I1(n10662_4),
+ .I2(n10661_4)
+);
+defparam n3744_s33.INIT=8'h01;
+ LUT4 n3735_s30 (
+ .F(n3735_33),
+ .I0(score_counter[3]),
+ .I1(score_counter[2]),
+ .I2(score_counter[1]),
+ .I3(score_counter[0])
+);
+defparam n3735_s30.INIT=16'h8000;
+ LUT4 n3735_s31 (
+ .F(n3735_34),
+ .I0(n3735_38),
+ .I1(n10667_4),
+ .I2(n10659_5),
+ .I3(score_counter[4])
+);
+defparam n3735_s31.INIT=16'h807F;
+ LUT2 n3735_s32 (
+ .F(n3735_35),
+ .I0(n3735_33),
+ .I1(n10662_4)
+);
+defparam n3735_s32.INIT=4'h8;
+ LUT4 n3735_s33 (
+ .F(n3735_36),
+ .I0(score_counter[0]),
+ .I1(n10666_4),
+ .I2(n10668_4),
+ .I3(score_counter[2])
+);
+defparam n3735_s33.INIT=16'hE800;
+ LUT4 n3735_s34 (
+ .F(n3735_37),
+ .I0(score_counter[5]),
+ .I1(score_counter[4]),
+ .I2(n3735_33),
+ .I3(n10671_4)
+);
+defparam n3735_s34.INIT=16'h8000;
+ LUT3 n3741_s21 (
+ .F(n3741_24),
+ .I0(qyb[2]),
+ .I1(qyb[3]),
+ .I2(qyb[4])
);
-defparam n11097_s35.INIT=16'hC4FC;
- LUT4 n11097_s36 (
- .F(n11097_39),
+defparam n3741_s21.INIT=8'hE0;
+ LUT4 n12765_s25 (
+ .F(n12765_28),
.I0(sx_Z[1]),
- .I1(sx_Z[2]),
- .I2(sx_Z[0]),
- .I3(n11097_46)
+ .I1(sx_Z[0]),
+ .I2(sx_Z[2]),
+ .I3(sx_Z[3])
);
-defparam n11097_s36.INIT=16'h7F00;
- LUT4 n11097_s37 (
- .F(n11097_40),
+defparam n12765_s25.INIT=16'h001F;
+ LUT4 n12765_s26 (
+ .F(n12765_29),
+ .I0(n4347_7),
+ .I1(n12765_47),
+ .I2(score_area_1_7),
+ .I3(sx_Z[6])
+);
+defparam n12765_s26.INIT=16'h30DF;
+ LUT4 n12765_s27 (
+ .F(n12765_30),
.I0(sx_Z[3]),
- .I1(sx_Z[1]),
- .I2(sx_Z[2]),
- .I3(sx_Z[4])
+ .I1(n12765_45),
+ .I2(sx_Z[6]),
+ .I3(n12765_38)
+);
+defparam n12765_s27.INIT=16'hFE0F;
+ LUT4 n12765_s28 (
+ .F(n12765_31),
+ .I0(n12765_39),
+ .I1(n12765_40),
+ .I2(sx_Z[5]),
+ .I3(sx_Z[6])
+);
+defparam n12765_s28.INIT=16'hAF30;
+ LUT4 n12765_s30 (
+ .F(n12765_33),
+ .I0(sx_Z[8]),
+ .I1(sx_Z[9]),
+ .I2(sx_Z[5]),
+ .I3(sx_Z[7])
+);
+defparam n12765_s30.INIT=16'h1000;
+ LUT4 n12765_s31 (
+ .F(n12765_34),
+ .I0(sx_Z[7]),
+ .I1(sx_Z[9]),
+ .I2(n12765_41),
+ .I3(sx_Z[8])
);
-defparam n11097_s37.INIT=16'hFE00;
- LUT3 square_s18 (
+defparam n12765_s31.INIT=16'h0100;
+ LUT4 n12765_s32 (
+ .F(n12765_35),
+ .I0(n12765_23),
+ .I1(bricks_active[16]),
+ .I2(bricks_active[12]),
+ .I3(n4347_6)
+);
+defparam n12765_s32.INIT=16'h0777;
+ LUT2 square_s18 (
.F(square_22),
- .I0(qx[2]),
- .I1(qx[3]),
- .I2(qx[4])
+ .I0(qx[5]),
+ .I1(sx_Z[5])
);
-defparam square_s18.INIT=8'h87;
+defparam square_s18.INIT=4'h4;
LUT4 square_s19 (
.F(square_23),
- .I0(qx[2]),
- .I1(sx_Z[3]),
- .I2(square_24),
- .I3(qx[3])
+ .I0(square_22),
+ .I1(square_27),
+ .I2(square_39),
+ .I3(square_28)
);
-defparam square_s19.INIT=16'hACC5;
- LUT3 ball_s11 (
- .F(ball_15),
- .I0(qxb[4]),
- .I1(n9048_9),
- .I2(sx_Z[4])
+defparam square_s19.INIT=16'h8CCF;
+ LUT4 square_s20 (
+ .F(square_24),
+ .I0(square_43),
+ .I1(sx_Z[5]),
+ .I2(square_28),
+ .I3(sx_Z[6])
);
-defparam ball_s11.INIT=8'h60;
- LUT4 ball_s12 (
- .F(ball_16),
- .I0(ball_24),
- .I1(sx_Z[3]),
- .I2(ball_19),
- .I3(ball_20)
+defparam square_s20.INIT=16'hF34D;
+ LUT4 ball_s19 (
+ .F(ball_23),
+ .I0(ball_27),
+ .I1(sx_Z[4]),
+ .I2(qxb[4]),
+ .I3(n10669_9)
);
-defparam ball_s12.INIT=16'h004D;
- LUT3 ball_s13 (
- .F(ball_17),
- .I0(n9048_9),
- .I1(qxb[4]),
- .I2(qxb[5])
+defparam ball_s19.INIT=16'h8EE8;
+ LUT3 ball_s20 (
+ .F(ball_24),
+ .I0(ball_41),
+ .I1(sx_Z[6]),
+ .I2(ball_37)
);
-defparam ball_s13.INIT=8'h4B;
- LUT3 n3741_s41 (
- .F(n3741_48),
- .I0(sy_Z[3]),
- .I1(n3741_49),
- .I2(n3741_53)
+defparam ball_s20.INIT=8'h0E;
+ LUT2 ball_s21 (
+ .F(ball_25),
+ .I0(ball_41),
+ .I1(sx_Z[6])
);
-defparam n3741_s41.INIT=8'hB2;
- LUT2 n3881_s5 (
- .F(n3881_9),
- .I0(sx_Z[0]),
- .I1(sx_Z[1])
+defparam ball_s21.INIT=4'h8;
+ LUT3 n4207_s42 (
+ .F(n4207_49),
+ .I0(sy_Z[5]),
+ .I1(n4207_70),
+ .I2(sy_Z[6])
);
-defparam n3881_s5.INIT=4'h8;
- LUT4 n3294_s45 (
- .F(n3294_48),
- .I0(qxb[2]),
- .I1(n3294_54),
- .I2(qx[2]),
- .I3(n3294_55)
+defparam n4207_s42.INIT=8'h07;
+ LUT4 n4207_s43 (
+ .F(n4207_50),
+ .I0(n4207_56),
+ .I1(n4207_57),
+ .I2(n4207_55),
+ .I3(n4207_58)
+);
+defparam n4207_s43.INIT=16'hEF00;
+ LUT4 n4207_s44 (
+ .F(n4207_51),
+ .I0(n4207_57),
+ .I1(n4207_56),
+ .I2(n4207_59),
+ .I3(n4207_55)
+);
+defparam n4207_s44.INIT=16'h000E;
+ LUT2 n4207_s47 (
+ .F(n4207_54),
+ .I0(qyb[0]),
+ .I1(qyb[1])
);
-defparam n3294_s45.INIT=16'h4300;
- LUT4 n3294_s46 (
- .F(n3294_49),
- .I0(qx[2]),
- .I1(qx[3]),
- .I2(n3294_56),
- .I3(n3294_57)
+defparam n4207_s47.INIT=4'h1;
+ LUT3 n7272_s89 (
+ .F(n7272_119),
+ .I0(\score_1[2] [2]),
+ .I1(\score_1[1] [2]),
+ .I2(sy_Z[1])
+);
+defparam n7272_s89.INIT=8'hCA;
+ LUT3 n7272_s90 (
+ .F(n7272_120),
+ .I0(\score_1[4] [4]),
+ .I1(\score_1[5] [4]),
+ .I2(sy_Z[1])
+);
+defparam n7272_s90.INIT=8'hCA;
+ LUT3 n7421_s81 (
+ .F(n7421_110),
+ .I0(\score[2] [2]),
+ .I1(\score[1] [2]),
+ .I2(sy_Z[1])
+);
+defparam n7421_s81.INIT=8'hCA;
+ LUT4 n7421_s82 (
+ .F(n7421_111),
+ .I0(\score[4] [4]),
+ .I1(\score[5] [4]),
+ .I2(sy_Z[2]),
+ .I3(sy_Z[1])
+);
+defparam n7421_s82.INIT=16'h0C0A;
+ LUT2 n7421_s83 (
+ .F(n7421_112),
+ .I0(sx_Z[1]),
+ .I1(sx_Z[2])
);
-defparam n3294_s46.INIT=16'hE177;
- LUT4 n3294_s47 (
- .F(n3294_50),
- .I0(qx[2]),
- .I1(n3294_55),
- .I2(qxb[2]),
- .I3(n3294_54)
+defparam n7421_s83.INIT=4'h8;
+ LUT4 n7421_s84 (
+ .F(n7421_113),
+ .I0(sy_Z[2]),
+ .I1(\score[5] [3]),
+ .I2(n7421_85),
+ .I3(sy_Z[3])
+);
+defparam n7421_s84.INIT=16'hBB0F;
+ LUT4 n6846_s18 (
+ .F(n6846_24),
+ .I0(score_counter[4]),
+ .I1(score_counter[7]),
+ .I2(score_counter[3]),
+ .I3(score_counter[5])
+);
+defparam n6846_s18.INIT=16'h7E17;
+ LUT2 n3744_s34 (
+ .F(n3744_37),
+ .I0(qx[5]),
+ .I1(qx[6])
);
-defparam n3294_s47.INIT=16'h0071;
- LUT4 n3294_s48 (
- .F(n3294_51),
- .I0(qx[4]),
- .I1(qxb[4]),
- .I2(qx[3]),
- .I3(qxb[3])
+defparam n3744_s34.INIT=4'h8;
+ LUT4 n3744_s35 (
+ .F(n3744_38),
+ .I0(qx[6]),
+ .I1(qx[5]),
+ .I2(ball_26),
+ .I3(ball_41)
+);
+defparam n3744_s35.INIT=16'hFCA0;
+ LUT4 n3744_s36 (
+ .F(n3744_39),
+ .I0(n3744_48),
+ .I1(n10669_9),
+ .I2(qx[4]),
+ .I3(qxb[4])
);
-defparam n3294_s48.INIT=16'hE0EE;
- LUT2 n3294_s49 (
- .F(n3294_52),
- .I0(qxb[4]),
- .I1(qx[4])
+defparam n3744_s36.INIT=16'hCEAF;
+ LUT4 n3744_s37 (
+ .F(n3744_40),
+ .I0(qx[6]),
+ .I1(ball_41),
+ .I2(ball_26),
+ .I3(qx[5])
);
-defparam n3294_s49.INIT=4'h8;
- LUT2 n11097_s38 (
- .F(n11097_41),
- .I0(sx_Z[4]),
- .I1(sx_Z[5])
+defparam n3744_s37.INIT=16'h1777;
+ LUT3 n3744_s39 (
+ .F(n3744_42),
+ .I0(qx[7]),
+ .I1(qxb[7]),
+ .I2(square_18)
);
-defparam n11097_s38.INIT=4'h1;
- LUT4 n11097_s39 (
- .F(n11097_42),
- .I0(sx_Z[0]),
- .I1(sx_Z[2]),
- .I2(sx_Z[3]),
- .I3(sx_Z[1])
+defparam n3744_s39.INIT=8'h2B;
+ LUT4 n3744_s40 (
+ .F(n3744_43),
+ .I0(qxb[5]),
+ .I1(qx[5]),
+ .I2(qx[6]),
+ .I3(square_39)
+);
+defparam n3744_s40.INIT=16'h0B0C;
+ LUT4 n3744_s41 (
+ .F(n3744_44),
+ .I0(square_39),
+ .I1(n3744_49),
+ .I2(qxb[6]),
+ .I3(qx[5])
);
-defparam n11097_s39.INIT=16'h31F3;
- LUT4 n11097_s40 (
- .F(n11097_43),
- .I0(sx_Z[2]),
- .I1(n11097_47),
- .I2(sx_Z[5]),
- .I3(n11097_46)
+defparam n3744_s41.INIT=16'h70C4;
+ LUT4 n3744_s42 (
+ .F(n3744_45),
+ .I0(n3744_66),
+ .I1(qxb[4]),
+ .I2(n3744_51),
+ .I3(n3744_52)
);
-defparam n11097_s40.INIT=16'h0D00;
- LUT4 n11097_s41 (
- .F(n11097_44),
- .I0(sx_Z[0]),
- .I1(sx_Z[1]),
- .I2(sx_Z[3]),
- .I3(sx_Z[2])
+defparam n3744_s42.INIT=16'h0017;
+ LUT4 n3744_s43 (
+ .F(n3744_46),
+ .I0(qx[5]),
+ .I1(square_39),
+ .I2(qx[6]),
+ .I3(qxb[6])
);
-defparam n11097_s41.INIT=16'h0001;
- LUT4 n11097_s42 (
- .F(n11097_45),
- .I0(sx_Z[2]),
- .I1(sx_Z[1]),
- .I2(n11097_46),
+defparam n3744_s43.INIT=16'h1E00;
+ LUT4 n3744_s44 (
+ .F(n3744_47),
+ .I0(qx[8]),
+ .I1(qxb[8]),
+ .I2(qxb[7]),
+ .I3(qx[7])
+);
+defparam n3744_s44.INIT=16'h73E5;
+ LUT4 n3735_s35 (
+ .F(n3735_38),
+ .I0(n10659_8),
+ .I1(n155_21),
+ .I2(bricks_active[0]),
+ .I3(n3735_33)
+);
+defparam n3735_s35.INIT=16'hB000;
+ LUT4 n12765_s35 (
+ .F(n12765_38),
+ .I0(sx_Z[6]),
+ .I1(n12765_42),
+ .I2(sx_Z[4]),
.I3(sx_Z[5])
);
-defparam n11097_s42.INIT=16'h8F00;
- LUT2 n11097_s43 (
- .F(n11097_46),
+defparam n12765_s35.INIT=16'h008F;
+ LUT4 n12765_s36 (
+ .F(n12765_39),
.I0(sx_Z[3]),
- .I1(sx_Z[4])
-);
-defparam n11097_s43.INIT=4'h1;
- LUT3 square_s20 (
- .F(square_24),
- .I0(qx[2]),
- .I1(sx_Z[2]),
- .I2(square_25)
+ .I1(sx_Z[0]),
+ .I2(n7421_112),
+ .I3(sx_Z[4])
);
-defparam square_s20.INIT=8'hBD;
- LUT3 ball_s15 (
- .F(ball_19),
- .I0(ball_21),
- .I1(ball_22),
+defparam n12765_s36.INIT=16'h007F;
+ LUT3 n12765_s37 (
+ .F(n12765_40),
+ .I0(sx_Z[3]),
+ .I1(sx_Z[4]),
.I2(sx_Z[2])
);
-defparam ball_s15.INIT=8'h2B;
- LUT3 ball_s16 (
- .F(ball_20),
- .I0(sx_Z[4]),
+defparam n12765_s37.INIT=8'h01;
+ LUT3 n12765_s38 (
+ .F(n12765_41),
+ .I0(n12765_43),
+ .I1(sx_Z[4]),
+ .I2(sx_Z[5])
+);
+defparam n12765_s38.INIT=8'h40;
+ LUT3 square_s23 (
+ .F(square_27),
+ .I0(sx_Z[5]),
+ .I1(qx[5]),
+ .I2(sx_Z[6])
+);
+defparam square_s23.INIT=8'hB0;
+ LUT4 square_s24 (
+ .F(square_28),
+ .I0(square_31),
+ .I1(square_32),
+ .I2(square_33),
+ .I3(square_34)
+);
+defparam square_s24.INIT=16'h0700;
+ LUT2 square_s26 (
+ .F(square_30),
+ .I0(qx[2]),
+ .I1(qx[3])
+);
+defparam square_s26.INIT=4'h8;
+ LUT3 ball_s22 (
+ .F(ball_26),
+ .I0(n10669_9),
.I1(qxb[4]),
- .I2(n9048_9)
+ .I2(qxb[5])
);
-defparam ball_s16.INIT=8'h41;
- LUT4 n3741_s42 (
- .F(n3741_49),
- .I0(n3741_51),
- .I1(sy_Z[2]),
- .I2(qyb[2]),
- .I3(n316_9)
+defparam ball_s22.INIT=8'h4B;
+ LUT4 ball_s23 (
+ .F(ball_27),
+ .I0(sx_Z[3]),
+ .I1(n12765_45),
+ .I2(n10658_9),
+ .I3(ball_30)
+);
+defparam ball_s23.INIT=16'hFAE8;
+ LUT2 n4207_s48 (
+ .F(n4207_55),
+ .I0(n4207_68),
+ .I1(qyb[4])
+);
+defparam n4207_s48.INIT=4'h4;
+ LUT4 n4207_s49 (
+ .F(n4207_56),
+ .I0(sy_Z[3]),
+ .I1(n4207_60),
+ .I2(n4207_61),
+ .I3(n4207_62)
+);
+defparam n4207_s49.INIT=16'h0B00;
+ LUT3 n4207_s50 (
+ .F(n4207_57),
+ .I0(qyb[4]),
+ .I1(n4207_68),
+ .I2(sy_Z[4])
+);
+defparam n4207_s50.INIT=8'h60;
+ LUT2 n4207_s51 (
+ .F(n4207_58),
+ .I0(qyb[5]),
+ .I1(sy_Z[5])
);
-defparam n3741_s42.INIT=16'h2BB2;
- LUT2 n3294_s51 (
- .F(n3294_54),
+defparam n4207_s51.INIT=4'h4;
+ LUT2 n4207_s52 (
+ .F(n4207_59),
+ .I0(sy_Z[5]),
+ .I1(qyb[5])
+);
+defparam n4207_s52.INIT=4'h4;
+ LUT3 n3744_s45 (
+ .F(n3744_48),
.I0(qx[3]),
- .I1(qxb[3])
+ .I1(qxb[3]),
+ .I2(n3744_53)
);
-defparam n3294_s51.INIT=4'h6;
- LUT4 n3294_s52 (
- .F(n3294_55),
- .I0(qx[1]),
- .I1(qx[0]),
- .I2(qxb[1]),
- .I3(qxb[0])
+defparam n3744_s45.INIT=8'h4D;
+ LUT4 n3744_s46 (
+ .F(n3744_49),
+ .I0(qx[5]),
+ .I1(qx[6]),
+ .I2(qxb[6]),
+ .I3(qxb[5])
);
-defparam n3294_s52.INIT=16'h8EAF;
- LUT4 n3294_s53 (
- .F(n3294_56),
- .I0(qxb[2]),
- .I1(qx[2]),
- .I2(qx[3]),
- .I3(qxb[3])
+defparam n3744_s46.INIT=16'h5CE0;
+ LUT4 n3744_s48 (
+ .F(n3744_51),
+ .I0(qx[2]),
+ .I1(qxb[3]),
+ .I2(n3744_54),
+ .I3(qx[3])
);
-defparam n3294_s53.INIT=16'hD3FE;
- LUT2 n3294_s54 (
- .F(n3294_57),
+defparam n3744_s48.INIT=16'hACC5;
+ LUT4 n3744_s49 (
+ .F(n3744_52),
.I0(qx[4]),
- .I1(qxb[4])
+ .I1(square_30),
+ .I2(qx[5]),
+ .I3(qxb[5])
);
-defparam n3294_s54.INIT=4'h9;
- LUT2 n11097_s44 (
- .F(n11097_47),
+defparam n3744_s49.INIT=16'h7800;
+ LUT3 n12765_s39 (
+ .F(n12765_42),
+ .I0(sx_Z[1]),
+ .I1(sx_Z[3]),
+ .I2(sx_Z[2])
+);
+defparam n12765_s39.INIT=8'h01;
+ LUT4 n12765_s40 (
+ .F(n12765_43),
.I0(sx_Z[0]),
- .I1(sx_Z[1])
+ .I1(sx_Z[1]),
+ .I2(sx_Z[3]),
+ .I3(sx_Z[2])
+);
+defparam n12765_s40.INIT=16'h0001;
+ LUT4 square_s27 (
+ .F(square_31),
+ .I0(qx[4]),
+ .I1(square_30),
+ .I2(sx_Z[4]),
+ .I3(sx_Z[3])
+);
+defparam square_s27.INIT=16'hF100;
+ LUT4 square_s28 (
+ .F(square_32),
+ .I0(sx_Z[2]),
+ .I1(square_35),
+ .I2(qx[3]),
+ .I3(qx[2])
+);
+defparam square_s28.INIT=16'hEE8F;
+ LUT4 square_s29 (
+ .F(square_33),
+ .I0(square_36),
+ .I1(qx[4]),
+ .I2(sx_Z[4]),
+ .I3(square_30)
+);
+defparam square_s29.INIT=16'hD400;
+ LUT4 square_s30 (
+ .F(square_34),
+ .I0(qx[4]),
+ .I1(qx[2]),
+ .I2(sx_Z[4]),
+ .I3(square_37)
+);
+defparam square_s30.INIT=16'hAFCE;
+ LUT4 ball_s26 (
+ .F(ball_30),
+ .I0(qxb[0]),
+ .I1(ball_31),
+ .I2(qxb[1]),
+ .I3(ball_32)
+);
+defparam ball_s26.INIT=16'h03FA;
+ LUT4 n4207_s53 (
+ .F(n4207_60),
+ .I0(n4207_63),
+ .I1(n319_6),
+ .I2(n4207_64),
+ .I3(sy_Z[2])
+);
+defparam n4207_s53.INIT=16'h32F3;
+ LUT2 n4207_s54 (
+ .F(n4207_61),
+ .I0(n4207_65),
+ .I1(qyb[3])
+);
+defparam n4207_s54.INIT=4'h4;
+ LUT4 n4207_s55 (
+ .F(n4207_62),
+ .I0(n4207_78),
+ .I1(sy_Z[4]),
+ .I2(qyb[4]),
+ .I3(n4207_68)
);
-defparam n11097_s44.INIT=4'h1;
- LUT4 square_s21 (
- .F(square_25),
+defparam n4207_s55.INIT=16'h8AFC;
+ LUT4 n3744_s50 (
+ .F(n3744_53),
+ .I0(qx[2]),
+ .I1(n3744_55),
+ .I2(n3744_56),
+ .I3(qxb[2])
+);
+defparam n3744_s50.INIT=16'hA8FE;
+ LUT4 n3744_s51 (
+ .F(n3744_54),
+ .I0(n3744_55),
+ .I1(n3744_56),
+ .I2(qx[2]),
+ .I3(qxb[2])
+);
+defparam n3744_s51.INIT=16'hFE1F;
+ LUT4 square_s31 (
+ .F(square_35),
.I0(qx[1]),
.I1(sx_Z[1]),
.I2(sx_Z[0]),
.I3(qx[0])
);
-defparam square_s21.INIT=16'hD4DD;
- LUT4 ball_s17 (
- .F(ball_21),
- .I0(sx_Z[0]),
- .I1(qxb[0]),
- .I2(sx_Z[1]),
- .I3(qxb[1])
+defparam square_s31.INIT=16'hD4DD;
+ LUT3 square_s32 (
+ .F(square_36),
+ .I0(sx_Z[2]),
+ .I1(square_35),
+ .I2(sx_Z[3])
+);
+defparam square_s32.INIT=8'h01;
+ LUT4 square_s33 (
+ .F(square_37),
+ .I0(sx_Z[2]),
+ .I1(square_35),
+ .I2(qx[2]),
+ .I3(qx[3])
);
-defparam ball_s17.INIT=16'h0D13;
- LUT3 ball_s18 (
- .F(ball_22),
+defparam square_s33.INIT=16'h0FF7;
+ LUT4 ball_s27 (
+ .F(ball_31),
.I0(qxb[0]),
+ .I1(sx_Z[1]),
+ .I2(sx_Z[0]),
+ .I3(sx_Z[2])
+);
+defparam ball_s27.INIT=16'h00BF;
+ LUT4 ball_s28 (
+ .F(ball_32),
+ .I0(ball_33),
.I1(qxb[1]),
- .I2(qxb[2])
+ .I2(sx_Z[2]),
+ .I3(qxb[2])
+);
+defparam ball_s28.INIT=16'hBF08;
+ LUT4 n4207_s56 (
+ .F(n4207_63),
+ .I0(qyb[1]),
+ .I1(qyb[0]),
+ .I2(qyb[2]),
+ .I3(qyb[3])
);
-defparam ball_s18.INIT=8'h1E;
- LUT4 n3741_s44 (
- .F(n3741_51),
+defparam n4207_s56.INIT=16'hFE00;
+ LUT4 n4207_s57 (
+ .F(n4207_64),
.I0(sy_Z[0]),
.I1(sy_Z[1]),
.I2(qyb[0]),
.I3(qyb[1])
);
-defparam n3741_s44.INIT=16'h3107;
- LUT4 n3294_s56 (
- .F(n3294_60),
- .I0(n9048_9),
- .I1(qxb[5]),
- .I2(qx[5]),
- .I3(qxb[4])
+defparam n4207_s57.INIT=16'h3107;
+ LUT4 n4207_s58 (
+ .F(n4207_65),
+ .I0(sy_Z[2]),
+ .I1(n4207_54),
+ .I2(qyb[2]),
+ .I3(n4207_64)
);
-defparam n3294_s56.INIT=16'hEB3C;
- LUT4 n3294_s57 (
- .F(n3294_62),
- .I0(n9048_9),
- .I1(qxb[4]),
- .I2(qxb[5]),
- .I3(qx[5])
+defparam n4207_s58.INIT=16'h8EEF;
+ LUT3 n3744_s52 (
+ .F(n3744_55),
+ .I0(qx[0]),
+ .I1(qxb[0]),
+ .I2(qxb[1])
+);
+defparam n3744_s52.INIT=8'h0B;
+ LUT4 n3744_s53 (
+ .F(n3744_56),
+ .I0(qx[0]),
+ .I1(qxb[0]),
+ .I2(qxb[1]),
+ .I3(qx[1])
+);
+defparam n3744_s53.INIT=16'hBF00;
+ LUT3 ball_s29 (
+ .F(ball_33),
+ .I0(sx_Z[0]),
+ .I1(qxb[0]),
+ .I2(sx_Z[1])
+);
+defparam ball_s29.INIT=8'h0D;
+ LUT4 ball_s30 (
+ .F(ball_35),
+ .I0(ball_11),
+ .I1(ball_43),
+ .I2(sx_Z[9]),
+ .I3(qxb[9])
+);
+defparam ball_s30.INIT=16'h7077;
+ LUT3 n3735_s36 (
+ .F(n3735_40),
+ .I0(n3735_44),
+ .I1(n3735_37),
+ .I2(score_counter[6])
+);
+defparam n3735_s36.INIT=8'h69;
+ LUT4 n3744_s54 (
+ .F(n3744_58),
+ .I0(n10658_4),
+ .I1(n3744_25),
+ .I2(n10659_4),
+ .I3(n3741_23)
+);
+defparam n3744_s54.INIT=16'h0004;
+ LUT4 n3736_s1 (
+ .F(n3736_5),
+ .I0(n3737_7),
+ .I1(n3735_42),
+ .I2(n3735_46),
+ .I3(n3735_7)
+);
+defparam n3736_s1.INIT=16'h40BF;
+ LUT4 n3735_s37 (
+ .F(n3735_42),
+ .I0(score_counter[0]),
+ .I1(n10654_4),
+ .I2(n3741_6),
+ .I3(n3739_10)
+);
+defparam n3735_s37.INIT=16'hF080;
+ LUT3 n3739_s16 (
+ .F(n3739_20),
+ .I0(n3741_6),
+ .I1(score_counter[0]),
+ .I2(n10654_4)
+);
+defparam n3739_s16.INIT=8'h80;
+ LUT4 n10654_s6 (
+ .F(n10654_10),
+ .I0(n191_6),
+ .I1(n187_6),
+ .I2(qxb[9]),
+ .I3(qxb[8])
+);
+defparam n10654_s6.INIT=16'h0400;
+ LUT3 n3741_s22 (
+ .F(n3741_26),
+ .I0(n3741_17),
+ .I1(qxb[9]),
+ .I2(qxb[8])
+);
+defparam n3741_s22.INIT=8'h10;
+ LUT4 n3738_s7 (
+ .F(n3738_11),
+ .I0(score_counter[2]),
+ .I1(n3739_13),
+ .I2(score_counter[0]),
+ .I3(n10662_4)
+);
+defparam n3738_s7.INIT=16'h2000;
+ LUT4 n4207_s60 (
+ .F(n4207_68),
+ .I0(qyb[3]),
+ .I1(qyb[2]),
+ .I2(qyb[0]),
+ .I3(qyb[1])
+);
+defparam n4207_s60.INIT=16'h0001;
+ LUT3 n6927_s1 (
+ .F(n6927_5),
+ .I0(n6880_4),
+ .I1(n6848),
+ .I2(n6925_4)
+);
+defparam n6927_s1.INIT=8'hBA;
+ LUT4 n6960_s2 (
+ .F(n6960_7),
+ .I0(n6847),
+ .I1(n6846),
+ .I2(n6843),
+ .I3(n6958_6)
+);
+defparam n6960_s2.INIT=16'h0B00;
+ LUT3 n7108_s1 (
+ .F(n7108_5),
+ .I0(n7061_6),
+ .I1(n7056),
+ .I2(n7106_4)
+);
+defparam n7108_s1.INIT=8'hEA;
+ LUT3 n3744_s55 (
+ .F(n3744_60),
+ .I0(ball_43),
+ .I1(qxb[7]),
+ .I2(qxb[8])
+);
+defparam n3744_s55.INIT=8'h80;
+ LUT4 n10661_s6 (
+ .F(n10661_10),
+ .I0(qxb[9]),
+ .I1(n155_21),
+ .I2(qxb[7]),
+ .I3(qxb[8])
);
-defparam n3294_s57.INIT=16'h4B00;
- LUT4 n9052_s8 (
- .F(n9052_12),
+defparam n10661_s6.INIT=16'h1000;
+ LUT4 n10663_s2 (
+ .F(n10663_6),
.I0(frame_Z),
- .I1(n9052_6),
- .I2(n9052_7),
- .I3(n9052_8)
-);
-defparam n9052_s8.INIT=16'h0800;
- LUT4 n9057_s2 (
- .F(n9057_6),
- .I0(n9054_5),
.I1(bricks_active[8]),
- .I2(n9054_6),
- .I3(n9051_4)
+ .I2(n10660_5),
+ .I3(n10657_5)
+);
+defparam n10663_s2.INIT=16'h8000;
+ LUT4 n10664_s3 (
+ .F(n10664_7),
+ .I0(n10660_5),
+ .I1(n10658_5),
+ .I2(n10658_6),
+ .I3(bricks_active[7])
+);
+defparam n10664_s3.INIT=16'hA800;
+ LUT4 n155_s6 (
+ .F(n155_24),
+ .I0(qxb[6]),
+ .I1(qxb[4]),
+ .I2(qxb[5]),
+ .I3(n191_6)
);
-defparam n9057_s2.INIT=16'h4000;
- LUT4 square_s22 (
- .F(square_27),
- .I0(qx[9]),
- .I1(qx[8]),
- .I2(square_20),
- .I3(sx_Z[9])
+defparam n155_s6.INIT=16'h0100;
+ LUT4 n4207_s61 (
+ .F(n4207_70),
+ .I0(n4207_68),
+ .I1(qyb[4]),
+ .I2(qyb[5]),
+ .I3(qyb[6])
);
-defparam square_s22.INIT=16'h80EA;
- LUT3 n11097_s45 (
- .F(n11097_49),
- .I0(n11097_26),
- .I1(sy_Z[5]),
- .I2(sy_Z[6])
+defparam n4207_s61.INIT=16'h4000;
+ LUT4 n3744_s56 (
+ .F(n3744_62),
+ .I0(qyb[3]),
+ .I1(qyb[2]),
+ .I2(qyb[0]),
+ .I3(qyb[1])
);
-defparam n11097_s45.INIT=8'h01;
- LUT3 n11097_s46 (
- .F(n11097_51),
- .I0(n11097_28),
- .I1(sy_Z[8]),
- .I2(sy_Z[9])
+defparam n3744_s56.INIT=16'h8000;
+ LUT4 n3735_s38 (
+ .F(n3735_44),
+ .I0(n3735_20),
+ .I1(n10669_4),
+ .I2(n3735_33),
+ .I3(n3735_26)
+);
+defparam n3735_s38.INIT=16'hEA00;
+ LUT4 n3737_s20 (
+ .F(n3737_24),
+ .I0(n10669_4),
+ .I1(n3735_33),
+ .I2(n3735_20),
+ .I3(n3737_18)
+);
+defparam n3737_s20.INIT=16'h8778;
+ LUT4 n3735_s39 (
+ .F(n3735_46),
+ .I0(score_counter[4]),
+ .I1(score_counter[3]),
+ .I2(n3739_12),
+ .I3(n3739_22)
+);
+defparam n3735_s39.INIT=16'h0028;
+ LUT4 n3741_s23 (
+ .F(n3741_28),
+ .I0(n3744_58),
+ .I1(n3744_68),
+ .I2(n3744_27),
+ .I3(n3741_19)
+);
+defparam n3741_s23.INIT=16'h56A9;
+ LUT4 n3735_s40 (
+ .F(n3735_48),
+ .I0(n3739_13),
+ .I1(n10658_4),
+ .I2(n3741_19),
+ .I3(n10657_4)
+);
+defparam n3735_s40.INIT=16'h4504;
+ LUT4 n317_s9 (
+ .F(n317_13),
+ .I0(qdy),
+ .I1(n319_6),
+ .I2(qyb[4]),
+ .I3(qyb[5])
);
-defparam n11097_s46.INIT=8'h01;
- LUT4 ball_s19 (
- .F(ball_24),
- .I0(qxb[2]),
- .I1(qxb[0]),
- .I2(qxb[1]),
- .I3(qxb[3])
+defparam n317_s9.INIT=16'h0008;
+ LUT3 n315_s7 (
+ .F(n315_11),
+ .I0(qyb[6]),
+ .I1(qyb[4]),
+ .I2(qyb[5])
);
-defparam ball_s19.INIT=16'hFE01;
- LUT4 n192_s5 (
- .F(n192_9),
- .I0(qxb[0]),
- .I1(qxb[1]),
- .I2(qxb[2]),
- .I3(qxb[3])
+defparam n315_s7.INIT=8'h01;
+ LUT3 n3744_s57 (
+ .F(n3744_64),
+ .I0(n3744_21),
+ .I1(qyb[7]),
+ .I2(qyb[8])
);
-defparam n192_s5.INIT=16'h001F;
- LUT4 square_s23 (
- .F(square_29),
- .I0(sx_Z[6]),
- .I1(qx[5]),
- .I2(n3294_37),
- .I3(qx[6])
+defparam n3744_s57.INIT=8'h80;
+ LUT4 n4207_s62 (
+ .F(n4207_72),
+ .I0(n4207_56),
+ .I1(qyb[4]),
+ .I2(n4207_68),
+ .I3(sy_Z[4])
);
-defparam square_s23.INIT=16'h5401;
- LUT4 n9050_s8 (
- .F(n9050_12),
- .I0(n9050_8),
- .I1(n9050_9),
- .I2(ball_11),
- .I3(frame_Z)
+defparam n4207_s62.INIT=16'h4155;
+ LUT4 n6923_s2 (
+ .F(n6923_7),
+ .I0(n6878_4),
+ .I1(n6880_4),
+ .I2(n6885_4),
+ .I3(n6909_5)
+);
+defparam n6923_s2.INIT=16'h0100;
+ LUT4 n6929_s1 (
+ .F(n6929_5),
+ .I0(n6895_6),
+ .I1(n6878_4),
+ .I2(n6880_4),
+ .I3(n6885_4)
+);
+defparam n6929_s1.INIT=16'hFFFE;
+ LUT4 n7066_s5 (
+ .F(n7066_9),
+ .I0(n7055),
+ .I1(n7054),
+ .I2(n7052),
+ .I3(n7053)
+);
+defparam n7066_s5.INIT=16'h0200;
+ LUT3 score_area_1_s7 (
+ .F(score_area_1_12),
+ .I0(sx_Z[4]),
+ .I1(sx_Z[5]),
+ .I2(score_area_1_8)
);
-defparam n9050_s8.INIT=16'h1F00;
- LUT4 n9063_s1 (
- .F(n9063_5),
- .I0(bricks_active[2]),
- .I1(n9061_4),
- .I2(frame_Z),
- .I3(n9051_5)
-);
-defparam n9063_s1.INIT=16'h8000;
- LUT4 n9051_s5 (
- .F(n9051_9),
- .I0(bricks_active[14]),
- .I1(n9049_5),
- .I2(frame_Z),
- .I3(n9051_5)
+defparam score_area_1_s7.INIT=8'hEF;
+ LUT4 ball_s31 (
+ .F(ball_37),
+ .I0(sx_Z[5]),
+ .I1(n10669_9),
+ .I2(qxb[4]),
+ .I3(qxb[5])
+);
+defparam ball_s31.INIT=16'h4510;
+ LUT4 ball_s32 (
+ .F(ball_39),
+ .I0(n10669_9),
+ .I1(qxb[4]),
+ .I2(qxb[5]),
+ .I3(sx_Z[5])
+);
+defparam ball_s32.INIT=16'h4B00;
+ LUT4 ball_s33 (
+ .F(ball_41),
+ .I0(n10669_9),
+ .I1(qxb[4]),
+ .I2(qxb[5]),
+ .I3(qxb[6])
+);
+defparam ball_s33.INIT=16'h40BF;
+ LUT3 n190_s9 (
+ .F(n190_13),
+ .I0(n192_4),
+ .I1(qxb[4]),
+ .I2(qxb[5])
+);
+defparam n190_s9.INIT=8'h80;
+ LUT4 n191_s5 (
+ .F(n191_9),
+ .I0(n155_24),
+ .I1(qxb[7]),
+ .I2(qxb[8]),
+ .I3(qxb[9])
+);
+defparam n191_s5.INIT=16'h0002;
+ LUT3 n3741_s24 (
+ .F(n3741_30),
+ .I0(n3741_16),
+ .I1(qyb[8]),
+ .I2(qyb[9])
+);
+defparam n3741_s24.INIT=8'h01;
+ LUT3 n319_s5 (
+ .F(n319_9),
+ .I0(n315_6),
+ .I1(qyb[8]),
+ .I2(qyb[9])
);
-defparam n9051_s5.INIT=16'h8000;
- LUT3 square_s24 (
- .F(square_31),
- .I0(qx[8]),
- .I1(square_20),
- .I2(sx_Z[8])
+defparam n319_s5.INIT=8'h02;
+ LUT4 n4207_s63 (
+ .F(n4207_74),
+ .I0(qyb[5]),
+ .I1(n4207_68),
+ .I2(qyb[4]),
+ .I3(qyb[6])
);
-defparam square_s24.INIT=8'h90;
- LUT4 n3294_s58 (
- .F(n3294_64),
- .I0(qx[7]),
- .I1(n9048_9),
- .I2(n155_8),
- .I3(qxb[7])
+defparam n4207_s63.INIT=16'h9A00;
+ LUT4 n4207_s64 (
+ .F(n4207_76),
+ .I0(qyb[5]),
+ .I1(n4207_68),
+ .I2(qyb[4]),
+ .I3(qyb[6])
);
-defparam n3294_s58.INIT=16'h4510;
- LUT4 square_s25 (
- .F(square_33),
- .I0(qx[5]),
- .I1(qx[2]),
- .I2(qx[3]),
- .I3(qx[4])
+defparam n4207_s64.INIT=16'hBADF;
+ LUT4 n6913_s2 (
+ .F(n6913_7),
+ .I0(n6878_4),
+ .I1(n6885_4),
+ .I2(n6895_6),
+ .I3(n6906_5)
+);
+defparam n6913_s2.INIT=16'h0100;
+ LUT3 n6905_s2 (
+ .F(n6905_7),
+ .I0(n6885_4),
+ .I1(n6895_6),
+ .I2(n6906_5)
+);
+defparam n6905_s2.INIT=8'h10;
+ LUT3 n6970_s2 (
+ .F(n6970_7),
+ .I0(n6888_5),
+ .I1(n6878_4),
+ .I2(n6906_5)
+);
+defparam n6970_s2.INIT=8'h10;
+ LUT3 n6962_s2 (
+ .F(n6962_7),
+ .I0(n6885_4),
+ .I1(n6878_4),
+ .I2(n6906_5)
+);
+defparam n6962_s2.INIT=8'h10;
+ LUT4 n6921_s2 (
+ .F(n6921_7),
+ .I0(n6880_4),
+ .I1(n6895_6),
+ .I2(n6878_4),
+ .I3(n6906_5)
+);
+defparam n6921_s2.INIT=16'h0100;
+ LUT4 n367_s6 (
+ .F(n367_11),
+ .I0(qyb[0]),
+ .I1(n3744_8),
+ .I2(qdy),
+ .I3(n319_9)
+);
+defparam n367_s6.INIT=16'h0054;
+ LUT4 n7102_s2 (
+ .F(n7102_7),
+ .I0(n7061_6),
+ .I1(n7076_4),
+ .I2(n7059_6),
+ .I3(n7087_5)
+);
+defparam n7102_s2.INIT=16'h0100;
+ LUT3 n4207_s65 (
+ .F(n4207_78),
+ .I0(n4207_64),
+ .I1(sy_Z[2]),
+ .I2(sy_Z[3])
);
-defparam square_s25.INIT=16'h9555;
- LUT4 n9058_s1 (
- .F(n9058_5),
- .I0(bricks_active[7]),
- .I1(n9054_5),
- .I2(n9054_6),
- .I3(n9052_12)
-);
-defparam n9058_s1.INIT=16'h2000;
- LUT4 n3741_s45 (
- .F(n3741_53),
- .I0(qyb[2]),
- .I1(qyb[0]),
- .I2(qyb[1]),
- .I3(qyb[3])
+defparam n4207_s65.INIT=8'h40;
+ LUT4 n4176_s36 (
+ .F(n4176_50),
+ .I0(sy_Z[2]),
+ .I1(sy_Z[3]),
+ .I2(sy_Z[1]),
+ .I3(sy_Z[4])
);
-defparam n3741_s45.INIT=16'h01FE;
- LUT4 n3741_s46 (
- .F(n3741_55),
- .I0(qyb[3]),
- .I1(qyb[2]),
- .I2(qyb[0]),
- .I3(qyb[1])
+defparam n4176_s36.INIT=16'h007F;
+ LUT4 n7272_s91 (
+ .F(n7272_122),
+ .I0(n7272_110),
+ .I1(sy_Z[1]),
+ .I2(sy_Z[2]),
+ .I3(sy_Z[3])
);
-defparam n3741_s46.INIT=16'h0001;
- LUT3 n3741_s47 (
- .F(n3741_57),
- .I0(n3741_55),
- .I1(qyb[4]),
- .I2(qyb[5])
+defparam n7272_s91.INIT=16'h1000;
+ LUT3 n12765_s41 (
+ .F(n12765_45),
+ .I0(sx_Z[0]),
+ .I1(sx_Z[1]),
+ .I2(sx_Z[2])
);
-defparam n3741_s47.INIT=8'h40;
- LUT4 n3741_s48 (
- .F(n3741_59),
- .I0(n3741_55),
- .I1(qyb[4]),
- .I2(qyb[5]),
- .I3(qyb[6])
+defparam n12765_s41.INIT=8'h80;
+ LUT3 n12765_s42 (
+ .F(n12765_47),
+ .I0(sx_Z[3]),
+ .I1(sx_Z[1]),
+ .I2(sx_Z[2])
);
-defparam n3741_s48.INIT=16'h4000;
- LUT4 n315_s4 (
- .F(n315_8),
- .I0(qyb[6]),
- .I1(n319_5),
- .I2(qyb[4]),
- .I3(qyb[5])
+defparam n12765_s42.INIT=8'h80;
+ LUT4 n12765_s43 (
+ .F(n12765_49),
+ .I0(sx_Z[3]),
+ .I1(sx_Z[4]),
+ .I2(sx_Z[1]),
+ .I3(sx_Z[2])
);
-defparam n315_s4.INIT=16'h8000;
- LUT4 n317_s8 (
- .F(n317_12),
- .I0(n319_5),
- .I1(qyb[4]),
- .I2(qyb[5]),
- .I3(qyb[6])
+defparam n12765_s43.INIT=16'h0111;
+ LUT3 n3744_s58 (
+ .F(n3744_66),
+ .I0(qx[4]),
+ .I1(qx[2]),
+ .I2(qx[3])
);
-defparam n317_s8.INIT=16'h7F80;
+defparam n3744_s58.INIT=8'h95;
+ LUT3 square_s34 (
+ .F(square_39),
+ .I0(qx[4]),
+ .I1(qx[2]),
+ .I2(qx[3])
+);
+defparam square_s34.INIT=8'h80;
+ LUT3 n3735_s41 (
+ .F(n3735_50),
+ .I0(score_counter[6]),
+ .I1(score_counter[5]),
+ .I2(n3735_34)
+);
+defparam n3735_s41.INIT=8'h08;
+ LUT4 n3735_s42 (
+ .F(n3735_52),
+ .I0(n10665_4),
+ .I1(n10666_4),
+ .I2(score_counter[5]),
+ .I3(n3735_34)
+);
+defparam n3735_s42.INIT=16'h00E0;
+ LUT4 n3735_s43 (
+ .F(n3735_54),
+ .I0(n3735_28),
+ .I1(n3737_14),
+ .I2(score_counter[5]),
+ .I3(n3735_34)
+);
+defparam n3735_s43.INIT=16'h0090;
+ LUT4 n3737_s21 (
+ .F(n3737_26),
+ .I0(n3737_17),
+ .I1(score_counter[3]),
+ .I2(score_counter[2]),
+ .I3(n10665_4)
+);
+defparam n3737_s21.INIT=16'h8000;
+ LUT4 n3737_s22 (
+ .F(n3737_28),
+ .I0(n3735_48),
+ .I1(n3735_42),
+ .I2(score_counter[3]),
+ .I3(score_counter[2])
+);
+defparam n3737_s22.INIT=16'hE000;
+ LUT4 n7143_s3 (
+ .F(n7143_9),
+ .I0(n7056),
+ .I1(n7066_9),
+ .I2(n7059_6),
+ .I3(n7087_5)
+);
+defparam n7143_s3.INIT=16'h0700;
+ LUT3 n7092_s2 (
+ .F(n7092_6),
+ .I0(n7059_6),
+ .I1(n7056),
+ .I2(n7066_9)
+);
+defparam n7092_s2.INIT=8'h15;
+ LUT3 n7145_s2 (
+ .F(n7145_7),
+ .I0(n7056),
+ .I1(n7066_9),
+ .I2(n7087_5)
+);
+defparam n7145_s2.INIT=8'h70;
+ LUT3 n7104_s2 (
+ .F(n7104_7),
+ .I0(n7056),
+ .I1(n7066_9),
+ .I2(n7102_7)
+);
+defparam n7104_s2.INIT=8'h70;
+ LUT3 n7086_s2 (
+ .F(n7086_7),
+ .I0(n7056),
+ .I1(n7066_9),
+ .I2(n7090_7)
+);
+defparam n7086_s2.INIT=8'h70;
+ LUT4 n7090_s2 (
+ .F(n7090_7),
+ .I0(n7056),
+ .I1(n7055),
+ .I2(n7076_5),
+ .I3(n7087_5)
+);
+defparam n7090_s2.INIT=16'hEF00;
+ LUT4 n7100_s1 (
+ .F(n7100_5),
+ .I0(n7056),
+ .I1(n7055),
+ .I2(n7076_5),
+ .I3(n7092_6)
+);
+defparam n7100_s1.INIT=16'h10FF;
LUT4 n162_s4 (
.F(n162_9),
.I0(qxb[0]),
- .I1(n191_6),
+ .I1(n191_9),
.I2(qdx),
- .I3(n190_5)
+ .I3(n190_4)
);
defparam n162_s4.INIT=16'h5510;
- LUT4 n3294_s59 (
- .F(n3294_66),
- .I0(bricks_active[4]),
- .I1(qyb[6]),
- .I2(n317_9),
- .I3(n9061_5)
+ LUT4 square_s35 (
+ .F(square_41),
+ .I0(qx[5]),
+ .I1(qx[6]),
+ .I2(square_39),
+ .I3(qx[7])
+);
+defparam square_s35.INIT=16'hFE01;
+ LUT4 ball_s34 (
+ .F(ball_43),
+ .I0(n10669_9),
+ .I1(qxb[4]),
+ .I2(qxb[5]),
+ .I3(qxb[6])
+);
+defparam ball_s34.INIT=16'h4000;
+ LUT4 n10659_s6 (
+ .F(n10659_10),
+ .I0(n10659_8),
+ .I1(qxb[4]),
+ .I2(qxb[5]),
+ .I3(qxb[6])
);
-defparam n3294_s59.INIT=16'h2000;
+defparam n10659_s6.INIT=16'h4000;
+ LUT3 n3737_s23 (
+ .F(n3737_30),
+ .I0(score_counter[1]),
+ .I1(score_counter[0]),
+ .I2(score_counter[3])
+);
+defparam n3737_s23.INIT=8'h80;
+ LUT4 n3739_s17 (
+ .F(n3739_22),
+ .I0(n3739_16),
+ .I1(score_counter[1]),
+ .I2(score_counter[0]),
+ .I3(n3739_7)
+);
+defparam n3739_s17.INIT=16'hBF40;
+ LUT4 n3737_s24 (
+ .F(n3737_32),
+ .I0(score_counter[1]),
+ .I1(score_counter[0]),
+ .I2(score_counter[3]),
+ .I3(n10664_7)
+);
+defparam n3737_s24.INIT=16'h8000;
+ LUT4 n3737_s25 (
+ .F(n3737_34),
+ .I0(score_counter[1]),
+ .I1(score_counter[0]),
+ .I2(n10659_4),
+ .I3(score_counter[2])
+);
+defparam n3737_s25.INIT=16'h8000;
+ LUT4 n3737_s26 (
+ .F(n3737_36),
+ .I0(score_counter[1]),
+ .I1(score_counter[0]),
+ .I2(n10660_4),
+ .I3(n3739_15)
+);
+defparam n3737_s26.INIT=16'h0080;
+ LUT4 n3739_s18 (
+ .F(n3739_24),
+ .I0(score_counter[1]),
+ .I1(score_counter[0]),
+ .I2(n10667_6),
+ .I3(n10667_7)
+);
+defparam n3739_s18.INIT=16'h8000;
+ LUT4 n3744_s59 (
+ .F(n3744_68),
+ .I0(n3744_23),
+ .I1(n3744_24),
+ .I2(n10667_6),
+ .I3(n10667_7)
+);
+defparam n3744_s59.INIT=16'hE000;
LUT4 n48_1_s1 (
.F(n48_1_4),
.I0(n48_4),
@@ -5291,10 +7872,125 @@ defparam n48_1_s1.INIT=16'hB0FF;
.F(n197_12),
.I0(qdx),
.I1(frame_Z),
- .I2(n191_6),
- .I3(n190_5)
+ .I2(n191_9),
+ .I3(n190_4)
);
defparam n197_s4.INIT=16'hAA6E;
+ LUT4 ball_s35 (
+ .F(ball_47),
+ .I0(ball_48),
+ .I1(sx_Z[9]),
+ .I2(qxb[9]),
+ .I3(n4180_40)
+);
+defparam ball_s35.INIT=16'h8A08;
+ LUT3 ball_s36 (
+ .F(ball_48),
+ .I0(sy_Z[9]),
+ .I1(qyb[9]),
+ .I2(n4194_40)
+);
+defparam ball_s36.INIT=8'hB2;
+ LUT4 n10655_s2 (
+ .F(n10655_6),
+ .I0(bricks_active[16]),
+ .I1(n3741_30),
+ .I2(n10661_10),
+ .I3(n10661_6)
+);
+defparam n10655_s2.INIT=16'h8000;
+ LUT4 n3740_s1 (
+ .F(n3740_5),
+ .I0(n3739_4),
+ .I1(n3741_6),
+ .I2(score_counter[0]),
+ .I3(n10654_4)
+);
+defparam n3740_s1.INIT=16'h6AAA;
+ LUT3 n4207_s66 (
+ .F(n4207_80),
+ .I0(qyb[7]),
+ .I1(n4207_70),
+ .I2(sy_Z[7])
+);
+defparam n4207_s66.INIT=8'h90;
+ LUT3 n4207_s67 (
+ .F(n4207_82),
+ .I0(sy_Z[7]),
+ .I1(qyb[7]),
+ .I2(n4207_70)
+);
+defparam n4207_s67.INIT=8'h14;
+ LUT4 n7151_s3 (
+ .F(n7151_9),
+ .I0(n7056),
+ .I1(n7066_9),
+ .I2(n7059_6),
+ .I3(n7087_5)
+);
+defparam n7151_s3.INIT=16'h0B00;
+ LUT3 n7153_s2 (
+ .F(n7153_7),
+ .I0(n7059_6),
+ .I1(n7066_9),
+ .I2(n7087_5)
+);
+defparam n7153_s2.INIT=8'h10;
+ LUT4 n10657_s3 (
+ .F(n10657_7),
+ .I0(frame_Z),
+ .I1(bricks_active[14]),
+ .I2(n3741_30),
+ .I3(n10657_5)
+);
+defparam n10657_s3.INIT=16'h8000;
+ LUT3 n3742_s1 (
+ .F(n3742_5),
+ .I0(n10654_4),
+ .I1(n10655_6),
+ .I2(n3741_28)
+);
+defparam n3742_s1.INIT=8'hE1;
+ LUT4 qdy_s5 (
+ .F(qdy_10),
+ .I0(n315_6),
+ .I1(qyb[8]),
+ .I2(qyb[9]),
+ .I3(n3744_9)
+);
+defparam qdy_s5.INIT=16'hFD00;
+ LUT4 ball_s37 (
+ .F(ball_50),
+ .I0(sx_Z[8]),
+ .I1(ball_43),
+ .I2(qxb[7]),
+ .I3(qxb[8])
+);
+defparam ball_s37.INIT=16'h1555;
+ LUT4 n7092_s3 (
+ .F(n7092_8),
+ .I0(n7061_6),
+ .I1(n7059_6),
+ .I2(n7056),
+ .I3(n7066_9)
+);
+defparam n7092_s3.INIT=16'hFEEE;
+ LUT4 n7094_s2 (
+ .F(n7094_7),
+ .I0(n7059_6),
+ .I1(n7056),
+ .I2(n7066_9),
+ .I3(n7090_7)
+);
+defparam n7094_s2.INIT=16'h1500;
+ LUT4 square_s36 (
+ .F(square_43),
+ .I0(qx[5]),
+ .I1(qx[4]),
+ .I2(qx[2]),
+ .I3(qx[3])
+);
+defparam square_s36.INIT=16'h8000;
DFFE qx_9_s0 (
.Q(qx[9]),
.D(n74_2),
@@ -5346,7 +8042,7 @@ defparam qx_0_s0.INIT=1'b0;
defparam qxb_9_s0.INIT=1'b0;
DFFE qxb_7_s0 (
.Q(qxb[7]),
- .D(n155_6),
+ .D(n155_19),
.CLK(clk_d),
.CE(qxb_9_6)
);
@@ -5423,51 +8119,428 @@ defparam qyb_2_s0.INIT=1'b0;
defparam qyb_1_s0.INIT=1'b0;
DFFE qyb_0_s0 (
.Q(qyb[0]),
- .D(n367_8),
+ .D(n367_11),
.CLK(clk_d),
.CE(qyb_6_5)
);
defparam qyb_0_s0.INIT=1'b0;
DFFE qdy_s0 (
.Q(qdy),
- .D(n3294_6),
+ .D(n3744_6),
.CLK(clk_d),
.CE(qdy_7)
);
+ DFFE score_counter_7_s0 (
+ .Q(score_counter[7]),
+ .D(n3735_3),
+ .CLK(clk_d),
+ .CE(frame_Z)
+);
+defparam score_counter_7_s0.INIT=1'b0;
+ DFFE score_counter_6_s0 (
+ .Q(score_counter[6]),
+ .D(n3736_5),
+ .CLK(clk_d),
+ .CE(frame_Z)
+);
+defparam score_counter_6_s0.INIT=1'b0;
+ DFFE score_counter_5_s0 (
+ .Q(score_counter[5]),
+ .D(n3737_3),
+ .CLK(clk_d),
+ .CE(frame_Z)
+);
+defparam score_counter_5_s0.INIT=1'b0;
+ DFFE score_counter_4_s0 (
+ .Q(score_counter[4]),
+ .D(n3738_3),
+ .CLK(clk_d),
+ .CE(frame_Z)
+);
+defparam score_counter_4_s0.INIT=1'b0;
+ DFFE score_counter_3_s0 (
+ .Q(score_counter[3]),
+ .D(n3739_3),
+ .CLK(clk_d),
+ .CE(frame_Z)
+);
+defparam score_counter_3_s0.INIT=1'b0;
+ DFFE score_counter_2_s0 (
+ .Q(score_counter[2]),
+ .D(n3740_5),
+ .CLK(clk_d),
+ .CE(frame_Z)
+);
+defparam score_counter_2_s0.INIT=1'b0;
+ DFFE score_counter_1_s0 (
+ .Q(score_counter[1]),
+ .D(n3741_3),
+ .CLK(clk_d),
+ .CE(frame_Z)
+);
+defparam score_counter_1_s0.INIT=1'b0;
+ DFFE score_counter_0_s0 (
+ .Q(score_counter[0]),
+ .D(n3742_5),
+ .CLK(clk_d),
+ .CE(frame_Z)
+);
+defparam score_counter_0_s0.INIT=1'b0;
DFFR square_s0 (
.Q(square),
- .D(n3710_46),
+ .D(n4176_46),
.CLK(clk_d),
.RESET(square_6)
);
DFFR ball_s0 (
.Q(ball),
- .D(n3741_33),
+ .D(n4207_33),
.CLK(clk_d),
.RESET(ball_6)
);
DFFS brick_s0 (
.Q(brick),
- .D(n3881_5),
+ .D(n4347_5),
+ .CLK(clk_d),
+ .SET(n12765_3)
+);
+ DFFS \score[6]_6_s0 (
+ .Q(\score[6] [6]),
+ .D(n6880_4),
+ .CLK(clk_d),
+ .SET(n6878_4)
+);
+ DFF \score[6]_5_s0 (
+ .Q(\score[6] [5]),
+ .D(n6905_7),
+ .CLK(clk_d)
+);
+ DFF \score[6]_4_s0 (
+ .Q(\score[6] [4]),
+ .D(n6906_5),
+ .CLK(clk_d)
+);
+ DFF \score[6]_2_s0 (
+ .Q(\score[6] [2]),
+ .D(n6909_5),
+ .CLK(clk_d)
+);
+ DFF \score[6]_1_s0 (
+ .Q(\score[6] [1]),
+ .D(n6911_3),
+ .CLK(clk_d)
+);
+ DFF \score[5]_6_s0 (
+ .Q(\score[5] [6]),
+ .D(n6913_7),
+ .CLK(clk_d)
+);
+ DFFS \score[5]_4_s0 (
+ .Q(\score[5] [4]),
+ .D(n6895_6),
+ .CLK(clk_d),
+ .SET(n6878_4)
+);
+ DFF \score[5]_3_s0 (
+ .Q(\score[5] [3]),
+ .D(n6919_3),
+ .CLK(clk_d)
+);
+ DFF \score[5]_2_s0 (
+ .Q(\score[5] [2]),
+ .D(n6921_7),
+ .CLK(clk_d)
+);
+ DFF \score[5]_1_s0 (
+ .Q(\score[5] [1]),
+ .D(n6923_7),
+ .CLK(clk_d)
+);
+ DFF \score[4]_6_s0 (
+ .Q(\score[4] [6]),
+ .D(n6925_3),
+ .CLK(clk_d)
+);
+ DFF \score[4]_5_s0 (
+ .Q(\score[4] [5]),
+ .D(n6927_5),
+ .CLK(clk_d)
+);
+ DFF \score[4]_4_s0 (
+ .Q(\score[4] [4]),
+ .D(n6929_5),
+ .CLK(clk_d)
+);
+ DFF \score[3]_6_s0 (
+ .Q(\score[3] [6]),
+ .D(n6937_3),
+ .CLK(clk_d)
+);
+ DFF \score[3]_5_s0 (
+ .Q(\score[3] [5]),
+ .D(n6939_3),
+ .CLK(clk_d)
+);
+ DFF \score[3]_4_s0 (
+ .Q(\score[3] [4]),
+ .D(n6941_3),
+ .CLK(clk_d)
+);
+ DFF \score[3]_3_s0 (
+ .Q(\score[3] [3]),
+ .D(n6944_5),
+ .CLK(clk_d)
+);
+ DFF \score[3]_2_s0 (
+ .Q(\score[3] [2]),
+ .D(n6946_5),
+ .CLK(clk_d)
+);
+ DFF \score[3]_1_s0 (
+ .Q(\score[3] [1]),
+ .D(n6948_3),
+ .CLK(clk_d)
+);
+ DFF \score[2]_6_s0 (
+ .Q(\score[2] [6]),
+ .D(n6950_3),
+ .CLK(clk_d)
+);
+ DFF \score[2]_5_s0 (
+ .Q(\score[2] [5]),
+ .D(n6952_5),
+ .CLK(clk_d)
+);
+ DFF \score[2]_4_s0 (
+ .Q(\score[2] [4]),
+ .D(n6954_3),
+ .CLK(clk_d)
+);
+ DFF \score[2]_2_s0 (
+ .Q(\score[2] [2]),
+ .D(n6958_5),
+ .CLK(clk_d)
+);
+ DFF \score[2]_1_s0 (
+ .Q(\score[2] [1]),
+ .D(n6960_7),
+ .CLK(clk_d)
+);
+ DFF \score[1]_6_s0 (
+ .Q(\score[1] [6]),
+ .D(n6962_7),
+ .CLK(clk_d)
+);
+ DFF \score[1]_5_s0 (
+ .Q(\score[1] [5]),
+ .D(n6964_5),
+ .CLK(clk_d)
+);
+ DFFS \score[1]_4_s0 (
+ .Q(\score[1] [4]),
+ .D(n6885_4),
+ .CLK(clk_d),
+ .SET(n6878_4)
+);
+ DFF \score[1]_2_s0 (
+ .Q(\score[1] [2]),
+ .D(n6970_7),
+ .CLK(clk_d)
+);
+ DFF \score[1]_1_s0 (
+ .Q(\score[1] [1]),
+ .D(n6972_5),
+ .CLK(clk_d)
+);
+ DFFS \score[0]_6_s0 (
+ .Q(\score[0] [6]),
+ .D(n6888_5),
+ .CLK(clk_d),
+ .SET(n6895_6)
+);
+ DFFS \score_1[6]_6_s0 (
+ .Q(\score_1[6] [6]),
+ .D(n7061_6),
+ .CLK(clk_d),
+ .SET(n7059_6)
+);
+ DFF \score_1[6]_5_s0 (
+ .Q(\score_1[6] [5]),
+ .D(n7086_7),
+ .CLK(clk_d)
+);
+ DFF \score_1[6]_4_s0 (
+ .Q(\score_1[6] [4]),
+ .D(n7087_5),
+ .CLK(clk_d)
+);
+ DFF \score_1[6]_2_s0 (
+ .Q(\score_1[6] [2]),
+ .D(n7090_7),
+ .CLK(clk_d)
+);
+ DFF \score_1[6]_1_s0 (
+ .Q(\score_1[6] [1]),
+ .D(n7092_8),
+ .CLK(clk_d)
+);
+ DFF \score_1[5]_6_s0 (
+ .Q(\score_1[5] [6]),
+ .D(n7094_7),
+ .CLK(clk_d)
+);
+ DFFS \score_1[5]_4_s0 (
+ .Q(\score_1[5] [4]),
+ .D(n7076_4),
+ .CLK(clk_d),
+ .SET(n7059_6)
+);
+ DFF \score_1[5]_3_s0 (
+ .Q(\score_1[5] [3]),
+ .D(n7100_5),
+ .CLK(clk_d)
+);
+ DFF \score_1[5]_2_s0 (
+ .Q(\score_1[5] [2]),
+ .D(n7102_7),
+ .CLK(clk_d)
+);
+ DFF \score_1[5]_1_s0 (
+ .Q(\score_1[5] [1]),
+ .D(n7104_7),
+ .CLK(clk_d)
+);
+ DFF \score_1[4]_6_s0 (
+ .Q(\score_1[4] [6]),
+ .D(n7106_3),
+ .CLK(clk_d)
+);
+ DFF \score_1[4]_5_s0 (
+ .Q(\score_1[4] [5]),
+ .D(n7108_5),
+ .CLK(clk_d)
+);
+ DFF \score_1[4]_4_s0 (
+ .Q(\score_1[4] [4]),
+ .D(n7110_3),
+ .CLK(clk_d)
+);
+ DFF \score_1[3]_6_s0 (
+ .Q(\score_1[3] [6]),
+ .D(n7118_3),
+ .CLK(clk_d)
+);
+ DFF \score_1[3]_5_s0 (
+ .Q(\score_1[3] [5]),
+ .D(n7120_3),
+ .CLK(clk_d)
+);
+ DFF \score_1[3]_4_s0 (
+ .Q(\score_1[3] [4]),
+ .D(n7122_3),
+ .CLK(clk_d)
+);
+ DFF \score_1[3]_3_s0 (
+ .Q(\score_1[3] [3]),
+ .D(n7125_5),
+ .CLK(clk_d)
+);
+ DFF \score_1[3]_2_s0 (
+ .Q(\score_1[3] [2]),
+ .D(n7127_5),
+ .CLK(clk_d)
+);
+ DFF \score_1[3]_1_s0 (
+ .Q(\score_1[3] [1]),
+ .D(n7129_3),
+ .CLK(clk_d)
+);
+ DFF \score_1[2]_6_s0 (
+ .Q(\score_1[2] [6]),
+ .D(n7131_3),
+ .CLK(clk_d)
+);
+ DFF \score_1[2]_5_s0 (
+ .Q(\score_1[2] [5]),
+ .D(n7133_5),
+ .CLK(clk_d)
+);
+ DFF \score_1[2]_4_s0 (
+ .Q(\score_1[2] [4]),
+ .D(n7135_3),
+ .CLK(clk_d)
+);
+ DFF \score_1[2]_2_s0 (
+ .Q(\score_1[2] [2]),
+ .D(n7139_5),
+ .CLK(clk_d)
+);
+ DFF \score_1[2]_1_s0 (
+ .Q(\score_1[2] [1]),
+ .D(n7141_5),
+ .CLK(clk_d)
+);
+ DFF \score_1[1]_6_s0 (
+ .Q(\score_1[1] [6]),
+ .D(n7143_9),
+ .CLK(clk_d)
+);
+ DFF \score_1[1]_5_s0 (
+ .Q(\score_1[1] [5]),
+ .D(n7145_7),
+ .CLK(clk_d)
+);
+ DFFS \score_1[1]_4_s0 (
+ .Q(\score_1[1] [4]),
+ .D(n7066_6),
+ .CLK(clk_d),
+ .SET(n7059_6)
+);
+ DFF \score_1[1]_2_s0 (
+ .Q(\score_1[1] [2]),
+ .D(n7151_9),
+ .CLK(clk_d)
+);
+ DFF \score_1[1]_1_s0 (
+ .Q(\score_1[1] [1]),
+ .D(n7153_7),
+ .CLK(clk_d)
+);
+ DFFS \score_1[0]_6_s0 (
+ .Q(\score_1[0] [6]),
+ .D(n7069_5),
+ .CLK(clk_d),
+ .SET(n7076_4)
+);
+ DFFR score_area_1_s0 (
+ .Q(score_area_1),
+ .D(n7272_106),
+ .CLK(clk_d),
+ .RESET(score_area_1_12)
+);
+ DFFR score_area_2_s0 (
+ .Q(score_area_2),
+ .D(n7421_101),
.CLK(clk_d),
- .SET(n11097_3)
+ .RESET(score_area_2_6)
);
DFFR red_7_s0 (
.Q(red_Z[7]),
- .D(ball),
+ .D(n7569_5),
.CLK(clk_d),
.RESET(square)
);
DFFR green_7_s0 (
.Q(green_Z[7]),
- .D(brick),
+ .D(n7553_5),
.CLK(clk_d),
- .RESET(n11074_3)
+ .RESET(n12742_3)
);
- DFF blue_7_s0 (
+ DFFS blue_7_s0 (
.Q(blue_Z[7]),
- .D(square),
- .CLK(clk_d)
+ .D(n7585_5),
+ .CLK(clk_d),
+ .SET(square)
);
DFFSE qyb_4_s1 (
.Q(qyb[4]),
@@ -5519,7 +8592,7 @@ defparam qxb_4_s2.INIT=1'b1;
defparam qxb_5_s2.INIT=1'b1;
DFFSE qxb_8_s2 (
.Q(qxb[8]),
- .D(n154_6),
+ .D(n154_8),
.CLK(clk_d),
.CE(qxb_9_6),
.SET(GND)
@@ -5561,7 +8634,7 @@ defparam qx_8_s1.INIT=1'b1;
.Q(bricks_active[0]),
.D(GND),
.CLK(clk_d),
- .CE(n9065_3),
+ .CE(n10671_3),
.SET(GND)
);
defparam bricks_active_0_s4.INIT=1'b1;
@@ -5569,7 +8642,7 @@ defparam bricks_active_0_s4.INIT=1'b1;
.Q(bricks_active[1]),
.D(GND),
.CLK(clk_d),
- .CE(n9064_3),
+ .CE(n10670_3),
.SET(GND)
);
defparam bricks_active_1_s4.INIT=1'b1;
@@ -5577,7 +8650,7 @@ defparam bricks_active_1_s4.INIT=1'b1;
.Q(bricks_active[2]),
.D(GND),
.CLK(clk_d),
- .CE(n9063_5),
+ .CE(n10669_3),
.SET(GND)
);
defparam bricks_active_2_s4.INIT=1'b1;
@@ -5585,7 +8658,7 @@ defparam bricks_active_2_s4.INIT=1'b1;
.Q(bricks_active[3]),
.D(GND),
.CLK(clk_d),
- .CE(n9062_3),
+ .CE(n10668_3),
.SET(GND)
);
defparam bricks_active_3_s4.INIT=1'b1;
@@ -5593,7 +8666,7 @@ defparam bricks_active_3_s4.INIT=1'b1;
.Q(bricks_active[4]),
.D(GND),
.CLK(clk_d),
- .CE(n9061_3),
+ .CE(n10667_3),
.SET(GND)
);
defparam bricks_active_4_s4.INIT=1'b1;
@@ -5601,7 +8674,7 @@ defparam bricks_active_4_s4.INIT=1'b1;
.Q(bricks_active[5]),
.D(GND),
.CLK(clk_d),
- .CE(n9060_3),
+ .CE(n10666_3),
.SET(GND)
);
defparam bricks_active_5_s4.INIT=1'b1;
@@ -5609,7 +8682,7 @@ defparam bricks_active_5_s4.INIT=1'b1;
.Q(bricks_active[6]),
.D(GND),
.CLK(clk_d),
- .CE(n9059_3),
+ .CE(n10665_3),
.SET(GND)
);
defparam bricks_active_6_s4.INIT=1'b1;
@@ -5617,7 +8690,7 @@ defparam bricks_active_6_s4.INIT=1'b1;
.Q(bricks_active[7]),
.D(GND),
.CLK(clk_d),
- .CE(n9058_5),
+ .CE(n10664_3),
.SET(GND)
);
defparam bricks_active_7_s4.INIT=1'b1;
@@ -5625,7 +8698,7 @@ defparam bricks_active_7_s4.INIT=1'b1;
.Q(bricks_active[8]),
.D(GND),
.CLK(clk_d),
- .CE(n9057_6),
+ .CE(n10663_6),
.SET(GND)
);
defparam bricks_active_8_s4.INIT=1'b1;
@@ -5633,7 +8706,7 @@ defparam bricks_active_8_s4.INIT=1'b1;
.Q(bricks_active[9]),
.D(GND),
.CLK(clk_d),
- .CE(n9056_3),
+ .CE(n10662_3),
.SET(GND)
);
defparam bricks_active_9_s4.INIT=1'b1;
@@ -5641,7 +8714,7 @@ defparam bricks_active_9_s4.INIT=1'b1;
.Q(bricks_active[10]),
.D(GND),
.CLK(clk_d),
- .CE(n9055_3),
+ .CE(n10661_3),
.SET(GND)
);
defparam bricks_active_10_s4.INIT=1'b1;
@@ -5649,7 +8722,7 @@ defparam bricks_active_10_s4.INIT=1'b1;
.Q(bricks_active[11]),
.D(GND),
.CLK(clk_d),
- .CE(n9054_3),
+ .CE(n10660_3),
.SET(GND)
);
defparam bricks_active_11_s4.INIT=1'b1;
@@ -5657,7 +8730,7 @@ defparam bricks_active_11_s4.INIT=1'b1;
.Q(bricks_active[12]),
.D(GND),
.CLK(clk_d),
- .CE(n9053_3),
+ .CE(n10659_3),
.SET(GND)
);
defparam bricks_active_12_s4.INIT=1'b1;
@@ -5665,7 +8738,7 @@ defparam bricks_active_12_s4.INIT=1'b1;
.Q(bricks_active[13]),
.D(GND),
.CLK(clk_d),
- .CE(n9052_3),
+ .CE(n10658_3),
.SET(GND)
);
defparam bricks_active_13_s4.INIT=1'b1;
@@ -5673,7 +8746,7 @@ defparam bricks_active_13_s4.INIT=1'b1;
.Q(bricks_active[14]),
.D(GND),
.CLK(clk_d),
- .CE(n9051_9),
+ .CE(n10657_7),
.SET(GND)
);
defparam bricks_active_14_s4.INIT=1'b1;
@@ -5681,7 +8754,7 @@ defparam bricks_active_14_s4.INIT=1'b1;
.Q(bricks_active[15]),
.D(GND),
.CLK(clk_d),
- .CE(n9050_3),
+ .CE(n10656_3),
.SET(GND)
);
defparam bricks_active_15_s4.INIT=1'b1;
@@ -5689,7 +8762,7 @@ defparam bricks_active_15_s4.INIT=1'b1;
.Q(bricks_active[16]),
.D(GND),
.CLK(clk_d),
- .CE(n9049_3),
+ .CE(n10655_3),
.SET(GND)
);
defparam bricks_active_16_s4.INIT=1'b1;
@@ -5697,7 +8770,7 @@ defparam bricks_active_16_s4.INIT=1'b1;
.Q(bricks_active[17]),
.D(GND),
.CLK(clk_d),
- .CE(n9048_3),
+ .CE(n10654_3),
.SET(GND)
);
defparam bricks_active_17_s4.INIT=1'b1;
@@ -5707,276 +8780,258 @@ defparam bricks_active_17_s4.INIT=1'b1;
.CLK(clk_d)
);
defparam qdx_s5.INIT=1'b0;
- ALU n3696_s20 (
- .SUM(n3696_21_SUM),
- .COUT(n3696_24),
+ ALU n4162_s20 (
+ .SUM(n4162_21_SUM),
+ .COUT(n4162_24),
.I0(VCC),
.I1(qx[0]),
.I3(GND),
.CIN(sx_Z[0])
);
-defparam n3696_s20.ALU_MODE=1;
- ALU n3696_s21 (
- .SUM(n3696_22_SUM),
- .COUT(n3696_26),
+defparam n4162_s20.ALU_MODE=1;
+ ALU n4162_s21 (
+ .SUM(n4162_22_SUM),
+ .COUT(n4162_26),
.I0(sx_Z[1]),
.I1(qx[1]),
.I3(GND),
- .CIN(n3696_24)
+ .CIN(n4162_24)
);
-defparam n3696_s21.ALU_MODE=1;
- ALU n3696_s22 (
- .SUM(n3696_23_SUM),
- .COUT(n3696_28),
+defparam n4162_s21.ALU_MODE=1;
+ ALU n4162_s22 (
+ .SUM(n4162_23_SUM),
+ .COUT(n4162_28),
.I0(sx_Z[2]),
.I1(qx[2]),
.I3(GND),
- .CIN(n3696_26)
+ .CIN(n4162_26)
);
-defparam n3696_s22.ALU_MODE=1;
- ALU n3696_s23 (
- .SUM(n3696_24_SUM),
- .COUT(n3696_30),
+defparam n4162_s22.ALU_MODE=1;
+ ALU n4162_s23 (
+ .SUM(n4162_24_SUM),
+ .COUT(n4162_30),
.I0(sx_Z[3]),
.I1(qx[3]),
.I3(GND),
- .CIN(n3696_28)
+ .CIN(n4162_28)
);
-defparam n3696_s23.ALU_MODE=1;
- ALU n3696_s24 (
- .SUM(n3696_25_SUM),
- .COUT(n3696_32),
+defparam n4162_s23.ALU_MODE=1;
+ ALU n4162_s24 (
+ .SUM(n4162_25_SUM),
+ .COUT(n4162_32),
.I0(sx_Z[4]),
.I1(qx[4]),
.I3(GND),
- .CIN(n3696_30)
+ .CIN(n4162_30)
);
-defparam n3696_s24.ALU_MODE=1;
- ALU n3696_s25 (
- .SUM(n3696_26_SUM),
- .COUT(n3696_34),
+defparam n4162_s24.ALU_MODE=1;
+ ALU n4162_s25 (
+ .SUM(n4162_26_SUM),
+ .COUT(n4162_34),
.I0(sx_Z[5]),
.I1(qx[5]),
.I3(GND),
- .CIN(n3696_32)
+ .CIN(n4162_32)
);
-defparam n3696_s25.ALU_MODE=1;
- ALU n3696_s26 (
- .SUM(n3696_27_SUM),
- .COUT(n3696_36),
+defparam n4162_s25.ALU_MODE=1;
+ ALU n4162_s26 (
+ .SUM(n4162_27_SUM),
+ .COUT(n4162_36),
.I0(sx_Z[6]),
.I1(qx[6]),
.I3(GND),
- .CIN(n3696_34)
+ .CIN(n4162_34)
);
-defparam n3696_s26.ALU_MODE=1;
- ALU n3696_s27 (
- .SUM(n3696_28_SUM),
- .COUT(n3696_38),
+defparam n4162_s26.ALU_MODE=1;
+ ALU n4162_s27 (
+ .SUM(n4162_28_SUM),
+ .COUT(n4162_38),
.I0(sx_Z[7]),
.I1(qx[7]),
.I3(GND),
- .CIN(n3696_36)
+ .CIN(n4162_36)
);
-defparam n3696_s27.ALU_MODE=1;
- ALU n3696_s28 (
- .SUM(n3696_29_SUM),
- .COUT(n3696_40),
+defparam n4162_s27.ALU_MODE=1;
+ ALU n4162_s28 (
+ .SUM(n4162_29_SUM),
+ .COUT(n4162_40),
.I0(sx_Z[8]),
.I1(qx[8]),
.I3(GND),
- .CIN(n3696_38)
+ .CIN(n4162_38)
);
-defparam n3696_s28.ALU_MODE=1;
- ALU n3696_s29 (
- .SUM(n3696_30_SUM),
- .COUT(n3696_42),
+defparam n4162_s28.ALU_MODE=1;
+ ALU n4162_s29 (
+ .SUM(n4162_30_SUM),
+ .COUT(n4162_42),
.I0(sx_Z[9]),
.I1(qx[9]),
.I3(GND),
- .CIN(n3696_40)
+ .CIN(n4162_40)
);
-defparam n3696_s29.ALU_MODE=1;
- ALU n3714_s20 (
- .SUM(n3714_21_SUM),
- .COUT(n3714_24),
+defparam n4162_s29.ALU_MODE=1;
+ ALU n4180_s20 (
+ .SUM(n4180_21_SUM),
+ .COUT(n4180_24),
.I0(VCC),
.I1(qxb[0]),
.I3(GND),
.CIN(sx_Z[0])
);
-defparam n3714_s20.ALU_MODE=1;
- ALU n3714_s21 (
- .SUM(n3714_22_SUM),
- .COUT(n3714_26),
+defparam n4180_s20.ALU_MODE=1;
+ ALU n4180_s21 (
+ .SUM(n4180_22_SUM),
+ .COUT(n4180_26),
.I0(sx_Z[1]),
.I1(qxb[1]),
.I3(GND),
- .CIN(n3714_24)
+ .CIN(n4180_24)
);
-defparam n3714_s21.ALU_MODE=1;
- ALU n3714_s22 (
- .SUM(n3714_23_SUM),
- .COUT(n3714_28),
+defparam n4180_s21.ALU_MODE=1;
+ ALU n4180_s22 (
+ .SUM(n4180_23_SUM),
+ .COUT(n4180_28),
.I0(sx_Z[2]),
.I1(qxb[2]),
.I3(GND),
- .CIN(n3714_26)
+ .CIN(n4180_26)
);
-defparam n3714_s22.ALU_MODE=1;
- ALU n3714_s23 (
- .SUM(n3714_24_SUM),
- .COUT(n3714_30),
+defparam n4180_s22.ALU_MODE=1;
+ ALU n4180_s23 (
+ .SUM(n4180_24_SUM),
+ .COUT(n4180_30),
.I0(sx_Z[3]),
.I1(qxb[3]),
.I3(GND),
- .CIN(n3714_28)
+ .CIN(n4180_28)
);
-defparam n3714_s23.ALU_MODE=1;
- ALU n3714_s24 (
- .SUM(n3714_25_SUM),
- .COUT(n3714_32),
+defparam n4180_s23.ALU_MODE=1;
+ ALU n4180_s24 (
+ .SUM(n4180_25_SUM),
+ .COUT(n4180_32),
.I0(sx_Z[4]),
.I1(qxb[4]),
.I3(GND),
- .CIN(n3714_30)
+ .CIN(n4180_30)
);
-defparam n3714_s24.ALU_MODE=1;
- ALU n3714_s25 (
- .SUM(n3714_26_SUM),
- .COUT(n3714_34),
+defparam n4180_s24.ALU_MODE=1;
+ ALU n4180_s25 (
+ .SUM(n4180_26_SUM),
+ .COUT(n4180_34),
.I0(sx_Z[5]),
.I1(qxb[5]),
.I3(GND),
- .CIN(n3714_32)
+ .CIN(n4180_32)
);
-defparam n3714_s25.ALU_MODE=1;
- ALU n3714_s26 (
- .SUM(n3714_27_SUM),
- .COUT(n3714_36),
+defparam n4180_s25.ALU_MODE=1;
+ ALU n4180_s26 (
+ .SUM(n4180_27_SUM),
+ .COUT(n4180_36),
.I0(sx_Z[6]),
.I1(qxb[6]),
.I3(GND),
- .CIN(n3714_34)
+ .CIN(n4180_34)
);
-defparam n3714_s26.ALU_MODE=1;
- ALU n3714_s27 (
- .SUM(n3714_28_SUM),
- .COUT(n3714_38),
+defparam n4180_s26.ALU_MODE=1;
+ ALU n4180_s27 (
+ .SUM(n4180_28_SUM),
+ .COUT(n4180_38),
.I0(sx_Z[7]),
.I1(qxb[7]),
.I3(GND),
- .CIN(n3714_36)
+ .CIN(n4180_36)
);
-defparam n3714_s27.ALU_MODE=1;
- ALU n3714_s28 (
- .SUM(n3714_29_SUM),
- .COUT(n3714_40),
+defparam n4180_s27.ALU_MODE=1;
+ ALU n4180_s28 (
+ .SUM(n4180_29_SUM),
+ .COUT(n4180_40),
.I0(sx_Z[8]),
.I1(qxb[8]),
.I3(GND),
- .CIN(n3714_38)
-);
-defparam n3714_s28.ALU_MODE=1;
- ALU n3714_s29 (
- .SUM(n3714_30_SUM),
- .COUT(n3714_42),
- .I0(sx_Z[9]),
- .I1(qxb[9]),
- .I3(GND),
- .CIN(n3714_40)
+ .CIN(n4180_38)
);
-defparam n3714_s29.ALU_MODE=1;
- ALU n3728_s20 (
- .SUM(n3728_21_SUM),
- .COUT(n3728_24),
+defparam n4180_s28.ALU_MODE=1;
+ ALU n4194_s20 (
+ .SUM(n4194_21_SUM),
+ .COUT(n4194_24),
.I0(VCC),
.I1(qyb[0]),
.I3(GND),
.CIN(sy_Z[0])
);
-defparam n3728_s20.ALU_MODE=1;
- ALU n3728_s21 (
- .SUM(n3728_22_SUM),
- .COUT(n3728_26),
+defparam n4194_s20.ALU_MODE=1;
+ ALU n4194_s21 (
+ .SUM(n4194_22_SUM),
+ .COUT(n4194_26),
.I0(sy_Z[1]),
.I1(qyb[1]),
.I3(GND),
- .CIN(n3728_24)
+ .CIN(n4194_24)
);
-defparam n3728_s21.ALU_MODE=1;
- ALU n3728_s22 (
- .SUM(n3728_23_SUM),
- .COUT(n3728_28),
+defparam n4194_s21.ALU_MODE=1;
+ ALU n4194_s22 (
+ .SUM(n4194_23_SUM),
+ .COUT(n4194_28),
.I0(sy_Z[2]),
.I1(qyb[2]),
.I3(GND),
- .CIN(n3728_26)
+ .CIN(n4194_26)
);
-defparam n3728_s22.ALU_MODE=1;
- ALU n3728_s23 (
- .SUM(n3728_24_SUM),
- .COUT(n3728_30),
+defparam n4194_s22.ALU_MODE=1;
+ ALU n4194_s23 (
+ .SUM(n4194_24_SUM),
+ .COUT(n4194_30),
.I0(sy_Z[3]),
.I1(qyb[3]),
.I3(GND),
- .CIN(n3728_28)
+ .CIN(n4194_28)
);
-defparam n3728_s23.ALU_MODE=1;
- ALU n3728_s24 (
- .SUM(n3728_25_SUM),
- .COUT(n3728_32),
+defparam n4194_s23.ALU_MODE=1;
+ ALU n4194_s24 (
+ .SUM(n4194_25_SUM),
+ .COUT(n4194_32),
.I0(sy_Z[4]),
.I1(qyb[4]),
.I3(GND),
- .CIN(n3728_30)
+ .CIN(n4194_30)
);
-defparam n3728_s24.ALU_MODE=1;
- ALU n3728_s25 (
- .SUM(n3728_26_SUM),
- .COUT(n3728_34),
+defparam n4194_s24.ALU_MODE=1;
+ ALU n4194_s25 (
+ .SUM(n4194_26_SUM),
+ .COUT(n4194_34),
.I0(sy_Z[5]),
.I1(qyb[5]),
.I3(GND),
- .CIN(n3728_32)
+ .CIN(n4194_32)
);
-defparam n3728_s25.ALU_MODE=1;
- ALU n3728_s26 (
- .SUM(n3728_27_SUM),
- .COUT(n3728_36),
+defparam n4194_s25.ALU_MODE=1;
+ ALU n4194_s26 (
+ .SUM(n4194_27_SUM),
+ .COUT(n4194_36),
.I0(sy_Z[6]),
.I1(qyb[6]),
.I3(GND),
- .CIN(n3728_34)
+ .CIN(n4194_34)
);
-defparam n3728_s26.ALU_MODE=1;
- ALU n3728_s27 (
- .SUM(n3728_28_SUM),
- .COUT(n3728_38),
+defparam n4194_s26.ALU_MODE=1;
+ ALU n4194_s27 (
+ .SUM(n4194_28_SUM),
+ .COUT(n4194_38),
.I0(sy_Z[7]),
.I1(qyb[7]),
.I3(GND),
- .CIN(n3728_36)
+ .CIN(n4194_36)
);
-defparam n3728_s27.ALU_MODE=1;
- ALU n3728_s28 (
- .SUM(n3728_29_SUM),
- .COUT(n3728_40),
+defparam n4194_s27.ALU_MODE=1;
+ ALU n4194_s28 (
+ .SUM(n4194_29_SUM),
+ .COUT(n4194_40),
.I0(sy_Z[8]),
.I1(qyb[8]),
.I3(GND),
- .CIN(n3728_38)
-);
-defparam n3728_s28.ALU_MODE=1;
- ALU n3728_s29 (
- .SUM(n3728_30_SUM),
- .COUT(n3728_42),
- .I0(sy_Z[9]),
- .I1(qyb[9]),
- .I3(GND),
- .CIN(n3728_40)
+ .CIN(n4194_38)
);
-defparam n3728_s29.ALU_MODE=1;
+defparam n4194_s28.ALU_MODE=1;
ALU n83_1_s (
.SUM(n83_2),
.COUT(n83_1_1),
@@ -6067,6 +9122,142 @@ defparam n75_1_s.ALU_MODE=2;
.CIN(n75_1_1)
);
defparam n74_1_s.ALU_MODE=2;
+ MUX2_LUT5 n7272_s92 (
+ .O(n7272_84),
+ .I0(n7273_13),
+ .I1(n7273_14),
+ .S0(sy_Z[2])
+);
+ MUX2_LUT5 n7272_s94 (
+ .O(n7272_86),
+ .I0(n7274_13),
+ .I1(n7274_14),
+ .S0(sy_Z[2])
+);
+ MUX2_LUT5 n7272_s67 (
+ .O(n7272_88),
+ .I0(n7275_13),
+ .I1(n7275_14),
+ .S0(sy_Z[2])
+);
+ MUX2_LUT5 n7272_s68 (
+ .O(n7272_90),
+ .I0(n7276_10),
+ .I1(n7276_11),
+ .S0(sy_Z[2])
+);
+ MUX2_LUT5 n7272_s96 (
+ .O(n7272_92),
+ .I0(n7278_13),
+ .I1(n7278_14),
+ .S0(sy_Z[2])
+);
+ MUX2_LUT5 n7421_s85 (
+ .O(n7421_79),
+ .I0(n7422_13),
+ .I1(n7422_14),
+ .S0(sy_Z[2])
+);
+ MUX2_LUT5 n7421_s87 (
+ .O(n7421_81),
+ .I0(n7423_13),
+ .I1(n7423_14),
+ .S0(sy_Z[2])
+);
+ MUX2_LUT5 n7421_s63 (
+ .O(n7421_83),
+ .I0(n7424_13),
+ .I1(n7424_14),
+ .S0(sy_Z[2])
+);
+ MUX2_LUT5 n7421_s64 (
+ .O(n7421_85),
+ .I0(n7425_10),
+ .I1(n7425_11),
+ .S0(sy_Z[2])
+);
+ MUX2_LUT5 n7421_s89 (
+ .O(n7421_87),
+ .I0(n7427_13),
+ .I1(n7427_14),
+ .S0(sy_Z[2])
+);
+ MUX2_LUT5 n7272_s93 (
+ .O(n7272_94),
+ .I0(n7273_17),
+ .I1(n7273_19),
+ .S0(sy_Z[2])
+);
+ MUX2_LUT5 n7272_s95 (
+ .O(n7272_96),
+ .I0(n7274_17),
+ .I1(n7274_19),
+ .S0(sy_Z[2])
+);
+ MUX2_LUT5 n7272_s97 (
+ .O(n7272_98),
+ .I0(n7278_17),
+ .I1(n7278_19),
+ .S0(sy_Z[2])
+);
+ MUX2_LUT5 n7421_s86 (
+ .O(n7421_89),
+ .I0(n7422_17),
+ .I1(n7422_19),
+ .S0(sy_Z[2])
+);
+ MUX2_LUT5 n7421_s88 (
+ .O(n7421_91),
+ .I0(n7423_17),
+ .I1(n7423_19),
+ .S0(sy_Z[2])
+);
+ MUX2_LUT5 n7421_s90 (
+ .O(n7421_93),
+ .I0(n7427_17),
+ .I1(n7427_19),
+ .S0(sy_Z[2])
+);
+ MUX2_LUT6 n7272_s73 (
+ .O(n7272_100),
+ .I0(n7272_84),
+ .I1(n7272_94),
+ .S0(sy_Z[3])
+);
+ MUX2_LUT6 n7272_s74 (
+ .O(n7272_102),
+ .I0(n7272_86),
+ .I1(n7272_96),
+ .S0(sy_Z[3])
+);
+ MUX2_LUT6 n7272_s75 (
+ .O(n7272_104),
+ .I0(n7272_92),
+ .I1(n7272_98),
+ .S0(sy_Z[3])
+);
+ MUX2_LUT6 n7421_s69 (
+ .O(n7421_95),
+ .I0(n7421_79),
+ .I1(n7421_89),
+ .S0(sy_Z[3])
+);
+ MUX2_LUT6 n7421_s70 (
+ .O(n7421_97),
+ .I0(n7421_81),
+ .I1(n7421_91),
+ .S0(sy_Z[3])
+);
+ MUX2_LUT6 n7421_s71 (
+ .O(n7421_99),
+ .I0(n7421_87),
+ .I1(n7421_93),
+ .S0(sy_Z[3])
+);
+ INV n6848_s6 (
+ .O(n6848),
+ .I(score_counter[0])
+);
VCC VCC_cZ (
.V(VCC)
);
@@ -6084,983 +9275,983 @@ endmodule /* game_loop */
`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
`pragma protect key_block
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+ww2KZwdaXeesK+tCgZJuV7rUoCMjQZpO7PYcHw==
`pragma protect encoding=(enctype="base64", line_length=76, bytes=55008)
`pragma protect data_keyowner="default-ip-vendor"
`pragma protect data_keyname="default-ip-key"
`pragma protect data_method="aes128-cfb"
`pragma protect data_block
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+rwYU
`pragma protect end_protected
module DVI_TX_Top (
clk_d,
@@ -7245,8 +10436,8 @@ wire GND;
);
game_loop arkanoid (
.clk_d(clk_d),
- .btn2_d(btn2_d),
.frame_Z(frame_Z),
+ .btn2_d(btn2_d),
.btn1_d(btn1_d),
.sx_Z(sx_Z[9:0]),
.sy_Z(sy_Z[9:0]),
diff --git a/impl/gwsynthesis/Nanoid20K_syn.rpt.html b/impl/gwsynthesis/Nanoid20K_syn.rpt.html
index 634d508..4eab22f 100644
--- a/impl/gwsynthesis/Nanoid20K_syn.rpt.html
+++ b/impl/gwsynthesis/Nanoid20K_syn.rpt.html
@@ -89,7 +89,7 @@
Created Time |
-Sat Jul 13 06:44:52 2024
+ | Sat Jul 13 08:05:23 2024
|
@@ -105,11 +105,11 @@
Synthesis Process |
-Running parser: CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.36s, Peak memory usage = 541.723MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.038s, Peak memory usage = 541.723MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 541.723MB Optimizing Phase 2: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.085s, Peak memory usage = 541.723MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 541.723MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 541.723MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 541.723MB Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 541.723MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.06s, Peak memory usage = 541.723MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 541.723MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 541.723MB Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 541.723MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.077s, Peak memory usage = 541.723MB Generate output files: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.066s, Peak memory usage = 541.723MB
|
+Running parser: CPU time = 0h 0m 0.437s, Elapsed time = 0h 0m 0.447s, Peak memory usage = 541.723MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.058s, Peak memory usage = 541.723MB Optimizing Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 541.723MB Optimizing Phase 2: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.113s, Peak memory usage = 541.723MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 541.723MB Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 541.723MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 541.723MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 541.723MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.096s, Peak memory usage = 541.723MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 541.723MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.029s, Peak memory usage = 541.723MB Tech-Mapping Phase 3: CPU time = 0h 0m 7s, Elapsed time = 0h 0m 7s, Peak memory usage = 541.723MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.128s, Peak memory usage = 541.723MB Generate output files: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.09s, Peak memory usage = 541.723MB
|
Total Time and Memory Usage |
-CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 541.723MB |
+CPU time = 0h 0m 8s, Elapsed time = 0h 0m 8s, Peak memory usage = 541.723MB |
@@ -141,19 +141,19 @@
Register |
-357 |
+427 |
    DFF |
-24 |
+75 |
    DFFE |
-20 |
+28 |
    DFFS |
-11 |
+20 |
    DFFSE |
@@ -161,7 +161,7 @@
    DFFR |
-12 |
+14 |
    DFFRE |
@@ -173,43 +173,43 @@
    DFFC |
-73 |
+72 |
    DFFCE |
-166 |
+167 |
LUT |
-742 |
+1057 |
    LUT2 |
-92 |
+147 |
    LUT3 |
-181 |
+270 |
    LUT4 |
-469 |
+640 |
ALU |
-139 |
+137 |
    ALU |
-139 |
+137 |
INV |
-11 |
+12 |
    INV |
-11 |
+12 |
IOLOGIC |
@@ -253,12 +253,12 @@
Logic |
-892(753 LUT, 139 ALU) / 20736 |
-5% |
+1206(1069 LUT, 137 ALU) / 20736 |
+6% |
Register |
-357 / 15750 |
+427 / 15750 |
3% |
@@ -268,7 +268,7 @@
  --Register as FF |
-357 / 15750 |
+427 / 15750 |
3% |
@@ -383,8 +383,8 @@
1 |
clk |
25.0(MHz) |
-149.6(MHz) |
-11 |
+118.0(MHz) |
+14 |
TOP |
@@ -854,11 +854,11 @@ Path 4
Slack |
-33.315 |
+31.528 |
Data Arrival Time |
-7.397 |
+9.184 |
Data Required Time |
@@ -866,11 +866,11 @@ Path 4
From |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_0_s0 |
+arkanoid/score_counter_7_s0 |
To |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0 |
+arkanoid/score_1[2]_1_s0 |
Launch Clk |
@@ -912,7 +912,7 @@ Path 4
0.587 |
tINS |
RR |
-206 |
+276 |
clk_ibuf/O |
@@ -921,15 +921,15 @@ Path 4
tNET |
RR |
1 |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_0_s0/CLK |
+arkanoid/score_counter_7_s0/CLK |
0.942 |
0.200 |
tC2Q |
RF |
-37 |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/din_d_0_s0/Q |
+14 |
+arkanoid/score_counter_7_s0/Q |
1.146 |
@@ -937,15 +937,15 @@ Path 4
tNET |
FF |
1 |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n688_s1/I1 |
+arkanoid/n7053_s12/I1 |
1.625 |
0.478 |
tINS |
FF |
-5 |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n688_s1/F |
+16 |
+arkanoid/n7053_s12/F |
1.829 |
@@ -953,151 +953,199 @@ Path 4
tNET |
FF |
1 |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s13/I1 |
+arkanoid/n7054_s15/I2 |
-2.308 |
-0.478 |
+2.220 |
+0.390 |
tINS |
FF |
1 |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s13/F |
+arkanoid/n7054_s15/F |
-2.512 |
+2.424 |
0.204 |
tNET |
FF |
1 |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s12/I1 |
+arkanoid/n7054_s13/I3 |
-2.990 |
-0.478 |
+2.744 |
+0.320 |
tINS |
FF |
-4 |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_3_s12/F |
+1 |
+arkanoid/n7054_s13/F |
-3.194 |
+2.948 |
0.204 |
tNET |
FF |
1 |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n630_s1/I2 |
+arkanoid/n7054_s12/I0 |
-3.585 |
-0.390 |
+3.394 |
+0.446 |
tINS |
FF |
-3 |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n630_s1/F |
+11 |
+arkanoid/n7054_s12/F |
-3.789 |
+3.598 |
0.204 |
tNET |
FF |
1 |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_2_s16/I0 |
+arkanoid/n7055_s20/I1 |
-4.235 |
-0.446 |
+4.076 |
+0.478 |
tINS |
FF |
-4 |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_one_9bit_2_s16/F |
+2 |
+arkanoid/n7055_s20/F |
-4.439 |
+4.281 |
0.204 |
tNET |
FF |
-2 |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n237_s5/I1 |
+1 |
+arkanoid/n7055_s19/I1 |
-4.931 |
-0.491 |
+4.759 |
+0.478 |
tINS |
-FR |
+FF |
+16 |
+arkanoid/n7055_s19/F |
+
+
+4.963 |
+0.204 |
+tNET |
+FF |
1 |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n237_s5/COUT |
+arkanoid/n7056_s22/I2 |
-4.931 |
-0.000 |
+5.354 |
+0.390 |
+tINS |
+FF |
+1 |
+arkanoid/n7056_s22/F |
+
+
+5.558 |
+0.204 |
tNET |
-RR |
-2 |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n236_s4/CIN |
+FF |
+1 |
+arkanoid/n7056_s21/I2 |
-5.336 |
-0.405 |
+5.949 |
+0.390 |
tINS |
-RF |
+FF |
1 |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n236_s4/SUM |
+arkanoid/n7056_s21/F |
-5.540 |
+6.153 |
0.204 |
tNET |
FF |
1 |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n603_s6/I3 |
+arkanoid/n7056_s20/I3 |
-5.860 |
+6.473 |
0.320 |
tINS |
FF |
+25 |
+arkanoid/n7056_s20/F |
+
+
+6.677 |
+0.204 |
+tNET |
+FF |
1 |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n603_s6/F |
+arkanoid/n7059_s3/I0 |
-6.064 |
+7.123 |
+0.446 |
+tINS |
+FF |
+12 |
+arkanoid/n7059_s3/F |
+
+
+7.327 |
0.204 |
tNET |
FF |
1 |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n603_s3/I0 |
+arkanoid/n7127_s1/I0 |
-6.510 |
+7.773 |
0.446 |
tINS |
FF |
+2 |
+arkanoid/n7127_s1/F |
+
+
+7.977 |
+0.204 |
+tNET |
+FF |
1 |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n603_s3/F |
+arkanoid/n7139_s1/I3 |
-6.714 |
+8.297 |
+0.320 |
+tINS |
+FF |
+2 |
+arkanoid/n7139_s1/F |
+
+
+8.501 |
0.204 |
tNET |
FF |
1 |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n603_s1/I1 |
+arkanoid/n7141_s1/I1 |
-7.192 |
+8.979 |
0.478 |
tINS |
FF |
1 |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n603_s1/F |
+arkanoid/n7141_s1/F |
-7.397 |
+9.184 |
0.204 |
tNET |
FF |
1 |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0/D |
+arkanoid/score_1[2]_1_s0/D |
Data Required Path:
@@ -1131,7 +1179,7 @@ Path 4
0.587 |
tINS |
RR |
-206 |
+276 |
clk_ibuf/O |
@@ -1140,7 +1188,7 @@ Path 4
tNET |
RR |
1 |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0/CLK |
+arkanoid/score_1[2]_1_s0/CLK |
40.712 |
@@ -1148,7 +1196,7 @@ Path 4
tSu |
|
1 |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/cnt_4_s0 |
+arkanoid/score_1[2]_1_s0 |
Path Statistics:
@@ -1163,12 +1211,12 @@ Path 4
Logic Level: |
-11 |
+14 |
Arrival Clock Path Delay: | cell: 0.587, 79.092%; route: 0.155, 20.908% |
-Arrival Data Path Delay: | cell: 4.412, 66.296%; route: 2.043, 30.699%; tC2Q: 0.200, 3.005% |
+Arrival Data Path Delay: | cell: 5.381, 63.750%; route: 2.860, 33.881%; tC2Q: 0.200, 2.369% |
Required Clock Path Delay: | cell: 0.587, 79.092%; route: 0.155, 20.908% |
@@ -1178,11 +1226,11 @@ Path 5
Slack |
-33.872 |
+32.108 |
Data Arrival Time |
-6.840 |
+8.604 |
Data Required Time |
@@ -1190,11 +1238,11 @@ Path 5
From |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0 |
+arkanoid/score_counter_7_s0 |
To |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0 |
+arkanoid/score_1[5]_1_s0 |
Launch Clk |
@@ -1236,7 +1284,7 @@ Path 5
0.587 |
tINS |
RR |
-206 |
+276 |
clk_ibuf/O |
@@ -1245,15 +1293,15 @@ Path 5
tNET |
RR |
1 |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0/CLK |
+arkanoid/score_counter_7_s0/CLK |
0.942 |
0.200 |
tC2Q |
RF |
-20 |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0/Q |
+14 |
+arkanoid/score_counter_7_s0/Q |
1.146 |
@@ -1261,15 +1309,15 @@ Path 5
tNET |
FF |
1 |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s20/I1 |
+arkanoid/n7053_s12/I1 |
1.625 |
0.478 |
tINS |
FF |
-1 |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s20/F |
+16 |
+arkanoid/n7053_s12/F |
1.829 |
@@ -1277,135 +1325,183 @@ Path 5
tNET |
FF |
1 |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s18/I1 |
+arkanoid/n7054_s15/I2 |
-2.308 |
-0.478 |
+2.220 |
+0.390 |
tINS |
FF |
-2 |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s18/F |
+1 |
+arkanoid/n7054_s15/F |
-2.512 |
+2.424 |
0.204 |
tNET |
FF |
1 |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15/I2 |
+arkanoid/n7054_s13/I3 |
-2.902 |
-0.390 |
+2.744 |
+0.320 |
tINS |
FF |
-4 |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s15/F |
+1 |
+arkanoid/n7054_s13/F |
-3.107 |
+2.948 |
0.204 |
tNET |
FF |
1 |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s14/I0 |
+arkanoid/n7054_s12/I0 |
-3.552 |
+3.394 |
0.446 |
tINS |
FF |
-4 |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_one_9bit_1_s14/F |
+11 |
+arkanoid/n7054_s12/F |
-3.757 |
+3.598 |
0.204 |
tNET |
FF |
-2 |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n238_s5/I1 |
+1 |
+arkanoid/n7055_s20/I1 |
-4.248 |
-0.491 |
+4.076 |
+0.478 |
tINS |
-FR |
+FF |
+2 |
+arkanoid/n7055_s20/F |
+
+
+4.281 |
+0.204 |
+tNET |
+FF |
1 |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n238_s5/COUT |
+arkanoid/n7055_s19/I1 |
-4.248 |
-0.000 |
+4.759 |
+0.478 |
+tINS |
+FF |
+16 |
+arkanoid/n7055_s19/F |
+
+
+4.963 |
+0.204 |
tNET |
-RR |
-2 |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n237_s5/CIN |
+FF |
+1 |
+arkanoid/n7056_s22/I2 |
-4.653 |
-0.405 |
+5.354 |
+0.390 |
tINS |
-RF |
-2 |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n237_s5/SUM |
+FF |
+1 |
+arkanoid/n7056_s22/F |
-4.857 |
+5.558 |
0.204 |
tNET |
FF |
1 |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n603_s6/I0 |
+arkanoid/n7056_s21/I2 |
-5.303 |
-0.446 |
+5.949 |
+0.390 |
tINS |
FF |
1 |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n603_s6/F |
+arkanoid/n7056_s21/F |
-5.507 |
+6.153 |
0.204 |
tNET |
FF |
1 |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n603_s3/I0 |
+arkanoid/n7056_s20/I3 |
-5.953 |
-0.446 |
+6.473 |
+0.320 |
tINS |
FF |
+25 |
+arkanoid/n7056_s20/F |
+
+
+6.677 |
+0.204 |
+tNET |
+FF |
1 |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n603_s3/F |
+arkanoid/n7076_s1/I0 |
+
+
+7.123 |
+0.446 |
+tINS |
+FF |
+4 |
+arkanoid/n7076_s1/F |
-6.157 |
+7.327 |
0.204 |
tNET |
FF |
1 |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n603_s1/I1 |
+arkanoid/n7102_s2/I1 |
-6.636 |
+7.805 |
0.478 |
tINS |
FF |
+2 |
+arkanoid/n7102_s2/F |
+
+
+8.010 |
+0.204 |
+tNET |
+FF |
+1 |
+arkanoid/n7104_s2/I2 |
+
+
+8.400 |
+0.390 |
+tINS |
+FF |
1 |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n603_s1/F |
+arkanoid/n7104_s2/F |
-6.840 |
+8.604 |
0.204 |
tNET |
FF |
1 |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0/D |
+arkanoid/score_1[5]_1_s0/D |
Data Required Path:
@@ -1439,7 +1535,7 @@ Path 5
0.587 |
tINS |
RR |
-206 |
+276 |
clk_ibuf/O |
@@ -1448,7 +1544,7 @@ Path 5
tNET |
RR |
1 |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0/CLK |
+arkanoid/score_1[5]_1_s0/CLK |
40.712 |
@@ -1456,7 +1552,7 @@ Path 5
tSu |
|
1 |
-DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0 |
+arkanoid/score_1[5]_1_s0 |
Path Statistics:
@@ -1471,12 +1567,12 @@ Path 5
Logic Level: |
-10 |
+13 |
Arrival Clock Path Delay: | cell: 0.587, 79.092%; route: 0.155, 20.908% |
-Arrival Data Path Delay: | cell: 4.059, 66.567%; route: 1.839, 30.153%; tC2Q: 0.200, 3.280% |
+Arrival Data Path Delay: | cell: 5.006, 63.677%; route: 2.656, 33.779%; tC2Q: 0.200, 2.544% |
Required Clock Path Delay: | cell: 0.587, 79.092%; route: 0.155, 20.908% |
diff --git a/impl/gwsynthesis/Nanoid20K_syn_resource.html b/impl/gwsynthesis/Nanoid20K_syn_resource.html
index b817cc3..6299dc6 100644
--- a/impl/gwsynthesis/Nanoid20K_syn_resource.html
+++ b/impl/gwsynthesis/Nanoid20K_syn_resource.html
@@ -41,7 +41,7 @@ Hierarchy Module Resource
(C:/Users/Petr/Documents/FPGA/Graphic 2/framebuffer/1/Nanoid20K/impl/gwsynthesis/RTL_GAO/gw_gao_top.v)
193 |
- |
-195 |
+191 |
- |
13 |
- |
@@ -50,16 +50,16 @@ Hierarchy Module Resource
(C:/Users/Petr/Documents/FPGA/Graphic 2/framebuffer/1/Nanoid20K/src/game_top.v)
56 |
30 |
-28 |
+29 |
- |
- |
- |
    |--arkanoid
(C:/Users/Petr/Documents/FPGA/Graphic 2/framebuffer/1/Nanoid20K/src/game_top.v) |
-56 |
-40 |
-310 |
+126 |
+38 |
+629 |
- |
- |
- |
diff --git a/impl/gwsynthesis/Nanoid20K_syn_rsc.xml b/impl/gwsynthesis/Nanoid20K_syn_rsc.xml
index dfb1c63..8abf5b0 100644
--- a/impl/gwsynthesis/Nanoid20K_syn_rsc.xml
+++ b/impl/gwsynthesis/Nanoid20K_syn_rsc.xml
@@ -1,8 +1,8 @@
-
-
-
+
+
+
diff --git a/impl/pnr/Nanoid20K.db b/impl/pnr/Nanoid20K.db
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diff --git a/impl/pnr/Nanoid20K.log b/impl/pnr/Nanoid20K.log
index 728b820..6d9d32f 100644
--- a/impl/pnr/Nanoid20K.log
+++ b/impl/pnr/Nanoid20K.log
@@ -25,5 +25,5 @@ Generate file "C:\Users\Petr\Documents\FPGA\Graphic 2\framebuffer\1\Nanoid20K\im
Generate file "C:\Users\Petr\Documents\FPGA\Graphic 2\framebuffer\1\Nanoid20K\impl\pnr\Nanoid20K.rpt.html" completed
Generate file "C:\Users\Petr\Documents\FPGA\Graphic 2\framebuffer\1\Nanoid20K\impl\pnr\Nanoid20K.rpt.txt" completed
Generate file "C:\Users\Petr\Documents\FPGA\Graphic 2\framebuffer\1\Nanoid20K\impl\pnr\Nanoid20K.tr.html" completed
-Sat Jul 13 06:44:58 2024
+Sat Jul 13 08:05:29 2024
diff --git a/impl/pnr/Nanoid20K.pin.html b/impl/pnr/Nanoid20K.pin.html
index 18d05c4..dc57cb7 100644
--- a/impl/pnr/Nanoid20K.pin.html
+++ b/impl/pnr/Nanoid20K.pin.html
@@ -78,7 +78,7 @@
Created Time |
-Sat Jul 13 06:44:58 2024
+ | Sat Jul 13 08:05:29 2024
|
diff --git a/impl/pnr/Nanoid20K.power.html b/impl/pnr/Nanoid20K.power.html
index dd0d297..a83484e 100644
--- a/impl/pnr/Nanoid20K.power.html
+++ b/impl/pnr/Nanoid20K.power.html
@@ -87,7 +87,7 @@
Created Time |
-Sat Jul 13 06:44:58 2024
+ | Sat Jul 13 08:05:29 2024
|
@@ -100,7 +100,7 @@
Total Power (mW) |
-186.943 |
+187.029 |
Quiescent Power (mW) |
@@ -108,7 +108,7 @@
Dynamic Power (mW) |
-82.761 |
+82.846 |
Psram Power (mW) |
@@ -119,7 +119,7 @@
Junction Temperature |
-29.010 |
+29.012 |
Theta JA |
@@ -127,7 +127,7 @@
Max Allowed Ambient Temperature |
-80.990 |
+80.988 |
@@ -196,9 +196,9 @@
VCC |
1.000 |
-66.923 |
+67.009 |
73.819 |
-140.742 |
+140.828 |
VCCX |
@@ -233,9 +233,9 @@
Logic |
-0.445 |
+0.531 |
NA |
-2.971 |
+3.007 |
IO |
@@ -265,8 +265,8 @@
game_top |
-65.820 |
-65.820(65.820) |
+65.906 |
+65.906(65.906) |
game_top/DVI_TX_Top_inst/ |
0.181 |
@@ -289,16 +289,16 @@
0.061(0.000) |
game_top/arkanoid/ |
-0.132 |
-0.132(0.000) |
+0.218 |
+0.218(0.000) |
game_top/gw_gao_inst_0/ |
-39.285 |
-39.285(39.285) |
+39.284 |
+39.284(39.284) |
game_top/gw_gao_inst_0/u_ao_top/ |
-39.282 |
-39.282(39.233) |
+39.281 |
+39.281(39.233) |
game_top/gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/ |
39.233 |
@@ -313,8 +313,8 @@
26.151(0.000) |
game_top/s480p/ |
-0.071 |
-0.071(0.000) |
+0.072 |
+0.072(0.000) |
@@ -324,16 +324,16 @@
Total Dynamic Power(mW) |
+clk |
+25.000 |
+48.429 |
+
+
tck_pad_i |
20.000 |
17.486 |
-clk |
-25.000 |
-48.343 |
-
-
rPLL/rpll_inst/CLKOUT.default_gen_clk |
250.000 |
0.034 |
diff --git a/impl/pnr/Nanoid20K.rpt.html b/impl/pnr/Nanoid20K.rpt.html
index a85f9f5..6a9f039 100644
--- a/impl/pnr/Nanoid20K.rpt.html
+++ b/impl/pnr/Nanoid20K.rpt.html
@@ -83,7 +83,7 @@
Created Time |
-Sat Jul 13 06:44:58 2024
+ | Sat Jul 13 08:05:29 2024
|
@@ -97,19 +97,19 @@
Place & Route Process |
Running placement:
- Placement Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.078s
- Placement Phase 1: CPU time = 0h 0m 0.257s, Elapsed time = 0h 0m 0.258s
- Placement Phase 2: CPU time = 0h 0m 0.129s, Elapsed time = 0h 0m 0.13s
+ Placement Phase 0: CPU time = 0h 0m 0.099s, Elapsed time = 0h 0m 0.099s
+ Placement Phase 1: CPU time = 0h 0m 0.263s, Elapsed time = 0h 0m 0.263s
+ Placement Phase 2: CPU time = 0h 0m 0.191s, Elapsed time = 0h 0m 0.191s
Placement Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s
- Total Placement: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s
+ Total Placement: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
Running routing:
Routing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s
- Routing Phase 1: CPU time = 0h 0m 0.305s, Elapsed time = 0h 0m 0.305s
- Routing Phase 2: CPU time = 0h 0m 0.628s, Elapsed time = 0h 0m 0.627s
+ Routing Phase 1: CPU time = 0h 0m 0.326s, Elapsed time = 0h 0m 0.326s
+ Routing Phase 2: CPU time = 0h 0m 0.717s, Elapsed time = 0h 0m 0.716s
Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
- Total Routing: CPU time = 0h 0m 0.933s, Elapsed time = 0h 0m 0.933s
+ Total Routing: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s
Generate output files:
- CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
+ CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s
|
@@ -129,12 +129,12 @@
Logic |
-915/20736 |
-5% |
+1229/20736 |
+6% |
    --LUT,ALU,ROM16 |
-915(746 LUT, 169 ALU, 0 ROM16) |
+1229(1062 LUT, 167 ALU, 0 ROM16) |
- |
@@ -144,7 +144,7 @@
Register |
-357/15750 |
+427/15750 |
3% |
@@ -154,7 +154,7 @@
    --Logic Register as FF |
-357/15552 |
+427/15552 |
3% |
@@ -169,8 +169,8 @@
CLS |
-602/10368 |
-6% |
+781/10368 |
+8% |
I/O Port |
diff --git a/impl/pnr/Nanoid20K.rpt.txt b/impl/pnr/Nanoid20K.rpt.txt
index c377cd3..ece7d53 100644
--- a/impl/pnr/Nanoid20K.rpt.txt
+++ b/impl/pnr/Nanoid20K.rpt.txt
@@ -12,25 +12,25 @@
: GW2AR-LV18QN88PFC9/I8
: GW2AR-18
: C
- :Sat Jul 13 06:44:58 2024
+ :Sat Jul 13 08:05:29 2024
2. PnR Details
Running placement:
- Placement Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.078s
- Placement Phase 1: CPU time = 0h 0m 0.257s, Elapsed time = 0h 0m 0.258s
- Placement Phase 2: CPU time = 0h 0m 0.129s, Elapsed time = 0h 0m 0.13s
+ Placement Phase 0: CPU time = 0h 0m 0.099s, Elapsed time = 0h 0m 0.099s
+ Placement Phase 1: CPU time = 0h 0m 0.263s, Elapsed time = 0h 0m 0.263s
+ Placement Phase 2: CPU time = 0h 0m 0.191s, Elapsed time = 0h 0m 0.191s
Placement Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s
- Total Placement: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s
+ Total Placement: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
Running routing:
Routing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s
- Routing Phase 1: CPU time = 0h 0m 0.305s, Elapsed time = 0h 0m 0.305s
- Routing Phase 2: CPU time = 0h 0m 0.628s, Elapsed time = 0h 0m 0.627s
+ Routing Phase 1: CPU time = 0h 0m 0.326s, Elapsed time = 0h 0m 0.326s
+ Routing Phase 2: CPU time = 0h 0m 0.717s, Elapsed time = 0h 0m 0.716s
Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
- Total Routing: CPU time = 0h 0m 0.933s, Elapsed time = 0h 0m 0.933s
+ Total Routing: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s
Generate output files:
- CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
+ CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s
Total Time and Memory Usage: CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s, Peak memory usage = 541MB
@@ -40,15 +40,15 @@
----------------------------------------------------------
Resources | Usage
----------------------------------------------------------
- Logic | 915/20736 5%
- --LUT,ALU,ROM16 | 915(746 LUT, 169 ALU, 0 ROM16)
+ Logic | 1229/20736 6%
+ --LUT,ALU,ROM16 | 1229(1062 LUT, 167 ALU, 0 ROM16)
--SSRAM(RAM16) | 0
- Register | 357/15750 3%
+ Register | 427/15750 3%
--Logic Register as Latch | 0/15552 0%
- --Logic Register as FF | 357/15552 3%
+ --Logic Register as FF | 427/15552 3%
--I/O Register as Latch | 0/198 0%
--I/O Register as FF | 0/198 0%
- CLS | 602/10368 6%
+ CLS | 781/10368 8%
I/O Port | 15
I/O Buf | 11
--Input Buf | 6
diff --git a/impl/pnr/Nanoid20K.timing_paths b/impl/pnr/Nanoid20K.timing_paths
index ab0a28c..b83e59c 100644
--- a/impl/pnr/Nanoid20K.timing_paths
+++ b/impl/pnr/Nanoid20K.timing_paths
@@ -1,7 +1,7 @@
=====
SETUP
-8.006
-2.726
+7.587
+3.144
10.732
gw_gao_inst_0/tck_ibuf
0.000
@@ -13,11 +13,11 @@ gw_gao_inst_0/u_ao_top/internal_reg_start_s1
1.848
2.048
gw_gao_inst_0/u_ao_top/internal_reg_start_syn_0_s0
-2.726
+3.144
=====
SETUP
-10.063
-1.720
+9.708
+2.075
11.783
clk_ibuf
0.000
@@ -26,422 +26,563 @@ gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_wr_s1
0.797
0.997
gw_gao_inst_0/u_ao_top/n836_s1
-1.400
-1.720
+1.584
+2.075
gw_gao_inst_0/u_ao_top/capture_end_tck_0_s0
-1.720
+2.075
=====
SETUP
-33.407
-7.360
+31.877
+8.890
40.767
clk_ibuf
0.000
0.587
-arkanoid/qxb_5_s2
+arkanoid/score_counter_4_s0
0.797
0.997
-arkanoid/n155_s4
-1.393
-1.839
-arkanoid/n9052_s3
-2.219
-2.609
-arkanoid/n3294_s37
-2.964
-3.442
-arkanoid/n3294_s20
-4.007
-4.499
-arkanoid/n3294_s9
-4.500
-4.820
-arkanoid/n3294_s4
-5.176
-5.654
-arkanoid/qxb_9_s2
-6.256
-6.730
-arkanoid/qxb_5_s2
-7.360
+arkanoid/n7053_s12
+1.370
+1.849
+arkanoid/n7054_s15
+1.871
+2.345
+arkanoid/n7054_s13
+2.469
+2.960
+arkanoid/n7054_s12
+2.961
+3.352
+arkanoid/n7055_s21
+3.709
+4.155
+arkanoid/n7055_s19
+4.720
+5.198
+arkanoid/n7056_s22
+5.225
+5.623
+arkanoid/n7056_s21
+5.624
+6.022
+arkanoid/n7056_s20
+6.023
+6.497
+arkanoid/n7059_s3
+6.506
+6.952
+arkanoid/n7127_s1
+7.331
+7.729
+arkanoid/n7139_s1
+7.731
+8.210
+arkanoid/score_1[2]_2_s0
+8.890
=====
SETUP
-33.407
-7.360
+32.184
+8.583
40.767
clk_ibuf
0.000
0.587
-arkanoid/qxb_5_s2
+arkanoid/score_counter_4_s0
0.797
0.997
-arkanoid/n155_s4
-1.393
-1.839
-arkanoid/n9052_s3
-2.219
-2.609
-arkanoid/n3294_s37
-2.964
-3.442
-arkanoid/n3294_s20
-4.007
-4.499
-arkanoid/n3294_s9
-4.500
-4.820
-arkanoid/n3294_s4
-5.176
-5.654
-arkanoid/qxb_9_s2
-6.256
-6.730
-arkanoid/qxb_4_s2
-7.360
+arkanoid/n7053_s12
+1.370
+1.849
+arkanoid/n7054_s15
+1.871
+2.345
+arkanoid/n7054_s13
+2.469
+2.960
+arkanoid/n7054_s12
+2.961
+3.352
+arkanoid/n7055_s21
+3.709
+4.155
+arkanoid/n7055_s19
+4.720
+5.198
+arkanoid/n7056_s22
+5.225
+5.623
+arkanoid/n7056_s21
+5.624
+6.022
+arkanoid/n7056_s20
+6.023
+6.497
+arkanoid/n7059_s3
+6.506
+6.952
+arkanoid/n7092_s2
+7.396
+7.875
+arkanoid/n7110_s0
+8.091
+8.583
+arkanoid/score_1[4]_4_s0
+8.583
=====
SETUP
-33.437
-7.330
+32.208
+8.558
40.767
clk_ibuf
0.000
0.587
-arkanoid/qxb_0_s0
+arkanoid/qyb_3_s0
0.797
0.997
-arkanoid/n9048_s6
-1.619
-2.010
-arkanoid/n9048_s4
-2.583
-2.973
-arkanoid/n9048_s2
-3.571
-3.961
-arkanoid/n3294_s29
-4.182
-4.655
-arkanoid/n3294_s13
-4.804
-5.194
-arkanoid/n3294_s6
-5.765
-6.210
-arkanoid/qdy_s3
-6.765
-7.047
-arkanoid/qdy_s0
-7.330
+arkanoid/n10667_s4
+1.615
+2.061
+arkanoid/n10667_s1
+2.421
+2.899
+arkanoid/n3739_s10
+3.490
+3.880
+arkanoid/n3737_s15
+4.851
+5.343
+arkanoid/n3737_s20
+5.492
+5.971
+arkanoid/n3737_s3
+6.335
+6.654
+arkanoid/n3735_s14
+6.872
+7.346
+arkanoid/n3735_s4
+7.494
+7.814
+arkanoid/n3736_s1
+8.160
+8.558
+arkanoid/score_counter_6_s0
+8.558
=====
SETUP
-33.514
-7.253
+32.212
+8.554
40.767
clk_ibuf
0.000
0.587
-arkanoid/qxb_0_s0
+arkanoid/score_counter_4_s0
0.797
0.997
-arkanoid/n9048_s6
-1.619
-2.010
-arkanoid/n9048_s4
-2.583
-2.973
-arkanoid/n9048_s2
-3.571
-3.961
-arkanoid/n3294_s29
-4.182
-4.655
-arkanoid/n3294_s13
-4.804
-5.194
-arkanoid/n3294_s6
-5.765
-6.210
-arkanoid/n3294_s3
-6.779
-7.253
-arkanoid/qdy_s0
-7.253
+arkanoid/n7053_s12
+1.370
+1.849
+arkanoid/n7054_s15
+1.871
+2.345
+arkanoid/n7054_s13
+2.469
+2.960
+arkanoid/n7054_s12
+2.961
+3.352
+arkanoid/n7055_s21
+3.709
+4.155
+arkanoid/n7055_s19
+4.720
+5.198
+arkanoid/n7056_s22
+5.225
+5.623
+arkanoid/n7056_s21
+5.624
+6.022
+arkanoid/n7056_s20
+6.023
+6.497
+arkanoid/n7059_s3
+6.506
+6.952
+arkanoid/n7092_s2
+7.396
+7.875
+arkanoid/n7100_s1
+8.234
+8.554
+arkanoid/score_1[5]_3_s0
+8.554
=====
SETUP
-33.565
-7.201
+32.222
+8.545
40.767
clk_ibuf
0.000
0.587
-arkanoid/qxb_5_s2
+arkanoid/score_counter_4_s0
0.797
0.997
-arkanoid/n155_s4
-1.393
-1.839
-arkanoid/n9052_s3
-2.219
-2.609
-arkanoid/n3294_s37
-2.964
-3.442
-arkanoid/n3294_s20
-4.007
-4.499
-arkanoid/n3294_s9
-4.500
-4.820
-arkanoid/n3294_s4
-5.176
-5.654
-arkanoid/qxb_9_s2
-6.256
-6.730
-arkanoid/qxb_0_s0
-7.201
+arkanoid/n7053_s12
+1.370
+1.849
+arkanoid/n7054_s15
+1.871
+2.345
+arkanoid/n7054_s13
+2.469
+2.960
+arkanoid/n7054_s12
+2.961
+3.352
+arkanoid/n7055_s21
+3.709
+4.155
+arkanoid/n7055_s19
+4.720
+5.198
+arkanoid/n7056_s22
+5.225
+5.623
+arkanoid/n7056_s21
+5.624
+6.022
+arkanoid/n7056_s20
+6.023
+6.497
+arkanoid/n7059_s3
+6.506
+6.952
+arkanoid/n7127_s1
+7.331
+7.729
+arkanoid/n7139_s1
+7.731
+8.223
+arkanoid/n7141_s1
+8.225
+8.545
+arkanoid/score_1[2]_1_s0
+8.545
=====
SETUP
-33.565
-7.201
+32.282
+8.484
40.767
clk_ibuf
0.000
0.587
-arkanoid/qxb_5_s2
+arkanoid/score_counter_5_s0
0.797
0.997
-arkanoid/n155_s4
-1.393
-1.839
-arkanoid/n9052_s3
-2.219
-2.609
-arkanoid/n3294_s37
+arkanoid/n6846_s18
+1.599
+2.090
+arkanoid/n6846_s17
+2.091
+2.489
+arkanoid/n6846_s13
+2.490
2.964
-3.442
-arkanoid/n3294_s20
-4.007
-4.499
-arkanoid/n3294_s9
-4.500
-4.820
-arkanoid/n3294_s4
-5.176
-5.654
-arkanoid/qxb_9_s2
-6.256
-6.730
-arkanoid/qxb_1_s0
-7.201
+arkanoid/n6846_s8
+2.965
+3.355
+arkanoid/n6843_s17
+3.370
+3.816
+arkanoid/n6845_s6
+4.255
+4.746
+arkanoid/n6845_s5
+4.895
+5.214
+arkanoid/n6843_s16
+5.392
+5.782
+arkanoid/n6878_s2
+5.805
+6.196
+arkanoid/n6895_s3
+6.573
+7.019
+arkanoid/n6909_s1
+7.248
+7.726
+arkanoid/n6923_s2
+8.086
+8.484
+arkanoid/score[5]_1_s0
+8.484
=====
SETUP
-33.565
-7.201
+32.365
+8.401
40.767
clk_ibuf
0.000
0.587
-arkanoid/qxb_5_s2
+arkanoid/score_counter_4_s0
0.797
0.997
-arkanoid/n155_s4
-1.393
-1.839
-arkanoid/n9052_s3
-2.219
-2.609
-arkanoid/n3294_s37
-2.964
-3.442
-arkanoid/n3294_s20
-4.007
-4.499
-arkanoid/n3294_s9
-4.500
-4.820
-arkanoid/n3294_s4
-5.176
-5.654
-arkanoid/qxb_9_s2
-6.256
-6.730
-arkanoid/qxb_2_s0
-7.201
+arkanoid/n7053_s12
+1.370
+1.849
+arkanoid/n7054_s15
+1.871
+2.345
+arkanoid/n7054_s13
+2.469
+2.960
+arkanoid/n7054_s12
+2.961
+3.352
+arkanoid/n7055_s21
+3.709
+4.155
+arkanoid/n7055_s19
+4.720
+5.198
+arkanoid/n7056_s22
+5.225
+5.623
+arkanoid/n7056_s21
+5.624
+6.022
+arkanoid/n7056_s20
+6.023
+6.497
+arkanoid/n7059_s3
+6.506
+6.952
+arkanoid/n7127_s1
+7.331
+7.721
+arkanoid/score_1[3]_2_s0
+8.401
=====
SETUP
-33.565
-7.201
+32.416
+8.351
40.767
clk_ibuf
0.000
0.587
-arkanoid/qxb_5_s2
+arkanoid/qxb_1_s0
0.797
0.997
-arkanoid/n155_s4
-1.393
-1.839
-arkanoid/n9052_s3
-2.219
-2.609
-arkanoid/n3294_s37
-2.964
-3.442
-arkanoid/n3294_s20
-4.007
-4.499
-arkanoid/n3294_s9
-4.500
-4.820
-arkanoid/n3294_s4
-5.176
-5.654
+arkanoid/n3744_s53
+1.591
+2.069
+arkanoid/n3744_s51
+2.286
+2.777
+arkanoid/n3744_s48
+2.926
+3.324
+arkanoid/n3744_s42
+3.325
+3.817
+arkanoid/n3744_s30
+3.965
+4.411
+arkanoid/n3744_s19
+4.896
+5.370
+arkanoid/n3744_s9
+5.518
+5.838
+arkanoid/qyb_9_s3
+6.290
+6.763
+arkanoid/qyb_9_s2
+6.914
+7.305
arkanoid/qxb_9_s2
-6.256
-6.730
-arkanoid/qxb_6_s0
-7.201
+7.324
+7.722
+arkanoid/qxb_3_s2
+8.351
=====
SETUP
-33.568
-7.198
+32.416
+8.351
40.767
clk_ibuf
0.000
0.587
-arkanoid/qxb_5_s2
+arkanoid/qxb_1_s0
0.797
0.997
-arkanoid/n155_s4
-1.393
-1.839
-arkanoid/n9052_s3
-2.219
-2.609
-arkanoid/n3294_s37
-2.964
-3.442
-arkanoid/n3294_s20
-4.007
-4.499
-arkanoid/n3294_s9
-4.500
-4.820
-arkanoid/n3294_s4
-5.176
-5.654
+arkanoid/n3744_s53
+1.591
+2.069
+arkanoid/n3744_s51
+2.286
+2.777
+arkanoid/n3744_s48
+2.926
+3.324
+arkanoid/n3744_s42
+3.325
+3.817
+arkanoid/n3744_s30
+3.965
+4.411
+arkanoid/n3744_s19
+4.896
+5.370
+arkanoid/n3744_s9
+5.518
+5.838
+arkanoid/qyb_9_s3
+6.290
+6.763
+arkanoid/qyb_9_s2
+6.914
+7.305
arkanoid/qxb_9_s2
-6.256
-6.730
-arkanoid/qxb_8_s2
-7.198
+7.324
+7.722
+arkanoid/qxb_1_s0
+8.351
=====
SETUP
-33.568
-7.198
+32.423
+8.343
40.767
clk_ibuf
0.000
0.587
-arkanoid/qxb_5_s2
+arkanoid/qxb_1_s0
0.797
0.997
-arkanoid/n155_s4
-1.393
-1.839
-arkanoid/n9052_s3
-2.219
-2.609
-arkanoid/n3294_s37
-2.964
-3.442
-arkanoid/n3294_s20
-4.007
-4.499
-arkanoid/n3294_s9
-4.500
-4.820
-arkanoid/n3294_s4
-5.176
-5.654
-arkanoid/qxb_9_s2
-6.256
-6.730
-arkanoid/qxb_3_s2
-7.198
+arkanoid/n10669_s6
+1.644
+2.123
+arkanoid/n10669_s3
+2.505
+2.896
+arkanoid/n10669_s1
+3.242
+3.561
+arkanoid/n3741_s16
+4.148
+4.594
+arkanoid/n3741_s10
+4.815
+5.288
+arkanoid/n3741_s3
+5.437
+5.756
+arkanoid/n3739_s7
+6.111
+6.431
+arkanoid/n3735_s37
+6.438
+6.829
+arkanoid/n3737_s22
+7.046
+7.524
+arkanoid/n3738_s0
+7.870
+8.343
+arkanoid/score_counter_4_s0
+8.343
=====
SETUP
-33.568
-7.198
+32.482
+8.285
40.767
clk_ibuf
0.000
0.587
-arkanoid/qxb_5_s2
+arkanoid/qyb_3_s0
0.797
0.997
-arkanoid/n155_s4
-1.393
-1.839
-arkanoid/n9052_s3
-2.219
-2.609
-arkanoid/n3294_s37
-2.964
-3.442
-arkanoid/n3294_s20
-4.007
-4.499
-arkanoid/n3294_s9
-4.500
-4.820
-arkanoid/n3294_s4
-5.176
-5.654
-arkanoid/qxb_9_s2
-6.256
-6.730
-arkanoid/qxb_7_s0
-7.198
+arkanoid/n10667_s4
+1.615
+2.061
+arkanoid/n10667_s1
+2.421
+2.899
+arkanoid/n3739_s10
+3.490
+3.880
+arkanoid/n3737_s15
+4.851
+5.343
+arkanoid/n3737_s20
+5.492
+5.971
+arkanoid/n3737_s3
+6.335
+6.654
+arkanoid/n3735_s14
+6.872
+7.346
+arkanoid/n3735_s4
+7.494
+7.814
+arkanoid/n3735_s0
+7.965
+8.285
+arkanoid/score_counter_7_s0
+8.285
=====
SETUP
-33.568
-7.198
+32.549
+8.217
40.767
clk_ibuf
0.000
0.587
-arkanoid/qxb_5_s2
+arkanoid/score_counter_4_s0
0.797
0.997
-arkanoid/n155_s4
-1.393
-1.839
-arkanoid/n9052_s3
-2.219
-2.609
-arkanoid/n3294_s37
-2.964
-3.442
-arkanoid/n3294_s20
-4.007
-4.499
-arkanoid/n3294_s9
-4.500
-4.820
-arkanoid/n3294_s4
-5.176
-5.654
-arkanoid/qxb_9_s2
-6.256
-6.730
-arkanoid/qxb_9_s0
-7.198
+arkanoid/n7053_s12
+1.370
+1.849
+arkanoid/n7054_s15
+1.871
+2.345
+arkanoid/n7054_s13
+2.469
+2.960
+arkanoid/n7054_s12
+2.961
+3.352
+arkanoid/n7055_s21
+3.709
+4.155
+arkanoid/n7055_s19
+4.720
+5.198
+arkanoid/n7056_s22
+5.225
+5.623
+arkanoid/n7056_s21
+5.624
+6.022
+arkanoid/n7056_s20
+6.023
+6.469
+arkanoid/n7131_s1
+7.104
+7.595
+arkanoid/n7131_s0
+7.744
+8.217
+arkanoid/score_1[2]_6_s0
+8.217
=====
SETUP
-22.775
-29.042
+23.315
+28.503
51.818
gw_gao_inst_0/tck_ibuf
25.000
@@ -452,18 +593,18 @@ gw_gao_inst_0/u_gw_jtag
gw_gao_inst_0/u_icon_top/enable_reg_2_s0
26.968
27.168
-gw_gao_inst_0/u_icon_top/n33_s1
-27.697
-28.142
+gw_gao_inst_0/u_icon_top/n33_s3
+27.320
+27.793
gw_gao_inst_0/u_icon_top/n33_s0
-28.355
-28.754
+27.794
+28.193
gw_gao_inst_0/u_icon_top/module_id_reg_0_s0
-29.042
+28.503
=====
SETUP
-22.775
-29.042
+23.315
+28.503
51.818
gw_gao_inst_0/tck_ibuf
25.000
@@ -474,18 +615,18 @@ gw_gao_inst_0/u_gw_jtag
gw_gao_inst_0/u_icon_top/enable_reg_2_s0
26.968
27.168
-gw_gao_inst_0/u_icon_top/n33_s1
-27.697
-28.142
+gw_gao_inst_0/u_icon_top/n33_s3
+27.320
+27.793
gw_gao_inst_0/u_icon_top/n33_s0
-28.355
-28.754
+27.794
+28.193
gw_gao_inst_0/u_icon_top/module_id_reg_1_s0
-29.042
+28.503
=====
SETUP
-22.775
-29.042
+23.315
+28.503
51.818
gw_gao_inst_0/tck_ibuf
25.000
@@ -496,18 +637,18 @@ gw_gao_inst_0/u_gw_jtag
gw_gao_inst_0/u_icon_top/enable_reg_2_s0
26.968
27.168
-gw_gao_inst_0/u_icon_top/n33_s1
-27.697
-28.142
+gw_gao_inst_0/u_icon_top/n33_s3
+27.320
+27.793
gw_gao_inst_0/u_icon_top/n33_s0
-28.355
-28.754
-gw_gao_inst_0/u_icon_top/module_id_reg_3_s0
-29.042
+27.794
+28.193
+gw_gao_inst_0/u_icon_top/module_id_reg_2_s0
+28.503
=====
SETUP
-22.939
-28.879
+23.315
+28.503
51.818
gw_gao_inst_0/tck_ibuf
25.000
@@ -518,18 +659,18 @@ gw_gao_inst_0/u_gw_jtag
gw_gao_inst_0/u_icon_top/enable_reg_2_s0
26.968
27.168
-gw_gao_inst_0/u_icon_top/n33_s1
-27.697
-28.142
+gw_gao_inst_0/u_icon_top/n33_s3
+27.320
+27.793
gw_gao_inst_0/u_icon_top/n33_s0
-28.355
-28.754
-gw_gao_inst_0/u_icon_top/module_id_reg_2_s0
-28.879
+27.794
+28.193
+gw_gao_inst_0/u_icon_top/module_id_reg_3_s0
+28.503
=====
SETUP
-23.020
-28.798
+23.388
+28.429
51.818
gw_gao_inst_0/tck_ibuf
25.000
@@ -537,18 +678,18 @@ gw_gao_inst_0/tck_ibuf
gw_gao_inst_0/u_gw_jtag
25.591
26.182
-gw_gao_inst_0/u_icon_top/enable_reg_2_s0
+gw_gao_inst_0/u_icon_top/enable_reg_1_s0
26.968
27.168
-gw_gao_inst_0/u_icon_top/n54_s1
-27.697
-28.170
+gw_gao_inst_0/u_icon_top/n54_s0
+27.310
+27.801
gw_gao_inst_0/u_icon_top/input_shift_reg_2_s0
-28.798
+28.429
=====
SETUP
-23.020
-28.798
+23.388
+28.429
51.818
gw_gao_inst_0/tck_ibuf
25.000
@@ -556,18 +697,18 @@ gw_gao_inst_0/tck_ibuf
gw_gao_inst_0/u_gw_jtag
25.591
26.182
-gw_gao_inst_0/u_icon_top/enable_reg_2_s0
+gw_gao_inst_0/u_icon_top/enable_reg_1_s0
26.968
27.168
-gw_gao_inst_0/u_icon_top/n54_s1
-27.697
-28.170
+gw_gao_inst_0/u_icon_top/n54_s0
+27.310
+27.801
gw_gao_inst_0/u_icon_top/input_shift_reg_3_s0
-28.798
+28.429
=====
SETUP
-23.020
-28.798
+23.388
+28.429
51.818
gw_gao_inst_0/tck_ibuf
25.000
@@ -575,18 +716,18 @@ gw_gao_inst_0/tck_ibuf
gw_gao_inst_0/u_gw_jtag
25.591
26.182
-gw_gao_inst_0/u_icon_top/enable_reg_2_s0
+gw_gao_inst_0/u_icon_top/enable_reg_1_s0
26.968
27.168
-gw_gao_inst_0/u_icon_top/n54_s1
-27.697
-28.170
+gw_gao_inst_0/u_icon_top/n54_s0
+27.310
+27.801
gw_gao_inst_0/u_icon_top/input_shift_reg_4_s0
-28.798
+28.429
=====
SETUP
-23.364
-28.454
+23.646
+28.172
51.818
gw_gao_inst_0/tck_ibuf
25.000
@@ -594,18 +735,15 @@ gw_gao_inst_0/tck_ibuf
gw_gao_inst_0/u_gw_jtag
25.591
26.182
-gw_gao_inst_0/u_icon_top/enable_reg_2_s0
+gw_gao_inst_0/u_icon_top/tdi_d_s0
26.968
27.168
-gw_gao_inst_0/u_icon_top/n54_s1
-27.697
-28.170
-gw_gao_inst_0/u_icon_top/input_shift_reg_0_s0
-28.454
+gw_gao_inst_0/u_ao_top/data_register_45_s0
+28.172
=====
SETUP
-23.364
-28.454
+23.732
+28.085
51.818
gw_gao_inst_0/tck_ibuf
25.000
@@ -613,18 +751,18 @@ gw_gao_inst_0/tck_ibuf
gw_gao_inst_0/u_gw_jtag
25.591
26.182
-gw_gao_inst_0/u_icon_top/enable_reg_2_s0
+gw_gao_inst_0/u_icon_top/enable_reg_1_s0
26.968
27.168
-gw_gao_inst_0/u_icon_top/n54_s1
-27.697
-28.170
-gw_gao_inst_0/u_icon_top/input_shift_reg_1_s0
-28.454
+gw_gao_inst_0/u_icon_top/n54_s0
+27.310
+27.801
+gw_gao_inst_0/u_icon_top/input_shift_reg_0_s0
+28.085
=====
SETUP
-23.527
-28.290
+23.732
+28.085
51.818
gw_gao_inst_0/tck_ibuf
25.000
@@ -632,15 +770,18 @@ gw_gao_inst_0/tck_ibuf
gw_gao_inst_0/u_gw_jtag
25.591
26.182
-gw_gao_inst_0/u_icon_top/tdi_d_s0
+gw_gao_inst_0/u_icon_top/enable_reg_1_s0
26.968
27.168
-gw_gao_inst_0/u_ao_top/data_register_45_s0
-28.290
+gw_gao_inst_0/u_icon_top/n54_s0
+27.310
+27.801
+gw_gao_inst_0/u_icon_top/input_shift_reg_1_s0
+28.085
=====
SETUP
-23.736
-28.081
+23.946
+27.872
51.818
gw_gao_inst_0/tck_ibuf
25.000
@@ -652,40 +793,40 @@ gw_gao_inst_0/u_icon_top/tdi_d_s0
26.968
27.168
gw_gao_inst_0/u_icon_top/input_shift_reg_4_s0
-28.081
+27.872
=====
HOLD
--0.423
-1.271
+-0.473
+1.221
1.694
clk_ibuf
0.000
0.581
gw_gao_inst_0/u_ao_top/capture_start_sel_s1
0.740
-0.914
+0.913
gw_gao_inst_0/u_ao_top/n836_s1
1.021
-1.271
+1.221
gw_gao_inst_0/u_ao_top/capture_end_tck_0_s0
-1.271
+1.221
=====
HOLD
-0.314
-1.268
+0.202
+1.156
0.954
clk_ibuf
0.000
0.581
-s480p/de_s0
+arkanoid/red_7_s0
0.740
0.914
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_12_s
-1.268
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_11_s
+1.156
=====
HOLD
-0.319
-1.273
+0.202
+1.156
0.954
clk_ibuf
0.000
@@ -694,11 +835,11 @@ arkanoid/red_7_s0
0.740
0.914
gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_11_s
-1.273
+1.156
=====
HOLD
-0.319
-1.273
+0.202
+1.156
0.954
clk_ibuf
0.000
@@ -706,8 +847,134 @@ clk_ibuf
arkanoid/red_7_s0
0.740
0.914
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_11_s
-1.273
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_10_s
+1.156
+=====
+HOLD
+0.202
+1.156
+0.954
+clk_ibuf
+0.000
+0.581
+arkanoid/red_7_s0
+0.740
+0.914
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_10_s
+1.156
+=====
+HOLD
+0.291
+2.042
+1.751
+gw_gao_inst_0/tck_ibuf
+0.000
+0.581
+gw_gao_inst_0/u_gw_jtag
+0.581
+1.162
+gw_gao_inst_0/u_ao_top/address_counter_11_s0
+1.649
+1.823
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_6_s
+2.042
+=====
+HOLD
+0.307
+1.261
+0.954
+clk_ibuf
+0.000
+0.581
+arkanoid/red_7_s0
+0.740
+0.914
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_9_s
+1.261
+=====
+HOLD
+0.307
+1.261
+0.954
+clk_ibuf
+0.000
+0.581
+arkanoid/red_7_s0
+0.740
+0.914
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_9_s
+1.261
+=====
+HOLD
+0.315
+1.156
+0.841
+clk_ibuf
+0.000
+0.581
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
+0.740
+0.914
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_6_s
+1.156
+=====
+HOLD
+0.317
+2.068
+1.751
+gw_gao_inst_0/tck_ibuf
+0.000
+0.581
+gw_gao_inst_0/u_gw_jtag
+0.581
+1.162
+gw_gao_inst_0/u_ao_top/address_counter_7_s0
+1.649
+1.823
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_8_s
+2.068
+=====
+HOLD
+0.317
+2.068
+1.751
+gw_gao_inst_0/tck_ibuf
+0.000
+0.581
+gw_gao_inst_0/u_gw_jtag
+0.581
+1.162
+gw_gao_inst_0/u_ao_top/address_counter_7_s0
+1.649
+1.823
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_6_s
+2.068
+=====
+HOLD
+0.342
+1.296
+0.954
+clk_ibuf
+0.000
+0.581
+arkanoid/red_7_s0
+0.740
+0.914
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_8_s
+1.296
+=====
+HOLD
+0.342
+1.296
+0.954
+clk_ibuf
+0.000
+0.581
+arkanoid/red_7_s0
+0.740
+0.914
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_8_s
+1.296
=====
HOLD
0.367
@@ -716,13 +983,13 @@ HOLD
clk_ibuf
0.000
0.581
-s480p/y_6_s0
+s480p/y_8_s0
0.740
0.914
-s480p/n109_s
+s480p/n107_s
0.916
1.116
-s480p/y_6_s0
+s480p/y_8_s0
1.116
=====
HOLD
@@ -764,13 +1031,13 @@ HOLD
clk_ibuf
0.000
0.581
-s480p/x_12_s0
+s480p/x_14_s0
0.740
0.914
-s480p/n168_s
+s480p/n166_s
0.916
1.116
-s480p/x_12_s0
+s480p/x_14_s0
1.116
=====
HOLD
@@ -783,13 +1050,13 @@ gw_gao_inst_0/tck_ibuf
gw_gao_inst_0/u_gw_jtag
0.581
1.162
-gw_gao_inst_0/u_ao_top/word_count_3_s0
+gw_gao_inst_0/u_ao_top/bit_count_3_s1
1.649
1.823
-gw_gao_inst_0/u_ao_top/data_to_word_counter_3_s2
+gw_gao_inst_0/u_ao_top/n445_s2
1.825
2.025
-gw_gao_inst_0/u_ao_top/word_count_3_s0
+gw_gao_inst_0/u_ao_top/bit_count_3_s1
2.025
=====
HOLD
@@ -802,32 +1069,13 @@ gw_gao_inst_0/tck_ibuf
gw_gao_inst_0/u_gw_jtag
0.581
1.162
-gw_gao_inst_0/u_ao_top/word_count_6_s0
-1.649
-1.823
-gw_gao_inst_0/u_ao_top/data_to_word_counter_6_s2
-1.825
-2.025
-gw_gao_inst_0/u_ao_top/word_count_6_s0
-2.025
-=====
-HOLD
-0.367
-2.025
-1.659
-gw_gao_inst_0/tck_ibuf
-0.000
-0.581
-gw_gao_inst_0/u_gw_jtag
-0.581
-1.162
-gw_gao_inst_0/u_ao_top/word_count_15_s0
+gw_gao_inst_0/u_ao_top/word_count_11_s0
1.649
1.823
-gw_gao_inst_0/u_ao_top/data_to_word_counter_15_s2
+gw_gao_inst_0/u_ao_top/data_to_word_counter_11_s2
1.825
2.025
-gw_gao_inst_0/u_ao_top/word_count_15_s0
+gw_gao_inst_0/u_ao_top/word_count_11_s0
2.025
=====
HOLD
@@ -837,45 +1085,13 @@ HOLD
clk_ibuf
0.000
0.581
-s480p/y_0_s0
-0.740
-0.914
-s480p/n115_s2
-0.917
-1.117
-s480p/y_0_s0
-1.117
-=====
-HOLD
-0.368
-1.117
-0.749
-clk_ibuf
-0.000
-0.581
-s480p/y_2_s0
-0.740
-0.914
-s480p/n113_s
-0.917
-1.117
-s480p/y_2_s0
-1.117
-=====
-HOLD
-0.368
-1.117
-0.749
-clk_ibuf
-0.000
-0.581
-s480p/y_8_s0
+s480p/y_6_s0
0.740
0.914
-s480p/n107_s
+s480p/n109_s
0.917
1.117
-s480p/y_8_s0
+s480p/y_6_s0
1.117
=====
HOLD
@@ -901,22 +1117,6 @@ HOLD
clk_ibuf
0.000
0.581
-s480p/x_6_s0
-0.740
-0.914
-s480p/n174_s
-0.917
-1.117
-s480p/x_6_s0
-1.117
-=====
-HOLD
-0.368
-1.117
-0.749
-clk_ibuf
-0.000
-0.581
s480p/x_8_s0
0.740
0.914
@@ -933,13 +1133,13 @@ HOLD
clk_ibuf
0.000
0.581
-s480p/x_14_s0
+s480p/x_12_s0
0.740
0.914
-s480p/n166_s
+s480p/n168_s
0.917
1.117
-s480p/x_14_s0
+s480p/x_12_s0
1.117
=====
HOLD
@@ -952,13 +1152,13 @@ gw_gao_inst_0/tck_ibuf
gw_gao_inst_0/u_gw_jtag
0.581
1.162
-gw_gao_inst_0/u_ao_top/word_count_0_s0
+gw_gao_inst_0/u_ao_top/bit_count_2_s1
1.649
1.823
-gw_gao_inst_0/u_ao_top/data_to_word_counter_0_s4
+gw_gao_inst_0/u_ao_top/n446_s2
1.827
2.026
-gw_gao_inst_0/u_ao_top/word_count_0_s0
+gw_gao_inst_0/u_ao_top/bit_count_2_s1
2.026
=====
HOLD
@@ -971,106 +1171,11 @@ gw_gao_inst_0/tck_ibuf
gw_gao_inst_0/u_gw_jtag
0.581
1.162
-gw_gao_inst_0/u_ao_top/word_count_11_s0
-1.649
-1.823
-gw_gao_inst_0/u_ao_top/data_to_word_counter_11_s2
-1.827
-2.026
-gw_gao_inst_0/u_ao_top/word_count_11_s0
-2.026
-=====
-HOLD
-0.368
-2.026
-1.659
-gw_gao_inst_0/tck_ibuf
-0.000
-0.581
-gw_gao_inst_0/u_gw_jtag
-0.581
-1.162
-gw_gao_inst_0/u_ao_top/word_count_13_s0
+gw_gao_inst_0/u_ao_top/word_count_6_s0
1.649
1.823
-gw_gao_inst_0/u_ao_top/data_to_word_counter_13_s2
+gw_gao_inst_0/u_ao_top/data_to_word_counter_6_s2
1.827
2.026
-gw_gao_inst_0/u_ao_top/word_count_13_s0
+gw_gao_inst_0/u_ao_top/word_count_6_s0
2.026
-=====
-HOLD
-0.369
-2.028
-1.659
-gw_gao_inst_0/tck_ibuf
-0.000
-0.581
-gw_gao_inst_0/u_gw_jtag
-0.581
-1.162
-gw_gao_inst_0/u_ao_top/bit_count_0_s3
-1.649
-1.823
-gw_gao_inst_0/u_ao_top/n448_s5
-1.828
-2.028
-gw_gao_inst_0/u_ao_top/bit_count_0_s3
-2.028
-=====
-HOLD
-0.369
-2.028
-1.659
-gw_gao_inst_0/tck_ibuf
-0.000
-0.581
-gw_gao_inst_0/u_gw_jtag
-0.581
-1.162
-gw_gao_inst_0/u_ao_top/bit_count_1_s1
-1.649
-1.823
-gw_gao_inst_0/u_ao_top/n447_s3
-1.828
-2.028
-gw_gao_inst_0/u_ao_top/bit_count_1_s1
-2.028
-=====
-HOLD
-0.369
-2.028
-1.659
-gw_gao_inst_0/tck_ibuf
-0.000
-0.581
-gw_gao_inst_0/u_gw_jtag
-0.581
-1.162
-gw_gao_inst_0/u_ao_top/word_count_1_s0
-1.649
-1.823
-gw_gao_inst_0/u_ao_top/data_to_word_counter_1_s2
-1.828
-2.028
-gw_gao_inst_0/u_ao_top/word_count_1_s0
-2.028
-=====
-HOLD
-0.369
-2.028
-1.659
-gw_gao_inst_0/tck_ibuf
-0.000
-0.581
-gw_gao_inst_0/u_gw_jtag
-0.581
-1.162
-gw_gao_inst_0/u_ao_top/word_count_5_s0
-1.649
-1.823
-gw_gao_inst_0/u_ao_top/data_to_word_counter_5_s2
-1.828
-2.028
-gw_gao_inst_0/u_ao_top/word_count_5_s0
-2.028
diff --git a/impl/pnr/Nanoid20K_tr_content.html b/impl/pnr/Nanoid20K_tr_content.html
index bd71f89..fe100a1 100644
--- a/impl/pnr/Nanoid20K_tr_content.html
+++ b/impl/pnr/Nanoid20K_tr_content.html
@@ -55,7 +55,7 @@
Created Time |
-Sat Jul 13 06:44:58 2024
+ | Sat Jul 13 08:05:29 2024
|
@@ -76,11 +76,11 @@
Numbers of Paths Analyzed |
-1748 |
+1923 |
Numbers of Endpoints Analyzed |
-1447 |
+1537 |
Numbers of Falling Endpoints |
@@ -189,16 +189,16 @@
1 |
clk |
25.000(MHz) |
-151.672(MHz) |
-8 |
+123.107(MHz) |
+13 |
TOP |
2 |
tck_pad_i |
20.000(MHz) |
-165.592(MHz) |
-8 |
+178.836(MHz) |
+6 |
TOP |
@@ -305,278 +305,278 @@ Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
1 |
-8.006 |
+7.587 |
gw_gao_inst_0/u_ao_top/internal_reg_start_s1/Q |
gw_gao_inst_0/u_ao_top/internal_reg_start_syn_0_s0/D |
tck_pad_i:[R] |
clk:[R] |
10.000 |
1.051 |
-0.878 |
+1.296 |
2 |
-10.063 |
+9.708 |
gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q |
gw_gao_inst_0/u_ao_top/capture_end_tck_0_s0/D |
clk:[R] |
tck_pad_i:[R] |
10.000 |
-1.051 |
-0.923 |
+1.278 |
3 |
-33.407 |
-arkanoid/qxb_5_s2/Q |
-arkanoid/qxb_5_s2/CE |
+31.877 |
+arkanoid/score_counter_4_s0/Q |
+arkanoid/score_1[2]_2_s0/D |
clk:[R] |
clk:[R] |
40.000 |
0.000 |
-6.563 |
+8.093 |
4 |
-33.407 |
-arkanoid/qxb_5_s2/Q |
-arkanoid/qxb_4_s2/CE |
+32.184 |
+arkanoid/score_counter_4_s0/Q |
+arkanoid/score_1[4]_4_s0/D |
clk:[R] |
clk:[R] |
40.000 |
0.000 |
-6.563 |
+7.786 |
5 |
-33.437 |
-arkanoid/qxb_0_s0/Q |
-arkanoid/qdy_s0/CE |
+32.208 |
+arkanoid/qyb_3_s0/Q |
+arkanoid/score_counter_6_s0/D |
clk:[R] |
clk:[R] |
40.000 |
0.000 |
-6.533 |
+7.762 |
6 |
-33.514 |
-arkanoid/qxb_0_s0/Q |
-arkanoid/qdy_s0/D |
+32.212 |
+arkanoid/score_counter_4_s0/Q |
+arkanoid/score_1[5]_3_s0/D |
clk:[R] |
clk:[R] |
40.000 |
0.000 |
-6.456 |
+7.758 |
7 |
-33.565 |
-arkanoid/qxb_5_s2/Q |
-arkanoid/qxb_0_s0/CE |
+32.222 |
+arkanoid/score_counter_4_s0/Q |
+arkanoid/score_1[2]_1_s0/D |
clk:[R] |
clk:[R] |
40.000 |
0.000 |
-6.405 |
+7.748 |
8 |
-33.565 |
-arkanoid/qxb_5_s2/Q |
-arkanoid/qxb_1_s0/CE |
+32.282 |
+arkanoid/score_counter_5_s0/Q |
+arkanoid/score[5]_1_s0/D |
clk:[R] |
clk:[R] |
40.000 |
0.000 |
-6.405 |
+7.688 |
9 |
-33.565 |
-arkanoid/qxb_5_s2/Q |
-arkanoid/qxb_2_s0/CE |
+32.365 |
+arkanoid/score_counter_4_s0/Q |
+arkanoid/score_1[3]_2_s0/D |
clk:[R] |
clk:[R] |
40.000 |
0.000 |
-6.405 |
+7.604 |
10 |
-33.565 |
-arkanoid/qxb_5_s2/Q |
-arkanoid/qxb_6_s0/CE |
+32.416 |
+arkanoid/qxb_1_s0/Q |
+arkanoid/qxb_3_s2/CE |
clk:[R] |
clk:[R] |
40.000 |
0.000 |
-6.405 |
+7.554 |
11 |
-33.568 |
-arkanoid/qxb_5_s2/Q |
-arkanoid/qxb_8_s2/CE |
+32.416 |
+arkanoid/qxb_1_s0/Q |
+arkanoid/qxb_1_s0/CE |
clk:[R] |
clk:[R] |
40.000 |
0.000 |
-6.402 |
+7.554 |
12 |
-33.568 |
-arkanoid/qxb_5_s2/Q |
-arkanoid/qxb_3_s2/CE |
+32.423 |
+arkanoid/qxb_1_s0/Q |
+arkanoid/score_counter_4_s0/D |
clk:[R] |
clk:[R] |
40.000 |
0.000 |
-6.402 |
+7.547 |
13 |
-33.568 |
-arkanoid/qxb_5_s2/Q |
-arkanoid/qxb_7_s0/CE |
+32.482 |
+arkanoid/qyb_3_s0/Q |
+arkanoid/score_counter_7_s0/D |
clk:[R] |
clk:[R] |
40.000 |
0.000 |
-6.402 |
+7.488 |
14 |
-33.568 |
-arkanoid/qxb_5_s2/Q |
-arkanoid/qxb_9_s0/CE |
+32.549 |
+arkanoid/score_counter_4_s0/Q |
+arkanoid/score_1[2]_6_s0/D |
clk:[R] |
clk:[R] |
40.000 |
0.000 |
-6.402 |
+7.421 |
15 |
-22.775 |
+23.315 |
gw_gao_inst_0/u_icon_top/enable_reg_2_s0/Q |
gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/CE |
tck_pad_i:[F] |
tck_pad_i:[R] |
25.000 |
0.121 |
-2.074 |
+1.534 |
16 |
-22.775 |
+23.315 |
gw_gao_inst_0/u_icon_top/enable_reg_2_s0/Q |
gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/CE |
tck_pad_i:[F] |
tck_pad_i:[R] |
25.000 |
0.121 |
-2.074 |
+1.534 |
17 |
-22.775 |
+23.315 |
gw_gao_inst_0/u_icon_top/enable_reg_2_s0/Q |
-gw_gao_inst_0/u_icon_top/module_id_reg_3_s0/CE |
+gw_gao_inst_0/u_icon_top/module_id_reg_2_s0/CE |
tck_pad_i:[F] |
tck_pad_i:[R] |
25.000 |
0.121 |
-2.074 |
+1.534 |
18 |
-22.939 |
+23.315 |
gw_gao_inst_0/u_icon_top/enable_reg_2_s0/Q |
-gw_gao_inst_0/u_icon_top/module_id_reg_2_s0/CE |
+gw_gao_inst_0/u_icon_top/module_id_reg_3_s0/CE |
tck_pad_i:[F] |
tck_pad_i:[R] |
25.000 |
0.121 |
-1.911 |
+1.534 |
19 |
-23.020 |
-gw_gao_inst_0/u_icon_top/enable_reg_2_s0/Q |
+23.388 |
+gw_gao_inst_0/u_icon_top/enable_reg_1_s0/Q |
gw_gao_inst_0/u_icon_top/input_shift_reg_2_s0/CE |
tck_pad_i:[F] |
tck_pad_i:[R] |
25.000 |
0.121 |
-1.829 |
+1.461 |
20 |
-23.020 |
-gw_gao_inst_0/u_icon_top/enable_reg_2_s0/Q |
+23.388 |
+gw_gao_inst_0/u_icon_top/enable_reg_1_s0/Q |
gw_gao_inst_0/u_icon_top/input_shift_reg_3_s0/CE |
tck_pad_i:[F] |
tck_pad_i:[R] |
25.000 |
0.121 |
-1.829 |
+1.461 |
21 |
-23.020 |
-gw_gao_inst_0/u_icon_top/enable_reg_2_s0/Q |
+23.388 |
+gw_gao_inst_0/u_icon_top/enable_reg_1_s0/Q |
gw_gao_inst_0/u_icon_top/input_shift_reg_4_s0/CE |
tck_pad_i:[F] |
tck_pad_i:[R] |
25.000 |
0.121 |
-1.829 |
+1.461 |
22 |
-23.364 |
-gw_gao_inst_0/u_icon_top/enable_reg_2_s0/Q |
-gw_gao_inst_0/u_icon_top/input_shift_reg_0_s0/CE |
+23.646 |
+gw_gao_inst_0/u_icon_top/tdi_d_s0/Q |
+gw_gao_inst_0/u_ao_top/data_register_45_s0/D |
tck_pad_i:[F] |
tck_pad_i:[R] |
25.000 |
0.121 |
-1.485 |
+1.203 |
23 |
-23.364 |
-gw_gao_inst_0/u_icon_top/enable_reg_2_s0/Q |
-gw_gao_inst_0/u_icon_top/input_shift_reg_1_s0/CE |
+23.732 |
+gw_gao_inst_0/u_icon_top/enable_reg_1_s0/Q |
+gw_gao_inst_0/u_icon_top/input_shift_reg_0_s0/CE |
tck_pad_i:[F] |
tck_pad_i:[R] |
25.000 |
0.121 |
-1.485 |
+1.117 |
24 |
-23.527 |
-gw_gao_inst_0/u_icon_top/tdi_d_s0/Q |
-gw_gao_inst_0/u_ao_top/data_register_45_s0/D |
+23.732 |
+gw_gao_inst_0/u_icon_top/enable_reg_1_s0/Q |
+gw_gao_inst_0/u_icon_top/input_shift_reg_1_s0/CE |
tck_pad_i:[F] |
tck_pad_i:[R] |
25.000 |
0.121 |
-1.322 |
+1.117 |
25 |
-23.736 |
+23.946 |
gw_gao_inst_0/u_icon_top/tdi_d_s0/Q |
gw_gao_inst_0/u_icon_top/input_shift_reg_4_s0/D |
tck_pad_i:[F] |
tck_pad_i:[R] |
25.000 |
0.121 |
-1.113 |
+0.903 |
@@ -595,220 +595,220 @@ Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
1 |
--0.423 |
+-0.473 |
gw_gao_inst_0/u_ao_top/capture_start_sel_s1/Q |
gw_gao_inst_0/u_ao_top/capture_end_tck_0_s0/D |
clk:[R] |
tck_pad_i:[R] |
0.000 |
-0.909 |
-0.531 |
+0.481 |
2 |
-0.314 |
-s480p/de_s0/Q |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_12_s/DI[0] |
+0.202 |
+arkanoid/red_7_s0/Q |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_11_s/DI[1] |
clk:[R] |
clk:[R] |
0.000 |
0.000 |
-0.528 |
+0.417 |
3 |
-0.319 |
+0.202 |
arkanoid/red_7_s0/Q |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_11_s/DI[1] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_11_s/DI[0] |
clk:[R] |
clk:[R] |
0.000 |
0.000 |
-0.533 |
+0.417 |
4 |
-0.319 |
+0.202 |
arkanoid/red_7_s0/Q |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_11_s/DI[0] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_10_s/DI[1] |
clk:[R] |
clk:[R] |
0.000 |
0.000 |
-0.533 |
+0.417 |
5 |
-0.367 |
-s480p/y_6_s0/Q |
-s480p/y_6_s0/D |
+0.202 |
+arkanoid/red_7_s0/Q |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_10_s/DI[0] |
clk:[R] |
clk:[R] |
0.000 |
0.000 |
-0.376 |
+0.417 |
6 |
-0.367 |
-s480p/y_12_s0/Q |
-s480p/y_12_s0/D |
-clk:[R] |
-clk:[R] |
+0.291 |
+gw_gao_inst_0/u_ao_top/address_counter_11_s0/Q |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_6_s/ADB[12] |
+tck_pad_i:[R] |
+tck_pad_i:[R] |
0.000 |
0.000 |
-0.376 |
+0.393 |
7 |
-0.367 |
-s480p/y_14_s0/Q |
-s480p/y_14_s0/D |
+0.307 |
+arkanoid/red_7_s0/Q |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_9_s/DI[1] |
clk:[R] |
clk:[R] |
0.000 |
0.000 |
-0.376 |
+0.522 |
8 |
-0.367 |
-s480p/x_12_s0/Q |
-s480p/x_12_s0/D |
+0.307 |
+arkanoid/red_7_s0/Q |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_9_s/DI[0] |
clk:[R] |
clk:[R] |
0.000 |
0.000 |
-0.376 |
+0.522 |
9 |
-0.367 |
-gw_gao_inst_0/u_ao_top/word_count_3_s0/Q |
-gw_gao_inst_0/u_ao_top/word_count_3_s0/D |
-tck_pad_i:[R] |
-tck_pad_i:[R] |
+0.315 |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_6_s/ADA[6] |
+clk:[R] |
+clk:[R] |
0.000 |
0.000 |
-0.376 |
+0.416 |
10 |
-0.367 |
-gw_gao_inst_0/u_ao_top/word_count_6_s0/Q |
-gw_gao_inst_0/u_ao_top/word_count_6_s0/D |
+0.317 |
+gw_gao_inst_0/u_ao_top/address_counter_7_s0/Q |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_8_s/ADB[8] |
tck_pad_i:[R] |
tck_pad_i:[R] |
0.000 |
0.000 |
-0.376 |
+0.419 |
11 |
-0.367 |
-gw_gao_inst_0/u_ao_top/word_count_15_s0/Q |
-gw_gao_inst_0/u_ao_top/word_count_15_s0/D |
+0.317 |
+gw_gao_inst_0/u_ao_top/address_counter_7_s0/Q |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_6_s/ADB[8] |
tck_pad_i:[R] |
tck_pad_i:[R] |
0.000 |
0.000 |
-0.376 |
+0.419 |
12 |
-0.368 |
-s480p/y_0_s0/Q |
-s480p/y_0_s0/D |
+0.342 |
+arkanoid/red_7_s0/Q |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_8_s/DI[1] |
clk:[R] |
clk:[R] |
0.000 |
0.000 |
-0.377 |
+0.557 |
13 |
-0.368 |
-s480p/y_2_s0/Q |
-s480p/y_2_s0/D |
+0.342 |
+arkanoid/red_7_s0/Q |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_8_s/DI[0] |
clk:[R] |
clk:[R] |
0.000 |
0.000 |
-0.377 |
+0.557 |
14 |
-0.368 |
+0.367 |
s480p/y_8_s0/Q |
s480p/y_8_s0/D |
clk:[R] |
clk:[R] |
0.000 |
0.000 |
-0.377 |
+0.376 |
15 |
-0.368 |
-s480p/x_2_s0/Q |
-s480p/x_2_s0/D |
+0.367 |
+s480p/y_12_s0/Q |
+s480p/y_12_s0/D |
clk:[R] |
clk:[R] |
0.000 |
0.000 |
-0.377 |
+0.376 |
16 |
-0.368 |
-s480p/x_6_s0/Q |
-s480p/x_6_s0/D |
+0.367 |
+s480p/y_14_s0/Q |
+s480p/y_14_s0/D |
clk:[R] |
clk:[R] |
0.000 |
0.000 |
-0.377 |
+0.376 |
17 |
-0.368 |
-s480p/x_8_s0/Q |
-s480p/x_8_s0/D |
+0.367 |
+s480p/x_14_s0/Q |
+s480p/x_14_s0/D |
clk:[R] |
clk:[R] |
0.000 |
0.000 |
-0.377 |
+0.376 |
18 |
-0.368 |
-s480p/x_14_s0/Q |
-s480p/x_14_s0/D |
-clk:[R] |
-clk:[R] |
+0.367 |
+gw_gao_inst_0/u_ao_top/bit_count_3_s1/Q |
+gw_gao_inst_0/u_ao_top/bit_count_3_s1/D |
+tck_pad_i:[R] |
+tck_pad_i:[R] |
0.000 |
0.000 |
-0.377 |
+0.376 |
19 |
-0.368 |
-gw_gao_inst_0/u_ao_top/word_count_0_s0/Q |
-gw_gao_inst_0/u_ao_top/word_count_0_s0/D |
+0.367 |
+gw_gao_inst_0/u_ao_top/word_count_11_s0/Q |
+gw_gao_inst_0/u_ao_top/word_count_11_s0/D |
tck_pad_i:[R] |
tck_pad_i:[R] |
0.000 |
0.000 |
-0.377 |
+0.376 |
20 |
0.368 |
-gw_gao_inst_0/u_ao_top/word_count_11_s0/Q |
-gw_gao_inst_0/u_ao_top/word_count_11_s0/D |
-tck_pad_i:[R] |
-tck_pad_i:[R] |
+s480p/y_6_s0/Q |
+s480p/y_6_s0/D |
+clk:[R] |
+clk:[R] |
0.000 |
0.000 |
0.377 |
@@ -816,57 +816,57 @@ Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
21 |
0.368 |
-gw_gao_inst_0/u_ao_top/word_count_13_s0/Q |
-gw_gao_inst_0/u_ao_top/word_count_13_s0/D |
-tck_pad_i:[R] |
-tck_pad_i:[R] |
+s480p/x_2_s0/Q |
+s480p/x_2_s0/D |
+clk:[R] |
+clk:[R] |
0.000 |
0.000 |
0.377 |
22 |
-0.369 |
-gw_gao_inst_0/u_ao_top/bit_count_0_s3/Q |
-gw_gao_inst_0/u_ao_top/bit_count_0_s3/D |
-tck_pad_i:[R] |
-tck_pad_i:[R] |
+0.368 |
+s480p/x_8_s0/Q |
+s480p/x_8_s0/D |
+clk:[R] |
+clk:[R] |
0.000 |
0.000 |
-0.378 |
+0.377 |
23 |
-0.369 |
-gw_gao_inst_0/u_ao_top/bit_count_1_s1/Q |
-gw_gao_inst_0/u_ao_top/bit_count_1_s1/D |
-tck_pad_i:[R] |
-tck_pad_i:[R] |
+0.368 |
+s480p/x_12_s0/Q |
+s480p/x_12_s0/D |
+clk:[R] |
+clk:[R] |
0.000 |
0.000 |
-0.378 |
+0.377 |
24 |
-0.369 |
-gw_gao_inst_0/u_ao_top/word_count_1_s0/Q |
-gw_gao_inst_0/u_ao_top/word_count_1_s0/D |
+0.368 |
+gw_gao_inst_0/u_ao_top/bit_count_2_s1/Q |
+gw_gao_inst_0/u_ao_top/bit_count_2_s1/D |
tck_pad_i:[R] |
tck_pad_i:[R] |
0.000 |
0.000 |
-0.378 |
+0.377 |
25 |
-0.369 |
-gw_gao_inst_0/u_ao_top/word_count_5_s0/Q |
-gw_gao_inst_0/u_ao_top/word_count_5_s0/D |
+0.368 |
+gw_gao_inst_0/u_ao_top/word_count_6_s0/Q |
+gw_gao_inst_0/u_ao_top/word_count_6_s0/D |
tck_pad_i:[R] |
tck_pad_i:[R] |
0.000 |
0.000 |
-0.378 |
+0.377 |
@@ -885,278 +885,278 @@ Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
1 |
-10.390 |
+10.398 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
gw_gao_inst_0/u_ao_top/capture_end_tck_0_s0/CLEAR |
clk:[F] |
tck_pad_i:[R] |
10.000 |
-1.031 |
-0.576 |
+0.568 |
2 |
-10.390 |
+10.398 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
gw_gao_inst_0/u_ao_top/capture_end_tck_1_s0/CLEAR |
clk:[F] |
tck_pad_i:[R] |
10.000 |
-1.031 |
-0.576 |
+0.568 |
3 |
-10.390 |
+10.398 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
gw_gao_inst_0/u_ao_top/capture_end_tck_2_s0/CLEAR |
clk:[F] |
tck_pad_i:[R] |
10.000 |
-1.031 |
-0.576 |
+0.568 |
4 |
-18.968 |
+18.998 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-gw_gao_inst_0/u_ao_top/internal_reg_start_syn_0_s0/CLEAR |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_1_s5/CLEAR |
clk:[F] |
clk:[R] |
20.000 |
0.020 |
-0.982 |
+0.952 |
5 |
-18.968 |
+18.998 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-gw_gao_inst_0/u_ao_top/internal_reg_start_syn_1_s0/CLEAR |
+gw_gao_inst_0/u_ao_top/capture_end_dly_s0/PRESET |
clk:[F] |
clk:[R] |
20.000 |
0.020 |
-0.982 |
+0.952 |
6 |
-19.033 |
+19.051 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-gw_gao_inst_0/u_ao_top/capture_start_sel_s1/CLEAR |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLEAR |
clk:[F] |
clk:[R] |
20.000 |
0.020 |
-0.917 |
+0.899 |
7 |
-19.033 |
+19.051 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-gw_gao_inst_0/u_ao_top/capture_end_dly_s0/PRESET |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_12_s6/CLEAR |
clk:[F] |
clk:[R] |
20.000 |
0.020 |
-0.917 |
+0.899 |
8 |
-19.033 |
+19.132 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-gw_gao_inst_0/u_ao_top/internal_reg_start_dly_0_s0/CLEAR |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_6_s5/CLEAR |
clk:[F] |
clk:[R] |
20.000 |
0.020 |
-0.917 |
+0.818 |
9 |
-19.376 |
+19.132 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLEAR |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR |
clk:[F] |
clk:[R] |
20.000 |
0.020 |
-0.574 |
+0.818 |
10 |
-19.376 |
+19.132 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_1_s5/CLEAR |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR |
clk:[F] |
clk:[R] |
20.000 |
0.020 |
-0.574 |
+0.818 |
11 |
-19.376 |
+19.132 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_4_s5/CLEAR |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_11_s1/CLEAR |
clk:[F] |
clk:[R] |
20.000 |
0.020 |
-0.574 |
+0.818 |
12 |
-19.376 |
+19.137 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_6_s5/CLEAR |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_7_s5/CLEAR |
clk:[F] |
clk:[R] |
20.000 |
0.020 |
-0.574 |
+0.813 |
13 |
-19.376 |
+19.137 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_7_s5/CLEAR |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_9_s5/CLEAR |
clk:[F] |
clk:[R] |
20.000 |
0.020 |
-0.574 |
+0.813 |
14 |
-19.376 |
+19.137 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_10_s5/CLEAR |
clk:[F] |
clk:[R] |
20.000 |
0.020 |
-0.574 |
+0.813 |
15 |
-19.376 |
+19.158 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_4_s5/CLEAR |
clk:[F] |
clk:[R] |
20.000 |
0.020 |
-0.574 |
+0.792 |
16 |
-19.376 |
+19.173 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_11_s1/CLEAR |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR |
clk:[F] |
clk:[R] |
20.000 |
0.020 |
-0.574 |
+0.777 |
17 |
-19.376 |
+19.173 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_12_s1/CLEAR |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR |
clk:[F] |
clk:[R] |
20.000 |
0.020 |
-0.574 |
+0.777 |
18 |
-19.376 |
+19.275 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR |
clk:[F] |
clk:[R] |
20.000 |
0.020 |
-0.574 |
+0.675 |
19 |
-19.376 |
+19.275 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-gw_gao_inst_0/u_ao_top/trigger_seq_start_s1/CLEAR |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR |
clk:[F] |
clk:[R] |
20.000 |
0.020 |
-0.574 |
+0.675 |
20 |
-19.376 |
+19.275 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-gw_gao_inst_0/u_ao_top/internal_reg_start_dly_1_s0/CLEAR |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR |
clk:[F] |
clk:[R] |
20.000 |
0.020 |
-0.574 |
+0.675 |
21 |
-19.381 |
+19.280 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_3_s5/CLEAR |
+gw_gao_inst_0/u_ao_top/trigger_seq_start_s1/CLEAR |
clk:[F] |
clk:[R] |
20.000 |
0.020 |
-0.569 |
+0.670 |
22 |
-19.381 |
+19.280 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_9_s5/CLEAR |
+gw_gao_inst_0/u_ao_top/internal_reg_start_dly_0_s0/CLEAR |
clk:[F] |
clk:[R] |
20.000 |
0.020 |
-0.569 |
+0.670 |
23 |
-19.387 |
+19.280 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR |
+gw_gao_inst_0/u_ao_top/internal_reg_start_dly_1_s0/CLEAR |
clk:[F] |
clk:[R] |
20.000 |
0.020 |
-0.563 |
+0.670 |
24 |
-19.387 |
+19.389 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR |
+gw_gao_inst_0/u_ao_top/internal_reg_start_syn_0_s0/CLEAR |
clk:[F] |
clk:[R] |
20.000 |
0.020 |
-0.563 |
+0.561 |
25 |
-19.387 |
+19.389 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR |
+gw_gao_inst_0/u_ao_top/internal_reg_start_syn_1_s0/CLEAR |
clk:[F] |
clk:[R] |
20.000 |
0.020 |
-0.563 |
+0.561 |
@@ -1175,278 +1175,278 @@ Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
1 |
--0.538 |
+-0.543 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
gw_gao_inst_0/u_ao_top/capture_end_tck_0_s0/CLEAR |
clk:[F] |
tck_pad_i:[R] |
0.000 |
-0.899 |
-0.405 |
+0.401 |
2 |
--0.538 |
+-0.543 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
gw_gao_inst_0/u_ao_top/capture_end_tck_1_s0/CLEAR |
clk:[F] |
tck_pad_i:[R] |
0.000 |
-0.899 |
-0.405 |
+0.401 |
3 |
--0.538 |
+-0.543 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
gw_gao_inst_0/u_ao_top/capture_end_tck_2_s0/CLEAR |
clk:[F] |
tck_pad_i:[R] |
0.000 |
-0.899 |
-0.405 |
+0.401 |
4 |
-20.402 |
+20.292 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR |
+gw_gao_inst_0/u_ao_top/capture_start_sel_s1/CLEAR |
clk:[F] |
clk:[R] |
-20.000 |
0.011 |
-0.401 |
+0.291 |
5 |
-20.402 |
+20.397 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR |
+gw_gao_inst_0/u_ao_top/internal_reg_start_syn_0_s0/CLEAR |
clk:[F] |
clk:[R] |
-20.000 |
0.011 |
-0.401 |
+0.396 |
6 |
-20.402 |
+20.397 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR |
+gw_gao_inst_0/u_ao_top/internal_reg_start_syn_1_s0/CLEAR |
clk:[F] |
clk:[R] |
-20.000 |
0.011 |
-0.401 |
+0.396 |
7 |
-20.402 |
+20.420 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR |
+gw_gao_inst_0/u_ao_top/trigger_seq_start_s1/CLEAR |
clk:[F] |
clk:[R] |
-20.000 |
0.011 |
-0.401 |
+0.419 |
8 |
-20.405 |
+20.420 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_3_s5/CLEAR |
+gw_gao_inst_0/u_ao_top/internal_reg_start_dly_0_s0/CLEAR |
clk:[F] |
clk:[R] |
-20.000 |
0.011 |
-0.404 |
+0.419 |
9 |
-20.405 |
+20.420 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_9_s5/CLEAR |
+gw_gao_inst_0/u_ao_top/internal_reg_start_dly_1_s0/CLEAR |
clk:[F] |
clk:[R] |
-20.000 |
0.011 |
-0.404 |
+0.419 |
10 |
-20.408 |
+20.423 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLEAR |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR |
clk:[F] |
clk:[R] |
-20.000 |
0.011 |
-0.407 |
+0.422 |
11 |
-20.408 |
+20.423 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_1_s5/CLEAR |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR |
clk:[F] |
clk:[R] |
-20.000 |
0.011 |
-0.407 |
+0.422 |
12 |
-20.408 |
+20.423 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_4_s5/CLEAR |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR |
clk:[F] |
clk:[R] |
-20.000 |
0.011 |
-0.407 |
+0.422 |
13 |
-20.408 |
+20.507 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_6_s5/CLEAR |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR |
clk:[F] |
clk:[R] |
-20.000 |
0.011 |
-0.407 |
+0.506 |
14 |
-20.408 |
+20.507 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_7_s5/CLEAR |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR |
clk:[F] |
clk:[R] |
-20.000 |
0.011 |
-0.407 |
+0.506 |
15 |
-20.408 |
+20.513 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_10_s5/CLEAR |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_4_s5/CLEAR |
clk:[F] |
clk:[R] |
-20.000 |
0.011 |
-0.407 |
+0.512 |
16 |
-20.408 |
+20.538 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_7_s5/CLEAR |
clk:[F] |
clk:[R] |
-20.000 |
0.011 |
-0.407 |
+0.537 |
17 |
-20.408 |
+20.538 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_11_s1/CLEAR |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_9_s5/CLEAR |
clk:[F] |
clk:[R] |
-20.000 |
0.011 |
-0.407 |
+0.537 |
18 |
-20.408 |
+20.538 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_12_s1/CLEAR |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_10_s5/CLEAR |
clk:[F] |
clk:[R] |
-20.000 |
0.011 |
-0.407 |
+0.537 |
19 |
-20.408 |
+20.541 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_6_s5/CLEAR |
clk:[F] |
clk:[R] |
-20.000 |
0.011 |
-0.407 |
+0.540 |
20 |
-20.408 |
+20.541 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-gw_gao_inst_0/u_ao_top/trigger_seq_start_s1/CLEAR |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR |
clk:[F] |
clk:[R] |
-20.000 |
0.011 |
-0.407 |
+0.540 |
21 |
-20.408 |
+20.541 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-gw_gao_inst_0/u_ao_top/internal_reg_start_dly_1_s0/CLEAR |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR |
clk:[F] |
clk:[R] |
-20.000 |
0.011 |
-0.407 |
+0.540 |
22 |
-20.613 |
+20.541 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-gw_gao_inst_0/u_ao_top/internal_reg_start_syn_0_s0/CLEAR |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_11_s1/CLEAR |
clk:[F] |
clk:[R] |
-20.000 |
0.011 |
-0.612 |
+0.540 |
23 |
-20.613 |
+20.546 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-gw_gao_inst_0/u_ao_top/internal_reg_start_syn_1_s0/CLEAR |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLEAR |
clk:[F] |
clk:[R] |
-20.000 |
0.011 |
-0.612 |
+0.545 |
24 |
-20.622 |
+20.546 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-gw_gao_inst_0/u_ao_top/capture_start_sel_s1/CLEAR |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_12_s6/CLEAR |
clk:[F] |
clk:[R] |
-20.000 |
0.011 |
-0.621 |
+0.545 |
25 |
-20.622 |
+20.650 |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-gw_gao_inst_0/u_ao_top/capture_end_dly_s0/PRESET |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_1_s5/CLEAR |
clk:[F] |
clk:[R] |
-20.000 |
0.011 |
-0.621 |
+0.648 |
@@ -1522,7 +1522,7 @@ Report Command:report_min_pulse_width -nworst 10 -detail
0.862 |
Low Pulse Width |
clk |
-arkanoid/qx_2_s1 |
+arkanoid/score[6]_2_s0 |
8 |
@@ -1531,7 +1531,7 @@ Report Command:report_min_pulse_width -nworst 10 -detail
0.862 |
Low Pulse Width |
clk |
-arkanoid/qx_1_s1 |
+DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0 |
9 |
@@ -1540,7 +1540,7 @@ Report Command:report_min_pulse_width -nworst 10 -detail
0.862 |
Low Pulse Width |
clk |
-s480p/y_9_s0 |
+DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/c1_d_s0 |
10 |
@@ -1549,7 +1549,7 @@ Report Command:report_min_pulse_width -nworst 10 -detail
0.862 |
Low Pulse Width |
clk |
-arkanoid/qxb_8_s2 |
+arkanoid/score[6]_4_s0 |
@@ -1560,11 +1560,11 @@ Path1
Slack |
-8.006 |
+7.587 |
Data Arrival Time |
-152.726 |
+153.144 |
Data Required Time |
@@ -1658,7 +1658,7 @@ Path1
tNET |
RR |
1 |
-R41C26[0][A] |
+R44C19[0][A] |
gw_gao_inst_0/u_ao_top/internal_reg_start_s1/CLK |
@@ -1667,16 +1667,16 @@ Path1
tC2Q |
RF |
2 |
-R41C26[0][A] |
+R44C19[0][A] |
gw_gao_inst_0/u_ao_top/internal_reg_start_s1/Q |
-152.726 |
-0.678 |
+153.144 |
+1.096 |
tNET |
FF |
1 |
-R43C27[0][B] |
+R44C19[1][A] |
gw_gao_inst_0/u_ao_top/internal_reg_start_syn_0_s0/D |
@@ -1723,7 +1723,7 @@ Path1
0.587 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -1733,7 +1733,7 @@ Path1
tNET |
RR |
1 |
-R43C27[0][B] |
+R44C19[1][A] |
gw_gao_inst_0/u_ao_top/internal_reg_start_syn_0_s0/CLK |
@@ -1751,7 +1751,7 @@ Path1
tSu |
|
1 |
-R43C27[0][B] |
+R44C19[1][A] |
gw_gao_inst_0/u_ao_top/internal_reg_start_syn_0_s0 |
@@ -1775,7 +1775,7 @@ Path1
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.678, 77.218%; tC2Q: 0.200, 22.782% |
+cell: 0.000, 0.000%; route: 1.096, 84.572%; tC2Q: 0.200, 15.428% |
Required Clock Path Delay |
@@ -1787,11 +1787,11 @@ Path2
Slack |
-10.063 |
+9.708 |
Data Arrival Time |
-41.720 |
+42.075 |
Data Required Time |
@@ -1857,7 +1857,7 @@ Path2
0.587 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -1867,7 +1867,7 @@ Path2
tNET |
RR |
1 |
-R39C25[2][A] |
+R40C21[2][A] |
gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
@@ -1876,34 +1876,34 @@ Path2
tC2Q |
RF |
26 |
-R39C25[2][A] |
+R40C21[2][A] |
gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q |
-41.400 |
-0.403 |
+41.584 |
+0.587 |
tNET |
FF |
1 |
-R41C26[1][A] |
+R44C21[0][A] |
gw_gao_inst_0/u_ao_top/n836_s1/I0 |
-41.720 |
-0.320 |
+42.075 |
+0.491 |
tINS |
-FF |
+FR |
1 |
-R41C26[1][A] |
+R44C21[0][A] |
gw_gao_inst_0/u_ao_top/n836_s1/F |
-41.720 |
+42.075 |
0.000 |
tNET |
-FF |
+RR |
1 |
-R41C26[1][A] |
+R44C21[0][A] |
gw_gao_inst_0/u_ao_top/capture_end_tck_0_s0/D |
@@ -1978,7 +1978,7 @@ Path2
tNET |
RR |
1 |
-R41C26[1][A] |
+R44C21[0][A] |
gw_gao_inst_0/u_ao_top/capture_end_tck_0_s0/CLK |
@@ -1996,7 +1996,7 @@ Path2
tSu |
|
1 |
-R41C26[1][A] |
+R44C21[0][A] |
gw_gao_inst_0/u_ao_top/capture_end_tck_0_s0 |
@@ -2020,7 +2020,7 @@ Path2
Arrival Data Path Delay |
-cell: 0.320, 34.643%; route: 0.403, 43.693%; tC2Q: 0.200, 21.664% |
+cell: 0.491, 38.435%; route: 0.587, 45.921%; tC2Q: 0.200, 15.644% |
Required Clock Path Delay |
@@ -2032,11 +2032,11 @@ Path3
Slack |
-33.407 |
+31.877 |
Data Arrival Time |
-7.360 |
+8.890 |
Data Required Time |
@@ -2044,11 +2044,11 @@ Path3
From |
-arkanoid/qxb_5_s2 |
+arkanoid/score_counter_4_s0 |
To |
-arkanoid/qxb_5_s2 |
+arkanoid/score_1[2]_2_s0 |
Launch Clk |
@@ -2102,7 +2102,7 @@ Path3
0.587 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -2112,152 +2112,242 @@ Path3
tNET |
RR |
1 |
-R43C40[0][B] |
-arkanoid/qxb_5_s2/CLK |
+R41C43[1][A] |
+arkanoid/score_counter_4_s0/CLK |
0.997 |
0.200 |
tC2Q |
RF |
-22 |
-R43C40[0][B] |
-arkanoid/qxb_5_s2/Q |
+19 |
+R41C43[1][A] |
+arkanoid/score_counter_4_s0/Q |
-1.393 |
-0.396 |
+1.370 |
+0.374 |
tNET |
FF |
1 |
-R42C39[0][B] |
-arkanoid/n155_s4/I1 |
+R42C41[3][B] |
+arkanoid/n7053_s12/I0 |
-1.839 |
-0.446 |
+1.849 |
+0.478 |
tINS |
FF |
-8 |
-R42C39[0][B] |
-arkanoid/n155_s4/F |
+16 |
+R42C41[3][B] |
+arkanoid/n7053_s12/F |
-2.219 |
-0.380 |
+1.871 |
+0.023 |
tNET |
FF |
1 |
-R41C40[2][A] |
-arkanoid/n9052_s3/I2 |
+R42C41[2][B] |
+arkanoid/n7054_s15/I2 |
+
+
+2.345 |
+0.473 |
+tINS |
+FR |
+1 |
+R42C41[2][B] |
+arkanoid/n7054_s15/F |
+
+
+2.469 |
+0.124 |
+tNET |
+RR |
+1 |
+R42C41[3][A] |
+arkanoid/n7054_s13/I3 |
+
+
+2.960 |
+0.491 |
+tINS |
+RR |
+1 |
+R42C41[3][A] |
+arkanoid/n7054_s13/F |
+
+
+2.961 |
+0.001 |
+tNET |
+RR |
+1 |
+R42C41[2][A] |
+arkanoid/n7054_s12/I0 |
-2.609 |
+3.352 |
0.390 |
tINS |
+RF |
+11 |
+R42C41[2][A] |
+arkanoid/n7054_s12/F |
+
+
+3.709 |
+0.357 |
+tNET |
+FF |
+1 |
+R42C42[2][A] |
+arkanoid/n7055_s21/I1 |
+
+
+4.155 |
+0.446 |
+tINS |
FF |
-7 |
-R41C40[2][A] |
-arkanoid/n9052_s3/F |
+3 |
+R42C42[2][A] |
+arkanoid/n7055_s21/F |
-2.964 |
-0.355 |
+4.720 |
+0.565 |
tNET |
FF |
1 |
-R41C39[0][A] |
-arkanoid/n3294_s37/I0 |
+R44C44[2][A] |
+arkanoid/n7055_s19/I2 |
-3.442 |
+5.198 |
0.478 |
tINS |
FF |
-1 |
-R41C39[0][A] |
-arkanoid/n3294_s37/F |
+16 |
+R44C44[2][A] |
+arkanoid/n7055_s19/F |
-4.007 |
-0.565 |
+5.225 |
+0.026 |
tNET |
FF |
1 |
-R44C39[0][A] |
-arkanoid/n3294_s20/I3 |
+R44C44[3][A] |
+arkanoid/n7056_s22/I2 |
-4.499 |
-0.491 |
+5.623 |
+0.398 |
tINS |
FR |
1 |
-R44C39[0][A] |
-arkanoid/n3294_s20/F |
+R44C44[3][A] |
+arkanoid/n7056_s22/F |
-4.500 |
+5.624 |
0.001 |
tNET |
RR |
1 |
-R44C39[3][A] |
-arkanoid/n3294_s9/I2 |
+R44C44[3][B] |
+arkanoid/n7056_s21/I2 |
-4.820 |
-0.320 |
+6.022 |
+0.398 |
tINS |
-RF |
+RR |
1 |
-R44C39[3][A] |
-arkanoid/n3294_s9/F |
+R44C44[3][B] |
+arkanoid/n7056_s21/F |
-5.176 |
-0.356 |
+6.023 |
+0.001 |
tNET |
-FF |
+RR |
1 |
-R43C38[1][B] |
-arkanoid/n3294_s4/I2 |
+R44C44[2][B] |
+arkanoid/n7056_s20/I3 |
-5.654 |
-0.478 |
+6.497 |
+0.473 |
tINS |
-FF |
-4 |
-R43C38[1][B] |
-arkanoid/n3294_s4/F |
+RR |
+25 |
+R44C44[2][B] |
+arkanoid/n7056_s20/F |
-6.256 |
-0.602 |
+6.506 |
+0.009 |
+tNET |
+RR |
+1 |
+R44C44[1][B] |
+arkanoid/n7059_s3/I0 |
+
+
+6.952 |
+0.446 |
+tINS |
+RF |
+12 |
+R44C44[1][B] |
+arkanoid/n7059_s3/F |
+
+
+7.331 |
+0.379 |
tNET |
FF |
1 |
-R39C41[2][A] |
-arkanoid/qxb_9_s2/I0 |
+R44C43[0][B] |
+arkanoid/n7127_s1/I0 |
-6.730 |
-0.473 |
+7.729 |
+0.398 |
tINS |
FR |
-10 |
-R39C41[2][A] |
-arkanoid/qxb_9_s2/F |
+2 |
+R44C43[0][B] |
+arkanoid/n7127_s1/F |
-7.360 |
-0.630 |
+7.731 |
+0.002 |
tNET |
RR |
1 |
-R43C40[0][B] |
-arkanoid/qxb_5_s2/CE |
+R44C43[1][A] |
+arkanoid/n7139_s1/I3 |
+
+
+8.210 |
+0.478 |
+tINS |
+RF |
+2 |
+R44C43[1][A] |
+arkanoid/n7139_s1/F |
+
+
+8.890 |
+0.680 |
+tNET |
+FF |
+1 |
+R42C44[2][B] |
+arkanoid/score_1[2]_2_s0/D |
Data Required Path:
@@ -2303,7 +2393,7 @@ Path3
0.587 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -2313,8 +2403,8 @@ Path3
tNET |
RR |
1 |
-R43C40[0][B] |
-arkanoid/qxb_5_s2/CLK |
+R42C44[2][B] |
+arkanoid/score_1[2]_2_s0/CLK |
40.767 |
@@ -2322,8 +2412,8 @@ Path3
tSu |
|
1 |
-R43C40[0][B] |
-arkanoid/qxb_5_s2 |
+R42C44[2][B] |
+arkanoid/score_1[2]_2_s0 |
Path Statistics:
@@ -2338,7 +2428,7 @@ Path3
Logic Level |
-8 |
+13 |
Arrival Clock Path Delay |
@@ -2346,7 +2436,7 @@ Path3
Arrival Data Path Delay |
-cell: 3.077, 46.889%; route: 3.286, 50.064%; tC2Q: 0.200, 3.047% |
+cell: 5.350, 66.103%; route: 2.543, 31.426%; tC2Q: 0.200, 2.471% |
Required Clock Path Delay |
@@ -2358,11 +2448,11 @@ Path4
Slack |
-33.407 |
+32.184 |
Data Arrival Time |
-7.360 |
+8.583 |
Data Required Time |
@@ -2370,11 +2460,11 @@ Path4
From |
-arkanoid/qxb_5_s2 |
+arkanoid/score_counter_4_s0 |
To |
-arkanoid/qxb_4_s2 |
+arkanoid/score_1[4]_4_s0 |
Launch Clk |
@@ -2428,7 +2518,7 @@ Path4
0.587 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -2438,152 +2528,242 @@ Path4
tNET |
RR |
1 |
-R43C40[0][B] |
-arkanoid/qxb_5_s2/CLK |
+R41C43[1][A] |
+arkanoid/score_counter_4_s0/CLK |
0.997 |
0.200 |
tC2Q |
RF |
-22 |
-R43C40[0][B] |
-arkanoid/qxb_5_s2/Q |
+19 |
+R41C43[1][A] |
+arkanoid/score_counter_4_s0/Q |
-1.393 |
-0.396 |
+1.370 |
+0.374 |
tNET |
FF |
1 |
-R42C39[0][B] |
-arkanoid/n155_s4/I1 |
+R42C41[3][B] |
+arkanoid/n7053_s12/I0 |
-1.839 |
-0.446 |
+1.849 |
+0.478 |
tINS |
FF |
-8 |
-R42C39[0][B] |
-arkanoid/n155_s4/F |
+16 |
+R42C41[3][B] |
+arkanoid/n7053_s12/F |
-2.219 |
-0.380 |
+1.871 |
+0.023 |
tNET |
FF |
1 |
-R41C40[2][A] |
-arkanoid/n9052_s3/I2 |
+R42C41[2][B] |
+arkanoid/n7054_s15/I2 |
+
+
+2.345 |
+0.473 |
+tINS |
+FR |
+1 |
+R42C41[2][B] |
+arkanoid/n7054_s15/F |
+
+
+2.469 |
+0.124 |
+tNET |
+RR |
+1 |
+R42C41[3][A] |
+arkanoid/n7054_s13/I3 |
+
+
+2.960 |
+0.491 |
+tINS |
+RR |
+1 |
+R42C41[3][A] |
+arkanoid/n7054_s13/F |
+
+
+2.961 |
+0.001 |
+tNET |
+RR |
+1 |
+R42C41[2][A] |
+arkanoid/n7054_s12/I0 |
-2.609 |
+3.352 |
0.390 |
tINS |
+RF |
+11 |
+R42C41[2][A] |
+arkanoid/n7054_s12/F |
+
+
+3.709 |
+0.357 |
+tNET |
FF |
-7 |
-R41C40[2][A] |
-arkanoid/n9052_s3/F |
+1 |
+R42C42[2][A] |
+arkanoid/n7055_s21/I1 |
-2.964 |
-0.355 |
+4.155 |
+0.446 |
+tINS |
+FF |
+3 |
+R42C42[2][A] |
+arkanoid/n7055_s21/F |
+
+
+4.720 |
+0.565 |
tNET |
FF |
1 |
-R41C39[0][A] |
-arkanoid/n3294_s37/I0 |
+R44C44[2][A] |
+arkanoid/n7055_s19/I2 |
-3.442 |
+5.198 |
0.478 |
tINS |
FF |
-1 |
-R41C39[0][A] |
-arkanoid/n3294_s37/F |
+16 |
+R44C44[2][A] |
+arkanoid/n7055_s19/F |
-4.007 |
-0.565 |
+5.225 |
+0.026 |
tNET |
FF |
1 |
-R44C39[0][A] |
-arkanoid/n3294_s20/I3 |
+R44C44[3][A] |
+arkanoid/n7056_s22/I2 |
-4.499 |
-0.491 |
+5.623 |
+0.398 |
tINS |
FR |
1 |
-R44C39[0][A] |
-arkanoid/n3294_s20/F |
+R44C44[3][A] |
+arkanoid/n7056_s22/F |
-4.500 |
+5.624 |
0.001 |
tNET |
RR |
1 |
-R44C39[3][A] |
-arkanoid/n3294_s9/I2 |
+R44C44[3][B] |
+arkanoid/n7056_s21/I2 |
-4.820 |
-0.320 |
+6.022 |
+0.398 |
tINS |
-RF |
+RR |
+1 |
+R44C44[3][B] |
+arkanoid/n7056_s21/F |
+
+
+6.023 |
+0.001 |
+tNET |
+RR |
+1 |
+R44C44[2][B] |
+arkanoid/n7056_s20/I3 |
+
+
+6.497 |
+0.473 |
+tINS |
+RR |
+25 |
+R44C44[2][B] |
+arkanoid/n7056_s20/F |
+
+
+6.506 |
+0.009 |
+tNET |
+RR |
1 |
-R44C39[3][A] |
-arkanoid/n3294_s9/F |
+R44C44[1][B] |
+arkanoid/n7059_s3/I0 |
+
+
+6.952 |
+0.446 |
+tINS |
+RF |
+12 |
+R44C44[1][B] |
+arkanoid/n7059_s3/F |
-5.176 |
-0.356 |
+7.396 |
+0.445 |
tNET |
FF |
1 |
-R43C38[1][B] |
-arkanoid/n3294_s4/I2 |
+R42C46[0][B] |
+arkanoid/n7092_s2/I0 |
-5.654 |
+7.875 |
0.478 |
tINS |
FF |
-4 |
-R43C38[1][B] |
-arkanoid/n3294_s4/F |
+2 |
+R42C46[0][B] |
+arkanoid/n7092_s2/F |
-6.256 |
-0.602 |
+8.091 |
+0.217 |
tNET |
FF |
1 |
-R39C41[2][A] |
-arkanoid/qxb_9_s2/I0 |
+R42C44[1][A] |
+arkanoid/n7110_s0/I2 |
-6.730 |
-0.473 |
+8.583 |
+0.491 |
tINS |
FR |
-10 |
-R39C41[2][A] |
-arkanoid/qxb_9_s2/F |
+1 |
+R42C44[1][A] |
+arkanoid/n7110_s0/F |
-7.360 |
-0.630 |
+8.583 |
+0.000 |
tNET |
RR |
1 |
-R43C40[0][A] |
-arkanoid/qxb_4_s2/CE |
+R42C44[1][A] |
+arkanoid/score_1[4]_4_s0/D |
Data Required Path:
@@ -2629,7 +2809,7 @@ Path4
0.587 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -2639,8 +2819,8 @@ Path4
tNET |
RR |
1 |
-R43C40[0][A] |
-arkanoid/qxb_4_s2/CLK |
+R42C44[1][A] |
+arkanoid/score_1[4]_4_s0/CLK |
40.767 |
@@ -2648,8 +2828,8 @@ Path4
tSu |
|
1 |
-R43C40[0][A] |
-arkanoid/qxb_4_s2 |
+R42C44[1][A] |
+arkanoid/score_1[4]_4_s0 |
Path Statistics:
@@ -2664,7 +2844,7 @@ Path4
Logic Level |
-8 |
+13 |
Arrival Clock Path Delay |
@@ -2672,7 +2852,7 @@ Path4
Arrival Data Path Delay |
-cell: 3.077, 46.889%; route: 3.286, 50.064%; tC2Q: 0.200, 3.047% |
+cell: 5.443, 69.903%; route: 2.143, 27.528%; tC2Q: 0.200, 2.569% |
Required Clock Path Delay |
@@ -2684,11 +2864,11 @@ Path5
Slack |
-33.437 |
+32.208 |
Data Arrival Time |
-7.330 |
+8.558 |
Data Required Time |
@@ -2696,11 +2876,11 @@ Path5
From |
-arkanoid/qxb_0_s0 |
+arkanoid/qyb_3_s0 |
To |
-arkanoid/qdy_s0 |
+arkanoid/score_counter_6_s0 |
Launch Clk |
@@ -2754,7 +2934,7 @@ Path5
0.587 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -2764,152 +2944,188 @@ Path5
tNET |
RR |
1 |
-R43C41[1][A] |
-arkanoid/qxb_0_s0/CLK |
+R36C34[0][A] |
+arkanoid/qyb_3_s0/CLK |
0.997 |
0.200 |
tC2Q |
RF |
-17 |
-R43C41[1][A] |
-arkanoid/qxb_0_s0/Q |
+12 |
+R36C34[0][A] |
+arkanoid/qyb_3_s0/Q |
-1.619 |
-0.623 |
+1.615 |
+0.618 |
tNET |
FF |
1 |
-R41C40[2][B] |
-arkanoid/n9048_s6/I0 |
+R39C38[1][B] |
+arkanoid/n10667_s4/I0 |
-2.010 |
-0.390 |
+2.061 |
+0.446 |
tINS |
FF |
-10 |
-R41C40[2][B] |
-arkanoid/n9048_s6/F |
+4 |
+R39C38[1][B] |
+arkanoid/n10667_s4/F |
-2.583 |
-0.573 |
+2.421 |
+0.360 |
tNET |
FF |
1 |
-R43C39[2][B] |
-arkanoid/n9048_s4/I0 |
+R40C39[1][B] |
+arkanoid/n10667_s1/I1 |
-2.973 |
-0.390 |
+2.899 |
+0.478 |
tINS |
FF |
-5 |
-R43C39[2][B] |
-arkanoid/n9048_s4/F |
+8 |
+R40C39[1][B] |
+arkanoid/n10667_s1/F |
-3.571 |
-0.597 |
+3.490 |
+0.591 |
tNET |
FF |
1 |
-R43C44[3][B] |
-arkanoid/n9048_s2/I0 |
+R41C43[2][B] |
+arkanoid/n3739_s10/I1 |
-3.961 |
+3.880 |
0.390 |
tINS |
FF |
-4 |
-R43C44[3][B] |
-arkanoid/n9048_s2/F |
+10 |
+R41C43[2][B] |
+arkanoid/n3739_s10/F |
-4.182 |
-0.221 |
+4.851 |
+0.971 |
tNET |
FF |
1 |
-R41C44[0][A] |
-arkanoid/n3294_s29/I3 |
+R40C44[0][B] |
+arkanoid/n3737_s15/I3 |
-4.655 |
-0.473 |
+5.343 |
+0.491 |
tINS |
FR |
-1 |
-R41C44[0][A] |
-arkanoid/n3294_s29/F |
+2 |
+R40C44[0][B] |
+arkanoid/n3737_s15/F |
-4.804 |
-0.149 |
+5.492 |
+0.150 |
tNET |
RR |
1 |
-R41C43[3][A] |
-arkanoid/n3294_s13/I0 |
+R40C43[2][A] |
+arkanoid/n3737_s20/I3 |
-5.194 |
-0.390 |
+5.971 |
+0.478 |
tINS |
RF |
-2 |
-R41C43[3][A] |
-arkanoid/n3294_s13/F |
+3 |
+R40C43[2][A] |
+arkanoid/n3737_s20/F |
-5.765 |
-0.570 |
+6.335 |
+0.364 |
tNET |
FF |
1 |
-R39C42[3][B] |
-arkanoid/n3294_s6/I1 |
+R41C44[3][B] |
+arkanoid/n3737_s3/I3 |
-6.210 |
-0.446 |
+6.654 |
+0.320 |
tINS |
FF |
+3 |
+R41C44[3][B] |
+arkanoid/n3737_s3/F |
+
+
+6.872 |
+0.218 |
+tNET |
+FF |
+1 |
+R41C42[1][A] |
+arkanoid/n3735_s14/I1 |
+
+
+7.346 |
+0.473 |
+tINS |
+FR |
+1 |
+R41C42[1][A] |
+arkanoid/n3735_s14/F |
+
+
+7.494 |
+0.149 |
+tNET |
+RR |
+1 |
+R40C42[2][B] |
+arkanoid/n3735_s4/I2 |
+
+
+7.814 |
+0.320 |
+tINS |
+RF |
2 |
-R39C42[3][B] |
-arkanoid/n3294_s6/F |
+R40C42[2][B] |
+arkanoid/n3735_s4/F |
-6.765 |
-0.555 |
+8.160 |
+0.346 |
tNET |
FF |
1 |
-R38C41[2][B] |
-arkanoid/qdy_s3/I1 |
+R40C41[0][A] |
+arkanoid/n3736_s1/I3 |
-7.047 |
-0.282 |
+8.558 |
+0.398 |
tINS |
FR |
1 |
-R38C41[2][B] |
-arkanoid/qdy_s3/F |
+R40C41[0][A] |
+arkanoid/n3736_s1/F |
-7.330 |
-0.283 |
+8.558 |
+0.000 |
tNET |
RR |
1 |
-R38C40[2][A] |
-arkanoid/qdy_s0/CE |
+R40C41[0][A] |
+arkanoid/score_counter_6_s0/D |
Data Required Path:
@@ -2955,7 +3171,7 @@ Path5
0.587 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -2965,8 +3181,8 @@ Path5
tNET |
RR |
1 |
-R38C40[2][A] |
-arkanoid/qdy_s0/CLK |
+R40C41[0][A] |
+arkanoid/score_counter_6_s0/CLK |
40.767 |
@@ -2974,8 +3190,8 @@ Path5
tSu |
|
1 |
-R38C40[2][A] |
-arkanoid/qdy_s0 |
+R40C41[0][A] |
+arkanoid/score_counter_6_s0 |
Path Statistics:
@@ -2990,7 +3206,7 @@ Path5
Logic Level |
-8 |
+10 |
Arrival Clock Path Delay |
@@ -2998,7 +3214,7 @@ Path5
Arrival Data Path Delay |
-cell: 2.763, 42.288%; route: 3.570, 54.651%; tC2Q: 0.200, 3.061% |
+cell: 3.795, 48.900%; route: 3.766, 48.524%; tC2Q: 0.200, 2.577% |
Required Clock Path Delay |
@@ -3010,11 +3226,11 @@ Path6
Slack |
-33.514 |
+32.212 |
Data Arrival Time |
-7.253 |
+8.554 |
Data Required Time |
@@ -3022,11 +3238,11 @@ Path6
From |
-arkanoid/qxb_0_s0 |
+arkanoid/score_counter_4_s0 |
To |
-arkanoid/qdy_s0 |
+arkanoid/score_1[5]_3_s0 |
Launch Clk |
@@ -3080,7 +3296,7 @@ Path6
0.587 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -3090,152 +3306,242 @@ Path6
tNET |
RR |
1 |
-R43C41[1][A] |
-arkanoid/qxb_0_s0/CLK |
+R41C43[1][A] |
+arkanoid/score_counter_4_s0/CLK |
0.997 |
0.200 |
tC2Q |
RF |
-17 |
-R43C41[1][A] |
-arkanoid/qxb_0_s0/Q |
+19 |
+R41C43[1][A] |
+arkanoid/score_counter_4_s0/Q |
-1.619 |
-0.623 |
+1.370 |
+0.374 |
tNET |
FF |
1 |
-R41C40[2][B] |
-arkanoid/n9048_s6/I0 |
+R42C41[3][B] |
+arkanoid/n7053_s12/I0 |
-2.010 |
-0.390 |
+1.849 |
+0.478 |
tINS |
FF |
-10 |
-R41C40[2][B] |
-arkanoid/n9048_s6/F |
+16 |
+R42C41[3][B] |
+arkanoid/n7053_s12/F |
-2.583 |
-0.573 |
+1.871 |
+0.023 |
tNET |
FF |
1 |
-R43C39[2][B] |
-arkanoid/n9048_s4/I0 |
+R42C41[2][B] |
+arkanoid/n7054_s15/I2 |
-2.973 |
-0.390 |
+2.345 |
+0.473 |
tINS |
-FF |
-5 |
-R43C39[2][B] |
-arkanoid/n9048_s4/F |
+FR |
+1 |
+R42C41[2][B] |
+arkanoid/n7054_s15/F |
-3.571 |
-0.597 |
+2.469 |
+0.124 |
tNET |
-FF |
+RR |
1 |
-R43C44[3][B] |
-arkanoid/n9048_s2/I0 |
+R42C41[3][A] |
+arkanoid/n7054_s13/I3 |
-3.961 |
-0.390 |
+2.960 |
+0.491 |
+tINS |
+RR |
+1 |
+R42C41[3][A] |
+arkanoid/n7054_s13/F |
+
+
+2.961 |
+0.001 |
+tNET |
+RR |
+1 |
+R42C41[2][A] |
+arkanoid/n7054_s12/I0 |
+
+
+3.352 |
+0.390 |
+tINS |
+RF |
+11 |
+R42C41[2][A] |
+arkanoid/n7054_s12/F |
+
+
+3.709 |
+0.357 |
+tNET |
+FF |
+1 |
+R42C42[2][A] |
+arkanoid/n7055_s21/I1 |
+
+
+4.155 |
+0.446 |
tINS |
FF |
-4 |
-R43C44[3][B] |
-arkanoid/n9048_s2/F |
+3 |
+R42C42[2][A] |
+arkanoid/n7055_s21/F |
-4.182 |
-0.221 |
+4.720 |
+0.565 |
tNET |
FF |
1 |
-R41C44[0][A] |
-arkanoid/n3294_s29/I3 |
+R44C44[2][A] |
+arkanoid/n7055_s19/I2 |
-4.655 |
-0.473 |
+5.198 |
+0.478 |
+tINS |
+FF |
+16 |
+R44C44[2][A] |
+arkanoid/n7055_s19/F |
+
+
+5.225 |
+0.026 |
+tNET |
+FF |
+1 |
+R44C44[3][A] |
+arkanoid/n7056_s22/I2 |
+
+
+5.623 |
+0.398 |
tINS |
FR |
1 |
-R41C44[0][A] |
-arkanoid/n3294_s29/F |
+R44C44[3][A] |
+arkanoid/n7056_s22/F |
-4.804 |
-0.149 |
+5.624 |
+0.001 |
tNET |
RR |
1 |
-R41C43[3][A] |
-arkanoid/n3294_s13/I0 |
+R44C44[3][B] |
+arkanoid/n7056_s21/I2 |
-5.194 |
-0.390 |
+6.022 |
+0.398 |
+tINS |
+RR |
+1 |
+R44C44[3][B] |
+arkanoid/n7056_s21/F |
+
+
+6.023 |
+0.001 |
+tNET |
+RR |
+1 |
+R44C44[2][B] |
+arkanoid/n7056_s20/I3 |
+
+
+6.497 |
+0.473 |
+tINS |
+RR |
+25 |
+R44C44[2][B] |
+arkanoid/n7056_s20/F |
+
+
+6.506 |
+0.009 |
+tNET |
+RR |
+1 |
+R44C44[1][B] |
+arkanoid/n7059_s3/I0 |
+
+
+6.952 |
+0.446 |
tINS |
RF |
-2 |
-R41C43[3][A] |
-arkanoid/n3294_s13/F |
+12 |
+R44C44[1][B] |
+arkanoid/n7059_s3/F |
-5.765 |
-0.570 |
+7.396 |
+0.445 |
tNET |
FF |
1 |
-R39C42[3][B] |
-arkanoid/n3294_s6/I1 |
+R42C46[0][B] |
+arkanoid/n7092_s2/I0 |
-6.210 |
-0.446 |
+7.875 |
+0.478 |
tINS |
FF |
2 |
-R39C42[3][B] |
-arkanoid/n3294_s6/F |
+R42C46[0][B] |
+arkanoid/n7092_s2/F |
-6.779 |
-0.569 |
+8.234 |
+0.360 |
tNET |
FF |
1 |
-R38C40[2][A] |
-arkanoid/n3294_s3/I2 |
+R42C44[0][B] |
+arkanoid/n7100_s1/I3 |
-7.253 |
-0.473 |
+8.554 |
+0.320 |
tINS |
-FR |
+FF |
1 |
-R38C40[2][A] |
-arkanoid/n3294_s3/F |
+R42C44[0][B] |
+arkanoid/n7100_s1/F |
-7.253 |
+8.554 |
0.000 |
tNET |
-RR |
+FF |
1 |
-R38C40[2][A] |
-arkanoid/qdy_s0/D |
+R42C44[0][B] |
+arkanoid/score_1[5]_3_s0/D |
Data Required Path:
@@ -3281,7 +3587,7 @@ Path6
0.587 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -3291,8 +3597,8 @@ Path6
tNET |
RR |
1 |
-R38C40[2][A] |
-arkanoid/qdy_s0/CLK |
+R42C44[0][B] |
+arkanoid/score_1[5]_3_s0/CLK |
40.767 |
@@ -3300,8 +3606,8 @@ Path6
tSu |
|
1 |
-R38C40[2][A] |
-arkanoid/qdy_s0 |
+R42C44[0][B] |
+arkanoid/score_1[5]_3_s0 |
Path Statistics:
@@ -3316,7 +3622,7 @@ Path6
Logic Level |
-8 |
+13 |
Arrival Clock Path Delay |
@@ -3324,7 +3630,7 @@ Path6
Arrival Data Path Delay |
-cell: 2.954, 45.758%; route: 3.302, 51.144%; tC2Q: 0.200, 3.098% |
+cell: 5.271, 67.948%; route: 2.286, 29.474%; tC2Q: 0.200, 2.578% |
Required Clock Path Delay |
@@ -3336,11 +3642,11 @@ Path7
Slack |
-33.565 |
+32.222 |
Data Arrival Time |
-7.201 |
+8.545 |
Data Required Time |
@@ -3348,11 +3654,11 @@ Path7
From |
-arkanoid/qxb_5_s2 |
+arkanoid/score_counter_4_s0 |
To |
-arkanoid/qxb_0_s0 |
+arkanoid/score_1[2]_1_s0 |
Launch Clk |
@@ -3406,7 +3712,7 @@ Path7
0.587 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -3416,152 +3722,260 @@ Path7
tNET |
RR |
1 |
-R43C40[0][B] |
-arkanoid/qxb_5_s2/CLK |
+R41C43[1][A] |
+arkanoid/score_counter_4_s0/CLK |
0.997 |
0.200 |
tC2Q |
RF |
-22 |
-R43C40[0][B] |
-arkanoid/qxb_5_s2/Q |
+19 |
+R41C43[1][A] |
+arkanoid/score_counter_4_s0/Q |
-1.393 |
-0.396 |
+1.370 |
+0.374 |
tNET |
FF |
1 |
-R42C39[0][B] |
-arkanoid/n155_s4/I1 |
+R42C41[3][B] |
+arkanoid/n7053_s12/I0 |
-1.839 |
-0.446 |
+1.849 |
+0.478 |
tINS |
FF |
-8 |
-R42C39[0][B] |
-arkanoid/n155_s4/F |
+16 |
+R42C41[3][B] |
+arkanoid/n7053_s12/F |
-2.219 |
-0.380 |
+1.871 |
+0.023 |
tNET |
FF |
1 |
-R41C40[2][A] |
-arkanoid/n9052_s3/I2 |
+R42C41[2][B] |
+arkanoid/n7054_s15/I2 |
+
+
+2.345 |
+0.473 |
+tINS |
+FR |
+1 |
+R42C41[2][B] |
+arkanoid/n7054_s15/F |
+
+
+2.469 |
+0.124 |
+tNET |
+RR |
+1 |
+R42C41[3][A] |
+arkanoid/n7054_s13/I3 |
+
+
+2.960 |
+0.491 |
+tINS |
+RR |
+1 |
+R42C41[3][A] |
+arkanoid/n7054_s13/F |
+
+
+2.961 |
+0.001 |
+tNET |
+RR |
+1 |
+R42C41[2][A] |
+arkanoid/n7054_s12/I0 |
-2.609 |
+3.352 |
0.390 |
tINS |
+RF |
+11 |
+R42C41[2][A] |
+arkanoid/n7054_s12/F |
+
+
+3.709 |
+0.357 |
+tNET |
FF |
-7 |
-R41C40[2][A] |
-arkanoid/n9052_s3/F |
+1 |
+R42C42[2][A] |
+arkanoid/n7055_s21/I1 |
-2.964 |
-0.355 |
+4.155 |
+0.446 |
+tINS |
+FF |
+3 |
+R42C42[2][A] |
+arkanoid/n7055_s21/F |
+
+
+4.720 |
+0.565 |
tNET |
FF |
1 |
-R41C39[0][A] |
-arkanoid/n3294_s37/I0 |
+R44C44[2][A] |
+arkanoid/n7055_s19/I2 |
-3.442 |
+5.198 |
0.478 |
tINS |
FF |
-1 |
-R41C39[0][A] |
-arkanoid/n3294_s37/F |
+16 |
+R44C44[2][A] |
+arkanoid/n7055_s19/F |
-4.007 |
-0.565 |
+5.225 |
+0.026 |
tNET |
FF |
1 |
-R44C39[0][A] |
-arkanoid/n3294_s20/I3 |
+R44C44[3][A] |
+arkanoid/n7056_s22/I2 |
-4.499 |
-0.491 |
+5.623 |
+0.398 |
tINS |
FR |
1 |
-R44C39[0][A] |
-arkanoid/n3294_s20/F |
+R44C44[3][A] |
+arkanoid/n7056_s22/F |
-4.500 |
+5.624 |
0.001 |
tNET |
RR |
1 |
-R44C39[3][A] |
-arkanoid/n3294_s9/I2 |
+R44C44[3][B] |
+arkanoid/n7056_s21/I2 |
-4.820 |
-0.320 |
+6.022 |
+0.398 |
tINS |
-RF |
+RR |
1 |
-R44C39[3][A] |
-arkanoid/n3294_s9/F |
+R44C44[3][B] |
+arkanoid/n7056_s21/F |
-5.176 |
-0.356 |
+6.023 |
+0.001 |
tNET |
-FF |
+RR |
1 |
-R43C38[1][B] |
-arkanoid/n3294_s4/I2 |
+R44C44[2][B] |
+arkanoid/n7056_s20/I3 |
-5.654 |
-0.478 |
+6.497 |
+0.473 |
tINS |
-FF |
-4 |
-R43C38[1][B] |
-arkanoid/n3294_s4/F |
+RR |
+25 |
+R44C44[2][B] |
+arkanoid/n7056_s20/F |
-6.256 |
-0.602 |
+6.506 |
+0.009 |
+tNET |
+RR |
+1 |
+R44C44[1][B] |
+arkanoid/n7059_s3/I0 |
+
+
+6.952 |
+0.446 |
+tINS |
+RF |
+12 |
+R44C44[1][B] |
+arkanoid/n7059_s3/F |
+
+
+7.331 |
+0.379 |
tNET |
FF |
1 |
-R39C41[2][A] |
-arkanoid/qxb_9_s2/I0 |
+R44C43[0][B] |
+arkanoid/n7127_s1/I0 |
-6.730 |
-0.473 |
+7.729 |
+0.398 |
tINS |
FR |
-10 |
-R39C41[2][A] |
-arkanoid/qxb_9_s2/F |
+2 |
+R44C43[0][B] |
+arkanoid/n7127_s1/F |
+
+
+7.731 |
+0.002 |
+tNET |
+RR |
+1 |
+R44C43[1][A] |
+arkanoid/n7139_s1/I3 |
+
+
+8.223 |
+0.491 |
+tINS |
+RR |
+2 |
+R44C43[1][A] |
+arkanoid/n7139_s1/F |
-7.201 |
-0.472 |
+8.225 |
+0.002 |
tNET |
RR |
1 |
-R43C41[1][A] |
-arkanoid/qxb_0_s0/CE |
+R44C43[0][A] |
+arkanoid/n7141_s1/I1 |
+
+
+8.545 |
+0.320 |
+tINS |
+RF |
+1 |
+R44C43[0][A] |
+arkanoid/n7141_s1/F |
+
+
+8.545 |
+0.000 |
+tNET |
+FF |
+1 |
+R44C43[0][A] |
+arkanoid/score_1[2]_1_s0/D |
Data Required Path:
@@ -3607,7 +4021,7 @@ Path7
0.587 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -3617,8 +4031,8 @@ Path7
tNET |
RR |
1 |
-R43C41[1][A] |
-arkanoid/qxb_0_s0/CLK |
+R44C43[0][A] |
+arkanoid/score_1[2]_1_s0/CLK |
40.767 |
@@ -3626,8 +4040,8 @@ Path7
tSu |
|
1 |
-R43C41[1][A] |
-arkanoid/qxb_0_s0 |
+R44C43[0][A] |
+arkanoid/score_1[2]_1_s0 |
Path Statistics:
@@ -3642,7 +4056,7 @@ Path7
Logic Level |
-8 |
+14 |
Arrival Clock Path Delay |
@@ -3650,7 +4064,7 @@ Path7
Arrival Data Path Delay |
-cell: 3.077, 48.048%; route: 3.127, 48.829%; tC2Q: 0.200, 3.122% |
+cell: 5.682, 73.338%; route: 1.866, 24.081%; tC2Q: 0.200, 2.581% |
Required Clock Path Delay |
@@ -3662,11 +4076,11 @@ Path8
Slack |
-33.565 |
+32.282 |
Data Arrival Time |
-7.201 |
+8.484 |
Data Required Time |
@@ -3674,11 +4088,11 @@ Path8
From |
-arkanoid/qxb_5_s2 |
+arkanoid/score_counter_5_s0 |
To |
-arkanoid/qxb_1_s0 |
+arkanoid/score[5]_1_s0 |
Launch Clk |
@@ -3732,7 +4146,7 @@ Path8
0.587 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -3742,8 +4156,8 @@ Path8
tNET |
RR |
1 |
-R43C40[0][B] |
-arkanoid/qxb_5_s2/CLK |
+R41C42[0][A] |
+arkanoid/score_counter_5_s0/CLK |
0.997 |
@@ -3751,143 +4165,233 @@ Path8
tC2Q |
RF |
22 |
-R43C40[0][B] |
-arkanoid/qxb_5_s2/Q |
+R41C42[0][A] |
+arkanoid/score_counter_5_s0/Q |
-1.393 |
-0.396 |
+1.599 |
+0.602 |
tNET |
FF |
1 |
-R42C39[0][B] |
-arkanoid/n155_s4/I1 |
+R40C45[2][A] |
+arkanoid/n6846_s18/I3 |
-1.839 |
-0.446 |
+2.090 |
+0.491 |
tINS |
-FF |
-8 |
-R42C39[0][B] |
-arkanoid/n155_s4/F |
+FR |
+1 |
+R40C45[2][A] |
+arkanoid/n6846_s18/F |
-2.219 |
-0.380 |
+2.091 |
+0.001 |
tNET |
-FF |
+RR |
1 |
-R41C40[2][A] |
-arkanoid/n9052_s3/I2 |
+R40C45[2][B] |
+arkanoid/n6846_s17/I0 |
-2.609 |
-0.390 |
+2.489 |
+0.398 |
tINS |
-FF |
-7 |
-R41C40[2][A] |
-arkanoid/n9052_s3/F |
+RR |
+1 |
+R40C45[2][B] |
+arkanoid/n6846_s17/F |
+
+
+2.490 |
+0.001 |
+tNET |
+RR |
+1 |
+R40C45[3][A] |
+arkanoid/n6846_s13/I2 |
2.964 |
-0.355 |
+0.473 |
+tINS |
+RR |
+1 |
+R40C45[3][A] |
+arkanoid/n6846_s13/F |
+
+
+2.965 |
+0.001 |
tNET |
-FF |
+RR |
1 |
-R41C39[0][A] |
-arkanoid/n3294_s37/I0 |
+R40C45[3][B] |
+arkanoid/n6846_s8/I3 |
-3.442 |
-0.478 |
+3.355 |
+0.390 |
tINS |
+RF |
+4 |
+R40C45[3][B] |
+arkanoid/n6846_s8/F |
+
+
+3.370 |
+0.015 |
+tNET |
FF |
1 |
-R41C39[0][A] |
-arkanoid/n3294_s37/F |
+R40C45[1][B] |
+arkanoid/n6843_s17/I3 |
-4.007 |
-0.565 |
+3.816 |
+0.446 |
+tINS |
+FF |
+5 |
+R40C45[1][B] |
+arkanoid/n6843_s17/F |
+
+
+4.255 |
+0.439 |
tNET |
FF |
1 |
-R44C39[0][A] |
-arkanoid/n3294_s20/I3 |
+R38C43[3][B] |
+arkanoid/n6845_s6/I0 |
-4.499 |
+4.746 |
0.491 |
tINS |
FR |
1 |
-R44C39[0][A] |
-arkanoid/n3294_s20/F |
+R38C43[3][B] |
+arkanoid/n6845_s6/F |
-4.500 |
-0.001 |
+4.895 |
+0.149 |
tNET |
RR |
1 |
-R44C39[3][A] |
-arkanoid/n3294_s9/I2 |
+R38C44[3][A] |
+arkanoid/n6845_s5/I0 |
-4.820 |
+5.214 |
0.320 |
tINS |
RF |
-1 |
-R44C39[3][A] |
-arkanoid/n3294_s9/F |
+11 |
+R38C44[3][A] |
+arkanoid/n6845_s5/F |
-5.176 |
-0.356 |
+5.392 |
+0.177 |
tNET |
FF |
1 |
-R43C38[1][B] |
-arkanoid/n3294_s4/I2 |
+R38C43[3][A] |
+arkanoid/n6843_s16/I2 |
-5.654 |
-0.478 |
+5.782 |
+0.390 |
tINS |
FF |
-4 |
-R43C38[1][B] |
-arkanoid/n3294_s4/F |
+10 |
+R38C43[3][A] |
+arkanoid/n6843_s16/F |
-6.256 |
-0.602 |
+5.805 |
+0.023 |
tNET |
FF |
1 |
-R39C41[2][A] |
-arkanoid/qxb_9_s2/I0 |
+R38C43[2][A] |
+arkanoid/n6878_s2/I1 |
-6.730 |
-0.473 |
+6.196 |
+0.390 |
tINS |
-FR |
-10 |
-R39C41[2][A] |
-arkanoid/qxb_9_s2/F |
+FF |
+7 |
+R38C43[2][A] |
+arkanoid/n6878_s2/F |
-7.201 |
-0.472 |
+6.573 |
+0.377 |
+tNET |
+FF |
+1 |
+R38C40[3][B] |
+arkanoid/n6895_s3/I3 |
+
+
+7.019 |
+0.446 |
+tINS |
+FF |
+8 |
+R38C40[3][B] |
+arkanoid/n6895_s3/F |
+
+
+7.248 |
+0.229 |
+tNET |
+FF |
+1 |
+R36C40[3][B] |
+arkanoid/n6909_s1/I0 |
+
+
+7.726 |
+0.478 |
+tINS |
+FF |
+2 |
+R36C40[3][B] |
+arkanoid/n6909_s1/F |
+
+
+8.086 |
+0.360 |
+tNET |
+FF |
+1 |
+R36C43[1][B] |
+arkanoid/n6923_s2/I3 |
+
+
+8.484 |
+0.398 |
+tINS |
+FR |
+1 |
+R36C43[1][B] |
+arkanoid/n6923_s2/F |
+
+
+8.484 |
+0.000 |
tNET |
RR |
1 |
-R43C41[0][A] |
-arkanoid/qxb_1_s0/CE |
+R36C43[1][B] |
+arkanoid/score[5]_1_s0/D |
Data Required Path:
@@ -3933,7 +4437,7 @@ Path8
0.587 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -3943,8 +4447,8 @@ Path8
tNET |
RR |
1 |
-R43C41[0][A] |
-arkanoid/qxb_1_s0/CLK |
+R36C43[1][B] |
+arkanoid/score[5]_1_s0/CLK |
40.767 |
@@ -3952,8 +4456,8 @@ Path8
tSu |
|
1 |
-R43C41[0][A] |
-arkanoid/qxb_1_s0 |
+R36C43[1][B] |
+arkanoid/score[5]_1_s0 |
Path Statistics:
@@ -3968,7 +4472,7 @@ Path8
Logic Level |
-8 |
+13 |
Arrival Clock Path Delay |
@@ -3976,7 +4480,7 @@ Path8
Arrival Data Path Delay |
-cell: 3.077, 48.048%; route: 3.127, 48.829%; tC2Q: 0.200, 3.122% |
+cell: 5.113, 66.514%; route: 2.374, 30.885%; tC2Q: 0.200, 2.601% |
Required Clock Path Delay |
@@ -3988,11 +4492,11 @@ Path9
Slack |
-33.565 |
+32.365 |
Data Arrival Time |
-7.201 |
+8.401 |
Data Required Time |
@@ -4000,11 +4504,11 @@ Path9
From |
-arkanoid/qxb_5_s2 |
+arkanoid/score_counter_4_s0 |
To |
-arkanoid/qxb_2_s0 |
+arkanoid/score_1[3]_2_s0 |
Launch Clk |
@@ -4058,7 +4562,7 @@ Path9
0.587 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -4068,152 +4572,224 @@ Path9
tNET |
RR |
1 |
-R43C40[0][B] |
-arkanoid/qxb_5_s2/CLK |
+R41C43[1][A] |
+arkanoid/score_counter_4_s0/CLK |
0.997 |
0.200 |
tC2Q |
RF |
-22 |
-R43C40[0][B] |
-arkanoid/qxb_5_s2/Q |
+19 |
+R41C43[1][A] |
+arkanoid/score_counter_4_s0/Q |
-1.393 |
-0.396 |
+1.370 |
+0.374 |
tNET |
FF |
1 |
-R42C39[0][B] |
-arkanoid/n155_s4/I1 |
+R42C41[3][B] |
+arkanoid/n7053_s12/I0 |
-1.839 |
-0.446 |
+1.849 |
+0.478 |
tINS |
FF |
-8 |
-R42C39[0][B] |
-arkanoid/n155_s4/F |
+16 |
+R42C41[3][B] |
+arkanoid/n7053_s12/F |
-2.219 |
-0.380 |
+1.871 |
+0.023 |
tNET |
FF |
1 |
-R41C40[2][A] |
-arkanoid/n9052_s3/I2 |
+R42C41[2][B] |
+arkanoid/n7054_s15/I2 |
+
+
+2.345 |
+0.473 |
+tINS |
+FR |
+1 |
+R42C41[2][B] |
+arkanoid/n7054_s15/F |
+
+
+2.469 |
+0.124 |
+tNET |
+RR |
+1 |
+R42C41[3][A] |
+arkanoid/n7054_s13/I3 |
+
+
+2.960 |
+0.491 |
+tINS |
+RR |
+1 |
+R42C41[3][A] |
+arkanoid/n7054_s13/F |
-2.609 |
+2.961 |
+0.001 |
+tNET |
+RR |
+1 |
+R42C41[2][A] |
+arkanoid/n7054_s12/I0 |
+
+
+3.352 |
0.390 |
tINS |
+RF |
+11 |
+R42C41[2][A] |
+arkanoid/n7054_s12/F |
+
+
+3.709 |
+0.357 |
+tNET |
FF |
-7 |
-R41C40[2][A] |
-arkanoid/n9052_s3/F |
+1 |
+R42C42[2][A] |
+arkanoid/n7055_s21/I1 |
-2.964 |
-0.355 |
+4.155 |
+0.446 |
+tINS |
+FF |
+3 |
+R42C42[2][A] |
+arkanoid/n7055_s21/F |
+
+
+4.720 |
+0.565 |
tNET |
FF |
1 |
-R41C39[0][A] |
-arkanoid/n3294_s37/I0 |
+R44C44[2][A] |
+arkanoid/n7055_s19/I2 |
-3.442 |
+5.198 |
0.478 |
tINS |
FF |
-1 |
-R41C39[0][A] |
-arkanoid/n3294_s37/F |
+16 |
+R44C44[2][A] |
+arkanoid/n7055_s19/F |
-4.007 |
-0.565 |
+5.225 |
+0.026 |
tNET |
FF |
1 |
-R44C39[0][A] |
-arkanoid/n3294_s20/I3 |
+R44C44[3][A] |
+arkanoid/n7056_s22/I2 |
-4.499 |
-0.491 |
+5.623 |
+0.398 |
tINS |
FR |
1 |
-R44C39[0][A] |
-arkanoid/n3294_s20/F |
+R44C44[3][A] |
+arkanoid/n7056_s22/F |
-4.500 |
+5.624 |
0.001 |
tNET |
RR |
1 |
-R44C39[3][A] |
-arkanoid/n3294_s9/I2 |
+R44C44[3][B] |
+arkanoid/n7056_s21/I2 |
-4.820 |
-0.320 |
+6.022 |
+0.398 |
tINS |
-RF |
+RR |
+1 |
+R44C44[3][B] |
+arkanoid/n7056_s21/F |
+
+
+6.023 |
+0.001 |
+tNET |
+RR |
1 |
-R44C39[3][A] |
-arkanoid/n3294_s9/F |
+R44C44[2][B] |
+arkanoid/n7056_s20/I3 |
+
+
+6.497 |
+0.473 |
+tINS |
+RR |
+25 |
+R44C44[2][B] |
+arkanoid/n7056_s20/F |
-5.176 |
-0.356 |
+6.506 |
+0.009 |
tNET |
-FF |
+RR |
1 |
-R43C38[1][B] |
-arkanoid/n3294_s4/I2 |
+R44C44[1][B] |
+arkanoid/n7059_s3/I0 |
-5.654 |
-0.478 |
+6.952 |
+0.446 |
tINS |
-FF |
-4 |
-R43C38[1][B] |
-arkanoid/n3294_s4/F |
+RF |
+12 |
+R44C44[1][B] |
+arkanoid/n7059_s3/F |
-6.256 |
-0.602 |
+7.331 |
+0.379 |
tNET |
FF |
1 |
-R39C41[2][A] |
-arkanoid/qxb_9_s2/I0 |
+R44C43[0][B] |
+arkanoid/n7127_s1/I0 |
-6.730 |
-0.473 |
+7.721 |
+0.390 |
tINS |
-FR |
-10 |
-R39C41[2][A] |
-arkanoid/qxb_9_s2/F |
+FF |
+2 |
+R44C43[0][B] |
+arkanoid/n7127_s1/F |
-7.201 |
-0.472 |
+8.401 |
+0.680 |
tNET |
-RR |
+FF |
1 |
-R43C41[0][B] |
-arkanoid/qxb_2_s0/CE |
+R42C44[2][A] |
+arkanoid/score_1[3]_2_s0/D |
Data Required Path:
@@ -4259,7 +4835,7 @@ Path9
0.587 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -4269,8 +4845,8 @@ Path9
tNET |
RR |
1 |
-R43C41[0][B] |
-arkanoid/qxb_2_s0/CLK |
+R42C44[2][A] |
+arkanoid/score_1[3]_2_s0/CLK |
40.767 |
@@ -4278,8 +4854,8 @@ Path9
tSu |
|
1 |
-R43C41[0][B] |
-arkanoid/qxb_2_s0 |
+R42C44[2][A] |
+arkanoid/score_1[3]_2_s0 |
Path Statistics:
@@ -4294,7 +4870,7 @@ Path9
Logic Level |
-8 |
+12 |
Arrival Clock Path Delay |
@@ -4302,7 +4878,7 @@ Path9
Arrival Data Path Delay |
-cell: 3.077, 48.048%; route: 3.127, 48.829%; tC2Q: 0.200, 3.122% |
+cell: 4.863, 63.956%; route: 2.541, 33.415%; tC2Q: 0.200, 2.630% |
Required Clock Path Delay |
@@ -4314,11 +4890,11 @@ Path10
Slack |
-33.565 |
+32.416 |
Data Arrival Time |
-7.201 |
+8.351 |
Data Required Time |
@@ -4326,11 +4902,11 @@ Path10
From |
-arkanoid/qxb_5_s2 |
+arkanoid/qxb_1_s0 |
To |
-arkanoid/qxb_6_s0 |
+arkanoid/qxb_3_s2 |
Launch Clk |
@@ -4384,7 +4960,7 @@ Path10
0.587 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -4394,152 +4970,206 @@ Path10
tNET |
RR |
1 |
-R43C40[0][B] |
-arkanoid/qxb_5_s2/CLK |
+R44C36[2][B] |
+arkanoid/qxb_1_s0/CLK |
0.997 |
0.200 |
tC2Q |
RF |
-22 |
-R43C40[0][B] |
-arkanoid/qxb_5_s2/Q |
+19 |
+R44C36[2][B] |
+arkanoid/qxb_1_s0/Q |
-1.393 |
-0.396 |
+1.591 |
+0.594 |
tNET |
FF |
1 |
-R42C39[0][B] |
-arkanoid/n155_s4/I1 |
+R43C33[3][B] |
+arkanoid/n3744_s53/I2 |
-1.839 |
-0.446 |
+2.069 |
+0.478 |
tINS |
FF |
-8 |
-R42C39[0][B] |
-arkanoid/n155_s4/F |
+2 |
+R43C33[3][B] |
+arkanoid/n3744_s53/F |
-2.219 |
-0.380 |
+2.286 |
+0.217 |
tNET |
FF |
1 |
-R41C40[2][A] |
-arkanoid/n9052_s3/I2 |
+R44C33[3][B] |
+arkanoid/n3744_s51/I1 |
-2.609 |
-0.390 |
+2.777 |
+0.491 |
tINS |
-FF |
-7 |
-R41C40[2][A] |
-arkanoid/n9052_s3/F |
+FR |
+1 |
+R44C33[3][B] |
+arkanoid/n3744_s51/F |
-2.964 |
-0.355 |
+2.926 |
+0.149 |
tNET |
-FF |
+RR |
1 |
-R41C39[0][A] |
-arkanoid/n3294_s37/I0 |
+R44C32[1][B] |
+arkanoid/n3744_s48/I2 |
-3.442 |
-0.478 |
+3.324 |
+0.398 |
tINS |
-FF |
+RR |
1 |
-R41C39[0][A] |
-arkanoid/n3294_s37/F |
+R44C32[1][B] |
+arkanoid/n3744_s48/F |
-4.007 |
-0.565 |
+3.325 |
+0.001 |
tNET |
-FF |
+RR |
1 |
-R44C39[0][A] |
-arkanoid/n3294_s20/I3 |
+R44C32[2][A] |
+arkanoid/n3744_s42/I2 |
-4.499 |
+3.817 |
0.491 |
tINS |
-FR |
+RR |
1 |
-R44C39[0][A] |
-arkanoid/n3294_s20/F |
+R44C32[2][A] |
+arkanoid/n3744_s42/F |
-4.500 |
-0.001 |
+3.965 |
+0.149 |
tNET |
RR |
1 |
-R44C39[3][A] |
-arkanoid/n3294_s9/I2 |
+R43C32[1][A] |
+arkanoid/n3744_s30/I2 |
-4.820 |
-0.320 |
+4.411 |
+0.446 |
tINS |
RF |
1 |
-R44C39[3][A] |
-arkanoid/n3294_s9/F |
+R43C32[1][A] |
+arkanoid/n3744_s30/F |
-5.176 |
-0.356 |
+4.896 |
+0.485 |
tNET |
FF |
1 |
-R43C38[1][B] |
-arkanoid/n3294_s4/I2 |
+R44C32[3][B] |
+arkanoid/n3744_s19/I2 |
-5.654 |
-0.478 |
+5.370 |
+0.473 |
tINS |
-FF |
-4 |
-R43C38[1][B] |
-arkanoid/n3294_s4/F |
+FR |
+1 |
+R44C32[3][B] |
+arkanoid/n3744_s19/F |
-6.256 |
-0.602 |
+5.518 |
+0.149 |
+tNET |
+RR |
+1 |
+R43C32[3][B] |
+arkanoid/n3744_s9/I2 |
+
+
+5.838 |
+0.320 |
+tINS |
+RF |
+2 |
+R43C32[3][B] |
+arkanoid/n3744_s9/F |
+
+
+6.290 |
+0.451 |
tNET |
FF |
1 |
-R39C41[2][A] |
-arkanoid/qxb_9_s2/I0 |
+R39C33[2][A] |
+arkanoid/qyb_9_s3/I2 |
-6.730 |
+6.763 |
0.473 |
tINS |
FR |
+2 |
+R39C33[2][A] |
+arkanoid/qyb_9_s3/F |
+
+
+6.914 |
+0.151 |
+tNET |
+RR |
+1 |
+R39C34[3][A] |
+arkanoid/qyb_9_s2/I1 |
+
+
+7.305 |
+0.390 |
+tINS |
+RF |
+11 |
+R39C34[3][A] |
+arkanoid/qyb_9_s2/F |
+
+
+7.324 |
+0.019 |
+tNET |
+FF |
+1 |
+R39C34[2][B] |
+arkanoid/qxb_9_s2/I2 |
+
+
+7.722 |
+0.398 |
+tINS |
+FR |
10 |
-R39C41[2][A] |
+R39C34[2][B] |
arkanoid/qxb_9_s2/F |
-7.201 |
-0.472 |
+8.351 |
+0.629 |
tNET |
RR |
1 |
-R43C41[1][B] |
-arkanoid/qxb_6_s0/CE |
+R44C36[0][A] |
+arkanoid/qxb_3_s2/CE |
Data Required Path:
@@ -4585,7 +5215,7 @@ Path10
0.587 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -4595,8 +5225,8 @@ Path10
tNET |
RR |
1 |
-R43C41[1][B] |
-arkanoid/qxb_6_s0/CLK |
+R44C36[0][A] |
+arkanoid/qxb_3_s2/CLK |
40.767 |
@@ -4604,8 +5234,8 @@ Path10
tSu |
|
1 |
-R43C41[1][B] |
-arkanoid/qxb_6_s0 |
+R44C36[0][A] |
+arkanoid/qxb_3_s2 |
Path Statistics:
@@ -4620,7 +5250,7 @@ Path10
Logic Level |
-8 |
+11 |
Arrival Clock Path Delay |
@@ -4628,7 +5258,7 @@ Path10
Arrival Data Path Delay |
-cell: 3.077, 48.048%; route: 3.127, 48.829%; tC2Q: 0.200, 3.122% |
+cell: 4.360, 57.716%; route: 2.994, 39.636%; tC2Q: 0.200, 2.647% |
Required Clock Path Delay |
@@ -4640,11 +5270,11 @@ Path11
Slack |
-33.568 |
+32.416 |
Data Arrival Time |
-7.198 |
+8.351 |
Data Required Time |
@@ -4652,11 +5282,11 @@ Path11
From |
-arkanoid/qxb_5_s2 |
+arkanoid/qxb_1_s0 |
To |
-arkanoid/qxb_8_s2 |
+arkanoid/qxb_1_s0 |
Launch Clk |
@@ -4710,7 +5340,7 @@ Path11
0.587 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -4720,152 +5350,206 @@ Path11
tNET |
RR |
1 |
-R43C40[0][B] |
-arkanoid/qxb_5_s2/CLK |
+R44C36[2][B] |
+arkanoid/qxb_1_s0/CLK |
0.997 |
0.200 |
tC2Q |
RF |
-22 |
-R43C40[0][B] |
-arkanoid/qxb_5_s2/Q |
+19 |
+R44C36[2][B] |
+arkanoid/qxb_1_s0/Q |
-1.393 |
-0.396 |
+1.591 |
+0.594 |
tNET |
FF |
1 |
-R42C39[0][B] |
-arkanoid/n155_s4/I1 |
+R43C33[3][B] |
+arkanoid/n3744_s53/I2 |
-1.839 |
-0.446 |
+2.069 |
+0.478 |
tINS |
FF |
-8 |
-R42C39[0][B] |
-arkanoid/n155_s4/F |
+2 |
+R43C33[3][B] |
+arkanoid/n3744_s53/F |
-2.219 |
-0.380 |
+2.286 |
+0.217 |
tNET |
FF |
1 |
-R41C40[2][A] |
-arkanoid/n9052_s3/I2 |
+R44C33[3][B] |
+arkanoid/n3744_s51/I1 |
-2.609 |
-0.390 |
+2.777 |
+0.491 |
tINS |
-FF |
-7 |
-R41C40[2][A] |
-arkanoid/n9052_s3/F |
+FR |
+1 |
+R44C33[3][B] |
+arkanoid/n3744_s51/F |
-2.964 |
-0.355 |
+2.926 |
+0.149 |
tNET |
-FF |
+RR |
1 |
-R41C39[0][A] |
-arkanoid/n3294_s37/I0 |
+R44C32[1][B] |
+arkanoid/n3744_s48/I2 |
-3.442 |
-0.478 |
+3.324 |
+0.398 |
tINS |
-FF |
+RR |
1 |
-R41C39[0][A] |
-arkanoid/n3294_s37/F |
+R44C32[1][B] |
+arkanoid/n3744_s48/F |
-4.007 |
-0.565 |
+3.325 |
+0.001 |
tNET |
-FF |
+RR |
1 |
-R44C39[0][A] |
-arkanoid/n3294_s20/I3 |
+R44C32[2][A] |
+arkanoid/n3744_s42/I2 |
-4.499 |
+3.817 |
0.491 |
tINS |
-FR |
+RR |
1 |
-R44C39[0][A] |
-arkanoid/n3294_s20/F |
+R44C32[2][A] |
+arkanoid/n3744_s42/F |
-4.500 |
-0.001 |
+3.965 |
+0.149 |
tNET |
RR |
1 |
-R44C39[3][A] |
-arkanoid/n3294_s9/I2 |
+R43C32[1][A] |
+arkanoid/n3744_s30/I2 |
-4.820 |
-0.320 |
+4.411 |
+0.446 |
tINS |
RF |
1 |
-R44C39[3][A] |
-arkanoid/n3294_s9/F |
+R43C32[1][A] |
+arkanoid/n3744_s30/F |
-5.176 |
-0.356 |
+4.896 |
+0.485 |
tNET |
FF |
1 |
-R43C38[1][B] |
-arkanoid/n3294_s4/I2 |
+R44C32[3][B] |
+arkanoid/n3744_s19/I2 |
-5.654 |
-0.478 |
+5.370 |
+0.473 |
tINS |
-FF |
-4 |
-R43C38[1][B] |
-arkanoid/n3294_s4/F |
+FR |
+1 |
+R44C32[3][B] |
+arkanoid/n3744_s19/F |
-6.256 |
-0.602 |
+5.518 |
+0.149 |
tNET |
-FF |
+RR |
1 |
-R39C41[2][A] |
-arkanoid/qxb_9_s2/I0 |
+R43C32[3][B] |
+arkanoid/n3744_s9/I2 |
-6.730 |
-0.473 |
+5.838 |
+0.320 |
+tINS |
+RF |
+2 |
+R43C32[3][B] |
+arkanoid/n3744_s9/F |
+
+
+6.290 |
+0.451 |
+tNET |
+FF |
+1 |
+R39C33[2][A] |
+arkanoid/qyb_9_s3/I2 |
+
+
+6.763 |
+0.473 |
+tINS |
+FR |
+2 |
+R39C33[2][A] |
+arkanoid/qyb_9_s3/F |
+
+
+6.914 |
+0.151 |
+tNET |
+RR |
+1 |
+R39C34[3][A] |
+arkanoid/qyb_9_s2/I1 |
+
+
+7.305 |
+0.390 |
+tINS |
+RF |
+11 |
+R39C34[3][A] |
+arkanoid/qyb_9_s2/F |
+
+
+7.324 |
+0.019 |
+tNET |
+FF |
+1 |
+R39C34[2][B] |
+arkanoid/qxb_9_s2/I2 |
+
+
+7.722 |
+0.398 |
tINS |
FR |
10 |
-R39C41[2][A] |
+R39C34[2][B] |
arkanoid/qxb_9_s2/F |
-7.198 |
-0.468 |
+8.351 |
+0.629 |
tNET |
RR |
1 |
-R44C41[1][A] |
-arkanoid/qxb_8_s2/CE |
+R44C36[2][B] |
+arkanoid/qxb_1_s0/CE |
Data Required Path:
@@ -4911,7 +5595,7 @@ Path11
0.587 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -4921,8 +5605,8 @@ Path11
tNET |
RR |
1 |
-R44C41[1][A] |
-arkanoid/qxb_8_s2/CLK |
+R44C36[2][B] |
+arkanoid/qxb_1_s0/CLK |
40.767 |
@@ -4930,8 +5614,8 @@ Path11
tSu |
|
1 |
-R44C41[1][A] |
-arkanoid/qxb_8_s2 |
+R44C36[2][B] |
+arkanoid/qxb_1_s0 |
Path Statistics:
@@ -4946,7 +5630,7 @@ Path11
Logic Level |
-8 |
+11 |
Arrival Clock Path Delay |
@@ -4954,7 +5638,7 @@ Path11
Arrival Data Path Delay |
-cell: 3.077, 48.072%; route: 3.124, 48.804%; tC2Q: 0.200, 3.124% |
+cell: 4.360, 57.716%; route: 2.994, 39.636%; tC2Q: 0.200, 2.647% |
Required Clock Path Delay |
@@ -4966,11 +5650,11 @@ Path12
Slack |
-33.568 |
+32.423 |
Data Arrival Time |
-7.198 |
+8.343 |
Data Required Time |
@@ -4978,11 +5662,11 @@ Path12
From |
-arkanoid/qxb_5_s2 |
+arkanoid/qxb_1_s0 |
To |
-arkanoid/qxb_3_s2 |
+arkanoid/score_counter_4_s0 |
Launch Clk |
@@ -5036,7 +5720,7 @@ Path12
0.587 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -5046,152 +5730,206 @@ Path12
tNET |
RR |
1 |
-R43C40[0][B] |
-arkanoid/qxb_5_s2/CLK |
+R44C36[2][B] |
+arkanoid/qxb_1_s0/CLK |
0.997 |
0.200 |
tC2Q |
RF |
-22 |
-R43C40[0][B] |
-arkanoid/qxb_5_s2/Q |
+19 |
+R44C36[2][B] |
+arkanoid/qxb_1_s0/Q |
-1.393 |
-0.396 |
+1.644 |
+0.647 |
tNET |
FF |
1 |
-R42C39[0][B] |
-arkanoid/n155_s4/I1 |
+R41C34[3][B] |
+arkanoid/n10669_s6/I1 |
-1.839 |
-0.446 |
+2.123 |
+0.478 |
tINS |
FF |
-8 |
-R42C39[0][B] |
-arkanoid/n155_s4/F |
+9 |
+R41C34[3][B] |
+arkanoid/n10669_s6/F |
-2.219 |
-0.380 |
+2.505 |
+0.383 |
tNET |
FF |
1 |
-R41C40[2][A] |
-arkanoid/n9052_s3/I2 |
+R42C35[0][B] |
+arkanoid/n10669_s3/I0 |
-2.609 |
+2.896 |
0.390 |
tINS |
FF |
-7 |
-R41C40[2][A] |
-arkanoid/n9052_s3/F |
+2 |
+R42C35[0][B] |
+arkanoid/n10669_s3/F |
-2.964 |
-0.355 |
+3.242 |
+0.346 |
tNET |
FF |
1 |
-R41C39[0][A] |
-arkanoid/n3294_s37/I0 |
+R41C35[1][B] |
+arkanoid/n10669_s1/I1 |
-3.442 |
-0.478 |
+3.561 |
+0.320 |
tINS |
FF |
+7 |
+R41C35[1][B] |
+arkanoid/n10669_s1/F |
+
+
+4.148 |
+0.587 |
+tNET |
+FF |
1 |
-R41C39[0][A] |
-arkanoid/n3294_s37/F |
+R42C39[1][B] |
+arkanoid/n3741_s16/I2 |
-4.007 |
-0.565 |
+4.594 |
+0.446 |
+tINS |
+FF |
+5 |
+R42C39[1][B] |
+arkanoid/n3741_s16/F |
+
+
+4.815 |
+0.221 |
tNET |
FF |
1 |
-R44C39[0][A] |
-arkanoid/n3294_s20/I3 |
+R44C39[2][B] |
+arkanoid/n3741_s10/I3 |
-4.499 |
-0.491 |
+5.288 |
+0.473 |
tINS |
FR |
1 |
-R44C39[0][A] |
-arkanoid/n3294_s20/F |
+R44C39[2][B] |
+arkanoid/n3741_s10/F |
-4.500 |
-0.001 |
+5.437 |
+0.149 |
tNET |
RR |
1 |
-R44C39[3][A] |
-arkanoid/n3294_s9/I2 |
+R43C39[3][B] |
+arkanoid/n3741_s3/I3 |
-4.820 |
+5.756 |
0.320 |
tINS |
RF |
+5 |
+R43C39[3][B] |
+arkanoid/n3741_s3/F |
+
+
+6.111 |
+0.355 |
+tNET |
+FF |
+1 |
+R41C39[3][A] |
+arkanoid/n3739_s7/I2 |
+
+
+6.431 |
+0.320 |
+tINS |
+FF |
+2 |
+R41C39[3][A] |
+arkanoid/n3739_s7/F |
+
+
+6.438 |
+0.008 |
+tNET |
+FF |
1 |
-R44C39[3][A] |
-arkanoid/n3294_s9/F |
+R41C39[0][B] |
+arkanoid/n3735_s37/I3 |
+
+
+6.829 |
+0.390 |
+tINS |
+FF |
+3 |
+R41C39[0][B] |
+arkanoid/n3735_s37/F |
-5.176 |
-0.356 |
+7.046 |
+0.217 |
tNET |
FF |
1 |
-R43C38[1][B] |
-arkanoid/n3294_s4/I2 |
+R41C41[0][A] |
+arkanoid/n3737_s22/I1 |
-5.654 |
+7.524 |
0.478 |
tINS |
FF |
-4 |
-R43C38[1][B] |
-arkanoid/n3294_s4/F |
+2 |
+R41C41[0][A] |
+arkanoid/n3737_s22/F |
-6.256 |
-0.602 |
+7.870 |
+0.346 |
tNET |
FF |
1 |
-R39C41[2][A] |
-arkanoid/qxb_9_s2/I0 |
+R41C43[1][A] |
+arkanoid/n3738_s0/I2 |
-6.730 |
+8.343 |
0.473 |
tINS |
FR |
-10 |
-R39C41[2][A] |
-arkanoid/qxb_9_s2/F |
+1 |
+R41C43[1][A] |
+arkanoid/n3738_s0/F |
-7.198 |
-0.468 |
+8.343 |
+0.000 |
tNET |
RR |
1 |
-R44C41[1][B] |
-arkanoid/qxb_3_s2/CE |
+R41C43[1][A] |
+arkanoid/score_counter_4_s0/D |
Data Required Path:
@@ -5237,7 +5975,7 @@ Path12
0.587 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -5247,8 +5985,8 @@ Path12
tNET |
RR |
1 |
-R44C41[1][B] |
-arkanoid/qxb_3_s2/CLK |
+R41C43[1][A] |
+arkanoid/score_counter_4_s0/CLK |
40.767 |
@@ -5256,8 +5994,8 @@ Path12
tSu |
|
1 |
-R44C41[1][B] |
-arkanoid/qxb_3_s2 |
+R41C43[1][A] |
+arkanoid/score_counter_4_s0 |
Path Statistics:
@@ -5272,7 +6010,7 @@ Path12
Logic Level |
-8 |
+11 |
Arrival Clock Path Delay |
@@ -5280,7 +6018,7 @@ Path12
Arrival Data Path Delay |
-cell: 3.077, 48.072%; route: 3.124, 48.804%; tC2Q: 0.200, 3.124% |
+cell: 4.089, 54.187%; route: 3.257, 43.163%; tC2Q: 0.200, 2.650% |
Required Clock Path Delay |
@@ -5292,11 +6030,11 @@ Path13
Slack |
-33.568 |
+32.482 |
Data Arrival Time |
-7.198 |
+8.285 |
Data Required Time |
@@ -5304,11 +6042,11 @@ Path13
From |
-arkanoid/qxb_5_s2 |
+arkanoid/qyb_3_s0 |
To |
-arkanoid/qxb_7_s0 |
+arkanoid/score_counter_7_s0 |
Launch Clk |
@@ -5362,7 +6100,7 @@ Path13
0.587 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -5372,152 +6110,188 @@ Path13
tNET |
RR |
1 |
-R43C40[0][B] |
-arkanoid/qxb_5_s2/CLK |
+R36C34[0][A] |
+arkanoid/qyb_3_s0/CLK |
0.997 |
0.200 |
tC2Q |
RF |
-22 |
-R43C40[0][B] |
-arkanoid/qxb_5_s2/Q |
+12 |
+R36C34[0][A] |
+arkanoid/qyb_3_s0/Q |
-1.393 |
-0.396 |
+1.615 |
+0.618 |
tNET |
FF |
1 |
-R42C39[0][B] |
-arkanoid/n155_s4/I1 |
+R39C38[1][B] |
+arkanoid/n10667_s4/I0 |
-1.839 |
+2.061 |
0.446 |
tINS |
FF |
-8 |
-R42C39[0][B] |
-arkanoid/n155_s4/F |
+4 |
+R39C38[1][B] |
+arkanoid/n10667_s4/F |
-2.219 |
-0.380 |
+2.421 |
+0.360 |
tNET |
FF |
1 |
-R41C40[2][A] |
-arkanoid/n9052_s3/I2 |
+R40C39[1][B] |
+arkanoid/n10667_s1/I1 |
-2.609 |
-0.390 |
+2.899 |
+0.478 |
tINS |
FF |
-7 |
-R41C40[2][A] |
-arkanoid/n9052_s3/F |
+8 |
+R40C39[1][B] |
+arkanoid/n10667_s1/F |
-2.964 |
-0.355 |
+3.490 |
+0.591 |
tNET |
FF |
1 |
-R41C39[0][A] |
-arkanoid/n3294_s37/I0 |
+R41C43[2][B] |
+arkanoid/n3739_s10/I1 |
-3.442 |
-0.478 |
+3.880 |
+0.390 |
tINS |
FF |
-1 |
-R41C39[0][A] |
-arkanoid/n3294_s37/F |
+10 |
+R41C43[2][B] |
+arkanoid/n3739_s10/F |
-4.007 |
-0.565 |
+4.851 |
+0.971 |
tNET |
FF |
1 |
-R44C39[0][A] |
-arkanoid/n3294_s20/I3 |
+R40C44[0][B] |
+arkanoid/n3737_s15/I3 |
-4.499 |
+5.343 |
0.491 |
tINS |
FR |
-1 |
-R44C39[0][A] |
-arkanoid/n3294_s20/F |
+2 |
+R40C44[0][B] |
+arkanoid/n3737_s15/F |
-4.500 |
-0.001 |
+5.492 |
+0.150 |
tNET |
RR |
1 |
-R44C39[3][A] |
-arkanoid/n3294_s9/I2 |
+R40C43[2][A] |
+arkanoid/n3737_s20/I3 |
-4.820 |
-0.320 |
+5.971 |
+0.478 |
tINS |
RF |
-1 |
-R44C39[3][A] |
-arkanoid/n3294_s9/F |
+3 |
+R40C43[2][A] |
+arkanoid/n3737_s20/F |
-5.176 |
-0.356 |
+6.335 |
+0.364 |
tNET |
FF |
1 |
-R43C38[1][B] |
-arkanoid/n3294_s4/I2 |
+R41C44[3][B] |
+arkanoid/n3737_s3/I3 |
-5.654 |
-0.478 |
+6.654 |
+0.320 |
tINS |
FF |
-4 |
-R43C38[1][B] |
-arkanoid/n3294_s4/F |
+3 |
+R41C44[3][B] |
+arkanoid/n3737_s3/F |
-6.256 |
-0.602 |
+6.872 |
+0.218 |
tNET |
FF |
1 |
-R39C41[2][A] |
-arkanoid/qxb_9_s2/I0 |
+R41C42[1][A] |
+arkanoid/n3735_s14/I1 |
-6.730 |
+7.346 |
0.473 |
tINS |
FR |
-10 |
-R39C41[2][A] |
-arkanoid/qxb_9_s2/F |
+1 |
+R41C42[1][A] |
+arkanoid/n3735_s14/F |
-7.198 |
-0.468 |
+7.494 |
+0.149 |
tNET |
RR |
1 |
-R44C41[0][B] |
-arkanoid/qxb_7_s0/CE |
+R40C42[2][B] |
+arkanoid/n3735_s4/I2 |
+
+
+7.814 |
+0.320 |
+tINS |
+RF |
+2 |
+R40C42[2][B] |
+arkanoid/n3735_s4/F |
+
+
+7.965 |
+0.151 |
+tNET |
+FF |
+1 |
+R40C41[0][B] |
+arkanoid/n3735_s0/I3 |
+
+
+8.285 |
+0.320 |
+tINS |
+FF |
+1 |
+R40C41[0][B] |
+arkanoid/n3735_s0/F |
+
+
+8.285 |
+0.000 |
+tNET |
+FF |
+1 |
+R40C41[0][B] |
+arkanoid/score_counter_7_s0/D |
Data Required Path:
@@ -5563,7 +6337,7 @@ Path13
0.587 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -5573,8 +6347,8 @@ Path13
tNET |
RR |
1 |
-R44C41[0][B] |
-arkanoid/qxb_7_s0/CLK |
+R40C41[0][B] |
+arkanoid/score_counter_7_s0/CLK |
40.767 |
@@ -5582,8 +6356,8 @@ Path13
tSu |
|
1 |
-R44C41[0][B] |
-arkanoid/qxb_7_s0 |
+R40C41[0][B] |
+arkanoid/score_counter_7_s0 |
Path Statistics:
@@ -5598,7 +6372,7 @@ Path13
Logic Level |
-8 |
+10 |
Arrival Clock Path Delay |
@@ -5606,7 +6380,7 @@ Path13
Arrival Data Path Delay |
-cell: 3.077, 48.072%; route: 3.124, 48.804%; tC2Q: 0.200, 3.124% |
+cell: 3.717, 49.640%; route: 3.571, 47.689%; tC2Q: 0.200, 2.671% |
Required Clock Path Delay |
@@ -5618,11 +6392,11 @@ Path14
Slack |
-33.568 |
+32.549 |
Data Arrival Time |
-7.198 |
+8.217 |
Data Required Time |
@@ -5630,11 +6404,11 @@ Path14
From |
-arkanoid/qxb_5_s2 |
+arkanoid/score_counter_4_s0 |
To |
-arkanoid/qxb_9_s0 |
+arkanoid/score_1[2]_6_s0 |
Launch Clk |
@@ -5688,7 +6462,7 @@ Path14
0.587 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -5698,152 +6472,224 @@ Path14
tNET |
RR |
1 |
-R43C40[0][B] |
-arkanoid/qxb_5_s2/CLK |
+R41C43[1][A] |
+arkanoid/score_counter_4_s0/CLK |
0.997 |
0.200 |
tC2Q |
RF |
-22 |
-R43C40[0][B] |
-arkanoid/qxb_5_s2/Q |
+19 |
+R41C43[1][A] |
+arkanoid/score_counter_4_s0/Q |
-1.393 |
-0.396 |
+1.370 |
+0.374 |
tNET |
FF |
1 |
-R42C39[0][B] |
-arkanoid/n155_s4/I1 |
+R42C41[3][B] |
+arkanoid/n7053_s12/I0 |
-1.839 |
-0.446 |
+1.849 |
+0.478 |
tINS |
FF |
-8 |
-R42C39[0][B] |
-arkanoid/n155_s4/F |
+16 |
+R42C41[3][B] |
+arkanoid/n7053_s12/F |
-2.219 |
-0.380 |
+1.871 |
+0.023 |
tNET |
FF |
1 |
-R41C40[2][A] |
-arkanoid/n9052_s3/I2 |
+R42C41[2][B] |
+arkanoid/n7054_s15/I2 |
+
+
+2.345 |
+0.473 |
+tINS |
+FR |
+1 |
+R42C41[2][B] |
+arkanoid/n7054_s15/F |
+
+
+2.469 |
+0.124 |
+tNET |
+RR |
+1 |
+R42C41[3][A] |
+arkanoid/n7054_s13/I3 |
+
+
+2.960 |
+0.491 |
+tINS |
+RR |
+1 |
+R42C41[3][A] |
+arkanoid/n7054_s13/F |
+
+
+2.961 |
+0.001 |
+tNET |
+RR |
+1 |
+R42C41[2][A] |
+arkanoid/n7054_s12/I0 |
-2.609 |
+3.352 |
0.390 |
tINS |
+RF |
+11 |
+R42C41[2][A] |
+arkanoid/n7054_s12/F |
+
+
+3.709 |
+0.357 |
+tNET |
FF |
-7 |
-R41C40[2][A] |
-arkanoid/n9052_s3/F |
+1 |
+R42C42[2][A] |
+arkanoid/n7055_s21/I1 |
-2.964 |
-0.355 |
+4.155 |
+0.446 |
+tINS |
+FF |
+3 |
+R42C42[2][A] |
+arkanoid/n7055_s21/F |
+
+
+4.720 |
+0.565 |
tNET |
FF |
1 |
-R41C39[0][A] |
-arkanoid/n3294_s37/I0 |
+R44C44[2][A] |
+arkanoid/n7055_s19/I2 |
-3.442 |
+5.198 |
0.478 |
tINS |
FF |
-1 |
-R41C39[0][A] |
-arkanoid/n3294_s37/F |
+16 |
+R44C44[2][A] |
+arkanoid/n7055_s19/F |
-4.007 |
-0.565 |
+5.225 |
+0.026 |
tNET |
FF |
1 |
-R44C39[0][A] |
-arkanoid/n3294_s20/I3 |
+R44C44[3][A] |
+arkanoid/n7056_s22/I2 |
-4.499 |
-0.491 |
+5.623 |
+0.398 |
tINS |
FR |
1 |
-R44C39[0][A] |
-arkanoid/n3294_s20/F |
+R44C44[3][A] |
+arkanoid/n7056_s22/F |
-4.500 |
+5.624 |
0.001 |
tNET |
RR |
1 |
-R44C39[3][A] |
-arkanoid/n3294_s9/I2 |
+R44C44[3][B] |
+arkanoid/n7056_s21/I2 |
-4.820 |
-0.320 |
+6.022 |
+0.398 |
tINS |
-RF |
+RR |
1 |
-R44C39[3][A] |
-arkanoid/n3294_s9/F |
+R44C44[3][B] |
+arkanoid/n7056_s21/F |
-5.176 |
-0.356 |
+6.023 |
+0.001 |
tNET |
-FF |
+RR |
1 |
-R43C38[1][B] |
-arkanoid/n3294_s4/I2 |
+R44C44[2][B] |
+arkanoid/n7056_s20/I3 |
-5.654 |
-0.478 |
+6.469 |
+0.446 |
tINS |
-FF |
-4 |
-R43C38[1][B] |
-arkanoid/n3294_s4/F |
+RF |
+25 |
+R44C44[2][B] |
+arkanoid/n7056_s20/F |
-6.256 |
-0.602 |
+7.104 |
+0.635 |
tNET |
FF |
1 |
-R39C41[2][A] |
-arkanoid/qxb_9_s2/I0 |
+R43C41[3][B] |
+arkanoid/n7131_s1/I0 |
-6.730 |
-0.473 |
+7.595 |
+0.491 |
tINS |
FR |
-10 |
-R39C41[2][A] |
-arkanoid/qxb_9_s2/F |
+1 |
+R43C41[3][B] |
+arkanoid/n7131_s1/F |
+
+
+7.744 |
+0.149 |
+tNET |
+RR |
+1 |
+R44C41[0][B] |
+arkanoid/n7131_s0/I0 |
+
+
+8.217 |
+0.473 |
+tINS |
+RR |
+1 |
+R44C41[0][B] |
+arkanoid/n7131_s0/F |
-7.198 |
-0.468 |
+8.217 |
+0.000 |
tNET |
RR |
1 |
-R44C41[0][A] |
-arkanoid/qxb_9_s0/CE |
+R44C41[0][B] |
+arkanoid/score_1[2]_6_s0/D |
Data Required Path:
@@ -5889,7 +6735,7 @@ Path14
0.587 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -5899,8 +6745,8 @@ Path14
tNET |
RR |
1 |
-R44C41[0][A] |
-arkanoid/qxb_9_s0/CLK |
+R44C41[0][B] |
+arkanoid/score_1[2]_6_s0/CLK |
40.767 |
@@ -5908,8 +6754,8 @@ Path14
tSu |
|
1 |
-R44C41[0][A] |
-arkanoid/qxb_9_s0 |
+R44C41[0][B] |
+arkanoid/score_1[2]_6_s0 |
Path Statistics:
@@ -5924,7 +6770,7 @@ Path14
Logic Level |
-8 |
+12 |
Arrival Clock Path Delay |
@@ -5932,7 +6778,7 @@ Path14
Arrival Data Path Delay |
-cell: 3.077, 48.072%; route: 3.124, 48.804%; tC2Q: 0.200, 3.124% |
+cell: 4.964, 66.898%; route: 2.256, 30.407%; tC2Q: 0.200, 2.695% |
Required Clock Path Delay |
@@ -5944,11 +6790,11 @@ Path15
Slack |
-22.775 |
+23.315 |
Data Arrival Time |
-29.042 |
+28.503 |
Data Required Time |
@@ -6042,7 +6888,7 @@ Path15
tNET |
FF |
1 |
-R29C31[0][B] |
+R36C26[2][A] |
gw_gao_inst_0/u_icon_top/enable_reg_2_s0/CLK |
@@ -6051,52 +6897,52 @@ Path15
tC2Q |
FF |
3 |
-R29C31[0][B] |
+R36C26[2][A] |
gw_gao_inst_0/u_icon_top/enable_reg_2_s0/Q |
-27.697 |
-0.528 |
+27.320 |
+0.152 |
tNET |
FF |
1 |
-R38C30[2][A] |
-gw_gao_inst_0/u_icon_top/n33_s1/I2 |
+R36C25[3][A] |
+gw_gao_inst_0/u_icon_top/n33_s3/I1 |
-28.142 |
-0.446 |
+27.793 |
+0.473 |
tINS |
-FF |
+FR |
1 |
-R38C30[2][A] |
-gw_gao_inst_0/u_icon_top/n33_s1/F |
+R36C25[3][A] |
+gw_gao_inst_0/u_icon_top/n33_s3/F |
-28.355 |
-0.213 |
+27.794 |
+0.001 |
tNET |
-FF |
+RR |
1 |
-R38C29[3][A] |
-gw_gao_inst_0/u_icon_top/n33_s0/I0 |
+R36C25[3][B] |
+gw_gao_inst_0/u_icon_top/n33_s0/I2 |
-28.754 |
+28.193 |
0.398 |
tINS |
-FR |
+RR |
4 |
-R38C29[3][A] |
+R36C25[3][B] |
gw_gao_inst_0/u_icon_top/n33_s0/F |
-29.042 |
-0.289 |
+28.503 |
+0.310 |
tNET |
RR |
1 |
-R38C28[0][B] |
+R36C24[0][A] |
gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/CE |
@@ -6171,7 +7017,7 @@ Path15
tNET |
RR |
1 |
-R38C28[0][B] |
+R36C24[0][A] |
gw_gao_inst_0/u_icon_top/module_id_reg_0_s0/CLK |
@@ -6180,7 +7026,7 @@ Path15
tSu |
|
1 |
-R38C28[0][B] |
+R36C24[0][A] |
gw_gao_inst_0/u_icon_top/module_id_reg_0_s0 |
@@ -6204,7 +7050,7 @@ Path15
Arrival Data Path Delay |
-cell: 0.844, 40.690%; route: 1.030, 49.668%; tC2Q: 0.200, 9.642% |
+cell: 0.871, 56.796%; route: 0.463, 30.170%; tC2Q: 0.200, 13.033% |
Required Clock Path Delay |
@@ -6216,11 +7062,11 @@ Path16
Slack |
-22.775 |
+23.315 |
Data Arrival Time |
-29.042 |
+28.503 |
Data Required Time |
@@ -6314,7 +7160,7 @@ Path16
tNET |
FF |
1 |
-R29C31[0][B] |
+R36C26[2][A] |
gw_gao_inst_0/u_icon_top/enable_reg_2_s0/CLK |
@@ -6323,52 +7169,52 @@ Path16
tC2Q |
FF |
3 |
-R29C31[0][B] |
+R36C26[2][A] |
gw_gao_inst_0/u_icon_top/enable_reg_2_s0/Q |
-27.697 |
-0.528 |
+27.320 |
+0.152 |
tNET |
FF |
1 |
-R38C30[2][A] |
-gw_gao_inst_0/u_icon_top/n33_s1/I2 |
+R36C25[3][A] |
+gw_gao_inst_0/u_icon_top/n33_s3/I1 |
-28.142 |
-0.446 |
+27.793 |
+0.473 |
tINS |
-FF |
+FR |
1 |
-R38C30[2][A] |
-gw_gao_inst_0/u_icon_top/n33_s1/F |
+R36C25[3][A] |
+gw_gao_inst_0/u_icon_top/n33_s3/F |
-28.355 |
-0.213 |
+27.794 |
+0.001 |
tNET |
-FF |
+RR |
1 |
-R38C29[3][A] |
-gw_gao_inst_0/u_icon_top/n33_s0/I0 |
+R36C25[3][B] |
+gw_gao_inst_0/u_icon_top/n33_s0/I2 |
-28.754 |
+28.193 |
0.398 |
tINS |
-FR |
+RR |
4 |
-R38C29[3][A] |
+R36C25[3][B] |
gw_gao_inst_0/u_icon_top/n33_s0/F |
-29.042 |
-0.289 |
+28.503 |
+0.310 |
tNET |
RR |
1 |
-R38C28[0][A] |
+R36C24[1][B] |
gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/CE |
@@ -6443,7 +7289,7 @@ Path16
tNET |
RR |
1 |
-R38C28[0][A] |
+R36C24[1][B] |
gw_gao_inst_0/u_icon_top/module_id_reg_1_s0/CLK |
@@ -6452,7 +7298,7 @@ Path16
tSu |
|
1 |
-R38C28[0][A] |
+R36C24[1][B] |
gw_gao_inst_0/u_icon_top/module_id_reg_1_s0 |
@@ -6476,7 +7322,7 @@ Path16
Arrival Data Path Delay |
-cell: 0.844, 40.690%; route: 1.030, 49.668%; tC2Q: 0.200, 9.642% |
+cell: 0.871, 56.796%; route: 0.463, 30.170%; tC2Q: 0.200, 13.033% |
Required Clock Path Delay |
@@ -6488,11 +7334,11 @@ Path17
Slack |
-22.775 |
+23.315 |
Data Arrival Time |
-29.042 |
+28.503 |
Data Required Time |
@@ -6504,7 +7350,7 @@ Path17
To |
-gw_gao_inst_0/u_icon_top/module_id_reg_3_s0 |
+gw_gao_inst_0/u_icon_top/module_id_reg_2_s0 |
Launch Clk |
@@ -6586,7 +7432,7 @@ Path17
tNET |
FF |
1 |
-R29C31[0][B] |
+R36C26[2][A] |
gw_gao_inst_0/u_icon_top/enable_reg_2_s0/CLK |
@@ -6595,53 +7441,53 @@ Path17
tC2Q |
FF |
3 |
-R29C31[0][B] |
+R36C26[2][A] |
gw_gao_inst_0/u_icon_top/enable_reg_2_s0/Q |
-27.697 |
-0.528 |
+27.320 |
+0.152 |
tNET |
FF |
1 |
-R38C30[2][A] |
-gw_gao_inst_0/u_icon_top/n33_s1/I2 |
+R36C25[3][A] |
+gw_gao_inst_0/u_icon_top/n33_s3/I1 |
-28.142 |
-0.446 |
+27.793 |
+0.473 |
tINS |
-FF |
+FR |
1 |
-R38C30[2][A] |
-gw_gao_inst_0/u_icon_top/n33_s1/F |
+R36C25[3][A] |
+gw_gao_inst_0/u_icon_top/n33_s3/F |
-28.355 |
-0.213 |
+27.794 |
+0.001 |
tNET |
-FF |
+RR |
1 |
-R38C29[3][A] |
-gw_gao_inst_0/u_icon_top/n33_s0/I0 |
+R36C25[3][B] |
+gw_gao_inst_0/u_icon_top/n33_s0/I2 |
-28.754 |
+28.193 |
0.398 |
tINS |
-FR |
+RR |
4 |
-R38C29[3][A] |
+R36C25[3][B] |
gw_gao_inst_0/u_icon_top/n33_s0/F |
-29.042 |
-0.289 |
+28.503 |
+0.310 |
tNET |
RR |
1 |
-R38C28[1][A] |
-gw_gao_inst_0/u_icon_top/module_id_reg_3_s0/CE |
+R36C24[1][A] |
+gw_gao_inst_0/u_icon_top/module_id_reg_2_s0/CE |
Data Required Path:
@@ -6715,8 +7561,8 @@ Path17
tNET |
RR |
1 |
-R38C28[1][A] |
-gw_gao_inst_0/u_icon_top/module_id_reg_3_s0/CLK |
+R36C24[1][A] |
+gw_gao_inst_0/u_icon_top/module_id_reg_2_s0/CLK |
51.818 |
@@ -6724,8 +7570,8 @@ Path17
tSu |
|
1 |
-R38C28[1][A] |
-gw_gao_inst_0/u_icon_top/module_id_reg_3_s0 |
+R36C24[1][A] |
+gw_gao_inst_0/u_icon_top/module_id_reg_2_s0 |
Path Statistics:
@@ -6748,7 +7594,7 @@ Path17
Arrival Data Path Delay |
-cell: 0.844, 40.690%; route: 1.030, 49.668%; tC2Q: 0.200, 9.642% |
+cell: 0.871, 56.796%; route: 0.463, 30.170%; tC2Q: 0.200, 13.033% |
Required Clock Path Delay |
@@ -6760,11 +7606,11 @@ Path18
Slack |
-22.939 |
+23.315 |
Data Arrival Time |
-28.879 |
+28.503 |
Data Required Time |
@@ -6776,7 +7622,7 @@ Path18
To |
-gw_gao_inst_0/u_icon_top/module_id_reg_2_s0 |
+gw_gao_inst_0/u_icon_top/module_id_reg_3_s0 |
Launch Clk |
@@ -6858,7 +7704,7 @@ Path18
tNET |
FF |
1 |
-R29C31[0][B] |
+R36C26[2][A] |
gw_gao_inst_0/u_icon_top/enable_reg_2_s0/CLK |
@@ -6867,53 +7713,53 @@ Path18
tC2Q |
FF |
3 |
-R29C31[0][B] |
+R36C26[2][A] |
gw_gao_inst_0/u_icon_top/enable_reg_2_s0/Q |
-27.697 |
-0.528 |
+27.320 |
+0.152 |
tNET |
FF |
1 |
-R38C30[2][A] |
-gw_gao_inst_0/u_icon_top/n33_s1/I2 |
+R36C25[3][A] |
+gw_gao_inst_0/u_icon_top/n33_s3/I1 |
-28.142 |
-0.446 |
+27.793 |
+0.473 |
tINS |
-FF |
+FR |
1 |
-R38C30[2][A] |
-gw_gao_inst_0/u_icon_top/n33_s1/F |
+R36C25[3][A] |
+gw_gao_inst_0/u_icon_top/n33_s3/F |
-28.355 |
-0.213 |
+27.794 |
+0.001 |
tNET |
-FF |
+RR |
1 |
-R38C29[3][A] |
-gw_gao_inst_0/u_icon_top/n33_s0/I0 |
+R36C25[3][B] |
+gw_gao_inst_0/u_icon_top/n33_s0/I2 |
-28.754 |
+28.193 |
0.398 |
tINS |
-FR |
+RR |
4 |
-R38C29[3][A] |
+R36C25[3][B] |
gw_gao_inst_0/u_icon_top/n33_s0/F |
-28.879 |
-0.125 |
+28.503 |
+0.310 |
tNET |
RR |
1 |
-R38C29[1][B] |
-gw_gao_inst_0/u_icon_top/module_id_reg_2_s0/CE |
+R36C24[0][B] |
+gw_gao_inst_0/u_icon_top/module_id_reg_3_s0/CE |
Data Required Path:
@@ -6987,8 +7833,8 @@ Path18
tNET |
RR |
1 |
-R38C29[1][B] |
-gw_gao_inst_0/u_icon_top/module_id_reg_2_s0/CLK |
+R36C24[0][B] |
+gw_gao_inst_0/u_icon_top/module_id_reg_3_s0/CLK |
51.818 |
@@ -6996,8 +7842,8 @@ Path18
tSu |
|
1 |
-R38C29[1][B] |
-gw_gao_inst_0/u_icon_top/module_id_reg_2_s0 |
+R36C24[0][B] |
+gw_gao_inst_0/u_icon_top/module_id_reg_3_s0 |
Path Statistics:
@@ -7020,7 +7866,7 @@ Path18
Arrival Data Path Delay |
-cell: 0.844, 44.169%; route: 0.867, 45.364%; tC2Q: 0.200, 10.467% |
+cell: 0.871, 56.796%; route: 0.463, 30.170%; tC2Q: 0.200, 13.033% |
Required Clock Path Delay |
@@ -7032,11 +7878,11 @@ Path19
Slack |
-23.020 |
+23.388 |
Data Arrival Time |
-28.798 |
+28.429 |
Data Required Time |
@@ -7044,7 +7890,7 @@ Path19
From |
-gw_gao_inst_0/u_icon_top/enable_reg_2_s0 |
+gw_gao_inst_0/u_icon_top/enable_reg_1_s0 |
To |
@@ -7130,8 +7976,8 @@ Path19
tNET |
FF |
1 |
-R29C31[0][B] |
-gw_gao_inst_0/u_icon_top/enable_reg_2_s0/CLK |
+R36C25[2][B] |
+gw_gao_inst_0/u_icon_top/enable_reg_1_s0/CLK |
27.168 |
@@ -7139,34 +7985,34 @@ Path19
tC2Q |
FF |
3 |
-R29C31[0][B] |
-gw_gao_inst_0/u_icon_top/enable_reg_2_s0/Q |
+R36C25[2][B] |
+gw_gao_inst_0/u_icon_top/enable_reg_1_s0/Q |
-27.697 |
-0.528 |
+27.310 |
+0.142 |
tNET |
FF |
1 |
-R38C30[1][B] |
-gw_gao_inst_0/u_icon_top/n54_s1/I2 |
+R36C25[1][B] |
+gw_gao_inst_0/u_icon_top/n54_s0/I1 |
-28.170 |
-0.473 |
+27.801 |
+0.491 |
tINS |
FR |
5 |
-R38C30[1][B] |
-gw_gao_inst_0/u_icon_top/n54_s1/F |
+R36C25[1][B] |
+gw_gao_inst_0/u_icon_top/n54_s0/F |
-28.798 |
+28.429 |
0.628 |
tNET |
RR |
1 |
-R38C30[0][A] |
+R36C25[0][A] |
gw_gao_inst_0/u_icon_top/input_shift_reg_2_s0/CE |
@@ -7241,7 +8087,7 @@ Path19
tNET |
RR |
1 |
-R38C30[0][A] |
+R36C25[0][A] |
gw_gao_inst_0/u_icon_top/input_shift_reg_2_s0/CLK |
@@ -7250,7 +8096,7 @@ Path19
tSu |
|
1 |
-R38C30[0][A] |
+R36C25[0][A] |
gw_gao_inst_0/u_icon_top/input_shift_reg_2_s0 |
@@ -7274,7 +8120,7 @@ Path19
Arrival Data Path Delay |
-cell: 0.473, 25.868%; route: 1.156, 63.201%; tC2Q: 0.200, 10.931% |
+cell: 0.491, 33.633%; route: 0.770, 52.677%; tC2Q: 0.200, 13.689% |
Required Clock Path Delay |
@@ -7286,11 +8132,11 @@ Path20
Slack |
-23.020 |
+23.388 |
Data Arrival Time |
-28.798 |
+28.429 |
Data Required Time |
@@ -7298,7 +8144,7 @@ Path20
From |
-gw_gao_inst_0/u_icon_top/enable_reg_2_s0 |
+gw_gao_inst_0/u_icon_top/enable_reg_1_s0 |
To |
@@ -7384,8 +8230,8 @@ Path20
tNET |
FF |
1 |
-R29C31[0][B] |
-gw_gao_inst_0/u_icon_top/enable_reg_2_s0/CLK |
+R36C25[2][B] |
+gw_gao_inst_0/u_icon_top/enable_reg_1_s0/CLK |
27.168 |
@@ -7393,34 +8239,34 @@ Path20
tC2Q |
FF |
3 |
-R29C31[0][B] |
-gw_gao_inst_0/u_icon_top/enable_reg_2_s0/Q |
+R36C25[2][B] |
+gw_gao_inst_0/u_icon_top/enable_reg_1_s0/Q |
-27.697 |
-0.528 |
+27.310 |
+0.142 |
tNET |
FF |
1 |
-R38C30[1][B] |
-gw_gao_inst_0/u_icon_top/n54_s1/I2 |
+R36C25[1][B] |
+gw_gao_inst_0/u_icon_top/n54_s0/I1 |
-28.170 |
-0.473 |
+27.801 |
+0.491 |
tINS |
FR |
5 |
-R38C30[1][B] |
-gw_gao_inst_0/u_icon_top/n54_s1/F |
+R36C25[1][B] |
+gw_gao_inst_0/u_icon_top/n54_s0/F |
-28.798 |
+28.429 |
0.628 |
tNET |
RR |
1 |
-R38C30[0][B] |
+R36C25[0][B] |
gw_gao_inst_0/u_icon_top/input_shift_reg_3_s0/CE |
@@ -7495,7 +8341,7 @@ Path20
tNET |
RR |
1 |
-R38C30[0][B] |
+R36C25[0][B] |
gw_gao_inst_0/u_icon_top/input_shift_reg_3_s0/CLK |
@@ -7504,7 +8350,7 @@ Path20
tSu |
|
1 |
-R38C30[0][B] |
+R36C25[0][B] |
gw_gao_inst_0/u_icon_top/input_shift_reg_3_s0 |
@@ -7528,7 +8374,7 @@ Path20
Arrival Data Path Delay |
-cell: 0.473, 25.868%; route: 1.156, 63.201%; tC2Q: 0.200, 10.931% |
+cell: 0.491, 33.633%; route: 0.770, 52.677%; tC2Q: 0.200, 13.689% |
Required Clock Path Delay |
@@ -7540,11 +8386,11 @@ Path21
Slack |
-23.020 |
+23.388 |
Data Arrival Time |
-28.798 |
+28.429 |
Data Required Time |
@@ -7552,7 +8398,7 @@ Path21
From |
-gw_gao_inst_0/u_icon_top/enable_reg_2_s0 |
+gw_gao_inst_0/u_icon_top/enable_reg_1_s0 |
To |
@@ -7638,8 +8484,8 @@ Path21
tNET |
FF |
1 |
-R29C31[0][B] |
-gw_gao_inst_0/u_icon_top/enable_reg_2_s0/CLK |
+R36C25[2][B] |
+gw_gao_inst_0/u_icon_top/enable_reg_1_s0/CLK |
27.168 |
@@ -7647,34 +8493,34 @@ Path21
tC2Q |
FF |
3 |
-R29C31[0][B] |
-gw_gao_inst_0/u_icon_top/enable_reg_2_s0/Q |
+R36C25[2][B] |
+gw_gao_inst_0/u_icon_top/enable_reg_1_s0/Q |
-27.697 |
-0.528 |
+27.310 |
+0.142 |
tNET |
FF |
1 |
-R38C30[1][B] |
-gw_gao_inst_0/u_icon_top/n54_s1/I2 |
+R36C25[1][B] |
+gw_gao_inst_0/u_icon_top/n54_s0/I1 |
-28.170 |
-0.473 |
+27.801 |
+0.491 |
tINS |
FR |
5 |
-R38C30[1][B] |
-gw_gao_inst_0/u_icon_top/n54_s1/F |
+R36C25[1][B] |
+gw_gao_inst_0/u_icon_top/n54_s0/F |
-28.798 |
+28.429 |
0.628 |
tNET |
RR |
1 |
-R38C30[1][A] |
+R36C25[1][A] |
gw_gao_inst_0/u_icon_top/input_shift_reg_4_s0/CE |
@@ -7749,7 +8595,7 @@ Path21
tNET |
RR |
1 |
-R38C30[1][A] |
+R36C25[1][A] |
gw_gao_inst_0/u_icon_top/input_shift_reg_4_s0/CLK |
@@ -7758,7 +8604,7 @@ Path21
tSu |
|
1 |
-R38C30[1][A] |
+R36C25[1][A] |
gw_gao_inst_0/u_icon_top/input_shift_reg_4_s0 |
@@ -7782,7 +8628,7 @@ Path21
Arrival Data Path Delay |
-cell: 0.473, 25.868%; route: 1.156, 63.201%; tC2Q: 0.200, 10.931% |
+cell: 0.491, 33.633%; route: 0.770, 52.677%; tC2Q: 0.200, 13.689% |
Required Clock Path Delay |
@@ -7794,11 +8640,11 @@ Path22
Slack |
-23.364 |
+23.646 |
Data Arrival Time |
-28.454 |
+28.172 |
Data Required Time |
@@ -7806,11 +8652,11 @@ Path22
From |
-gw_gao_inst_0/u_icon_top/enable_reg_2_s0 |
+gw_gao_inst_0/u_icon_top/tdi_d_s0 |
To |
-gw_gao_inst_0/u_icon_top/input_shift_reg_0_s0 |
+gw_gao_inst_0/u_ao_top/data_register_45_s0 |
Launch Clk |
@@ -7892,44 +8738,26 @@ Path22
tNET |
FF |
1 |
-R29C31[0][B] |
-gw_gao_inst_0/u_icon_top/enable_reg_2_s0/CLK |
+R29C25[0][A] |
+gw_gao_inst_0/u_icon_top/tdi_d_s0/CLK |
27.168 |
0.200 |
tC2Q |
FF |
-3 |
-R29C31[0][B] |
-gw_gao_inst_0/u_icon_top/enable_reg_2_s0/Q |
+2 |
+R29C25[0][A] |
+gw_gao_inst_0/u_icon_top/tdi_d_s0/Q |
-27.697 |
-0.528 |
+28.172 |
+1.003 |
tNET |
FF |
1 |
-R38C30[1][B] |
-gw_gao_inst_0/u_icon_top/n54_s1/I2 |
-
-
-28.170 |
-0.473 |
-tINS |
-FR |
-5 |
-R38C30[1][B] |
-gw_gao_inst_0/u_icon_top/n54_s1/F |
-
-
-28.454 |
-0.284 |
-tNET |
-RR |
-1 |
-R38C29[2][A] |
-gw_gao_inst_0/u_icon_top/input_shift_reg_0_s0/CE |
+R41C24[1][B] |
+gw_gao_inst_0/u_ao_top/data_register_45_s0/D |
Data Required Path:
@@ -8003,8 +8831,8 @@ Path22
tNET |
RR |
1 |
-R38C29[2][A] |
-gw_gao_inst_0/u_icon_top/input_shift_reg_0_s0/CLK |
+R41C24[1][B] |
+gw_gao_inst_0/u_ao_top/data_register_45_s0/CLK |
51.818 |
@@ -8012,8 +8840,8 @@ Path22
tSu |
|
1 |
-R38C29[2][A] |
-gw_gao_inst_0/u_icon_top/input_shift_reg_0_s0 |
+R41C24[1][B] |
+gw_gao_inst_0/u_ao_top/data_register_45_s0 |
Path Statistics:
@@ -8028,7 +8856,7 @@ Path22
Logic Level |
-2 |
+1 |
Arrival Clock Path Delay |
@@ -8036,7 +8864,7 @@ Path22
Arrival Data Path Delay |
-cell: 0.473, 31.862%; route: 0.812, 54.673%; tC2Q: 0.200, 13.465% |
+cell: 0.000, 0.000%; route: 1.003, 83.377%; tC2Q: 0.200, 16.623% |
Required Clock Path Delay |
@@ -8048,11 +8876,11 @@ Path23
Slack |
-23.364 |
+23.732 |
Data Arrival Time |
-28.454 |
+28.085 |
Data Required Time |
@@ -8060,11 +8888,11 @@ Path23
From |
-gw_gao_inst_0/u_icon_top/enable_reg_2_s0 |
+gw_gao_inst_0/u_icon_top/enable_reg_1_s0 |
To |
-gw_gao_inst_0/u_icon_top/input_shift_reg_1_s0 |
+gw_gao_inst_0/u_icon_top/input_shift_reg_0_s0 |
Launch Clk |
@@ -8146,8 +8974,8 @@ Path23
tNET |
FF |
1 |
-R29C31[0][B] |
-gw_gao_inst_0/u_icon_top/enable_reg_2_s0/CLK |
+R36C25[2][B] |
+gw_gao_inst_0/u_icon_top/enable_reg_1_s0/CLK |
27.168 |
@@ -8155,35 +8983,35 @@ Path23
tC2Q |
FF |
3 |
-R29C31[0][B] |
-gw_gao_inst_0/u_icon_top/enable_reg_2_s0/Q |
+R36C25[2][B] |
+gw_gao_inst_0/u_icon_top/enable_reg_1_s0/Q |
-27.697 |
-0.528 |
+27.310 |
+0.142 |
tNET |
FF |
1 |
-R38C30[1][B] |
-gw_gao_inst_0/u_icon_top/n54_s1/I2 |
+R36C25[1][B] |
+gw_gao_inst_0/u_icon_top/n54_s0/I1 |
-28.170 |
-0.473 |
+27.801 |
+0.491 |
tINS |
FR |
5 |
-R38C30[1][B] |
-gw_gao_inst_0/u_icon_top/n54_s1/F |
+R36C25[1][B] |
+gw_gao_inst_0/u_icon_top/n54_s0/F |
-28.454 |
+28.085 |
0.284 |
tNET |
RR |
1 |
-R38C29[2][B] |
-gw_gao_inst_0/u_icon_top/input_shift_reg_1_s0/CE |
+R36C24[2][A] |
+gw_gao_inst_0/u_icon_top/input_shift_reg_0_s0/CE |
Data Required Path:
@@ -8257,8 +9085,8 @@ Path23
tNET |
RR |
1 |
-R38C29[2][B] |
-gw_gao_inst_0/u_icon_top/input_shift_reg_1_s0/CLK |
+R36C24[2][A] |
+gw_gao_inst_0/u_icon_top/input_shift_reg_0_s0/CLK |
51.818 |
@@ -8266,8 +9094,8 @@ Path23
tSu |
|
1 |
-R38C29[2][B] |
-gw_gao_inst_0/u_icon_top/input_shift_reg_1_s0 |
+R36C24[2][A] |
+gw_gao_inst_0/u_icon_top/input_shift_reg_0_s0 |
Path Statistics:
@@ -8290,7 +9118,7 @@ Path23
Arrival Data Path Delay |
-cell: 0.473, 31.862%; route: 0.812, 54.673%; tC2Q: 0.200, 13.465% |
+cell: 0.491, 44.000%; route: 0.425, 38.092%; tC2Q: 0.200, 17.909% |
Required Clock Path Delay |
@@ -8302,11 +9130,11 @@ Path24
Slack |
-23.527 |
+23.732 |
Data Arrival Time |
-28.290 |
+28.085 |
Data Required Time |
@@ -8314,11 +9142,11 @@ Path24
From |
-gw_gao_inst_0/u_icon_top/tdi_d_s0 |
+gw_gao_inst_0/u_icon_top/enable_reg_1_s0 |
To |
-gw_gao_inst_0/u_ao_top/data_register_45_s0 |
+gw_gao_inst_0/u_icon_top/input_shift_reg_1_s0 |
Launch Clk |
@@ -8400,26 +9228,44 @@ Path24
tNET |
FF |
1 |
-R29C31[0][A] |
-gw_gao_inst_0/u_icon_top/tdi_d_s0/CLK |
+R36C25[2][B] |
+gw_gao_inst_0/u_icon_top/enable_reg_1_s0/CLK |
27.168 |
0.200 |
tC2Q |
FF |
-2 |
-R29C31[0][A] |
-gw_gao_inst_0/u_icon_top/tdi_d_s0/Q |
+3 |
+R36C25[2][B] |
+gw_gao_inst_0/u_icon_top/enable_reg_1_s0/Q |
-28.290 |
-1.122 |
+27.310 |
+0.142 |
tNET |
FF |
1 |
-R40C30[2][A] |
-gw_gao_inst_0/u_ao_top/data_register_45_s0/D |
+R36C25[1][B] |
+gw_gao_inst_0/u_icon_top/n54_s0/I1 |
+
+
+27.801 |
+0.491 |
+tINS |
+FR |
+5 |
+R36C25[1][B] |
+gw_gao_inst_0/u_icon_top/n54_s0/F |
+
+
+28.085 |
+0.284 |
+tNET |
+RR |
+1 |
+R36C24[2][B] |
+gw_gao_inst_0/u_icon_top/input_shift_reg_1_s0/CE |
Data Required Path:
@@ -8493,8 +9339,8 @@ Path24
tNET |
RR |
1 |
-R40C30[2][A] |
-gw_gao_inst_0/u_ao_top/data_register_45_s0/CLK |
+R36C24[2][B] |
+gw_gao_inst_0/u_icon_top/input_shift_reg_1_s0/CLK |
51.818 |
@@ -8502,8 +9348,8 @@ Path24
tSu |
|
1 |
-R40C30[2][A] |
-gw_gao_inst_0/u_ao_top/data_register_45_s0 |
+R36C24[2][B] |
+gw_gao_inst_0/u_icon_top/input_shift_reg_1_s0 |
Path Statistics:
@@ -8518,7 +9364,7 @@ Path24
Logic Level |
-1 |
+2 |
Arrival Clock Path Delay |
@@ -8526,7 +9372,7 @@ Path24
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 1.122, 84.872%; tC2Q: 0.200, 15.128% |
+cell: 0.491, 44.000%; route: 0.425, 38.092%; tC2Q: 0.200, 17.909% |
Required Clock Path Delay |
@@ -8538,11 +9384,11 @@ Path25
Slack |
-23.736 |
+23.946 |
Data Arrival Time |
-28.081 |
+27.872 |
Data Required Time |
@@ -8636,7 +9482,7 @@ Path25
tNET |
FF |
1 |
-R29C31[0][A] |
+R29C25[0][A] |
gw_gao_inst_0/u_icon_top/tdi_d_s0/CLK |
@@ -8645,16 +9491,16 @@ Path25
tC2Q |
FF |
2 |
-R29C31[0][A] |
+R29C25[0][A] |
gw_gao_inst_0/u_icon_top/tdi_d_s0/Q |
-28.081 |
-0.913 |
+27.872 |
+0.703 |
tNET |
FF |
1 |
-R38C30[1][A] |
+R36C25[1][A] |
gw_gao_inst_0/u_icon_top/input_shift_reg_4_s0/D |
@@ -8729,7 +9575,7 @@ Path25
tNET |
RR |
1 |
-R38C30[1][A] |
+R36C25[1][A] |
gw_gao_inst_0/u_icon_top/input_shift_reg_4_s0/CLK |
@@ -8738,7 +9584,7 @@ Path25
tSu |
|
1 |
-R38C30[1][A] |
+R36C25[1][A] |
gw_gao_inst_0/u_icon_top/input_shift_reg_4_s0 |
@@ -8762,7 +9608,7 @@ Path25
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.913, 82.027%; tC2Q: 0.200, 17.973% |
+cell: 0.000, 0.000%; route: 0.703, 77.865%; tC2Q: 0.200, 22.135% |
Required Clock Path Delay |
@@ -8776,11 +9622,11 @@ Path1
Slack |
--0.423 |
+-0.473 |
Data Arrival Time |
-201.271 |
+201.221 |
Data Required Time |
@@ -8846,7 +9692,7 @@ Path1
0.581 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -8856,43 +9702,43 @@ Path1
tNET |
RR |
1 |
-R43C26[2][A] |
+R44C20[2][A] |
gw_gao_inst_0/u_ao_top/capture_start_sel_s1/CLK |
-200.914 |
-0.174 |
+200.913 |
+0.173 |
tC2Q |
-RR |
+RF |
3 |
-R43C26[2][A] |
+R44C20[2][A] |
gw_gao_inst_0/u_ao_top/capture_start_sel_s1/Q |
201.021 |
-0.107 |
+0.108 |
tNET |
-RR |
+FF |
1 |
-R41C26[1][A] |
+R44C21[0][A] |
gw_gao_inst_0/u_ao_top/n836_s1/I1 |
-201.271 |
-0.250 |
+201.221 |
+0.200 |
tINS |
-RF |
+FF |
1 |
-R41C26[1][A] |
+R44C21[0][A] |
gw_gao_inst_0/u_ao_top/n836_s1/F |
-201.271 |
+201.221 |
0.000 |
tNET |
FF |
1 |
-R41C26[1][A] |
+R44C21[0][A] |
gw_gao_inst_0/u_ao_top/capture_end_tck_0_s0/D |
@@ -8967,7 +9813,7 @@ Path1
tNET |
RR |
1 |
-R41C26[1][A] |
+R44C21[0][A] |
gw_gao_inst_0/u_ao_top/capture_end_tck_0_s0/CLK |
@@ -8985,7 +9831,7 @@ Path1
tHld |
|
1 |
-R41C26[1][A] |
+R44C21[0][A] |
gw_gao_inst_0/u_ao_top/capture_end_tck_0_s0 |
@@ -9009,7 +9855,7 @@ Path1
Arrival Data Path Delay |
-cell: 0.250, 47.044%; route: 0.107, 20.187%; tC2Q: 0.174, 32.769% |
+cell: 0.200, 41.564%; route: 0.108, 22.426%; tC2Q: 0.173, 36.010% |
Required Clock Path Delay |
@@ -9021,11 +9867,11 @@ Path2
Slack |
-0.314 |
+0.202 |
Data Arrival Time |
-1.268 |
+1.156 |
Data Required Time |
@@ -9033,11 +9879,11 @@ Path2
From |
-s480p/de_s0 |
+arkanoid/red_7_s0 |
To |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_12_s |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_11_s |
Launch Clk |
@@ -9091,7 +9937,7 @@ Path2
0.581 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -9101,26 +9947,26 @@ Path2
tNET |
RR |
1 |
-R41C33[0][A] |
-s480p/de_s0/CLK |
+R42C30[0][A] |
+arkanoid/red_7_s0/CLK |
0.914 |
0.174 |
tC2Q |
RR |
-2 |
-R41C33[0][A] |
-s480p/de_s0/Q |
+32 |
+R42C30[0][A] |
+arkanoid/red_7_s0/Q |
-1.268 |
-0.354 |
+1.156 |
+0.242 |
tNET |
RR |
1 |
-BSRAM_R46[10] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_12_s/DI[0] |
+BSRAM_R46[9] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_11_s/DI[1] |
Data Required Path:
@@ -9166,7 +10012,7 @@ Path2
0.581 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -9176,8 +10022,8 @@ Path2
tNET |
RR |
1 |
-BSRAM_R46[10] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_12_s/CLKA |
+BSRAM_R46[9] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_11_s/CLKA |
0.954 |
@@ -9185,8 +10031,8 @@ Path2
tHld |
|
1 |
-BSRAM_R46[10] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_12_s |
+BSRAM_R46[9] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_11_s |
Path Statistics:
@@ -9209,7 +10055,7 @@ Path2
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.354, 67.040%; tC2Q: 0.174, 32.960% |
+cell: 0.000, 0.000%; route: 0.242, 58.196%; tC2Q: 0.174, 41.804% |
Required Clock Path Delay |
@@ -9221,11 +10067,11 @@ Path3
Slack |
-0.319 |
+0.202 |
Data Arrival Time |
-1.273 |
+1.156 |
Data Required Time |
@@ -9291,7 +10137,7 @@ Path3
0.581 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -9301,7 +10147,7 @@ Path3
tNET |
RR |
1 |
-R39C34[2][A] |
+R42C30[0][A] |
arkanoid/red_7_s0/CLK |
@@ -9310,17 +10156,17 @@ Path3
tC2Q |
RR |
32 |
-R39C34[2][A] |
+R42C30[0][A] |
arkanoid/red_7_s0/Q |
-1.273 |
-0.359 |
+1.156 |
+0.242 |
tNET |
RR |
1 |
BSRAM_R46[9] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_11_s/DI[1] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_11_s/DI[0] |
Data Required Path:
@@ -9366,7 +10212,7 @@ Path3
0.581 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -9409,7 +10255,7 @@ Path3
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.359, 67.360%; tC2Q: 0.174, 32.640% |
+cell: 0.000, 0.000%; route: 0.242, 58.196%; tC2Q: 0.174, 41.804% |
Required Clock Path Delay |
@@ -9421,11 +10267,11 @@ Path4
Slack |
-0.319 |
+0.202 |
Data Arrival Time |
-1.273 |
+1.156 |
Data Required Time |
@@ -9437,7 +10283,7 @@ Path4
To |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_11_s |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_10_s |
Launch Clk |
@@ -9491,7 +10337,7 @@ Path4
0.581 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -9501,7 +10347,7 @@ Path4
tNET |
RR |
1 |
-R39C34[2][A] |
+R42C30[0][A] |
arkanoid/red_7_s0/CLK |
@@ -9510,17 +10356,17 @@ Path4
tC2Q |
RR |
32 |
-R39C34[2][A] |
+R42C30[0][A] |
arkanoid/red_7_s0/Q |
-1.273 |
-0.359 |
+1.156 |
+0.242 |
tNET |
RR |
1 |
-BSRAM_R46[9] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_11_s/DI[0] |
+BSRAM_R46[8] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_10_s/DI[1] |
Data Required Path:
@@ -9566,7 +10412,7 @@ Path4
0.581 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -9576,8 +10422,8 @@ Path4
tNET |
RR |
1 |
-BSRAM_R46[9] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_11_s/CLKA |
+BSRAM_R46[8] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_10_s/CLKA |
0.954 |
@@ -9585,8 +10431,8 @@ Path4
tHld |
|
1 |
-BSRAM_R46[9] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_11_s |
+BSRAM_R46[8] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_10_s |
Path Statistics:
@@ -9609,7 +10455,7 @@ Path4
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.359, 67.360%; tC2Q: 0.174, 32.640% |
+cell: 0.000, 0.000%; route: 0.242, 58.196%; tC2Q: 0.174, 41.804% |
Required Clock Path Delay |
@@ -9621,23 +10467,23 @@ Path5
Slack |
-0.367 |
+0.202 |
Data Arrival Time |
-1.116 |
+1.156 |
Data Required Time |
-0.749 |
+0.954 |
From |
-s480p/y_6_s0 |
+arkanoid/red_7_s0 |
To |
-s480p/y_6_s0 |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_10_s |
Launch Clk |
@@ -9691,7 +10537,7 @@ Path5
0.581 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -9701,44 +10547,26 @@ Path5
tNET |
RR |
1 |
-R39C33[0][A] |
-s480p/y_6_s0/CLK |
+R42C30[0][A] |
+arkanoid/red_7_s0/CLK |
0.914 |
0.174 |
tC2Q |
RR |
-3 |
-R39C33[0][A] |
-s480p/y_6_s0/Q |
+32 |
+R42C30[0][A] |
+arkanoid/red_7_s0/Q |
-0.916 |
-0.002 |
+1.156 |
+0.242 |
tNET |
RR |
-2 |
-R39C33[0][A] |
-s480p/n109_s/I1 |
-
-
-1.116 |
-0.200 |
-tINS |
-RF |
-1 |
-R39C33[0][A] |
-s480p/n109_s/SUM |
-
-
-1.116 |
-0.000 |
-tNET |
-FF |
1 |
-R39C33[0][A] |
-s480p/y_6_s0/D |
+BSRAM_R46[8] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_10_s/DI[0] |
Data Required Path:
@@ -9784,7 +10612,7 @@ Path5
0.581 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -9794,17 +10622,17 @@ Path5
tNET |
RR |
1 |
-R39C33[0][A] |
-s480p/y_6_s0/CLK |
+BSRAM_R46[8] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_10_s/CLKA |
-0.749 |
-0.009 |
+0.954 |
+0.215 |
tHld |
|
1 |
-R39C33[0][A] |
-s480p/y_6_s0 |
+BSRAM_R46[8] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_10_s |
Path Statistics:
@@ -9819,7 +10647,7 @@ Path5
Logic Level |
-2 |
+1 |
Arrival Clock Path Delay |
@@ -9827,7 +10655,7 @@ Path5
Arrival Data Path Delay |
-cell: 0.200, 53.157%; route: 0.002, 0.560%; tC2Q: 0.174, 46.283% |
+cell: 0.000, 0.000%; route: 0.242, 58.196%; tC2Q: 0.174, 41.804% |
Required Clock Path Delay |
@@ -9839,31 +10667,31 @@ Path6
Slack |
-0.367 |
+0.291 |
Data Arrival Time |
-1.116 |
+2.042 |
Data Required Time |
-0.749 |
+1.751 |
From |
-s480p/y_12_s0 |
+gw_gao_inst_0/u_ao_top/address_counter_11_s0 |
To |
-s480p/y_12_s0 |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_6_s |
Launch Clk |
-clk:[R] |
+tck_pad_i:[R] |
Latch Clk |
-clk:[R] |
+tck_pad_i:[R] |
Data Arrival Path:
@@ -9893,7 +10721,7 @@ Path6
|
|
|
-clk |
+tck_pad_i |
0.000 |
@@ -9901,62 +10729,62 @@ Path6
tCL |
RR |
1 |
-IOL29[A] |
-clk_ibuf/I |
+IOR26[A] |
+gw_gao_inst_0/tck_ibuf/I |
0.581 |
0.581 |
tINS |
RR |
-207 |
-IOL29[A] |
-clk_ibuf/O |
+1 |
+IOR26[A] |
+gw_gao_inst_0/tck_ibuf/O |
-0.740 |
-0.159 |
+0.581 |
+0.000 |
tNET |
RR |
1 |
-R39C34[0][A] |
-s480p/y_12_s0/CLK |
+- |
+gw_gao_inst_0/u_gw_jtag/tck_pad_i |
-0.914 |
-0.174 |
-tC2Q |
+1.162 |
+0.581 |
+tINS |
RR |
-3 |
-R39C34[0][A] |
-s480p/y_12_s0/Q |
+181 |
+- |
+gw_gao_inst_0/u_gw_jtag/tck_o |
-0.916 |
-0.002 |
-tNET |
+1.649 |
+0.487 |
+tNET |
RR |
-2 |
-R39C34[0][A] |
-s480p/n103_s/I1 |
+1 |
+R42C21[2][A] |
+gw_gao_inst_0/u_ao_top/address_counter_11_s0/CLK |
-1.116 |
-0.200 |
-tINS |
-RF |
-1 |
-R39C34[0][A] |
-s480p/n103_s/SUM |
+1.823 |
+0.174 |
+tC2Q |
+RR |
+15 |
+R42C21[2][A] |
+gw_gao_inst_0/u_ao_top/address_counter_11_s0/Q |
-1.116 |
-0.000 |
+2.042 |
+0.219 |
tNET |
-FF |
+RR |
1 |
-R39C34[0][A] |
-s480p/y_12_s0/D |
+BSRAM_R46[5] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_6_s/ADB[12] |
Data Required Path:
@@ -9986,7 +10814,7 @@ Path6
|
|
|
-clk |
+tck_pad_i |
0.000 |
@@ -9994,35 +10822,53 @@ Path6
tCL |
RR |
1 |
-IOL29[A] |
-clk_ibuf/I |
+IOR26[A] |
+gw_gao_inst_0/tck_ibuf/I |
0.581 |
0.581 |
tINS |
RR |
-207 |
-IOL29[A] |
-clk_ibuf/O |
+1 |
+IOR26[A] |
+gw_gao_inst_0/tck_ibuf/O |
-0.740 |
-0.159 |
+0.581 |
+0.000 |
tNET |
RR |
1 |
-R39C34[0][A] |
-s480p/y_12_s0/CLK |
+- |
+gw_gao_inst_0/u_gw_jtag/tck_pad_i |
-0.749 |
-0.009 |
+1.162 |
+0.581 |
+tINS |
+RR |
+181 |
+- |
+gw_gao_inst_0/u_gw_jtag/tck_o |
+
+
+1.649 |
+0.487 |
+tNET |
+RR |
+1 |
+BSRAM_R46[5] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKB |
+
+
+1.751 |
+0.102 |
tHld |
|
1 |
-R39C34[0][A] |
-s480p/y_12_s0 |
+BSRAM_R46[5] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_6_s |
Path Statistics:
@@ -10037,19 +10883,19 @@ Path6
Logic Level |
-2 |
+1 |
Arrival Clock Path Delay |
-cell: 0.581, 78.528%; route: 0.159, 21.472% |
+cell: 1.162, 70.449%; route: 0.487, 29.551% |
Arrival Data Path Delay |
-cell: 0.200, 53.157%; route: 0.002, 0.560%; tC2Q: 0.174, 46.283% |
+cell: 0.000, 0.000%; route: 0.219, 55.680%; tC2Q: 0.174, 44.320% |
Required Clock Path Delay |
-cell: 0.581, 78.528%; route: 0.159, 21.472% |
+cell: 1.162, 70.449%; route: 0.487, 29.551% |
Path7
@@ -10057,23 +10903,23 @@ Path7
Slack |
-0.367 |
+0.307 |
Data Arrival Time |
-1.116 |
+1.261 |
Data Required Time |
-0.749 |
+0.954 |
From |
-s480p/y_14_s0 |
+arkanoid/red_7_s0 |
To |
-s480p/y_14_s0 |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_9_s |
Launch Clk |
@@ -10127,7 +10973,7 @@ Path7
0.581 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -10137,44 +10983,26 @@ Path7
tNET |
RR |
1 |
-R39C34[1][A] |
-s480p/y_14_s0/CLK |
+R42C30[0][A] |
+arkanoid/red_7_s0/CLK |
0.914 |
0.174 |
tC2Q |
RR |
-3 |
-R39C34[1][A] |
-s480p/y_14_s0/Q |
+32 |
+R42C30[0][A] |
+arkanoid/red_7_s0/Q |
-0.916 |
-0.002 |
+1.261 |
+0.348 |
tNET |
RR |
-2 |
-R39C34[1][A] |
-s480p/n101_s/I1 |
-
-
-1.116 |
-0.200 |
-tINS |
-RF |
-1 |
-R39C34[1][A] |
-s480p/n101_s/SUM |
-
-
-1.116 |
-0.000 |
-tNET |
-FF |
1 |
-R39C34[1][A] |
-s480p/y_14_s0/D |
+BSRAM_R46[7] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_9_s/DI[1] |
Data Required Path:
@@ -10220,7 +11048,7 @@ Path7
0.581 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -10230,17 +11058,17 @@ Path7
tNET |
RR |
1 |
-R39C34[1][A] |
-s480p/y_14_s0/CLK |
+BSRAM_R46[7] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_9_s/CLKA |
-0.749 |
-0.009 |
+0.954 |
+0.215 |
tHld |
|
1 |
-R39C34[1][A] |
-s480p/y_14_s0 |
+BSRAM_R46[7] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_9_s |
Path Statistics:
@@ -10255,7 +11083,7 @@ Path7
Logic Level |
-2 |
+1 |
Arrival Clock Path Delay |
@@ -10263,7 +11091,7 @@ Path7
Arrival Data Path Delay |
-cell: 0.200, 53.157%; route: 0.002, 0.560%; tC2Q: 0.174, 46.283% |
+cell: 0.000, 0.000%; route: 0.348, 66.623%; tC2Q: 0.174, 33.377% |
Required Clock Path Delay |
@@ -10275,23 +11103,23 @@ Path8
Slack |
-0.367 |
+0.307 |
Data Arrival Time |
-1.116 |
+1.261 |
Data Required Time |
-0.749 |
+0.954 |
From |
-s480p/x_12_s0 |
+arkanoid/red_7_s0 |
To |
-s480p/x_12_s0 |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_9_s |
Launch Clk |
@@ -10345,7 +11173,7 @@ Path8
0.581 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -10355,44 +11183,26 @@ Path8
tNET |
RR |
1 |
-R38C34[0][A] |
-s480p/x_12_s0/CLK |
+R42C30[0][A] |
+arkanoid/red_7_s0/CLK |
0.914 |
0.174 |
tC2Q |
RR |
-3 |
-R38C34[0][A] |
-s480p/x_12_s0/Q |
+32 |
+R42C30[0][A] |
+arkanoid/red_7_s0/Q |
-0.916 |
-0.002 |
+1.261 |
+0.348 |
tNET |
RR |
-2 |
-R38C34[0][A] |
-s480p/n168_s/I1 |
-
-
-1.116 |
-0.200 |
-tINS |
-RF |
-1 |
-R38C34[0][A] |
-s480p/n168_s/SUM |
-
-
-1.116 |
-0.000 |
-tNET |
-FF |
1 |
-R38C34[0][A] |
-s480p/x_12_s0/D |
+BSRAM_R46[7] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_9_s/DI[0] |
Data Required Path:
@@ -10438,7 +11248,7 @@ Path8
0.581 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -10448,17 +11258,17 @@ Path8
tNET |
RR |
1 |
-R38C34[0][A] |
-s480p/x_12_s0/CLK |
+BSRAM_R46[7] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_9_s/CLKA |
-0.749 |
-0.009 |
+0.954 |
+0.215 |
tHld |
|
1 |
-R38C34[0][A] |
-s480p/x_12_s0 |
+BSRAM_R46[7] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_9_s |
Path Statistics:
@@ -10473,7 +11283,7 @@ Path8
Logic Level |
-2 |
+1 |
Arrival Clock Path Delay |
@@ -10481,7 +11291,7 @@ Path8
Arrival Data Path Delay |
-cell: 0.200, 53.157%; route: 0.002, 0.560%; tC2Q: 0.174, 46.283% |
+cell: 0.000, 0.000%; route: 0.348, 66.623%; tC2Q: 0.174, 33.377% |
Required Clock Path Delay |
@@ -10493,31 +11303,31 @@ Path9
Slack |
-0.367 |
+0.315 |
Data Arrival Time |
-2.025 |
+1.156 |
Data Required Time |
-1.659 |
+0.841 |
From |
-gw_gao_inst_0/u_ao_top/word_count_3_s0 |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
To |
-gw_gao_inst_0/u_ao_top/word_count_3_s0 |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_6_s |
Launch Clk |
-tck_pad_i:[R] |
+clk:[R] |
Latch Clk |
-tck_pad_i:[R] |
+clk:[R] |
Data Arrival Path:
@@ -10547,7 +11357,7 @@ Path9
|
|
|
-tck_pad_i |
+clk |
0.000 |
@@ -10555,80 +11365,44 @@ Path9
tCL |
RR |
1 |
-IOR26[A] |
-gw_gao_inst_0/tck_ibuf/I |
-
-
-0.581 |
-0.581 |
-tINS |
-RR |
-1 |
-IOR26[A] |
-gw_gao_inst_0/tck_ibuf/O |
+IOL29[A] |
+clk_ibuf/I |
0.581 |
-0.000 |
-tNET |
-RR |
-1 |
-- |
-gw_gao_inst_0/u_gw_jtag/tck_pad_i |
-
-
-1.162 |
0.581 |
tINS |
RR |
-181 |
-- |
-gw_gao_inst_0/u_gw_jtag/tck_o |
+277 |
+IOL29[A] |
+clk_ibuf/O |
-1.649 |
-0.487 |
+0.740 |
+0.159 |
tNET |
RR |
1 |
-R41C31[0][A] |
-gw_gao_inst_0/u_ao_top/word_count_3_s0/CLK |
+R40C20[2][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK |
-1.823 |
+0.914 |
0.174 |
tC2Q |
RR |
-3 |
-R41C31[0][A] |
-gw_gao_inst_0/u_ao_top/word_count_3_s0/Q |
+16 |
+R40C20[2][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q |
-1.825 |
-0.002 |
+1.156 |
+0.242 |
tNET |
RR |
1 |
-R41C31[0][A] |
-gw_gao_inst_0/u_ao_top/data_to_word_counter_3_s2/I2 |
-
-
-2.025 |
-0.200 |
-tINS |
-RF |
-1 |
-R41C31[0][A] |
-gw_gao_inst_0/u_ao_top/data_to_word_counter_3_s2/F |
-
-
-2.025 |
-0.000 |
-tNET |
-FF |
-1 |
-R41C31[0][A] |
-gw_gao_inst_0/u_ao_top/word_count_3_s0/D |
+BSRAM_R46[5] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_6_s/ADA[6] |
Data Required Path:
@@ -10658,7 +11432,7 @@ Path9
|
|
|
-tck_pad_i |
+clk |
0.000 |
@@ -10666,53 +11440,35 @@ Path9
tCL |
RR |
1 |
-IOR26[A] |
-gw_gao_inst_0/tck_ibuf/I |
-
-
-0.581 |
-0.581 |
-tINS |
-RR |
-1 |
-IOR26[A] |
-gw_gao_inst_0/tck_ibuf/O |
+IOL29[A] |
+clk_ibuf/I |
0.581 |
-0.000 |
-tNET |
-RR |
-1 |
-- |
-gw_gao_inst_0/u_gw_jtag/tck_pad_i |
-
-
-1.162 |
0.581 |
tINS |
RR |
-181 |
-- |
-gw_gao_inst_0/u_gw_jtag/tck_o |
+277 |
+IOL29[A] |
+clk_ibuf/O |
-1.649 |
-0.487 |
+0.740 |
+0.159 |
tNET |
RR |
1 |
-R41C31[0][A] |
-gw_gao_inst_0/u_ao_top/word_count_3_s0/CLK |
+BSRAM_R46[5] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA |
-1.659 |
-0.009 |
+0.841 |
+0.102 |
tHld |
|
1 |
-R41C31[0][A] |
-gw_gao_inst_0/u_ao_top/word_count_3_s0 |
+BSRAM_R46[5] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_6_s |
Path Statistics:
@@ -10727,19 +11483,19 @@ Path9
Logic Level |
-2 |
+1 |
Arrival Clock Path Delay |
-cell: 1.162, 70.449%; route: 0.487, 29.551% |
+cell: 0.581, 78.528%; route: 0.159, 21.472% |
Arrival Data Path Delay |
-cell: 0.200, 53.157%; route: 0.002, 0.560%; tC2Q: 0.174, 46.283% |
+cell: 0.000, 0.000%; route: 0.242, 58.181%; tC2Q: 0.174, 41.819% |
Required Clock Path Delay |
-cell: 1.162, 70.449%; route: 0.487, 29.551% |
+cell: 0.581, 78.528%; route: 0.159, 21.472% |
Path10
@@ -10747,23 +11503,23 @@ Path10
Slack |
-0.367 |
+0.317 |
Data Arrival Time |
-2.025 |
+2.068 |
Data Required Time |
-1.659 |
+1.751 |
From |
-gw_gao_inst_0/u_ao_top/word_count_6_s0 |
+gw_gao_inst_0/u_ao_top/address_counter_7_s0 |
To |
-gw_gao_inst_0/u_ao_top/word_count_6_s0 |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_8_s |
Launch Clk |
@@ -10845,44 +11601,26 @@ Path10
tNET |
RR |
1 |
-R44C29[0][A] |
-gw_gao_inst_0/u_ao_top/word_count_6_s0/CLK |
+R42C21[2][B] |
+gw_gao_inst_0/u_ao_top/address_counter_7_s0/CLK |
1.823 |
0.174 |
tC2Q |
RR |
-3 |
-R44C29[0][A] |
-gw_gao_inst_0/u_ao_top/word_count_6_s0/Q |
+17 |
+R42C21[2][B] |
+gw_gao_inst_0/u_ao_top/address_counter_7_s0/Q |
-1.825 |
-0.002 |
+2.068 |
+0.245 |
tNET |
RR |
1 |
-R44C29[0][A] |
-gw_gao_inst_0/u_ao_top/data_to_word_counter_6_s2/I2 |
-
-
-2.025 |
-0.200 |
-tINS |
-RF |
-1 |
-R44C29[0][A] |
-gw_gao_inst_0/u_ao_top/data_to_word_counter_6_s2/F |
-
-
-2.025 |
-0.000 |
-tNET |
-FF |
-1 |
-R44C29[0][A] |
-gw_gao_inst_0/u_ao_top/word_count_6_s0/D |
+BSRAM_R46[6] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_8_s/ADB[8] |
Data Required Path:
@@ -10956,17 +11694,17 @@ Path10
tNET |
RR |
1 |
-R44C29[0][A] |
-gw_gao_inst_0/u_ao_top/word_count_6_s0/CLK |
+BSRAM_R46[6] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_8_s/CLKB |
-1.659 |
-0.009 |
+1.751 |
+0.102 |
tHld |
|
1 |
-R44C29[0][A] |
-gw_gao_inst_0/u_ao_top/word_count_6_s0 |
+BSRAM_R46[6] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_8_s |
Path Statistics:
@@ -10981,7 +11719,7 @@ Path10
Logic Level |
-2 |
+1 |
Arrival Clock Path Delay |
@@ -10989,7 +11727,7 @@ Path10
Arrival Data Path Delay |
-cell: 0.200, 53.157%; route: 0.002, 0.560%; tC2Q: 0.174, 46.283% |
+cell: 0.000, 0.000%; route: 0.245, 58.463%; tC2Q: 0.174, 41.537% |
Required Clock Path Delay |
@@ -11001,23 +11739,23 @@ Path11
Slack |
-0.367 |
+0.317 |
Data Arrival Time |
-2.025 |
+2.068 |
Data Required Time |
-1.659 |
+1.751 |
From |
-gw_gao_inst_0/u_ao_top/word_count_15_s0 |
+gw_gao_inst_0/u_ao_top/address_counter_7_s0 |
To |
-gw_gao_inst_0/u_ao_top/word_count_15_s0 |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_6_s |
Launch Clk |
@@ -11099,44 +11837,26 @@ Path11
tNET |
RR |
1 |
-R43C31[0][A] |
-gw_gao_inst_0/u_ao_top/word_count_15_s0/CLK |
+R42C21[2][B] |
+gw_gao_inst_0/u_ao_top/address_counter_7_s0/CLK |
1.823 |
0.174 |
tC2Q |
RR |
-3 |
-R43C31[0][A] |
-gw_gao_inst_0/u_ao_top/word_count_15_s0/Q |
+17 |
+R42C21[2][B] |
+gw_gao_inst_0/u_ao_top/address_counter_7_s0/Q |
-1.825 |
-0.002 |
+2.068 |
+0.245 |
tNET |
RR |
1 |
-R43C31[0][A] |
-gw_gao_inst_0/u_ao_top/data_to_word_counter_15_s2/I3 |
-
-
-2.025 |
-0.200 |
-tINS |
-RF |
-1 |
-R43C31[0][A] |
-gw_gao_inst_0/u_ao_top/data_to_word_counter_15_s2/F |
-
-
-2.025 |
-0.000 |
-tNET |
-FF |
-1 |
-R43C31[0][A] |
-gw_gao_inst_0/u_ao_top/word_count_15_s0/D |
+BSRAM_R46[5] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_6_s/ADB[8] |
Data Required Path:
@@ -11210,17 +11930,17 @@ Path11
tNET |
RR |
1 |
-R43C31[0][A] |
-gw_gao_inst_0/u_ao_top/word_count_15_s0/CLK |
+BSRAM_R46[5] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKB |
-1.659 |
-0.009 |
+1.751 |
+0.102 |
tHld |
|
1 |
-R43C31[0][A] |
-gw_gao_inst_0/u_ao_top/word_count_15_s0 |
+BSRAM_R46[5] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_6_s |
Path Statistics:
@@ -11235,7 +11955,7 @@ Path11
Logic Level |
-2 |
+1 |
Arrival Clock Path Delay |
@@ -11243,7 +11963,7 @@ Path11
Arrival Data Path Delay |
-cell: 0.200, 53.157%; route: 0.002, 0.560%; tC2Q: 0.174, 46.283% |
+cell: 0.000, 0.000%; route: 0.245, 58.463%; tC2Q: 0.174, 41.537% |
Required Clock Path Delay |
@@ -11255,23 +11975,23 @@ Path12
Slack |
-0.368 |
+0.342 |
Data Arrival Time |
-1.117 |
+1.296 |
Data Required Time |
-0.749 |
+0.954 |
From |
-s480p/y_0_s0 |
+arkanoid/red_7_s0 |
To |
-s480p/y_0_s0 |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_8_s |
Launch Clk |
@@ -11325,7 +12045,7 @@ Path12
0.581 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -11335,44 +12055,26 @@ Path12
tNET |
RR |
1 |
-R39C31[1][A] |
-s480p/y_0_s0/CLK |
+R42C30[0][A] |
+arkanoid/red_7_s0/CLK |
0.914 |
0.174 |
tC2Q |
RR |
-5 |
-R39C31[1][A] |
-s480p/y_0_s0/Q |
+32 |
+R42C30[0][A] |
+arkanoid/red_7_s0/Q |
-0.917 |
-0.003 |
+1.296 |
+0.383 |
tNET |
RR |
1 |
-R39C31[1][A] |
-s480p/n115_s2/I0 |
-
-
-1.117 |
-0.200 |
-tINS |
-RF |
-1 |
-R39C31[1][A] |
-s480p/n115_s2/F |
-
-
-1.117 |
-0.000 |
-tNET |
-FF |
-1 |
-R39C31[1][A] |
-s480p/y_0_s0/D |
+BSRAM_R46[6] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_8_s/DI[1] |
Data Required Path:
@@ -11418,7 +12120,7 @@ Path12
0.581 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -11428,17 +12130,17 @@ Path12
tNET |
RR |
1 |
-R39C31[1][A] |
-s480p/y_0_s0/CLK |
+BSRAM_R46[6] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_8_s/CLKA |
-0.749 |
-0.009 |
+0.954 |
+0.215 |
tHld |
|
1 |
-R39C31[1][A] |
-s480p/y_0_s0 |
+BSRAM_R46[6] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_8_s |
Path Statistics:
@@ -11453,7 +12155,7 @@ Path12
Logic Level |
-2 |
+1 |
Arrival Clock Path Delay |
@@ -11461,7 +12163,7 @@ Path12
Arrival Data Path Delay |
-cell: 0.200, 53.008%; route: 0.003, 0.838%; tC2Q: 0.174, 46.154% |
+cell: 0.000, 0.000%; route: 0.383, 68.721%; tC2Q: 0.174, 31.279% |
Required Clock Path Delay |
@@ -11473,23 +12175,23 @@ Path13
Slack |
-0.368 |
+0.342 |
Data Arrival Time |
-1.117 |
+1.296 |
Data Required Time |
-0.749 |
+0.954 |
From |
-s480p/y_2_s0 |
+arkanoid/red_7_s0 |
To |
-s480p/y_2_s0 |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_8_s |
Launch Clk |
@@ -11543,7 +12245,7 @@ Path13
0.581 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -11553,44 +12255,26 @@ Path13
tNET |
RR |
1 |
-R39C32[1][A] |
-s480p/y_2_s0/CLK |
+R42C30[0][A] |
+arkanoid/red_7_s0/CLK |
0.914 |
0.174 |
tC2Q |
RR |
-5 |
-R39C32[1][A] |
-s480p/y_2_s0/Q |
+32 |
+R42C30[0][A] |
+arkanoid/red_7_s0/Q |
-0.917 |
-0.003 |
+1.296 |
+0.383 |
tNET |
RR |
-2 |
-R39C32[1][A] |
-s480p/n113_s/I1 |
-
-
-1.117 |
-0.200 |
-tINS |
-RF |
-1 |
-R39C32[1][A] |
-s480p/n113_s/SUM |
-
-
-1.117 |
-0.000 |
-tNET |
-FF |
1 |
-R39C32[1][A] |
-s480p/y_2_s0/D |
+BSRAM_R46[6] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_8_s/DI[0] |
Data Required Path:
@@ -11636,7 +12320,7 @@ Path13
0.581 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -11646,17 +12330,17 @@ Path13
tNET |
RR |
1 |
-R39C32[1][A] |
-s480p/y_2_s0/CLK |
+BSRAM_R46[6] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_8_s/CLKA |
-0.749 |
-0.009 |
+0.954 |
+0.215 |
tHld |
|
1 |
-R39C32[1][A] |
-s480p/y_2_s0 |
+BSRAM_R46[6] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_mem_0_8_s |
Path Statistics:
@@ -11671,7 +12355,7 @@ Path13
Logic Level |
-2 |
+1 |
Arrival Clock Path Delay |
@@ -11679,7 +12363,7 @@ Path13
Arrival Data Path Delay |
-cell: 0.200, 53.008%; route: 0.003, 0.838%; tC2Q: 0.174, 46.154% |
+cell: 0.000, 0.000%; route: 0.383, 68.721%; tC2Q: 0.174, 31.279% |
Required Clock Path Delay |
@@ -11691,11 +12375,11 @@ Path14
Slack |
-0.368 |
+0.367 |
Data Arrival Time |
-1.117 |
+1.116 |
Data Required Time |
@@ -11761,7 +12445,7 @@ Path14
0.581 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -11771,7 +12455,7 @@ Path14
tNET |
RR |
1 |
-R39C33[1][A] |
+R36C28[1][A] |
s480p/y_8_s0/CLK |
@@ -11779,35 +12463,35 @@ Path14
0.174 |
tC2Q |
RR |
-4 |
-R39C33[1][A] |
+3 |
+R36C28[1][A] |
s480p/y_8_s0/Q |
-0.917 |
-0.003 |
+0.916 |
+0.002 |
tNET |
RR |
2 |
-R39C33[1][A] |
+R36C28[1][A] |
s480p/n107_s/I1 |
-1.117 |
+1.116 |
0.200 |
tINS |
RF |
1 |
-R39C33[1][A] |
+R36C28[1][A] |
s480p/n107_s/SUM |
-1.117 |
+1.116 |
0.000 |
tNET |
FF |
1 |
-R39C33[1][A] |
+R36C28[1][A] |
s480p/y_8_s0/D |
@@ -11854,7 +12538,7 @@ Path14
0.581 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -11864,7 +12548,7 @@ Path14
tNET |
RR |
1 |
-R39C33[1][A] |
+R36C28[1][A] |
s480p/y_8_s0/CLK |
@@ -11873,7 +12557,7 @@ Path14
tHld |
|
1 |
-R39C33[1][A] |
+R36C28[1][A] |
s480p/y_8_s0 |
@@ -11897,7 +12581,7 @@ Path14
Arrival Data Path Delay |
-cell: 0.200, 53.008%; route: 0.003, 0.838%; tC2Q: 0.174, 46.154% |
+cell: 0.200, 53.157%; route: 0.002, 0.560%; tC2Q: 0.174, 46.283% |
Required Clock Path Delay |
@@ -11909,11 +12593,11 @@ Path15
Slack |
-0.368 |
+0.367 |
Data Arrival Time |
-1.117 |
+1.116 |
Data Required Time |
@@ -11921,11 +12605,11 @@ Path15
From |
-s480p/x_2_s0 |
+s480p/y_12_s0 |
To |
-s480p/x_2_s0 |
+s480p/y_12_s0 |
Launch Clk |
@@ -11979,7 +12663,7 @@ Path15
0.581 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -11989,44 +12673,44 @@ Path15
tNET |
RR |
1 |
-R38C32[1][A] |
-s480p/x_2_s0/CLK |
+R36C29[0][A] |
+s480p/y_12_s0/CLK |
0.914 |
0.174 |
tC2Q |
RR |
-4 |
-R38C32[1][A] |
-s480p/x_2_s0/Q |
+3 |
+R36C29[0][A] |
+s480p/y_12_s0/Q |
-0.917 |
-0.003 |
+0.916 |
+0.002 |
tNET |
RR |
2 |
-R38C32[1][A] |
-s480p/n178_s/I1 |
+R36C29[0][A] |
+s480p/n103_s/I1 |
-1.117 |
+1.116 |
0.200 |
tINS |
RF |
1 |
-R38C32[1][A] |
-s480p/n178_s/SUM |
+R36C29[0][A] |
+s480p/n103_s/SUM |
-1.117 |
+1.116 |
0.000 |
tNET |
FF |
1 |
-R38C32[1][A] |
-s480p/x_2_s0/D |
+R36C29[0][A] |
+s480p/y_12_s0/D |
Data Required Path:
@@ -12072,7 +12756,7 @@ Path15
0.581 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -12082,8 +12766,8 @@ Path15
tNET |
RR |
1 |
-R38C32[1][A] |
-s480p/x_2_s0/CLK |
+R36C29[0][A] |
+s480p/y_12_s0/CLK |
0.749 |
@@ -12091,8 +12775,8 @@ Path15
tHld |
|
1 |
-R38C32[1][A] |
-s480p/x_2_s0 |
+R36C29[0][A] |
+s480p/y_12_s0 |
Path Statistics:
@@ -12115,7 +12799,7 @@ Path15
Arrival Data Path Delay |
-cell: 0.200, 53.008%; route: 0.003, 0.838%; tC2Q: 0.174, 46.154% |
+cell: 0.200, 53.157%; route: 0.002, 0.560%; tC2Q: 0.174, 46.283% |
Required Clock Path Delay |
@@ -12127,11 +12811,11 @@ Path16
Slack |
-0.368 |
+0.367 |
Data Arrival Time |
-1.117 |
+1.116 |
Data Required Time |
@@ -12139,11 +12823,11 @@ Path16
From |
-s480p/x_6_s0 |
+s480p/y_14_s0 |
To |
-s480p/x_6_s0 |
+s480p/y_14_s0 |
Launch Clk |
@@ -12197,7 +12881,7 @@ Path16
0.581 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -12207,44 +12891,44 @@ Path16
tNET |
RR |
1 |
-R38C33[0][A] |
-s480p/x_6_s0/CLK |
+R36C29[1][A] |
+s480p/y_14_s0/CLK |
0.914 |
0.174 |
tC2Q |
RR |
-5 |
-R38C33[0][A] |
-s480p/x_6_s0/Q |
+3 |
+R36C29[1][A] |
+s480p/y_14_s0/Q |
-0.917 |
-0.003 |
+0.916 |
+0.002 |
tNET |
RR |
2 |
-R38C33[0][A] |
-s480p/n174_s/I1 |
+R36C29[1][A] |
+s480p/n101_s/I1 |
-1.117 |
+1.116 |
0.200 |
tINS |
RF |
1 |
-R38C33[0][A] |
-s480p/n174_s/SUM |
+R36C29[1][A] |
+s480p/n101_s/SUM |
-1.117 |
+1.116 |
0.000 |
tNET |
FF |
1 |
-R38C33[0][A] |
-s480p/x_6_s0/D |
+R36C29[1][A] |
+s480p/y_14_s0/D |
Data Required Path:
@@ -12290,7 +12974,7 @@ Path16
0.581 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -12300,8 +12984,8 @@ Path16
tNET |
RR |
1 |
-R38C33[0][A] |
-s480p/x_6_s0/CLK |
+R36C29[1][A] |
+s480p/y_14_s0/CLK |
0.749 |
@@ -12309,8 +12993,8 @@ Path16
tHld |
|
1 |
-R38C33[0][A] |
-s480p/x_6_s0 |
+R36C29[1][A] |
+s480p/y_14_s0 |
Path Statistics:
@@ -12333,7 +13017,7 @@ Path16
Arrival Data Path Delay |
-cell: 0.200, 53.008%; route: 0.003, 0.838%; tC2Q: 0.174, 46.154% |
+cell: 0.200, 53.157%; route: 0.002, 0.560%; tC2Q: 0.174, 46.283% |
Required Clock Path Delay |
@@ -12345,11 +13029,11 @@ Path17
Slack |
-0.368 |
+0.367 |
Data Arrival Time |
-1.117 |
+1.116 |
Data Required Time |
@@ -12357,11 +13041,11 @@ Path17
From |
-s480p/x_8_s0 |
+s480p/x_14_s0 |
To |
-s480p/x_8_s0 |
+s480p/x_14_s0 |
Launch Clk |
@@ -12415,7 +13099,7 @@ Path17
0.581 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -12425,44 +13109,44 @@ Path17
tNET |
RR |
1 |
-R38C33[1][A] |
-s480p/x_8_s0/CLK |
+R41C29[1][A] |
+s480p/x_14_s0/CLK |
0.914 |
0.174 |
tC2Q |
RR |
-4 |
-R38C33[1][A] |
-s480p/x_8_s0/Q |
+3 |
+R41C29[1][A] |
+s480p/x_14_s0/Q |
-0.917 |
-0.003 |
+0.916 |
+0.002 |
tNET |
RR |
2 |
-R38C33[1][A] |
-s480p/n172_s/I1 |
+R41C29[1][A] |
+s480p/n166_s/I1 |
-1.117 |
+1.116 |
0.200 |
tINS |
RF |
1 |
-R38C33[1][A] |
-s480p/n172_s/SUM |
+R41C29[1][A] |
+s480p/n166_s/SUM |
-1.117 |
+1.116 |
0.000 |
tNET |
FF |
1 |
-R38C33[1][A] |
-s480p/x_8_s0/D |
+R41C29[1][A] |
+s480p/x_14_s0/D |
Data Required Path:
@@ -12508,7 +13192,7 @@ Path17
0.581 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -12518,8 +13202,8 @@ Path17
tNET |
RR |
1 |
-R38C33[1][A] |
-s480p/x_8_s0/CLK |
+R41C29[1][A] |
+s480p/x_14_s0/CLK |
0.749 |
@@ -12527,8 +13211,8 @@ Path17
tHld |
|
1 |
-R38C33[1][A] |
-s480p/x_8_s0 |
+R41C29[1][A] |
+s480p/x_14_s0 |
Path Statistics:
@@ -12551,7 +13235,7 @@ Path17
Arrival Data Path Delay |
-cell: 0.200, 53.008%; route: 0.003, 0.838%; tC2Q: 0.174, 46.154% |
+cell: 0.200, 53.157%; route: 0.002, 0.560%; tC2Q: 0.174, 46.283% |
Required Clock Path Delay |
@@ -12563,31 +13247,31 @@ Path18
Slack |
-0.368 |
+0.367 |
Data Arrival Time |
-1.117 |
+2.025 |
Data Required Time |
-0.749 |
+1.659 |
From |
-s480p/x_14_s0 |
+gw_gao_inst_0/u_ao_top/bit_count_3_s1 |
To |
-s480p/x_14_s0 |
+gw_gao_inst_0/u_ao_top/bit_count_3_s1 |
Launch Clk |
-clk:[R] |
+tck_pad_i:[R] |
Latch Clk |
-clk:[R] |
+tck_pad_i:[R] |
Data Arrival Path:
@@ -12617,7 +13301,7 @@ Path18
|
|
|
-clk |
+tck_pad_i |
0.000 |
@@ -12625,62 +13309,80 @@ Path18
tCL |
RR |
1 |
-IOL29[A] |
-clk_ibuf/I |
+IOR26[A] |
+gw_gao_inst_0/tck_ibuf/I |
0.581 |
0.581 |
tINS |
RR |
-207 |
-IOL29[A] |
-clk_ibuf/O |
+1 |
+IOR26[A] |
+gw_gao_inst_0/tck_ibuf/O |
-0.740 |
-0.159 |
+0.581 |
+0.000 |
tNET |
RR |
1 |
-R38C34[1][A] |
-s480p/x_14_s0/CLK |
+- |
+gw_gao_inst_0/u_gw_jtag/tck_pad_i |
-0.914 |
+1.162 |
+0.581 |
+tINS |
+RR |
+181 |
+- |
+gw_gao_inst_0/u_gw_jtag/tck_o |
+
+
+1.649 |
+0.487 |
+tNET |
+RR |
+1 |
+R41C24[0][A] |
+gw_gao_inst_0/u_ao_top/bit_count_3_s1/CLK |
+
+
+1.823 |
0.174 |
tC2Q |
RR |
-3 |
-R38C34[1][A] |
-s480p/x_14_s0/Q |
+4 |
+R41C24[0][A] |
+gw_gao_inst_0/u_ao_top/bit_count_3_s1/Q |
-0.917 |
-0.003 |
+1.825 |
+0.002 |
tNET |
RR |
-2 |
-R38C34[1][A] |
-s480p/n166_s/I1 |
+1 |
+R41C24[0][A] |
+gw_gao_inst_0/u_ao_top/n445_s2/I1 |
-1.117 |
+2.025 |
0.200 |
tINS |
RF |
1 |
-R38C34[1][A] |
-s480p/n166_s/SUM |
+R41C24[0][A] |
+gw_gao_inst_0/u_ao_top/n445_s2/F |
-1.117 |
+2.025 |
0.000 |
tNET |
FF |
1 |
-R38C34[1][A] |
-s480p/x_14_s0/D |
+R41C24[0][A] |
+gw_gao_inst_0/u_ao_top/bit_count_3_s1/D |
Data Required Path:
@@ -12710,7 +13412,7 @@ Path18
|
|
|
-clk |
+tck_pad_i |
0.000 |
@@ -12718,35 +13420,53 @@ Path18
tCL |
RR |
1 |
-IOL29[A] |
-clk_ibuf/I |
+IOR26[A] |
+gw_gao_inst_0/tck_ibuf/I |
0.581 |
0.581 |
tINS |
RR |
-207 |
-IOL29[A] |
-clk_ibuf/O |
+1 |
+IOR26[A] |
+gw_gao_inst_0/tck_ibuf/O |
-0.740 |
-0.159 |
+0.581 |
+0.000 |
tNET |
RR |
1 |
-R38C34[1][A] |
-s480p/x_14_s0/CLK |
+- |
+gw_gao_inst_0/u_gw_jtag/tck_pad_i |
-0.749 |
+1.162 |
+0.581 |
+tINS |
+RR |
+181 |
+- |
+gw_gao_inst_0/u_gw_jtag/tck_o |
+
+
+1.649 |
+0.487 |
+tNET |
+RR |
+1 |
+R41C24[0][A] |
+gw_gao_inst_0/u_ao_top/bit_count_3_s1/CLK |
+
+
+1.659 |
0.009 |
tHld |
|
1 |
-R38C34[1][A] |
-s480p/x_14_s0 |
+R41C24[0][A] |
+gw_gao_inst_0/u_ao_top/bit_count_3_s1 |
Path Statistics:
@@ -12765,15 +13485,15 @@ Path18
Arrival Clock Path Delay |
-cell: 0.581, 78.528%; route: 0.159, 21.472% |
+cell: 1.162, 70.449%; route: 0.487, 29.551% |
Arrival Data Path Delay |
-cell: 0.200, 53.008%; route: 0.003, 0.838%; tC2Q: 0.174, 46.154% |
+cell: 0.200, 53.157%; route: 0.002, 0.560%; tC2Q: 0.174, 46.283% |
Required Clock Path Delay |
-cell: 0.581, 78.528%; route: 0.159, 21.472% |
+cell: 1.162, 70.449%; route: 0.487, 29.551% |
Path19
@@ -12781,11 +13501,11 @@ Path19
Slack |
-0.368 |
+0.367 |
Data Arrival Time |
-2.026 |
+2.025 |
Data Required Time |
@@ -12793,11 +13513,11 @@ Path19
From |
-gw_gao_inst_0/u_ao_top/word_count_0_s0 |
+gw_gao_inst_0/u_ao_top/word_count_11_s0 |
To |
-gw_gao_inst_0/u_ao_top/word_count_0_s0 |
+gw_gao_inst_0/u_ao_top/word_count_11_s0 |
Launch Clk |
@@ -12879,44 +13599,44 @@ Path19
tNET |
RR |
1 |
-R41C30[0][A] |
-gw_gao_inst_0/u_ao_top/word_count_0_s0/CLK |
+R42C24[0][A] |
+gw_gao_inst_0/u_ao_top/word_count_11_s0/CLK |
1.823 |
0.174 |
tC2Q |
RR |
-5 |
-R41C30[0][A] |
-gw_gao_inst_0/u_ao_top/word_count_0_s0/Q |
+2 |
+R42C24[0][A] |
+gw_gao_inst_0/u_ao_top/word_count_11_s0/Q |
-1.827 |
-0.003 |
+1.825 |
+0.002 |
tNET |
RR |
1 |
-R41C30[0][A] |
-gw_gao_inst_0/u_ao_top/data_to_word_counter_0_s4/I0 |
+R42C24[0][A] |
+gw_gao_inst_0/u_ao_top/data_to_word_counter_11_s2/I3 |
-2.026 |
+2.025 |
0.200 |
tINS |
RF |
1 |
-R41C30[0][A] |
-gw_gao_inst_0/u_ao_top/data_to_word_counter_0_s4/F |
+R42C24[0][A] |
+gw_gao_inst_0/u_ao_top/data_to_word_counter_11_s2/F |
-2.026 |
+2.025 |
0.000 |
tNET |
FF |
1 |
-R41C30[0][A] |
-gw_gao_inst_0/u_ao_top/word_count_0_s0/D |
+R42C24[0][A] |
+gw_gao_inst_0/u_ao_top/word_count_11_s0/D |
Data Required Path:
@@ -12990,8 +13710,8 @@ Path19
tNET |
RR |
1 |
-R41C30[0][A] |
-gw_gao_inst_0/u_ao_top/word_count_0_s0/CLK |
+R42C24[0][A] |
+gw_gao_inst_0/u_ao_top/word_count_11_s0/CLK |
1.659 |
@@ -12999,8 +13719,8 @@ Path19
tHld |
|
1 |
-R41C30[0][A] |
-gw_gao_inst_0/u_ao_top/word_count_0_s0 |
+R42C24[0][A] |
+gw_gao_inst_0/u_ao_top/word_count_11_s0 |
Path Statistics:
@@ -13023,7 +13743,7 @@ Path19
Arrival Data Path Delay |
-cell: 0.200, 53.008%; route: 0.003, 0.838%; tC2Q: 0.174, 46.154% |
+cell: 0.200, 53.157%; route: 0.002, 0.560%; tC2Q: 0.174, 46.283% |
Required Clock Path Delay |
@@ -13039,27 +13759,27 @@ Path20
Data Arrival Time |
-2.026 |
+1.117 |
Data Required Time |
-1.659 |
+0.749 |
From |
-gw_gao_inst_0/u_ao_top/word_count_11_s0 |
+s480p/y_6_s0 |
To |
-gw_gao_inst_0/u_ao_top/word_count_11_s0 |
+s480p/y_6_s0 |
Launch Clk |
-tck_pad_i:[R] |
+clk:[R] |
Latch Clk |
-tck_pad_i:[R] |
+clk:[R] |
Data Arrival Path:
@@ -13089,7 +13809,7 @@ Path20
|
|
|
-tck_pad_i |
+clk |
0.000 |
@@ -13097,80 +13817,62 @@ Path20
tCL |
RR |
1 |
-IOR26[A] |
-gw_gao_inst_0/tck_ibuf/I |
-
-
-0.581 |
-0.581 |
-tINS |
-RR |
-1 |
-IOR26[A] |
-gw_gao_inst_0/tck_ibuf/O |
+IOL29[A] |
+clk_ibuf/I |
0.581 |
-0.000 |
-tNET |
-RR |
-1 |
-- |
-gw_gao_inst_0/u_gw_jtag/tck_pad_i |
-
-
-1.162 |
0.581 |
tINS |
RR |
-181 |
-- |
-gw_gao_inst_0/u_gw_jtag/tck_o |
+277 |
+IOL29[A] |
+clk_ibuf/O |
-1.649 |
-0.487 |
+0.740 |
+0.159 |
tNET |
RR |
1 |
-R43C31[1][A] |
-gw_gao_inst_0/u_ao_top/word_count_11_s0/CLK |
+R36C28[0][A] |
+s480p/y_6_s0/CLK |
-1.823 |
+0.914 |
0.174 |
tC2Q |
RR |
3 |
-R43C31[1][A] |
-gw_gao_inst_0/u_ao_top/word_count_11_s0/Q |
+R36C28[0][A] |
+s480p/y_6_s0/Q |
-1.827 |
+0.917 |
0.003 |
tNET |
RR |
-1 |
-R43C31[1][A] |
-gw_gao_inst_0/u_ao_top/data_to_word_counter_11_s2/I2 |
+2 |
+R36C28[0][A] |
+s480p/n109_s/I1 |
-2.026 |
+1.117 |
0.200 |
tINS |
RF |
1 |
-R43C31[1][A] |
-gw_gao_inst_0/u_ao_top/data_to_word_counter_11_s2/F |
+R36C28[0][A] |
+s480p/n109_s/SUM |
-2.026 |
+1.117 |
0.000 |
tNET |
FF |
1 |
-R43C31[1][A] |
-gw_gao_inst_0/u_ao_top/word_count_11_s0/D |
+R36C28[0][A] |
+s480p/y_6_s0/D |
Data Required Path:
@@ -13200,7 +13902,7 @@ Path20
|
|
|
-tck_pad_i |
+clk |
0.000 |
@@ -13208,53 +13910,35 @@ Path20
tCL |
RR |
1 |
-IOR26[A] |
-gw_gao_inst_0/tck_ibuf/I |
-
-
-0.581 |
-0.581 |
-tINS |
-RR |
-1 |
-IOR26[A] |
-gw_gao_inst_0/tck_ibuf/O |
+IOL29[A] |
+clk_ibuf/I |
0.581 |
-0.000 |
-tNET |
-RR |
-1 |
-- |
-gw_gao_inst_0/u_gw_jtag/tck_pad_i |
-
-
-1.162 |
0.581 |
tINS |
RR |
-181 |
-- |
-gw_gao_inst_0/u_gw_jtag/tck_o |
+277 |
+IOL29[A] |
+clk_ibuf/O |
-1.649 |
-0.487 |
+0.740 |
+0.159 |
tNET |
RR |
1 |
-R43C31[1][A] |
-gw_gao_inst_0/u_ao_top/word_count_11_s0/CLK |
+R36C28[0][A] |
+s480p/y_6_s0/CLK |
-1.659 |
+0.749 |
0.009 |
tHld |
|
1 |
-R43C31[1][A] |
-gw_gao_inst_0/u_ao_top/word_count_11_s0 |
+R36C28[0][A] |
+s480p/y_6_s0 |
Path Statistics:
@@ -13273,7 +13957,7 @@ Path20
Arrival Clock Path Delay |
-cell: 1.162, 70.449%; route: 0.487, 29.551% |
+cell: 0.581, 78.528%; route: 0.159, 21.472% |
Arrival Data Path Delay |
@@ -13281,7 +13965,7 @@ Path20
Required Clock Path Delay |
-cell: 1.162, 70.449%; route: 0.487, 29.551% |
+cell: 0.581, 78.528%; route: 0.159, 21.472% |
Path21
@@ -13293,27 +13977,27 @@ Path21
Data Arrival Time |
-2.026 |
+1.117 |
Data Required Time |
-1.659 |
+0.749 |
From |
-gw_gao_inst_0/u_ao_top/word_count_13_s0 |
+s480p/x_2_s0 |
To |
-gw_gao_inst_0/u_ao_top/word_count_13_s0 |
+s480p/x_2_s0 |
Launch Clk |
-tck_pad_i:[R] |
+clk:[R] |
Latch Clk |
-tck_pad_i:[R] |
+clk:[R] |
Data Arrival Path:
@@ -13343,7 +14027,7 @@ Path21
|
|
|
-tck_pad_i |
+clk |
0.000 |
@@ -13351,80 +14035,62 @@ Path21
tCL |
RR |
1 |
-IOR26[A] |
-gw_gao_inst_0/tck_ibuf/I |
-
-
-0.581 |
-0.581 |
-tINS |
-RR |
-1 |
-IOR26[A] |
-gw_gao_inst_0/tck_ibuf/O |
+IOL29[A] |
+clk_ibuf/I |
0.581 |
-0.000 |
-tNET |
-RR |
-1 |
-- |
-gw_gao_inst_0/u_gw_jtag/tck_pad_i |
-
-
-1.162 |
0.581 |
tINS |
RR |
-181 |
-- |
-gw_gao_inst_0/u_gw_jtag/tck_o |
+277 |
+IOL29[A] |
+clk_ibuf/O |
-1.649 |
-0.487 |
+0.740 |
+0.159 |
tNET |
RR |
1 |
-R44C31[0][A] |
-gw_gao_inst_0/u_ao_top/word_count_13_s0/CLK |
+R41C27[1][A] |
+s480p/x_2_s0/CLK |
-1.823 |
+0.914 |
0.174 |
tC2Q |
RR |
-3 |
-R44C31[0][A] |
-gw_gao_inst_0/u_ao_top/word_count_13_s0/Q |
+4 |
+R41C27[1][A] |
+s480p/x_2_s0/Q |
-1.827 |
+0.917 |
0.003 |
tNET |
RR |
-1 |
-R44C31[0][A] |
-gw_gao_inst_0/u_ao_top/data_to_word_counter_13_s2/I3 |
+2 |
+R41C27[1][A] |
+s480p/n178_s/I1 |
-2.026 |
+1.117 |
0.200 |
tINS |
RF |
1 |
-R44C31[0][A] |
-gw_gao_inst_0/u_ao_top/data_to_word_counter_13_s2/F |
+R41C27[1][A] |
+s480p/n178_s/SUM |
-2.026 |
+1.117 |
0.000 |
tNET |
FF |
1 |
-R44C31[0][A] |
-gw_gao_inst_0/u_ao_top/word_count_13_s0/D |
+R41C27[1][A] |
+s480p/x_2_s0/D |
Data Required Path:
@@ -13454,7 +14120,7 @@ Path21
|
|
|
-tck_pad_i |
+clk |
0.000 |
@@ -13462,53 +14128,35 @@ Path21
tCL |
RR |
1 |
-IOR26[A] |
-gw_gao_inst_0/tck_ibuf/I |
-
-
-0.581 |
-0.581 |
-tINS |
-RR |
-1 |
-IOR26[A] |
-gw_gao_inst_0/tck_ibuf/O |
+IOL29[A] |
+clk_ibuf/I |
0.581 |
-0.000 |
-tNET |
-RR |
-1 |
-- |
-gw_gao_inst_0/u_gw_jtag/tck_pad_i |
-
-
-1.162 |
0.581 |
tINS |
RR |
-181 |
-- |
-gw_gao_inst_0/u_gw_jtag/tck_o |
+277 |
+IOL29[A] |
+clk_ibuf/O |
-1.649 |
-0.487 |
+0.740 |
+0.159 |
tNET |
RR |
1 |
-R44C31[0][A] |
-gw_gao_inst_0/u_ao_top/word_count_13_s0/CLK |
+R41C27[1][A] |
+s480p/x_2_s0/CLK |
-1.659 |
+0.749 |
0.009 |
tHld |
|
1 |
-R44C31[0][A] |
-gw_gao_inst_0/u_ao_top/word_count_13_s0 |
+R41C27[1][A] |
+s480p/x_2_s0 |
Path Statistics:
@@ -13527,7 +14175,7 @@ Path21
Arrival Clock Path Delay |
-cell: 1.162, 70.449%; route: 0.487, 29.551% |
+cell: 0.581, 78.528%; route: 0.159, 21.472% |
Arrival Data Path Delay |
@@ -13535,7 +14183,7 @@ Path21
Required Clock Path Delay |
-cell: 1.162, 70.449%; route: 0.487, 29.551% |
+cell: 0.581, 78.528%; route: 0.159, 21.472% |
Path22
@@ -13543,31 +14191,31 @@ Path22
Slack |
-0.369 |
+0.368 |
Data Arrival Time |
-2.028 |
+1.117 |
Data Required Time |
-1.659 |
+0.749 |
From |
-gw_gao_inst_0/u_ao_top/bit_count_0_s3 |
+s480p/x_8_s0 |
To |
-gw_gao_inst_0/u_ao_top/bit_count_0_s3 |
+s480p/x_8_s0 |
Launch Clk |
-tck_pad_i:[R] |
+clk:[R] |
Latch Clk |
-tck_pad_i:[R] |
+clk:[R] |
Data Arrival Path:
@@ -13597,7 +14245,7 @@ Path22
|
|
|
-tck_pad_i |
+clk |
0.000 |
@@ -13605,80 +14253,62 @@ Path22
tCL |
RR |
1 |
-IOR26[A] |
-gw_gao_inst_0/tck_ibuf/I |
-
-
-0.581 |
-0.581 |
-tINS |
-RR |
-1 |
-IOR26[A] |
-gw_gao_inst_0/tck_ibuf/O |
+IOL29[A] |
+clk_ibuf/I |
0.581 |
-0.000 |
-tNET |
-RR |
-1 |
-- |
-gw_gao_inst_0/u_gw_jtag/tck_pad_i |
-
-
-1.162 |
0.581 |
tINS |
RR |
-181 |
-- |
-gw_gao_inst_0/u_gw_jtag/tck_o |
+277 |
+IOL29[A] |
+clk_ibuf/O |
-1.649 |
-0.487 |
+0.740 |
+0.159 |
tNET |
RR |
1 |
-R42C29[1][A] |
-gw_gao_inst_0/u_ao_top/bit_count_0_s3/CLK |
+R41C28[1][A] |
+s480p/x_8_s0/CLK |
-1.823 |
+0.914 |
0.174 |
tC2Q |
RR |
-7 |
-R42C29[1][A] |
-gw_gao_inst_0/u_ao_top/bit_count_0_s3/Q |
+4 |
+R41C28[1][A] |
+s480p/x_8_s0/Q |
-1.828 |
-0.004 |
+0.917 |
+0.003 |
tNET |
RR |
-1 |
-R42C29[1][A] |
-gw_gao_inst_0/u_ao_top/n448_s5/I0 |
+2 |
+R41C28[1][A] |
+s480p/n172_s/I1 |
-2.028 |
+1.117 |
0.200 |
tINS |
RF |
1 |
-R42C29[1][A] |
-gw_gao_inst_0/u_ao_top/n448_s5/F |
+R41C28[1][A] |
+s480p/n172_s/SUM |
-2.028 |
+1.117 |
0.000 |
tNET |
FF |
1 |
-R42C29[1][A] |
-gw_gao_inst_0/u_ao_top/bit_count_0_s3/D |
+R41C28[1][A] |
+s480p/x_8_s0/D |
Data Required Path:
@@ -13708,7 +14338,7 @@ Path22
|
|
|
-tck_pad_i |
+clk |
0.000 |
@@ -13716,53 +14346,35 @@ Path22
tCL |
RR |
1 |
-IOR26[A] |
-gw_gao_inst_0/tck_ibuf/I |
-
-
-0.581 |
-0.581 |
-tINS |
-RR |
-1 |
-IOR26[A] |
-gw_gao_inst_0/tck_ibuf/O |
+IOL29[A] |
+clk_ibuf/I |
0.581 |
-0.000 |
-tNET |
-RR |
-1 |
-- |
-gw_gao_inst_0/u_gw_jtag/tck_pad_i |
-
-
-1.162 |
0.581 |
tINS |
RR |
-181 |
-- |
-gw_gao_inst_0/u_gw_jtag/tck_o |
+277 |
+IOL29[A] |
+clk_ibuf/O |
-1.649 |
-0.487 |
+0.740 |
+0.159 |
tNET |
RR |
1 |
-R42C29[1][A] |
-gw_gao_inst_0/u_ao_top/bit_count_0_s3/CLK |
+R41C28[1][A] |
+s480p/x_8_s0/CLK |
-1.659 |
+0.749 |
0.009 |
tHld |
|
1 |
-R42C29[1][A] |
-gw_gao_inst_0/u_ao_top/bit_count_0_s3 |
+R41C28[1][A] |
+s480p/x_8_s0 |
Path Statistics:
@@ -13781,15 +14393,15 @@ Path22
Arrival Clock Path Delay |
-cell: 1.162, 70.449%; route: 0.487, 29.551% |
+cell: 0.581, 78.528%; route: 0.159, 21.472% |
Arrival Data Path Delay |
-cell: 0.200, 52.861%; route: 0.004, 1.114%; tC2Q: 0.174, 46.025% |
+cell: 0.200, 53.008%; route: 0.003, 0.838%; tC2Q: 0.174, 46.154% |
Required Clock Path Delay |
-cell: 1.162, 70.449%; route: 0.487, 29.551% |
+cell: 0.581, 78.528%; route: 0.159, 21.472% |
Path23
@@ -13797,31 +14409,31 @@ Path23
Slack |
-0.369 |
+0.368 |
Data Arrival Time |
-2.028 |
+1.117 |
Data Required Time |
-1.659 |
+0.749 |
From |
-gw_gao_inst_0/u_ao_top/bit_count_1_s1 |
+s480p/x_12_s0 |
To |
-gw_gao_inst_0/u_ao_top/bit_count_1_s1 |
+s480p/x_12_s0 |
Launch Clk |
-tck_pad_i:[R] |
+clk:[R] |
Latch Clk |
-tck_pad_i:[R] |
+clk:[R] |
Data Arrival Path:
@@ -13851,7 +14463,7 @@ Path23
|
|
|
-tck_pad_i |
+clk |
0.000 |
@@ -13859,80 +14471,62 @@ Path23
tCL |
RR |
1 |
-IOR26[A] |
-gw_gao_inst_0/tck_ibuf/I |
-
-
-0.581 |
-0.581 |
-tINS |
-RR |
-1 |
-IOR26[A] |
-gw_gao_inst_0/tck_ibuf/O |
+IOL29[A] |
+clk_ibuf/I |
0.581 |
-0.000 |
-tNET |
-RR |
-1 |
-- |
-gw_gao_inst_0/u_gw_jtag/tck_pad_i |
-
-
-1.162 |
0.581 |
tINS |
RR |
-181 |
-- |
-gw_gao_inst_0/u_gw_jtag/tck_o |
+277 |
+IOL29[A] |
+clk_ibuf/O |
-1.649 |
-0.487 |
+0.740 |
+0.159 |
tNET |
RR |
1 |
-R39C30[1][A] |
-gw_gao_inst_0/u_ao_top/bit_count_1_s1/CLK |
+R41C29[0][A] |
+s480p/x_12_s0/CLK |
-1.823 |
+0.914 |
0.174 |
tC2Q |
RR |
-6 |
-R39C30[1][A] |
-gw_gao_inst_0/u_ao_top/bit_count_1_s1/Q |
+3 |
+R41C29[0][A] |
+s480p/x_12_s0/Q |
-1.828 |
-0.004 |
+0.917 |
+0.003 |
tNET |
RR |
-1 |
-R39C30[1][A] |
-gw_gao_inst_0/u_ao_top/n447_s3/I3 |
+2 |
+R41C29[0][A] |
+s480p/n168_s/I1 |
-2.028 |
+1.117 |
0.200 |
tINS |
RF |
1 |
-R39C30[1][A] |
-gw_gao_inst_0/u_ao_top/n447_s3/F |
+R41C29[0][A] |
+s480p/n168_s/SUM |
-2.028 |
+1.117 |
0.000 |
tNET |
FF |
1 |
-R39C30[1][A] |
-gw_gao_inst_0/u_ao_top/bit_count_1_s1/D |
+R41C29[0][A] |
+s480p/x_12_s0/D |
Data Required Path:
@@ -13962,7 +14556,7 @@ Path23
|
|
|
-tck_pad_i |
+clk |
0.000 |
@@ -13970,53 +14564,35 @@ Path23
tCL |
RR |
1 |
-IOR26[A] |
-gw_gao_inst_0/tck_ibuf/I |
-
-
-0.581 |
-0.581 |
-tINS |
-RR |
-1 |
-IOR26[A] |
-gw_gao_inst_0/tck_ibuf/O |
+IOL29[A] |
+clk_ibuf/I |
0.581 |
-0.000 |
-tNET |
-RR |
-1 |
-- |
-gw_gao_inst_0/u_gw_jtag/tck_pad_i |
-
-
-1.162 |
0.581 |
tINS |
RR |
-181 |
-- |
-gw_gao_inst_0/u_gw_jtag/tck_o |
+277 |
+IOL29[A] |
+clk_ibuf/O |
-1.649 |
-0.487 |
+0.740 |
+0.159 |
tNET |
RR |
1 |
-R39C30[1][A] |
-gw_gao_inst_0/u_ao_top/bit_count_1_s1/CLK |
+R41C29[0][A] |
+s480p/x_12_s0/CLK |
-1.659 |
+0.749 |
0.009 |
tHld |
|
1 |
-R39C30[1][A] |
-gw_gao_inst_0/u_ao_top/bit_count_1_s1 |
+R41C29[0][A] |
+s480p/x_12_s0 |
Path Statistics:
@@ -14035,15 +14611,15 @@ Path23
Arrival Clock Path Delay |
-cell: 1.162, 70.449%; route: 0.487, 29.551% |
+cell: 0.581, 78.528%; route: 0.159, 21.472% |
Arrival Data Path Delay |
-cell: 0.200, 52.861%; route: 0.004, 1.114%; tC2Q: 0.174, 46.025% |
+cell: 0.200, 53.008%; route: 0.003, 0.838%; tC2Q: 0.174, 46.154% |
Required Clock Path Delay |
-cell: 1.162, 70.449%; route: 0.487, 29.551% |
+cell: 0.581, 78.528%; route: 0.159, 21.472% |
Path24
@@ -14051,11 +14627,11 @@ Path24
Slack |
-0.369 |
+0.368 |
Data Arrival Time |
-2.028 |
+2.026 |
Data Required Time |
@@ -14063,11 +14639,11 @@ Path24
From |
-gw_gao_inst_0/u_ao_top/word_count_1_s0 |
+gw_gao_inst_0/u_ao_top/bit_count_2_s1 |
To |
-gw_gao_inst_0/u_ao_top/word_count_1_s0 |
+gw_gao_inst_0/u_ao_top/bit_count_2_s1 |
Launch Clk |
@@ -14149,44 +14725,44 @@ Path24
tNET |
RR |
1 |
-R41C31[1][A] |
-gw_gao_inst_0/u_ao_top/word_count_1_s0/CLK |
+R41C26[1][A] |
+gw_gao_inst_0/u_ao_top/bit_count_2_s1/CLK |
1.823 |
0.174 |
tC2Q |
RR |
-5 |
-R41C31[1][A] |
-gw_gao_inst_0/u_ao_top/word_count_1_s0/Q |
+4 |
+R41C26[1][A] |
+gw_gao_inst_0/u_ao_top/bit_count_2_s1/Q |
-1.828 |
-0.004 |
+1.827 |
+0.003 |
tNET |
RR |
1 |
-R41C31[1][A] |
-gw_gao_inst_0/u_ao_top/data_to_word_counter_1_s2/I1 |
+R41C26[1][A] |
+gw_gao_inst_0/u_ao_top/n446_s2/I3 |
-2.028 |
+2.026 |
0.200 |
tINS |
RF |
1 |
-R41C31[1][A] |
-gw_gao_inst_0/u_ao_top/data_to_word_counter_1_s2/F |
+R41C26[1][A] |
+gw_gao_inst_0/u_ao_top/n446_s2/F |
-2.028 |
+2.026 |
0.000 |
tNET |
FF |
1 |
-R41C31[1][A] |
-gw_gao_inst_0/u_ao_top/word_count_1_s0/D |
+R41C26[1][A] |
+gw_gao_inst_0/u_ao_top/bit_count_2_s1/D |
Data Required Path:
@@ -14260,8 +14836,8 @@ Path24
tNET |
RR |
1 |
-R41C31[1][A] |
-gw_gao_inst_0/u_ao_top/word_count_1_s0/CLK |
+R41C26[1][A] |
+gw_gao_inst_0/u_ao_top/bit_count_2_s1/CLK |
1.659 |
@@ -14269,8 +14845,8 @@ Path24
tHld |
|
1 |
-R41C31[1][A] |
-gw_gao_inst_0/u_ao_top/word_count_1_s0 |
+R41C26[1][A] |
+gw_gao_inst_0/u_ao_top/bit_count_2_s1 |
Path Statistics:
@@ -14293,7 +14869,7 @@ Path24
Arrival Data Path Delay |
-cell: 0.200, 52.861%; route: 0.004, 1.114%; tC2Q: 0.174, 46.025% |
+cell: 0.200, 53.008%; route: 0.003, 0.838%; tC2Q: 0.174, 46.154% |
Required Clock Path Delay |
@@ -14305,11 +14881,11 @@ Path25
Slack |
-0.369 |
+0.368 |
Data Arrival Time |
-2.028 |
+2.026 |
Data Required Time |
@@ -14317,11 +14893,11 @@ Path25
From |
-gw_gao_inst_0/u_ao_top/word_count_5_s0 |
+gw_gao_inst_0/u_ao_top/word_count_6_s0 |
To |
-gw_gao_inst_0/u_ao_top/word_count_5_s0 |
+gw_gao_inst_0/u_ao_top/word_count_6_s0 |
Launch Clk |
@@ -14403,44 +14979,44 @@ Path25
tNET |
RR |
1 |
-R43C29[1][A] |
-gw_gao_inst_0/u_ao_top/word_count_5_s0/CLK |
+R42C26[0][A] |
+gw_gao_inst_0/u_ao_top/word_count_6_s0/CLK |
1.823 |
0.174 |
tC2Q |
RR |
-4 |
-R43C29[1][A] |
-gw_gao_inst_0/u_ao_top/word_count_5_s0/Q |
+3 |
+R42C26[0][A] |
+gw_gao_inst_0/u_ao_top/word_count_6_s0/Q |
-1.828 |
-0.004 |
+1.827 |
+0.003 |
tNET |
RR |
1 |
-R43C29[1][A] |
-gw_gao_inst_0/u_ao_top/data_to_word_counter_5_s2/I3 |
+R42C26[0][A] |
+gw_gao_inst_0/u_ao_top/data_to_word_counter_6_s2/I1 |
-2.028 |
+2.026 |
0.200 |
tINS |
RF |
1 |
-R43C29[1][A] |
-gw_gao_inst_0/u_ao_top/data_to_word_counter_5_s2/F |
+R42C26[0][A] |
+gw_gao_inst_0/u_ao_top/data_to_word_counter_6_s2/F |
-2.028 |
+2.026 |
0.000 |
tNET |
FF |
1 |
-R43C29[1][A] |
-gw_gao_inst_0/u_ao_top/word_count_5_s0/D |
+R42C26[0][A] |
+gw_gao_inst_0/u_ao_top/word_count_6_s0/D |
Data Required Path:
@@ -14514,8 +15090,8 @@ Path25
tNET |
RR |
1 |
-R43C29[1][A] |
-gw_gao_inst_0/u_ao_top/word_count_5_s0/CLK |
+R42C26[0][A] |
+gw_gao_inst_0/u_ao_top/word_count_6_s0/CLK |
1.659 |
@@ -14523,8 +15099,8 @@ Path25
tHld |
|
1 |
-R43C29[1][A] |
-gw_gao_inst_0/u_ao_top/word_count_5_s0 |
+R42C26[0][A] |
+gw_gao_inst_0/u_ao_top/word_count_6_s0 |
Path Statistics:
@@ -14547,7 +15123,7 @@ Path25
Arrival Data Path Delay |
-cell: 0.200, 52.861%; route: 0.004, 1.114%; tC2Q: 0.174, 46.025% |
+cell: 0.200, 53.008%; route: 0.003, 0.838%; tC2Q: 0.174, 46.154% |
Required Clock Path Delay |
@@ -14561,11 +15137,11 @@ Path1
Slack |
-10.390 |
+10.398 |
Data Arrival Time |
-141.393 |
+141.384 |
Data Required Time |
@@ -14631,7 +15207,7 @@ Path1
0.591 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -14641,7 +15217,7 @@ Path1
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -14650,16 +15226,16 @@ Path1
tC2Q |
FF |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-141.393 |
-0.376 |
+141.384 |
+0.368 |
tNET |
FF |
1 |
-R41C26[1][A] |
+R44C21[0][A] |
gw_gao_inst_0/u_ao_top/capture_end_tck_0_s0/CLEAR |
@@ -14734,7 +15310,7 @@ Path1
tNET |
RR |
1 |
-R41C26[1][A] |
+R44C21[0][A] |
gw_gao_inst_0/u_ao_top/capture_end_tck_0_s0/CLK |
@@ -14752,7 +15328,7 @@ Path1
tSu |
|
1 |
-R41C26[1][A] |
+R44C21[0][A] |
gw_gao_inst_0/u_ao_top/capture_end_tck_0_s0 |
@@ -14776,7 +15352,7 @@ Path1
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.376, 65.304%; tC2Q: 0.200, 34.696% |
+cell: 0.000, 0.000%; route: 0.368, 64.776%; tC2Q: 0.200, 35.224% |
Required Clock Path Delay |
@@ -14788,11 +15364,11 @@ Path2
Slack |
-10.390 |
+10.398 |
Data Arrival Time |
-141.393 |
+141.384 |
Data Required Time |
@@ -14858,7 +15434,7 @@ Path2
0.591 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -14868,7 +15444,7 @@ Path2
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -14877,16 +15453,16 @@ Path2
tC2Q |
FF |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-141.393 |
-0.376 |
+141.384 |
+0.368 |
tNET |
FF |
1 |
-R41C26[2][A] |
+R44C21[2][A] |
gw_gao_inst_0/u_ao_top/capture_end_tck_1_s0/CLEAR |
@@ -14961,7 +15537,7 @@ Path2
tNET |
RR |
1 |
-R41C26[2][A] |
+R44C21[2][A] |
gw_gao_inst_0/u_ao_top/capture_end_tck_1_s0/CLK |
@@ -14979,7 +15555,7 @@ Path2
tSu |
|
1 |
-R41C26[2][A] |
+R44C21[2][A] |
gw_gao_inst_0/u_ao_top/capture_end_tck_1_s0 |
@@ -15003,7 +15579,7 @@ Path2
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.376, 65.304%; tC2Q: 0.200, 34.696% |
+cell: 0.000, 0.000%; route: 0.368, 64.776%; tC2Q: 0.200, 35.224% |
Required Clock Path Delay |
@@ -15015,11 +15591,11 @@ Path3
Slack |
-10.390 |
+10.398 |
Data Arrival Time |
-141.393 |
+141.384 |
Data Required Time |
@@ -15085,7 +15661,7 @@ Path3
0.591 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -15095,7 +15671,7 @@ Path3
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -15104,16 +15680,16 @@ Path3
tC2Q |
FF |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-141.393 |
-0.376 |
+141.384 |
+0.368 |
tNET |
FF |
1 |
-R41C26[1][B] |
+R44C21[0][B] |
gw_gao_inst_0/u_ao_top/capture_end_tck_2_s0/CLEAR |
@@ -15188,7 +15764,7 @@ Path3
tNET |
RR |
1 |
-R41C26[1][B] |
+R44C21[0][B] |
gw_gao_inst_0/u_ao_top/capture_end_tck_2_s0/CLK |
@@ -15206,7 +15782,7 @@ Path3
tSu |
|
1 |
-R41C26[1][B] |
+R44C21[0][B] |
gw_gao_inst_0/u_ao_top/capture_end_tck_2_s0 |
@@ -15230,7 +15806,7 @@ Path3
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.376, 65.304%; tC2Q: 0.200, 34.696% |
+cell: 0.000, 0.000%; route: 0.368, 64.776%; tC2Q: 0.200, 35.224% |
Required Clock Path Delay |
@@ -15242,11 +15818,11 @@ Path4
Slack |
-18.968 |
+18.998 |
Data Arrival Time |
-21.799 |
+21.769 |
Data Required Time |
@@ -15258,7 +15834,7 @@ Path4
To |
-gw_gao_inst_0/u_ao_top/internal_reg_start_syn_0_s0 |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_1_s5 |
Launch Clk |
@@ -15312,7 +15888,7 @@ Path4
0.591 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -15322,7 +15898,7 @@ Path4
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -15331,17 +15907,17 @@ Path4
tC2Q |
FF |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-21.799 |
-0.782 |
+21.769 |
+0.752 |
tNET |
FF |
1 |
-R43C27[0][B] |
-gw_gao_inst_0/u_ao_top/internal_reg_start_syn_0_s0/CLEAR |
+R39C19[1][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_1_s5/CLEAR |
Data Required Path:
@@ -15387,7 +15963,7 @@ Path4
0.587 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -15397,8 +15973,8 @@ Path4
tNET |
RR |
1 |
-R43C27[0][B] |
-gw_gao_inst_0/u_ao_top/internal_reg_start_syn_0_s0/CLK |
+R39C19[1][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_1_s5/CLK |
40.767 |
@@ -15406,8 +15982,8 @@ Path4
tSu |
|
1 |
-R43C27[0][B] |
-gw_gao_inst_0/u_ao_top/internal_reg_start_syn_0_s0 |
+R39C19[1][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_1_s5 |
Path Statistics:
@@ -15430,7 +16006,7 @@ Path4
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.782, 79.637%; tC2Q: 0.200, 20.363% |
+cell: 0.000, 0.000%; route: 0.752, 78.998%; tC2Q: 0.200, 21.002% |
Required Clock Path Delay |
@@ -15442,11 +16018,11 @@ Path5
Slack |
-18.968 |
+18.998 |
Data Arrival Time |
-21.799 |
+21.769 |
Data Required Time |
@@ -15458,7 +16034,7 @@ Path5
To |
-gw_gao_inst_0/u_ao_top/internal_reg_start_syn_1_s0 |
+gw_gao_inst_0/u_ao_top/capture_end_dly_s0 |
Launch Clk |
@@ -15512,7 +16088,7 @@ Path5
0.591 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -15522,7 +16098,7 @@ Path5
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -15531,17 +16107,17 @@ Path5
tC2Q |
FF |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-21.799 |
-0.782 |
+21.769 |
+0.752 |
tNET |
FF |
1 |
-R43C27[0][A] |
-gw_gao_inst_0/u_ao_top/internal_reg_start_syn_1_s0/CLEAR |
+R39C19[0][A] |
+gw_gao_inst_0/u_ao_top/capture_end_dly_s0/PRESET |
Data Required Path:
@@ -15587,7 +16163,7 @@ Path5
0.587 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -15597,8 +16173,8 @@ Path5
tNET |
RR |
1 |
-R43C27[0][A] |
-gw_gao_inst_0/u_ao_top/internal_reg_start_syn_1_s0/CLK |
+R39C19[0][A] |
+gw_gao_inst_0/u_ao_top/capture_end_dly_s0/CLK |
40.767 |
@@ -15606,8 +16182,8 @@ Path5
tSu |
|
1 |
-R43C27[0][A] |
-gw_gao_inst_0/u_ao_top/internal_reg_start_syn_1_s0 |
+R39C19[0][A] |
+gw_gao_inst_0/u_ao_top/capture_end_dly_s0 |
Path Statistics:
@@ -15630,7 +16206,7 @@ Path5
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.782, 79.637%; tC2Q: 0.200, 20.363% |
+cell: 0.000, 0.000%; route: 0.752, 78.998%; tC2Q: 0.200, 21.002% |
Required Clock Path Delay |
@@ -15642,11 +16218,11 @@ Path6
Slack |
-19.033 |
+19.051 |
Data Arrival Time |
-21.733 |
+21.715 |
Data Required Time |
@@ -15658,7 +16234,7 @@ Path6
To |
-gw_gao_inst_0/u_ao_top/capture_start_sel_s1 |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_0_s5 |
Launch Clk |
@@ -15712,7 +16288,7 @@ Path6
0.591 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -15722,7 +16298,7 @@ Path6
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -15731,17 +16307,17 @@ Path6
tC2Q |
FF |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-21.733 |
-0.717 |
+21.715 |
+0.699 |
tNET |
FF |
1 |
-R43C26[2][A] |
-gw_gao_inst_0/u_ao_top/capture_start_sel_s1/CLEAR |
+R40C25[1][B] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLEAR |
Data Required Path:
@@ -15787,7 +16363,7 @@ Path6
0.587 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -15797,8 +16373,8 @@ Path6
tNET |
RR |
1 |
-R43C26[2][A] |
-gw_gao_inst_0/u_ao_top/capture_start_sel_s1/CLK |
+R40C25[1][B] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLK |
40.767 |
@@ -15806,8 +16382,8 @@ Path6
tSu |
|
1 |
-R43C26[2][A] |
-gw_gao_inst_0/u_ao_top/capture_start_sel_s1 |
+R40C25[1][B] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_0_s5 |
Path Statistics:
@@ -15830,7 +16406,7 @@ Path6
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.717, 78.182%; tC2Q: 0.200, 21.818% |
+cell: 0.000, 0.000%; route: 0.699, 77.751%; tC2Q: 0.200, 22.249% |
Required Clock Path Delay |
@@ -15842,11 +16418,11 @@ Path7
Slack |
-19.033 |
+19.051 |
Data Arrival Time |
-21.733 |
+21.715 |
Data Required Time |
@@ -15858,7 +16434,7 @@ Path7
To |
-gw_gao_inst_0/u_ao_top/capture_end_dly_s0 |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_12_s6 |
Launch Clk |
@@ -15912,7 +16488,7 @@ Path7
0.591 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -15922,7 +16498,7 @@ Path7
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -15931,17 +16507,17 @@ Path7
tC2Q |
FF |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-21.733 |
-0.717 |
+21.715 |
+0.699 |
tNET |
FF |
1 |
-R43C26[0][B] |
-gw_gao_inst_0/u_ao_top/capture_end_dly_s0/PRESET |
+R40C25[1][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_12_s6/CLEAR |
Data Required Path:
@@ -15987,7 +16563,7 @@ Path7
0.587 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -15997,8 +16573,8 @@ Path7
tNET |
RR |
1 |
-R43C26[0][B] |
-gw_gao_inst_0/u_ao_top/capture_end_dly_s0/CLK |
+R40C25[1][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_12_s6/CLK |
40.767 |
@@ -16006,8 +16582,8 @@ Path7
tSu |
|
1 |
-R43C26[0][B] |
-gw_gao_inst_0/u_ao_top/capture_end_dly_s0 |
+R40C25[1][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_12_s6 |
Path Statistics:
@@ -16030,7 +16606,7 @@ Path7
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.717, 78.182%; tC2Q: 0.200, 21.818% |
+cell: 0.000, 0.000%; route: 0.699, 77.751%; tC2Q: 0.200, 22.249% |
Required Clock Path Delay |
@@ -16042,11 +16618,11 @@ Path8
Slack |
-19.033 |
+19.132 |
Data Arrival Time |
-21.733 |
+21.635 |
Data Required Time |
@@ -16058,7 +16634,7 @@ Path8
To |
-gw_gao_inst_0/u_ao_top/internal_reg_start_dly_0_s0 |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_6_s5 |
Launch Clk |
@@ -16112,7 +16688,7 @@ Path8
0.591 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -16122,7 +16698,7 @@ Path8
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -16131,17 +16707,17 @@ Path8
tC2Q |
FF |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-21.733 |
-0.717 |
+21.635 |
+0.618 |
tNET |
FF |
1 |
-R43C26[0][A] |
-gw_gao_inst_0/u_ao_top/internal_reg_start_dly_0_s0/CLEAR |
+R39C21[2][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_6_s5/CLEAR |
Data Required Path:
@@ -16187,7 +16763,7 @@ Path8
0.587 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -16197,8 +16773,8 @@ Path8
tNET |
RR |
1 |
-R43C26[0][A] |
-gw_gao_inst_0/u_ao_top/internal_reg_start_dly_0_s0/CLK |
+R39C21[2][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_6_s5/CLK |
40.767 |
@@ -16206,8 +16782,8 @@ Path8
tSu |
|
1 |
-R43C26[0][A] |
-gw_gao_inst_0/u_ao_top/internal_reg_start_dly_0_s0 |
+R39C21[2][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_6_s5 |
Path Statistics:
@@ -16230,7 +16806,7 @@ Path8
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.717, 78.182%; tC2Q: 0.200, 21.818% |
+cell: 0.000, 0.000%; route: 0.618, 75.562%; tC2Q: 0.200, 24.438% |
Required Clock Path Delay |
@@ -16242,11 +16818,11 @@ Path9
Slack |
-19.376 |
+19.132 |
Data Arrival Time |
-21.390 |
+21.635 |
Data Required Time |
@@ -16258,7 +16834,7 @@ Path9
To |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_0_s5 |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
Launch Clk |
@@ -16312,7 +16888,7 @@ Path9
0.591 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -16322,7 +16898,7 @@ Path9
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -16331,17 +16907,17 @@ Path9
tC2Q |
FF |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-21.390 |
-0.374 |
+21.635 |
+0.618 |
tNET |
FF |
1 |
-R39C22[2][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLEAR |
+R39C21[1][B] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR |
Data Required Path:
@@ -16387,7 +16963,7 @@ Path9
0.587 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -16397,8 +16973,8 @@ Path9
tNET |
RR |
1 |
-R39C22[2][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLK |
+R39C21[1][B] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK |
40.767 |
@@ -16406,8 +16982,8 @@ Path9
tSu |
|
1 |
-R39C22[2][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_0_s5 |
+R39C21[1][B] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
Path Statistics:
@@ -16430,7 +17006,7 @@ Path9
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.374, 65.131%; tC2Q: 0.200, 34.869% |
+cell: 0.000, 0.000%; route: 0.618, 75.562%; tC2Q: 0.200, 24.438% |
Required Clock Path Delay |
@@ -16442,11 +17018,11 @@ Path10
Slack |
-19.376 |
+19.132 |
Data Arrival Time |
-21.390 |
+21.635 |
Data Required Time |
@@ -16458,7 +17034,7 @@ Path10
To |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_1_s5 |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
Launch Clk |
@@ -16512,7 +17088,7 @@ Path10
0.591 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -16522,7 +17098,7 @@ Path10
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -16531,17 +17107,17 @@ Path10
tC2Q |
FF |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-21.390 |
-0.374 |
+21.635 |
+0.618 |
tNET |
FF |
1 |
-R39C23[1][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_1_s5/CLEAR |
+R39C21[0][B] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR |
Data Required Path:
@@ -16587,7 +17163,7 @@ Path10
0.587 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -16597,8 +17173,8 @@ Path10
tNET |
RR |
1 |
-R39C23[1][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_1_s5/CLK |
+R39C21[0][B] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK |
40.767 |
@@ -16606,8 +17182,8 @@ Path10
tSu |
|
1 |
-R39C23[1][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_1_s5 |
+R39C21[0][B] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
Path Statistics:
@@ -16630,7 +17206,7 @@ Path10
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.374, 65.131%; tC2Q: 0.200, 34.869% |
+cell: 0.000, 0.000%; route: 0.618, 75.562%; tC2Q: 0.200, 24.438% |
Required Clock Path Delay |
@@ -16642,11 +17218,11 @@ Path11
Slack |
-19.376 |
+19.132 |
Data Arrival Time |
-21.390 |
+21.635 |
Data Required Time |
@@ -16658,7 +17234,7 @@ Path11
To |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_4_s5 |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_11_s1 |
Launch Clk |
@@ -16712,7 +17288,7 @@ Path11
0.591 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -16722,7 +17298,7 @@ Path11
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -16731,17 +17307,17 @@ Path11
tC2Q |
FF |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-21.390 |
-0.374 |
+21.635 |
+0.618 |
tNET |
FF |
1 |
-R39C23[1][B] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_4_s5/CLEAR |
+R39C21[0][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_11_s1/CLEAR |
Data Required Path:
@@ -16787,7 +17363,7 @@ Path11
0.587 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -16797,8 +17373,8 @@ Path11
tNET |
RR |
1 |
-R39C23[1][B] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_4_s5/CLK |
+R39C21[0][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_11_s1/CLK |
40.767 |
@@ -16806,8 +17382,8 @@ Path11
tSu |
|
1 |
-R39C23[1][B] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_4_s5 |
+R39C21[0][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_11_s1 |
Path Statistics:
@@ -16830,7 +17406,7 @@ Path11
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.374, 65.131%; tC2Q: 0.200, 34.869% |
+cell: 0.000, 0.000%; route: 0.618, 75.562%; tC2Q: 0.200, 24.438% |
Required Clock Path Delay |
@@ -16842,11 +17418,11 @@ Path12
Slack |
-19.376 |
+19.137 |
Data Arrival Time |
-21.390 |
+21.630 |
Data Required Time |
@@ -16858,7 +17434,7 @@ Path12
To |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_6_s5 |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_7_s5 |
Launch Clk |
@@ -16912,7 +17488,7 @@ Path12
0.591 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -16922,7 +17498,7 @@ Path12
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -16931,17 +17507,17 @@ Path12
tC2Q |
FF |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-21.390 |
-0.374 |
+21.630 |
+0.613 |
tNET |
FF |
1 |
-R39C22[0][B] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_6_s5/CLEAR |
+R39C22[0][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_7_s5/CLEAR |
Data Required Path:
@@ -16987,7 +17563,7 @@ Path12
0.587 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -16997,8 +17573,8 @@ Path12
tNET |
RR |
1 |
-R39C22[0][B] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_6_s5/CLK |
+R39C22[0][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_7_s5/CLK |
40.767 |
@@ -17006,8 +17582,8 @@ Path12
tSu |
|
1 |
-R39C22[0][B] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_6_s5 |
+R39C22[0][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_7_s5 |
Path Statistics:
@@ -17030,7 +17606,7 @@ Path12
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.374, 65.131%; tC2Q: 0.200, 34.869% |
+cell: 0.000, 0.000%; route: 0.613, 75.414%; tC2Q: 0.200, 24.586% |
Required Clock Path Delay |
@@ -17042,11 +17618,11 @@ Path13
Slack |
-19.376 |
+19.137 |
Data Arrival Time |
-21.390 |
+21.630 |
Data Required Time |
@@ -17058,7 +17634,7 @@ Path13
To |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_7_s5 |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_9_s5 |
Launch Clk |
@@ -17112,7 +17688,7 @@ Path13
0.591 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -17122,7 +17698,7 @@ Path13
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -17131,17 +17707,17 @@ Path13
tC2Q |
FF |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-21.390 |
-0.374 |
+21.630 |
+0.613 |
tNET |
FF |
1 |
-R39C25[0][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_7_s5/CLEAR |
+R39C22[1][B] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_9_s5/CLEAR |
Data Required Path:
@@ -17187,7 +17763,7 @@ Path13
0.587 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -17197,8 +17773,8 @@ Path13
tNET |
RR |
1 |
-R39C25[0][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_7_s5/CLK |
+R39C22[1][B] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_9_s5/CLK |
40.767 |
@@ -17206,8 +17782,8 @@ Path13
tSu |
|
1 |
-R39C25[0][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_7_s5 |
+R39C22[1][B] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_9_s5 |
Path Statistics:
@@ -17230,7 +17806,7 @@ Path13
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.374, 65.131%; tC2Q: 0.200, 34.869% |
+cell: 0.000, 0.000%; route: 0.613, 75.414%; tC2Q: 0.200, 24.586% |
Required Clock Path Delay |
@@ -17242,11 +17818,11 @@ Path14
Slack |
-19.376 |
+19.137 |
Data Arrival Time |
-21.390 |
+21.630 |
Data Required Time |
@@ -17312,7 +17888,7 @@ Path14
0.591 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -17322,7 +17898,7 @@ Path14
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -17331,16 +17907,16 @@ Path14
tC2Q |
FF |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-21.390 |
-0.374 |
+21.630 |
+0.613 |
tNET |
FF |
1 |
-R39C23[0][A] |
+R39C22[0][B] |
gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_10_s5/CLEAR |
@@ -17387,7 +17963,7 @@ Path14
0.587 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -17397,7 +17973,7 @@ Path14
tNET |
RR |
1 |
-R39C23[0][A] |
+R39C22[0][B] |
gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_10_s5/CLK |
@@ -17406,7 +17982,7 @@ Path14
tSu |
|
1 |
-R39C23[0][A] |
+R39C22[0][B] |
gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_10_s5 |
@@ -17430,7 +18006,7 @@ Path14
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.374, 65.131%; tC2Q: 0.200, 34.869% |
+cell: 0.000, 0.000%; route: 0.613, 75.414%; tC2Q: 0.200, 24.586% |
Required Clock Path Delay |
@@ -17442,11 +18018,11 @@ Path15
Slack |
-19.376 |
+19.158 |
Data Arrival Time |
-21.390 |
+21.609 |
Data Required Time |
@@ -17458,7 +18034,7 @@ Path15
To |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_4_s5 |
Launch Clk |
@@ -17512,7 +18088,7 @@ Path15
0.591 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -17522,7 +18098,7 @@ Path15
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -17531,17 +18107,17 @@ Path15
tC2Q |
FF |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-21.390 |
-0.374 |
+21.609 |
+0.592 |
tNET |
FF |
1 |
-R39C22[1][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR |
+R39C20[1][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_4_s5/CLEAR |
Data Required Path:
@@ -17587,7 +18163,7 @@ Path15
0.587 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -17597,8 +18173,8 @@ Path15
tNET |
RR |
1 |
-R39C22[1][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK |
+R39C20[1][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_4_s5/CLK |
40.767 |
@@ -17606,8 +18182,8 @@ Path15
tSu |
|
1 |
-R39C22[1][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
+R39C20[1][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_4_s5 |
Path Statistics:
@@ -17630,7 +18206,7 @@ Path15
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.374, 65.131%; tC2Q: 0.200, 34.869% |
+cell: 0.000, 0.000%; route: 0.592, 74.749%; tC2Q: 0.200, 25.251% |
Required Clock Path Delay |
@@ -17642,11 +18218,11 @@ Path16
Slack |
-19.376 |
+19.173 |
Data Arrival Time |
-21.390 |
+21.594 |
Data Required Time |
@@ -17658,7 +18234,7 @@ Path16
To |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_11_s1 |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
Launch Clk |
@@ -17712,7 +18288,7 @@ Path16
0.591 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -17722,7 +18298,7 @@ Path16
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -17731,17 +18307,17 @@ Path16
tC2Q |
FF |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-21.390 |
-0.374 |
+21.594 |
+0.577 |
tNET |
FF |
1 |
-R39C23[2][B] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_11_s1/CLEAR |
+R40C20[0][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR |
Data Required Path:
@@ -17787,7 +18363,7 @@ Path16
0.587 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -17797,8 +18373,8 @@ Path16
tNET |
RR |
1 |
-R39C23[2][B] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_11_s1/CLK |
+R40C20[0][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK |
40.767 |
@@ -17806,8 +18382,8 @@ Path16
tSu |
|
1 |
-R39C23[2][B] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_11_s1 |
+R40C20[0][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
Path Statistics:
@@ -17830,7 +18406,7 @@ Path16
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.374, 65.131%; tC2Q: 0.200, 34.869% |
+cell: 0.000, 0.000%; route: 0.577, 74.262%; tC2Q: 0.200, 25.738% |
Required Clock Path Delay |
@@ -17842,11 +18418,11 @@ Path17
Slack |
-19.376 |
+19.173 |
Data Arrival Time |
-21.390 |
+21.594 |
Data Required Time |
@@ -17858,7 +18434,7 @@ Path17
To |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_12_s1 |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
Launch Clk |
@@ -17912,7 +18488,7 @@ Path17
0.591 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -17922,7 +18498,7 @@ Path17
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -17931,17 +18507,17 @@ Path17
tC2Q |
FF |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-21.390 |
-0.374 |
+21.594 |
+0.577 |
tNET |
FF |
1 |
-R39C23[2][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_12_s1/CLEAR |
+R40C20[2][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR |
Data Required Path:
@@ -17987,7 +18563,7 @@ Path17
0.587 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -17997,8 +18573,8 @@ Path17
tNET |
RR |
1 |
-R39C23[2][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_12_s1/CLK |
+R40C20[2][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK |
40.767 |
@@ -18006,8 +18582,8 @@ Path17
tSu |
|
1 |
-R39C23[2][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_12_s1 |
+R40C20[2][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
Path Statistics:
@@ -18030,7 +18606,7 @@ Path17
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.374, 65.131%; tC2Q: 0.200, 34.869% |
+cell: 0.000, 0.000%; route: 0.577, 74.262%; tC2Q: 0.200, 25.738% |
Required Clock Path Delay |
@@ -18042,11 +18618,11 @@ Path18
Slack |
-19.376 |
+19.275 |
Data Arrival Time |
-21.390 |
+21.492 |
Data Required Time |
@@ -18058,7 +18634,7 @@ Path18
To |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_loop_s1 |
Launch Clk |
@@ -18112,7 +18688,7 @@ Path18
0.591 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -18122,7 +18698,7 @@ Path18
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -18131,17 +18707,17 @@ Path18
tC2Q |
FF |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-21.390 |
-0.374 |
+21.492 |
+0.475 |
tNET |
FF |
1 |
-R39C25[2][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR |
+R40C21[0][B] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR |
Data Required Path:
@@ -18187,7 +18763,7 @@ Path18
0.587 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -18197,8 +18773,8 @@ Path18
tNET |
RR |
1 |
-R39C25[2][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
+R40C21[0][B] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_loop_s1/CLK |
40.767 |
@@ -18206,8 +18782,8 @@ Path18
tSu |
|
1 |
-R39C25[2][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
+R40C21[0][B] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_loop_s1 |
Path Statistics:
@@ -18230,7 +18806,7 @@ Path18
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.374, 65.131%; tC2Q: 0.200, 34.869% |
+cell: 0.000, 0.000%; route: 0.475, 70.382%; tC2Q: 0.200, 29.618% |
Required Clock Path Delay |
@@ -18242,11 +18818,11 @@ Path19
Slack |
-19.376 |
+19.275 |
Data Arrival Time |
-21.390 |
+21.492 |
Data Required Time |
@@ -18258,7 +18834,7 @@ Path19
To |
-gw_gao_inst_0/u_ao_top/trigger_seq_start_s1 |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 |
Launch Clk |
@@ -18312,7 +18888,7 @@ Path19
0.591 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -18322,7 +18898,7 @@ Path19
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -18331,17 +18907,17 @@ Path19
tC2Q |
FF |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-21.390 |
-0.374 |
+21.492 |
+0.475 |
tNET |
FF |
1 |
-R39C25[1][B] |
-gw_gao_inst_0/u_ao_top/trigger_seq_start_s1/CLEAR |
+R40C21[1][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR |
Data Required Path:
@@ -18387,7 +18963,7 @@ Path19
0.587 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -18397,8 +18973,8 @@ Path19
tNET |
RR |
1 |
-R39C25[1][B] |
-gw_gao_inst_0/u_ao_top/trigger_seq_start_s1/CLK |
+R40C21[1][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK |
40.767 |
@@ -18406,8 +18982,8 @@ Path19
tSu |
|
1 |
-R39C25[1][B] |
-gw_gao_inst_0/u_ao_top/trigger_seq_start_s1 |
+R40C21[1][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 |
Path Statistics:
@@ -18430,7 +19006,7 @@ Path19
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.374, 65.131%; tC2Q: 0.200, 34.869% |
+cell: 0.000, 0.000%; route: 0.475, 70.382%; tC2Q: 0.200, 29.618% |
Required Clock Path Delay |
@@ -18442,11 +19018,11 @@ Path20
Slack |
-19.376 |
+19.275 |
Data Arrival Time |
-21.390 |
+21.492 |
Data Required Time |
@@ -18458,7 +19034,7 @@ Path20
To |
-gw_gao_inst_0/u_ao_top/internal_reg_start_dly_1_s0 |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
Launch Clk |
@@ -18512,7 +19088,7 @@ Path20
0.591 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -18522,7 +19098,7 @@ Path20
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -18531,17 +19107,17 @@ Path20
tC2Q |
FF |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-21.390 |
-0.374 |
+21.492 |
+0.475 |
tNET |
FF |
1 |
-R39C25[0][B] |
-gw_gao_inst_0/u_ao_top/internal_reg_start_dly_1_s0/CLEAR |
+R40C21[2][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR |
Data Required Path:
@@ -18587,7 +19163,7 @@ Path20
0.587 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -18597,8 +19173,8 @@ Path20
tNET |
RR |
1 |
-R39C25[0][B] |
-gw_gao_inst_0/u_ao_top/internal_reg_start_dly_1_s0/CLK |
+R40C21[2][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
40.767 |
@@ -18606,8 +19182,8 @@ Path20
tSu |
|
1 |
-R39C25[0][B] |
-gw_gao_inst_0/u_ao_top/internal_reg_start_dly_1_s0 |
+R40C21[2][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
Path Statistics:
@@ -18630,7 +19206,7 @@ Path20
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.374, 65.131%; tC2Q: 0.200, 34.869% |
+cell: 0.000, 0.000%; route: 0.475, 70.382%; tC2Q: 0.200, 29.618% |
Required Clock Path Delay |
@@ -18642,11 +19218,11 @@ Path21
Slack |
-19.381 |
+19.280 |
Data Arrival Time |
-21.385 |
+21.487 |
Data Required Time |
@@ -18658,7 +19234,7 @@ Path21
To |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_3_s5 |
+gw_gao_inst_0/u_ao_top/trigger_seq_start_s1 |
Launch Clk |
@@ -18712,7 +19288,7 @@ Path21
0.591 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -18722,7 +19298,7 @@ Path21
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -18731,17 +19307,17 @@ Path21
tC2Q |
FF |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-21.385 |
-0.369 |
+21.487 |
+0.470 |
tNET |
FF |
1 |
-R39C26[0][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_3_s5/CLEAR |
+R40C22[1][A] |
+gw_gao_inst_0/u_ao_top/trigger_seq_start_s1/CLEAR |
Data Required Path:
@@ -18787,7 +19363,7 @@ Path21
0.587 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -18797,8 +19373,8 @@ Path21
tNET |
RR |
1 |
-R39C26[0][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_3_s5/CLK |
+R40C22[1][A] |
+gw_gao_inst_0/u_ao_top/trigger_seq_start_s1/CLK |
40.767 |
@@ -18806,8 +19382,8 @@ Path21
tSu |
|
1 |
-R39C26[0][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_3_s5 |
+R40C22[1][A] |
+gw_gao_inst_0/u_ao_top/trigger_seq_start_s1 |
Path Statistics:
@@ -18830,7 +19406,7 @@ Path21
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.369, 64.828%; tC2Q: 0.200, 35.172% |
+cell: 0.000, 0.000%; route: 0.470, 70.163%; tC2Q: 0.200, 29.837% |
Required Clock Path Delay |
@@ -18842,11 +19418,11 @@ Path22
Slack |
-19.381 |
+19.280 |
Data Arrival Time |
-21.385 |
+21.487 |
Data Required Time |
@@ -18858,7 +19434,7 @@ Path22
To |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_9_s5 |
+gw_gao_inst_0/u_ao_top/internal_reg_start_dly_0_s0 |
Launch Clk |
@@ -18912,7 +19488,7 @@ Path22
0.591 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -18922,7 +19498,7 @@ Path22
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -18931,17 +19507,17 @@ Path22
tC2Q |
FF |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-21.385 |
-0.369 |
+21.487 |
+0.470 |
tNET |
FF |
1 |
-R39C26[2][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_9_s5/CLEAR |
+R40C22[0][A] |
+gw_gao_inst_0/u_ao_top/internal_reg_start_dly_0_s0/CLEAR |
Data Required Path:
@@ -18987,7 +19563,7 @@ Path22
0.587 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -18997,8 +19573,8 @@ Path22
tNET |
RR |
1 |
-R39C26[2][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_9_s5/CLK |
+R40C22[0][A] |
+gw_gao_inst_0/u_ao_top/internal_reg_start_dly_0_s0/CLK |
40.767 |
@@ -19006,8 +19582,8 @@ Path22
tSu |
|
1 |
-R39C26[2][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_9_s5 |
+R40C22[0][A] |
+gw_gao_inst_0/u_ao_top/internal_reg_start_dly_0_s0 |
Path Statistics:
@@ -19030,7 +19606,7 @@ Path22
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.369, 64.828%; tC2Q: 0.200, 35.172% |
+cell: 0.000, 0.000%; route: 0.470, 70.163%; tC2Q: 0.200, 29.837% |
Required Clock Path Delay |
@@ -19042,11 +19618,11 @@ Path23
Slack |
-19.387 |
+19.280 |
Data Arrival Time |
-21.380 |
+21.487 |
Data Required Time |
@@ -19058,7 +19634,7 @@ Path23
To |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_loop_s1 |
+gw_gao_inst_0/u_ao_top/internal_reg_start_dly_1_s0 |
Launch Clk |
@@ -19112,7 +19688,7 @@ Path23
0.591 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -19122,7 +19698,7 @@ Path23
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -19131,17 +19707,17 @@ Path23
tC2Q |
FF |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-21.380 |
-0.363 |
+21.487 |
+0.470 |
tNET |
FF |
1 |
-R39C24[0][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR |
+R40C22[0][B] |
+gw_gao_inst_0/u_ao_top/internal_reg_start_dly_1_s0/CLEAR |
Data Required Path:
@@ -19187,7 +19763,7 @@ Path23
0.587 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -19197,8 +19773,8 @@ Path23
tNET |
RR |
1 |
-R39C24[0][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_loop_s1/CLK |
+R40C22[0][B] |
+gw_gao_inst_0/u_ao_top/internal_reg_start_dly_1_s0/CLK |
40.767 |
@@ -19206,8 +19782,8 @@ Path23
tSu |
|
1 |
-R39C24[0][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_loop_s1 |
+R40C22[0][B] |
+gw_gao_inst_0/u_ao_top/internal_reg_start_dly_1_s0 |
Path Statistics:
@@ -19230,7 +19806,7 @@ Path23
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.363, 64.493%; tC2Q: 0.200, 35.507% |
+cell: 0.000, 0.000%; route: 0.470, 70.163%; tC2Q: 0.200, 29.837% |
Required Clock Path Delay |
@@ -19242,11 +19818,11 @@ Path24
Slack |
-19.387 |
+19.389 |
Data Arrival Time |
-21.380 |
+21.378 |
Data Required Time |
@@ -19258,7 +19834,7 @@ Path24
To |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
+gw_gao_inst_0/u_ao_top/internal_reg_start_syn_0_s0 |
Launch Clk |
@@ -19312,7 +19888,7 @@ Path24
0.591 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -19322,7 +19898,7 @@ Path24
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -19331,17 +19907,17 @@ Path24
tC2Q |
FF |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-21.380 |
-0.363 |
+21.378 |
+0.361 |
tNET |
FF |
1 |
-R39C24[1][B] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR |
+R44C19[1][A] |
+gw_gao_inst_0/u_ao_top/internal_reg_start_syn_0_s0/CLEAR |
Data Required Path:
@@ -19387,7 +19963,7 @@ Path24
0.587 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -19397,8 +19973,8 @@ Path24
tNET |
RR |
1 |
-R39C24[1][B] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK |
+R44C19[1][A] |
+gw_gao_inst_0/u_ao_top/internal_reg_start_syn_0_s0/CLK |
40.767 |
@@ -19406,8 +19982,8 @@ Path24
tSu |
|
1 |
-R39C24[1][B] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
+R44C19[1][A] |
+gw_gao_inst_0/u_ao_top/internal_reg_start_syn_0_s0 |
Path Statistics:
@@ -19430,7 +20006,7 @@ Path24
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.363, 64.493%; tC2Q: 0.200, 35.507% |
+cell: 0.000, 0.000%; route: 0.361, 64.352%; tC2Q: 0.200, 35.648% |
Required Clock Path Delay |
@@ -19442,11 +20018,11 @@ Path25
Slack |
-19.387 |
+19.389 |
Data Arrival Time |
-21.380 |
+21.378 |
Data Required Time |
@@ -19458,7 +20034,7 @@ Path25
To |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
+gw_gao_inst_0/u_ao_top/internal_reg_start_syn_1_s0 |
Launch Clk |
@@ -19512,7 +20088,7 @@ Path25
0.591 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -19522,7 +20098,7 @@ Path25
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -19531,17 +20107,17 @@ Path25
tC2Q |
FF |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-21.380 |
-0.363 |
+21.378 |
+0.361 |
tNET |
FF |
1 |
-R39C24[0][B] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR |
+R44C19[1][B] |
+gw_gao_inst_0/u_ao_top/internal_reg_start_syn_1_s0/CLEAR |
Data Required Path:
@@ -19587,7 +20163,7 @@ Path25
0.587 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -19597,8 +20173,8 @@ Path25
tNET |
RR |
1 |
-R39C24[0][B] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK |
+R44C19[1][B] |
+gw_gao_inst_0/u_ao_top/internal_reg_start_syn_1_s0/CLK |
40.767 |
@@ -19606,8 +20182,8 @@ Path25
tSu |
|
1 |
-R39C24[0][B] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
+R44C19[1][B] |
+gw_gao_inst_0/u_ao_top/internal_reg_start_syn_1_s0 |
Path Statistics:
@@ -19630,7 +20206,7 @@ Path25
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.363, 64.493%; tC2Q: 0.200, 35.507% |
+cell: 0.000, 0.000%; route: 0.361, 64.352%; tC2Q: 0.200, 35.648% |
Required Clock Path Delay |
@@ -19644,11 +20220,11 @@ Path1
Slack |
--0.538 |
+-0.543 |
Data Arrival Time |
-101.156 |
+101.151 |
Data Required Time |
@@ -19714,7 +20290,7 @@ Path1
0.583 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -19724,7 +20300,7 @@ Path1
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -19733,16 +20309,16 @@ Path1
tC2Q |
FR |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-101.156 |
-0.231 |
+101.151 |
+0.226 |
tNET |
RR |
1 |
-R41C26[1][A] |
+R44C21[0][A] |
gw_gao_inst_0/u_ao_top/capture_end_tck_0_s0/CLEAR |
@@ -19817,7 +20393,7 @@ Path1
tNET |
RR |
1 |
-R41C26[1][A] |
+R44C21[0][A] |
gw_gao_inst_0/u_ao_top/capture_end_tck_0_s0/CLK |
@@ -19835,7 +20411,7 @@ Path1
tHld |
|
1 |
-R41C26[1][A] |
+R44C21[0][A] |
gw_gao_inst_0/u_ao_top/capture_end_tck_0_s0 |
@@ -19859,7 +20435,7 @@ Path1
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.231, 57.042%; tC2Q: 0.174, 42.958% |
+cell: 0.000, 0.000%; route: 0.226, 56.533%; tC2Q: 0.174, 43.467% |
Required Clock Path Delay |
@@ -19871,11 +20447,11 @@ Path2
Slack |
--0.538 |
+-0.543 |
Data Arrival Time |
-101.156 |
+101.151 |
Data Required Time |
@@ -19941,7 +20517,7 @@ Path2
0.583 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -19951,7 +20527,7 @@ Path2
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -19960,16 +20536,16 @@ Path2
tC2Q |
FR |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-101.156 |
-0.231 |
+101.151 |
+0.226 |
tNET |
RR |
1 |
-R41C26[2][A] |
+R44C21[2][A] |
gw_gao_inst_0/u_ao_top/capture_end_tck_1_s0/CLEAR |
@@ -20044,7 +20620,7 @@ Path2
tNET |
RR |
1 |
-R41C26[2][A] |
+R44C21[2][A] |
gw_gao_inst_0/u_ao_top/capture_end_tck_1_s0/CLK |
@@ -20062,7 +20638,7 @@ Path2
tHld |
|
1 |
-R41C26[2][A] |
+R44C21[2][A] |
gw_gao_inst_0/u_ao_top/capture_end_tck_1_s0 |
@@ -20086,7 +20662,7 @@ Path2
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.231, 57.042%; tC2Q: 0.174, 42.958% |
+cell: 0.000, 0.000%; route: 0.226, 56.533%; tC2Q: 0.174, 43.467% |
Required Clock Path Delay |
@@ -20098,11 +20674,11 @@ Path3
Slack |
--0.538 |
+-0.543 |
Data Arrival Time |
-101.156 |
+101.151 |
Data Required Time |
@@ -20168,7 +20744,7 @@ Path3
0.583 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -20178,7 +20754,7 @@ Path3
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -20187,16 +20763,16 @@ Path3
tC2Q |
FR |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-101.156 |
-0.231 |
+101.151 |
+0.226 |
tNET |
RR |
1 |
-R41C26[1][B] |
+R44C21[0][B] |
gw_gao_inst_0/u_ao_top/capture_end_tck_2_s0/CLEAR |
@@ -20271,7 +20847,7 @@ Path3
tNET |
RR |
1 |
-R41C26[1][B] |
+R44C21[0][B] |
gw_gao_inst_0/u_ao_top/capture_end_tck_2_s0/CLK |
@@ -20289,7 +20865,7 @@ Path3
tHld |
|
1 |
-R41C26[1][B] |
+R44C21[0][B] |
gw_gao_inst_0/u_ao_top/capture_end_tck_2_s0 |
@@ -20313,7 +20889,7 @@ Path3
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.231, 57.042%; tC2Q: 0.174, 42.958% |
+cell: 0.000, 0.000%; route: 0.226, 56.533%; tC2Q: 0.174, 43.467% |
Required Clock Path Delay |
@@ -20325,11 +20901,11 @@ Path4
Slack |
-20.402 |
+20.292 |
Data Arrival Time |
-21.151 |
+21.041 |
Data Required Time |
@@ -20341,7 +20917,7 @@ Path4
To |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_loop_s1 |
+gw_gao_inst_0/u_ao_top/capture_start_sel_s1 |
Launch Clk |
@@ -20395,7 +20971,7 @@ Path4
0.583 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -20405,7 +20981,7 @@ Path4
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -20414,17 +20990,17 @@ Path4
tC2Q |
FR |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-21.151 |
-0.227 |
+21.041 |
+0.117 |
tNET |
RR |
1 |
-R39C24[0][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR |
+R44C20[2][A] |
+gw_gao_inst_0/u_ao_top/capture_start_sel_s1/CLEAR |
Data Required Path:
@@ -20470,7 +21046,7 @@ Path4
0.581 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -20480,8 +21056,8 @@ Path4
tNET |
RR |
1 |
-R39C24[0][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_loop_s1/CLK |
+R44C20[2][A] |
+gw_gao_inst_0/u_ao_top/capture_start_sel_s1/CLK |
0.749 |
@@ -20489,8 +21065,8 @@ Path4
tHld |
|
1 |
-R39C24[0][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_loop_s1 |
+R44C20[2][A] |
+gw_gao_inst_0/u_ao_top/capture_start_sel_s1 |
Path Statistics:
@@ -20513,7 +21089,7 @@ Path4
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.227, 56.540%; tC2Q: 0.174, 43.460% |
+cell: 0.000, 0.000%; route: 0.117, 40.192%; tC2Q: 0.174, 59.808% |
Required Clock Path Delay |
@@ -20525,11 +21101,11 @@ Path5
Slack |
-20.402 |
+20.397 |
Data Arrival Time |
-21.151 |
+21.147 |
Data Required Time |
@@ -20541,7 +21117,7 @@ Path5
To |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
+gw_gao_inst_0/u_ao_top/internal_reg_start_syn_0_s0 |
Launch Clk |
@@ -20595,7 +21171,7 @@ Path5
0.583 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -20605,7 +21181,7 @@ Path5
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -20614,17 +21190,17 @@ Path5
tC2Q |
FR |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-21.151 |
-0.227 |
+21.147 |
+0.222 |
tNET |
RR |
1 |
-R39C24[1][B] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR |
+R44C19[1][A] |
+gw_gao_inst_0/u_ao_top/internal_reg_start_syn_0_s0/CLEAR |
Data Required Path:
@@ -20670,7 +21246,7 @@ Path5
0.581 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -20680,8 +21256,8 @@ Path5
tNET |
RR |
1 |
-R39C24[1][B] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK |
+R44C19[1][A] |
+gw_gao_inst_0/u_ao_top/internal_reg_start_syn_0_s0/CLK |
0.749 |
@@ -20689,8 +21265,8 @@ Path5
tHld |
|
1 |
-R39C24[1][B] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
+R44C19[1][A] |
+gw_gao_inst_0/u_ao_top/internal_reg_start_syn_0_s0 |
Path Statistics:
@@ -20713,7 +21289,7 @@ Path5
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.227, 56.540%; tC2Q: 0.174, 43.460% |
+cell: 0.000, 0.000%; route: 0.222, 56.063%; tC2Q: 0.174, 43.937% |
Required Clock Path Delay |
@@ -20725,11 +21301,11 @@ Path6
Slack |
-20.402 |
+20.397 |
Data Arrival Time |
-21.151 |
+21.147 |
Data Required Time |
@@ -20741,7 +21317,7 @@ Path6
To |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
+gw_gao_inst_0/u_ao_top/internal_reg_start_syn_1_s0 |
Launch Clk |
@@ -20795,7 +21371,7 @@ Path6
0.583 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -20805,7 +21381,7 @@ Path6
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -20814,17 +21390,17 @@ Path6
tC2Q |
FR |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-21.151 |
-0.227 |
+21.147 |
+0.222 |
tNET |
RR |
1 |
-R39C24[0][B] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR |
+R44C19[1][B] |
+gw_gao_inst_0/u_ao_top/internal_reg_start_syn_1_s0/CLEAR |
Data Required Path:
@@ -20870,7 +21446,7 @@ Path6
0.581 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -20880,8 +21456,8 @@ Path6
tNET |
RR |
1 |
-R39C24[0][B] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK |
+R44C19[1][B] |
+gw_gao_inst_0/u_ao_top/internal_reg_start_syn_1_s0/CLK |
0.749 |
@@ -20889,8 +21465,8 @@ Path6
tHld |
|
1 |
-R39C24[0][B] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
+R44C19[1][B] |
+gw_gao_inst_0/u_ao_top/internal_reg_start_syn_1_s0 |
Path Statistics:
@@ -20913,7 +21489,7 @@ Path6
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.227, 56.540%; tC2Q: 0.174, 43.460% |
+cell: 0.000, 0.000%; route: 0.222, 56.063%; tC2Q: 0.174, 43.937% |
Required Clock Path Delay |
@@ -20925,11 +21501,11 @@ Path7
Slack |
-20.402 |
+20.420 |
Data Arrival Time |
-21.151 |
+21.169 |
Data Required Time |
@@ -20941,7 +21517,7 @@ Path7
To |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 |
+gw_gao_inst_0/u_ao_top/trigger_seq_start_s1 |
Launch Clk |
@@ -20995,7 +21571,7 @@ Path7
0.583 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -21005,7 +21581,7 @@ Path7
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -21014,17 +21590,17 @@ Path7
tC2Q |
FR |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-21.151 |
-0.227 |
+21.169 |
+0.245 |
tNET |
RR |
1 |
-R39C24[2][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR |
+R40C22[1][A] |
+gw_gao_inst_0/u_ao_top/trigger_seq_start_s1/CLEAR |
Data Required Path:
@@ -21070,7 +21646,7 @@ Path7
0.581 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -21080,8 +21656,8 @@ Path7
tNET |
RR |
1 |
-R39C24[2][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK |
+R40C22[1][A] |
+gw_gao_inst_0/u_ao_top/trigger_seq_start_s1/CLK |
0.749 |
@@ -21089,8 +21665,8 @@ Path7
tHld |
|
1 |
-R39C24[2][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 |
+R40C22[1][A] |
+gw_gao_inst_0/u_ao_top/trigger_seq_start_s1 |
Path Statistics:
@@ -21113,7 +21689,7 @@ Path7
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.227, 56.540%; tC2Q: 0.174, 43.460% |
+cell: 0.000, 0.000%; route: 0.245, 58.439%; tC2Q: 0.174, 41.561% |
Required Clock Path Delay |
@@ -21125,11 +21701,11 @@ Path8
Slack |
-20.405 |
+20.420 |
Data Arrival Time |
-21.155 |
+21.169 |
Data Required Time |
@@ -21141,7 +21717,7 @@ Path8
To |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_3_s5 |
+gw_gao_inst_0/u_ao_top/internal_reg_start_dly_0_s0 |
Launch Clk |
@@ -21195,7 +21771,7 @@ Path8
0.583 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -21205,7 +21781,7 @@ Path8
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -21214,17 +21790,17 @@ Path8
tC2Q |
FR |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-21.155 |
-0.230 |
+21.169 |
+0.245 |
tNET |
RR |
1 |
-R39C26[0][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_3_s5/CLEAR |
+R40C22[0][A] |
+gw_gao_inst_0/u_ao_top/internal_reg_start_dly_0_s0/CLEAR |
Data Required Path:
@@ -21270,7 +21846,7 @@ Path8
0.581 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -21280,8 +21856,8 @@ Path8
tNET |
RR |
1 |
-R39C26[0][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_3_s5/CLK |
+R40C22[0][A] |
+gw_gao_inst_0/u_ao_top/internal_reg_start_dly_0_s0/CLK |
0.749 |
@@ -21289,8 +21865,8 @@ Path8
tHld |
|
1 |
-R39C26[0][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_3_s5 |
+R40C22[0][A] |
+gw_gao_inst_0/u_ao_top/internal_reg_start_dly_0_s0 |
Path Statistics:
@@ -21313,7 +21889,7 @@ Path8
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.230, 56.935%; tC2Q: 0.174, 43.065% |
+cell: 0.000, 0.000%; route: 0.245, 58.439%; tC2Q: 0.174, 41.561% |
Required Clock Path Delay |
@@ -21325,11 +21901,11 @@ Path9
Slack |
-20.405 |
+20.420 |
Data Arrival Time |
-21.155 |
+21.169 |
Data Required Time |
@@ -21341,7 +21917,7 @@ Path9
To |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_9_s5 |
+gw_gao_inst_0/u_ao_top/internal_reg_start_dly_1_s0 |
Launch Clk |
@@ -21395,7 +21971,7 @@ Path9
0.583 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -21405,7 +21981,7 @@ Path9
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -21414,17 +21990,17 @@ Path9
tC2Q |
FR |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-21.155 |
-0.230 |
+21.169 |
+0.245 |
tNET |
RR |
1 |
-R39C26[2][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_9_s5/CLEAR |
+R40C22[0][B] |
+gw_gao_inst_0/u_ao_top/internal_reg_start_dly_1_s0/CLEAR |
Data Required Path:
@@ -21470,7 +22046,7 @@ Path9
0.581 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -21480,8 +22056,8 @@ Path9
tNET |
RR |
1 |
-R39C26[2][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_9_s5/CLK |
+R40C22[0][B] |
+gw_gao_inst_0/u_ao_top/internal_reg_start_dly_1_s0/CLK |
0.749 |
@@ -21489,8 +22065,8 @@ Path9
tHld |
|
1 |
-R39C26[2][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_9_s5 |
+R40C22[0][B] |
+gw_gao_inst_0/u_ao_top/internal_reg_start_dly_1_s0 |
Path Statistics:
@@ -21513,7 +22089,7 @@ Path9
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.230, 56.935%; tC2Q: 0.174, 43.065% |
+cell: 0.000, 0.000%; route: 0.245, 58.439%; tC2Q: 0.174, 41.561% |
Required Clock Path Delay |
@@ -21525,11 +22101,11 @@ Path10
Slack |
-20.408 |
+20.423 |
Data Arrival Time |
-21.157 |
+21.172 |
Data Required Time |
@@ -21541,7 +22117,7 @@ Path10
To |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_0_s5 |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_loop_s1 |
Launch Clk |
@@ -21595,7 +22171,7 @@ Path10
0.583 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -21605,7 +22181,7 @@ Path10
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -21614,17 +22190,17 @@ Path10
tC2Q |
FR |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-21.157 |
-0.233 |
+21.172 |
+0.247 |
tNET |
RR |
1 |
-R39C22[2][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLEAR |
+R40C21[0][B] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR |
Data Required Path:
@@ -21670,7 +22246,7 @@ Path10
0.581 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -21680,8 +22256,8 @@ Path10
tNET |
RR |
1 |
-R39C22[2][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLK |
+R40C21[0][B] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_loop_s1/CLK |
0.749 |
@@ -21689,8 +22265,8 @@ Path10
tHld |
|
1 |
-R39C22[2][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_0_s5 |
+R40C21[0][B] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_loop_s1 |
Path Statistics:
@@ -21713,7 +22289,7 @@ Path10
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.233, 57.208%; tC2Q: 0.174, 42.792% |
+cell: 0.000, 0.000%; route: 0.247, 58.694%; tC2Q: 0.174, 41.306% |
Required Clock Path Delay |
@@ -21725,11 +22301,11 @@ Path11
Slack |
-20.408 |
+20.423 |
Data Arrival Time |
-21.157 |
+21.172 |
Data Required Time |
@@ -21741,7 +22317,7 @@ Path11
To |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_1_s5 |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 |
Launch Clk |
@@ -21795,7 +22371,7 @@ Path11
0.583 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -21805,7 +22381,7 @@ Path11
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -21814,17 +22390,17 @@ Path11
tC2Q |
FR |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-21.157 |
-0.233 |
+21.172 |
+0.247 |
tNET |
RR |
1 |
-R39C23[1][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_1_s5/CLEAR |
+R40C21[1][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR |
Data Required Path:
@@ -21870,7 +22446,7 @@ Path11
0.581 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -21880,8 +22456,8 @@ Path11
tNET |
RR |
1 |
-R39C23[1][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_1_s5/CLK |
+R40C21[1][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK |
0.749 |
@@ -21889,8 +22465,8 @@ Path11
tHld |
|
1 |
-R39C23[1][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_1_s5 |
+R40C21[1][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/mem_addr_inc_en_s1 |
Path Statistics:
@@ -21913,7 +22489,7 @@ Path11
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.233, 57.208%; tC2Q: 0.174, 42.792% |
+cell: 0.000, 0.000%; route: 0.247, 58.694%; tC2Q: 0.174, 41.306% |
Required Clock Path Delay |
@@ -21925,11 +22501,11 @@ Path12
Slack |
-20.408 |
+20.423 |
Data Arrival Time |
-21.157 |
+21.172 |
Data Required Time |
@@ -21941,7 +22517,7 @@ Path12
To |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_4_s5 |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
Launch Clk |
@@ -21995,7 +22571,7 @@ Path12
0.583 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -22005,7 +22581,7 @@ Path12
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -22014,17 +22590,17 @@ Path12
tC2Q |
FR |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-21.157 |
-0.233 |
+21.172 |
+0.247 |
tNET |
RR |
1 |
-R39C23[1][B] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_4_s5/CLEAR |
+R40C21[2][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR |
Data Required Path:
@@ -22070,7 +22646,7 @@ Path12
0.581 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -22080,8 +22656,8 @@ Path12
tNET |
RR |
1 |
-R39C23[1][B] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_4_s5/CLK |
+R40C21[2][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
0.749 |
@@ -22089,8 +22665,8 @@ Path12
tHld |
|
1 |
-R39C23[1][B] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_4_s5 |
+R40C21[2][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
Path Statistics:
@@ -22113,7 +22689,7 @@ Path12
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.233, 57.208%; tC2Q: 0.174, 42.792% |
+cell: 0.000, 0.000%; route: 0.247, 58.694%; tC2Q: 0.174, 41.306% |
Required Clock Path Delay |
@@ -22125,11 +22701,11 @@ Path13
Slack |
-20.408 |
+20.507 |
Data Arrival Time |
-21.157 |
+21.256 |
Data Required Time |
@@ -22141,7 +22717,7 @@ Path13
To |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_6_s5 |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
Launch Clk |
@@ -22195,7 +22771,7 @@ Path13
0.583 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -22205,7 +22781,7 @@ Path13
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -22214,17 +22790,17 @@ Path13
tC2Q |
FR |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-21.157 |
-0.233 |
+21.256 |
+0.332 |
tNET |
RR |
1 |
-R39C22[0][B] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_6_s5/CLEAR |
+R40C20[0][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR |
Data Required Path:
@@ -22270,7 +22846,7 @@ Path13
0.581 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -22280,8 +22856,8 @@ Path13
tNET |
RR |
1 |
-R39C22[0][B] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_6_s5/CLK |
+R40C20[0][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK |
0.749 |
@@ -22289,8 +22865,8 @@ Path13
tHld |
|
1 |
-R39C22[0][B] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_6_s5 |
+R40C20[0][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_2_s1 |
Path Statistics:
@@ -22313,7 +22889,7 @@ Path13
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.233, 57.208%; tC2Q: 0.174, 42.792% |
+cell: 0.000, 0.000%; route: 0.332, 65.571%; tC2Q: 0.174, 34.429% |
Required Clock Path Delay |
@@ -22325,11 +22901,11 @@ Path14
Slack |
-20.408 |
+20.507 |
Data Arrival Time |
-21.157 |
+21.256 |
Data Required Time |
@@ -22341,7 +22917,7 @@ Path14
To |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_7_s5 |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
Launch Clk |
@@ -22395,7 +22971,7 @@ Path14
0.583 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -22405,7 +22981,7 @@ Path14
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -22414,17 +22990,17 @@ Path14
tC2Q |
FR |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-21.157 |
-0.233 |
+21.256 |
+0.332 |
tNET |
RR |
1 |
-R39C25[0][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_7_s5/CLEAR |
+R40C20[2][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR |
Data Required Path:
@@ -22470,7 +23046,7 @@ Path14
0.581 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -22480,8 +23056,8 @@ Path14
tNET |
RR |
1 |
-R39C25[0][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_7_s5/CLK |
+R40C20[2][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK |
0.749 |
@@ -22489,8 +23065,8 @@ Path14
tHld |
|
1 |
-R39C25[0][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_7_s5 |
+R40C20[2][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
Path Statistics:
@@ -22513,7 +23089,7 @@ Path14
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.233, 57.208%; tC2Q: 0.174, 42.792% |
+cell: 0.000, 0.000%; route: 0.332, 65.571%; tC2Q: 0.174, 34.429% |
Required Clock Path Delay |
@@ -22525,11 +23101,11 @@ Path15
Slack |
-20.408 |
+20.513 |
Data Arrival Time |
-21.157 |
+21.262 |
Data Required Time |
@@ -22541,7 +23117,7 @@ Path15
To |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_10_s5 |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_4_s5 |
Launch Clk |
@@ -22595,7 +23171,7 @@ Path15
0.583 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -22605,7 +23181,7 @@ Path15
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -22614,17 +23190,17 @@ Path15
tC2Q |
FR |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-21.157 |
-0.233 |
+21.262 |
+0.338 |
tNET |
RR |
1 |
-R39C23[0][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_10_s5/CLEAR |
+R39C20[1][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_4_s5/CLEAR |
Data Required Path:
@@ -22670,7 +23246,7 @@ Path15
0.581 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -22680,8 +23256,8 @@ Path15
tNET |
RR |
1 |
-R39C23[0][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_10_s5/CLK |
+R39C20[1][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_4_s5/CLK |
0.749 |
@@ -22689,8 +23265,8 @@ Path15
tHld |
|
1 |
-R39C23[0][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_10_s5 |
+R39C20[1][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_4_s5 |
Path Statistics:
@@ -22713,7 +23289,7 @@ Path15
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.233, 57.208%; tC2Q: 0.174, 42.792% |
+cell: 0.000, 0.000%; route: 0.338, 66.000%; tC2Q: 0.174, 34.000% |
Required Clock Path Delay |
@@ -22725,11 +23301,11 @@ Path16
Slack |
-20.408 |
+20.538 |
Data Arrival Time |
-21.157 |
+21.288 |
Data Required Time |
@@ -22741,7 +23317,7 @@ Path16
To |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_7_s5 |
Launch Clk |
@@ -22795,7 +23371,7 @@ Path16
0.583 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -22805,7 +23381,7 @@ Path16
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -22814,17 +23390,17 @@ Path16
tC2Q |
FR |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-21.157 |
-0.233 |
+21.288 |
+0.363 |
tNET |
RR |
1 |
-R39C22[1][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR |
+R39C22[0][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_7_s5/CLEAR |
Data Required Path:
@@ -22870,7 +23446,7 @@ Path16
0.581 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -22880,8 +23456,8 @@ Path16
tNET |
RR |
1 |
-R39C22[1][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK |
+R39C22[0][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_7_s5/CLK |
0.749 |
@@ -22889,8 +23465,8 @@ Path16
tHld |
|
1 |
-R39C22[1][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
+R39C22[0][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_7_s5 |
Path Statistics:
@@ -22913,7 +23489,7 @@ Path16
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.233, 57.208%; tC2Q: 0.174, 42.792% |
+cell: 0.000, 0.000%; route: 0.363, 67.587%; tC2Q: 0.174, 32.413% |
Required Clock Path Delay |
@@ -22925,11 +23501,11 @@ Path17
Slack |
-20.408 |
+20.538 |
Data Arrival Time |
-21.157 |
+21.288 |
Data Required Time |
@@ -22941,7 +23517,7 @@ Path17
To |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_11_s1 |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_9_s5 |
Launch Clk |
@@ -22995,7 +23571,7 @@ Path17
0.583 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -23005,7 +23581,7 @@ Path17
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -23014,17 +23590,17 @@ Path17
tC2Q |
FR |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-21.157 |
-0.233 |
+21.288 |
+0.363 |
tNET |
RR |
1 |
-R39C23[2][B] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_11_s1/CLEAR |
+R39C22[1][B] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_9_s5/CLEAR |
Data Required Path:
@@ -23070,7 +23646,7 @@ Path17
0.581 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -23080,8 +23656,8 @@ Path17
tNET |
RR |
1 |
-R39C23[2][B] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_11_s1/CLK |
+R39C22[1][B] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_9_s5/CLK |
0.749 |
@@ -23089,8 +23665,8 @@ Path17
tHld |
|
1 |
-R39C23[2][B] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_11_s1 |
+R39C22[1][B] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_9_s5 |
Path Statistics:
@@ -23113,7 +23689,7 @@ Path17
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.233, 57.208%; tC2Q: 0.174, 42.792% |
+cell: 0.000, 0.000%; route: 0.363, 67.587%; tC2Q: 0.174, 32.413% |
Required Clock Path Delay |
@@ -23125,11 +23701,11 @@ Path18
Slack |
-20.408 |
+20.538 |
Data Arrival Time |
-21.157 |
+21.288 |
Data Required Time |
@@ -23141,7 +23717,7 @@ Path18
To |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_12_s1 |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_10_s5 |
Launch Clk |
@@ -23195,7 +23771,7 @@ Path18
0.583 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -23205,7 +23781,7 @@ Path18
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -23214,17 +23790,17 @@ Path18
tC2Q |
FR |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-21.157 |
-0.233 |
+21.288 |
+0.363 |
tNET |
RR |
1 |
-R39C23[2][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_12_s1/CLEAR |
+R39C22[0][B] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_10_s5/CLEAR |
Data Required Path:
@@ -23270,7 +23846,7 @@ Path18
0.581 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -23280,8 +23856,8 @@ Path18
tNET |
RR |
1 |
-R39C23[2][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_12_s1/CLK |
+R39C22[0][B] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_10_s5/CLK |
0.749 |
@@ -23289,8 +23865,8 @@ Path18
tHld |
|
1 |
-R39C23[2][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_12_s1 |
+R39C22[0][B] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_10_s5 |
Path Statistics:
@@ -23313,7 +23889,7 @@ Path18
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.233, 57.208%; tC2Q: 0.174, 42.792% |
+cell: 0.000, 0.000%; route: 0.363, 67.587%; tC2Q: 0.174, 32.413% |
Required Clock Path Delay |
@@ -23325,11 +23901,11 @@ Path19
Slack |
-20.408 |
+20.541 |
Data Arrival Time |
-21.157 |
+21.290 |
Data Required Time |
@@ -23341,7 +23917,7 @@ Path19
To |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_6_s5 |
Launch Clk |
@@ -23395,7 +23971,7 @@ Path19
0.583 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -23405,7 +23981,7 @@ Path19
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -23414,17 +23990,17 @@ Path19
tC2Q |
FR |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-21.157 |
-0.233 |
+21.290 |
+0.366 |
tNET |
RR |
1 |
-R39C25[2][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR |
+R39C21[2][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_6_s5/CLEAR |
Data Required Path:
@@ -23470,7 +24046,7 @@ Path19
0.581 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -23480,8 +24056,8 @@ Path19
tNET |
RR |
1 |
-R39C25[2][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK |
+R39C21[2][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_6_s5/CLK |
0.749 |
@@ -23489,8 +24065,8 @@ Path19
tHld |
|
1 |
-R39C25[2][A] |
-gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_wr_s1 |
+R39C21[2][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_6_s5 |
Path Statistics:
@@ -23513,7 +24089,7 @@ Path19
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.233, 57.208%; tC2Q: 0.174, 42.792% |
+cell: 0.000, 0.000%; route: 0.366, 67.742%; tC2Q: 0.174, 32.258% |
Required Clock Path Delay |
@@ -23525,11 +24101,11 @@ Path20
Slack |
-20.408 |
+20.541 |
Data Arrival Time |
-21.157 |
+21.290 |
Data Required Time |
@@ -23541,7 +24117,7 @@ Path20
To |
-gw_gao_inst_0/u_ao_top/trigger_seq_start_s1 |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
Launch Clk |
@@ -23595,7 +24171,7 @@ Path20
0.583 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -23605,7 +24181,7 @@ Path20
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -23614,17 +24190,17 @@ Path20
tC2Q |
FR |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-21.157 |
-0.233 |
+21.290 |
+0.366 |
tNET |
RR |
1 |
-R39C25[1][B] |
-gw_gao_inst_0/u_ao_top/trigger_seq_start_s1/CLEAR |
+R39C21[1][B] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR |
Data Required Path:
@@ -23670,7 +24246,7 @@ Path20
0.581 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -23680,8 +24256,8 @@ Path20
tNET |
RR |
1 |
-R39C25[1][B] |
-gw_gao_inst_0/u_ao_top/trigger_seq_start_s1/CLK |
+R39C21[1][B] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK |
0.749 |
@@ -23689,8 +24265,8 @@ Path20
tHld |
|
1 |
-R39C25[1][B] |
-gw_gao_inst_0/u_ao_top/trigger_seq_start_s1 |
+R39C21[1][B] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_3_s1 |
Path Statistics:
@@ -23713,7 +24289,7 @@ Path20
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.233, 57.208%; tC2Q: 0.174, 42.792% |
+cell: 0.000, 0.000%; route: 0.366, 67.742%; tC2Q: 0.174, 32.258% |
Required Clock Path Delay |
@@ -23725,11 +24301,11 @@ Path21
Slack |
-20.408 |
+20.541 |
Data Arrival Time |
-21.157 |
+21.290 |
Data Required Time |
@@ -23741,7 +24317,7 @@ Path21
To |
-gw_gao_inst_0/u_ao_top/internal_reg_start_dly_1_s0 |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
Launch Clk |
@@ -23795,7 +24371,7 @@ Path21
0.583 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -23805,7 +24381,7 @@ Path21
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -23814,17 +24390,17 @@ Path21
tC2Q |
FR |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-21.157 |
-0.233 |
+21.290 |
+0.366 |
tNET |
RR |
1 |
-R39C25[0][B] |
-gw_gao_inst_0/u_ao_top/internal_reg_start_dly_1_s0/CLEAR |
+R39C21[0][B] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR |
Data Required Path:
@@ -23870,7 +24446,7 @@ Path21
0.581 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -23880,8 +24456,8 @@ Path21
tNET |
RR |
1 |
-R39C25[0][B] |
-gw_gao_inst_0/u_ao_top/internal_reg_start_dly_1_s0/CLK |
+R39C21[0][B] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK |
0.749 |
@@ -23889,8 +24465,8 @@ Path21
tHld |
|
1 |
-R39C25[0][B] |
-gw_gao_inst_0/u_ao_top/internal_reg_start_dly_1_s0 |
+R39C21[0][B] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_8_s1 |
Path Statistics:
@@ -23913,7 +24489,7 @@ Path21
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.233, 57.208%; tC2Q: 0.174, 42.792% |
+cell: 0.000, 0.000%; route: 0.366, 67.742%; tC2Q: 0.174, 32.258% |
Required Clock Path Delay |
@@ -23925,11 +24501,11 @@ Path22
Slack |
-20.613 |
+20.541 |
Data Arrival Time |
-21.362 |
+21.290 |
Data Required Time |
@@ -23941,7 +24517,7 @@ Path22
To |
-gw_gao_inst_0/u_ao_top/internal_reg_start_syn_0_s0 |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_11_s1 |
Launch Clk |
@@ -23995,7 +24571,7 @@ Path22
0.583 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -24005,7 +24581,7 @@ Path22
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -24014,17 +24590,17 @@ Path22
tC2Q |
FR |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-21.362 |
-0.438 |
+21.290 |
+0.366 |
tNET |
RR |
1 |
-R43C27[0][B] |
-gw_gao_inst_0/u_ao_top/internal_reg_start_syn_0_s0/CLEAR |
+R39C21[0][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_11_s1/CLEAR |
Data Required Path:
@@ -24070,7 +24646,7 @@ Path22
0.581 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -24080,8 +24656,8 @@ Path22
tNET |
RR |
1 |
-R43C27[0][B] |
-gw_gao_inst_0/u_ao_top/internal_reg_start_syn_0_s0/CLK |
+R39C21[0][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_11_s1/CLK |
0.749 |
@@ -24089,8 +24665,8 @@ Path22
tHld |
|
1 |
-R43C27[0][B] |
-gw_gao_inst_0/u_ao_top/internal_reg_start_syn_0_s0 |
+R39C21[0][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_11_s1 |
Path Statistics:
@@ -24113,7 +24689,7 @@ Path22
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.438, 71.552%; tC2Q: 0.174, 28.448% |
+cell: 0.000, 0.000%; route: 0.366, 67.742%; tC2Q: 0.174, 32.258% |
Required Clock Path Delay |
@@ -24125,11 +24701,11 @@ Path23
Slack |
-20.613 |
+20.546 |
Data Arrival Time |
-21.362 |
+21.295 |
Data Required Time |
@@ -24141,7 +24717,7 @@ Path23
To |
-gw_gao_inst_0/u_ao_top/internal_reg_start_syn_1_s0 |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_0_s5 |
Launch Clk |
@@ -24195,7 +24771,7 @@ Path23
0.583 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -24205,7 +24781,7 @@ Path23
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -24214,17 +24790,17 @@ Path23
tC2Q |
FR |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-21.362 |
-0.438 |
+21.295 |
+0.371 |
tNET |
RR |
1 |
-R43C27[0][A] |
-gw_gao_inst_0/u_ao_top/internal_reg_start_syn_1_s0/CLEAR |
+R40C25[1][B] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLEAR |
Data Required Path:
@@ -24270,7 +24846,7 @@ Path23
0.581 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -24280,8 +24856,8 @@ Path23
tNET |
RR |
1 |
-R43C27[0][A] |
-gw_gao_inst_0/u_ao_top/internal_reg_start_syn_1_s0/CLK |
+R40C25[1][B] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLK |
0.749 |
@@ -24289,8 +24865,8 @@ Path23
tHld |
|
1 |
-R43C27[0][A] |
-gw_gao_inst_0/u_ao_top/internal_reg_start_syn_1_s0 |
+R40C25[1][B] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_0_s5 |
Path Statistics:
@@ -24313,7 +24889,7 @@ Path23
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.438, 71.552%; tC2Q: 0.174, 28.448% |
+cell: 0.000, 0.000%; route: 0.371, 68.052%; tC2Q: 0.174, 31.948% |
Required Clock Path Delay |
@@ -24325,11 +24901,11 @@ Path24
Slack |
-20.622 |
+20.546 |
Data Arrival Time |
-21.371 |
+21.295 |
Data Required Time |
@@ -24341,7 +24917,7 @@ Path24
To |
-gw_gao_inst_0/u_ao_top/capture_start_sel_s1 |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_12_s6 |
Launch Clk |
@@ -24395,7 +24971,7 @@ Path24
0.583 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -24405,7 +24981,7 @@ Path24
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -24414,17 +24990,17 @@ Path24
tC2Q |
FR |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-21.371 |
-0.447 |
+21.295 |
+0.371 |
tNET |
RR |
1 |
-R43C26[2][A] |
-gw_gao_inst_0/u_ao_top/capture_start_sel_s1/CLEAR |
+R40C25[1][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_12_s6/CLEAR |
Data Required Path:
@@ -24470,7 +25046,7 @@ Path24
0.581 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -24480,8 +25056,8 @@ Path24
tNET |
RR |
1 |
-R43C26[2][A] |
-gw_gao_inst_0/u_ao_top/capture_start_sel_s1/CLK |
+R40C25[1][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_12_s6/CLK |
0.749 |
@@ -24489,8 +25065,8 @@ Path24
tHld |
|
1 |
-R43C26[2][A] |
-gw_gao_inst_0/u_ao_top/capture_start_sel_s1 |
+R40C25[1][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_12_s6 |
Path Statistics:
@@ -24513,7 +25089,7 @@ Path24
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.447, 71.951%; tC2Q: 0.174, 28.049% |
+cell: 0.000, 0.000%; route: 0.371, 68.052%; tC2Q: 0.174, 31.948% |
Required Clock Path Delay |
@@ -24525,11 +25101,11 @@ Path25
Slack |
-20.622 |
+20.650 |
Data Arrival Time |
-21.371 |
+21.399 |
Data Required Time |
@@ -24541,7 +25117,7 @@ Path25
To |
-gw_gao_inst_0/u_ao_top/capture_end_dly_s0 |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_1_s5 |
Launch Clk |
@@ -24595,7 +25171,7 @@ Path25
0.583 |
tINS |
FF |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -24605,7 +25181,7 @@ Path25
tNET |
FF |
1 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/CLK |
@@ -24614,17 +25190,17 @@ Path25
tC2Q |
FR |
26 |
-R40C24[1][B] |
+R44C20[1][A] |
gw_gao_inst_0/u_ao_top/rst_ao_s0/Q |
-21.371 |
-0.447 |
+21.399 |
+0.474 |
tNET |
RR |
1 |
-R43C26[0][B] |
-gw_gao_inst_0/u_ao_top/capture_end_dly_s0/PRESET |
+R39C19[1][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_1_s5/CLEAR |
Data Required Path:
@@ -24670,7 +25246,7 @@ Path25
0.581 |
tINS |
RR |
-207 |
+277 |
IOL29[A] |
clk_ibuf/O |
@@ -24680,8 +25256,8 @@ Path25
tNET |
RR |
1 |
-R43C26[0][B] |
-gw_gao_inst_0/u_ao_top/capture_end_dly_s0/CLK |
+R39C19[1][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_1_s5/CLK |
0.749 |
@@ -24689,8 +25265,8 @@ Path25
tHld |
|
1 |
-R43C26[0][B] |
-gw_gao_inst_0/u_ao_top/capture_end_dly_s0 |
+R39C19[1][A] |
+gw_gao_inst_0/u_ao_top/u_ao_mem_ctrl/capture_mem_addr_1_s5 |
Path Statistics:
@@ -24713,7 +25289,7 @@ Path25
Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.447, 71.951%; tC2Q: 0.174, 28.049% |
+cell: 0.000, 0.000%; route: 0.474, 73.149%; tC2Q: 0.174, 26.851% |
Required Clock Path Delay |
@@ -25455,7 +26031,7 @@ MPW7
Objects: |
-arkanoid/qx_2_s1 |
+arkanoid/score[6]_2_s0 |
Late clock Path:
@@ -25500,7 +26076,7 @@ MPW7
0.225 |
tNET |
FF |
-arkanoid/qx_2_s1/CLK |
+arkanoid/score[6]_2_s0/CLK |
Early clock Path:
@@ -25545,7 +26121,7 @@ MPW7
0.159 |
tNET |
RR |
-arkanoid/qx_2_s1/CLK |
+arkanoid/score[6]_2_s0/CLK |
MPW8
@@ -25573,7 +26149,7 @@ MPW8
Objects: |
-arkanoid/qx_1_s1 |
+DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0 |
Late clock Path:
@@ -25618,7 +26194,7 @@ MPW8
0.225 |
tNET |
FF |
-arkanoid/qx_1_s1/CLK |
+DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0/CLK |
Early clock Path:
@@ -25663,7 +26239,7 @@ MPW8
0.159 |
tNET |
RR |
-arkanoid/qx_1_s1/CLK |
+DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0/CLK |
MPW9
@@ -25691,7 +26267,7 @@ MPW9
Objects: |
-s480p/y_9_s0 |
+DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/c1_d_s0 |
Late clock Path:
@@ -25736,7 +26312,7 @@ MPW9
0.225 |
tNET |
FF |
-s480p/y_9_s0/CLK |
+DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/c1_d_s0/CLK |
Early clock Path:
@@ -25781,7 +26357,7 @@ MPW9
0.159 |
tNET |
RR |
-s480p/y_9_s0/CLK |
+DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/c1_d_s0/CLK |
MPW10
@@ -25809,7 +26385,7 @@ MPW10
Objects: |
-arkanoid/qxb_8_s2 |
+arkanoid/score[6]_4_s0 |
Late clock Path:
@@ -25854,7 +26430,7 @@ MPW10
0.225 |
tNET |
FF |
-arkanoid/qxb_8_s2/CLK |
+arkanoid/score[6]_4_s0/CLK |
Early clock Path:
@@ -25899,7 +26475,7 @@ MPW10
0.159 |
tNET |
RR |
-arkanoid/qxb_8_s2/CLK |
+arkanoid/score[6]_4_s0/CLK |
@@ -25912,64 +26488,64 @@ Report Command:report_high_fanout_nets -max_nets 10
MAX DELAY |
-207 |
+277 |
clk_d |
-10.063 |
+9.708 |
0.225 |
181 |
control0[0] |
-8.006 |
+7.587 |
0.786 |
+47 |
+sy_Z[1] |
+34.411 |
+1.638 |
+
+
46 |
n45_3 |
-47.213 |
-1.412 |
+47.616 |
+0.843 |
44 |
din_d[0] |
-33.844 |
-0.454 |
+34.065 |
+0.430 |
42 |
de_d |
-38.067 |
-1.230 |
+38.481 |
+0.819 |
38 |
din_d[0] |
-33.578 |
-0.416 |
+33.300 |
+0.422 |
37 |
din_d[0] |
-33.577 |
-0.427 |
-
-
-34 |
-addr_ct_en_14 |
-44.963 |
-0.913 |
+32.941 |
+0.391 |
33 |
n73_7 |
-36.772 |
-0.815 |
+36.204 |
+0.930 |
32 |
-green_Z[7] |
-35.662 |
-1.495 |
+red_Z[7] |
+35.396 |
+1.612 |
@@ -25980,44 +26556,44 @@ Report Command:report_route_congestion -max_grids 10
ROUTE CONGESTIONS |
-R38C34 |
-84.72% |
+R39C23 |
+90.28% |
-R39C33 |
-84.72% |
+R36C24 |
+86.11% |
-R42C27 |
+R38C28 |
84.72% |
-R39C27 |
-81.94% |
+R40C23 |
+84.72% |
-R38C33 |
-81.94% |
+R39C20 |
+83.33% |
-R43C27 |
-80.56% |
+R39C24 |
+83.33% |
-R42C23 |
-80.56% |
+R38C22 |
+83.33% |
-R40C25 |
-79.17% |
+R41C28 |
+83.33% |
-R39C23 |
-79.17% |
+R42C21 |
+81.94% |
-R42C26 |
-79.17% |
+R36C28 |
+81.94% |
diff --git a/impl/pnr/ao_0.bin b/impl/pnr/ao_0.bin
index e229f71b29c30d43f44b3770ede5d1cea1599bc8..c2f6a67bd18ec96216ec508102d8ce79a7ea674c 100644
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