Merge branch 'main' of https://github.com/FPGAwars/iceWires

FPGAwars · Nov 4, 2023 · 9c2dac5 · 9c2dac5
2 parents b0fc2a0 + b5f3b60
commit 9c2dac5
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/locale/translation.js b/locale/translation.js
@@ -2125,11 +2125,11 @@ gettext('31-bits');
 gettext('Alhambra-II');
 gettext('01-Manual-testing');
 gettext('not-x32: 32-bits not gate');
+gettext('02-Reg: 2 bits Register. Verilog implementation');
 gettext('## Uint32-2bit Manual testing');
 gettext('Alhambra-II');
 gettext('01-Manual-testing');
-gettext('UINT32-8bit-verilog:  Extend a 8-bit unsigned integer to 32-bits. Verilog implementation ');
-gettext('## Uint32-8bit Manual testing');
+gettext('## 08-Uint32 Manual testing');
 gettext('Alhambra-II');
 gettext('01-Manual-testing');
 gettext('UINT32-16bit-verilog:  Extend a 16-bit unsigned integer to 32-bits. Verilog implementation ');