Merge branch 'main' of https://github.com/FPGAwars/iceWires

FPGAwars · Nov 4, 2023 · 6021582 · 6021582
2 parents 046b972 + 6a25b42
commit 6021582
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Showing 15 changed files with 2,111 additions and 2,339 deletions.
diff --git a/locale/ca_ES/ca_ES.po b/locale/ca_ES/ca_ES.po
diff --git a/locale/cs_CZ/cs_CZ.po b/locale/cs_CZ/cs_CZ.po
diff --git a/locale/de_DE/de_DE.po b/locale/de_DE/de_DE.po
diff --git a/locale/el_GR/el_GR.po b/locale/el_GR/el_GR.po
diff --git a/locale/es_ES/es_ES.po b/locale/es_ES/es_ES.po
diff --git a/locale/eu_ES/eu_ES.po b/locale/eu_ES/eu_ES.po
diff --git a/locale/fr_FR/fr_FR.po b/locale/fr_FR/fr_FR.po
diff --git a/locale/gl_ES/gl_ES.po b/locale/gl_ES/gl_ES.po
diff --git a/locale/it_IT/it_IT.po b/locale/it_IT/it_IT.po
diff --git a/locale/ko_KR/ko_KR.po b/locale/ko_KR/ko_KR.po
diff --git a/locale/nl_NL/nl_NL.po b/locale/nl_NL/nl_NL.po
diff --git a/locale/ru_RU/ru_RU.po b/locale/ru_RU/ru_RU.po
diff --git a/locale/translation.js b/locale/translation.js
@@ -2022,16 +2022,13 @@ gettext('03-Bits');
 gettext('Alhambra-II');
 gettext('01-Manual-testing');
 gettext('not-x4: 4-bits not gate');
-gettext('UINT4-1bit-verilog:  Extend a 1-bit unsigned integer to 4-bits. Verilog implementation ');
-gettext('## Uint4-1bit: Manual testing');
+gettext('## 01-Uint4: Manual testing');
 gettext('Alhambra-II');
 gettext('01-Manual-testing');
-gettext('UINT4-2bit-verilog:  Extend a 2-bit unsigned integer to 4-bits. Verilog implementation ');
-gettext('## Uint4-2bit: Manual testing');
+gettext('## 02-Uint4: Manual testing');
 gettext('Alhambra-II');
 gettext('01-Manual-testing');
-gettext('UINT4-3bit-verilog:  Extend a 3-bit unsigned integer to 4-bits. Verilog implementation ');
-gettext('## Uint4-3bit: Manual testing');
+gettext('## 03-Uint4: Manual testing');
 gettext('01-bit');
 gettext('02-bits');
 gettext('03-bits');