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bs9.c
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bs9.c
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/*
*******************
Bit Shift Assembler
*******************
Version: 06-Jan-2025
The assembler was developed and tested on a MAC with macOS Catalina.
Using no specific options of the host system, it should run on any
computer with a standard C-compiler, e.g. Linux, Windows, Amiga OS, etc.
This assembler is a Cross-Assembler, it is run on a (modern) host system,
but produces code for target machines running a Motorola 6809
or a Hitachi 6309 CPU, e.g. Thomson MO and TO series,
Dragon 32/64, Commodore Super PET and Tandy CoCo.
Compiling
=========
If your compiler is named "gcc" for example, compile with:
gcc -o bs9 bs9.c
If you have GNU make and sudo installed, you may also use these lines
to install the binary to /usr/local/bin:
make
sudo make install
Running
=======
If you have a source code named "hello.as9", run the assembler with:
bs9 hello
It will read "hello.as9" as input file and write the
listing file with cross reference "hello.lst".
Binary output is controlled within the source file by means
of the pseudo op "STORE" (see below for syntax):
Case sensitivity
================
mnemonics, and pseudo opcodes are insensitive to case:
LDA lda Lda are all equivalent (Load Accumulator A)
FCB fcb Fcb are all equivalent (define byte data)
Label and named constants are case sensitive by default!
The option "-i" switches off the case sensitivity for symbols.
Also the pseudo op "CASE +/-" may be used to switch sensitivity.
LDA #Cr and LDA #CR use different constants!
JMP Lab_10 and JMP LAB_10 jump to different targets!
Directives
==========
CPU = 6809 allow code for 6809 only
CPU = 6309 allow full 6309 instruction set (default)
Labels and Constants
====================
LABEL LDX #Value define LABEL for current PC
TXTPTR = $21b8 define constant TXTPTR
OLDPTR EQU $21ba define constant OLDPTR
CURRENT SET 5 define variable CURRENT
Modules (Subroutines)
=====================
The pseudo instructions
MODULE
...
ENDMOD
or the aliases
SUBROUTINE
...
ENDSUB
define a namespace for local variables.
Variables starting with a '.' (dot) have a scope limited to code
between MODULE and ENDMOD.
Example:
MODULE Delay
.loop LEAX -1,X
BNE .loop
RTS
ENDMOD
MODULE Strout
.loop LDA ,X+
BEQ .ret
JSR Chrout
BRA .loop
.ret RTS
ENDMOD
There is no conflict in using the label ".loop" twice, because they
are used in separate modules. Internally the assembler generates the names:
Delay.loop
Strout.loop
Strout.ret
for these labels.
Assign addresses to symbols
===========================
LABEL ENUM value define label with value
LABEL ENUM use last ENUM value + 1
& = value set start value for BSS segment
TXTPTR BSS 2 assign TXTPTR = &, & += 2
CURSOR BSS 1 assign CURSOR = &, & += 1
Labels and constants can have only one value.
Variables, which get their value assigned with "SET",
may change their values.
Labels that are defined by their current position must start
at the first column.
Examples of pseudo opcodes (directives):
========================================
ORG $E000 set program counter
STORE START,$2000,"basic.rom" write binary image file "basic.rom"
STORE START,$2000,"basic.rom",bin,1 write binary image, headed by load address
STORE START,$2000,"basic.s19",s19 write binary file in Motorola S-Record format
STORE START,$2000,"basic.s19",s19,Main write binary and provide execution start address
LOAD START,"image.bin" load binary file to START and following addresses
LOAD "image.bin" load binary file starting at current address
LIST + switch on assembler listing
LIST - switch off assembler listing
BITS . . * . * . . . stores a byte from 8 bit symbols
BYTE $20,"Example",0 stores a series of byte data
WORD LAB_10, WriteTape,$0200 stores a series of word data
LONG 1000000 stores 32 bit long data
REAL 3.1415926 stores a 32 bit real
FILL N ($EA) fill memory with N bytes containing $EA
FILL $A000 - * (0) fill memory from pc(*) upto $9FFF
INCLUDE "filename" includes specified file
END stops assembly
CASE - symbols are not case sensitive
SIZE print code size info
TXTTAB BSS 2 define TXTTAB and increase address pointer by 2
* = $E000 set program counter
& = $033A set BSS address pointer
ORG $E000 set program counter
SETDP $20 assume content of direct page register
FCB $20,"Example",0 stores a series of byte data
FDB LAB_10, WriteTape,$0200 stores a series of word data
FCC "Example\n" store ASCII string
ALIGN 16 align PC (fill gaps with NOPs)
ALIGN * 8 (0) align PC (fill gaps with 0)
ALIGN & 256 (0) align BSS (fill gaps with 0)
Examples of Operands
====================
6 = decimal constant
$A12 = hex constant
MURX = label or constant
"hello\r" = ASCII string with CR at end
Table_Offset + 2 * [LEN-1] = address
Constants
=========
'A' char constant
%1111 0000 bytet constant
? length of BYTE data line
$ffd2 hex constant
Unary operators in address calculations
========================================
< low byte
> extended address (override DP mode)
( parenthesis
) parenthesis
+ positive sign
- negative sign
! logical NOT
~ bitwise NOT
Binary operators in address calculations
========================================
+ addition
- subtraction
* multiplication or program counter (context sensitive)
/ division
& bitwise and
| bitwise or
^ bitwise xor
Relational operators
====================
== equal
!= not equal
> greater than
< less than
>= greater than or equal to
<= less than or equal to
<< left shift
>> right shift
&& and
|| or
Relational operators return the integer 0 (false) or 1 (true).
User macros
===========
Example:
MACRO PrintString(Message)
LDX #Message ; address of message
LDB #?Message ; length of message
JMP [SWI1PT] ; jump through vector
ENDM
defines a MACRO for loading a 16bit word into X and Y
Call:
OK .BYTE "\nOK\n"
PrintString(OK)
Generated Code:
LDX #OK
LDB #4
JMP [SWI1PT]
Macros accept up to 10 parameter and may have any length.
MACLIST ON : List expanded macro code lines
MACLIST OFF : Do not list expanded macro code lines
Conditional assembly
====================
Example: Assemble first part if C64 has a non zero value
if MO5
STA $D000
else
STA $9000
endif
Example: Assemble first part if MO5 is defined ($0000 - $ffff)
(undefined symbols are set to UNDEF ($00ff0000)
ifdef MO5
STA $D000
else
STA $9000
endif
assembles the first statement if MO5 is not zero and the second if zero.
Example: Assemble if symbol is undefined
ifndef TO9
STA $D000 ; Code for MO5 and TO8
endif
Another example:
if MO5 | TO9 ; true if either MO5 or TO9 is true (not zero)
LDA #MASK
if MO5
STA ICR_REG
else
STA TO9_ICR_REG
endif ; finishes inner if
endif ; finishes outer if
Example: check and force error
if (MAXLEN & $ff00)
#error This code is 8 bit only, MAXLEN too large!
endif
The maximum nesting depth is 10
For more examples see the complete operating system for the
Thomson MO5 available from the user "Bit Shifter" e.g. at
forum64 or the forum of the VzEkC.
Listing
=======
The program listings lists the original source code preceded by the
generated code in form of hexadecimal bigendian word or byte values.
For example:
27 9ff6 b6 fe30 LDA IO_SDCARD
28 9ff9 1034 8e ANDR A,E ; test IO_INCD#
29 9ffc 27 06 BEQ +
30 9ffe 8e a096 LDX #Msg_NOT ; " not"
^ ^ ^ ^ ^ ^ ^ ^
| | | | | | | \- Comment
| | | | | | \----------- Operand
| | | | | \------------------- Mnemonic
| | | | \----- Address/Value Operand (Word or Byte)
| | | \-------- Postbyte (Byte)
| | \------------- Opcode (Word or Byte)
| \------------------ Program address
\--------------------- Line number
*/
// switch off windows warnings for string functions
#define _CRT_SECURE_NO_WARNINGS
#include <stdlib.h>
#include <stdio.h>
#include <stdarg.h>
#include <string.h>
#include <math.h>
#include <ctype.h>
#include <errno.h>
#include <time.h>
int CPU = 6309; // default: Hitachi 6309
#define MAX_STR 1024
// The array ROM receives the assembled code.
// The size is one page more than 64K because program counter
// overflows are detected after using the new value.
// So references to pc + n do no harm if pc is near the boundary
unsigned char ROM[0x10100]; // binary
// Used to detect overwrite attempts
unsigned char LOCK[0x10100]; // binary
// A two pass assembler must set the instruction length in phase 1
// These values are stored in ADL, in order to avoid phase errors
// 0: no code generated for this address
// >0: instruction length locked
// <0: data byte or not start byte of instruction
int ErrNum; // error count
int ListGlobal = 1; // global listing control
int ListOn = 1; // listing control
FILE *sf; // source file
FILE *lf; // listing file
FILE *df; // debug file
FILE *pf; // preprocessed file
FILE *of; // object file
// forward references
void AddLabel(char *p);
void ErrorLine(char *p);
void ErrorMsg(const char *format, ...);
char *ExtractOpText(char *);
char *EvalOperand(char *, int *, int);
char *ExtractValue(char *, int *);
// store code or data into ROM array
// ***
// Put
// ***
void Put(int i, int v, char *p)
{
if (df) fprintf(df,"LOCK[%4.4x]=%x ROM[%4.4x]=%x v=%4.4x\n",
i,LOCK[i],i,ROM[i],v);
v &= 0xff;
if (LOCK[i] && ROM[i] != v)
{
++ErrNum;
if (p) ErrorLine(p);
ErrorMsg("Tried to overwrite address %4.4x\n",i);
exit(1);
}
ROM[i] = v;
LOCK[i] = 1;
}
// **********
// StrCaseStr
// **********
char *StrCaseStr(char *s1, const char *s2)
{
char h1[MAX_STR];
char h2[MAX_STR];
char *r;
unsigned int i;
memset(h1,0,sizeof(h1));
memset(h2,0,sizeof(h2));
for (i=0 ; i < strlen(s1) && i < sizeof(h1)-1 ; ++i)
h1[i] = toupper(s1[i]);
for (i=0 ; i < strlen(s2) && i < sizeof(h2)-1 ; ++i)
h2[i] = toupper(s2[i]);
r = strstr(h1,h2);
if (r) r = s1 + (r - h1);
return r;
}
// ***********
// AssertAlloc
// ***********
void *AssertAlloc(void *p)
{
if (p) return p;
fprintf(stderr, "Allocation of memory failed.\n");
exit(1);
}
// ***********
// MallocOrDie
// ***********
void *MallocOrDie(size_t size)
{
return AssertAlloc(calloc(size,1));
}
// ************
// ReallocOrDie
// ************
void *ReallocOrDie(void *p, size_t size)
{
return AssertAlloc(realloc(p, size));
}
// ************
// AssertFileOp
// ************
FILE *AssertFileOp(FILE *p, const char *msg)
{
if (p) return p;
perror(msg);
exit(1);
}
// *******
// StrNDup
// *******
char *StrNDup(void *src, unsigned int n)
{
char *dst;
if (n > MAX_STR)
{
fprintf(stderr,"*** tried to allocate %d bytes for string\n",n);
fprintf(stderr,"*** current maximum length is %d\n",MAX_STR);
exit(1);
}
dst = (char *)MallocOrDie(n+1);
memmove(dst,src,n);
return dst;
}
#define ADMODES 8
enum Addressing_Mode
{
AM_None , // 0
AM_Inherent , // 1
AM_Register , // 2
AM_Relative , // 3
AM_Immediate , // 4
AM_Direct , // 5
AM_Indexed , // 6
AM_Extended // 7
};
struct MatStruct
{
char Mne[6]; // Mnemonic
int Opc[ADMODES]; // Opcodes
} Mat[] =
{
// 0 1 2 3 4 5 6 7
// Mnem CPU Inher Reg Rela Imm Direct Ind Ext
// ---------------------------------------------------------------
{"NEG" ,{0, -1, -1, -1, -1, 0x00, 0x60, 0x70}},
{"COM" ,{0, -1, -1, -1, -1, 0x03, 0x63, 0x73}},
{"LSR" ,{0, -1, -1, -1, -1, 0x04, 0x64, 0x74}},
{"ROR" ,{0, -1, -1, -1, -1, 0x06, 0x66, 0x76}},
{"ASR" ,{0, -1, -1, -1, -1, 0x07, 0x67, 0x77}},
{"ASL" ,{0, -1, -1, -1, -1, 0x08, 0x68, 0x78}},
{"LSL" ,{0, -1, -1, -1, -1, 0x08, 0x68, 0x78}},
{"ROL" ,{0, -1, -1, -1, -1, 0x09, 0x69, 0x79}},
{"DEC" ,{0, -1, -1, -1, -1, 0x0a, 0x6a, 0x7a}},
{"INC" ,{0, -1, -1, -1, -1, 0x0c, 0x6c, 0x7c}},
{"TST" ,{0, -1, -1, -1, -1, 0x0d, 0x6d, 0x7d}},
{"JMP" ,{0, -1, -1, -1, -1, 0x0e, 0x6e, 0x7e}},
{"CLR" ,{0, -1, -1, -1, -1, 0x0f, 0x6f, 0x7f}},
{"NOP" ,{0, 0x12, -1, -1, -1, -1, -1, -1}},
{"SYNC" ,{0, 0x13, -1, -1, -1, -1, -1, -1}},
{"LBRA" ,{0, -1, -1, 0x16, -1, -1, -1, -1}},
{"LBSR" ,{0, -1, -1, 0x17, -1, -1, -1, -1}},
{"DAA" ,{0, 0x19, -1, -1, -1, -1, -1, -1}},
{"ORCC" ,{0, -1, -1, -1, 0x1a, -1, -1, -1}},
{"ANDCC" ,{0, -1, -1, -1, 0x1c, -1, -1, -1}},
{"SEX" ,{0, 0x1d, -1, -1, -1, -1, -1, -1}},
{"EXG" ,{0, -1, 0x1e, -1, -1, -1, -1, -1}},
{"TFR" ,{0, -1, 0x1f, -1, -1, -1, -1, -1}},
{"BRA" ,{0, -1, -1, 0x20, -1, -1, -1, -1}},
{"BRN" ,{0, -1, -1, 0x21, -1, -1, -1, -1}},
{"BHI" ,{0, -1, -1, 0x22, -1, -1, -1, -1}},
{"BLS" ,{0, -1, -1, 0x23, -1, -1, -1, -1}},
{"BCC" ,{0, -1, -1, 0x24, -1, -1, -1, -1}},
{"BHS" ,{0, -1, -1, 0x24, -1, -1, -1, -1}},
{"BCS" ,{0, -1, -1, 0x25, -1, -1, -1, -1}},
{"BLO" ,{0, -1, -1, 0x25, -1, -1, -1, -1}},
{"BNE" ,{0, -1, -1, 0x26, -1, -1, -1, -1}},
{"BEQ" ,{0, -1, -1, 0x27, -1, -1, -1, -1}},
{"BVC" ,{0, -1, -1, 0x28, -1, -1, -1, -1}},
{"BVS" ,{0, -1, -1, 0x29, -1, -1, -1, -1}},
{"BPL" ,{0, -1, -1, 0x2a, -1, -1, -1, -1}},
{"BMI" ,{0, -1, -1, 0x2b, -1, -1, -1, -1}},
{"BGE" ,{0, -1, -1, 0x2c, -1, -1, -1, -1}},
{"BLT" ,{0, -1, -1, 0x2d, -1, -1, -1, -1}},
{"BGT" ,{0, -1, -1, 0x2e, -1, -1, -1, -1}},
{"BLE" ,{0, -1, -1, 0x2f, -1, -1, -1, -1}},
{"LEAX" ,{0, -1, -1, -1, -1, -1, 0x30, -1}},
{"LEAY" ,{0, -1, -1, -1, -1, -1, 0x31, -1}},
{"LEAS" ,{0, -1, -1, -1, -1, -1, 0x32, -1}},
{"LEAU" ,{0, -1, -1, -1, -1, -1, 0x33, -1}},
{"PSHS" ,{0, -1, 0x34, -1, -1, -1, -1, -1}},
{"PULS" ,{0, -1, 0x35, -1, -1, -1, -1, -1}},
{"PSHU" ,{0, -1, 0x36, -1, -1, -1, -1, -1}},
{"PULU" ,{0, -1, 0x37, -1, -1, -1, -1, -1}},
{"RTS" ,{0, 0x39, -1, -1, -1, -1, -1, -1}},
{"ABX" ,{0, 0x3a, -1, -1, -1, -1, -1, -1}},
{"RTI" ,{0, 0x3b, -1, -1, -1, -1, -1, -1}},
{"CWAI" ,{0, -1, -1, -1, 0x3c, -1, -1, -1}},
{"MUL" ,{0, 0x3d, -1, -1, -1, -1, -1, -1}},
{"RESET" ,{0, 0x3e, -1, -1, -1, -1, -1, -1}},
{"SWI" ,{0, 0x3f, -1, -1, -1, -1, -1, -1}},
{"NEGA" ,{0, 0x40, -1, -1, -1, -1, -1, -1}},
{"COMA" ,{0, 0x43, -1, -1, -1, -1, -1, -1}},
{"LSRA" ,{0, 0x44, -1, -1, -1, -1, -1, -1}},
{"RORA" ,{0, 0x46, -1, -1, -1, -1, -1, -1}},
{"ASRA" ,{0, 0x47, -1, -1, -1, -1, -1, -1}},
{"ASLA" ,{0, 0x48, -1, -1, -1, -1, -1, -1}},
{"LSLA" ,{0, 0x48, -1, -1, -1, -1, -1, -1}},
{"ROLA" ,{0, 0x49, -1, -1, -1, -1, -1, -1}},
{"DECA" ,{0, 0x4a, -1, -1, -1, -1, -1, -1}},
{"INCA" ,{0, 0x4c, -1, -1, -1, -1, -1, -1}},
{"TSTA" ,{0, 0x4d, -1, -1, -1, -1, -1, -1}},
{"CLRA" ,{0, 0x4f, -1, -1, -1, -1, -1, -1}},
{"NEGB" ,{0, 0x50, -1, -1, -1, -1, -1, -1}},
{"COMB" ,{0, 0x53, -1, -1, -1, -1, -1, -1}},
{"LSRB" ,{0, 0x54, -1, -1, -1, -1, -1, -1}},
{"RORB" ,{0, 0x56, -1, -1, -1, -1, -1, -1}},
{"ASRB" ,{0, 0x57, -1, -1, -1, -1, -1, -1}},
{"ASLB" ,{0, 0x58, -1, -1, -1, -1, -1, -1}},
{"LSLB" ,{0, 0x58, -1, -1, -1, -1, -1, -1}},
{"ROLB" ,{0, 0x59, -1, -1, -1, -1, -1, -1}},
{"DECB" ,{0, 0x5a, -1, -1, -1, -1, -1, -1}},
{"INCB" ,{0, 0x5c, -1, -1, -1, -1, -1, -1}},
{"TSTB" ,{0, 0x5d, -1, -1, -1, -1, -1, -1}},
{"CLRB" ,{0, 0x5f, -1, -1, -1, -1, -1, -1}},
{"SUBA" ,{0, -1, -1, -1, 0x80, 0x90, 0xa0, 0xb0}},
{"CMPA" ,{0, -1, -1, -1, 0x81, 0x91, 0xa1, 0xb1}},
{"SBCA" ,{0, -1, -1, -1, 0x82, 0x92, 0xa2, 0xb2}},
{"SUBD" ,{0, -1, -1, -1, 0x83, 0x93, 0xa3, 0xb3}},
{"ANDA" ,{0, -1, -1, -1, 0x84, 0x94, 0xa4, 0xb4}},
{"BITA" ,{0, -1, -1, -1, 0x85, 0x95, 0xa5, 0xb5}},
{"LDA" ,{0, -1, -1, -1, 0x86, 0x96, 0xa6, 0xb6}},
{"EORA" ,{0, -1, -1, -1, 0x88, 0x98, 0xa8, 0xb8}},
{"ADCA" ,{0, -1, -1, -1, 0x89, 0x99, 0xa9, 0xb9}},
{"ORA" ,{0, -1, -1, -1, 0x8a, 0x9a, 0xaa, 0xba}},
{"ADDA" ,{0, -1, -1, -1, 0x8b, 0x9b, 0xab, 0xbb}},
{"CMPX" ,{0, -1, -1, -1, 0x8c, 0x9c, 0xac, 0xbc}},
{"BSR" ,{0, -1, -1, 0x8d, -1, -1, -1, -1}},
{"LDX" ,{0, -1, -1, -1, 0x8e, 0x9e, 0xae, 0xbe}},
{"STA" ,{0, -1, -1, -1, -1, 0x97, 0xa7, 0xb7}},
{"JSR" ,{0, -1, -1, -1, -1, 0x9d, 0xad, 0xbd}},
{"STX" ,{0, -1, -1, -1, -1, 0x9f, 0xaf, 0xbf}},
{"SUBB" ,{0, -1, -1, -1, 0xc0, 0xd0, 0xe0, 0xf0}},
{"CMPB" ,{0, -1, -1, -1, 0xc1, 0xd1, 0xe1, 0xf1}},
{"SBCB" ,{0, -1, -1, -1, 0xc2, 0xd2, 0xe2, 0xf2}},
{"ADDD" ,{0, -1, -1, -1, 0xc3, 0xd3, 0xe3, 0xf3}},
{"ANDB" ,{0, -1, -1, -1, 0xc4, 0xd4, 0xe4, 0xf4}},
{"BITB" ,{0, -1, -1, -1, 0xc5, 0xd5, 0xe5, 0xf5}},
{"LDB" ,{0, -1, -1, -1, 0xc6, 0xd6, 0xe6, 0xf6}},
{"EORB" ,{0, -1, -1, -1, 0xc8, 0xd8, 0xe8, 0xf8}},
{"ADCB" ,{0, -1, -1, -1, 0xc9, 0xd9, 0xe9, 0xf9}},
{"ORB" ,{0, -1, -1, -1, 0xca, 0xda, 0xea, 0xfa}},
{"ADDB" ,{0, -1, -1, -1, 0xcb, 0xdb, 0xeb, 0xfb}},
{"LDD" ,{0, -1, -1, -1, 0xcc, 0xdc, 0xec, 0xfc}},
{"LDU" ,{0, -1, -1, -1, 0xce, 0xde, 0xee, 0xfe}},
{"STB" ,{0, -1, -1, -1, -1, 0xd7, 0xe7, 0xf7}},
{"STD" ,{0, -1, -1, -1, -1, 0xdd, 0xed, 0xfd}},
{"STU" ,{0, -1, -1, -1, -1, 0xdf, 0xef, 0xff}},
{"LBRN" ,{0, -1, -1,0x1021, -1, -1, -1, -1}},
{"LBHI" ,{0, -1, -1,0x1022, -1, -1, -1, -1}},
{"LBLS" ,{0, -1, -1,0x1023, -1, -1, -1, -1}},
{"LBCC" ,{0, -1, -1,0x1024, -1, -1, -1, -1}},
{"LBHS" ,{0, -1, -1,0x1024, -1, -1, -1, -1}},
{"LBCS" ,{0, -1, -1,0x1025, -1, -1, -1, -1}},
{"LBLO" ,{0, -1, -1,0x1025, -1, -1, -1, -1}},
{"LBNE" ,{0, -1, -1,0x1026, -1, -1, -1, -1}},
{"LBEQ" ,{0, -1, -1,0x1027, -1, -1, -1, -1}},
{"LBVC" ,{0, -1, -1,0x1028, -1, -1, -1, -1}},
{"LBVS" ,{0, -1, -1,0x1029, -1, -1, -1, -1}},
{"LBPL" ,{0, -1, -1,0x102a, -1, -1, -1, -1}},
{"LBMI" ,{0, -1, -1,0x102b, -1, -1, -1, -1}},
{"LBGE" ,{0, -1, -1,0x102c, -1, -1, -1, -1}},
{"LBLT" ,{0, -1, -1,0x102d, -1, -1, -1, -1}},
{"LBGT" ,{0, -1, -1,0x102e, -1, -1, -1, -1}},
{"LBLE" ,{0, -1, -1,0x102f, -1, -1, -1, -1}},
{"SWI2" ,{0,0x103f, -1, -1, -1, -1, -1, -1}},
{"CMPD" ,{0, -1, -1, -1,0x1083,0x1093,0x10a3,0x10b3}},
{"CMPY" ,{0, -1, -1, -1,0x108c,0x109c,0x10ac,0x10bc}},
{"LDY" ,{0, -1, -1, -1,0x108e,0x109e,0x10ae,0x10be}},
{"STY" ,{0, -1, -1, -1, -1,0x109f,0x10af,0x10bf}},
{"LDS" ,{0, -1, -1, -1,0x10ce,0x10de,0x10ee,0x10fe}},
{"STS" ,{0, -1, -1, -1, -1,0x10df,0x10ef,0x10ff}},
{"SWI3" ,{0,0x113f, -1, -1, -1, -1, -1, -1}},
{"CMPU" ,{0, -1, -1, -1,0x1183,0x1193,0x11a3,0x11b3}},
{"CMPS" ,{0, -1, -1, -1,0x118c,0x119c,0x11ac,0x11bc}},
// 6309 0 1 2 3 4 5 6 7
// Mnem CPU Inher Reg Rela Imm Direct Ind Ext
// ---------------------------------------------------------------
{"SEXW" ,{1, 0x14, -1, -1, -1, -1, -1, -1}},
{"ADDR" ,{1, -1,0x1030, -1, -1, -1, -1, -1}},
{"ADCR" ,{1, -1,0x1031, -1, -1, -1, -1, -1}},
{"SUBR" ,{1, -1,0x1032, -1, -1, -1, -1, -1}},
{"SBCR" ,{1, -1,0x1033, -1, -1, -1, -1, -1}},
{"ANDR" ,{1, -1,0x1034, -1, -1, -1, -1, -1}},
{"ORR" ,{1, -1,0x1035, -1, -1, -1, -1, -1}},
{"EORR" ,{1, -1,0x1036, -1, -1, -1, -1, -1}},
{"CMPR" ,{1, -1,0x1037, -1, -1, -1, -1, -1}},
{"TFM" ,{1, -1,0x1138, -1, -1, -1, -1, -1}},
{"BITMD" ,{1, -1, -1, -1,0x113c, -1, -1, -1}},
{"LDMD" ,{1, -1, -1, -1,0x113d, -1, -1, -1}},
{"PSHSW" ,{1,0x1038, -1, -1, -1, -1, -1, -1}},
{"PULSW" ,{1,0x1039, -1, -1, -1, -1, -1, -1}},
{"PSHUW" ,{1,0x103A, -1, -1, -1, -1, -1, -1}},
{"PULUW" ,{1,0x103B, -1, -1, -1, -1, -1, -1}},
{"NEGD" ,{1,0x1040, -1, -1, -1, -1, -1, -1}},
{"COMD" ,{1,0x1043, -1, -1, -1, -1, -1, -1}},
{"LSRD" ,{1,0x1044, -1, -1, -1, -1, -1, -1}},
{"RORD" ,{1,0x1046, -1, -1, -1, -1, -1, -1}},
{"ASRD" ,{1,0x1047, -1, -1, -1, -1, -1, -1}},
{"ASLD" ,{1,0x1048, -1, -1, -1, -1, -1, -1}},
{"LSLD" ,{1,0x1048, -1, -1, -1, -1, -1, -1}},
{"ROLD" ,{1,0x1049, -1, -1, -1, -1, -1, -1}},
{"DECD" ,{1,0x104A, -1, -1, -1, -1, -1, -1}},
{"INCD" ,{1,0x104C, -1, -1, -1, -1, -1, -1}},
{"TSTD" ,{1,0x104D, -1, -1, -1, -1, -1, -1}},
{"CLRD" ,{1,0x104F, -1, -1, -1, -1, -1, -1}},
{"COMW" ,{1,0x1053, -1, -1, -1, -1, -1, -1}},
{"LSRW" ,{1,0x1054, -1, -1, -1, -1, -1, -1}},
{"RORW" ,{1,0x1056, -1, -1, -1, -1, -1, -1}},
{"ROLW" ,{1,0x1059, -1, -1, -1, -1, -1, -1}},
{"DECW" ,{1,0x105A, -1, -1, -1, -1, -1, -1}},
{"INCW" ,{1,0x105C, -1, -1, -1, -1, -1, -1}},
{"TSTW" ,{1,0x105D, -1, -1, -1, -1, -1, -1}},
{"CLRW" ,{1,0x105F, -1, -1, -1, -1, -1, -1}},
{"COME" ,{1,0x1143, -1, -1, -1, -1, -1, -1}},
{"DECE" ,{1,0x114A, -1, -1, -1, -1, -1, -1}},
{"INCE" ,{1,0x114C, -1, -1, -1, -1, -1, -1}},
{"TSTE" ,{1,0x114D, -1, -1, -1, -1, -1, -1}},
{"CLRE" ,{1,0x114F, -1, -1, -1, -1, -1, -1}},
{"COMF" ,{1,0x1153, -1, -1, -1, -1, -1, -1}},
{"DECF" ,{1,0x115A, -1, -1, -1, -1, -1, -1}},
{"INCF" ,{1,0x115C, -1, -1, -1, -1, -1, -1}},
{"TSTF" ,{1,0x115D, -1, -1, -1, -1, -1, -1}},
{"CLRF" ,{1,0x115F, -1, -1, -1, -1, -1, -1}},
{"OIM" ,{1, -1, -1, -1, -1, 0x01, 0x61, 0x71}},
{"AIM" ,{1, -1, -1, -1, -1, 0x02, 0x62, 0x72}},
{"EIM" ,{1, -1, -1, -1, -1, 0x05, 0x65, 0x75}},
{"TIM" ,{1, -1, -1, -1, -1, 0x0b, 0x6b, 0x7b}},
{"STW" ,{1, -1, -1, -1, -1,0x1097,0x10a7,0x10b7}},
{"STQ" ,{1, -1, -1, -1, -1,0x10dd,0x10ed,0x10fd}},
{"STE" ,{1, -1, -1, -1, -1,0x1197,0x11a7,0x11b7}},
{"STF" ,{1, -1, -1, -1, -1,0x11d7,0x11e7,0x11f7}},
{"LDQ" ,{1, -1, -1, -1, 0xcd,0x10dc,0x10ec,0x10fc}},
{"SUBW" ,{1, -1, -1, -1,0x1080,0x1090,0x10a0,0x10b0}},
{"CMPW" ,{1, -1, -1, -1,0x1081,0x1091,0x10a1,0x10b1}},
{"SBCD" ,{1, -1, -1, -1,0x1082,0x1092,0x10a2,0x10b2}},
{"ANDD" ,{1, -1, -1, -1,0x1084,0x1094,0x10a4,0x10b4}},
{"BITD" ,{1, -1, -1, -1,0x1085,0x1095,0x10a5,0x10b5}},
{"LDW" ,{1, -1, -1, -1,0x1086,0x1096,0x10a6,0x10b6}},
{"EORD" ,{1, -1, -1, -1,0x1088,0x1098,0x10a8,0x10b8}},
{"ADCD" ,{1, -1, -1, -1,0x1089,0x1099,0x10a9,0x10b9}},
{"ORD" ,{1, -1, -1, -1,0x108a,0x109a,0x10aa,0x10ba}},
{"ADDW" ,{1, -1, -1, -1,0x108b,0x109b,0x10ab,0x10bb}},
{"SUBE" ,{1, -1, -1, -1,0x1180,0x1190,0x11a0,0x11b0}},
{"CMPE" ,{1, -1, -1, -1,0x1181,0x1191,0x11a1,0x11b1}},
{"LDE" ,{1, -1, -1, -1,0x1186,0x1196,0x11a6,0x11b6}},
{"ADDE" ,{1, -1, -1, -1,0x118b,0x119b,0x11ab,0x11bb}},
{"DIVD" ,{1, -1, -1, -1,0x118d,0x119d,0x11ad,0x11bd}},
{"DIVQ" ,{1, -1, -1, -1,0x118e,0x119e,0x11ae,0x11be}},
{"MULD" ,{1, -1, -1, -1,0x118f,0x119f,0x11af,0x11bf}},
{"SUBF" ,{1, -1, -1, -1,0x11c0,0x11d0,0x11e0,0x11f0}},
{"CMPF" ,{1, -1, -1, -1,0x11c1,0x11d1,0x11e1,0x11f1}},
{"LDF" ,{1, -1, -1, -1,0x11c6,0x11d6,0x11e6,0x11f6}},
{"ADDF" ,{1, -1, -1, -1,0x11cb,0x11db,0x11eb,0x11fb}},
{"BAND" ,{1, -1, -1, -1, -1,0x1130, -1, -1}},
{"BIAND" ,{1, -1, -1, -1, -1,0x1131, -1, -1}},
{"BOR" ,{1, -1, -1, -1, -1,0x1132, -1, -1}},
{"BIOR" ,{1, -1, -1, -1, -1,0x1133, -1, -1}},
{"BEOR" ,{1, -1, -1, -1, -1,0x1134, -1, -1}},
{"BIEOR" ,{1, -1, -1, -1, -1,0x1135, -1, -1}},
{"LDBT" ,{1, -1, -1, -1, -1,0x1136, -1, -1}},
{"STBT" ,{1, -1, -1, -1, -1,0x1137, -1, -1}}
};
#define DIMOP_6809 139
#define DIMOP_6309 (sizeof(Mat) / sizeof(struct MatStruct))
int DimOp = DIMOP_6309;
// register Q is not included, it appears never as operand
// and is only part of the mnemonic
const char *Register_6309[] =
{
// 0 1 2 3 4 5 6 7 8 9 A B C D E F
"D","X","Y","U","S","PC","W","V","A","B","CC","DP","*","0","E","F"
};
const char *Register_6809[] =
{
// 0 1 2 3 4 5 6 7 8 9 A B C D E F
"D","X","Y","U","S","PC","-","-","A","B","CC","DP","*","*","-","-"
};
const char **RegisterNames = Register_6309;
struct PushStruct
{
char Reg[3];
int Val;
} PushList[10] =
{
{"CC" , 0x01}, // bit 0
{"A" , 0x02}, // bit 1
{"B" , 0x04}, // bit 2
{"D" , 0x06}, // bit 1 and 2
{"DP" , 0x08}, // bit 3
{"X" , 0x10}, // bit 4
{"Y" , 0x20}, // bit 5
{"S" , 0x40}, // bit 6
{"U" , 0x40}, // bit 6
{"PC" , 0x80} // bit 7
};
#define UNDEF (int) 0xff0000
int SkipHex = 0; // switch on with -x
int Debug = 0; // switch on with -d
int LiNo = 0; // line number of current file
int WithLiNo = 0; // print line numbers in listing if set
int TotalLiNo = 0; // total line number
int Preprocess = 0; // print preprocessed source file <file.pp>
int Quiet = 0; // switch for quiet mode
int ERRMAX = 10; // stop assemby after ERRMAX errors
int EnumValue = -1; // last used ENUM value
int MacLev; // macro nesting level
int MacList = 1; // macro listing option
int ModuleStart; // address of a module
int Optimize; // branch and jump omtimization
int FormLn; // lines per page [inactive]
int DP; // current direct page
int CodeStyle; // 1: operand has no spaces (old form)
int MneIndex; // current mnemonic
int oc; // op code
int pb; // post byte
int am; // address mode
int il; // instruction length
int ol; // opcode length
int pl; // postbyte length
int ql; // operand length
int pc = -1; // program counter
int bss; // bss counter
int nops; // snychronisation nops
int Phase; // phase or pass of 2-pass assembler
int IfLevel; // if nesting level
int Skipping; // inside 'false' branch
int SkipLine[10]; // skipping value for each nesting level
int ForcedEnd; // Triggered by END command
int IgnoreCase; // 1: Ignore case for symbols
int ForcedMode; // -1: direct page, +1: extended
int optc; // count optimization messages
int Preset; // value for initialisation
// local labels
#define PLUMAX 200
int minlab[11];
int plucnt[11];
int plulab[11][PLUMAX];
// Filenames
#define FNSIZE 256
char *Src; // source file
char Lst[FNSIZE]; // list file
char Pre[FNSIZE]; // preprocessed file
char Opt[FNSIZE]; // optimzation hints
int GenStart = 0x10000 ; // Lowest assemble address
int GenEnd = 0 ; // Highest assemble address
// These arrays hold the parameter for storage files
#define SFMAX 20
int SFA[SFMAX]; // start address of data block
int SFL[SFMAX]; // length of data block
char *SFF[SFMAX]; // filename
int SFE[SFMAX]; // execution start address
int SFR[SFMAX]; // number of records in a S19 file
int SFT[SFMAX]; // file format
int StoreCount = 0; // number of segments to store
enum OutfileFormat { BINARY, SRECORD, SPARROW };
signed char ADL[0x10000];
// organize nesting of include files
struct IncludeStackStruct
{
FILE *fp;
int LiNo;
char *Src;
} IncludeStack[100];
int IncludeLevel;
#define ML 256
int ArgPtr[10]; // macro argument pointer
char Line[ML]; // source line
char Label[ML]; // current label
char MacArgs[ML]; // macro arguments
unsigned char Operand[ML]; // binary operand
char OpText[ML]; // operand source
char Comment[ML]; // comment source
char Hint[ML]; // optimization hints
char Scope[ML]; // for local symbols
char datebuffer [80];
// state of label definition
// defined or BSS or defined by position
#define LDEF 1
#define LBSS 2
#define LPOS 3
#define MAXLAB 8000
struct LabelStruct
{
char *Name; // Label name - case sensitive
int Address; // Range 0 - 65536
int Bytes; // Length of object (string for example)
int Locked; // Cannot change value
int NumRef; // # of references
int *Ref; // list of references
int *Att; // list of attributes
} lab[MAXLAB];
int Labels; // number of labels
// maximum number of macros
#define MAXMAC 200
// special character in macros used to mark argument
#define CHAMAC '`'
struct MacroStruct
{
char *Name; // MACRO Name(arg,arg,...) (up to 10 arguments)
char *Body; // "Line1\nLine2\n ... LastLine\n"
int Narg; // # of macro arguments (0-10)
int Cola; // column of macro definition (for pretty printing)
int Type; // 0: name(arg1,arg2)) 1: name arg1,arg2
} Mac[MAXMAC];
char *MacPtr[MAXMAC]; // pointer inside macro body
int Macros; // total number of macros
char Cstat[26];
// *******
// MneStat
// *******
void MneStat(void)
{
unsigned int i,j;
for (i=0 ; i < DIMOP_6309 ; ++i)
for (j=0 ; j < strlen(Mat[i].Mne) ; ++j)
++Cstat[Mat[i].Mne[j]-'A'];
for (i=0 ; i < 26 ; ++i)
printf("%c:%3d\n",'A'+i,Cstat[i]);
}
// *********
// SkipSpace
// *********
char *SkipSpace(char *p)
{
if (*p) while (isspace(*p)) ++p;
return p;
}
// ********
// StrMatch
// ********
char *StrMatch(char *s, const char *m)
{
int i,j,k,l;
k = strlen(s);
l = strlen(m);
for (j = 0 ; j <= k-l ; ++j)
{
if (s[j] == ';') break; // don't search comment
for (i = 0 ; i < l ; ++i)
{
if (toupper(s[j+i]) != toupper(m[i])) break;
}
if (i == l) return (s + j);
}
return NULL;
}
// Check if keyword (m) is in string (s)
// Make sure, it's not part of a larger word
// by checking the characters before and after
// ******
// StrKey
// ******
char *StrKey(char *s, const char *m)
{
char *r = StrMatch(s,m);
if (r) // match was true
{
if ((r > s && isalnum(*(r-1))) || // check before
(isalnum(*(r+strlen(m))))) r = NULL; // check after
}
return r;
}
// ****
// isym
// ****
int isym(char c)
{
return (c == '.' || c == '$' || c == '_' || isalnum(c));
}
// *********
// GetSymbol
// *********
char *GetSymbol(char *p, char *s)
{
if (*p == '.') // expand local symbol
{
if (Scope[0])
{
strcpy(s,Scope);
s += strlen(s);
*s++ = *p++;