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Add ability for registry to specify input (IC) file variable names for constituents #259

Merged
merged 12 commits into from
Apr 19, 2024
Merged

Add ability for registry to specify input (IC) file variable names for constituents #259

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b4739c4
Add new constituent 'variables' to registry, and clean-up schema file.
nusbaume Apr 4, 2024
11fd904
Update registry generator to pass out new constituent IC names dictio…
nusbaume Apr 5, 2024
d3ebe9f
Remove const. dictionary (not needed), and update code generation and…
nusbaume Apr 8, 2024
1e8dde6
Fix CCPP dimension error in unit tests.
nusbaume Apr 8, 2024
df9a0a0
Fix unit test failures, and change order of variable index checking n…
nusbaume Apr 9, 2024
1f9b971
Fix CAM-SIMA build problems.
nusbaume Apr 11, 2024
c92e6d6
Check for standard name in ncdata_check file if input names aren't fo…
nusbaume Apr 12, 2024
c7972df
Move stdname converter script to new 'tools' directory.
nusbaume Apr 12, 2024
63b05e1
Fix unit tests, and remove unused 'config' variable from registry gen…
nusbaume Apr 14, 2024
65842b3
Merge remote-tracking branch 'upstream/development' into registry_con…
nusbaume Apr 14, 2024
d1de970
Fix unit test broken by missed merge.
nusbaume Apr 14, 2024
f6e6a34
Impelement code review requests.
nusbaume Apr 18, 2024
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9 changes: 4 additions & 5 deletions cime_config/cam_autogen.py
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Original file line number Diff line number Diff line change
Expand Up @@ -359,8 +359,7 @@ def _update_genccpp_dir(utility_files, genccpp_dir):

###############################################################################
def generate_registry(data_search, build_cache, atm_root, bldroot,
source_mods_dir, dycore, gen_fort_indent,
reg_config=None):
source_mods_dir, dycore, gen_fort_indent):
###############################################################################
"""
Generate the CAM data source and metadata from the registry,
Expand All @@ -382,14 +381,14 @@ def generate_registry(data_search, build_cache, atm_root, bldroot,
if os.path.exists(genreg_dir):
do_gen_registry = build_cache.registry_mismatch(gen_reg_file,
registry_files,
dycore, reg_config)
dycore)
else:
os.makedirs(genreg_dir)
do_gen_registry = True
# End if
if do_gen_registry:
for reg_file in registry_files:
retvals = gen_registry(reg_file, dycore, reg_config, genreg_dir,
retvals = gen_registry(reg_file, dycore, genreg_dir,
gen_fort_indent, source_mods_dir, atm_root,
logger=_LOGGER, schema_paths=data_search,
error_on_no_validate=True)
Expand All @@ -407,7 +406,7 @@ def generate_registry(data_search, build_cache, atm_root, bldroot,
# Save build details in the build cache
reg_file_paths = [x.file_path for x in reg_file_list if x.file_path]
build_cache.update_registry(gen_reg_file, registry_files, dycore,
reg_config, reg_file_paths, ic_names)
reg_file_paths, ic_names)
else:
# If we did not run the registry generator, retrieve info from cache
reg_file_paths = build_cache.reg_file_list()
Expand Down
19 changes: 6 additions & 13 deletions cime_config/cam_build_cache.py
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Original file line number Diff line number Diff line change
Expand Up @@ -215,7 +215,6 @@ def __init__(self, build_cache):
self.__gen_init_file = None
self.__registry_files = {}
self.__dycore = None
self.__config = None
self.__sdfs = {}
self.__schemes = {}
self.__host_files = {}
Expand Down Expand Up @@ -244,8 +243,6 @@ def __init__(self, build_cache):
self.__registry_files[new_entry.key] = new_entry
elif item.tag == 'dycore':
self.__dycore = item.text
elif item.tag == 'config':
self.__config = item.text
elif item.tag == 'reg_gen_file':
self.__reg_gen_files.append(clean_xml_text(item))
elif item.tag == 'ic_name_entry':
Expand Down Expand Up @@ -316,11 +313,10 @@ def __init__(self, build_cache):
# end if

def update_registry(self, gen_reg_file, registry_source_files,
dycore, config, reg_file_list, ic_names):
dycore, reg_file_list, ic_names):
"""Replace the registry cache data with input data
"""
self.__dycore = dycore
self.__config = config
self.__gen_reg_file = FileStatus(gen_reg_file, 'generate_registry_file')
self.__registry_files = {}
for rfile in registry_source_files:
Expand Down Expand Up @@ -393,8 +389,6 @@ def write(self):
# end for
dycore = ET.SubElement(registry, 'dycore')
dycore.text = self.__dycore
config = ET.SubElement(registry, 'config')
config.text = self.__config
for rgen_file in self.__reg_gen_files:
rgen_entry = ET.SubElement(registry, 'reg_gen_file')
rgen_entry.text = rgen_file
Expand Down Expand Up @@ -450,14 +444,13 @@ def write(self):
#End with

def registry_mismatch(self, gen_reg_file, registry_source_files,
dycore, config):
dycore):
"""
Determine if the registry input data differs from the data
stored in our cache. Return True if the data differs.
"""
mismatch = False
mismatch = (not self.__dycore) or (self.__dycore != dycore)
mismatch = mismatch or (self.__config != config)
if not mismatch:
mismatch = self.__gen_reg_file.hash_mismatch(gen_reg_file)
# end if
Expand All @@ -467,7 +460,7 @@ def registry_mismatch(self, gen_reg_file, registry_source_files,
my_reg_keys = set(self.__registry_files.keys())
test_reg_keys = {FileStatus.gen_key(x)
for x in registry_source_files}
mismatch = (my_reg_keys != test_reg_keys)
mismatch = my_reg_keys != test_reg_keys
for ref_file in registry_source_files:
if mismatch:
break
Expand Down Expand Up @@ -522,7 +515,7 @@ def ccpp_mismatch(self, sdfs, scheme_files, host_files,
if not mismatch:
my_scheme_keys = set(self.__schemes.keys())
test_scheme_keys = {FileStatus.gen_key(x) for x in scheme_files}
mismatch = (my_scheme_keys != test_scheme_keys)
mismatch = my_scheme_keys != test_scheme_keys
for ref_file in scheme_files:
if mismatch:
break
Expand All @@ -537,7 +530,7 @@ def ccpp_mismatch(self, sdfs, scheme_files, host_files,
if not mismatch:
my_host_keys = set(self.__host_files.keys())
test_host_keys = {FileStatus.gen_key(x) for x in host_files}
mismatch = (my_host_keys != test_host_keys)
mismatch = my_host_keys != test_host_keys
for ref_file in host_files:
if mismatch:
break
Expand All @@ -564,7 +557,7 @@ def xml_nl_mismatch(self, create_nl_file, xml_files):
# Note that this method will ignore duplicated files.
my_xml_keys = set(self.__xml_files.keys())
test_xml_keys = {FileStatus.gen_key(x) for x in xml_files.values()}
mismatch = (my_xml_keys != test_xml_keys)
mismatch = my_xml_keys != test_xml_keys
for ref_file in xml_files.values():
if mismatch:
break
Expand Down
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