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PE_VCD.vcd
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$date
Tue Jun 22 13:33:27 2021
$end
$version
Icarus Verilog
$end
$timescale
1ns
$end
$scope module PE_tb $end
$scope module CUT $end
$var wire 1 ! clk $end
$var wire 8 " di [7:0] $end
$var wire 8 # do [7:0] $end
$var wire 1 $ rst $end
$var wire 24 % si [23:0] $end
$var wire 24 & so [23:0] $end
$var wire 8 ' wi [7:0] $end
$var wire 8 ( wo [7:0] $end
$var wire 24 ) soReg_input [23:0] $end
$var reg 8 * diReg [7:0] $end
$var reg 24 + soReg [23:0] $end
$var reg 8 , wiReg [7:0] $end
$scope module MAC_UNIT $end
$var wire 8 - di [7:0] $end
$var wire 24 . si [23:0] $end
$var wire 8 / wi [7:0] $end
$var wire 24 0 so [23:0] $end
$var wire 16 1 multOut [15:0] $end
$scope module ADD $end
$var wire 24 2 b [23:0] $end
$var wire 24 3 o [23:0] $end
$var wire 16 4 a [15:0] $end
$upscope $end
$scope module MUL $end
$var wire 8 5 x [7:0] $end
$var wire 8 6 y [7:0] $end
$var wire 16 7 po [15:0] $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
b0 7
b0 6
b0 5
b0 4
bx 3
bx 2
b0 1
bx 0
b0 /
bx .
b0 -
b0 ,
b0 +
b0 *
bx )
b0 (
bx '
b0 &
bx %
1$
b0 #
bx "
0!
$end
#17
1!
#34
0!
#50
b1 )
b1 0
b1 3
b1 %
b1 .
b1 2
b1010 '
b1010 "
0$
#51
b1 &
b1 +
b1100101 )
b1100101 0
b1100101 3
b1100100 1
b1100100 4
b1100100 7
b1010 (
b1010 ,
b1010 /
b1010 6
b1010 #
b1010 *
b1010 -
b1010 5
1!
#68
0!
#85
b1100101 &
b1100101 +
1!
#100
b1110011 )
b1110011 0
b1110011 3
b1111 %
b1111 .
b1111 2
b10100 '
b11110110 "
#102
0!
#119
b1110011 &
b1110011 +
b10100 (
b10100 ,
b10100 /
b10100 6
b111111111111111101000111 )
b111111111111111101000111 0
b111111111111111101000111 3
b1111111100111000 1
b1111111100111000 4
b1111111100111000 7
b11110110 #
b11110110 *
b11110110 -
b11110110 5
1!
#136
0!
#150
b11111111 '
b1100 "
#153
b111111111111111101000111 &
b111111111111111101000111 +
b11111111 (
b11111111 ,
b11111111 /
b11111111 6
b11 )
b11 0
b11 3
b1111111111110100 1
b1111111111110100 4
b1111111111110100 7
b1100 #
b1100 *
b1100 -
b1100 5
1!
#170
0!
#187
b11 &
b11 +
1!
#200