From abc6d65a85d90f90067deb76d0aeba78e5683d56 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 25 Jul 2024 10:03:59 +0200 Subject: [PATCH 01/56] soc/intel/baytrail: Change NC GPIO to input pull up 20K MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All Intel SOCs use input pullup 20K as not connected GPIO. Also GPIO output mode may be harmful. Signed-off-by: Michał Żygowski --- src/soc/intel/baytrail/include/soc/gpio.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/baytrail/include/soc/gpio.h b/src/soc/intel/baytrail/include/soc/gpio.h index ba94c5d5bea..cc32b9ab940 100644 --- a/src/soc/intel/baytrail/include/soc/gpio.h +++ b/src/soc/intel/baytrail/include/soc/gpio.h @@ -325,7 +325,7 @@ #define GPIO_INPUT_LEGACY GPIO_INPUT_LEGACY_NOPU #define GPIO_INPUT_PU GPIO_INPUT_PU_20K #define GPIO_INPUT_PD GPIO_INPUT_PD_20K -#define GPIO_NC GPIO_OUT_HIGH +#define GPIO_NC GPIO_INPUT_PU_20K #define GPIO_DEFAULT GPIO_FUNC0 /* 16 DirectIRQs per supported bank */ From 9b626ff28d64f5ae80d37d290892d2dd2625ca27 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Wed, 15 May 2024 15:49:09 +0200 Subject: [PATCH 02/56] southbridge/intel/common/firmware: Use the ME file path directly MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fixes a problem where changing ME binary in the config would not result in the desired ME binary be included in the rebuilt coreboot binary. Signed-off-by: Michał Żygowski --- src/southbridge/intel/common/firmware/Makefile.mk | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/southbridge/intel/common/firmware/Makefile.mk b/src/southbridge/intel/common/firmware/Makefile.mk index c97c61972ba..97e01fb046e 100644 --- a/src/southbridge/intel/common/firmware/Makefile.mk +++ b/src/southbridge/intel/common/firmware/Makefile.mk @@ -30,8 +30,7 @@ OBJ_ME_BIN := $(obj)/me.bin ifneq ($(CONFIG_STITCH_ME_BIN),y) -$(OBJ_ME_BIN): $(call strip_quotes,$(CONFIG_ME_BIN_PATH)) - cp $< $@ +OBJ_ME_BIN := $(call strip_quotes,$(CONFIG_ME_BIN_PATH)) endif From 96cc592e8fd694102e72f475210529187b54610b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Wed, 24 Apr 2024 23:00:46 +0200 Subject: [PATCH 03/56] src/soc/intel/baytrail/northcluster.c: add NOOP set_resources to avoid an error in log MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- src/soc/intel/baytrail/northcluster.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c index 509efbe2aa8..5ba39215e13 100644 --- a/src/soc/intel/baytrail/northcluster.c +++ b/src/soc/intel/baytrail/northcluster.c @@ -123,6 +123,7 @@ static void nc_generate_ssdt(const struct device *dev) static struct device_operations nc_ops = { .read_resources = nc_read_resources, + .set_resources = noop_set_resources, .acpi_fill_ssdt = nc_generate_ssdt, .ops_pci = &soc_pci_ops, }; From ab1c454dccc4410ebfcf6b1daa7ee3e02239e5cc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Wed, 24 Apr 2024 23:01:10 +0200 Subject: [PATCH 04/56] src/soc/intel/baytrail: Fix the FUNC_DIS bits description MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit BayTrail EDS is correct. MIPI is disabled in a different manner which does not use FUNC_DIS register. Signed-off-by: Michał Żygowski --- src/soc/intel/baytrail/include/soc/pm.h | 5 +---- src/soc/intel/baytrail/southcluster.c | 2 -- 2 files changed, 1 insertion(+), 6 deletions(-) diff --git a/src/soc/intel/baytrail/include/soc/pm.h b/src/soc/intel/baytrail/include/soc/pm.h index 9d276ec1343..0d3c61bd258 100644 --- a/src/soc/intel/baytrail/include/soc/pm.h +++ b/src/soc/intel/baytrail/include/soc/pm.h @@ -66,13 +66,10 @@ #define HSUART1_DIS (1 << 3) #define HSUART2_DIS (1 << 4) #define SPI_DIS (1 << 5) -/* Baytrail EDS says this should be 11 but it appears to be wrong */ -#define MIPI_DIS (1 << 8) +#define MMC_DIS (1 << 8) #define SDIO_DIS (1 << 9) #define SD_DIS (1 << 10) -/* Baytrail EDS says these should be 8 but it appears to be wrong */ #define MMC45_DIS (1 << 11) -#define MMC_DIS (1 << 11) #define HDA_DIS (1 << 12) #define LPE_DIS (1 << 13) #define OTG_DIS (1 << 14) diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 45c61d30f69..dcfef541400 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -432,8 +432,6 @@ static void sc_disable_devfn(struct device *dev) uint32_t mask2 = 0; switch (dev->path.pci.devfn) { - SET_DIS_MASK(MIPI); - break; SET_DIS_MASK(SDIO); break; SET_DIS_MASK(SD); From 6869349dd52ccd5412cd61696408030fe4cbc541 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Wed, 24 Apr 2024 23:01:48 +0200 Subject: [PATCH 05/56] src/device/pciexp_device.c: Control ASPM with Kconfig option MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Even if PCIEXP_ASPM is not selected, it doesn't mean all PCIe devices will have the correct ASPM disabled state set. Ensure the ASPM is disabled if it is not selected. Signed-off-by: Michał Żygowski --- src/device/pciexp_device.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index 660bdb3ad79..08a0d3c21cd 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -576,7 +576,7 @@ static void pciexp_enable_aspm(struct device *root, unsigned int root_cap, if (exit_latency >= 0 && exit_latency <= ok_latency) apmc |= PCIE_ASPM_L1; - if (apmc != PCIE_ASPM_NONE) { + if (CONFIG(PCIEXP_ASPM) && apmc != PCIE_ASPM_NONE) { /* Set APMC in root port first */ lnkctl = pci_read_config16(root, root_cap + PCI_EXP_LNKCTL); lnkctl |= apmc; @@ -586,9 +586,22 @@ static void pciexp_enable_aspm(struct device *root, unsigned int root_cap, lnkctl = pci_read_config16(endp, endp_cap + PCI_EXP_LNKCTL); lnkctl |= apmc; pci_write_config16(endp, endp_cap + PCI_EXP_LNKCTL, lnkctl); + } else { + /* Disable ASPM in root port first */ + lnkctl = pci_read_config16(root, root_cap + PCI_EXP_LNKCTL); + lnkctl &= ~3; + pci_write_config16(root, root_cap + PCI_EXP_LNKCTL, lnkctl); + + /* Disable ASPM in endpoint device next */ + lnkctl = pci_read_config16(endp, endp_cap + PCI_EXP_LNKCTL); + lnkctl &= ~3; + pci_write_config16(endp, endp_cap + PCI_EXP_LNKCTL, lnkctl); } - printk(BIOS_INFO, "ASPM: Enabled %s\n", aspm_type_str[apmc]); + if (CONFIG(PCIEXP_ASPM)) + printk(BIOS_INFO, "ASPM: Enabled %s\n", aspm_type_str[apmc]); + else + printk(BIOS_INFO, "ASPM: Disabled\n"); } static void pciexp_dev_set_max_payload_size(struct device *dev, unsigned int max_payload) @@ -714,8 +727,7 @@ static void pciexp_tune_dev(struct device *dev) pciexp_config_L1_sub_state(root, dev); /* Check for and enable ASPM */ - if (CONFIG(PCIEXP_ASPM)) - pciexp_enable_aspm(root, root_cap, dev, cap); + pciexp_enable_aspm(root, root_cap, dev, cap); } /* Clear PCIe Lane Error Status */ From e52d9e54df3d6e628cd4763817546271664f47dc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Wed, 24 Apr 2024 23:02:07 +0200 Subject: [PATCH 06/56] src/soc/intel/baytrail/Kconfig: Do not select PCIE_ASPM MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Leave the choice to enable ASPM to the user via Kconfig. Signed-off-by: Michał Żygowski --- src/soc/intel/baytrail/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 97a5a1ce708..9775893a6bc 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -14,7 +14,6 @@ config SOC_INTEL_BAYTRAIL select SOUTHBRIDGE_INTEL_COMMON_RESET select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT - select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK select REG_SCRIPT select RTC From 51940045905f489e5714f17476cf5f93ce648400 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Wed, 24 Apr 2024 23:04:23 +0200 Subject: [PATCH 07/56] src/soc/intel/baytrail/lpss.c: Configure INT_PIN as in FSP solution MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Native code misses the interrupt configuration for LPSS devices. Replicate the FSP default interrupt configuration. Signed-off-by: Michał Żygowski --- src/soc/intel/baytrail/include/soc/iosf.h | 2 + src/soc/intel/baytrail/lpss.c | 68 +++++++++++++++++++++++ 2 files changed, 70 insertions(+) diff --git a/src/soc/intel/baytrail/include/soc/iosf.h b/src/soc/intel/baytrail/include/soc/iosf.h index d4fcdf3f7b7..1bfa0033331 100644 --- a/src/soc/intel/baytrail/include/soc/iosf.h +++ b/src/soc/intel/baytrail/include/soc/iosf.h @@ -276,6 +276,8 @@ void iosf_ssus_write(int reg, uint32_t val); # define LPSS_CTL_PCI_CFG_DIS (1 << 20) # define LPSS_CTL_SNOOP (1 << 18) # define LPSS_CTL_NOSNOOP (1 << 19) +# define LPSS_CTL_INT_PIN_MASK (0xf << 2) +# define LPSS_CTL_INT_PIN_SHIFT 2 # define LPSS_CTL_PM_CAP_PRSNT (1 << 1) /* diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c index 9ed7c3b6d1f..e69765e802e 100644 --- a/src/soc/intel/baytrail/lpss.c +++ b/src/soc/intel/baytrail/lpss.c @@ -10,6 +10,7 @@ #include #include +#include #include #include #include @@ -155,6 +156,72 @@ static void i2c_set_pins(struct device *dev) } } +#define CASE_DEV(name_) \ + case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC) + +#define INTA 1 +#define INTB 2 +#define INTC 3 +#define INTD 4 + +static void dev_set_int_pin(struct device *dev, int iosf_reg) +{ + u32 val; + u8 pin = INTA; + + switch (dev->path.pci.devfn) { + CASE_DEV(SIO_DMA1): + pin = INTA; + break; + CASE_DEV(I2C1): + pin = INTC; + break; + CASE_DEV(I2C2): + pin = INTD; + break; + CASE_DEV(I2C3): + pin = INTB; + break; + CASE_DEV(I2C4): + pin = INTA; + break; + CASE_DEV(I2C5): + pin = INTC; + break; + CASE_DEV(I2C6): + pin = INTD; + break; + CASE_DEV(I2C7): + pin = INTB; + break; + CASE_DEV(SIO_DMA2): + pin = INTA; + break; + CASE_DEV(PWM1): + pin = INTD; + break; + CASE_DEV(PWM2): + pin = INTB; + break; + CASE_DEV(HSUART1): + pin = INTC; + break; + CASE_DEV(HSUART2): + pin = INTD; + break; + CASE_DEV(SPI): + pin = INTB; + break; + default: + return; + } + + val = iosf_lpss_read(iosf_reg); + val &= ~LPSS_CTL_INT_PIN_MASK; + val |= (pin << LPSS_CTL_INT_PIN_SHIFT); + iosf_lpss_write(iosf_reg, val); +} + static void i2c_disable_resets(struct device *dev) { /* Release the I2C devices from reset. */ @@ -193,6 +260,7 @@ static void lpss_init(struct device *dev) return; } dev_enable_snoop_and_pm(dev, iosf_reg); + dev_set_int_pin(dev, iosf_reg); i2c_disable_resets(dev); i2c_set_pins(dev); From 0366522dd4e8f44e5057bb75cf8c16dee9ba3083 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Wed, 24 Apr 2024 23:03:16 +0200 Subject: [PATCH 08/56] soc/intel/baytrail/southcluster.c: Handle OTG and MIPI disabling properly MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Disable OTG and MIPI as described in BayTrail BWG Vol. 2 (Document Number: 514148, Rev, 1.47). Signed-off-by: Michał Żygowski --- src/soc/intel/baytrail/include/soc/iosf.h | 6 +++ src/soc/intel/baytrail/southcluster.c | 46 +++++++++++++++++++++++ 2 files changed, 52 insertions(+) diff --git a/src/soc/intel/baytrail/include/soc/iosf.h b/src/soc/intel/baytrail/include/soc/iosf.h index 1bfa0033331..1504835e88c 100644 --- a/src/soc/intel/baytrail/include/soc/iosf.h +++ b/src/soc/intel/baytrail/include/soc/iosf.h @@ -239,6 +239,12 @@ void iosf_ssus_write(int reg, uint32_t val); #define PUNIT_SOC_POWER_BUDGET 0x02 #define PUNIT_SOC_ENERGY_CREDIT 0x03 +#define PUNIT_ISPSSPM0 0x39 +# define PUNIT_ISPSSPM0_ISPSSC_MASK (3 << 0) +# define PUNIT_ISPSSPM0_ISPSSC_SHIFT 0 +# define PUNIT_ISPSSPM0_ISPSSS_MASK (3 << 24) +# define PUNIT_ISPSSPM0_ISPSSS_SHIFT 24 +# define PUNIT_ISPSSPM0_FUSEDIS (1 << 26) #define PUNIT_PTMC 0x80 #define PUNIT_GFXT 0x88 #define PUNIT_VEDT 0x89 diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index dcfef541400..e4252f09f89 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -19,6 +19,7 @@ #include #include +#include #include #include #include @@ -415,6 +416,42 @@ static void sc_init(struct device *dev) * Common code for the south cluster devices. */ +static void disable_mipi_dev(struct device *dev) +{ + u32 val; + + /* + * ISP/IUNIT PCI D3hot request via PCI PM_CAP is ignored by HW. + * Requesting power state of ISP is done via P-unit. + * Check ISP current state and disable it if needed. + */ + val = iosf_punit_read(PUNIT_ISPSSPM0); + if ((val & PUNIT_ISPSSPM0_ISPSSS_MASK) == 0) { + printk(BIOS_DEBUG, "ISP subsystem powered on, requesting power off\n"); + iosf_punit_write(PUNIT_ISPSSPM0, val | PUNIT_ISPSSPM0_ISPSSC_MASK); + val = iosf_punit_read(PUNIT_ISPSSPM0); + if ((val & PUNIT_ISPSSPM0_ISPSSS_MASK) == 0) { + printk(BIOS_DEBUG, "ISP subsystem powered off\n"); + } + } else if ((val & PUNIT_ISPSSPM0_ISPSSS_MASK) == PUNIT_ISPSSPM0_ISPSSS_MASK) { + printk(BIOS_DEBUG, "ISP subsystem already powered off\n"); + } else { + printk(BIOS_WARNING, "ISP subsystem invalid power state\n"); + } + + /* Disable BARs */ + pci_write_config16(dev, PCI_COMMAND, 0); + pci_write_config16(dev, PCI_BASE_ADDRESS_0, 0); + pci_write_config16(dev, PCI_BASE_ADDRESS_1, 0); + pci_write_config16(dev, PCI_BASE_ADDRESS_2, 0); + pci_write_config16(dev, PCI_BASE_ADDRESS_3, 0); + pci_write_config16(dev, PCI_BASE_ADDRESS_4, 0); + pci_write_config16(dev, PCI_BASE_ADDRESS_5, 0); + + /* Disable DMA, MMIO access and PCICFG access */ + pci_update_config32(dev, 0xfc, ~0, (3 << 30) | (1 << 4)); +} + #define SET_DIS_MASK(name_) \ case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ mask |= name_ ## _DIS @@ -432,6 +469,9 @@ static void sc_disable_devfn(struct device *dev) uint32_t mask2 = 0; switch (dev->path.pci.devfn) { + case PCI_DEVFN(MIPI_DEV, MIPI_FUNC): + disable_mipi_dev(dev); + return; SET_DIS_MASK(SDIO); break; SET_DIS_MASK(SD); @@ -569,6 +609,9 @@ static int place_device_in_d3hot(struct device *dev) * Work around this by hard coding the offset. */ switch (dev->path.pci.devfn) { + case PCI_DEVFN(MIPI_DEV, MIPI_FUNC): + offset = 0x80; + break; case PCI_DEVFN(MMC_DEV, MMC_FUNC): offset = 0x80; break; @@ -584,6 +627,9 @@ static int place_device_in_d3hot(struct device *dev) case PCI_DEVFN(LPE_DEV, LPE_FUNC): offset = 0x80; break; + case PCI_DEVFN(OTG_DEV, OTG_FUNC): + offset = 0x80; + break; case PCI_DEVFN(SIO_DMA1_DEV, SIO_DMA1_FUNC): offset = 0x80; break; From 1962087bd5d67557fc17ebcbd71ef3a78281b4a8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Wed, 24 Apr 2024 23:06:26 +0200 Subject: [PATCH 09/56] soc/intel/baytrail/pcie.c: Add support for PCIe hotplug MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit By default FSP was configuring the ports as hotpluggable. Allow hotplug configuration based on Kconfig. Use the procedure described in Bay Trail BWG Vol.2 (Document Number: 514148, Rev, 1.47) to initialize PCIe port. Signed-off-by: Michał Żygowski --- src/soc/intel/baytrail/include/soc/pcie.h | 5 ++++ src/soc/intel/baytrail/pcie.c | 32 +++++++++++++++++++---- 2 files changed, 32 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/baytrail/include/soc/pcie.h b/src/soc/intel/baytrail/include/soc/pcie.h index 06dd1cefb68..bc68d0b6686 100644 --- a/src/soc/intel/baytrail/include/soc/pcie.h +++ b/src/soc/intel/baytrail/include/soc/pcie.h @@ -29,6 +29,9 @@ # define HPS (1 << 5) #define SLCTL_SLSTS 0x58 # define PDS (1 << 22) +# define HPE (1 << 5) +# define PDE (1 << 3) +# define ABE (1 << 0) #define DCAP2 0x64 # define OBFFS (0x3 << 18) # define LTRMS (1 << 11) @@ -67,6 +70,8 @@ # define LANECFG_SHIFT 14 # define LANECFG_MASK (0x3 << LANECFG_SHIFT) #define AERCH 0x100 +#define UEM 0x108 +# define CT (1 << 14) #define NFTS 0x314 #define L0SC 0x318 #define CFG2 0x320 diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c index de3f0c5b9b0..94d7abee32b 100644 --- a/src/soc/intel/baytrail/pcie.c +++ b/src/soc/intel/baytrail/pcie.c @@ -67,8 +67,6 @@ static const struct reg_script init_static_after_exit_latency[] = { /* Read and write back capability registers. */ REG_PCI_OR32(0x34, 0), REG_PCI_OR32(0x80, 0), - /* Retrain the link. */ - REG_PCI_OR16(LCTL, RL), REG_SCRIPT_END, }; @@ -81,10 +79,12 @@ static void byt_pcie_init(struct device *dev) REG_PCI_RMW32(LCAP, ~L1EXIT_MASK, 2 << (L1EXIT_SHIFT + pll_en_off)), REG_SCRIPT_NEXT(init_static_after_exit_latency), +#if !CONFIG(PCIEXP_HOTPLUG) /* Disable hot plug, set power to 10W, set slot number. */ REG_PCI_RMW32(SLCAP, ~(HPC | HPS), (1 << SLS_SHIFT) | (100 << SLV_SHIFT) | (root_port_offset(dev) << SLN_SHIFT)), +#endif /* Dynamic clock gating. */ REG_PCI_OR32(RPPGEN, RPDLCGEN | RPDBCGEN | RPSCGEN), REG_PCI_OR32(PWRCTL, RPL1SQPOL | RPDTSQPOL), @@ -94,6 +94,9 @@ static void byt_pcie_init(struct device *dev) reg_script_run_on_dev(dev, init_script); + if (pci_read_config32(dev, SLCTL_SLSTS) & PDS) + pci_update_config16(dev, LCTL, ~RL, RL); + if (is_first_port(dev)) { struct soc_intel_baytrail_config *config = config_of(dev); uint32_t reg = pci_read_config32(dev, RPPGEN); @@ -170,6 +173,19 @@ static u8 all_ports_no_dev_present(struct device *dev) static void check_device_present(struct device *dev) { + struct reg_script hotplug_port[] = { + REG_PCI_RMW32(PCIEALC, ~(1 << 26), 0), + /* Configure hot plug, set power to 10W, set slot number. */ + REG_PCI_RMW32(SLCAP, ~(HPC | HPS), + (1 << SLS_SHIFT) | (100 << SLV_SHIFT) | + (root_port_offset(dev) << SLN_SHIFT) | + (HPC | HPS)), + REG_PCI_RMW32(SLCTL_SLSTS, ~HPE, 0), + REG_PCI_OR32(SLCTL_SLSTS, (ABE | PDE)), + REG_PCI_OR32(UEM, CT), + REG_SCRIPT_END, + }; + /* Set slot implemented. */ pci_write_config32(dev, XCAP, pci_read_config32(dev, XCAP) | SI); @@ -177,19 +193,25 @@ static void check_device_present(struct device *dev) if (!(pci_read_config32(dev, SLCTL_SLSTS) & PDS)) { printk(BIOS_DEBUG, "No PCIe device present.\n"); if (is_first_port(dev)) { - if (all_ports_no_dev_present(dev)) { + if (all_ports_no_dev_present(dev) && !CONFIG(PCIEXP_HOTPLUG)) { reg_script_run_on_dev(dev, no_dev_behind_port); dev->enabled = 0; } } else { - reg_script_run_on_dev(dev, no_dev_behind_port); - dev->enabled = 0; + if (!CONFIG(PCIEXP_HOTPLUG)) { + reg_script_run_on_dev(dev, no_dev_behind_port); + dev->enabled = 0; + } } } else if (!dev->enabled) { /* Port is disabled, but device present. Disable link. */ pci_write_config32(dev, LCTL, pci_read_config32(dev, LCTL) | LD); + return; } + + if (CONFIG(PCIEXP_HOTPLUG)) + reg_script_run_on_dev(dev, hotplug_port); } static void byt_pcie_enable(struct device *dev) From 7da86deff7edc37a4d72e80b258604a28578cdd1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 25 Jul 2024 11:04:48 +0200 Subject: [PATCH 10/56] mainboard/intel/minnowmax/devicetree.cb: Use default FSP settings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- src/mainboard/intel/minnowmax/devicetree.cb | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/minnowmax/devicetree.cb b/src/mainboard/intel/minnowmax/devicetree.cb index 349e6cbda63..2e93e93e6ca 100644 --- a/src/mainboard/intel/minnowmax/devicetree.cb +++ b/src/mainboard/intel/minnowmax/devicetree.cb @@ -40,7 +40,7 @@ chip soc/intel/baytrail register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" # SD Card controller - register "sdcard_cap_low" = "0x036864b2" + register "sdcard_cap_low" = "0x076864b2" register "sdcard_cap_high" = "0x0" # VR PS2 control @@ -57,6 +57,7 @@ chip soc/intel/baytrail device cpu_cluster 0 on end device domain 0 on + subsystemid 0x8086 0x7270 inherit device pci 00.0 on end # 8086 0F00 - SoC router device pci 02.0 on end # 8086 0F31 - GFX micro HDMI device pci 03.0 off end # 8086 0F38 - MIPI From bb1b6974100d03f60972356fe1004ee9188de227 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 25 Jul 2024 11:05:18 +0200 Subject: [PATCH 11/56] mainboard/intel/minnowmax/devicetree.cb: Enable both SATA ports MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Minnowboard has two SATA ports: one on the standard SATA connector, second on the expansion I/O header. Signed-off-by: Michał Żygowski --- src/mainboard/intel/minnowmax/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/intel/minnowmax/devicetree.cb b/src/mainboard/intel/minnowmax/devicetree.cb index 2e93e93e6ca..de45a83747e 100644 --- a/src/mainboard/intel/minnowmax/devicetree.cb +++ b/src/mainboard/intel/minnowmax/devicetree.cb @@ -16,7 +16,7 @@ chip soc/intel/baytrail # SATA port enable mask (2 ports) - register "sata_port_map" = "0x1" + register "sata_port_map" = "0x3" register "sata_ahci" = "0x1" register "ide_legacy_combined" = "0x0" From fa97cc0ef04611d045486e6ecde2d9fe683a1cea Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 25 Jul 2024 11:06:43 +0200 Subject: [PATCH 12/56] mainboard/intel/minnowmax/devicetree.cb: Describe OTG controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Describe OTG controller in the devicetree. Also add comment about known issue with writing to OTG IOSF port that will cause a hang if OTG is disabled runtime using PMC FUNC_DIS. When OTG is disabled by a soft strap in the flash descriptor, the issue does not occur though. Signed-off-by: Michał Żygowski --- src/mainboard/intel/minnowmax/devicetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/intel/minnowmax/devicetree.cb b/src/mainboard/intel/minnowmax/devicetree.cb index de45a83747e..43203ebea60 100644 --- a/src/mainboard/intel/minnowmax/devicetree.cb +++ b/src/mainboard/intel/minnowmax/devicetree.cb @@ -67,6 +67,7 @@ chip soc/intel/baytrail device pci 13.0 on end # 8086 0F23 - SATA AHCI Onboard & HSEC device pci 14.0 on end # 8086 0F35 - USB XHCI - Onboard & HSEC - Enabling both EHCI and XHCI will default to EHCI if not changed at runtime device pci 15.0 on end # 8086 0F28 - LP Engine Audio LSEC + device pci 16.0 on end # 8086 0F37 - OTG Controller # Keep enabled to avoid hangs at perf_power_settings device pci 17.0 off end # 8086 0F50 - MMC Port device pci 18.0 on end # 8086 0F40 - SIO - DMA device pci 18.1 off end # 8086 0F41 - I2C Port 1 (0) From c6d6d327dfae9d9ca8bb517a561794d24a4e4c1b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 25 Apr 2024 00:19:45 +0200 Subject: [PATCH 13/56] src/soc/intel/baytrail/lpss.c: Add additional programming requirements per BWG MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Implement additional LPSS programming requirements per Bay Trail BWG Vol.2 (Document Number 514148, Rev, 1.47). These settings also reflect the the FSP behavior. Signed-off-by: Michał Żygowski --- src/soc/intel/baytrail/lpss.c | 153 ++++++++++++++++++++++++++++------ 1 file changed, 127 insertions(+), 26 deletions(-) diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c index e69765e802e..f65b726253d 100644 --- a/src/soc/intel/baytrail/lpss.c +++ b/src/soc/intel/baytrail/lpss.c @@ -18,6 +18,23 @@ #include "chip.h" +#define LPSS_SPI_CLOCK_PARAMS 0x400 +#define LPSS_UART_CLOCK_PARAMS 0x800 +# define LPSS_CLOCK_PARAMS_CLOCK_EN (1 << 0) +# define LPSS_CLOCK_PARAMS_CLOCK_UPDATE (1 << 31) +#define LPSS_SPI_SOFTWARE_RESET 0x404 +#define LPSS_SOFTWARE_RESET 0x804 +# define LPSS_SOFTWARE_RESET_FUNC (1 << 0) +# define LPSS_SOFTWARE_RESET_APB (1 << 1) + +/* Setting for UART 44.2368Mhz M/N = 0.442368 (0x1b00/0x3d09) x 100 Mhz */ +#define UART_CLOCK_44P2368_MHZ ((0x3d09 << 16) | (0x1b00 << 1)) +/* Setting for SPI 50Mhz M/N = 0.5 (0x1/0x2) x 100 Mhz */ +#define SPI_CLOCK_50_MHZ ((0x2 << 16) | (0x1 << 1)) + +#define CASE_DEV(name_) \ + case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC) + static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index) { struct reg_script ops[] = { @@ -49,6 +66,31 @@ static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index reg_script_run_on_dev(dev, ops); } +static void dev_set_frequency(struct device *dev, u32 reg, u32 freq) +{ + struct reg_script ops[] = { + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, reg, freq), + REG_RES_OR32(PCI_BASE_ADDRESS_0, reg, LPSS_CLOCK_PARAMS_CLOCK_EN), + REG_RES_OR32(PCI_BASE_ADDRESS_0, reg, LPSS_CLOCK_PARAMS_CLOCK_UPDATE), + REG_SCRIPT_END + }; + + reg_script_run_on_dev(dev, ops); +} + +static void dev_configure_default_frequency(struct device *dev) +{ + switch (dev->path.pci.devfn) { + CASE_DEV(HSUART1): + CASE_DEV(HSUART2): + dev_set_frequency(dev, LPSS_UART_CLOCK_PARAMS, UART_CLOCK_44P2368_MHZ); + break; + CASE_DEV(SPI): + dev_set_frequency(dev, LPSS_SPI_CLOCK_PARAMS, SPI_CLOCK_50_MHZ); + break; + } +} + static void dev_enable_snoop_and_pm(struct device *dev, int iosf_reg) { struct reg_script ops[] = { @@ -105,60 +147,98 @@ static void dev_ctl_reg(struct device *dev, int *iosf_reg, int *nvs_index) } } -#define CASE_I2C(name_) case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC) -#define PIN_SET_FOR_I2C 0x2003C881 +#define PIN_SET_FOR_I2C 0x2003C881 +#define PIN_SET_FOR_PWM 0x2003CD01 +#define PIN_SET_FOR_UART 0x2003CC81 +#define PIN_SET_FOR_SPI 0x2003CC81 +#define PIN_SET_FOR_SPI_CLK 0x2003CD01 -static void i2c_set_pins(struct device *dev) +static void dev_set_pins(struct device *dev) { switch (dev->path.pci.devfn) { - CASE_I2C(I2C1) : + CASE_DEV(I2C1): write32((volatile void *)(IO_BASE_ADDRESS + 0x0210), PIN_SET_FOR_I2C); write32((volatile void *)(IO_BASE_ADDRESS + 0x0200), PIN_SET_FOR_I2C); break; - CASE_I2C(I2C2) : + CASE_DEV(I2C2): write32((volatile void *)(IO_BASE_ADDRESS + 0x01F0), PIN_SET_FOR_I2C); write32((volatile void *)(IO_BASE_ADDRESS + 0x01E0), PIN_SET_FOR_I2C); break; - CASE_I2C(I2C3) : + CASE_DEV(I2C3): write32((volatile void *)(IO_BASE_ADDRESS + 0x01D0), PIN_SET_FOR_I2C); write32((volatile void *)(IO_BASE_ADDRESS + 0x01B0), PIN_SET_FOR_I2C); break; - CASE_I2C(I2C4) : + CASE_DEV(I2C4): write32((volatile void *)(IO_BASE_ADDRESS + 0x0190), PIN_SET_FOR_I2C); write32((volatile void *)(IO_BASE_ADDRESS + 0x01C0), PIN_SET_FOR_I2C); break; - CASE_I2C(I2C5) : + CASE_DEV(I2C5): write32((volatile void *)(IO_BASE_ADDRESS + 0x01A0), PIN_SET_FOR_I2C); write32((volatile void *)(IO_BASE_ADDRESS + 0x0170), PIN_SET_FOR_I2C); break; - CASE_I2C(I2C6) : + CASE_DEV(I2C6): write32((volatile void *)(IO_BASE_ADDRESS + 0x0150), PIN_SET_FOR_I2C); write32((volatile void *)(IO_BASE_ADDRESS + 0x0140), PIN_SET_FOR_I2C); break; - CASE_I2C(I2C7) : + CASE_DEV(I2C7): write32((volatile void *)(IO_BASE_ADDRESS + 0x0180), PIN_SET_FOR_I2C); write32((volatile void *)(IO_BASE_ADDRESS + 0x0160), PIN_SET_FOR_I2C); break; + CASE_DEV(PWM1): + write32((volatile void *)(IO_BASE_ADDRESS + 0x00A0), + PIN_SET_FOR_PWM); + break; + CASE_DEV(PWM2): + write32((volatile void *)(IO_BASE_ADDRESS + 0x00B0), + PIN_SET_FOR_PWM); + break; + CASE_DEV(HSUART1): + write32((volatile void *)(IO_BASE_ADDRESS + 0x0020), + PIN_SET_FOR_UART); + write32((volatile void *)(IO_BASE_ADDRESS + 0x0010), + PIN_SET_FOR_UART); + write32((volatile void *)(IO_BASE_ADDRESS + 0x0000), + PIN_SET_FOR_UART); + write32((volatile void *)(IO_BASE_ADDRESS + 0x0040), + PIN_SET_FOR_UART); + break; + CASE_DEV(HSUART2): + write32((volatile void *)(IO_BASE_ADDRESS + 0x0090), + PIN_SET_FOR_UART); + write32((volatile void *)(IO_BASE_ADDRESS + 0x0080), + PIN_SET_FOR_UART); + write32((volatile void *)(IO_BASE_ADDRESS + 0x0060), + PIN_SET_FOR_UART); + write32((volatile void *)(IO_BASE_ADDRESS + 0x0070), + PIN_SET_FOR_UART); + break; + CASE_DEV(SPI): + write32((volatile void *)(IO_BASE_ADDRESS + 0x0110), + PIN_SET_FOR_SPI); + write32((volatile void *)(IO_BASE_ADDRESS + 0x0100), + PIN_SET_FOR_SPI_CLK); + write32((volatile void *)(IO_BASE_ADDRESS + 0x0130), + PIN_SET_FOR_SPI); + write32((volatile void *)(IO_BASE_ADDRESS + 0x0120), + PIN_SET_FOR_SPI); + break; } } -#define CASE_DEV(name_) \ - case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC) - #define INTA 1 #define INTB 2 #define INTC 3 @@ -222,28 +302,48 @@ static void dev_set_int_pin(struct device *dev, int iosf_reg) iosf_lpss_write(iosf_reg, val); } -static void i2c_disable_resets(struct device *dev) +static void dev_disable_resets(struct device *dev) { - /* Release the I2C devices from reset. */ + /* Release the LPSS devices from reset. */ static const struct reg_script ops[] = { - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x804, 0x3), + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, LPSS_SOFTWARE_RESET, + LPSS_SOFTWARE_RESET_FUNC | LPSS_SOFTWARE_RESET_APB), + REG_SCRIPT_END, + }; + + static const struct reg_script spi_ops[] = { + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, LPSS_SPI_SOFTWARE_RESET, + LPSS_SOFTWARE_RESET_FUNC | LPSS_SOFTWARE_RESET_APB), REG_SCRIPT_END, }; switch (dev->path.pci.devfn) { - CASE_I2C(I2C1): - CASE_I2C(I2C2): - CASE_I2C(I2C3): - CASE_I2C(I2C4): - CASE_I2C(I2C5): - CASE_I2C(I2C6): - CASE_I2C(I2C7): + CASE_DEV(I2C1): + CASE_DEV(I2C2): + CASE_DEV(I2C3): + CASE_DEV(I2C4): + CASE_DEV(I2C5): + CASE_DEV(I2C6): + CASE_DEV(I2C7): printk(BIOS_DEBUG, "Releasing I2C device from reset.\n"); - reg_script_run_on_dev(dev, ops); break; + CASE_DEV(PWM1): + CASE_DEV(PWM2): + printk(BIOS_DEBUG, "Releasing PWM device from reset.\n"); + break; + CASE_DEV(HSUART1): + CASE_DEV(HSUART2): + printk(BIOS_DEBUG, "Releasing HSUART device from reset.\n"); + break; + CASE_DEV(SPI): + printk(BIOS_DEBUG, "Releasing SPI device from reset.\n"); + reg_script_run_on_dev(dev, spi_ops); + return; default: return; } + + reg_script_run_on_dev(dev, ops); } static void lpss_init(struct device *dev) @@ -261,8 +361,9 @@ static void lpss_init(struct device *dev) } dev_enable_snoop_and_pm(dev, iosf_reg); dev_set_int_pin(dev, iosf_reg); - i2c_disable_resets(dev); - i2c_set_pins(dev); + dev_configure_default_frequency(dev); + dev_disable_resets(dev); + dev_set_pins(dev); if (config->lpss_acpi_mode) dev_enable_acpi_mode(dev, iosf_reg, nvs_index); From 0607f3cb99817d5bc2ca95c2e07b9841b30eccf5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 25 Apr 2024 00:51:12 +0200 Subject: [PATCH 14/56] soc/intel/baytrail/southcluster.c: Enable resources on LPC bridge MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit LPC bridge device must call enable_resources to recursively enable resources for child devices. Otherwise child devices behind LPC bus may have misconfigured resources. Signed-off-by: Michał Żygowski --- src/soc/intel/baytrail/southcluster.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index e4252f09f89..6a352da2757 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -746,6 +746,7 @@ void southcluster_enable_dev(struct device *dev) static struct device_operations device_ops = { .read_resources = sc_read_resources, .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, .write_acpi_tables = acpi_write_hpet, .init = sc_init, .enable = southcluster_enable_dev, From 1430661ca656c85cb3d14f4f8aa9d8582b310f1d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 7 May 2024 14:52:01 +0200 Subject: [PATCH 15/56] device/pci_device.c: Clear bridge VGA16 decoding control bit after probing MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit After VGA16 bit was probed, it was never clear resulting in VGA16 bit being enabled in all ports without any VGA device behind them. Clear the VGA16 bit after probing and let coreboot set it back later for devices where it is necessary. Signed-off-by: Michał Żygowski --- src/device/pci_device.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 3b51272d674..90444e3e428 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1003,6 +1003,10 @@ static void pci_bridge_vga_compat(struct bus *const bus) bridge_ctrl = pci_read_config16(bus->dev, PCI_BRIDGE_CONTROL); bus->no_vga16 = !(bridge_ctrl & PCI_BRIDGE_CTL_VGA16); + + /* Clear the VGA16 and let coreboot set it where necessary later */ + bridge_ctrl &= ~PCI_BRIDGE_CTL_VGA16; + pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, bridge_ctrl); } /** From a18ce1e0318f391bacda6954dc8006637c9aea4b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 7 May 2024 14:38:35 +0200 Subject: [PATCH 16/56] soc/intel/baytrail: Add TXE BIOS flow implementation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Implement TXE BIOS flow as per Bay Trail TXE BWG (Document Number: 514966, Revision 0.7). Signed-off-by: Michał Żygowski --- src/mainboard/intel/minnowmax/romstage.c | 1 - src/soc/intel/baytrail/Kconfig | 5 + src/soc/intel/baytrail/Makefile.mk | 3 + src/soc/intel/baytrail/include/soc/pm.h | 2 + src/soc/intel/baytrail/include/soc/txe.h | 350 +++++++ src/soc/intel/baytrail/pmutil.c | 33 + src/soc/intel/baytrail/romstage/Makefile.mk | 1 + src/soc/intel/baytrail/romstage/romstage.c | 27 +- src/soc/intel/baytrail/romstage/txe.c | 275 +++++ src/soc/intel/baytrail/txe.c | 110 ++ src/soc/intel/baytrail/txei.c | 1039 +++++++++++++++++++ 11 files changed, 1832 insertions(+), 14 deletions(-) create mode 100644 src/soc/intel/baytrail/include/soc/txe.h create mode 100644 src/soc/intel/baytrail/romstage/txe.c create mode 100644 src/soc/intel/baytrail/txe.c create mode 100644 src/soc/intel/baytrail/txei.c diff --git a/src/mainboard/intel/minnowmax/romstage.c b/src/mainboard/intel/minnowmax/romstage.c index 470b45a7283..4b6b95c500c 100644 --- a/src/mainboard/intel/minnowmax/romstage.c +++ b/src/mainboard/intel/minnowmax/romstage.c @@ -66,7 +66,6 @@ void mainboard_fill_mrc_params(struct mrc_params *mp) mp->mainboard.dram_type = DRAM_DDR3L; mp->mainboard.dram_info_location = DRAM_INFO_SPD_MEM, - mp->txe_size_mb = 16; mp->mainboard.dram_data[0] = spd_content; mp->mainboard.dram_data[1] = NULL; diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 9775893a6bc..b4aa36a9983 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -32,6 +32,7 @@ config SOC_INTEL_BAYTRAIL select TCO_SPACE_NOT_YET_SPLIT select USE_DDR3 select UDK_2017_BINDING + select HAVE_CF9_RESET_PREPARE help Bay Trail M/D part support. @@ -266,4 +267,8 @@ config CPU_MICROCODE_CBFS_LEN endif +config BAYTRAIL_FTPM + bool "Enable fTPM functionality in TXE" + default n + endif diff --git a/src/soc/intel/baytrail/Makefile.mk b/src/soc/intel/baytrail/Makefile.mk index 615d289e144..28deeed9f9f 100644 --- a/src/soc/intel/baytrail/Makefile.mk +++ b/src/soc/intel/baytrail/Makefile.mk @@ -16,6 +16,7 @@ bootblock-y += bootblock/bootblock.c romstage-y += iosf.c romstage-y += memmap.c romstage-y += pmutil.c +romstage-y += txei.c postcar-y += iosf.c postcar-y += memmap.c @@ -44,6 +45,8 @@ ramstage-y += scc.c ramstage-y += sd.c ramstage-y += smm.c ramstage-y += southcluster.c +ramstage-y += txe.c +ramstage-y += txei.c ramstage-y += xhci.c ramstage-$(CONFIG_ELOG) += elog.c ramstage-$(CONFIG_VGA_ROM_RUN) += int15.c diff --git a/src/soc/intel/baytrail/include/soc/pm.h b/src/soc/intel/baytrail/include/soc/pm.h index 0d3c61bd258..f772e2da94a 100644 --- a/src/soc/intel/baytrail/include/soc/pm.h +++ b/src/soc/intel/baytrail/include/soc/pm.h @@ -272,6 +272,8 @@ void enable_gpe(uint32_t mask); void disable_gpe(uint32_t mask); void disable_all_gpe(void); +void global_reset(void); + void southcluster_log_state(void); /* Return non-zero when RTC failure happened. */ diff --git a/src/soc/intel/baytrail/include/soc/txe.h b/src/soc/intel/baytrail/include/soc/txe.h new file mode 100644 index 00000000000..c208850e1f6 --- /dev/null +++ b/src/soc/intel/baytrail/include/soc/txe.h @@ -0,0 +1,350 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef BAYTRAIL_TXE_H +#define BAYTRAIL_TXE_H + +#include + +/* TXE PCI configuration registers */ +#define TXE_FWSTS0 0x40 +#define TXE_CWS_MASK (0xf << 0) +#define TXE_CWS_SHIFT 0 +#define TXE_MANUF_MODE (1 << 4) +#define TXE_FPT_BAD (1 << 5) +#define TXE_CURR_OPSTATE_MASK (0x7 << 6) +#define TXE_CURR_OPSTATE_SHIFT 6 +#define TXE_FW_INIT_COMPLETE (1 << 9) +#define TXE_FW_BUP_LD_FLR (1 << 10) +#define TXE_FW_UPD_IN_PROGRESS (1 << 11) +#define TXE_ERR_CODE_MASK (0xf << 12) +#define TXE_ERR_CODE_SHIFT 12 +#define TXE_CURR_OPMODE_MASK (0xf << 16) +#define TXE_CURR_OPMODE_SHIFT 16 +#define SEC_RESET_COUNT_MASK (0xf << 20) +#define DID_ACK_DATA_MASK (0x7 << 25) +#define DID_ACK_DATA_SHIFT 25 +#define NO_DID_ACK_RECEIVED (0 << 25) +#define NON_PWR_CYCLE_RESET (1 << 25) +#define PWR_CYCLE_RESET (2 << 25) +#define ACK_DATA_GO_TO_S3 (3 << 25) +#define ACK_DATA_GO_TO_S4 (4 << 25) +#define ACK_DATA_GO_TO_S5 (5 << 25) +#define PERFORM_GLOBAL_RESET (6 << 25) +#define ACK_DATA_CONTINUE_BOOT (7 << 25) +#define DID_MSG_ACK_MASK (0xf << 28) +#define DID_MSG_GOT_ACK (1 << 28) +#define DID_MSG_NO_ACK (0 << 28) + +#define TXE_MEM_REQ 0x44 +#define MEM_REQ_MEM_SIZE_MASK 0xffff +#define MEM_REQ_INVALID (1 << 30) +#define MEM_REQ_VALID (1 << 31) + +#define TXE_FWSTS1 0x48 /* aka GS_SHDW */ + +#define TXE_SEC_TO_HOST0 0x4c +#define TXE_SEC_TO_HOST1 0x50 /* Secure Boot Status */ +#define TXE_SEC_TO_HOST2 0x54 +#define TXE_SEC_TO_HOST3 0x58 +#define TXE_SEC_TO_HOST4 0x5c + +#define TXE_SECURE_BOOT_STS TXE_SEC_TO_HOST1 + +#define TXE_DID_MSG 0x60 +#define DID_MSG_STATUS_MASK (0xf << 24) +#define DID_STATUS_SUCCESS (0 << 24) +#define DID_STATUS_NO_MEM (1 << 24) +#define DID_STATUS_MEM_INIT_ERR (2 << 24) +#define DID_MSG_DONE_MASK (0xf << 28) +#define DID_MSG_DID_NOT_DONE (0 << 28) +#define DID_MSG_DID_DONE (1 << 28) + +#define TXE_HOST_TO_SEC0 0x64 +#define TXE_HOST_TO_SEC1 0x68 +#define TXE_HOST_TO_SEC2 0x6c +#define TXE_HOST_TO_SEC3 0x70 +#define TXE_HOST_TO_SEC4 0x74 +#define TXE_HOST_TO_SEC5 0x78 +#define TXE_HOST_TO_SEC6 0x7c + +#define TXE_POWER_CAPID 0x80 +#define TXE_PME_CTRLSTS 0x84 + +#define TXE_CLK_GATE_DIS 0x88 + +#define TXE_TPM_ICR 0x8C +#define TPM_REQ (1 << 0) + +#define TXE_MSI_CAP 0xa0 + +#define TXE_IADBGCTRL 0xB0 +#define CPU_PUBLIC_DBG_EN (1 << 0) +#define EXPOSE_SOCID (1 << 1) +#define IADBGCTRL_LOCK (1 << 30) +#define IADBGCTRL_DBG_STS (1 << 31) + +#define TXE_CPU_BIOS_ENV_PROTECT 0xb4 +#define CPU_PROTECT_BIOS_ENV (1 << 0) +#define CPU_DIS_BSP_INIT (1 << 1) +#define BIOS_RDY_FOR_EVENT (1 << 2) +#define CPU_BIOS_ENV_ATTACKED (1 << 3) + +#define TXE_SATT1_BIOS_CTRL 0xc0 +#define TXE_SATT1_BIOS_BASE 0xc4 +#define TXE_SATT1_BIOS_SIZE 0xc8 +#define TXE_SATT4_TPM_CTRL 0xd0 +#define SATT_VALID (1 << 0) +#define SATT_TARGET_MASK (7 << 1) +#define SATT_TARGET_MEM (0 << 1) +#define SATT_TARGET_PCI (1 << 1) +#define SATT_TARGET_IOSF (2 << 1) +#define SATT_TARGET_SPI (3 << 1) +#define SATT_TARGET_DDR (4 << 1) +#define SATT_BRG_BA_MSB_SHIFT 8 +#define SATT_BRG_BA_MSB_MASK (0xf << 8) +#define SATT_BRG_HOST_EN (1 << 12) +#define SATT4_SEC_TPM_DIS (1 << 13) +#define TXE_SATT4_TPM_BASE 0xd4 +#define TXE_SATT4_TPM_SIZE 0xd8 + +/* TXE MMIO configuration registers behind BAR0 */ +#define TXE_MMIO_SEC_IPC_INPUT_DRBELL 0x80400 +#define TXE_MMIO_SEC_IPC_INPUT_STS 0x80408 +#define TXE_MMIO_SEC_IPC_OUTPUT_STS 0x8040C +#define TXE_MMIO_SEC_IPC_HOST_INT_STS 0x80410 +#define TXE_MMIO_IPC_INPUT_PAYLOAD 0x80500 + +/* TXE MMIO configuration registers behind BAR1 */ +#define TXE_MMIO_HOST_CB_WW 0x00 +#define TXE_MMIO_HOST_CSR 0x04 +#define TXE_MMIO_SEC_CB_RW 0x08 +#define TXE_MMIO_SEC_CSR 0x0c +#define CSR_IE (1 << 0) +#define CSR_IS (1 << 1) +#define CSR_IG (1 << 2) +#define CSR_READY (1 << 3) +#define CSR_RESET (1 << 4) +#define CSR_RP_START 8 +#define CSR_RP (((1 << 8) - 1) << CSR_RP_START) +#define CSR_WP_START 16 +#define CSR_WP (((1 << 8) - 1) << CSR_WP_START) +#define CSR_CBD_START 24 +#define CSR_CBD (((1 << 8) - 1) << CSR_CBD_START) + +#define TXE_MMIO_SATT_TPM_SAP_BA 0x1064 + +#define TXE_MMIO_SEC_IPC_READINESS 0x2040 +#define TXE_MMIO_SEC_IPC_OUTPUT_DRBELL 0x2048 +#define TXE_MMIO_IPC_OUTPUT_PAYLOAD 0x20c0 +#define TXE_MMIO_HOST_IPC_READINESS 0x2150 +#define IPC_READINESS_HOST_RDY (1 << 0) +#define IPC_READINESS_SEC_RDY (1 << 1) +#define IPC_READINESS_RDY_CLR (1 << 2) +#define TXE_MMIO_S_SEC_IPC_OUTPUT_STS 0x2154 +#define IPC_OUTPUT_READY (1 << 0) + +#define TXE_MMIO_ALIVENESS_RESP 0x2044 +#define TXE_ALIVENESS_ACK (1 << 0) +#define TXE_MMIO_ALIVENESS_REQ 0x214c +#define TXE_ALIVENESS_REQ (1 << 0) + +#define TXE_MMIO_HHISR 0x2020 +#define HHISR_INT_BAR0_STS (1 << 0) +#define HHISR_INT_BAR1_STS (1 << 1) +#define TXE_MMIO_HISR 0x2060 + +#define TXE_MMIO_TPM_DSABLE 0x2268 +#define TPM_DISABLE (1 << 0) +#define TPM_DISABLE_LOCK (1 << 1) + +#define TXEI_BASE_ADDRESS 0xce000000 +#define TXEI2_BASE_ADDRESS 0xce100000 + +/* TXE Current Working States */ +#define TXE_FWSTS0_CWS_RESET 0x0 +#define TXE_FWSTS0_CWS_INIT 0x1 +#define TXE_FWSTS0_CWS_RECOVERY 0x2 +#define TXE_FWSTS0_CWS_NORMAL 0x5 + +/* TXE Current Operation Modes */ +#define TXE_FWSTS0_COM_NORMAL 0x0 +#define TXE_FWSTS0_COM_DEBUG 0x2 +#define TXE_FWSTS0_COM_SOFT_TEMP_DISABLE 0x3 +#define TXE_FWSTS0_COM_SECOVER_JMPR 0x4 +#define TXE_FWSTS0_COM_SECOVER_TXEI_MSG 0x5 + +/* TXE Current Operational State */ +#define TXE_FWSTS0_STATE_PREBOOT 0x0 +#define TXE_FWSTS0_STATE_M0_UMA 0x1 +#define TXE_FWSTS0_STATE_MOFF 0x4 +#define TXE_FWSTS0_STATE_M0 0x5 +#define TXE_FWSTS0_STATE_BRINGUP 0x6 +#define TXE_FWSTS0_STATE_ERROR 0x7 + +/* TXE MKHI commands */ +#define MKHI_CBM_GROUP_ID 0x00 +#define MKHI_CBM_GLOBAL_RESET 0x0b + +/* Origin of Global Reset command */ +#define GR_ORIGIN_BIOS_POST 0x2 + +#define MKHI_FWCAPS_GROUP_ID 0x03 +#define MKHI_GET_RULE 0x02 +#define MKHI_SET_RULE 0x03 + +#define MKHI_FWCAPS_RULE_ID 0x0 +#define MKHI_SEC_DISABLE_RULE_ID 0x6 +#define MKHI_LCL_FWUPD_RULE_ID 0x7 +#define MKHI_FW_FEATURE_STATE_RULE_ID 0x20 +#define MKHI_OEM_TAG_RULE_ID 0x2b + +#define MKHI_HMRFPO_GROUP_ID 0x05 +#define HMRFPO_ENABLE 0x01 +#define HMRFPO_LOCK 0x02 +#define HMRFPO_GET_STATUS 0x03 +#define HMRFPO_DISABLE 0x04 + +#define MKHI_GEN_GROUP_ID 0xff +#define MKHI_GET_FW_VERSION 0x02 +#define MKHI_SEC_UNCONFIGURE 0x0d +#define MKHI_GET_SEC_UNCONFIG_STATE 0x0e +#define MKHI_END_OF_POST 0x0c + +/* Fixed Address TXEI Header's Host Address field value */ +#define BIOS_HOST_ADDR 0x00 +/* Fixed Address TXEI Header's TXE Address field value */ +#define HECI_MKHI_ADDR 0x07 +/* Fixed Address TXEI Header's TXE Address for MEI bus messages */ +#define HECI_TXEI_ADDR 0x00 + +/* Timeouts */ +#define HECI_WAIT_DELAY 1000 /* 1ms timeout for IO delay */ +#define HECI_INIT_TIMEOUT 15000000 /* 15sec timeout in microseconds */ +#define HECI_READY_TIMEOUT 8000000 /* 8sec timeout in microseconds */ +#define HECI_READ_TIMEOUT 5000000 /* 5sec timeout in microseconds */ +#define HECI_SEND_TIMEOUT 5000000 /* 5sec timeout in microseconds */ +#define HECI_MAX_RETRY 3 /* Value based off HECI HPS */ +#define HECI_MSG_DELAY 2000000 /* show warning msg and stay for 2 seconds. */ + +/* TXE RX and TX error status */ +enum txe_tx_rx_status { + /* + * Transmission of HECI message is success or + * Reception of HECI message is success. + */ + TXE_TX_RX_SUCCESS = 0, + + /* Timeout to send a message to TXE */ + TXE_TX_ERR_TIMEOUT = 1, + + /* Timeout to receive the response message from TXE */ + TXE_RX_ERR_TIMEOUT = 2, + + /* + * Response length doesn't match with expected + * response message length + */ + TXE_RX_ERR_RESP_LEN_MISMATCH = 3, + + /* TXE is not ready during TX flow */ + TXE_TX_ERR_TXE_NOT_READY = 4, + + /* TXE is not ready during RX flow */ + TXE_RX_ERR_TXE_NOT_READY = 5, + + /* Invalid input arguments provided for TX API */ + TXE_TX_ERR_INPUT = 6, + + /* Invalid input arguments provided for RX API */ + TXE_RX_ERR_INPUT = 7, +}; + +union txe_fwsts0 { + u32 data; + struct { + u32 working_state: 4; + u32 mfg_mode: 1; + u32 fpt_bad: 1; + u32 operation_state: 3; + u32 fw_init_complete: 1; + u32 ft_bup_ld_flr: 1; + u32 update_in_progress: 1; + u32 error_code: 4; + u32 operation_mode: 4; + u32 reset_count: 4; + u32 reserved1: 1; + u32 ack_data: 3; + u32 bios_msg_ack: 4; + } __packed fields; +}; + +union txe_fwsts1 { + u32 data; + struct { + u32 reserved1: 16; + u32 current_state: 8; + u32 current_pmevent: 4; + u32 progress_code: 4; + } __packed fields; +}; + +union txe_sbsts { + u32 data; + struct { + u32 sb_executed: 1; + u32 recovery: 1; + u32 debug_was_enabled: 1; + u32 debug_is_enabled: 1; + u32 emulation_mode: 1; + u32 sbm_svn: 6; + u32 km_id: 4; + u32 km_svn: 4; + u32 alt_bios_limit: 13; + } __packed fields; +}; + +/* MKHI Message Header */ +struct mkhi_hdr { + uint8_t group_id; + uint8_t command:7; + uint8_t is_resp:1; + uint8_t rsvd; + uint8_t result; +} __packed; + +struct get_fw_version_resp { + struct mkhi_hdr hdr; + uint16_t code_minor; + uint16_t code_major; + uint16_t code_build_no; + uint16_t code_hotfix; + uint16_t recovery_minor; + uint16_t recovery_major; + uint16_t recovery_build_no; + uint16_t recovery_hotfix; + uint16_t fitc_minor; + uint16_t fitc_major; + uint16_t fitc_build_no; + uint16_t fitc_hotfix; +} __packed; + +bool is_txe_devfn_visible(void); +void txe_early_init(void); +void txe_txei_init(void); +int txe_get_uma_size(void); +void txe_send_did(uintptr_t uma_base, int uma_size, int s3resume); +void txe_handle_bios_action(uint32_t bios_action); +bool txe_is_excluded_from_bios_flows(void); +bool txe_in_recovery(void); +bool txe_has_error(void); +bool txe_fw_update_in_progress(void); +void txe_hide_device(void); +void txe_fw_shadow_done(void); +int txe_global_reset(void); +int txe_aliveness_request(uintptr_t tempbar, bool request); +void txe_print_secure_boot_status(void); +void dump_txe_status(void); +void txe_do_send_end_of_post(void); +int txe_get_fw_version(struct get_fw_version_resp *reply); + +#endif diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c index 6308227a8cf..b914fa5d345 100644 --- a/src/soc/intel/baytrail/pmutil.c +++ b/src/soc/intel/baytrail/pmutil.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include @@ -19,6 +20,7 @@ #include #include #include +#include uint16_t get_pmbase(void) { @@ -368,3 +370,34 @@ void poweroff(void) pm1_cnt |= (0xf << 10); outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT); } + +static void pmc_global_reset_enable(bool enable) +{ + uint32_t reg = read32p(PMC_BASE_ADDRESS + ETR); + + if (enable) + reg |= CF9GR; + else + reg &= ~CF9GR; + + write32p(PMC_BASE_ADDRESS + ETR, reg); +} + +void cf9_reset_prepare(void) +{ + pmc_global_reset_enable(false); +} + +void global_reset(void) +{ + printk(BIOS_INFO, "%s() called!\n", __func__); + + pmc_global_reset_enable(false); + + if (!txe_global_reset()) + return; + + pmc_global_reset_enable(true); + do_full_reset(); + halt(); +} diff --git a/src/soc/intel/baytrail/romstage/Makefile.mk b/src/soc/intel/baytrail/romstage/Makefile.mk index 95e69ec2378..b232a50e12f 100644 --- a/src/soc/intel/baytrail/romstage/Makefile.mk +++ b/src/soc/intel/baytrail/romstage/Makefile.mk @@ -4,3 +4,4 @@ romstage-y += romstage.c romstage-y += raminit.c romstage-y += gfx.c romstage-y += pmc.c +romstage-y += txe.c diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index c1d6a08dc5a..b36c71a0acb 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -15,6 +15,7 @@ #include #include #include +#include static struct chipset_power_state power_state; @@ -85,22 +86,13 @@ static int chipset_prev_sleep_state(const struct chipset_power_state *ps) return prev_sleep_state; } -static void print_txe_status(const char* timepoint) -{ - pci_devfn_t txe = PCI_DEV(0, TXE_DEV, TXE_FUNC); - - printk(BIOS_DEBUG, "TXE status %s\n", timepoint); - printk(BIOS_DEBUG, "TXE SEC FWSTS0 %08x\n", pci_read_config32(txe, 0x40)); - printk(BIOS_DEBUG, "TXE SEC FWSTS1 %08x\n", pci_read_config32(txe, 0x48)); - printk(BIOS_DEBUG, "TXE SB STATUS %08x\n", pci_read_config32(txe, 0x50)); -} - /* Entry from cpu/intel/car/romstage.c */ void mainboard_romstage_entry(void) { struct chipset_power_state *ps; int prev_sleep_state; struct mrc_params mp; + int uma_size; set_max_freq(); @@ -108,9 +100,20 @@ void mainboard_romstage_entry(void) gfx_init(); + txe_early_init(); + memset(&mp, 0, sizeof(mp)); + + /* Get the UMA size */ + uma_size = txe_get_uma_size(); + mp.txe_size_mb = uma_size; + mainboard_fill_mrc_params(&mp); + /* If mainboard requested 0MB UMA, treat it as TXE disable */ + if (mp.txe_size_mb == 0) + txe_hide_device(); + timestamp_add_now(TS_INITRAM_START); ps = fill_power_state(); @@ -122,12 +125,10 @@ void mainboard_romstage_entry(void) elog_boot_notify(s3resume); - print_txe_status("before MRC"); - /* Initialize RAM */ raminit(&mp, prev_sleep_state); - print_txe_status("after MRC"); + txe_send_did((uintptr_t)mp.txe_base_address, mp.txe_size_mb, s3resume); timestamp_add_now(TS_INITRAM_END); diff --git a/src/soc/intel/baytrail/romstage/txe.c b/src/soc/intel/baytrail/romstage/txe.c new file mode 100644 index 00000000000..435eed817ca --- /dev/null +++ b/src/soc/intel/baytrail/romstage/txe.c @@ -0,0 +1,275 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define FTPM_SIZE 4*KiB + +static bool is_ftpm_enabled(void) +{ + uint32_t reg = pci_read_config32(PCI_DEV(0, TXE_DEV, TXE_FUNC), + TXE_SATT4_TPM_CTRL); + + if((reg & SATT4_SEC_TPM_DIS) == SATT4_SEC_TPM_DIS) { + printk(BIOS_DEBUG, "TXE fTPM disabled\n"); + return false; + } + + printk(BIOS_DEBUG, "TXE fTPM enabled\n"); + return true; +} + +int txe_get_uma_size(void) +{ + uint32_t uma_size, reg; + pci_devfn_t txe = PCI_DEV(0, TXE_DEV, TXE_FUNC); + + if (txe_is_excluded_from_bios_flows()) + return 0; + + if (!is_txe_devfn_visible()) + return 0; + + printk(BIOS_DEBUG, "Obtaining TXE UMA requirements\n"); + + do { + reg = pci_read_config32(txe, TXE_MEM_REQ); + } while (((reg & MEM_REQ_VALID) != MEM_REQ_VALID) && + ((reg & MEM_REQ_INVALID) != MEM_REQ_INVALID)); + + uma_size = 0; + + if ((reg & MEM_REQ_VALID) == MEM_REQ_VALID) { + reg = pci_read_config32(txe, TXE_MEM_REQ); + uma_size = (reg & MEM_REQ_MEM_SIZE_MASK) * KiB / MiB; + printk(BIOS_INFO, "SeC UMA Size Requested: %d MB\n", uma_size); + } else if ((reg & MEM_REQ_INVALID) == MEM_REQ_INVALID) { + printk(BIOS_ERR, "TXE UMA size request invalid\n"); + } else { + printk(BIOS_ERR, "TXE not working properly\n"); + } + + /* + * Add an extra 1*MiB memory for fTPM communication buffer. + * MRC allocates memory in MiB granualrity. + */ + if (CONFIG(BAYTRAIL_FTPM) && uma_size != 0) { + if (is_ftpm_enabled()) + uma_size++; + } + + return (int)uma_size; +} + +void txe_early_init(void) +{ + pci_devfn_t txe = PCI_DEV(0, TXE_DEV, TXE_FUNC); + uint32_t reg; + bool txe_disable = false; + + if (!is_txe_devfn_visible()) + return; + + if (txe_is_excluded_from_bios_flows()) { + printk(BIOS_INFO, "TXE excluded from platform flows\n"); + printk(BIOS_INFO, "Taking TXE Error BIOS Path\n"); + return; + } + + /* Init PCI Power Management capability ID */ + pci_write_config32 (txe, TXE_POWER_CAPID, 0x4803A001); + + if (txe_in_recovery()) { + printk(BIOS_INFO, "Taking TXE Recovery BIOS Path\n"); + return; + } + + if (txe_has_error()) { + printk(BIOS_ERR, "Taking TXE Error BIOS Path\n"); + return; + } + + if (txe_fw_update_in_progress()) { + printk(BIOS_INFO, "Taking TXE FW Update BIOS Path\n"); + return; + } + + /* Check if we don't need to hide the TXE device */ + reg = pci_read_config32(txe, TXE_FWSTS0); + + switch ((reg & TXE_CURR_OPMODE_MASK) >> TXE_CURR_OPMODE_SHIFT) { + case TXE_FWSTS0_COM_NORMAL: + printk(BIOS_INFO, "TXE Current Operational Mode: NORMAL\n"); + printk(BIOS_INFO, "Taking TXE Normal BIOS Path\n"); + break; + case TXE_FWSTS0_COM_DEBUG: + printk(BIOS_INFO, "TXE Current Operational Mode: DEBUG\n"); + txe_disable = true; + break; + case TXE_FWSTS0_COM_SOFT_TEMP_DISABLE: + printk(BIOS_INFO, "TXE Current Operational Mode: SOFT_TEMP_DISABLE\n"); + txe_disable = true; + break; + case TXE_FWSTS0_COM_SECOVER_JMPR: + printk(BIOS_INFO, "TXE Current Operational Mode: SECOVER_JMPR\n"); + txe_disable = true; + break; + case TXE_FWSTS0_COM_SECOVER_TXEI_MSG: + printk(BIOS_INFO, "TXE Current Operational Mode: SECOVER_TXEI_MSG\n"); + txe_disable = true; + break; + } + + if (txe_disable) { + printk(BIOS_INFO, "Taking TXE Disable BIOS Path\n"); + txe_hide_device(); + } +} + +static void txei_assign_resource(pci_devfn_t dev) +{ + u16 pcireg; + + /* Assign Resources */ + /* Clear BIT 1-2 of Command Register */ + pcireg = pci_read_config16(dev, PCI_COMMAND); + pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_write_config16(dev, PCI_COMMAND, pcireg); + + /* Program Temporary BAR for TXEI device */ + pci_write_config32(dev, PCI_BASE_ADDRESS_0, TXEI_BASE_ADDRESS); + pci_write_config32(dev, PCI_BASE_ADDRESS_1, TXEI2_BASE_ADDRESS); + + /* Enable Bus Master and MMIO Space */ + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); +} + +static void txe_write_did_message(pci_devfn_t txe, uint32_t status) +{ + uint32_t reg; + + if (pci_read_config32(txe, TXE_DID_MSG) & DID_MSG_DID_DONE) { + printk(BIOS_WARNING, "TXE DRAM Init Done already set! Skipping DID message\n"); + return; + } + + printk(BIOS_INFO, "Sending TXE DID message with status: %u\n", status >> 24); + pci_write_config32(txe, TXE_DID_MSG, status | DID_MSG_DID_DONE); + + reg = pci_read_config32(txe, TXE_FWSTS0); + printk(BIOS_DEBUG, "TXE FWSTS0 before DID %08x\n", reg); + + /* Poll for DID ACK for 5 seconds */ + for (int i =0; i < 5000; i++) { + reg = pci_read_config32(txe, TXE_FWSTS0); + if ((reg & DID_MSG_ACK_MASK) == DID_MSG_GOT_ACK) { + printk(BIOS_DEBUG, "TXE DRAM Init Done ACK received\n"); + break; + } + mdelay(1); + } + + if ((reg & DID_MSG_ACK_MASK) != DID_MSG_GOT_ACK) { + printk(BIOS_ERR, "Timeout waiting for TXE DRAM Init Done ACK!\n"); + return; + } + + reg &= DID_ACK_DATA_MASK; + printk(BIOS_DEBUG, "TXE BIOS action: %u\n", reg >> DID_ACK_DATA_SHIFT); + /* Ensure resources are programmed before requesting global reset */ + txei_assign_resource(txe); + + txe_handle_bios_action(reg); +} + +static bool is_uma_allocated_for_ftpm(uintptr_t uma_base) +{ + pci_devfn_t txe = PCI_DEV(0, TXE_DEV, TXE_FUNC); + uint32_t txe_uma_size, tolm; + + txe_uma_size = pci_read_config32(txe, TXE_MEM_REQ); + txe_uma_size = (txe_uma_size & MEM_REQ_MEM_SIZE_MASK) * KiB; + + tolm = iosf_bunit_read(BUNIT_BMBOUND) & ~((1 << 27) - 1); + + if (tolm - uma_base >= txe_uma_size + FTPM_SIZE) + return true; + + printk(BIOS_ERR, "Not enough TXE UMA memory allocated for fTPM\n"); + + return false; +} + +void txe_send_did(uintptr_t uma_base, int uma_size, int s3resume) +{ + uintptr_t ftpm_base; + pci_devfn_t txe = PCI_DEV(0, TXE_DEV, TXE_FUNC); + uint32_t txe_uma_size; + + if (!is_txe_devfn_visible()) { + printk(BIOS_ERR, "TXE device hidden! Skipping DID message\n"); + return; + } + + txe_uma_size = pci_read_config32(txe, TXE_MEM_REQ); + txe_uma_size = (txe_uma_size & MEM_REQ_MEM_SIZE_MASK) * KiB; + + if (uma_base == 0 || uma_size == 0) { + printk(BIOS_ERR, "TXE UMA invalid! Disabling UMA\n"); + pci_and_config32(txe, TXE_SATT4_TPM_CTRL, ~SATT_VALID); + pci_and_config32(txe, TXE_SATT1_BIOS_CTRL, ~SATT_VALID); + txe_write_did_message(txe, DID_STATUS_NO_MEM); + return; + } + + /* MRC return the UMA base as bits [32:20]*/ + uma_base = uma_base << 20; + printk(BIOS_DEBUG, "TXE: UMA base: %08lx\n", uma_base); + + if (CONFIG(BAYTRAIL_FTPM) && is_ftpm_enabled() && is_uma_allocated_for_ftpm(uma_base)) { + ftpm_base = uma_base + txe_uma_size; + if (!s3resume) + memset((void *)ftpm_base, 0, FTPM_SIZE); + + printk(BIOS_DEBUG, "TXE: fTPM base: %08lx\n", ftpm_base); + + pci_write_config32(txe, TXE_SATT4_TPM_BASE, ftpm_base); + pci_write_config32(txe, TXE_SATT4_TPM_SIZE, FTPM_SIZE); + pci_update_config32(txe, TXE_SATT4_TPM_CTRL, ~SATT_TARGET_MASK, + SATT_TARGET_MEM); + pci_or_config32(txe, TXE_SATT4_TPM_CTRL, SATT_VALID); + + printk(BIOS_DEBUG, "TXE: SATT TPM BASE: %08x\n", + pci_read_config32(txe, TXE_SATT4_TPM_BASE)); + printk(BIOS_DEBUG, "TXE: SATT TPM SIZE: %08x\n", + pci_read_config32(txe, TXE_SATT4_TPM_SIZE)); + printk(BIOS_DEBUG, "TXE: SATT TPM CTRL: %08x\n", + pci_read_config32(txe, TXE_SATT4_TPM_CTRL)); + } else { + pci_and_config32(txe, TXE_SATT4_TPM_CTRL, ~SATT_VALID); + } + + pci_write_config32(txe, TXE_SATT1_BIOS_BASE, uma_base); + pci_write_config32(txe, TXE_SATT1_BIOS_SIZE, uma_size * MiB); + pci_or_config32(txe, TXE_SATT1_BIOS_CTRL, SATT_VALID); + + printk(BIOS_DEBUG, "TXE: SATT UMA BASE: %08x\n", + pci_read_config32(txe, TXE_SATT1_BIOS_BASE)); + printk(BIOS_DEBUG, "TXE: SATT UMA SIZE: %08x\n", + pci_read_config32(txe, TXE_SATT1_BIOS_SIZE)); + printk(BIOS_DEBUG, "TXE: SATT UMA CTRL: %08x\n", + pci_read_config32(txe, TXE_SATT1_BIOS_CTRL)); + + txe_write_did_message(txe, DID_STATUS_SUCCESS); +} diff --git a/src/soc/intel/baytrail/txe.c b/src/soc/intel/baytrail/txe.c new file mode 100644 index 00000000000..32df1a9d9dd --- /dev/null +++ b/src/soc/intel/baytrail/txe.c @@ -0,0 +1,110 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include "chip.h" + +static void txe_enable(struct device *dev) +{ + southcluster_enable_dev(dev); + + txe_fw_shadow_done(); + + txe_print_secure_boot_status(); +} + +static void txe_init(struct device *dev) +{ + uint32_t reg; + + dump_txe_status(); + txe_txei_init(); + + /* Configure interrupt */ + pci_and_config8(dev, TXE_MSI_CAP, 0xfc); + + reg = pci_read_config32(dev, TXE_FWSTS0); + if ((reg & DID_MSG_ACK_MASK) == DID_MSG_GOT_ACK) { + reg &= DID_ACK_DATA_MASK; + txe_handle_bios_action(reg); + } +} + +static void txe_final(struct device *dev) +{ + struct get_fw_version_resp fw_ver; + + if (!txe_get_fw_version(&fw_ver)) { + printk(BIOS_DEBUG, "TXE FW version:\n" + "\tCode version: %d.%d.%d.%d\n" + "\tRecovery version: %d.%d.%d.%d\n" + "\tFITC version: %d.%d.%d.%d\n", + fw_ver.code_minor, + fw_ver.code_major, + fw_ver.code_hotfix, + fw_ver.code_build_no, + fw_ver.recovery_minor, + fw_ver.recovery_major, + fw_ver.recovery_hotfix, + fw_ver.recovery_build_no, + fw_ver.fitc_minor, + fw_ver.fitc_major, + fw_ver.fitc_hotfix, + fw_ver.fitc_build_no); + } +} + +static void txe_finalize(struct device *dev) +{ + struct resource *heci_bar1; + + dump_txe_status(); + + txe_do_send_end_of_post(); + + if (!dev) + return; + + heci_bar1 = find_resource(dev, PCI_BASE_ADDRESS_1); + + if (!heci_bar1 || heci_bar1->base == 0) { + printk(BIOS_DEBUG, "HECI BAR1 not assigned, not sending aliveness request"); + return; + } + + txe_aliveness_request((uintptr_t)heci_bar1->base, false); +} + +static void txe_eop(void *unused) +{ + txe_finalize(pcidev_on_root(TXE_DEV, TXE_FUNC)); +} + +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, txe_eop, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, txe_eop, NULL); + +static const struct device_operations device_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = txe_init, + .enable = txe_enable, + .final = txe_final, + .ops_pci = &soc_pci_ops, +}; + +static const struct pci_driver southcluster __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VID_INTEL, + .device = TXE_DEVID, +}; diff --git a/src/soc/intel/baytrail/txei.c b/src/soc/intel/baytrail/txei.c new file mode 100644 index 00000000000..874c2c0a081 --- /dev/null +++ b/src/soc/intel/baytrail/txei.c @@ -0,0 +1,1039 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define __SIMPLE_DEVICE__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SLOT_SIZE sizeof(uint32_t) +/* Circular buffer on TXEI has only 16 slots */ +#define TXEI_CIRCULAR_BUFFER_SIZE 16 + +#define TXEI_HDR_IS_COMPLETE (1 << 31) +#define TXEI_HDR_LENGTH_START 16 +#define TXEI_HDR_LENGTH_SIZE 9 +#define TXEI_HDR_LENGTH (((1 << TXEI_HDR_LENGTH_SIZE) - 1) << TXEI_HDR_LENGTH_START) +#define TXEI_HDR_HOST_ADDR_START 8 +#define TXEI_HDR_HOST_ADDR (((1 << 8) - 1) << TXEI_HDR_HOST_ADDR_START) +#define TXEI_HDR_TXE_ADDR_START 0 +#define TXEI_HDR_TXE_ADDR (((1 << 8) - 1) << TXEI_HDR_TXE_ADDR_START) + +enum txe_cmd_result { + TXE_CMD_RESULT_GLOBAL_RESET_REQUESTED, + TXE_CMD_RESULT_SUCCESS, + TXE_CMD_RESULT_ERROR, + TXE_CMD_RESULT_DISABLED, + TXE_CMD_RESULT_RETRY, +}; + +bool is_txe_devfn_visible(void) +{ + if (!is_devfn_enabled(PCI_DEVFN(TXE_DEV, TXE_FUNC))) { + printk(BIOS_WARNING, "TXE device %x.%x is disabled\n", TXE_DEV, TXE_FUNC); + return false; + } + + if (pci_read_config16(PCI_DEV(0, TXE_DEV, TXE_FUNC), PCI_VENDOR_ID) == 0xFFFF) { + printk(BIOS_WARNING, "TXE device %x.%x is hidden\n", TXE_DEV, TXE_FUNC); + return false; + } + + return true; +} + +/* Get HECI BAR 0 from PCI configuration space */ +static uintptr_t get_txei_bar(pci_devfn_t dev) +{ + uintptr_t bar; + + bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0); + bar &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; + assert(bar != 0); + return bar; +} + +static uintptr_t get_txei_bar1(pci_devfn_t dev) +{ + uintptr_t bar; + + bar = pci_read_config32(dev, PCI_BASE_ADDRESS_1); + bar &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; + assert(bar != 0); + return bar; +} + +static void txei_assign_resource(pci_devfn_t dev, uintptr_t tempbar0, uintptr_t tempbar1) +{ + u16 pcireg; + + /* Assign Resources */ + /* Clear BIT 1-2 of Command Register */ + pcireg = pci_read_config16(dev, PCI_COMMAND); + pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_write_config16(dev, PCI_COMMAND, pcireg); + + /* Program Temporary BAR for TXEI device */ + if (tempbar0 == 0) + pci_write_config32(dev, PCI_BASE_ADDRESS_0, TXEI_BASE_ADDRESS); + else + pci_write_config32(dev, PCI_BASE_ADDRESS_0, tempbar0); + + if (tempbar1 == 0) + pci_write_config32(dev, PCI_BASE_ADDRESS_1, TXEI2_BASE_ADDRESS); + else + pci_write_config32(dev, PCI_BASE_ADDRESS_1, tempbar1); + + /* Enable Bus Master and MMIO Space */ + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); +} + +int txe_aliveness_request(uintptr_t tempbar, bool request) +{ + struct stopwatch sw; + + if (request) + write32p(tempbar + TXE_MMIO_ALIVENESS_REQ, + read32p(tempbar + TXE_MMIO_ALIVENESS_REQ) | TXE_ALIVENESS_REQ); + else + write32p(tempbar + TXE_MMIO_ALIVENESS_REQ, + read32p(tempbar + TXE_MMIO_ALIVENESS_REQ) & (uint32_t)~TXE_ALIVENESS_REQ); + + stopwatch_init_usecs_expire(&sw, HECI_READY_TIMEOUT); + while ((read32p(tempbar + TXE_MMIO_ALIVENESS_RESP) & 1) != request) { + // Check if init timeout has expired. + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "Timeout when sending TXE aliveness request: %d\n", request); + return -1; + } + + udelay(100); + } + + return 0; +} + +void txe_handle_bios_action(uint32_t bios_action) +{ + switch (bios_action) { + /* Do nothing for the below actions */ + case NO_DID_ACK_RECEIVED: + case ACK_DATA_GO_TO_S3: + case ACK_DATA_GO_TO_S4: + case ACK_DATA_GO_TO_S5: + return; + case ACK_DATA_CONTINUE_BOOT: + printk(BIOS_INFO, "TXE requested to continue boot\n"); + break; + case NON_PWR_CYCLE_RESET: + printk(BIOS_INFO, "TXE requested a reset\n"); + system_reset(); + break; + case PWR_CYCLE_RESET: + printk(BIOS_INFO, "TXE requested a power cycle reset\n"); + full_reset(); + break; + case PERFORM_GLOBAL_RESET: + printk(BIOS_INFO, "TXE requested a global reset\n"); + printk(BIOS_INFO, "Global reset will be performed in ramstage\n"); + break; + default: + printk(BIOS_INFO, "TXE invalid BIOS action %x\n", + bios_action >> DID_ACK_DATA_SHIFT); + break; + } +} + +/* + * Initialize the TXE device with provided temporary BAR. If BAR is 0 use a + * default. + */ +void txe_txei_init(void) +{ + pci_devfn_t dev = PCI_DEV(0, TXE_DEV, TXE_FUNC); + uint32_t aliveness_req, aliveness_resp; + uint32_t txe_opmode; + uintptr_t tempbar0, tempbar; + struct stopwatch sw; + + /* Check if device enabled */ + if (!is_txe_devfn_visible()) + return; + + tempbar0 = pci_read_config32(dev, PCI_BASE_ADDRESS_0); + tempbar0 &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; + tempbar = pci_read_config32(dev, PCI_BASE_ADDRESS_1); + tempbar &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; + + txe_opmode = pci_read_config32(dev, TXE_FWSTS0); + txe_opmode &= TXE_CURR_OPMODE_MASK; + txe_opmode >>= TXE_CURR_OPMODE_SHIFT; + + if (txe_opmode == TXE_FWSTS0_COM_DEBUG || + txe_opmode == TXE_FWSTS0_COM_SOFT_TEMP_DISABLE || + txe_opmode == TXE_FWSTS0_COM_SECOVER_JMPR || + txe_opmode == TXE_FWSTS0_COM_SECOVER_TXEI_MSG) + return; + + /* Assign TXEI resource and enable the resource */ + txei_assign_resource(dev, tempbar0, tempbar); + + /* Ensure the BARs are the same as we just set them */ + tempbar0 = pci_read_config32(dev, PCI_BASE_ADDRESS_0); + tempbar0 &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; + tempbar = pci_read_config32(dev, PCI_BASE_ADDRESS_1); + tempbar &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; + + stopwatch_init_usecs_expire(&sw, HECI_READY_TIMEOUT); + do { + aliveness_req = read32p(tempbar + TXE_MMIO_ALIVENESS_REQ) & TXE_ALIVENESS_REQ; + aliveness_resp = read32p(tempbar + TXE_MMIO_ALIVENESS_RESP) & TXE_ALIVENESS_ACK; + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "Timeout waiting for TXE aliveness early sync\n"); + return; + } + + udelay(1000); + } while(aliveness_req != aliveness_resp); + + if ((read32p(tempbar + TXE_MMIO_ALIVENESS_REQ) & TXE_ALIVENESS_REQ) == TXE_ALIVENESS_REQ) + txe_aliveness_request(tempbar, false); + + write32p(tempbar + TXE_MMIO_HOST_IPC_READINESS, + read32p(tempbar + TXE_MMIO_HOST_IPC_READINESS) | IPC_READINESS_RDY_CLR); + + stopwatch_init_usecs_expire(&sw, HECI_READY_TIMEOUT); + do { + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "Timeout waiting for TXE IPC readiness\n"); + return; + } + + udelay(1000); + } while(!(read32p(tempbar + TXE_MMIO_SEC_IPC_READINESS) & IPC_READINESS_SEC_RDY)); + + write32p(tempbar + TXE_MMIO_HHISR, + read32p(tempbar + TXE_MMIO_HHISR) & ~(HHISR_INT_BAR0_STS | HHISR_INT_BAR0_STS)); + + write32p(tempbar + TXE_MMIO_S_SEC_IPC_OUTPUT_STS, + read32p(tempbar + TXE_MMIO_S_SEC_IPC_OUTPUT_STS) | IPC_OUTPUT_READY); + + write32p(tempbar + TXE_MMIO_HOST_IPC_READINESS, + read32p(tempbar + TXE_MMIO_HOST_IPC_READINESS) | IPC_READINESS_HOST_RDY); + + txe_aliveness_request(tempbar, true); +} + +bool txe_is_excluded_from_bios_flows(void) +{ + uint32_t reg; + + if (read32p(PMC_BASE_ADDRESS + 0xc) & 0x10) { + reg = read32p(PMC_BASE_ADDRESS + 0x2c) & 0xf; + switch (reg) { + case 0: + case 4: + case 5: + case 6: + return true; + } + } + + return false; +} + +bool txe_in_recovery(void) +{ + if (!is_txe_devfn_visible()) + return false; + + uint32_t reg = pci_read_config32(PCI_DEV(0, TXE_DEV, TXE_FUNC), TXE_FWSTS0); + + return ((reg & TXE_CWS_MASK) == TXE_FWSTS0_CWS_RECOVERY); +} + +bool txe_has_error(void) +{ + if (!is_txe_devfn_visible()) + return false; + + uint32_t reg = pci_read_config32(PCI_DEV(0, TXE_DEV, TXE_FUNC), TXE_FWSTS0); + + return ((reg & TXE_ERR_CODE_MASK) != 0); +} + +bool txe_fw_update_in_progress(void) +{ + if (!is_txe_devfn_visible()) + return false; + + uint32_t reg = pci_read_config32(PCI_DEV(0, TXE_DEV, TXE_FUNC), TXE_FWSTS0); + + return !!(reg & TXE_FW_UPD_IN_PROGRESS); +} + +void txe_hide_device(void) +{ + write32p(PMC_BASE_ADDRESS + FUNC_DIS, + read32p(PMC_BASE_ADDRESS + FUNC_DIS) | TXE_DIS); +} + +void txe_fw_shadow_done(void) +{ + if (!is_txe_devfn_visible()) + return; + + printk(BIOS_DEBUG, "TXE: sending FW SHADOW DONE\n"); + pci_or_config32(PCI_DEV(0, TXE_DEV, TXE_FUNC), TXE_HOST_TO_SEC0, 1); +} + +static uint32_t read_bar(pci_devfn_t dev, uint32_t offset) +{ + return read32p(get_txei_bar(dev) + offset); +} + +static uint32_t read_bar1(pci_devfn_t dev, uint32_t offset) +{ + return read32p(get_txei_bar1(dev) + offset); +} + +static void write_bar(pci_devfn_t dev, uint32_t offset, uint32_t val) +{ + return write32p(get_txei_bar(dev) + offset, val); +} + +static void write_bar1(pci_devfn_t dev, uint32_t offset, uint32_t val) +{ + return write32p(get_txei_bar1(dev) + offset, val); +} + +static bool txe_ipc_ready(void) +{ + uint32_t ipc_input_sts; + ipc_input_sts = read_bar(PCI_DEV(0, TXE_DEV, TXE_FUNC), TXE_MMIO_SEC_IPC_INPUT_STS); + return !!(ipc_input_sts & 1); +} + +static int wait_heci_ipc_ready(void) +{ + struct stopwatch sw; + + stopwatch_init_usecs_expire(&sw, HECI_READY_TIMEOUT); + while (!txe_ipc_ready()) { + udelay(HECI_WAIT_DELAY); + if (stopwatch_expired(&sw)) + return 0; + } + + return 1; +} + +static bool check_heci_reset(void) +{ + return ((read_bar1(PCI_DEV(0, TXE_DEV, TXE_FUNC), TXE_MMIO_SEC_IPC_READINESS) & IPC_READINESS_SEC_RDY) == 0); +} + +static uint32_t read_slot(uint32_t idx) +{ + return read_bar1(PCI_DEV(0, TXE_DEV, TXE_FUNC), TXE_MMIO_IPC_OUTPUT_PAYLOAD + idx * SLOT_SIZE); +} + +static void write_slot(uint32_t idx, uint32_t val) +{ + write_bar(PCI_DEV(0, TXE_DEV, TXE_FUNC), TXE_MMIO_IPC_INPUT_PAYLOAD + idx * SLOT_SIZE, val); +} + +static void set_ipc_input_doorbell(void) +{ + uint32_t ipc_input_doorbell; + ipc_input_doorbell = read_bar(PCI_DEV(0, TXE_DEV, TXE_FUNC), TXE_MMIO_SEC_IPC_INPUT_DRBELL); + write_bar(PCI_DEV(0, TXE_DEV, TXE_FUNC), TXE_MMIO_SEC_IPC_INPUT_DRBELL, ipc_input_doorbell | 1); +} + +static int ipc_output_ready(void) +{ + uint32_t ipc_output_sts; + ipc_output_sts = read_bar1(PCI_DEV(0, TXE_DEV, TXE_FUNC), TXE_MMIO_S_SEC_IPC_OUTPUT_STS); + return !!(ipc_output_sts & 1); +} + +static void set_ipc_output_ready(void) +{ + uint32_t ipc_output_sts; + ipc_output_sts = read_bar1(PCI_DEV(0, TXE_DEV, TXE_FUNC), TXE_MMIO_S_SEC_IPC_OUTPUT_STS); + write_bar1(PCI_DEV(0, TXE_DEV, TXE_FUNC), TXE_MMIO_SEC_IPC_OUTPUT_STS, ipc_output_sts | 1); +} + +static int wait_read_slots(void) +{ + struct stopwatch sw; + + stopwatch_init_usecs_expire(&sw, HECI_READ_TIMEOUT); + while (true) { + udelay(HECI_WAIT_DELAY); + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "HECI: timed out reading answer!\n"); + return 0; + } + + if (!ipc_output_ready()) + break; + } + return 1; +} + + +static size_t hdr_get_length(uint32_t hdr) +{ + return (hdr & TXEI_HDR_LENGTH) >> TXEI_HDR_LENGTH_START; +} + +/* get number of full 4-byte slots */ +static size_t bytes_to_slots(size_t bytes) +{ + return (bytes + (SLOT_SIZE - 1) + SLOT_SIZE) / SLOT_SIZE; +} + +static int +send_one_message(uint32_t hdr, const void *buff) +{ + size_t pend_len, pend_slots, i; + const uint32_t *p = buff; + + if (!wait_heci_ipc_ready()) + return 0; + + /* First, write header */ + write_slot(0, hdr); + + pend_len = hdr_get_length(hdr); + pend_slots = bytes_to_slots(pend_len); + + /* Write the body in whole slots */ + for (i = 1; i < pend_slots; i++, *p++) { + write_slot(i, *p); + } + + set_ipc_input_doorbell(); + + return pend_len; +} + +static bool heci_can_send(void) +{ + pci_devfn_t dev = PCI_DEV(0, TXE_DEV, TXE_FUNC); + uint32_t fw_sts0; + + if (!is_txe_devfn_visible()) + return false; + + if (txe_is_excluded_from_bios_flows()) { + printk(BIOS_INFO, "TXE excluded from platform flows\n"); + printk(BIOS_ERR, "Can not send HECI messages\n"); + return false; + } + + if (txe_has_error()) { + printk(BIOS_ERR, "TXE Error occurred, not sending HECI message\n"); + return false; + } + + if (txe_fw_update_in_progress()) { + printk(BIOS_INFO, "TXE FW is updating, not sending HECI message\n"); + return false; + } + + fw_sts0 = pci_read_config32(dev, TXE_FWSTS0); + + switch ((fw_sts0 & TXE_CURR_OPMODE_MASK) >> TXE_CURR_OPMODE_SHIFT) { + case TXE_FWSTS0_COM_NORMAL: + case TXE_FWSTS0_COM_SECOVER_TXEI_MSG: + break; + case TXE_FWSTS0_COM_DEBUG: + case TXE_FWSTS0_COM_SOFT_TEMP_DISABLE: + case TXE_FWSTS0_COM_SECOVER_JMPR: + printk(BIOS_INFO, "Current TXE operation mode does not allow" + " sending HECI messages\n"); + return false; + } + + return true; +} + +static enum txe_tx_rx_status +heci_send(const void *msg, size_t len, uint8_t host_addr, uint8_t client_addr) +{ + uint8_t retry; + uint32_t hdr; + size_t sent, remaining, cb_size, max_length; + const uint8_t *p; + + if (!msg || !len) + return TXE_TX_ERR_INPUT; + + if (!heci_can_send()) + return TXE_TX_ERR_INPUT; + + for (retry = 0; retry < HECI_MAX_RETRY; retry++) { + p = msg; + + if (check_heci_reset()) + txe_txei_init(); + + if (!wait_heci_ipc_ready()) { + printk(BIOS_ERR, "HECI: not ready\n"); + continue; + } + + cb_size = TXEI_CIRCULAR_BUFFER_SIZE; + /* + * Reserve one slot for the header. Limit max message + * length by 9 bits that are available in the header. + */ + max_length = MIN(cb_size, (1 << TXEI_HDR_LENGTH_SIZE) - 1) + - SLOT_SIZE; + remaining = len; + + /* + * Fragment the message into smaller messages not exceeding + * useful circular buffer length. Mark last message complete. + */ + do { + hdr = MIN(max_length, remaining) + << TXEI_HDR_LENGTH_START; + hdr |= client_addr << TXEI_HDR_TXE_ADDR_START; + hdr |= host_addr << TXEI_HDR_HOST_ADDR_START; + hdr |= (MIN(max_length, remaining) == remaining) ? + TXEI_HDR_IS_COMPLETE : 0; + sent = send_one_message(hdr, p); + p += sent; + remaining -= sent; + } while (remaining > 0 && sent != 0); + + if (!remaining) + return TXE_TX_RX_SUCCESS; + } + + return TXE_TX_ERR_TXE_NOT_READY; +} + +static enum txe_tx_rx_status +recv_one_message(uint32_t *hdr, void *buff, size_t maxlen, size_t *recv_len) +{ + uint32_t *p = buff; + size_t recv_slots, i; + + /* wait for the rest of messages to arrive */ + if (!wait_read_slots()) + return TXE_RX_ERR_TIMEOUT; + + *hdr = read_slot(0); + *recv_len = hdr_get_length(*hdr); + + if (!*recv_len) + return TXE_TX_RX_SUCCESS; + + recv_slots = bytes_to_slots(*recv_len); + + i = 0; + if (*recv_len > maxlen) { + printk(BIOS_ERR, "HECI: response is too big\n"); + return TXE_RX_ERR_RESP_LEN_MISMATCH; + } + + /* fetch whole slots first */ + for (i = 1; i < recv_slots; i++, *p++) { + *p = read_slot(i); + } + + return TXE_TX_RX_SUCCESS; +} + +static enum txe_tx_rx_status heci_receive(void *buff, size_t *maxlen) +{ + uint8_t retry; + size_t left, received; + uint32_t hdr = 0; + uint8_t *p; + enum txe_tx_rx_status ret = TXE_RX_ERR_TIMEOUT; + + if (!buff || !maxlen || !*maxlen) + return TXE_RX_ERR_INPUT; + + for (retry = 0; retry < HECI_MAX_RETRY; retry++) { + p = buff; + left = *maxlen; + + if (check_heci_reset()) + txe_txei_init(); + + if (!wait_heci_ipc_ready()) { + printk(BIOS_ERR, "HECI: not ready\n"); + break; + } + + /* + * Receive multiple packets until we meet one marked + * complete or we run out of space in caller-provided buffer. + */ + do { + ret = recv_one_message(&hdr, p, left, &received); + if (ret) { + printk(BIOS_ERR, "HECI: Failed to receive!\n"); + return TXE_RX_ERR_TXE_NOT_READY; + } + set_ipc_output_ready(); + left -= received; + p += received; + } while (received && !(hdr & TXEI_HDR_IS_COMPLETE) && left > 0); + + if ((hdr & TXEI_HDR_IS_COMPLETE) && received) { + *maxlen = p - (uint8_t *)buff; + return TXE_TX_RX_SUCCESS; + } + } + + return TXE_RX_ERR_TXE_NOT_READY; +} + +static enum txe_tx_rx_status heci_send_receive(const void *snd_msg, size_t snd_sz, void *rcv_msg, + size_t *rcv_sz, uint8_t txe_addr) +{ + enum txe_tx_rx_status ret; + + ret = heci_send(snd_msg, snd_sz, BIOS_HOST_ADDR, txe_addr); + if (ret) { + printk(BIOS_ERR, "HECI: send Failed\n"); + return ret; + } + + if (rcv_msg != NULL) { + ret = heci_receive(rcv_msg, rcv_sz); + if (ret) + printk(BIOS_ERR, "HECI: receive Failed\n"); + } + + return ret; +} + +static bool txe_cws_normal(void) +{ + if (!is_txe_devfn_visible()) + return false; + + uint32_t reg = pci_read_config32(PCI_DEV(0, TXE_DEV, TXE_FUNC), TXE_FWSTS0); + + return ((reg & TXE_CWS_MASK) == TXE_FWSTS0_CWS_NORMAL); +} + +static bool txe_com_normal(void) +{ + if (!is_txe_devfn_visible()) + return false; + + uint32_t reg = pci_read_config32(PCI_DEV(0, TXE_DEV, TXE_FUNC), TXE_FWSTS0); + reg &= TXE_CURR_OPMODE_MASK; + reg >>= TXE_CURR_OPMODE_SHIFT; + + return (reg == TXE_FWSTS0_COM_NORMAL); +} + +static bool txe_did_done(void) +{ + if (!is_txe_devfn_visible()) + return false; + + uint32_t reg = pci_read_config32(PCI_DEV(0, TXE_DEV, TXE_FUNC), TXE_DID_MSG); + + return ((reg & DID_MSG_DID_DONE) == DID_MSG_DID_DONE); +} + +int txe_global_reset(void) +{ + int status; + struct mkhi_hdr reply; + struct reset_message { + struct mkhi_hdr hdr; + uint8_t req_origin; + uint8_t reset_type; + } __packed; + struct reset_message msg = { + .hdr = { + .group_id = MKHI_CBM_GROUP_ID, + .command = MKHI_CBM_GLOBAL_RESET, + }, + .req_origin = GR_ORIGIN_BIOS_POST, + .reset_type = 1 + }; + size_t reply_size; + + printk(BIOS_DEBUG, "HECI: Global Reset Command\n"); + + if (!txe_cws_normal()) { + printk(BIOS_ERR, "HECI: TXE does not meet required prerequisites\n"); + return 0; + } + + reply_size = sizeof(reply); + memset(&reply, 0, reply_size); + + txe_txei_init(); + + status = heci_send_receive(&msg, sizeof(msg), &reply, &reply_size, HECI_MKHI_ADDR); + + printk(BIOS_DEBUG, "HECI: Global Reset %s!\n", !status ? "success" : "failure"); + return status; +} + +int txe_get_fw_version(struct get_fw_version_resp *reply) +{ + int status; + struct mkhi_hdr msg = { + .group_id = MKHI_GEN_GROUP_ID, + .command = MKHI_GET_FW_VERSION, + }; + size_t reply_size; + + printk(BIOS_DEBUG, "HECI: Get FW version Command\n"); + + if (!txe_cws_normal()) { + printk(BIOS_ERR, "HECI: TXE does not meet required prerequisites\n"); + return 0; + } + + reply_size = sizeof(*reply); + memset(reply, 0, reply_size); + + txe_txei_init(); + + status = heci_send_receive(&msg, sizeof(msg), reply, &reply_size, HECI_MKHI_ADDR); + + printk(BIOS_DEBUG, "HECI: Get FW version %s!\n", !status ? "success" : "failure"); + return status; +} + +static enum txe_cmd_result decode_heci_send_receive_error(enum txe_tx_rx_status ret) +{ + switch (ret) { + case TXE_TX_ERR_TXE_NOT_READY: + case TXE_RX_ERR_TXE_NOT_READY: + case TXE_RX_ERR_RESP_LEN_MISMATCH: + case TXE_RX_ERR_TIMEOUT: + return TXE_CMD_RESULT_RETRY; + default: + return TXE_CMD_RESULT_ERROR; + } +} + +static enum txe_cmd_result txe_receive_eop(void) +{ + enum { + EOP_REQUESTED_ACTION_CONTINUE = 0, + EOP_REQUESTED_ACTION_GLOBAL_RESET = 1, + }; + enum txe_tx_rx_status ret; + struct end_of_post_resp { + /* FIXME: why this volatile is neded to read the hdr fields properly? */ + volatile struct mkhi_hdr hdr; + uint32_t requested_actions; + } __packed resp = {}; + size_t resp_size = sizeof(resp); + + ret = heci_receive(&resp, &resp_size); + if (ret) + return decode_heci_send_receive_error(ret); + + if (resp.hdr.group_id != MKHI_GEN_GROUP_ID || + resp.hdr.command != MKHI_END_OF_POST) { + printk(BIOS_ERR, "HECI: EOP Unexpected response group or command.\n"); + return TXE_CMD_RESULT_ERROR; + } + + if (resp.hdr.result) { + printk(BIOS_ERR, "HECI: EOP Resp Failed: %u\n", resp.hdr.result); + return TXE_CMD_RESULT_ERROR; + } + + printk(BIOS_INFO, "TXE: EOP requested action: "); + + switch (resp.requested_actions) { + case EOP_REQUESTED_ACTION_GLOBAL_RESET: + printk(BIOS_INFO, "global reset\n"); + return TXE_CMD_RESULT_GLOBAL_RESET_REQUESTED; + case EOP_REQUESTED_ACTION_CONTINUE: + printk(BIOS_INFO, "continue boot\n"); + return TXE_CMD_RESULT_SUCCESS; + default: + printk(BIOS_INFO, "unknown %u\n", resp.requested_actions); + return TXE_CMD_RESULT_ERROR; + } +} + +static enum txe_cmd_result txe_send_eop(void) +{ + enum txe_tx_rx_status ret; + struct end_of_post_msg { + struct mkhi_hdr hdr; + } __packed msg = { + .hdr = { + .group_id = MKHI_GEN_GROUP_ID, + .command = MKHI_END_OF_POST, + }, + }; + + /* + * Prerequisites: + * 1) fwsts0 CWS is Normal + * 2) fwsts0 COM is Normal + * 3) Only sent after DID + */ + if (!txe_cws_normal() || !txe_com_normal() || !txe_did_done()) { + printk(BIOS_ERR, "HECI: Prerequisites not met for sending EOP\n"); + return TXE_CMD_RESULT_ERROR; + } + + printk(BIOS_INFO, "HECI: Sending End-of-Post\n"); + + txe_txei_init(); + + ret = heci_send(&msg, sizeof(msg), BIOS_HOST_ADDR, HECI_MKHI_ADDR); + if (ret) + return decode_heci_send_receive_error(ret); + + return TXE_CMD_RESULT_SUCCESS; +} + +static enum txe_cmd_result txe_send_and_receive_eop(void) +{ + enum txe_cmd_result ret; + + ret = txe_send_eop(); + if (ret != TXE_CMD_RESULT_SUCCESS) + return ret; + + return txe_receive_eop(); +} + +static enum txe_cmd_result txe_send_cmd_retries(enum txe_cmd_result (*txe_send_command)(void)) +{ + size_t retry; + enum txe_cmd_result ret; + for (retry = 0; retry < HECI_MAX_RETRY; retry++) { + ret = txe_send_command(); + if (ret != TXE_CMD_RESULT_RETRY) + break; + } + return ret; +} + +/* + * On EOP error, the BIOS is required to send an MEI bus disable message to the + * TXE, followed by disabling all TXEI devices. After successfully completing + * this, it is safe to boot. + */ +static void txe_handle_eop_error(void) +{ + txe_hide_device(); +} + +static void handle_txe_eop_result(enum txe_cmd_result result) +{ + switch (result) { + case TXE_CMD_RESULT_GLOBAL_RESET_REQUESTED: + printk(BIOS_INFO, "TXE requested global reset in EOP response, resetting...\n"); + global_reset(); + break; + case TXE_CMD_RESULT_SUCCESS: + printk(BIOS_INFO, "TXE EOP successful, continuing boot\n"); + break; + case TXE_CMD_RESULT_DISABLED: + printk(BIOS_INFO, "TXE is disabled, continuing boot\n"); + break; + case TXE_CMD_RESULT_ERROR: /* fallthrough */ + default: + printk(BIOS_ERR, "Failed to send EOP to TXE, %d\n", result); + + /* In non-vboot builds or recovery mode, follow the BWG in order + to continue to boot securely. */ + txe_handle_eop_error(); + break; + } +} + +void txe_do_send_end_of_post(void) +{ + enum txe_cmd_result ret; + + if (platform_is_resuming()) { + printk(BIOS_INFO, "Skip sending EOP during S3 resume\n"); + return; + } + + ret = txe_send_cmd_retries(txe_send_and_receive_eop); + handle_txe_eop_result(ret); +} + +void txe_print_secure_boot_status(void) +{ + union txe_sbsts sb_sts; + + if (!is_txe_devfn_visible()) + return; + + sb_sts.data = pci_read_config32(PCI_DEV(0, TXE_DEV, TXE_FUNC), TXE_SECURE_BOOT_STS); + + printk(BIOS_INFO, "TXE: Secure Boot flow executed: %s " + "(valid only if Global Valid Fuse is set)\n", + sb_sts.fields.sb_executed ? "YES" : "NO"); + printk(BIOS_INFO, "TXE: Recovery flow executed: %s " + "(valid only if Global Valid Fuse is set)\n", + sb_sts.fields.recovery ? "YES" : "NO"); + printk(BIOS_INFO, "TXE: Debug was enabled: %s\n", + sb_sts.fields.debug_was_enabled ? "YES" : "NO"); + printk(BIOS_INFO, "TXE: Debug is enabled: %s\n", + sb_sts.fields.debug_is_enabled ? "YES" : "NO"); + printk(BIOS_INFO, "TXE: Emulation mode: %s\n", + sb_sts.fields.emulation_mode ? "YES" : "NO"); + printk(BIOS_INFO, "TXE: Secure Boot Manifest SVN: 0x%x\n", + sb_sts.fields.sbm_svn); + printk(BIOS_INFO, "TXE: Key Manifest ID: 0x%x\n", + sb_sts.fields.km_id); + printk(BIOS_INFO, "TXE: Key Manifest SVN: 0x%x\n", + sb_sts.fields.km_svn); + printk(BIOS_INFO, "TXE: Alternative BIOS Limit: %08x\n", + sb_sts.fields.alt_bios_limit << 13); +} + +static const char * const txe_bios_actions[] = +{ + "No DRAM Init Done ACK received", + "Non power cycle reset", + "Power cycle reset", + "Go to S3", + "Go to S4", + "Go to S5", + "Perform Global Reset", + "Continue Boot" +}; + +static const char * const txe_cws_values[] = { + [0 ... 15 ] = "Reserved", + [TXE_FWSTS0_CWS_RESET] = "RESET", + [TXE_FWSTS0_CWS_INIT] = "INIT", + [TXE_FWSTS0_CWS_RECOVERY] = "RECOVERY", + [TXE_FWSTS0_CWS_NORMAL] = "NORMAL", +}; + +static const char * const txe_com_values[] = { + [0 ... 15 ] = "Reserved", + [TXE_FWSTS0_COM_NORMAL] = "Normal", + [TXE_FWSTS0_COM_DEBUG] = "Debug", + [TXE_FWSTS0_COM_SOFT_TEMP_DISABLE] = "Soft Temporary Disable", + [TXE_FWSTS0_COM_SECOVER_JMPR] = "Security Override via Jumper", + [TXE_FWSTS0_COM_SECOVER_TXEI_MSG] = "Security Override via MEI Message" +}; + +static const char * const txe_opstate_values[] = { + [0 ... 7] = "Reserved", + [TXE_FWSTS0_STATE_PREBOOT] = "Preboot", + [TXE_FWSTS0_STATE_M0_UMA] = "M0 with UMA", + [TXE_FWSTS0_STATE_MOFF] = "MOff", + [TXE_FWSTS0_STATE_M0] = "M0 without UMA", + [TXE_FWSTS0_STATE_BRINGUP] = "Bring up", + [TXE_FWSTS0_STATE_ERROR] = "M0 without UMA but with error" +}; + +static const char * const txe_pm_event_values[] = { + [0 ... 15] = "Reserved", + [0] = "Clean Moff --> M0 wake", + [1] = "Moff --> M0 wake after error", + [2] = "Clean global reset", + [3] = "Global Reset after an error", + [4] = "Clean SeC reset", + [5] = "SeC reset due to exception", + [6] = "Pseudo-global reset", + [11] = "Power cycle reset through MOff", + [13] = "S0/M0 --> S0/MOff" +}; + +static const char * const txe_error_code_values[] = { + [0 ... 15] = "Reserved", + [0] = "No Error", + [1] = "Uncategorized failure (see Extended Error Code)", + [3] = "Image Failure", + [4] = "Debug Failure", + [5] = "Internal ROM Error", + [6] = "Invalid fuse configuration", + [7] = "Failed to access SPI flash", +}; + +static const char * const txe_progress_code_values[] = { + [0 ... 15] = "Reserved", + [0] = "ROM", + [1] = "Bringup", + [2] = "uKernel", + [3] = "Policy module", + [4] = "Module loading", + [6] = "Host Communication", +}; + +void dump_txe_status(void) +{ + union txe_fwsts0 fwsts0; + union txe_fwsts1 fwsts1; + + if (!is_txe_devfn_visible()) + return; + + fwsts0.data = pci_read_config32(PCI_DEV(0, TXE_DEV, TXE_FUNC), TXE_FWSTS0); + fwsts1.data = pci_read_config32(PCI_DEV(0, TXE_DEV, TXE_FUNC), TXE_FWSTS1); + + + printk(BIOS_DEBUG, "TXE: FWSTS0 : 0x%08X\n", fwsts0.data); + printk(BIOS_DEBUG, "TXE: FWSTS1 : 0x%08X\n", fwsts1.data); + + printk(BIOS_DEBUG, "TXE: Manufacturing Mode : %s\n", + fwsts0.fields.mfg_mode ? "YES" : "NO"); + printk(BIOS_DEBUG, "TXE: FW Partition Table : %s\n", + fwsts0.fields.fpt_bad ? "BAD" : "OK"); + printk(BIOS_DEBUG, "TXE: Bringup Loader Failure : %s\n", + fwsts0.fields.ft_bup_ld_flr ? "YES" : "NO"); + printk(BIOS_DEBUG, "TXE: Firmware Init Complete : %s\n", + fwsts0.fields.fw_init_complete ? "YES" : "NO"); + printk(BIOS_DEBUG, "TXE: Update In Progress : %s\n", + fwsts0.fields.update_in_progress ? "YES" : "NO"); + printk(BIOS_DEBUG, "TXE: Current Working State : %u (%s)\n", + fwsts0.fields.working_state, + txe_cws_values[fwsts0.fields.working_state]); + printk(BIOS_DEBUG, "TXE: Current Operation State : %u (%s)\n", + fwsts0.fields.operation_state, + txe_opstate_values[fwsts0.fields.operation_state]); + printk(BIOS_DEBUG, "TXE: Current Operation Mode : %u (%s)\n", + fwsts0.fields.operation_mode, + txe_com_values[fwsts0.fields.operation_mode]); + printk(BIOS_DEBUG, "TXE: DRAM Init Done ACK : %u\n", + fwsts0.fields.bios_msg_ack); + printk(BIOS_DEBUG, "TXE: BIOS Action : %s\n", + txe_bios_actions[fwsts0.fields.ack_data]); + printk(BIOS_DEBUG, "TXE: Progress Code : %u (%s)\n", + fwsts1.fields.progress_code, + txe_progress_code_values[fwsts1.fields.progress_code]); + printk(BIOS_DEBUG, "TXE: PM Event : %u (%s)\n", + fwsts1.fields.current_pmevent, + txe_pm_event_values[fwsts1.fields.current_pmevent]); + printk(BIOS_DEBUG, "TXE: Error Code : %u (%s)\n", + fwsts0.fields.error_code, + txe_error_code_values[fwsts0.fields.error_code]); + printk(BIOS_DEBUG, "TXE: Extended Error Code : %u\n", + fwsts1.fields.current_state); +} From 39ea044a70ab2592d871079c82ec4c48880abd4c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Fri, 10 May 2024 17:03:05 +0200 Subject: [PATCH 17/56] payloads/external/SeaBIOS: Add option to override CBFS location MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If the CBFS end is not at address 0xFFFFFFFF, then SeabIOS will not be able to find CBFS. This option allows to set the CBFS end in situations where COREBOOT region does not end at address 0xFFFFFFFF. Signed-off-by: Michał Żygowski --- payloads/external/Makefile.mk | 3 ++- payloads/external/SeaBIOS/Kconfig | 4 ++++ payloads/external/SeaBIOS/Makefile | 1 + 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/payloads/external/Makefile.mk b/payloads/external/Makefile.mk index 0855e6815b4..4da1d807135 100644 --- a/payloads/external/Makefile.mk +++ b/payloads/external/Makefile.mk @@ -87,7 +87,8 @@ $(SEABIOS_TARGET_PATH): $(DOTCONFIG) CONFIG_DRIVERS_UART_8250MEM_32=$(CONFIG_DRIVERS_UART_8250MEM_32) \ CONFIG_ENABLE_HSUART=$(CONFIG_ENABLE_HSUART) \ CONFIG_CONSOLE_UART_BASE_ADDRESS=$(CONFIG_CONSOLE_UART_BASE_ADDRESS) \ - CONFIG_SEABIOS_HARDWARE_IRQ=$(CONFIG_SEABIOS_HARDWARE_IRQ) + CONFIG_SEABIOS_HARDWARE_IRQ=$(CONFIG_SEABIOS_HARDWARE_IRQ) \ + CONFIG_SEABIOS_CBFS_LOCATION=$(CONFIG_SEABIOS_CBFS_LOCATION) payloads/external/SeaBIOS/seabios/out/vgabios.bin: $(SEABIOS_TARGET_PATH) payloads/external/SeaBIOS/seabios/.config: $(SEABIOS_TARGET_PATH) diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig index 5131fe3f121..4a66aaad833 100644 --- a/payloads/external/SeaBIOS/Kconfig +++ b/payloads/external/SeaBIOS/Kconfig @@ -141,6 +141,10 @@ config SEABIOS_SERCON_PORT_ADDR By default primary console UART defined by TTYS0_BASE is used. +config SEABIOS_CBFS_LOCATION + hex + default 0x0 + config PAYLOAD_VGABIOS_FILE string depends on SEABIOS_VGA_COREBOOT diff --git a/payloads/external/SeaBIOS/Makefile b/payloads/external/SeaBIOS/Makefile index 7926f3fb90a..ca0d52a27df 100644 --- a/payloads/external/SeaBIOS/Makefile +++ b/payloads/external/SeaBIOS/Makefile @@ -39,6 +39,7 @@ checkout: fetch config: checkout echo " CONFIG SeaBIOS $(TAG-y)" echo "CONFIG_COREBOOT=y" > seabios/.config + echo "CONFIG_CBFS_LOCATION=$(CONFIG_SEABIOS_CBFS_LOCATION)" >> seabios/.config ifeq ($(CONFIG_CONSOLE_SERIAL)$(CONFIG_DRIVERS_UART_8250IO),yy) echo "CONFIG_DEBUG_SERIAL=y" >> seabios/.config echo "CONFIG_DEBUG_SERIAL_PORT=$(CONFIG_TTYS0_BASE)" >> seabios/.config From 6ea62c4f94c99fcca1038f9d993bde9250163d9d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 9 Apr 2024 12:51:54 +0200 Subject: [PATCH 18/56] soc/intel/baytrail: Put microcode and bootblock into BOOTBLOCK region MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit With CBFS_VERIFICATION one cannot fetch the early microcode update from CBFS, as walkcbfs_asm is unsafe to be compiled with CBFS_VERIFICATION. As a workaround, put a microcode copy in the IBB under a fixed address. Bootblock and microcode will be verified by TXE when TXE_SECURE_BOOT is enabled, so it will be safe to use. Also put the microcode and bootblock in the BOOTBLOCK region which will cover whole IBB to cleanly separate code and data to be verfied by TXE from the rest of CBFS. it will make the updates easier and keep CBFS_VERIFICATION working properly. Signed-off-by: Michał Żygowski --- src/cpu/intel/microcode/Makefile.mk | 2 + src/soc/intel/baytrail/Kconfig | 50 +++++-- src/soc/intel/baytrail/Makefile.mk | 36 +++-- .../intel/baytrail/bootblock/microcode_asm.S | 128 ++++++++++++++++++ 4 files changed, 188 insertions(+), 28 deletions(-) create mode 100644 src/soc/intel/baytrail/bootblock/microcode_asm.S diff --git a/src/cpu/intel/microcode/Makefile.mk b/src/cpu/intel/microcode/Makefile.mk index 4e10a4b15f1..abad89eb0bc 100644 --- a/src/cpu/intel/microcode/Makefile.mk +++ b/src/cpu/intel/microcode/Makefile.mk @@ -1,6 +1,8 @@ ## SPDX-License-Identifier: GPL-2.0-only +ifneq ($(CONFIG_CBFS_VERIFICATION),y) bootblock-$(CONFIG_MICROCODE_UPDATE_PRE_RAM) += microcode_asm.S +endif bootblock-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c ramstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index b4aa36a9983..9d5fd4de171 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -161,9 +161,14 @@ config VGA_BIOS_ID depends on VGA_BIOS default "8086,0f31" +config BAYTRAIL_FTPM + bool "Enable fTPM functionality in TXE" + default n + config TXE_SECURE_BOOT bool "Perform verified boot with TXE Secure Boot" depends on !VBOOT + select FIXED_BOOTBLOCK_SIZE default n help The TXE on Baytrail SOC has Secure Boot capability. Choose this @@ -255,20 +260,49 @@ config TXE_SB_SBM_MANIFEST_SVN if TXE_SECURE_BOOT -# Put the microcode right after the manifest, so it will be verified by IBB -# and accessible without walkcbfs ASM routine if CBFS_VERIFICATION is enabled. -config CPU_MICROCODE_CBFS_LOC +# This addresses will be used by BSP to locate microcode in bootblock before +# setting up CAR. With CBFS verification we cannot use walkcbfs ASM routine, so +# put the microcode copy in the BOOTBLOCK FMAP region right after SB manifest +# for use by BSP. APs will load microcode from CBFS file in COREBOOT region when +# CBFS_VERIFICATION will be able to verify it already in ramstage. It is safe to +# hardcode the address, because TXE will verify it together with IBB. + +config EARLY_CPU_MICROCODE_LOC hex - default 0xfffe1000 + default 0xfffe0400 -config CPU_MICROCODE_CBFS_LEN +config EARLY_CPU_MICROCODE_LEN hex default 0x19800 -endif +# Ensure the bootblock does not overlap the microcode. We have 0x6400 bytes +# of space after microcode till the ned of ROM. Make a small gap of 256 bytes +# between the microcode and the bootblock just in case. Linker may add some +# additional data in the beginning of the bootblock binary. -config BAYTRAIL_FTPM - bool "Enable fTPM functionality in TXE" +config C_ENV_BOOTBLOCK_SIZE + default 0x6300 + +# Make sure nothing gets in the IBB besides bootblock and microcode, because +# if any CBFS file is put into IBB, it will not be available after +# FW_SHADOW_DONE. Thus we put bootblock into the FMAP region. + +config BOOTBLOCK_IN_CBFS + bool default n +if PAYLOAD_SEABIOS + +# Need to override the end of CBFS region for SeaBIOS to work properly +# 0xfffdf000 is the beginning address of Key Manifest. If no Key Manifest +# is used, then it may be 0xfffe0000. Of course it also depends on FMAP +# layout. +config SEABIOS_CBFS_LOCATION + default 0xfffdf000 if TXE_SB_INCLUDE_KEY_MANIFEST + default 0xfffe0000 + +endif # PAYLOAD_SEABIOS + +endif # TXE_SECURE_BOOT + endif diff --git a/src/soc/intel/baytrail/Makefile.mk b/src/soc/intel/baytrail/Makefile.mk index 28deeed9f9f..2f825d3746f 100644 --- a/src/soc/intel/baytrail/Makefile.mk +++ b/src/soc/intel/baytrail/Makefile.mk @@ -11,6 +11,9 @@ all-y += tsc_freq.c bootblock-y += ../../../cpu/intel/car/non-evict/cache_as_ram.S bootblock-y += ../../../cpu/intel/car/bootblock.c bootblock-y += ../../../cpu/x86/early_reset.S +ifeq ($(CONFIG_CBFS_VERIFICATION),y) +bootblock-$(CONFIG_TXE_SECURE_BOOT) += bootblock/microcode_asm.S +endif bootblock-y += bootblock/bootblock.c romstage-y += iosf.c @@ -90,33 +93,26 @@ endif ifeq ($(CONFIG_TXE_SECURE_BOOT),y) -cbfs-files-y += manifests.bin -manifests.bin-file := $(objcbfs)/sb_manifests -manifests.bin-type := raw - -ifeq ($(CONFIG_TXE_SB_INCLUDE_KEY_MANIFEST),y) +# Add BSP microcode to bootblock region +microcode_pos = $(call int-subtract, $(CONFIG_ROM_SIZE) $(call int-subtract, 0x100000000 $(CONFIG_EARLY_CPU_MICROCODE_LOC))) -manifests.bin-COREBOOT-position := $(call int-subtract, 0x100000000 0x21000) +add_bootblock = \ + $(CBFSTOOL) $(1) write -d -r BOOTBLOCK -f $(2); \ + dd if=$(cpu_microcode_blob.bin-file) of=$(1) conv=notrunc bs=1 \ + seek=$(microcode_pos) >/dev/null 2>&1 +ifeq ($(CONFIG_TXE_SB_INCLUDE_KEY_MANIFEST),y) ifneq ($(call strip_quotes,$(CONFIG_TXE_SB_KEY_MANIFEST_PATH)),) -$(objcbfs)/sb_manifests: $(call strip_quotes,$(CONFIG_TXE_SB_KEY_MANIFEST_PATH)) - dd if=/dev/zero of=$@ bs=5120 count=1 2> /dev/null - dd if=$< of=$@ conv=notrunc 2> /dev/null -else +key_manifest_pos = $(call int-subtract, $(CONFIG_ROM_SIZE) 0x21000) -$(objcbfs)/sb_manifests: - dd if=/dev/zero of=$@ bs=5120 count=1 2> /dev/null +$(call add_intermediate, add_txe_sb_km, $(call strip_quotes,$(CONFIG_TXE_SB_KEY_MANIFEST_PATH))) + printf " DD Adding SB Key Manifest\n" \ + dd if=$(CONFIG_TXE_SB_KEY_MANIFEST_PATH) \ + of=$< conv=notrunc bs=4K \ + seek=$(key_manifest_pos) >/dev/null 2>&1 endif - -else # CONFIG_TXE_SB_INCLUDE_KEY_MANIFEST - -manifests.bin-COREBOOT-position := $(call int-subtract, 0x100000000 0x20000) - -$(objcbfs)/sb_manifests: - dd if=/dev/zero of=$@ bs=1024 count=1 2> /dev/null - endif # CONFIG_TXE_SB_INCLUDE_KEY_MANIFEST files_added:: $(obj)/coreboot.rom $(TXESBMANTOOL) diff --git a/src/soc/intel/baytrail/bootblock/microcode_asm.S b/src/soc/intel/baytrail/bootblock/microcode_asm.S new file mode 100644 index 00000000000..e01bf573d07 --- /dev/null +++ b/src/soc/intel/baytrail/bootblock/microcode_asm.S @@ -0,0 +1,128 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * input %esp: return address (not pointer to return address!) + * clobber the content of eax, ebx, ecx, edx, esi, edi, and ebp + */ + +#include +#include + +#define HEADER_VER_OFFSET 0 +#define UPDATE_VER_OFFSET 4 +#define DATE_OFFSET 8 +#define PROCESSOR_SIG_OFFSET 12 +#define CHKSUM_OFFSET 16 +#define LOADER_REV_OFFSET 20 +#define PROCESSOR_FLAG 24 +#define DATA_SIZE_OFFSET 28 +#define TOTAL_OFFSET 32 +#define HEADER_SIZE 48 + +/* + * The microcode header is 48 bytes wide and has the following + * structure: + * Header Version : 32bit + * Update Revision : 32bit + * Date : 32bit + * Processor Signature : 32bit + * Checksum : 32bit + * Loader Revision : 32bit + * Processor Flags : 32bit + * Data Size : 32bit + * Total Size : 32bit + * Reserved : 96bit + * + * We only check if the Processor signature and flags match and check + * if the revision of the update is newer than what is installed + */ + +.code32 +.section .init +.global update_bsp_microcode + +update_bsp_microcode: + movl $(CONFIG_EARLY_CPU_MICROCODE_LOC), %esi + movl $(CONFIG_EARLY_CPU_MICROCODE_LEN), %edi + addl %esi, %edi + + /* + * Microcode revision -> %ebx + * Processor flags -> %ebp + * Current installed microcode revision -> %edx + */ + + /* Processor flags + * rdmsr 0x17 + * pf = 1 << ((msr.hi >> 18) & 7) */ + movl $IA32_PLATFORM_ID, %ecx + rdmsr + shr $18, %edx + andl $7, %edx + movl $1, %eax + /* needs to be %cl for shl */ + movl %edx, %ecx + shl %cl, %eax + movl %eax, %ebp + + /* Fetch the current microcode revision*/ + xorl %eax, %eax + xorl %edx, %edx + movl $IA32_BIOS_SIGN_ID, %ecx + wrmsr + movl $0x1, %eax + cpuid + + /* Processor family+model signature=cpuid_eax(1) */ + movl %eax, %ebx + + movl $IA32_BIOS_SIGN_ID, %ecx + rdmsr + +check_microcode_entry: + /* Test if header revision is non zero */ + cmpl $0, HEADER_VER_OFFSET(%esi) + je end_microcode_update + + /* Processor family+model signature=cpuid_eax(1) */ + cmpl PROCESSOR_SIG_OFFSET(%esi), %ebx + jne next_entry + + /* Processor flags */ + test PROCESSOR_FLAG(%esi), %ebp + jz next_entry + + /* Check if revision is higher than current */ + cmpl UPDATE_VER_OFFSET(%esi), %edx + /* Don't upgrade if already greater or equal */ + jge end_microcode_update + + /* Do actual update */ + movl %esi, %eax + addl $HEADER_SIZE, %eax + xorl %edx, %edx + movl $IA32_BIOS_UPDT_TRIG, %ecx + wrmsr + + jmp end_microcode_update + +next_entry: + movl TOTAL_OFFSET(%esi), %eax + cmpl $0, %eax + jne 1f + /* Newer microcode updates include a size field, whereas older + * containers set it at 0 and are exactly 2048 bytes long */ + addl $2048, %esi + jmp check_end +1: + addl %eax, %esi + +check_end: + cmpl %esi, %edi + ja check_microcode_entry + +end_microcode_update: + jmp *%esp + + +_update_bsp_microcode_end: From d4774c07a370d096add4e2209415ce8bd63237c8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Wed, 15 May 2024 15:47:24 +0200 Subject: [PATCH 19/56] src/device/dram/ddr3.c: Add ECC type to DDR3 parsed data MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The spd_add_smbios17 function already assumes MEMORY_BUS_WIDTH_64 non-ECC only, but did not fill in the ecc_type information, which resulted in SMBIOS type 16 Memory Error Correction field to be out of specitions (0 is not defined). Fill in the ecc_type field as MEMORY_ARRAY_ECC_NONE. Signed-off-by: Michał Żygowski --- src/device/dram/ddr3.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index 1fa3f4c3b2b..7c6448f9d56 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -544,6 +544,8 @@ enum cb_err spd_add_smbios17(const u8 channel, const u8 slot, const u16 selected mem_info->dimm_cnt++; } + mem_info->ecc_type = MEMORY_ARRAY_ECC_NONE; + return CB_SUCCESS; } From 3dd9ee66ed6291ce0955ba85cd37e69905c2bc82 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Fri, 10 May 2024 17:04:58 +0200 Subject: [PATCH 20/56] mb/intel/minnowmax: Add layout with separate bootblock and manifests MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- src/mainboard/intel/minnowmax/Kconfig | 4 ++++ src/mainboard/intel/minnowmax/board.fmd | 15 +++++++++++++++ src/mainboard/intel/minnowmax/board_sb.fmd | 17 +++++++++++++++++ 3 files changed, 36 insertions(+) create mode 100644 src/mainboard/intel/minnowmax/board.fmd create mode 100644 src/mainboard/intel/minnowmax/board_sb.fmd diff --git a/src/mainboard/intel/minnowmax/Kconfig b/src/mainboard/intel/minnowmax/Kconfig index 27eded4da59..6c7c9f7d742 100644 --- a/src/mainboard/intel/minnowmax/Kconfig +++ b/src/mainboard/intel/minnowmax/Kconfig @@ -54,4 +54,8 @@ config VGA_BIOS bool default y +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board_sb.fmd" if TXE_SECURE_BOOT + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd" + endif # BOARD_INTEL_MINNOWMAX diff --git a/src/mainboard/intel/minnowmax/board.fmd b/src/mainboard/intel/minnowmax/board.fmd new file mode 100644 index 00000000000..0107e0db5dd --- /dev/null +++ b/src/mainboard/intel/minnowmax/board.fmd @@ -0,0 +1,15 @@ +FLASH 8M { + SI_ALL 2M { + SI_DESC 4K + SI_ME + } + + RW_MRC_CACHE 64K + SMMSTORE 256K + BOOTSPLASH 512K + + WP_RO { + FMAP 4K + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/intel/minnowmax/board_sb.fmd b/src/mainboard/intel/minnowmax/board_sb.fmd new file mode 100644 index 00000000000..4b51911de2c --- /dev/null +++ b/src/mainboard/intel/minnowmax/board_sb.fmd @@ -0,0 +1,17 @@ +FLASH 8M { + SI_ALL 2M { + SI_DESC 4K + SI_ME + } + + RW_MRC_CACHE 64K + SMMSTORE 256K + BOOTSPLASH 512K + + WP_RO { + FMAP 4K + COREBOOT(CBFS) + MANIFESTS 0x1400 + BOOTBLOCK 0x1fc00 + } +} From e1a4d8353d380c6da449499560e7a3c377cad4f3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Fri, 10 May 2024 15:04:57 +0200 Subject: [PATCH 21/56] src/mainboard/intel/minnowmax: Use SPDX license headers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- src/mainboard/intel/minnowmax/Kconfig | 16 +----------- src/mainboard/intel/minnowmax/Kconfig.name | 2 ++ src/mainboard/intel/minnowmax/Makefile.inc | 25 ------------------- src/mainboard/intel/minnowmax/Makefile.mk | 12 +++++++++ src/mainboard/intel/minnowmax/acpi/ec.asl | 1 + .../intel/minnowmax/acpi/mainboard.asl | 17 +------------ .../intel/minnowmax/acpi/superio.asl | 1 + src/mainboard/intel/minnowmax/acpi_tables.c | 16 +----------- src/mainboard/intel/minnowmax/cmos.layout | 15 +---------- src/mainboard/intel/minnowmax/devicetree.cb | 16 +----------- src/mainboard/intel/minnowmax/dsdt.asl | 17 +------------ src/mainboard/intel/minnowmax/gpio.c | 16 +----------- src/mainboard/intel/minnowmax/irqroute.c | 15 +---------- src/mainboard/intel/minnowmax/irqroute.h | 16 +----------- src/mainboard/intel/minnowmax/mainboard.c | 17 +------------ src/mainboard/intel/minnowmax/romstage.c | 18 +------------ 16 files changed, 27 insertions(+), 193 deletions(-) delete mode 100644 src/mainboard/intel/minnowmax/Makefile.inc create mode 100644 src/mainboard/intel/minnowmax/Makefile.mk diff --git a/src/mainboard/intel/minnowmax/Kconfig b/src/mainboard/intel/minnowmax/Kconfig index 6c7c9f7d742..f9d5ca4c7fd 100644 --- a/src/mainboard/intel/minnowmax/Kconfig +++ b/src/mainboard/intel/minnowmax/Kconfig @@ -1,18 +1,4 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. -## Copyright (C) 2014 Intel Corporation -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +## SPDX-License-Identifier: GPL-2.0-only if BOARD_INTEL_MINNOWMAX diff --git a/src/mainboard/intel/minnowmax/Kconfig.name b/src/mainboard/intel/minnowmax/Kconfig.name index abe92259603..a8606fccc8c 100644 --- a/src/mainboard/intel/minnowmax/Kconfig.name +++ b/src/mainboard/intel/minnowmax/Kconfig.name @@ -1,2 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + config BOARD_INTEL_MINNOWMAX bool "Minnow Max" diff --git a/src/mainboard/intel/minnowmax/Makefile.inc b/src/mainboard/intel/minnowmax/Makefile.inc deleted file mode 100644 index 9c957ecbb33..00000000000 --- a/src/mainboard/intel/minnowmax/Makefile.inc +++ /dev/null @@ -1,25 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -ramstage-y += gpio.c -ramstage-y += irqroute.c - -#SPD_SOURCES = micron_1GiB_1066MHz_dimm_MT41K256M16HA-125 # 0b0000 -#SPD_SOURCES += micron_2GiB_1066MHz_dimm_MT41K256M16HA-125 # 0b0001 -#SPD_SOURCES += micron_1GiB_1333MHz_dimm_MT41K256M16HA-125 # 0b0010 -#SPD_SOURCES += micron_2GiB_1333MHz_dimm_MT41K256M16HA-125 # 0b0011 - -SPD_SOURCES = micron_1GiB_dimm_MT41K256M16HA-125 # 0b0000 -SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125 # 0b0001 diff --git a/src/mainboard/intel/minnowmax/Makefile.mk b/src/mainboard/intel/minnowmax/Makefile.mk new file mode 100644 index 00000000000..b7e5ce29c5f --- /dev/null +++ b/src/mainboard/intel/minnowmax/Makefile.mk @@ -0,0 +1,12 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ramstage-y += gpio.c +ramstage-y += irqroute.c + +#SPD_SOURCES = micron_1GiB_1066MHz_dimm_MT41K256M16HA-125 # 0b0000 +#SPD_SOURCES += micron_2GiB_1066MHz_dimm_MT41K256M16HA-125 # 0b0001 +#SPD_SOURCES += micron_1GiB_1333MHz_dimm_MT41K256M16HA-125 # 0b0010 +#SPD_SOURCES += micron_2GiB_1333MHz_dimm_MT41K256M16HA-125 # 0b0011 + +SPD_SOURCES = micron_1GiB_dimm_MT41K256M16HA-125 # 0b0000 +SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125 # 0b0001 diff --git a/src/mainboard/intel/minnowmax/acpi/ec.asl b/src/mainboard/intel/minnowmax/acpi/ec.asl index e69de29bb2d..853b0877b33 100644 --- a/src/mainboard/intel/minnowmax/acpi/ec.asl +++ b/src/mainboard/intel/minnowmax/acpi/ec.asl @@ -0,0 +1 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ diff --git a/src/mainboard/intel/minnowmax/acpi/mainboard.asl b/src/mainboard/intel/minnowmax/acpi/mainboard.asl index c159c847a7d..7d1b0a91168 100644 --- a/src/mainboard/intel/minnowmax/acpi/mainboard.asl +++ b/src/mainboard/intel/minnowmax/acpi/mainboard.asl @@ -1,19 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - +/* SPDX-License-Identifier: GPL-2.0-only */ Scope (\_SB.PCI0.LPEA) { diff --git a/src/mainboard/intel/minnowmax/acpi/superio.asl b/src/mainboard/intel/minnowmax/acpi/superio.asl index e69de29bb2d..853b0877b33 100644 --- a/src/mainboard/intel/minnowmax/acpi/superio.asl +++ b/src/mainboard/intel/minnowmax/acpi/superio.asl @@ -0,0 +1 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ diff --git a/src/mainboard/intel/minnowmax/acpi_tables.c b/src/mainboard/intel/minnowmax/acpi_tables.c index 743e2e2c06e..d3b6582ddf9 100644 --- a/src/mainboard/intel/minnowmax/acpi_tables.c +++ b/src/mainboard/intel/minnowmax/acpi_tables.c @@ -1,18 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/mainboard/intel/minnowmax/cmos.layout b/src/mainboard/intel/minnowmax/cmos.layout index 4cb51061912..b3cea3cd0fc 100644 --- a/src/mainboard/intel/minnowmax/cmos.layout +++ b/src/mainboard/intel/minnowmax/cmos.layout @@ -1,17 +1,4 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +## SPDX-License-Identifier: GPL-2.0-only # ----------------------------------------------------------------- entries diff --git a/src/mainboard/intel/minnowmax/devicetree.cb b/src/mainboard/intel/minnowmax/devicetree.cb index 43203ebea60..2e5ca78fd75 100644 --- a/src/mainboard/intel/minnowmax/devicetree.cb +++ b/src/mainboard/intel/minnowmax/devicetree.cb @@ -1,18 +1,4 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. -## Copyright (C) 2014 Intel Corporation -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +## SPDX-License-Identifier: GPL-2.0-only chip soc/intel/baytrail # SATA port enable mask (2 ports) diff --git a/src/mainboard/intel/minnowmax/dsdt.asl b/src/mainboard/intel/minnowmax/dsdt.asl index b3fd497025c..09db35910de 100644 --- a/src/mainboard/intel/minnowmax/dsdt.asl +++ b/src/mainboard/intel/minnowmax/dsdt.asl @@ -1,19 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #define INCLUDE_LPE 1 #define INCLUDE_SCC 1 diff --git a/src/mainboard/intel/minnowmax/gpio.c b/src/mainboard/intel/minnowmax/gpio.c index b0f78c8b57d..15c114129c8 100644 --- a/src/mainboard/intel/minnowmax/gpio.c +++ b/src/mainboard/intel/minnowmax/gpio.c @@ -1,18 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/mainboard/intel/minnowmax/irqroute.c b/src/mainboard/intel/minnowmax/irqroute.c index db8c512a439..6fa036672e6 100644 --- a/src/mainboard/intel/minnowmax/irqroute.c +++ b/src/mainboard/intel/minnowmax/irqroute.c @@ -1,17 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include "irqroute.h" diff --git a/src/mainboard/intel/minnowmax/irqroute.h b/src/mainboard/intel/minnowmax/irqroute.h index 3e40e50d018..9739f6f620c 100644 --- a/src/mainboard/intel/minnowmax/irqroute.h +++ b/src/mainboard/intel/minnowmax/irqroute.h @@ -1,18 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include diff --git a/src/mainboard/intel/minnowmax/mainboard.c b/src/mainboard/intel/minnowmax/mainboard.c index 0fe12594207..e87b3bba78f 100644 --- a/src/mainboard/intel/minnowmax/mainboard.c +++ b/src/mainboard/intel/minnowmax/mainboard.c @@ -1,19 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include diff --git a/src/mainboard/intel/minnowmax/romstage.c b/src/mainboard/intel/minnowmax/romstage.c index 4b6b95c500c..0bd9d16fc4b 100644 --- a/src/mainboard/intel/minnowmax/romstage.c +++ b/src/mainboard/intel/minnowmax/romstage.c @@ -1,20 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * Copyright (C) 2014 Intel Corporation - * Copyright (C) 2018 CMR Surgical Limited - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include #include From 6d73706625fe0e8915af73105e76100ce70b8a20 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 25 Jul 2024 12:55:40 +0200 Subject: [PATCH 22/56] 3rdparty/dasharo-blobs: Bump For MinnowBoard blobs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- 3rdparty/dasharo-blobs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty/dasharo-blobs b/3rdparty/dasharo-blobs index 1048394018f..d4c10a43fb3 160000 --- a/3rdparty/dasharo-blobs +++ b/3rdparty/dasharo-blobs @@ -1 +1 @@ -Subproject commit 1048394018f9f8a65ee8d1546f0303fd5fa79f8c +Subproject commit d4c10a43fb3e26e557d071cda7e802fdeab40084 From 55a5223c6fb8dab3f077ee8626770ace0b56a6c2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 25 Jul 2024 12:59:26 +0200 Subject: [PATCH 23/56] configs/config.intel_minnowmax: Add configs for regular and SB build MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- .github/workflows/build.yml | 50 +++++++++++++++- .github/workflows/deploy-template.yml | 8 +++ ...minnowmax => config.intel_minnowmax_no_sb} | 17 ++++-- configs/config.intel_minnowmax_sb | 59 +++++++++++++++++++ 4 files changed, 128 insertions(+), 6 deletions(-) rename configs/{config.intel_minnowmax => config.intel_minnowmax_no_sb} (71%) create mode 100644 configs/config.intel_minnowmax_sb diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 5873e6d1295..9347d4f4bb8 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -264,6 +264,39 @@ jobs: path: | build/coreboot.rom retention-days: 30 + build_intel_minnowmax: + runs-on: ubuntu-22.04 + container: + image: ghcr.io/dasharo/dasharo-sdk:v1.5.0 + options: --user 1001 + strategy: + matrix: + vendor: [ intel ] + model: [ minnowmax ] + variant: [ no_sb, sb ] + steps: + - name: Checkout repository + uses: actions/checkout@v4 + with: + # Checkout pull request HEAD commit instead of merge commit + # See: https://github.com/actions/checkout#checkout-pull-request-head-commit-instead-of-merge-commit + ref: ${{ github.event.pull_request.head.sha }} + # Fetch complete history + fetch-depth: 0 + - name: Checkout all submodules + run: git submodule update --init --recursive --checkout + - name: Build Dasharo + run: | + cp configs/config.${{ matrix.vendor }}_${{ matrix.model }}_${{ matrix.variant }} .config + make olddefconfig + make + - name: Save artifacts + uses: actions/upload-artifact@v4 + with: + name: "dasharo-${{ matrix.vendor }}-${{ matrix.model }}-${{ matrix.variant }}" + path: | + build/coreboot.rom + retention-days: 30 deploy_protectli_adl: if: startsWith(github.ref, 'refs/tags/protectli_vault_adl') @@ -375,4 +408,19 @@ jobs: strategy: matrix: vendor: [ hardkernel ] - model: [ odroid_h4 ] \ No newline at end of file + model: [ odroid_h4 ] + deploy_intel_minnowmax: + if: startsWith(github.ref, 'refs/tags/intel_minnowmax') + needs: build_intel_minnowmax + uses: ./.github/workflows/deploy-template.yml + with: + platform: intel + vendor: ${{ matrix.vendor }} + model: ${{ matrix.model }} + type: ${{ matrix.type }} + secrets: inherit + strategy: + matrix: + vendor: [ intel ] + model: [ minnowmax ] + type: [ no_sb, sb ] diff --git a/.github/workflows/deploy-template.yml b/.github/workflows/deploy-template.yml index 1e094c0632e..6ca6a0682a4 100644 --- a/.github/workflows/deploy-template.yml +++ b/.github/workflows/deploy-template.yml @@ -48,6 +48,10 @@ jobs: base_dir="msi" model=$(echo "$tag" | cut -d'_' -f1-2) release=$(echo "$tag" | cut -d'_' -f3) + elif [ "${{ inputs.platform }}" == "intel" ]; then + base_dir="3mdeb/intel_minnowmax" + model="" + release=$(echo "$tag" | cut -d'_' -f3) fi echo "base_dir=$base_dir" >> "$GITHUB_OUTPUT" echo "model=$model" >> "$GITHUB_OUTPUT" @@ -68,6 +72,8 @@ jobs: first_part=$(echo ${{ steps.tag_name.outputs.tag }} | cut -d "_" -f1) second_part=$(echo ${{ steps.tag_name.outputs.tag }} | cut -d "_" -f2) echo "artifact_name=dasharo-$first_part-${second_part}_${{ inputs.type }}" >> "$GITHUB_OUTPUT" + elif [ "${{ inputs.platform }}" == "intel" ]; then + echo "artifact_name=dasharo-${{ inputs.vendor }}-${{ inputs.model }}-${{ inputs.type }}" >> "$GITHUB_OUTPUT" fi - name: Download workflow artifact @@ -93,6 +99,8 @@ jobs: new_name=$(echo "${{ inputs.vendor }}_${{ inputs.model }}_${{ inputs.payload }}_${release}.rom" | sed 's/.*/\L&/') elif [ "${{ inputs.platform }}" == "msi" ]; then new_name=$(echo "${model}_${{ inputs.type }}_${release}.rom" | sed 's/-/_/g; s/.*/\L&/') + elif [ "${{ inputs.platform }}" == "intel" ]; then + new_name=$(echo "${{ inputs.vendor }}-${{ inputs.model }}-${{ inputs.type }}_${release}.rom" | sed 's/-/_/g; s/.*/\L&/') fi # Create release directory if it doesn't exist diff --git a/configs/config.intel_minnowmax b/configs/config.intel_minnowmax_no_sb similarity index 71% rename from configs/config.intel_minnowmax rename to configs/config.intel_minnowmax_no_sb index dd569fb8221..ebbd9abdbfe 100644 --- a/configs/config.intel_minnowmax +++ b/configs/config.intel_minnowmax_no_sb @@ -1,22 +1,30 @@ +CONFIG_LOCALVERSION="0.9.0-rc1" CONFIG_VENDOR_INTEL=y CONFIG_ONBOARD_VGA_IS_PRIMARY=y # CONFIG_VGA_BIOS is not set CONFIG_PXE_ROM_ID="8086,1539" -CONFIG_IFD_BIN_PATH="IFWI_HEADER.bin" -CONFIG_ME_BIN_PATH="VLV_SEC_REGION.bin" +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/txe.bin" CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 CONFIG_EDK2_BOOT_TIMEOUT=3 CONFIG_BOARD_INTEL_MINNOWMAX=y CONFIG_HAVE_IFD_BIN=y CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/dasharo/bootsplash.bmp" CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/mrc.elf" +CONFIG_MRC_RMT=y CONFIG_HAVE_ME_BIN=y CONFIG_NO_GFX_INIT=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y CONFIG_BOOTMEDIA_SMM_BWP=y CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y CONFIG_PAYLOAD_EDK2=y CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2" -CONFIG_EDK2_TAG_OR_REV="ae0ecedb0c0e57157f11e320f6a4e66806355404" +CONFIG_EDK2_TAG_OR_REV="f6f62e8efe2fd35d2f28c906e8e72a8b7f12b28c" CONFIG_EDK2_USE_EDK2_PLATFORMS=y CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" CONFIG_EDK2_PLATFORMS_TAG_OR_REV="3323ed481d35096fb6a7eae7b49f35eff00f86cf" @@ -24,7 +32,7 @@ CONFIG_EDK2_CBMEM_LOGGING=y CONFIG_EDK2_FOLLOW_BGRT_SPEC=y # CONFIG_EDK2_PS2_SUPPORT is not set CONFIG_EDK2_SERIAL_SUPPORT=y -CONFIG_EDK2_GOP_FILE="IntelBYTGopDriver.efi" +CONFIG_EDK2_GOP_FILE="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/IntelGopDriver.efi" CONFIG_EDK2_DISABLE_TPM=y CONFIG_BUILD_IPXE=y # CONFIG_IPXE_SERIAL_CONSOLE is not set @@ -39,7 +47,6 @@ CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y CONFIG_EDK2_DASHARO_USB_CONFIG=y CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y -CONFIG_EDK2_DASHARO_NETWORK_BOOT_DEFAULT_ENABLE=y CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y CONFIG_EDK2_BOOT_MENU_KEY=0x0011 CONFIG_EDK2_SETUP_MENU_KEY=0x000C diff --git a/configs/config.intel_minnowmax_sb b/configs/config.intel_minnowmax_sb new file mode 100644 index 00000000000..72cfe440f56 --- /dev/null +++ b/configs/config.intel_minnowmax_sb @@ -0,0 +1,59 @@ +CONFIG_LOCALVERSION="0.9.0-rc1" +CONFIG_VENDOR_INTEL=y +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +# CONFIG_VGA_BIOS is not set +CONFIG_PXE_ROM_ID="8086,1539" +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/txe_sb.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_EDK2_BOOT_TIMEOUT=3 +CONFIG_BOARD_INTEL_MINNOWMAX=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/dasharo/bootsplash.bmp" +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/mrc.elf" +CONFIG_MRC_RMT=y +CONFIG_TXE_SECURE_BOOT=y +CONFIG_TXE_SB_INCLUDE_KEY_MANIFEST=y +CONFIG_TXE_SB_GENERATE_KEY_MANIFEST=y +CONFIG_TXE_SB_KEY_MANIFEST_KEY_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/oem_key_priv_sample.pem" +CONFIG_TXE_SB_SBM_MANIFEST_KEY_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/sb_key_priv_sample.pem" +CONFIG_HAVE_ME_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_CBFS_VERIFICATION=y +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_SMM_BWP=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2" +CONFIG_EDK2_TAG_OR_REV="f6f62e8efe2fd35d2f28c906e8e72a8b7f12b28c" +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="3323ed481d35096fb6a7eae7b49f35eff00f86cf" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +# CONFIG_EDK2_PS2_SUPPORT is not set +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_EDK2_GOP_FILE="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/IntelGopDriver.efi" +CONFIG_EDK2_DISABLE_TPM=y +CONFIG_BUILD_IPXE=y +# CONFIG_IPXE_SERIAL_CONSOLE is not set +CONFIG_IPXE_NO_PROMPT=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0011 +CONFIG_EDK2_SETUP_MENU_KEY=0x000C +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y From 8c08e1f678c57b5db34508fff19c3c74632861a8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 25 Jul 2024 16:20:45 +0200 Subject: [PATCH 24/56] arch/x86/smbios.c: Strip leading spaces from CPU brand string MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Intel Bay Trail SoCs (confirmed on Atom E3845) have leading spaces in the CPU brand string returned by CPUID. Strip these spaces so that SMBIOS CPU string does not look weird in the EDK2 setup page and the dmidecode output. Signed-off-by: Michał Żygowski --- src/arch/x86/smbios.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 2cf529e931e..6c0151f4d46 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -39,6 +39,8 @@ static int smbios_processor_name(u8 *start) } tmp[12] = 0; str = (const char *)tmp; + /* Skip leading spaces. */ + while (*str == ' ') str++; } } return smbios_add_string(start, str); From 60acd6e4b5a2d9eabaec824dd5cb20a81aabb326 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Fri, 26 Jul 2024 12:06:30 +0200 Subject: [PATCH 25/56] payloads/external/iPXE/Makefile: Use newer iPXE base revision MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- payloads/external/iPXE/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/external/iPXE/Makefile b/payloads/external/iPXE/Makefile index 8c908143d47..80aba7ce7d0 100644 --- a/payloads/external/iPXE/Makefile +++ b/payloads/external/iPXE/Makefile @@ -4,7 +4,7 @@ # When updating, change the name both here and in payloads/external/iPXE/Kconfig # Temporarily Dasharo fork is used until i225/i226 native support is merged. -STABLE_COMMIT_ID=35d84756c8fc55b55922a24a8cd9e7ea27f92edb +STABLE_COMMIT_ID=de0e1cf11bf9f29fde4e6da77f1199091f6b90fa TAG-$(CONFIG_IPXE_MASTER)=origin/master TAG-$(CONFIG_IPXE_STABLE)=$(STABLE_COMMIT_ID) From 941d6a689889970b5aabd02d730039c10ab039f3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 6 Aug 2024 12:00:11 +0200 Subject: [PATCH 26/56] build.sh: Add options to build Intel MinnowMax MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- build.sh | 43 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/build.sh b/build.sh index ce7191d4e43..85d80a2162b 100755 --- a/build.sh +++ b/build.sh @@ -23,6 +23,8 @@ usage() { echo -e "\toptiplex_9010 - build Dasharo compatible with Dell OptiPlex 7010/9010" echo -e "\tqemu - build Dasharo for QEMU Q35" echo -e "\tqemu_full - build Dasharo for QEMU Q35 with all menus available" + echo -e "\tminnow_no_sb - build Dasharo compatbile with Intel MinnowMax without TXE Secure Boot" + echo -e "\tminnow_sb - build Dasharo compatbile with Intel MinnowMax with TXE Secure Boot" } SDKVER="2023-11-24_2731fa619b" @@ -220,6 +222,41 @@ function build_qemu { fi } +function build_minnowboard { + DEFCONFIG="configs/config.intel_minnowmax_$1" + FW_VERSION=$(cat ${DEFCONFIG} | grep CONFIG_LOCALVERSION | cut -d '=' -f 2 | tr -d '"') + SDKVER=v1.5.0 + + # checkout several submodules needed by these boards (some others are checked + # out by coreboot's Makefile) + git submodule update --init --force --checkout \ + 3rdparty/dasharo-blobs + + docker run --rm -t -e USER_ID=$(id -u) -e GROUP=$(id -g) -e GROUP_ID=$(id -g) \ + -v $PWD:/home/coreboot/coreboot -v $HOME/.ssh:/home/coreboot/.ssh \ + -v $HOME/.ssh:/home/coreboot/.ssh \ + -w /home/coreboot/coreboot ghcr.io/dasharo/dasharo-sdk:$SDKVER \ + /bin/bash -c "make distclean" + + cp $DEFCONFIG .config + + echo "Building Dasharo compatbile with Intel Minnowmax (version $FW_VERSION)" + + docker run --rm -t -e USER_ID=$(id -u) -e GROUP=$(id -g) -e GROUP_ID=$(id -g) \ + -v $PWD:/home/coreboot/coreboot -v $HOME/.ssh:/home/coreboot/.ssh \ + -w /home/coreboot/coreboot ghcr.io/dasharo/dasharo-sdk:$SDKVER \ + /bin/bash -c "make olddefconfig && make -j$(nproc)" + + cp build/coreboot.rom intel_minnowmax_${FW_VERSION}_$1.rom + if [ $? -eq 0 ]; then + echo "Result binary placed in $PWD/intel_minnowmax_${FW_VERSION}_$1.rom" + sha256sum intel_minnowmax_${FW_VERSION}_$1.rom > intel_minnowmax_${FW_VERSION}_$1.rom.sha256 + else + echo "Build failed!" + exit 1 + fi +} + CMD="$1" case "$CMD" in @@ -289,6 +326,12 @@ case "$CMD" in "qemu_full" | "QEMU_full" | "q35_full" | "Q35_full" ) build_qemu "_all_menus" ;; + "minnow_no_sb" ) + build_minnowboard "no_sb" + ;; + "minnow_sb" ) + build_minnowboard "sb" + ;; *) echo "Invalid command: \"$CMD\"" usage From 6e0a831727c99a243df406f99d8fe85324737be0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Filip=20Lewi=C5=84ski?= Date: Mon, 19 Aug 2024 17:51:28 +0200 Subject: [PATCH 27/56] src/device/pciexp_device.c: switch ASPM disabling order MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Filip Lewiński --- src/device/pciexp_device.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index 08a0d3c21cd..5c1ffe07d07 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -587,15 +587,15 @@ static void pciexp_enable_aspm(struct device *root, unsigned int root_cap, lnkctl |= apmc; pci_write_config16(endp, endp_cap + PCI_EXP_LNKCTL, lnkctl); } else { - /* Disable ASPM in root port first */ - lnkctl = pci_read_config16(root, root_cap + PCI_EXP_LNKCTL); - lnkctl &= ~3; - pci_write_config16(root, root_cap + PCI_EXP_LNKCTL, lnkctl); - - /* Disable ASPM in endpoint device next */ + /* Disable ASPM in endpoint device first */ lnkctl = pci_read_config16(endp, endp_cap + PCI_EXP_LNKCTL); lnkctl &= ~3; pci_write_config16(endp, endp_cap + PCI_EXP_LNKCTL, lnkctl); + + /* Disable ASPM in root port next */ + lnkctl = pci_read_config16(root, root_cap + PCI_EXP_LNKCTL); + lnkctl &= ~3; + pci_write_config16(root, root_cap + PCI_EXP_LNKCTL, lnkctl); } if (CONFIG(PCIEXP_ASPM)) From faaa8e024051866fc760f7962e1421d2bf224196 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Filip=20Lewi=C5=84ski?= Date: Mon, 19 Aug 2024 18:15:16 +0200 Subject: [PATCH 28/56] src/soc/intel/baytrail/pcie.c: set power and slot number regardless of hotplug MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Filip Lewiński --- src/soc/intel/baytrail/pcie.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c index 94d7abee32b..d4d501f6b4d 100644 --- a/src/soc/intel/baytrail/pcie.c +++ b/src/soc/intel/baytrail/pcie.c @@ -79,11 +79,13 @@ static void byt_pcie_init(struct device *dev) REG_PCI_RMW32(LCAP, ~L1EXIT_MASK, 2 << (L1EXIT_SHIFT + pll_en_off)), REG_SCRIPT_NEXT(init_static_after_exit_latency), -#if !CONFIG(PCIEXP_HOTPLUG) - /* Disable hot plug, set power to 10W, set slot number. */ - REG_PCI_RMW32(SLCAP, ~(HPC | HPS), + /* Set power to 10W, set slot number. */ + REG_PCI_RMW32(SLCAP, 0xffffffff, (1 << SLS_SHIFT) | (100 << SLV_SHIFT) | (root_port_offset(dev) << SLN_SHIFT)), +#if !CONFIG(PCIEXP_HOTPLUG) + /* Disable hot plug */ + REG_PCI_RMW32(SLCAP, ~(HPC | HPS), 0), #endif /* Dynamic clock gating. */ REG_PCI_OR32(RPPGEN, RPDLCGEN | RPDBCGEN | RPSCGEN), From 1f3e0206e16e30373d7e1de43a597748b1e62e73 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Filip=20Lewi=C5=84ski?= Date: Mon, 19 Aug 2024 18:27:02 +0200 Subject: [PATCH 29/56] src/soc/intel/baytrail/pcie.c: update hotplug function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Filip Lewiński --- src/soc/intel/baytrail/pcie.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c index d4d501f6b4d..2fcfd4c7535 100644 --- a/src/soc/intel/baytrail/pcie.c +++ b/src/soc/intel/baytrail/pcie.c @@ -177,11 +177,8 @@ static void check_device_present(struct device *dev) { struct reg_script hotplug_port[] = { REG_PCI_RMW32(PCIEALC, ~(1 << 26), 0), - /* Configure hot plug, set power to 10W, set slot number. */ - REG_PCI_RMW32(SLCAP, ~(HPC | HPS), - (1 << SLS_SHIFT) | (100 << SLV_SHIFT) | - (root_port_offset(dev) << SLN_SHIFT) | - (HPC | HPS)), + /* Configure hot plug */ + REG_PCI_OR32(SLCAP, ~(HPC | HPS)), REG_PCI_RMW32(SLCTL_SLSTS, ~HPE, 0), REG_PCI_OR32(SLCTL_SLSTS, (ABE | PDE)), REG_PCI_OR32(UEM, CT), From 830eb1e774e17c9f854d6db4c527a83aacaa3a56 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Wed, 18 Sep 2024 15:32:03 +0200 Subject: [PATCH 30/56] src/mainboard/intel/minnowmax/devicetree.cb: Enable HD Audio MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- src/mainboard/intel/minnowmax/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/intel/minnowmax/devicetree.cb b/src/mainboard/intel/minnowmax/devicetree.cb index 2e5ca78fd75..448cb76ae65 100644 --- a/src/mainboard/intel/minnowmax/devicetree.cb +++ b/src/mainboard/intel/minnowmax/devicetree.cb @@ -64,7 +64,7 @@ chip soc/intel/baytrail device pci 18.6 on end # 8086 0F46 - I2C Port 6 (5) LSEC device pci 18.7 on end # 8086 0F47 - I2C Port 7 (6) HSEC device pci 1a.0 on end # 8086 0F18 - TXE - device pci 1b.0 off end # 8086 0F04 - HD Audio + device pci 1b.0 on end # 8086 0F04 - HD Audio device pci 1c.0 on end # 8086 0F48 - PCIe Port 1 (0) Must remain on device pci 1c.1 on end # 8086 0F4A - PCIe Port 2 (1) Onboard GBE (some models) device pci 1c.2 on end # 8086 0F4C - PCIe Port 3 (2) Onboard GBE From ffca799536c4c9cb8dfd04c0173672341e1f0bf5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Wed, 18 Sep 2024 16:21:51 +0200 Subject: [PATCH 31/56] src/soc/intel/baytrail: Publish device NVS to avoid ACPI errors MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- src/soc/intel/baytrail/emmc.c | 18 ++++++++++++++++++ src/soc/intel/baytrail/lpe.c | 12 ++++++++++++ src/soc/intel/baytrail/lpss.c | 17 +++++++++++++++++ src/soc/intel/baytrail/sd.c | 18 ++++++++++++++++++ 4 files changed, 65 insertions(+) diff --git a/src/soc/intel/baytrail/emmc.c b/src/soc/intel/baytrail/emmc.c index 3bfad01f4b2..20c9c701b2e 100644 --- a/src/soc/intel/baytrail/emmc.c +++ b/src/soc/intel/baytrail/emmc.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -30,6 +31,21 @@ static const struct reg_script emmc_ops[] = { REG_SCRIPT_END, }; +static void acpi_store_nvs(struct device *dev, int nvs_index) +{ + struct resource *bar; + struct device_nvs *dev_nvs = acpi_get_device_nvs(); + + /* Save BAR0 and BAR1 to ACPI NVS */ + bar = probe_resource(dev, PCI_BASE_ADDRESS_0); + if (bar) + dev_nvs->scc_bar0[nvs_index] = (u32)bar->base; + + bar = probe_resource(dev, PCI_BASE_ADDRESS_1); + if (bar) + dev_nvs->scc_bar1[nvs_index] = (u32)bar->base; +} + static void emmc_init(struct device *dev) { struct soc_intel_baytrail_config *config = config_of(dev); @@ -39,6 +55,8 @@ static void emmc_init(struct device *dev) if (config->scc_acpi_mode) scc_enable_acpi_mode(dev, SCC_MMC_CTL, SCC_NVS_MMC); + else + acpi_store_nvs(dev, SCC_NVS_MMC); } static struct device_operations device_ops = { diff --git a/src/soc/intel/baytrail/lpe.c b/src/soc/intel/baytrail/lpe.c index 71a1e1f99ec..55439951483 100644 --- a/src/soc/intel/baytrail/lpe.c +++ b/src/soc/intel/baytrail/lpe.c @@ -39,6 +39,16 @@ static void assign_device_nvs(struct device *dev, u32 *field, unsigned int index *field = res->base; } +static void store_acpi_nvs(struct device *dev) +{ + struct device_nvs *dev_nvs = acpi_get_device_nvs(); + + /* Save BAR0, BAR1, and firmware base to ACPI NVS */ + assign_device_nvs(dev, &dev_nvs->lpe_bar0, PCI_BASE_ADDRESS_0); + assign_device_nvs(dev, &dev_nvs->lpe_bar1, PCI_BASE_ADDRESS_1); + assign_device_nvs(dev, &dev_nvs->lpe_fw, FIRMWARE_PCI_REG_BASE); +} + static void lpe_enable_acpi_mode(struct device *dev) { static const struct reg_script ops[] = { @@ -141,6 +151,8 @@ static void lpe_init(struct device *dev) if (config->lpe_acpi_mode) lpe_enable_acpi_mode(dev); + else + store_acpi_nvs(dev); } static void lpe_read_resources(struct device *dev) diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c index f65b726253d..197481ba0f2 100644 --- a/src/soc/intel/baytrail/lpss.c +++ b/src/soc/intel/baytrail/lpss.c @@ -35,6 +35,21 @@ #define CASE_DEV(name_) \ case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC) +static void store_acpi_nvs(struct device *dev, int nvs_index) +{ + struct resource *bar; + struct device_nvs *dev_nvs = acpi_get_device_nvs(); + + /* Save BAR0 and BAR1 to ACPI NVS */ + bar = probe_resource(dev, PCI_BASE_ADDRESS_0); + if (bar) + dev_nvs->lpss_bar0[nvs_index] = (u32)bar->base; + + bar = probe_resource(dev, PCI_BASE_ADDRESS_1); + if (bar) + dev_nvs->lpss_bar1[nvs_index] = (u32)bar->base; +} + static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index) { struct reg_script ops[] = { @@ -367,6 +382,8 @@ static void lpss_init(struct device *dev) if (config->lpss_acpi_mode) dev_enable_acpi_mode(dev, iosf_reg, nvs_index); + else + store_acpi_nvs(dev, nvs_index); } static struct device_operations device_ops = { diff --git a/src/soc/intel/baytrail/sd.c b/src/soc/intel/baytrail/sd.c index 920a96004eb..080efc5458a 100644 --- a/src/soc/intel/baytrail/sd.c +++ b/src/soc/intel/baytrail/sd.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -16,6 +17,21 @@ #define CAP_OVERRIDE_HIGH 0xa4 #define USE_CAP_OVERRIDES (1 << 31) +static void acpi_store_nvs(struct device *dev, int nvs_index) +{ + struct resource *bar; + struct device_nvs *dev_nvs = acpi_get_device_nvs(); + + /* Save BAR0 and BAR1 to ACPI NVS */ + bar = probe_resource(dev, PCI_BASE_ADDRESS_0); + if (bar) + dev_nvs->scc_bar0[nvs_index] = (u32)bar->base; + + bar = probe_resource(dev, PCI_BASE_ADDRESS_1); + if (bar) + dev_nvs->scc_bar1[nvs_index] = (u32)bar->base; +} + static void sd_init(struct device *dev) { struct soc_intel_baytrail_config *config = config_of(dev); @@ -29,6 +45,8 @@ static void sd_init(struct device *dev) if (config->scc_acpi_mode) scc_enable_acpi_mode(dev, SCC_SD_CTL, SCC_NVS_SD); + else + acpi_store_nvs(dev, SCC_NVS_SD); } static const struct device_operations device_ops = { From 488a221bf692a3fbf019b93f223f81b6c1825488 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 24 Sep 2024 12:03:50 +0200 Subject: [PATCH 32/56] soc/intel/baytrail: Add option to disable HPET MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- src/soc/intel/baytrail/Kconfig | 10 ++++++++++ src/soc/intel/baytrail/acpi/lpc.asl | 2 ++ src/soc/intel/baytrail/southcluster.c | 2 ++ 3 files changed, 14 insertions(+) diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 9d5fd4de171..124b97c40b3 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -61,6 +61,16 @@ config SMM_RESERVED_SIZE hex default 0x100000 +config DISABLE_HPET + bool "Disable the HPET device" + default n + help + Enable this to disable the HPET support. + On BayTrail and Braswell/Cherry Trail platforms HPET halts + when CPU enters deep C states. Select this opton to prevent + the OS from using HPET as timer source, as it may lead to + soft CPU lockups. + config HAVE_MRC bool "Add a System Agent binary" help diff --git a/src/soc/intel/baytrail/acpi/lpc.asl b/src/soc/intel/baytrail/acpi/lpc.asl index e41fcc09601..3937cf13c48 100644 --- a/src/soc/intel/baytrail/acpi/lpc.asl +++ b/src/soc/intel/baytrail/acpi/lpc.asl @@ -34,6 +34,7 @@ Device (LPCB) }) } +#if !CONFIG(DISABLE_HPET) Device (HPET) { Name (_HID, EISAID("PNP0103")) @@ -49,6 +50,7 @@ Device (LPCB) Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x400) }) } +#endif Device(PIC) /* 8259 Interrupt Controller */ { diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 6a352da2757..bee6b1e609e 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -747,7 +747,9 @@ static struct device_operations device_ops = { .read_resources = sc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, +#if !CONFIG(DISABLE_HPET) .write_acpi_tables = acpi_write_hpet, +#endif .init = sc_init, .enable = southcluster_enable_dev, .scan_bus = scan_static_bus, From 1feec7c573cf7fcdce29b5b2eadd3f86359766d9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Wed, 18 Sep 2024 16:22:21 +0200 Subject: [PATCH 33/56] src/soc/intel/baytrail/cpu.c: Sync MTRRs in later boot phase MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Linux complained on inconsistent MTRRs. Apparently they were not set for APs correctly. Signed-off-by: Michał Żygowski --- src/soc/intel/baytrail/Kconfig | 1 + src/soc/intel/baytrail/cpu.c | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 124b97c40b3..cb11de1a24e 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -33,6 +33,7 @@ config SOC_INTEL_BAYTRAIL select USE_DDR3 select UDK_2017_BINDING select HAVE_CF9_RESET_PREPARE + select PARALLEL_MP_AP_WORK help Bay Trail M/D part support. diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index 81c0212aab9..3e83bcc0883 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -225,3 +226,21 @@ void mp_init_cpus(struct bus *cpu_bus) /* TODO: Handle mp_init_with_smm failure? */ mp_init_with_smm(cpu_bus, &mp_ops); } + +static void wrapper_x86_setup_mtrrs(void *unused) +{ + x86_setup_mtrrs_with_detect(); +} + +/* Ensure to re-program all MTRRs based on DRAM resource settings */ +static void post_cpus_init(void *unused) +{ + /* Ensure all APs finish the task and continue */ + if (mp_run_on_all_cpus_synchronously(&wrapper_x86_setup_mtrrs, NULL) != CB_SUCCESS) + printk(BIOS_ERR, "MTRR programming failure\n"); + + x86_mtrr_check(); +} + +BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_EXIT, post_cpus_init, NULL); +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, post_cpus_init, NULL); From 5bb6859f1da252110a6f0be37b76831c1d88ed3c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Filip=20Lewi=C5=84ski?= Date: Wed, 28 Aug 2024 16:11:29 +0200 Subject: [PATCH 34/56] src/mainboard/intel/minnowmax/Kconfig: enable S3 suspend MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Filip Lewiński --- src/mainboard/intel/minnowmax/Kconfig | 1 + src/soc/intel/baytrail/Makefile.mk | 2 ++ 2 files changed, 3 insertions(+) diff --git a/src/mainboard/intel/minnowmax/Kconfig b/src/mainboard/intel/minnowmax/Kconfig index f9d5ca4c7fd..7c4c4e16a71 100644 --- a/src/mainboard/intel/minnowmax/Kconfig +++ b/src/mainboard/intel/minnowmax/Kconfig @@ -9,6 +9,7 @@ config BOARD_SPECIFIC_OPTIONS select ENABLE_BUILTIN_COM1 select HAVE_SPD_IN_CBFS select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME select HAVE_OPTION_TABLE select INTEL_GMA_HAVE_VBT diff --git a/src/soc/intel/baytrail/Makefile.mk b/src/soc/intel/baytrail/Makefile.mk index 2f825d3746f..b523b0e1bfc 100644 --- a/src/soc/intel/baytrail/Makefile.mk +++ b/src/soc/intel/baytrail/Makefile.mk @@ -15,6 +15,7 @@ ifeq ($(CONFIG_CBFS_VERIFICATION),y) bootblock-$(CONFIG_TXE_SECURE_BOOT) += bootblock/microcode_asm.S endif bootblock-y += bootblock/bootblock.c +bootblock-y += pmutil.c romstage-y += iosf.c romstage-y += memmap.c @@ -23,6 +24,7 @@ romstage-y += txei.c postcar-y += iosf.c postcar-y += memmap.c +postcar-y += pmutil.c ramstage-y += acpi.c ramstage-y += chip.c From 09cad1a0a20645ed0c6e3fb03da7ab79b2fd3b61 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 24 Sep 2024 16:18:38 +0200 Subject: [PATCH 35/56] soc/intel/baytrail: Add proper UART support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- src/soc/intel/baytrail/acpi/lpc.asl | 65 ++++++++++++++++++-- src/soc/intel/baytrail/bootblock/bootblock.c | 10 ++- 2 files changed, 69 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/baytrail/acpi/lpc.asl b/src/soc/intel/baytrail/acpi/lpc.asl index 3937cf13c48..69e1f27d253 100644 --- a/src/soc/intel/baytrail/acpi/lpc.asl +++ b/src/soc/intel/baytrail/acpi/lpc.asl @@ -8,6 +8,16 @@ Device (LPCB) { Name(_ADR, 0x001f0000) + OperationRegion(LPC0, PCI_Config, 0x00, 0xC0) + Field(LPC0, AnyAcc, NoLock, Preserve) + { + Offset(0x08), + SRID, 8, // Revision ID + Offset(0x080), + C1EN, 1, // COM1 Enable + , 31 + } + #include "irqlinks.asl" #include "acpi/ec.asl" @@ -126,14 +136,61 @@ Device (LPCB) Name (_UID, 1) Method (_STA, 0, NotSerialized) { - Return (0x0F) + If (^^C1EN) + { + Return (0x0F) + } + Else + { + Return (0x00) + } + } + + Method(_DIS,0,Serialized) + { + ^^C1EN = 0 } - Name (_CRS, ResourceTemplate () + Method(_SRS,1,Serialized) + { + } + + + Name(BUF0,ResourceTemplate() { - IO (Decode16, 0x03F8, 0x3F8, 0x08, 0x08) - IRQNoFlags () {4} + IO (Decode16, 0x03F8, 0x03F8, 0x01, 0x08) + IRQNoFlags() {3} }) + + Name(BUF1,ResourceTemplate() + { + IO (Decode16, 0x03F8, 0x03F8, 0x01, 0x08) + IRQNoFlags() {4} + }) + + Method(_PRS,0,Serialized) + { + If (^^SRID <= 0x04) + { + Return(BUF0) + } + Else + { + Return(BUF1) + } + } + + Method(_CRS,0,Serialized) + { + If (^^SRID <= 0x04) + { + Return(BUF0) + } + Else + { + Return(BUF1) + } + } } #endif diff --git a/src/soc/intel/baytrail/bootblock/bootblock.c b/src/soc/intel/baytrail/bootblock/bootblock.c index d1bd2b9d381..4eeac8f1280 100644 --- a/src/soc/intel/baytrail/bootblock/bootblock.c +++ b/src/soc/intel/baytrail/bootblock/bootblock.c @@ -69,10 +69,16 @@ static void byt_config_com1_and_enable(void) uint32_t reg32; /* Enable COM1 for debug message output. */ - reg32 = read32((const volatile void *)(PMC_BASE_ADDRESS + GEN_PMCON1)); + reg32 = read32p(PMC_BASE_ADDRESS + GEN_PMCON1); reg32 &= ~(SUS_PWR_FLR | PWR_FLR); reg32 |= UART_EN; - write32 ((volatile void *)(PMC_BASE_ADDRESS + GEN_PMCON1), reg32); + write32p(PMC_BASE_ADDRESS + GEN_PMCON1, reg32); + + /* Enable IRQ3 or IRQ4 for the UART */ + if (pci_read_config8(PCI_DEV(0, LPC_DEV, 0), REVID) >= RID_B_STEPPING_START) + write8p(ILB_BASE_ADDRESS + 0x88, read8p(ILB_BASE_ADDRESS + 0x88) | BIT(4)); + else + write8p(ILB_BASE_ADDRESS + 0x88, read8p(ILB_BASE_ADDRESS + 0x88) | BIT(3)); /* Set up the pads to select the UART function */ ssus_enable_internal_pull(UART_RXD_PAD, PAD_PU_2K | PAD_PULL_UP); From 580ec06c2a36c9a0b87daa8b421bf03ce46f9c0b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 24 Sep 2024 16:20:07 +0200 Subject: [PATCH 36/56] soc/intel/baytrail/northcluster.c: Do not report the same region twice MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- src/soc/intel/baytrail/northcluster.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c index 5ba39215e13..5c3cc1e1891 100644 --- a/src/soc/intel/baytrail/northcluster.c +++ b/src/soc/intel/baytrail/northcluster.c @@ -84,8 +84,8 @@ static void nc_read_resources(struct device *dev) smmrrl = (iosf_bunit_read(BUNIT_SMRRL) & 0xffff) * MiB; smmrrh = ((iosf_bunit_read(BUNIT_SMRRH) & 0xffff) + 1) * MiB; - /* 0xc0000 -> smrrl - cacheable and usable */ - ram_from_to(dev, index++, 0xc0000, smmrrl); + /* 1MB -> smrrl - cacheable and usable */ + ram_from_to(dev, index++, 1 * MiB, smmrrl); if (smmrrh > smmrrl) reserved_ram_from_to(dev, index++, smmrrl, smmrrh); From 50c3a1b3c69666f0eabc1b6f3f3a2fcef78bc4a5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 24 Sep 2024 16:21:31 +0200 Subject: [PATCH 37/56] src/soc/intel/baytrail/Kconfig: Disable S1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- src/soc/intel/baytrail/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index cb11de1a24e..49b76c30bca 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -34,6 +34,7 @@ config SOC_INTEL_BAYTRAIL select UDK_2017_BINDING select HAVE_CF9_RESET_PREPARE select PARALLEL_MP_AP_WORK + select ACPI_S1_NOT_SUPPORTED help Bay Trail M/D part support. From 610901859773a08d50773238235c0b8c6d44dbfc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 24 Sep 2024 17:06:33 +0200 Subject: [PATCH 38/56] configs/config.intel_minnowmax_no_sb: Disable SMM BWP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- configs/config.intel_minnowmax_no_sb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/config.intel_minnowmax_no_sb b/configs/config.intel_minnowmax_no_sb index ebbd9abdbfe..2b7d08917c2 100644 --- a/configs/config.intel_minnowmax_no_sb +++ b/configs/config.intel_minnowmax_no_sb @@ -10,6 +10,7 @@ CONFIG_EDK2_BOOT_TIMEOUT=3 CONFIG_BOARD_INTEL_MINNOWMAX=y CONFIG_HAVE_IFD_BIN=y CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/dasharo/bootsplash.bmp" +CONFIG_DISABLE_HPET=y CONFIG_HAVE_MRC=y CONFIG_MRC_FILE="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/mrc.elf" CONFIG_MRC_RMT=y @@ -20,7 +21,6 @@ CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y CONFIG_DRIVERS_GENERIC_CBFS_UUID=y CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y -CONFIG_BOOTMEDIA_SMM_BWP=y CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y CONFIG_PAYLOAD_EDK2=y CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2" From 5b87f853145d0e78519ab0f39fcda2b60c32ac7c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 26 Sep 2024 13:53:12 +0200 Subject: [PATCH 39/56] acpi: Add support for CSRT table MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- src/acpi/acpi.c | 92 +++++++++++++++++++++++++++++++++++++++++ src/include/acpi/acpi.h | 87 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 179 insertions(+) diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index fdbc3129dd0..31d36474841 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -1255,6 +1256,95 @@ static void acpi_create_wdat(acpi_header_t *header, void *unused) header->length = current - (unsigned long)wdat; } +void acpi_create_csrt(acpi_csrt_t *csrt, + unsigned long (*acpi_fill_csrt)(acpi_csrt_t *csrt_struct, + unsigned long current)) +{ + acpi_header_t *header = &(csrt->header); + unsigned long current = (unsigned long)csrt + sizeof(acpi_csrt_t); + + memset((void *)csrt, 0, sizeof(struct acpi_crat_header)); + + if (acpi_fill_header(header, "CSRT", CSRT, sizeof(acpi_csrt_t)) != CB_SUCCESS) + return; + + current = acpi_fill_csrt(csrt, current); + + /* (Re)calculate length and checksum. */ + header->length = current - (unsigned long)csrt; + header->checksum = acpi_checksum((void *)csrt, header->length); +} + +void acpi_write_csrt_group_hdr(unsigned long *current, const char vendor_id[4], + const char subvendor_id[4], u16 device_id, + u16 subdevice_id, u16 revision) +{ + struct acpi_csrt_group *group = (struct acpi_csrt_group *)*current; + + memcpy(&group->vendor_id, vendor_id, 4); + memcpy(&group->subvendor_id, subvendor_id, 4); + group->device_id = device_id; + group->subdevice_id = subdevice_id; + group->revision = revision; + group->reserved = 0; + group->shared_info_length = 0; + group->length = sizeof(*group); + + *current += sizeof(*group); +} + +void acpi_write_csrt_shared_info(unsigned long *current, struct acpi_csrt_group *group, + struct device *dev, unsigned int bar, + u16 major_version, u16 minor_version, + u32 gsi_interrupt, u8 interrupt_polarity, + u8 interrupt_mode, u8 num_channels, + u8 dma_address_width, u16 base_request_line, + u16 num_handshake_signals, u32 max_block_size) + +{ + struct acpi_csrt_shared_info *info = (struct acpi_csrt_shared_info *)*current; + struct resource *res = find_resource(dev, bar); + + if (res) { + info->mmio_base_low = res->base; + info->mmio_base_high = res->base >> 32; + } else { + info->mmio_base_low = 0; + info->mmio_base_high = 0; + } + + info->major_version = major_version; + info->minor_version = minor_version; + info->gsi_interrupt = gsi_interrupt; + info->interrupt_polarity = interrupt_polarity; + info->interrupt_mode = interrupt_mode; + info->num_channels = num_channels; + info->dma_address_width = dma_address_width; + info->base_request_line = base_request_line; + info->num_handshake_signals = num_handshake_signals; + info->max_block_size = max_block_size; + + group->shared_info_length = sizeof(*info); + group->length += sizeof(*info); + + *current += sizeof(*info); +} + +void acpi_write_csrt_descriptor(unsigned long *current, struct acpi_csrt_group *group, + u16 type, u16 subtype, const char uid[4]) +{ + struct acpi_csrt_descriptor *desc = (struct acpi_csrt_descriptor *)*current; + + desc->length = sizeof(*desc); + desc->type = type; + desc->subtype = subtype; + memcpy(&desc->uid, uid, 4); + + group->length += sizeof(*desc); + + *current += sizeof(*desc); +} + unsigned long acpi_create_lpi_desc_ncst(acpi_lpi_desc_ncst_t *lpi_desc, uint16_t uid) { memset(lpi_desc, 0, sizeof(acpi_lpi_desc_ncst_t)); @@ -1811,6 +1901,8 @@ int get_acpi_table_revision(enum acpi_tables table) return 1; case CRAT: return 1; + case CSRT: + return 0; case LPIT: /* ACPI 5.1 up to 6.3: 0 */ return 0; case SPCR: diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index c39683ed4ec..38ac18a13dc 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -106,6 +106,7 @@ enum acpi_tables { XSDT, /* Extended System Description Table */ /* Additional proprietary tables used by coreboot */ CRAT, /* Component Resource Attribute Table */ + CSRT, /* Core System Resources Table */ IORT, /* Input Output Remapping Table */ NHLT, /* Non HD audio Link Table */ SPMI, /* Server Platform Management Interface table */ @@ -1722,6 +1723,73 @@ typedef struct acpi_table_wdat { u32 entries; } __packed acpi_wdat_t; +/* ACPI CSRT */ + +/* Resource Group subtable */ +struct acpi_csrt_group { + u32 length; + u32 vendor_id; + u32 subvendor_id; + u16 device_id; + u16 subdevice_id; + u16 revision; + u16 reserved; + u32 shared_info_length; +} __packed; + +/* Shared Info subtable */ +struct acpi_csrt_shared_info { + u16 major_version; + u16 minor_version; + u32 mmio_base_low; + u32 mmio_base_high; + u32 gsi_interrupt; + u8 interrupt_polarity; + u8 interrupt_mode; + u8 num_channels; + u8 dma_address_width; + u16 base_request_line; + u16 num_handshake_signals; + u32 max_block_size; +} __packed; + +/* Interrupt mode */ + +#define ACPI_LEVEL_SENSITIVE (u8) 0x00 +#define ACPI_EDGE_SENSITIVE (u8) 0x01 + +/* Interrupt Polarity */ + +#define ACPI_ACTIVE_HIGH (u8) 0x00 +#define ACPI_ACTIVE_LOW (u8) 0x01 +#define ACPI_ACTIVE_BOTH (u8) 0x02 + +/* Resource Descriptor subtable */ +struct acpi_csrt_descriptor { + u32 length; + u16 type; + u16 subtype; + u32 uid; +} __packed; + +/* Resource Types and Subtypes */ +#define ACPI_CSRT_TYPE_INTERRUPT 0x0001 +#define ACPI_CSRT_INTERRUPT_LINE 0x0000 +#define ACPI_CSRT_INTERRUPT_CONTROLLER 0x0001 +#define ACPI_CSRT_TYPE_TIMER 0x0002 +#define ACPI_CSRT_TIMER 0x0000 +#define ACPI_CSRT_TYPE_DMA 0x0003 +#define ACPI_CSRT_DMA_CHANNEL 0x0000 +#define ACPI_CSRT_DMA_CONTROLLER 0x0001 + +typedef struct acpi_table_csrt { + acpi_header_t header; /* Common ACPI table header */ + /* struct acpi_csrt_group group_hdr; */ + /* struct acpi_csrt_shared_info shared_info; */ + /* struct acpi_csrt_descriptor descriptors[0]; */ +} __packed acpi_csrt_t; + + uintptr_t get_coreboot_rsdp(void); void acpi_create_einj(acpi_einj_t *einj, uintptr_t addr, u8 actions); @@ -1913,6 +1981,25 @@ unsigned long acpi_gtdt_add_watchdog(unsigned long current, uint64_t refresh_fra */ unsigned long acpi_soc_fill_wdat(acpi_wdat_t *wdat, unsigned long current); +void acpi_create_csrt(acpi_csrt_t *csrt, + unsigned long (*acpi_fill_csrt)(acpi_csrt_t *csrt_struct, + unsigned long current)); + +void acpi_write_csrt_group_hdr(unsigned long *current, const char vendor_id[4], + const char subvendor_id[4], u16 device_id, + u16 subdevice_id, u16 revision); + +void acpi_write_csrt_shared_info(unsigned long *current, struct acpi_csrt_group *group, + struct device *dev, unsigned int bar, + u16 major_version, u16 minor_version, + u32 gsi_interrupt, u8 interrupt_polarity, + u8 interrupt_mode, u8 num_channels, + u8 dma_address_width, u16 base_request_line, + u16 num_handshake_signals, u32 max_block_size); + +void acpi_write_csrt_descriptor(unsigned long *current, struct acpi_csrt_group *group, + u16 type, u16 subtype, const char uid[4]); + /* For ACPI S3 support. */ void __noreturn acpi_resume(void *wake_vec); void mainboard_suspend_resume(void); From 9b3f173c327428bb5f82f4d7d842d32f916a3372 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 26 Sep 2024 13:56:18 +0200 Subject: [PATCH 40/56] soc/intel/baytrail/lpss: Publish CSRT table for LPSS devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- src/soc/intel/baytrail/include/soc/irq.h | 5 ++ src/soc/intel/baytrail/lpss.c | 84 ++++++++++++++++++++++-- 2 files changed, 84 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/baytrail/include/soc/irq.h b/src/soc/intel/baytrail/include/soc/irq.h index e13cae82a46..747b77b5f68 100644 --- a/src/soc/intel/baytrail/include/soc/irq.h +++ b/src/soc/intel/baytrail/include/soc/irq.h @@ -3,6 +3,11 @@ #ifndef _BAYTRAIL_IRQ_H_ #define _BAYTRAIL_IRQ_H_ +#define INTA 1 +#define INTB 2 +#define INTC 3 +#define INTD 4 + #define PIRQA_APIC_IRQ 16 #define PIRQB_APIC_IRQ 17 #define PIRQC_APIC_IRQ 18 diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c index 197481ba0f2..8ed339a0f66 100644 --- a/src/soc/intel/baytrail/lpss.c +++ b/src/soc/intel/baytrail/lpss.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include @@ -32,6 +33,17 @@ /* Setting for SPI 50Mhz M/N = 0.5 (0x1/0x2) x 100 Mhz */ #define SPI_CLOCK_50_MHZ ((0x2 << 16) | (0x1 << 1)) +/* CSRT constants */ +#define DMA1_GROUP_REVISION 2 +#define DMA2_GROUP_REVISION 3 +#define DMA1_NUM_CHANNELS 6 +#define DMA2_NUM_CHANNELS 8 +#define DMA1_BASE_REQ_LINE 0 +#define DMA2_BASE_REQ_LINE 16 +#define DMA_MAX_BLOCK_SIZE 0xfff +#define DMA_ADDRESS_WIDTH 32 +#define DMA_NUM_HANDSHAKE_SIGNALS 16 + #define CASE_DEV(name_) \ case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC) @@ -254,11 +266,6 @@ static void dev_set_pins(struct device *dev) } } -#define INTA 1 -#define INTB 2 -#define INTC 3 -#define INTD 4 - static void dev_set_int_pin(struct device *dev, int iosf_reg) { u32 val; @@ -386,12 +393,79 @@ static void lpss_init(struct device *dev) store_acpi_nvs(dev, nvs_index); } +static void lpss_write_dma_group(struct device *dma, unsigned long *current, u16 revision, + const char cntlr_uid[4], u32 gsi, u8 num_channels, + u16 base_request_line) +{ + struct acpi_csrt_group *group = (struct acpi_csrt_group *)*current; + + acpi_write_csrt_group_hdr(current, "INTL", "\0\0\0\0", + 0x9c60, 0, revision); + + acpi_write_csrt_shared_info(current, group, dma, PCI_BASE_ADDRESS_0, + 1 /* major_ver */, 0 /* minor_ver */, + gsi, ACPI_ACTIVE_BOTH, + ACPI_LEVEL_SENSITIVE, num_channels, + DMA_ADDRESS_WIDTH, base_request_line, + DMA_NUM_HANDSHAKE_SIGNALS, + DMA_MAX_BLOCK_SIZE); + + acpi_write_csrt_descriptor(current, group, ACPI_CSRT_TYPE_DMA, + ACPI_CSRT_DMA_CONTROLLER, cntlr_uid); + + char uid[4] = "CHA"; + for (unsigned int ch = 0; ch < num_channels; ch++) { + uid[3] = ch + 0x30; + acpi_write_csrt_descriptor(current, group, ACPI_CSRT_TYPE_DMA, + ACPI_CSRT_DMA_CHANNEL, uid); + } +} + +static unsigned long lpss_fill_csrt(acpi_csrt_t *csrt_struct, unsigned long current) +{ + struct device *dma1 = pcidev_on_root(SIO_DMA1_DEV, SIO_DMA1_FUNC); + struct device *dma2 = pcidev_on_root(SIO_DMA2_DEV, SIO_DMA2_FUNC); + + if (dma1 && dma1->enabled) { + lpss_write_dma_group(dma1, ¤t, DMA1_GROUP_REVISION, "SPI ", + LPSS_DMA1_IRQ, DMA1_NUM_CHANNELS, DMA1_BASE_REQ_LINE); + } + if (dma2 && dma2->enabled) { + lpss_write_dma_group(dma2, ¤t, DMA2_GROUP_REVISION, "I2C ", + LPSS_DMA2_IRQ, DMA2_NUM_CHANNELS, DMA2_BASE_REQ_LINE); + } + + return current; +} + +static unsigned long lpss_write_csrt(const struct device *device, unsigned long current, + acpi_rsdp_t *rsdp) +{ + acpi_csrt_t *csrt; + static bool csrt_written = false; + + if (csrt_written) + return current; + + printk(BIOS_DEBUG, "ACPI: * CSRT\n"); + current = ALIGN_UP(current, 16); + csrt = (acpi_csrt_t *)current; + acpi_create_csrt(csrt, lpss_fill_csrt); + acpi_add_table(rsdp, csrt); + csrt_written = true; + + current += csrt->header.length; + + return current; +} + static struct device_operations device_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = lpss_init, .ops_pci = &soc_pci_ops, + .write_acpi_tables = lpss_write_csrt, }; static const unsigned short pci_device_ids[] = { From 26dbc3f49ddfef852d0d274c527a2f8bdd4a4737 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 26 Sep 2024 13:57:37 +0200 Subject: [PATCH 41/56] soc/intel/baytrail/scc: Program PCI interrupts for SCC devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- src/soc/intel/baytrail/emmc.c | 6 +++++- src/soc/intel/baytrail/include/soc/iosf.h | 6 ++++-- src/soc/intel/baytrail/scc.c | 1 + src/soc/intel/baytrail/sd.c | 13 +++++++++++++ 4 files changed, 23 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/baytrail/emmc.c b/src/soc/intel/baytrail/emmc.c index 20c9c701b2e..869c6d87dd1 100644 --- a/src/soc/intel/baytrail/emmc.c +++ b/src/soc/intel/baytrail/emmc.c @@ -9,6 +9,7 @@ #include #include +#include #include #include #include "chip.h" @@ -28,6 +29,9 @@ static const struct reg_script emmc_ops[] = { REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c4, ~0x3c, 0x3c), /* Max timeout */ REG_RES_WRITE8(PCI_BASE_ADDRESS_0, 0x002e, 0x0e), + /* Configure INTA for PCI mode */ + REG_IOSF_RMW(IOSF_PORT_SCC, SCC_MMC45_CTL, + ~SSC_CTL_INT_PIN_MASK, (INTA << SSC_CTL_INT_PIN_SHIFT)), REG_SCRIPT_END, }; @@ -54,7 +58,7 @@ static void emmc_init(struct device *dev) reg_script_run_on_dev(dev, emmc_ops); if (config->scc_acpi_mode) - scc_enable_acpi_mode(dev, SCC_MMC_CTL, SCC_NVS_MMC); + scc_enable_acpi_mode(dev, SCC_MMC45_CTL, SCC_NVS_MMC); else acpi_store_nvs(dev, SCC_NVS_MMC); } diff --git a/src/soc/intel/baytrail/include/soc/iosf.h b/src/soc/intel/baytrail/include/soc/iosf.h index 1504835e88c..9ff637b1d7f 100644 --- a/src/soc/intel/baytrail/include/soc/iosf.h +++ b/src/soc/intel/baytrail/include/soc/iosf.h @@ -289,12 +289,14 @@ void iosf_ssus_write(int reg, uint32_t val); /* * SCC Registers */ +#define SCC_MMC_CTL 0x500 #define SCC_SD_CTL 0x504 #define SCC_SDIO_CTL 0x508 -#define SCC_MMC_CTL 0x50c +#define SCC_MMC45_CTL 0x50c # define SCC_CTL_PCI_CFG_DIS (1 << 0) # define SCC_CTL_ACPI_INT_EN (1 << 1) - +# define SSC_CTL_INT_PIN_MASK (0xf << 8) +# define SSC_CTL_INT_PIN_SHIFT 8 /* * CCU Registers */ diff --git a/src/soc/intel/baytrail/scc.c b/src/soc/intel/baytrail/scc.c index 8892b531f98..55eeb15e001 100644 --- a/src/soc/intel/baytrail/scc.c +++ b/src/soc/intel/baytrail/scc.c @@ -43,6 +43,7 @@ static const struct reg_script scc_after_dll[] = { * iosf2ocp_private.GENREGRW1.cr_clock_enable_clk_ocp = 01 * iosf2ocp_private.GENREGRW1.cr_clock_enable_clk_xin = 01 */ + REG_IOSF_RMW(IOSF_PORT_SCC, 0x600, ~0x380, 0x0), REG_IOSF_RMW(IOSF_PORT_SCC, 0x600, ~0xf, 0x5), /* Enable IOSF Snoop */ REG_IOSF_OR(IOSF_PORT_SCC, 0x00, (1 << 7)), diff --git a/src/soc/intel/baytrail/sd.c b/src/soc/intel/baytrail/sd.c index 080efc5458a..f10d7bf7b75 100644 --- a/src/soc/intel/baytrail/sd.c +++ b/src/soc/intel/baytrail/sd.c @@ -6,9 +6,11 @@ #include #include #include +#include #include #include +#include #include #include #include "chip.h" @@ -36,6 +38,15 @@ static void sd_init(struct device *dev) { struct soc_intel_baytrail_config *config = config_of(dev); + static const struct reg_script init_sd[] = { + /* Configure Maximum Timeout */ + REG_RES_WRITE8(PCI_BASE_ADDRESS_0, 0x2e, 0xe), + /* Configure INTA for PCI mode */ + REG_IOSF_RMW(IOSF_PORT_SCC, SCC_SD_CTL, + ~SSC_CTL_INT_PIN_MASK, (INTA << SSC_CTL_INT_PIN_SHIFT)), + REG_SCRIPT_END, + }; + if (config->sdcard_cap_low != 0 || config->sdcard_cap_high != 0) { printk(BIOS_DEBUG, "Overriding SD Card controller caps.\n"); pci_write_config32(dev, CAP_OVERRIDE_LOW, config->sdcard_cap_low); @@ -43,6 +54,8 @@ static void sd_init(struct device *dev) USE_CAP_OVERRIDES); } + reg_script_run_on_dev(dev, init_sd); + if (config->scc_acpi_mode) scc_enable_acpi_mode(dev, SCC_SD_CTL, SCC_NVS_SD); else From 2a95b19f0121888507a2e7d2f94aae884d7eeff0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 26 Sep 2024 13:57:56 +0200 Subject: [PATCH 42/56] src/mainboard/intel/minnowmax/irqroute.h: Add missing OTG IRQ MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- src/mainboard/intel/minnowmax/irqroute.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/intel/minnowmax/irqroute.h b/src/mainboard/intel/minnowmax/irqroute.h index 9739f6f620c..7665cb19a01 100644 --- a/src/mainboard/intel/minnowmax/irqroute.h +++ b/src/mainboard/intel/minnowmax/irqroute.h @@ -12,6 +12,7 @@ *IR13h SATA INT(A) - PIRQ D *IR14h XHCI INT(A) - PIRQ E *IR15h LP Audio INT(A) - PIRQ F + *IR15h OTG INT(A) - PIRQ G *IR17h MMC INT(A) - PIRQ F *IR18h SIO INT(ABCD) - PIRQ BADC *IR1Ah TXE INT(A) - PIRQ F @@ -31,6 +32,7 @@ PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \ PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \ PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(OTG_DEV, G, A, A, A), \ PCI_DEV_PIRQ_ROUTE(MMC45_DEV, F, A, A, A), \ PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \ PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \ From b925d032f75abe1541217931d6df1675830eb7ad Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 26 Sep 2024 13:58:49 +0200 Subject: [PATCH 43/56] src/mainboard/intel/minnowmax/gpio.c: Match Intel reference FW settings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- src/mainboard/intel/minnowmax/gpio.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mainboard/intel/minnowmax/gpio.c b/src/mainboard/intel/minnowmax/gpio.c index 15c114129c8..1e97cc0a71d 100644 --- a/src/mainboard/intel/minnowmax/gpio.c +++ b/src/mainboard/intel/minnowmax/gpio.c @@ -23,9 +23,9 @@ static const struct soc_gpio_map gpncore_gpio_map[] = { GPIO_NC, // GPIO_S0_NC[03] - No Connect GPIO_NC, // GPIO_S0_NC[04] - No Connect GPIO_NC, // GPIO_S0_NC[05] - No Connect - GPIO_NC, // GPIO_S0_NC[06] - No Connect + GPIO_FUNC2, // GPIO_S0_NC[06] - DDI1_HPD GPIO_FUNC2, // GPIO_S0_NC[07] - DDI1_DDCDAT - GPIO_NC, // GPIO_S0_NC[08] - No Connect + GPIO_FUNC2, // GPIO_S0_NC[08] - DDI1_DDCCLK GPIO_NC, // GPIO_S0_NC[09] - No Connect GPIO_NC, // GPIO_S0_NC[10] - No Connect GPIO_NC, // GPIO_S0_NC[11] - No Connect @@ -103,7 +103,7 @@ static const struct soc_gpio_map gpscore_gpio_map[] = { GPIO_FUNC1, // GPIO_S0_SC[051] - PCU_SMB_DATA GPIO_FUNC1, // GPIO_S0_SC[052] - PCU_SMB_CLK GPIO_FUNC1, // GPIO_S0_SC[053] - PCU_SMB_ALERT - GPIO_FUNC1, // GPIO_S0_SC[054] - ILB_8254_SPKR + GPIO_NC, // GPIO_S0_SC[054] - ILB_8254_SPKR GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S0_SC[055] - TP8 (GPIO_S0_SC_55) GPIO_FUNC0, // GPIO_S0_SC[056] - GPIO_S0_SC_56 GPIO_FUNC1, // GPIO_S0_SC[057] - PCU_UART3_TXD @@ -165,9 +165,9 @@ static const struct soc_gpio_map gpssus_gpio_map[] = { // Memory: 0=1GB 1=2GB or 4GB GPIO_INPUT, // GPIO_S5[06] - BOM_OP2 GPIO_INPUT, // GPIO_S5[07] - BOM_OP3 - GPIO_OUT_HIGH_LEGACY, // GPIO_S5[08] - SOC_USB_HOST_EN0 - GPIO_OUT_HIGH_LEGACY, // GPIO_S5[09] - SOC_USB_HOST_EN1 - GPIO_OUT_HIGH_LEGACY, // GPIO_S5[10] - GPIO_S5_10_UNLOCK + GPIO_OUT_LOW_LEGACY, // GPIO_S5[08] - SOC_USB_HOST_EN0 + GPIO_OUT_LOW_LEGACY, // GPIO_S5[09] - SOC_USB_HOST_EN1 + GPIO_OUT_LOW_LEGACY, // GPIO_S5[10] - GPIO_S5_10_UNLOCK GPIO_FUNC0, // GPIO_S5[11] - SUSPWRDNACK (TP14) GPIO_FUNC0, // GPIO_S5[12] - PMC_SUSCLK0 GPIO_FUNC1, // GPIO_S5[13] - PMC_SLP_S0IX (TP10) From 7bca5b31d78d01e1179ca5efdc61faa3ffc2b5d5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 26 Sep 2024 13:59:22 +0200 Subject: [PATCH 44/56] soc/intel/baytrail/southcluster.c: Use generic IOAPIC init API MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- src/soc/intel/baytrail/southcluster.c | 33 ++++----------------------- 1 file changed, 5 insertions(+), 28 deletions(-) diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index bee6b1e609e..abb3ad74f0c 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -144,10 +144,6 @@ static void com1_configure_resume(struct device *dev) static void sc_enable_ioapic(struct device *dev) { - int i; - u32 reg32; - volatile u32 *ioapic_index = (u32 *)(IO_APIC_ADDR); - volatile u32 *ioapic_data = (u32 *)(IO_APIC_ADDR + 0x10); u8 *ilb_base = (u8 *)(pci_read_config32(dev, IBASE) & ~0x0f); /* @@ -155,34 +151,15 @@ static void sc_enable_ioapic(struct device *dev) * Set SCI IRQ to IRQ9 */ write32(ilb_base + ILB_OIC, 0x100); /* AEN */ - reg32 = read32(ilb_base + ILB_OIC); /* Read back per BWG */ + read32(ilb_base + ILB_OIC); /* Read back per BWG */ write32(ilb_base + ACTL, 0); /* ACTL bit 2:0 SCIS IRQ9 */ - *ioapic_index = 0; - *ioapic_data = (1 << 25); - /* affirm full set of redirection table entries ("write once") */ - *ioapic_index = 1; - reg32 = *ioapic_data; - *ioapic_index = 1; - *ioapic_data = reg32; - - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); - if (reg32 != (1 << 25)) - die("APIC Error\n"); - - printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); - for (i=0; i<3; i++) { - *ioapic_index = i; - printk(BIOS_SPEW, " reg 0x%04x:", i); - reg32 = *ioapic_data; - printk(BIOS_SPEW, " 0x%08x\n", reg32); - } + ioapic_set_max_vectors(VIO_APIC_VADDR, 87); + setup_ioapic((void *)IO_APIC_ADDR, 2); - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ + /* Use Processor System Bus to deliver interrupts. */ + ioapic_set_boot_config((void *)IO_APIC_ADDR, true); } static void sc_enable_serial_irqs(struct device *dev) From b550c34f9e7b83e95661540573a714464ce87ee7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 26 Sep 2024 14:53:59 +0200 Subject: [PATCH 45/56] soc/intel/baytrail: Postpone setting SSC ACPI mode to APM handler MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- src/soc/intel/baytrail/emmc.c | 4 ++-- src/soc/intel/baytrail/include/soc/iosf.h | 4 ++-- src/soc/intel/baytrail/scc.c | 7 +++++-- src/soc/intel/baytrail/smihandler.c | 18 ++++++++++++++++++ 4 files changed, 27 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/baytrail/emmc.c b/src/soc/intel/baytrail/emmc.c index 869c6d87dd1..00cae1994d0 100644 --- a/src/soc/intel/baytrail/emmc.c +++ b/src/soc/intel/baytrail/emmc.c @@ -30,7 +30,7 @@ static const struct reg_script emmc_ops[] = { /* Max timeout */ REG_RES_WRITE8(PCI_BASE_ADDRESS_0, 0x002e, 0x0e), /* Configure INTA for PCI mode */ - REG_IOSF_RMW(IOSF_PORT_SCC, SCC_MMC45_CTL, + REG_IOSF_RMW(IOSF_PORT_SCC, SCC_MMC_CTL, ~SSC_CTL_INT_PIN_MASK, (INTA << SSC_CTL_INT_PIN_SHIFT)), REG_SCRIPT_END, }; @@ -58,7 +58,7 @@ static void emmc_init(struct device *dev) reg_script_run_on_dev(dev, emmc_ops); if (config->scc_acpi_mode) - scc_enable_acpi_mode(dev, SCC_MMC45_CTL, SCC_NVS_MMC); + scc_enable_acpi_mode(dev, SCC_MMC_CTL, SCC_NVS_MMC); else acpi_store_nvs(dev, SCC_NVS_MMC); } diff --git a/src/soc/intel/baytrail/include/soc/iosf.h b/src/soc/intel/baytrail/include/soc/iosf.h index 9ff637b1d7f..7938509b97d 100644 --- a/src/soc/intel/baytrail/include/soc/iosf.h +++ b/src/soc/intel/baytrail/include/soc/iosf.h @@ -289,10 +289,10 @@ void iosf_ssus_write(int reg, uint32_t val); /* * SCC Registers */ -#define SCC_MMC_CTL 0x500 +#define SCC_MMC41_CTL 0x500 #define SCC_SD_CTL 0x504 #define SCC_SDIO_CTL 0x508 -#define SCC_MMC45_CTL 0x50c +#define SCC_MMC_CTL 0x50c # define SCC_CTL_PCI_CFG_DIS (1 << 0) # define SCC_CTL_ACPI_INT_EN (1 << 1) # define SSC_CTL_INT_PIN_MASK (0xf << 8) diff --git a/src/soc/intel/baytrail/scc.c b/src/soc/intel/baytrail/scc.c index 55eeb15e001..fd1c66a6401 100644 --- a/src/soc/intel/baytrail/scc.c +++ b/src/soc/intel/baytrail/scc.c @@ -75,9 +75,12 @@ void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index) /* Disable PCI interrupt, enable Memory and Bus Master */ REG_PCI_OR16(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INT_DISABLE), - /* Enable ACPI mode */ - REG_IOSF_OR(IOSF_PORT_SCC, iosf_reg, + /* Enable ACPI mode - skip it, let APM do the switch + * so payloads can boot from SSC devices. + */ + /* REG_IOSF_OR(IOSF_PORT_SCC, iosf_reg, SCC_CTL_PCI_CFG_DIS | SCC_CTL_ACPI_INT_EN), + */ REG_SCRIPT_END }; struct resource *bar; diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index 9a478437fda..ea894076752 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -248,6 +248,23 @@ static void soc_legacy(void) LPSS_ACPI_MODE_DISABLE(SPI); } +static void ssc_acpi_mode(void) +{ + struct device_nvs *dev_nvs = acpi_get_device_nvs(); + u32 reg32; + +#define SCC_ACPI_MODE_ENABLE(name_) \ + do { if (dev_nvs->scc_en[SCC_NVS_ ## name_]) { \ + reg32 = iosf_scc_read(SCC_ ## name_ ## _CTL); \ + reg32 |= SCC_CTL_PCI_CFG_DIS | SCC_CTL_ACPI_INT_EN; \ + iosf_scc_write(SCC_ ## name_ ## _CTL, reg32); \ + } } while (0) + + SCC_ACPI_MODE_ENABLE(MMC); + SCC_ACPI_MODE_ENABLE(SD); + SCC_ACPI_MODE_ENABLE(SDIO); +} + static void southbridge_smi_store(void) { u8 sub_command, ret; @@ -277,6 +294,7 @@ static void southbridge_smi_apmc(void) disable_pm1_control(SCI_EN); break; case APM_CNT_ACPI_ENABLE: + ssc_acpi_mode(); enable_pm1_control(SCI_EN); break; case APM_CNT_ELOG_GSMI: From a2298ba57b3a08f73b97519a9983d21e4188403b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 26 Sep 2024 14:55:16 +0200 Subject: [PATCH 46/56] soc/intel/baytrail: Allow disabling SERIRQ MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- src/soc/intel/baytrail/chip.h | 2 ++ src/soc/intel/baytrail/southcluster.c | 8 ++++++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/baytrail/chip.h b/src/soc/intel/baytrail/chip.h index cf50f1addae..412762cdd08 100644 --- a/src/soc/intel/baytrail/chip.h +++ b/src/soc/intel/baytrail/chip.h @@ -57,6 +57,8 @@ struct soc_intel_baytrail_config { /* Allow PCIe devices to wake system from suspend. */ int pcie_wake_enable; + uint8_t serirq_enable; + uint8_t gpu_pipea_port_select; /* Port select: 1=DP_B 2=DP_C */ uint16_t gpu_pipea_power_on_delay; uint16_t gpu_pipea_light_on_delay; diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index abb3ad74f0c..de424836102 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -164,7 +164,7 @@ static void sc_enable_ioapic(struct device *dev) static void sc_enable_serial_irqs(struct device *dev) { -#ifdef SETUPSERIQ /* NOT defined. Remove when the TODO is done. */ + struct soc_intel_baytrail_config *config = config_of(dev); /* * TODO: SERIRQ seems to have a number of problems on baytrail. * With it enabled, we get some spurious interrupts (ps2) @@ -182,6 +182,11 @@ static void sc_enable_serial_irqs(struct device *dev) reg8 |= (1 << 3); /* IOCHK# NMI Disable for now */ outb(reg8, 0x61); + if (!config->serirq_enable) { + write32(ibase + ILB_OIC, read32(ibase + ILB_OIC) & ~SIRQEN); + return; + } + write32(ibase + ILB_OIC, read32(ibase + ILB_OIC) | SIRQEN); write8(ibase + ILB_SERIRQ_CNTL, SCNT_CONTINUOUS_MODE); @@ -194,7 +199,6 @@ static void sc_enable_serial_irqs(struct device *dev) outb(0x00, 0xED); /* I/O Delay to get the 1 frame */ write8(ibase + ILB_SERIRQ_CNTL, SCNT_QUIET_MODE); } -#endif /* DON'T SET UP IRQS */ } /* From fe3dde551d06ec4815e5276785dc420ce35f716c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 26 Sep 2024 14:56:41 +0200 Subject: [PATCH 47/56] mainboard/intel/minnowmax/devicetree.cb: Put SSC and LPSS into ACPI mode MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- src/mainboard/intel/minnowmax/devicetree.cb | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/intel/minnowmax/devicetree.cb b/src/mainboard/intel/minnowmax/devicetree.cb index 448cb76ae65..4d3d5d93229 100644 --- a/src/mainboard/intel/minnowmax/devicetree.cb +++ b/src/mainboard/intel/minnowmax/devicetree.cb @@ -36,6 +36,8 @@ chip soc/intel/baytrail # Allow PCIe devices to wake system from suspend register "pcie_wake_enable" = "1" + register "lpss_acpi_mode" = "1" + register "scc_acpi_mode" = "1" # Disable SLP_X stretching after SUS power well fail. register "disable_slp_x_stretch_sus_fail" = "1" From 9488d5fbd8fd60382f9e7f3aa7f1f69ee919b6a7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 8 Oct 2024 17:11:19 +0200 Subject: [PATCH 48/56] device/pciexp_device.c: Use disable_pcie_aspm to disable ASPM too MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- src/device/pciexp_device.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index 5c1ffe07d07..af74d608d6c 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -556,9 +556,6 @@ static void pciexp_enable_aspm(struct device *root, unsigned int root_cap, u16 lnkctl; u32 devcap; - if (endp->disable_pcie_aspm) - return; - /* Get endpoint device capabilities for acceptable limits */ devcap = pci_read_config32(endp, endp_cap + PCI_EXP_DEVCAP); @@ -576,7 +573,7 @@ static void pciexp_enable_aspm(struct device *root, unsigned int root_cap, if (exit_latency >= 0 && exit_latency <= ok_latency) apmc |= PCIE_ASPM_L1; - if (CONFIG(PCIEXP_ASPM) && apmc != PCIE_ASPM_NONE) { + if (CONFIG(PCIEXP_ASPM) && apmc != PCIE_ASPM_NONE && !endp->disable_pcie_aspm) { /* Set APMC in root port first */ lnkctl = pci_read_config16(root, root_cap + PCI_EXP_LNKCTL); lnkctl |= apmc; From 7008e4ae42529f6d1cf4cb050d1d17ac00c49828 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 8 Oct 2024 17:13:19 +0200 Subject: [PATCH 49/56] soc/intel/baytrail/Makefile.mk: Check if MANIFESTS region start is correct MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- src/soc/intel/baytrail/Makefile.mk | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/src/soc/intel/baytrail/Makefile.mk b/src/soc/intel/baytrail/Makefile.mk index b523b0e1bfc..8e7f5d04675 100644 --- a/src/soc/intel/baytrail/Makefile.mk +++ b/src/soc/intel/baytrail/Makefile.mk @@ -106,13 +106,12 @@ add_bootblock = \ ifeq ($(CONFIG_TXE_SB_INCLUDE_KEY_MANIFEST),y) ifneq ($(call strip_quotes,$(CONFIG_TXE_SB_KEY_MANIFEST_PATH)),) -key_manifest_pos = $(call int-subtract, $(CONFIG_ROM_SIZE) 0x21000) - -$(call add_intermediate, add_txe_sb_km, $(call strip_quotes,$(CONFIG_TXE_SB_KEY_MANIFEST_PATH))) - printf " DD Adding SB Key Manifest\n" \ - dd if=$(CONFIG_TXE_SB_KEY_MANIFEST_PATH) \ - of=$< conv=notrunc bs=4K \ - seek=$(key_manifest_pos) >/dev/null 2>&1 +$(call add_intermediate, add_txe_sb_km, $(obj)/fmap_config.h $(call strip_quotes,$(CONFIG_TXE_SB_KEY_MANIFEST_PATH))) + $(if $(filter 1,, $(call int-eq, $(call get_fmap_value,FMAP_SECTION_MANIFESTS_START) $(call int-subtract, $(CONFIG_ROM_SIZE) 0x21000)) \ + $(call int-eq, $(call get_fmap_value,FMAP_SECTION_MANIFESTS_START) 0xfffdf000)), , \ + $(error FMAP_SECTION_MANIFESTS_START must be at 0xfffdf000)) + printf " CBFSTOOL Adding SB Key Manifest\n" \ + $(CBFSTOOL) $(1) write -d -r MANIFESTS -f $(CONFIG_TXE_SB_KEY_MANIFEST_PATH) endif endif # CONFIG_TXE_SB_INCLUDE_KEY_MANIFEST From 432744b83a9436a85b6a56c00eeeb5b4b8d86054 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 8 Oct 2024 17:13:40 +0200 Subject: [PATCH 50/56] configs/config.intel_minnowmax_sb: Disable SMM BWP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit SMM BWP does not work properly yet. Signed-off-by: Michał Żygowski --- configs/config.intel_minnowmax_sb | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/config.intel_minnowmax_sb b/configs/config.intel_minnowmax_sb index 72cfe440f56..cebb8759062 100644 --- a/configs/config.intel_minnowmax_sb +++ b/configs/config.intel_minnowmax_sb @@ -26,7 +26,6 @@ CONFIG_DRIVERS_GENERIC_CBFS_UUID=y CONFIG_CBFS_VERIFICATION=y CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y -CONFIG_BOOTMEDIA_SMM_BWP=y CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y CONFIG_PAYLOAD_EDK2=y CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2" From 7f9cfc2454d16b0e35e8d68bda200a47467c774b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 8 Oct 2024 17:36:28 +0200 Subject: [PATCH 51/56] configs/config.intel_minnowmax: Bump to rc3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- configs/config.intel_minnowmax_no_sb | 4 ++-- configs/config.intel_minnowmax_sb | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/configs/config.intel_minnowmax_no_sb b/configs/config.intel_minnowmax_no_sb index 2b7d08917c2..31dad43d676 100644 --- a/configs/config.intel_minnowmax_no_sb +++ b/configs/config.intel_minnowmax_no_sb @@ -1,4 +1,4 @@ -CONFIG_LOCALVERSION="0.9.0-rc1" +CONFIG_LOCALVERSION="0.9.0-rc3" CONFIG_VENDOR_INTEL=y CONFIG_ONBOARD_VGA_IS_PRIMARY=y # CONFIG_VGA_BIOS is not set @@ -24,7 +24,7 @@ CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y CONFIG_PAYLOAD_EDK2=y CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2" -CONFIG_EDK2_TAG_OR_REV="f6f62e8efe2fd35d2f28c906e8e72a8b7f12b28c" +CONFIG_EDK2_TAG_OR_REV="e91a6e499eff7ff601fe65383d16811ee96fce2c" CONFIG_EDK2_USE_EDK2_PLATFORMS=y CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" CONFIG_EDK2_PLATFORMS_TAG_OR_REV="3323ed481d35096fb6a7eae7b49f35eff00f86cf" diff --git a/configs/config.intel_minnowmax_sb b/configs/config.intel_minnowmax_sb index cebb8759062..907188d374d 100644 --- a/configs/config.intel_minnowmax_sb +++ b/configs/config.intel_minnowmax_sb @@ -1,4 +1,4 @@ -CONFIG_LOCALVERSION="0.9.0-rc1" +CONFIG_LOCALVERSION="0.9.0-rc3" CONFIG_VENDOR_INTEL=y CONFIG_ONBOARD_VGA_IS_PRIMARY=y # CONFIG_VGA_BIOS is not set @@ -29,7 +29,7 @@ CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y CONFIG_PAYLOAD_EDK2=y CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2" -CONFIG_EDK2_TAG_OR_REV="f6f62e8efe2fd35d2f28c906e8e72a8b7f12b28c" +CONFIG_EDK2_TAG_OR_REV="e91a6e499eff7ff601fe65383d16811ee96fce2c" CONFIG_EDK2_USE_EDK2_PLATFORMS=y CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" CONFIG_EDK2_PLATFORMS_TAG_OR_REV="3323ed481d35096fb6a7eae7b49f35eff00f86cf" From 9e444b9c6bfe27d3be9541005a1f6130db06f8e2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 15 Oct 2024 15:33:28 +0200 Subject: [PATCH 52/56] soc/intel/baytrail/Kconfig: Fix grammar --- src/soc/intel/baytrail/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 49b76c30bca..3a00ce9e7d8 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -272,7 +272,7 @@ config TXE_SB_SBM_MANIFEST_SVN if TXE_SECURE_BOOT -# This addresses will be used by BSP to locate microcode in bootblock before +# This address will be used by BSP to locate microcode in bootblock before # setting up CAR. With CBFS verification we cannot use walkcbfs ASM routine, so # put the microcode copy in the BOOTBLOCK FMAP region right after SB manifest # for use by BSP. APs will load microcode from CBFS file in COREBOOT region when From 4a0e6c1f7e43e90fb061c1e1d924d4cc234fccce Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 17 Oct 2024 09:51:27 +0200 Subject: [PATCH 53/56] src/soc/intel/baytrail/Makefile.mk: Remove excessive comma MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- src/soc/intel/baytrail/Makefile.mk | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/baytrail/Makefile.mk b/src/soc/intel/baytrail/Makefile.mk index 8e7f5d04675..9cfa9894fcd 100644 --- a/src/soc/intel/baytrail/Makefile.mk +++ b/src/soc/intel/baytrail/Makefile.mk @@ -107,8 +107,8 @@ ifeq ($(CONFIG_TXE_SB_INCLUDE_KEY_MANIFEST),y) ifneq ($(call strip_quotes,$(CONFIG_TXE_SB_KEY_MANIFEST_PATH)),) $(call add_intermediate, add_txe_sb_km, $(obj)/fmap_config.h $(call strip_quotes,$(CONFIG_TXE_SB_KEY_MANIFEST_PATH))) - $(if $(filter 1,, $(call int-eq, $(call get_fmap_value,FMAP_SECTION_MANIFESTS_START) $(call int-subtract, $(CONFIG_ROM_SIZE) 0x21000)) \ - $(call int-eq, $(call get_fmap_value,FMAP_SECTION_MANIFESTS_START) 0xfffdf000)), , \ + $(if $(filter 1, $(call int-eq, $(call get_fmap_value,FMAP_SECTION_MANIFESTS_START) $(call int-subtract, $(CONFIG_ROM_SIZE) 0x21000)) \ + $(call int-eq, $(call get_fmap_value,FMAP_SECTION_MANIFESTS_START) 0xfffdf000)), , \ $(error FMAP_SECTION_MANIFESTS_START must be at 0xfffdf000)) printf " CBFSTOOL Adding SB Key Manifest\n" \ $(CBFSTOOL) $(1) write -d -r MANIFESTS -f $(CONFIG_TXE_SB_KEY_MANIFEST_PATH) From c23fdbee041001b49966caecd68e9cbe383895c1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 17 Oct 2024 09:54:20 +0200 Subject: [PATCH 54/56] src/soc/intel/baytrail/Kconfig: Fix typo MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- src/soc/intel/baytrail/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 3a00ce9e7d8..259e57d37f3 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -288,7 +288,7 @@ config EARLY_CPU_MICROCODE_LEN default 0x19800 # Ensure the bootblock does not overlap the microcode. We have 0x6400 bytes -# of space after microcode till the ned of ROM. Make a small gap of 256 bytes +# of space after microcode till the end of ROM. Make a small gap of 256 bytes # between the microcode and the bootblock just in case. Linker may add some # additional data in the beginning of the bootblock binary. From 2a5d4c8194814b08938b9fa0139c21ea087abe56 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 17 Oct 2024 10:11:59 +0200 Subject: [PATCH 55/56] src/soc/intel/baytrail/txei.c: Do not break printk string MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- src/soc/intel/baytrail/txei.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/soc/intel/baytrail/txei.c b/src/soc/intel/baytrail/txei.c index 874c2c0a081..755b4634b6c 100644 --- a/src/soc/intel/baytrail/txei.c +++ b/src/soc/intel/baytrail/txei.c @@ -462,8 +462,7 @@ static bool heci_can_send(void) case TXE_FWSTS0_COM_DEBUG: case TXE_FWSTS0_COM_SOFT_TEMP_DISABLE: case TXE_FWSTS0_COM_SECOVER_JMPR: - printk(BIOS_INFO, "Current TXE operation mode does not allow" - " sending HECI messages\n"); + printk(BIOS_INFO, "Current TXE operation mode does not allow sending HECI messages\n"); return false; } From 6a4524e4130d3cf460d9aa66859d1f9ff2af7aa2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 17 Oct 2024 10:59:14 +0200 Subject: [PATCH 56/56] src/soc/intel/baytrail/txei.c: Refactor slot calculation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- src/soc/intel/baytrail/txei.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/baytrail/txei.c b/src/soc/intel/baytrail/txei.c index 755b4634b6c..d55349598f9 100644 --- a/src/soc/intel/baytrail/txei.c +++ b/src/soc/intel/baytrail/txei.c @@ -401,7 +401,7 @@ static size_t hdr_get_length(uint32_t hdr) /* get number of full 4-byte slots */ static size_t bytes_to_slots(size_t bytes) { - return (bytes + (SLOT_SIZE - 1) + SLOT_SIZE) / SLOT_SIZE; + return ALIGN_UP(bytes, SLOT_SIZE) / SLOT_SIZE; } static int @@ -419,8 +419,11 @@ send_one_message(uint32_t hdr, const void *buff) pend_len = hdr_get_length(hdr); pend_slots = bytes_to_slots(pend_len); - /* Write the body in whole slots */ - for (i = 1; i < pend_slots; i++, *p++) { + /* + * Write the body in whole slots starting from second slot + * (1st slot is HECI header, not counted in message size). + */ + for (i = 1; i < pend_slots + 1; i++, *p++) { write_slot(i, *p); } @@ -550,8 +553,11 @@ recv_one_message(uint32_t *hdr, void *buff, size_t maxlen, size_t *recv_len) return TXE_RX_ERR_RESP_LEN_MISMATCH; } - /* fetch whole slots first */ - for (i = 1; i < recv_slots; i++, *p++) { + /* + * Fetch whole slots starting from second slot + * (1st slot is HECI header, to counted in message size). + */ + for (i = 1; i < recv_slots + 1; i++, *p++) { *p = read_slot(i); }