System_Verilog_Basics/Operators at main · Daniyal-Tahsildar/System_Verilog_Basics

Name		Name	Last commit message	Last commit date
parent directory ..
pack_unpack_sample		pack_unpack_sample
README.md		README.md
concatenation_replication.sv		concatenation_replication.sv
set_membership.sv		set_membership.sv
streaming_operator.sv		streaming_operator.sv
wildcard_equality.sv		wildcard_equality.sv

README.md

This directory contains example code illustrating different types of operators used in SystemVerilog.

The suggested order to read the files is as follows:

Concatenation and Replication Operator:
- Explores concatenation across different data types, explains differences between right-hand-side and left-hand-side concatenation.
- Demonstrates replication using a constant number and a 'WIDTH macro.
Wildcard Equality Operator:
- Delves into wildcard equality and inequality, highlighting their utility in comparing masked variables generated using XOR.
Set Membership Operator:
- Showcases various usage scenarios of the set membership operator across different data types.
- Explains its application in both conditional statements and constraint blocks.
Streaming Operator:
- Demonstrates left and right streaming operators for SV and user-defined data types, detailing distinct behaviors for left-hand-side (LHS) and right-hand-side (RHS) assignments.
- The Example offers a comprehensive demonstration of using the streaming operator within a class to execute pack and unpack operations.
  - It is advisable to explore this example after becoming familiar with object-oriented concepts in SystemVerilog.