This directory contains example code showcasing the utilization of compiler directives in SystemVerilog
.
The suggested order to read the files is as follows:
-
- Introduces the functionality of
'define
and'undef
. - Explores parameterized macros, multi-line macros, and macros with and without default values for arguments.
- Introduces the functionality of
-
- Demonstrates the creation of methods using
'define
, that accepts arguments and utilizes them throughout the codebase.
- Demonstrates the creation of methods using
-
Using 'ifdef, 'ifndef and 'else:
- Illustrates the application of conditional directives, showcasing how distinct code blocks execute based on defined macros.