diff --git a/Code/OSEK/HwPlatform/ARM/OsHwPltfm.c b/Code/OSEK/HwPlatform/ARM/OsHwPltfm.c
index 455e840..0e7b055 100644
--- a/Code/OSEK/HwPlatform/ARM/OsHwPltfm.c
+++ b/Code/OSEK/HwPlatform/ARM/OsHwPltfm.c
@@ -129,7 +129,7 @@ void osInitInterrupts(void)
 ///
 /// \return void
 //------------------------------------------------------------------------------------------------------------------
-void osSetPMR(uint32 level)
+void osSetInterruptPriorityMask(uint32 level)
 {
   uint32 IntPrioBit = OsHwGetInterruptPrioBits();
   OsSetSysBasepriReg((level << (8U - IntPrioBit)));
@@ -144,7 +144,7 @@ void osSetPMR(uint32 level)
 ///
 /// \return void
 //------------------------------------------------------------------------------------------------------------------
-uint32 osGetPMR(void)
+uint32 osGetInterruptPriorityMask(void)
 {
   uint32 level = 0;
   uint32 IntPrioBit = OsHwGetInterruptPrioBits();
diff --git a/Code/OSEK/HwPlatform/ARM/OsHwPltfm.h b/Code/OSEK/HwPlatform/ARM/OsHwPltfm.h
index 6011abb..edbc887 100644
--- a/Code/OSEK/HwPlatform/ARM/OsHwPltfm.h
+++ b/Code/OSEK/HwPlatform/ARM/OsHwPltfm.h
@@ -110,8 +110,8 @@ typedef union
 #define SYS_TICK_ENABLE_INT          1U
 #define SYS_TICK_ENABLE_TIMER        1U
 
-uint32 osGetPMR(void);
-void   osSetPMR(uint32 level);
+uint32 osGetInterruptPriorityMask(void);
+void   osSetInterruptPriorityMask(uint32 level);
 uint32 OsGetEIIC(void);
 void   Ostm_Start(void);
 void   Ostm_Init(void);
diff --git a/Code/OSEK/HwPlatform/RISC-V/OsAsm.s b/Code/OSEK/HwPlatform/RISC-V/OsAsm.s
index a07ecd9..aff34d2 100644
--- a/Code/OSEK/HwPlatform/RISC-V/OsAsm.s
+++ b/Code/OSEK/HwPlatform/RISC-V/OsAsm.s
@@ -144,6 +144,7 @@ OsDispatchHandler:
                    jal OsDispatcher
                    mv sp, a0
                    OsRestoreCpuContext
+                   csrw mcause, zero
                    mret
 
 .size OsDispatchHandler, .-OsDispatchHandler
@@ -175,6 +176,7 @@ OsCat2IsrWrapper:
                    jal OsIntCallDispatch
                    mv sp, a0
                    OsRestoreCpuContext
+                   csrw mcause, zero
                    mret
 
 .size OsCat2IsrWrapper, .-OsCat2IsrWrapper
@@ -227,6 +229,7 @@ OsStartNewTask:
                  mv x29,x0
                  mv x30,x0
                  mv x31,x0
+                 csrw mcause, zero
                  mret
 
 .size OsStartNewTask, .-OsStartNewTask
diff --git a/Code/OSEK/HwPlatform/RISC-V/OsHwPltfm.c b/Code/OSEK/HwPlatform/RISC-V/OsHwPltfm.c
index 706ff21..66ee82f 100644
--- a/Code/OSEK/HwPlatform/RISC-V/OsHwPltfm.c
+++ b/Code/OSEK/HwPlatform/RISC-V/OsHwPltfm.c
@@ -40,8 +40,7 @@ volatile uint32 OsHwPltfmSavedIntState = 0;
 //------------------------------------------------------------------------------------------------------------------
 boolean OsIsInterruptContext(void)
 {
-  //return((boolean)(PFIC->GISR.bit.GACTSTA));
-  return 0;
+  return((uint32_t)(riscv_read_csr(RVCSR_MCAUSE_OFFSET) >> 31) == 0ul ? FALSE : TRUE);
 }
 
 //------------------------------------------------------------------------------------------------------------------
@@ -55,25 +54,7 @@ boolean OsIsInterruptContext(void)
 //------------------------------------------------------------------------------------------------------------------
 uint32 osGetHwIntNestingLevel(void)
 {
-/*
-  uint8 u8CurrentNestingLevel = PFIC->GISR.bit.NESTSTA;
-
-  switch(u8CurrentNestingLevel)
-  {
-    case 0x03: u8CurrentNestingLevel = 2u; break;
-    case 0x07: u8CurrentNestingLevel = 3u; break;
-    case 0x0F: u8CurrentNestingLevel = 4u; break;
-    case 0x1F: u8CurrentNestingLevel = 5u; break;
-    case 0x3F: u8CurrentNestingLevel = 6u; break;
-    case 0x7F: u8CurrentNestingLevel = 7u; break;
-    case 0xFF: u8CurrentNestingLevel = 8u; break;
-    default:
-    break;
-  }
-
-  return((uint32)(u8CurrentNestingLevel));
-*/
-return 1;
+  return 1;
 }
 
 //-----------------------------------------------------------------------------
@@ -139,42 +120,7 @@ void osHwTimerReload(void)
 //------------------------------------------------------------------------------------------------------------------
 void osInitInterrupts(void)
 {
-#if 0
-  uint32 u32IntRegOffset    = 0;
-  uint32 u32IntBitPosition  = 0;
-  
-  OsSetIntVectTableAddress((uint32*)&osIntVectTable);
-
-  for(uint32 IntId = 0; IntId <= 103; IntId++)
-  {
-    u32IntRegOffset    = (uint32)(IntId / 32u);
-    u32IntBitPosition  = (uint32)(IntId - (32u*u32IntRegOffset));
-    
-    if(IsrLookupTable[IntId].IsrFunc != pISR(Undefined))
-    {
-      /* configure the interrupt's priority */
-      *((volatile uint8*)((uint32)(&PFIC->IPRIOR0) + IntId)) = (uint8)((IsrLookupTable[IntId].Prio) << 4u);
 
-      /* enable the interrupt */
-      *((volatile uint32*)((uint32)(&PFIC->IENR1.reg) + sizeof(uint32)*u32IntRegOffset)) |= (uint32)(1ul << u32IntBitPosition);
-    }
-    else
-    {
-      /* disable the interrupt */
-      *((volatile uint32*)((&PFIC->IRER1.reg) + sizeof(uint32)*u32IntRegOffset)) |= (uint32)(1ul << u32IntBitPosition);
-    }
-  }
-
-  /* configure the interrupt system control
-    8 nested levels, 3 preemption bits, no Hardware stack */
-  osSetINTSYSCR(0x0E);
-#endif
-}
-
-ISR(WindowWatchdogInt);
-ISR(WindowWatchdogInt)
-{
- __asm("nop");
 }
 
 //------------------------------------------------------------------------------------------------------------------
@@ -186,7 +132,7 @@ ISR(WindowWatchdogInt)
 ///
 /// \return void
 //------------------------------------------------------------------------------------------------------------------
-void osSetPMR(uint32 level)
+void osSetInterruptPriorityMask(uint32 level) /*osSetInterruptPriorityMask*/
 {
   (void)level;
   //PFIC->ITHRESDR.reg = (uint32)level << 4;
@@ -201,7 +147,7 @@ void osSetPMR(uint32 level)
 ///
 /// \return void
 //------------------------------------------------------------------------------------------------------------------
-uint32 osGetPMR(void)
+uint32 osGetInterruptPriorityMask(void) /*osGetInterruptPriorityMask*/
 {
   //return(PFIC->ITHRESDR.reg >> 4);
   return 0;
@@ -210,7 +156,7 @@ uint32 osGetPMR(void)
 //------------------------------------------------------------------------------------------------------------------
 /// \brief  OsRunCat2Isr
 ///
-/// \descr  This function is the entry point of all category 2 interrupts (PLIC).
+/// \descr  This function is the entry point of all category 2 interrupts
 ///
 /// \param  void
 ///
@@ -247,7 +193,7 @@ void OsCatchAllCpuExceptions(void)
 //------------------------------------------------------------------------------------------------------------------
 void osSaveAndDisableIntState(void)
 {
-  //OsHwPltfmSavedIntState = csr_read_clr_bits_mstatus(MSTATUS_MIE_BIT_MASK);
+  OsHwPltfmSavedIntState = riscv_read_clear_csr(RVCSR_MSTATUS_OFFSET, RVCSR_MSTATUS_MIE_BITS);
 }
 
 //------------------------------------------------------------------------------------------------------------------
@@ -261,5 +207,5 @@ void osSaveAndDisableIntState(void)
 //------------------------------------------------------------------------------------------------------------------
 void osRestoreSavedIntState(void)
 {
-  //csr_write_mstatus(OsHwPltfmSavedIntState);
+  riscv_write_csr(RVCSR_MSTATUS_OFFSET, OsHwPltfmSavedIntState);
 }
diff --git a/Code/OSEK/HwPlatform/RISC-V/OsHwPltfm.h b/Code/OSEK/HwPlatform/RISC-V/OsHwPltfm.h
index eb272fc..d4f3a9a 100644
--- a/Code/OSEK/HwPlatform/RISC-V/OsHwPltfm.h
+++ b/Code/OSEK/HwPlatform/RISC-V/OsHwPltfm.h
@@ -32,8 +32,8 @@
 //=========================================================================================
 #define osDispatch()              HW_PER_SIO->RISCV_SOFTIRQ.reg = (1ul << (HW_PER_SIO->CPUID.reg)); __asm("fence"); riscv_set_csr(RVCSR_MIE_OFFSET, RVCSR_MIE_MSIE_BITS);
 
-#define ENABLE_INTERRUPTS()       riscv_set_csr(RVCSR_MSTATUS_OFFSET, 0x08ul)
-#define DISABLE_INTERRUPTS()      riscv_clear_csr(RVCSR_MSTATUS_OFFSET, 0x08ul)
+#define ENABLE_INTERRUPTS()       riscv_set_csr(RVCSR_MSTATUS_OFFSET, RVCSR_MSTATUS_MIE_BITS)
+#define DISABLE_INTERRUPTS()      riscv_clear_csr(RVCSR_MSTATUS_OFFSET, RVCSR_MSTATUS_MIE_BITS)
 
 #define osSetINTSYSCR(value)        //__asm volatile ("csrw    0x804, %0" : : "r" (value) :)
 #define osMaskClearINTSYSCR(value)  //__asm volatile ("csrrc   zero, 0x804, %0" : : "r" (value) :)
@@ -54,8 +54,8 @@ extern uint32 osIntVectTable;
 //=========================================================================================
 // Functions Prototype
 //=========================================================================================
-uint32 osGetPMR(void);
-void osSetPMR(uint32 level);
+uint32 osGetInterruptPriorityMask(void);
+void osSetInterruptPriorityMask(uint32 level);
 void osHwTimerInit(void);
 void osHwTimerStart(void);
 void osHwTimerReload(void);
diff --git a/Code/OSEK/OsCore.c b/Code/OSEK/OsCore.c
index 03bef45..05e857c 100644
--- a/Code/OSEK/OsCore.c
+++ b/Code/OSEK/OsCore.c
@@ -526,10 +526,10 @@ void OS_ResumeAllInterrupts(void)
 void OS_SuspendOSInterrupts(void)
 {
   /* Get the global mask prio */
-  OCB_Cfg.OsInterruptSavedLevel = osGetPMR();
+  OCB_Cfg.OsInterruptSavedLevel = osGetInterruptPriorityMask();
 
   /* Disable OS interrupts */
-  osSetPMR(OS_INT_CAT1_LOWEST_PRIO_LEVEL);
+  osSetInterruptPriorityMask(OS_INT_CAT1_LOWEST_PRIO_LEVEL);
 }
 
 //------------------------------------------------------------------------------------------------------------------
@@ -544,7 +544,7 @@ void OS_SuspendOSInterrupts(void)
 void OS_ResumeOSInterrupts(void)
 {
   /* Restore the global mask prio */
-  osSetPMR(OCB_Cfg.OsInterruptSavedLevel);
+  osSetInterruptPriorityMask(OCB_Cfg.OsInterruptSavedLevel);
 }
 
 //------------------------------------------------------------------------------------------------------------------