diff --git a/hugr-llvm/src/extension/logic.rs b/hugr-llvm/src/extension/logic.rs
index a1d42d3f6..32a58923c 100644
--- a/hugr-llvm/src/extension/logic.rs
+++ b/hugr-llvm/src/extension/logic.rs
@@ -56,6 +56,7 @@ fn emit_logic_op<'c, H: HugrView>(
             }
             acc
         }
+        LogicOp::Not => builder.build_not(inputs[0], "")?,
         op => {
             return Err(anyhow!("LogicOpEmitter: Unknown op: {op:?}"));
         }
@@ -140,4 +141,11 @@ mod test {
         let hugr = test_logic_op(LogicOp::Eq, 2);
         check_emission!(hugr, llvm_ctx);
     }
+
+    #[rstest]
+    fn not(mut llvm_ctx: TestContext) {
+        llvm_ctx.add_extensions(add_logic_extensions);
+        let hugr = test_logic_op(LogicOp::Not, 1);
+        check_emission!(hugr, llvm_ctx);
+    }
 }
diff --git a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__logic__test__not@llvm14.snap b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__logic__test__not@llvm14.snap
new file mode 100644
index 000000000..04b199fd3
--- /dev/null
+++ b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__logic__test__not@llvm14.snap
@@ -0,0 +1,18 @@
+---
+source: hugr-llvm/src/extension/logic.rs
+expression: mod_str
+---
+; ModuleID = 'test_context'
+source_filename = "test_context"
+
+define { i32, {}, {} } @_hl.main.1({ i32, {}, {} } %0) {
+alloca_block:
+  br label %entry_block
+
+entry_block:                                      ; preds = %alloca_block
+  %1 = extractvalue { i32, {}, {} } %0, 0
+  %2 = xor i32 %1, -1
+  %3 = trunc i32 %2 to i1
+  %4 = select i1 %3, { i32, {}, {} } { i32 1, {} poison, {} undef }, { i32, {}, {} } { i32 0, {} undef, {} poison }
+  ret { i32, {}, {} } %4
+}
diff --git a/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__logic__test__not@pre-mem2reg@llvm14.snap b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__logic__test__not@pre-mem2reg@llvm14.snap
new file mode 100644
index 000000000..86cf3f41c
--- /dev/null
+++ b/hugr-llvm/src/extension/snapshots/hugr_llvm__extension__logic__test__not@pre-mem2reg@llvm14.snap
@@ -0,0 +1,27 @@
+---
+source: hugr-llvm/src/extension/logic.rs
+expression: mod_str
+---
+; ModuleID = 'test_context'
+source_filename = "test_context"
+
+define { i32, {}, {} } @_hl.main.1({ i32, {}, {} } %0) {
+alloca_block:
+  %"0" = alloca { i32, {}, {} }, align 8
+  %"2_0" = alloca { i32, {}, {} }, align 8
+  %"4_0" = alloca { i32, {}, {} }, align 8
+  br label %entry_block
+
+entry_block:                                      ; preds = %alloca_block
+  store { i32, {}, {} } %0, { i32, {}, {} }* %"2_0", align 4
+  %"2_01" = load { i32, {}, {} }, { i32, {}, {} }* %"2_0", align 4
+  %1 = extractvalue { i32, {}, {} } %"2_01", 0
+  %2 = xor i32 %1, -1
+  %3 = trunc i32 %2 to i1
+  %4 = select i1 %3, { i32, {}, {} } { i32 1, {} poison, {} undef }, { i32, {}, {} } { i32 0, {} undef, {} poison }
+  store { i32, {}, {} } %4, { i32, {}, {} }* %"4_0", align 4
+  %"4_02" = load { i32, {}, {} }, { i32, {}, {} }* %"4_0", align 4
+  store { i32, {}, {} } %"4_02", { i32, {}, {} }* %"0", align 4
+  %"03" = load { i32, {}, {} }, { i32, {}, {} }* %"0", align 4
+  ret { i32, {}, {} } %"03"
+}