| Category | Difficulty |
|---|---|
| HW | 5 |
| Projects | 8 |
This is the seminal class in the hardware systems track in ECE. Most students take this course shortly after 18-240 and before. This course has no exams, and your grade is solely determined by how well you do on the projects. The level of difficulty of the projects vary wildly, ranging from something that can be done in a single evening to something that could take many, many days.
The homeworks are a lot like the homeworks that were in 18-240. They aren't super intellectually challenging, but take a fair bit of time to do them correctly.
It's important to note that lectures aren't mandatory, and much of what you need to be able to complete the projects are in just a few of the lecture slides. That being said, Professor Nace put in a lot of time into making the lectures and they cover a lot of interesting topics. Additionally, the content from Professor Nace's lecture slides are chalk full of content used for hardware interviews. Additionally, Professor Nace tries to get a few guest lecturers to come in towards the end of the semester from some prominent companies.
While there are not too many resources for the course, Nace has several books that you can ask about during his OH that you can checkout at the CMU library. In addition, if you're serious about learning how to use System Verilog professionally, the textbook is a worthwhile investment.
- System Verilog
- Pipelining
- FSM+D Design and Implementation
- FPGA Synthesis
- Signal Tap
- Hardware Design
- VCS
- Industry Verification
Similar to the 240 style of homeworks. Can range from short coding assignments to paper assignments you'll discuss in class. Again, these aren't super challenging, but they do take a lot of time.
Some of these labs are very time intensive. Additionally, for one of the labs (USB), you will be assigned a random partner from the class. They are mostly self-paced, so the onus is own yourself to make sure you stay on top of all the assignments and check-ins.
The router lab can be deceivingly simple, since the basic concepts of a router (just need to forward data), is easy to grasp, but actually implementing it can lead to many issues, especially since there are performance requirements for the lab.
The final lab, where you have to work with the SMP 68K machine is quite time consuming, and requires a lot of datasheet digging and waveform debugging. It's a nice comprehensive lab to conclude the course, but expect to spend a lot of time figuring out not only what is going on in your code, but how the hardware fundamentally works.
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Start the labs early
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Don't be afraid of the TAs. Nace usually vets them thoroughly
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Not impossible to do well, the grading scheme is quite forgiving
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There are some important 240 concepts you should know before taking this class. For example, understanding Mealy and Moore machines, and how to construct them to perform tasks that aren't just simple exercises -- in 240 you might be asked to make a palindrome detector, but in this class you might want to make Mealy machines to perform more complicated logic.
Planning some of your state machines on paper ahead of time can be useful.
- Expect to spend a lot of time on this class
- This class is incredibly System Verilog intensive. You will have to know SV language specifics, as well as how to translate complex designs and thoughts into SV.