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driver-icarus.c
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/*
* Copyright 2012-2013 Andrew Smith
* Copyright 2012 Xiangfu <[email protected]>
* Copyright 2013-2014 Con Kolivas <[email protected]>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 3 of the License, or (at your option)
* any later version. See COPYING for more details.
*/
/*
* Those code should be works fine with V2 and V3 bitstream of Icarus.
* Operation:
* No detection implement.
* Input: 64B = 32B midstate + 20B fill bytes + last 12 bytes of block head.
* Return: send back 32bits immediately when Icarus found a valid nonce.
* no query protocol implemented here, if no data send back in ~11.3
* seconds (full cover time on 32bit nonce range by 380MH/s speed)
* just send another work.
* Notice:
* 1. Icarus will start calculate when you push a work to them, even they
* are busy.
* 2. The 2 FPGAs on Icarus will distribute the job, one will calculate the
* 0 ~ 7FFFFFFF, another one will cover the 80000000 ~ FFFFFFFF.
* 3. It's possible for 2 FPGAs both find valid nonce in the meantime, the 2
* valid nonce will all be send back.
* 4. Icarus will stop work when: a valid nonce has been found or 32 bits
* nonce range is completely calculated.
*/
#include <float.h>
#include <limits.h>
#include <pthread.h>
#include <stdint.h>
#include <stdio.h>
#include <strings.h>
#include <sys/time.h>
#include <unistd.h>
#include <math.h>
#include "config.h"
#ifdef WIN32
#include <windows.h>
#endif
#include "compat.h"
#include "miner.h"
#include "usbutils.h"
#define ROCKMINER
#define ROCKMINER_PRINT_DEBUG 0
// The serial I/O speed - Linux uses a define 'B115200' in bits/termios.h
#define ICARUS_IO_SPEED 115200
#define ICARUS_BUF_SIZE 8
// The size of a successful nonce read
#define ANT_READ_SIZE 5
#define ICARUS_READ_SIZE 4
#define ROCK_READ_SIZE 8
// Ensure the sizes are correct for the Serial read
#if (ICARUS_READ_SIZE != 4)
#error ICARUS_READ_SIZE must be 4
#endif
#define ASSERT1(condition) __maybe_unused static char sizeof_uint32_t_must_be_4[(condition)?1:-1]
ASSERT1(sizeof(uint32_t) == 4);
// TODO: USB? Different calculation? - see usbstats to work it out e.g. 1/2 of normal send time
// or even use that number? 1/2
// #define ICARUS_READ_TIME(baud) ((double)ICARUS_READ_SIZE * (double)8.0 / (double)(baud))
// maybe 1ms?
#define ICARUS_READ_TIME(baud) (0.001)
// USB ms timeout to wait - user specified timeouts are multiples of this
#define ICARUS_WAIT_TIMEOUT 100
#define ANT_WAIT_TIMEOUT 10
#define ICARUS_CMR2_TIMEOUT 1
// Defined in multiples of ICARUS_WAIT_TIMEOUT
// Must of course be greater than ICARUS_READ_COUNT_TIMING/ICARUS_WAIT_TIMEOUT
// There's no need to have this bigger, since the overhead/latency of extra work
// is pretty small once you get beyond a 10s nonce range time and 10s also
// means that nothing slower than 429MH/s can go idle so most icarus devices
// will always mine without idling
#define ICARUS_READ_TIME_LIMIT_MAX 100
// In timing mode: Default starting value until an estimate can be obtained
// 5000 ms allows for up to a ~840MH/s device
#define ICARUS_READ_COUNT_TIMING 5000
// Antminer USB is > 1GH/s so use a shorter limit
// 1000 ms allows for up to ~4GH/s device
#define ANTUSB_READ_COUNT_TIMING 1000
#define ICARUS_READ_COUNT_MIN ICARUS_WAIT_TIMEOUT
#define SECTOMS(s) ((int)((s) * 1000))
// How many ms below the expected completion time to abort work
// extra in case the last read is delayed
#define ICARUS_READ_REDUCE ((int)(ICARUS_WAIT_TIMEOUT * 1.5))
// For a standard Icarus REV3 (to 5 places)
// Since this rounds up a the last digit - it is a slight overestimate
// Thus the hash rate will be a VERY slight underestimate
// (by a lot less than the displayed accuracy)
// Minor inaccuracy of these numbers doesn't affect the work done,
// only the displayed MH/s
#define ICARUS_REV3_HASH_TIME 0.0000000026316
#define LANCELOT_HASH_TIME 0.0000000025000
#define ASICMINERUSB_HASH_TIME 0.0000000029761
// TODO: What is it?
#define CAIRNSMORE1_HASH_TIME 0.0000000027000
// Per FPGA
#define CAIRNSMORE2_HASH_TIME 0.0000000066600
#define NANOSEC 1000000000.0
#define ANTMINERUSB_HASH_MHZ 0.000000125
#define ANTMINERUSB_HASH_TIME (ANTMINERUSB_HASH_MHZ / (double)(opt_anu_freq))
#define CAIRNSMORE2_INTS 4
// Icarus Rev3 doesn't send a completion message when it finishes
// the full nonce range, so to avoid being idle we must abort the
// work (by starting a new work item) shortly before it finishes
//
// Thus we need to estimate 2 things:
// 1) How many hashes were done if the work was aborted
// 2) How high can the timeout be before the Icarus is idle,
// to minimise the number of work items started
// We set 2) to 'the calculated estimate' - ICARUS_READ_REDUCE
// to ensure the estimate ends before idle
//
// The simple calculation used is:
// Tn = Total time in seconds to calculate n hashes
// Hs = seconds per hash
// Xn = number of hashes
// W = code/usb overhead per work
//
// Rough but reasonable estimate:
// Tn = Hs * Xn + W (of the form y = mx + b)
//
// Thus:
// Line of best fit (using least squares)
//
// Hs = (n*Sum(XiTi)-Sum(Xi)*Sum(Ti))/(n*Sum(Xi^2)-Sum(Xi)^2)
// W = Sum(Ti)/n - (Hs*Sum(Xi))/n
//
// N.B. W is less when aborting work since we aren't waiting for the reply
// to be transferred back (ICARUS_READ_TIME)
// Calculating the hashes aborted at n seconds is thus just n/Hs
// (though this is still a slight overestimate due to code delays)
//
// Both below must be exceeded to complete a set of data
// Minimum how long after the first, the last data point must be
#define HISTORY_SEC 60
// Minimum how many points a single ICARUS_HISTORY should have
#define MIN_DATA_COUNT 5
// The value MIN_DATA_COUNT used is doubled each history until it exceeds:
#define MAX_MIN_DATA_COUNT 100
static struct timeval history_sec = { HISTORY_SEC, 0 };
// Store the last INFO_HISTORY data sets
// [0] = current data, not yet ready to be included as an estimate
// Each new data set throws the last old set off the end thus
// keeping a ongoing average of recent data
#define INFO_HISTORY 10
struct ICARUS_HISTORY {
struct timeval finish;
double sumXiTi;
double sumXi;
double sumTi;
double sumXi2;
uint32_t values;
uint32_t hash_count_min;
uint32_t hash_count_max;
};
enum timing_mode { MODE_DEFAULT, MODE_SHORT, MODE_LONG, MODE_VALUE };
static const char *MODE_DEFAULT_STR = "default";
static const char *MODE_SHORT_STR = "short";
static const char *MODE_SHORT_STREQ = "short=";
static const char *MODE_LONG_STR = "long";
static const char *MODE_LONG_STREQ = "long=";
static const char *MODE_VALUE_STR = "value";
static const char *MODE_UNKNOWN_STR = "unknown";
struct ICARUS_INFO {
enum sub_ident ident;
int intinfo;
// time to calculate the golden_ob
uint64_t golden_hashes;
struct timeval golden_tv;
struct ICARUS_HISTORY history[INFO_HISTORY+1];
uint32_t min_data_count;
int timeout;
// seconds per Hash
double Hs;
// ms til we abort
int read_time;
// ms limit for (short=/long=) read_time
int read_time_limit;
// How long without hashes is considered a failed device
int fail_time;
enum timing_mode timing_mode;
bool do_icarus_timing;
double fullnonce;
int count;
double W;
uint32_t values;
uint64_t hash_count_range;
// Determine the cost of history processing
// (which will only affect W)
uint64_t history_count;
struct timeval history_time;
// icarus-options
int baud;
int work_division;
int fpga_count;
uint32_t nonce_mask;
uint8_t cmr2_speed;
bool speed_next_work;
bool flash_next_work;
int nonce_size;
bool failing;
};
#define ICARUS_MIDSTATE_SIZE 32
#define ICARUS_UNUSED_SIZE 16
#define ICARUS_WORK_SIZE 12
#define ICARUS_WORK_DATA_OFFSET 64
#define ICARUS_CMR2_SPEED_FACTOR 2.5
#define ICARUS_CMR2_SPEED_MIN_INT 100
#define ICARUS_CMR2_SPEED_DEF_INT 180
#define ICARUS_CMR2_SPEED_MAX_INT 220
#define CMR2_INT_TO_SPEED(_speed) ((uint8_t)((float)_speed / ICARUS_CMR2_SPEED_FACTOR))
#define ICARUS_CMR2_SPEED_MIN CMR2_INT_TO_SPEED(ICARUS_CMR2_SPEED_MIN_INT)
#define ICARUS_CMR2_SPEED_DEF CMR2_INT_TO_SPEED(ICARUS_CMR2_SPEED_DEF_INT)
#define ICARUS_CMR2_SPEED_MAX CMR2_INT_TO_SPEED(ICARUS_CMR2_SPEED_MAX_INT)
#define ICARUS_CMR2_SPEED_INC 1
#define ICARUS_CMR2_SPEED_DEC -1
#define ICARUS_CMR2_SPEED_FAIL -10
#define ICARUS_CMR2_PREFIX ((uint8_t)0xB7)
#define ICARUS_CMR2_CMD_SPEED ((uint8_t)0)
#define ICARUS_CMR2_CMD_FLASH ((uint8_t)1)
#define ICARUS_CMR2_DATA_FLASH_OFF ((uint8_t)0)
#define ICARUS_CMR2_DATA_FLASH_ON ((uint8_t)1)
#define ICARUS_CMR2_CHECK ((uint8_t)0x6D)
struct ICARUS_WORK {
uint8_t midstate[ICARUS_MIDSTATE_SIZE];
// These 4 bytes are for CMR2 bitstreams that handle MHz adjustment
uint8_t check;
uint8_t data;
uint8_t cmd;
uint8_t prefix;
uint8_t unused[ICARUS_UNUSED_SIZE];
uint8_t work[ICARUS_WORK_SIZE];
};
#define MAX_DEVICE_NUM 100
#define MAX_WORK_BUFFER_SIZE 2
#define MAX_CHIP_NUM 24
#define NONCE_CORRECTION_TIMES 3
#define MAX_TRIES 4
//#define NONCE_TEST
#define RM_CMD_MASK 0x0F
#define RM_STATUS_MASK 0xF0
#define RM_CHIP_MASK 0x3F
#define RM_PRODUCT_MASK 0xC0
#define RM_PRODUCT_RBOX 0x00
#define RM_PRODUCT_T1 0x10
#ifdef NONCE_TEST
int device_nonce_conunts[MAX_DEVICE_NUM];
int chip_nonce_conunts[MAX_CHIP_NUM];
int chip_work_conunts[MAX_CHIP_NUM];
int device_nonce_corr_ok_1[MAX_DEVICE_NUM];
int device_nonce_corr_ok[MAX_DEVICE_NUM];
int device_nonce_corr_fail[MAX_DEVICE_NUM];
int device_nonce_corr_fail_2[MAX_DEVICE_NUM];
#endif
typedef enum {
NONCE_DATA1_OFFSET= 0,
NONCE_DATA2_OFFSET,
NONCE_DATA3_OFFSET,
NONCE_DATA4_OFFSET,
NONCE_TASK_CMD_OFFSET,
NONCE_CHIP_NO_OFFSET,
NONCE_TASK_NO_OFFSET,
NONCE_COMMAND_OFFSET,
NONCE_MAX_OFFSET
} NONCE_OFFSET;
typedef enum {
NONCE_DATA_CMD= 0,
NONCE_TASK_COMPLETE_CMD,
NONCE_GET_TASK_CMD,
} NONCE_COMMAND;
typedef struct NONCE_DATA
{
int chip_no ;
unsigned int task_no ;
unsigned char work_state;
int cmd_value;
}NONCE_DATA;
typedef enum {
ROCKMINER_RBOX= 0,
ROCKMINER_T1,
ROCKMINER_MAX
} ROCKMINER_PRODUCT_T;
typedef struct ROCKMINER_CHIP_INFO
{
unsigned char freq;
int error_cnt;
time_t last_received_task_complete_time;
}ROCKMINER_CHIP_INFO;
typedef struct ROCKMINER_DEVICE_INFO
{
unsigned char detect_chip_no;
unsigned char chip_max;
unsigned char product_id;
float min_frq;
float def_frq;
float max_frq;
ROCKMINER_CHIP_INFO chip[MAX_CHIP_NUM];
time_t dev_detect_time;
}ROCKMINER_DEVICE_INFO;
ROCKMINER_DEVICE_INFO rmdev[MAX_DEVICE_NUM];
#define END_CONDITION 0x0000ffff
// Looking for options in --icarus-timing and --icarus-options:
//
// Code increments this each time we start to look at a device
// However, this means that if other devices are checked by
// the Icarus code (e.g. Avalon only as at 20130517)
// they will count in the option offset
//
// This, however, is deterministic so that's OK
//
// If we were to increment after successfully finding an Icarus
// that would be random since an Icarus may fail and thus we'd
// not be able to predict the option order
//
// Devices are checked in the order libusb finds them which is ?
//
static int option_offset = -1;
/*
#define ICA_BUFSIZ (0x200)
static void transfer_read(struct cgpu_info *icarus, uint8_t request_type, uint8_t bRequest, uint16_t wValue, uint16_t wIndex, char *buf, int bufsiz, int *amount, enum usb_cmds cmd)
{
int err;
err = usb_transfer_read(icarus, request_type, bRequest, wValue, wIndex, buf, bufsiz, amount, cmd);
applog(LOG_DEBUG, "%s: cgid %d %s got err %d",
icarus->drv->name, icarus->cgminer_id,
usb_cmdname(cmd), err);
}
*/
static void _transfer(struct cgpu_info *icarus, uint8_t request_type, uint8_t bRequest, uint16_t wValue, uint16_t wIndex, uint32_t *data, int siz, enum usb_cmds cmd)
{
int err;
err = usb_transfer_data(icarus, request_type, bRequest, wValue, wIndex, data, siz, cmd);
applog(LOG_DEBUG, "%s: cgid %d %s got err %d",
icarus->drv->name, icarus->cgminer_id,
usb_cmdname(cmd), err);
}
#define transfer(icarus, request_type, bRequest, wValue, wIndex, cmd) \
_transfer(icarus, request_type, bRequest, wValue, wIndex, NULL, 0, cmd)
static void icarus_initialise(struct cgpu_info *icarus, int baud)
{
struct ICARUS_INFO *info = (struct ICARUS_INFO *)(icarus->device_data);
uint16_t wValue, wIndex;
enum sub_ident ident;
int interface;
if (icarus->usbinfo.nodev)
return;
interface = _usb_interface(icarus, info->intinfo);
ident = usb_ident(icarus);
switch (ident) {
case IDENT_BLT:
case IDENT_LLT:
case IDENT_CMR1:
case IDENT_CMR2:
// Reset
transfer(icarus, FTDI_TYPE_OUT, FTDI_REQUEST_RESET, FTDI_VALUE_RESET,
interface, C_RESET);
if (icarus->usbinfo.nodev)
return;
// Latency
_usb_ftdi_set_latency(icarus, info->intinfo);
if (icarus->usbinfo.nodev)
return;
// Set data control
transfer(icarus, FTDI_TYPE_OUT, FTDI_REQUEST_DATA, FTDI_VALUE_DATA_BLT,
interface, C_SETDATA);
if (icarus->usbinfo.nodev)
return;
// default to BLT/LLT 115200
wValue = FTDI_VALUE_BAUD_BLT;
wIndex = FTDI_INDEX_BAUD_BLT;
if (ident == IDENT_CMR1 || ident == IDENT_CMR2) {
switch (baud) {
case 115200:
wValue = FTDI_VALUE_BAUD_CMR_115;
wIndex = FTDI_INDEX_BAUD_CMR_115;
break;
case 57600:
wValue = FTDI_VALUE_BAUD_CMR_57;
wIndex = FTDI_INDEX_BAUD_CMR_57;
break;
default:
quit(1, "icarus_intialise() invalid baud (%d) for Cairnsmore1", baud);
break;
}
}
// Set the baud
transfer(icarus, FTDI_TYPE_OUT, FTDI_REQUEST_BAUD, wValue,
(wIndex & 0xff00) | interface, C_SETBAUD);
if (icarus->usbinfo.nodev)
return;
// Set Modem Control
transfer(icarus, FTDI_TYPE_OUT, FTDI_REQUEST_MODEM, FTDI_VALUE_MODEM,
interface, C_SETMODEM);
if (icarus->usbinfo.nodev)
return;
// Set Flow Control
transfer(icarus, FTDI_TYPE_OUT, FTDI_REQUEST_FLOW, FTDI_VALUE_FLOW,
interface, C_SETFLOW);
if (icarus->usbinfo.nodev)
return;
// Clear any sent data
transfer(icarus, FTDI_TYPE_OUT, FTDI_REQUEST_RESET, FTDI_VALUE_PURGE_TX,
interface, C_PURGETX);
if (icarus->usbinfo.nodev)
return;
// Clear any received data
transfer(icarus, FTDI_TYPE_OUT, FTDI_REQUEST_RESET, FTDI_VALUE_PURGE_RX,
interface, C_PURGERX);
break;
case IDENT_ICA:
// Set Data Control
transfer(icarus, PL2303_CTRL_OUT, PL2303_REQUEST_CTRL, PL2303_VALUE_CTRL,
interface, C_SETDATA);
if (icarus->usbinfo.nodev)
return;
// Set Line Control
uint32_t ica_data[2] = { PL2303_VALUE_LINE0, PL2303_VALUE_LINE1 };
_transfer(icarus, PL2303_CTRL_OUT, PL2303_REQUEST_LINE, PL2303_VALUE_LINE,
interface, &ica_data[0], PL2303_VALUE_LINE_SIZE, C_SETLINE);
if (icarus->usbinfo.nodev)
return;
// Vendor
transfer(icarus, PL2303_VENDOR_OUT, PL2303_REQUEST_VENDOR, PL2303_VALUE_VENDOR,
interface, C_VENDOR);
break;
case IDENT_AMU:
case IDENT_ANU:
// Enable the UART
transfer(icarus, CP210X_TYPE_OUT, CP210X_REQUEST_IFC_ENABLE,
CP210X_VALUE_UART_ENABLE,
interface, C_ENABLE_UART);
if (icarus->usbinfo.nodev)
return;
// Set data control
transfer(icarus, CP210X_TYPE_OUT, CP210X_REQUEST_DATA, CP210X_VALUE_DATA,
interface, C_SETDATA);
if (icarus->usbinfo.nodev)
return;
// Set the baud
uint32_t data = CP210X_DATA_BAUD;
_transfer(icarus, CP210X_TYPE_OUT, CP210X_REQUEST_BAUD, 0,
interface, &data, sizeof(data), C_SETBAUD);
break;
default:
quit(1, "icarus_intialise() called with invalid %s cgid %i ident=%d",
icarus->drv->name, icarus->cgminer_id, ident);
}
}
static void rev(unsigned char *s, size_t l)
{
size_t i, j;
unsigned char t;
for (i = 0, j = l - 1; i < j; i++, j--) {
t = s[i];
s[i] = s[j];
s[j] = t;
}
}
#define ICA_NONCE_ERROR -1
#define ICA_NONCE_OK 0
#define ICA_NONCE_RESTART 1
#define ICA_NONCE_TIMEOUT 2
static int icarus_get_nonce(struct cgpu_info *icarus, unsigned char *buf, struct timeval *tv_start,
struct timeval *tv_finish, struct thr_info *thr, int read_time)
{
struct ICARUS_INFO *info = (struct ICARUS_INFO *)(icarus->device_data);
int err, amt, rc;
if (icarus->usbinfo.nodev)
return ICA_NONCE_ERROR;
cgtime(tv_start);
err = usb_read_ii_timeout_cancellable(icarus, info->intinfo, (char *)buf,
info->nonce_size, &amt, read_time,
C_GETRESULTS);
cgtime(tv_finish);
if (err < 0 && err != LIBUSB_ERROR_TIMEOUT) {
applog(LOG_ERR, "%s%i: Comms error (rerr=%d amt=%d)", icarus->drv->name,
icarus->device_id, err, amt);
dev_error(icarus, REASON_DEV_COMMS_ERROR);
return ICA_NONCE_ERROR;
}
if (amt >= ICARUS_READ_SIZE)
return ICA_NONCE_OK;
rc = SECTOMS(tdiff(tv_finish, tv_start));
if (thr && thr->work_restart) {
applog(LOG_DEBUG, "Icarus Read: Work restart at %d ms", rc);
return ICA_NONCE_RESTART;
}
if (amt > 0)
applog(LOG_DEBUG, "Icarus Read: Timeout reading for %d ms", rc);
else
applog(LOG_DEBUG, "Icarus Read: No data for %d ms", rc);
return ICA_NONCE_TIMEOUT;
}
static const char *timing_mode_str(enum timing_mode timing_mode)
{
switch(timing_mode) {
case MODE_DEFAULT:
return MODE_DEFAULT_STR;
case MODE_SHORT:
return MODE_SHORT_STR;
case MODE_LONG:
return MODE_LONG_STR;
case MODE_VALUE:
return MODE_VALUE_STR;
default:
return MODE_UNKNOWN_STR;
}
}
static void set_timing_mode(int this_option_offset, struct cgpu_info *icarus)
{
struct ICARUS_INFO *info = (struct ICARUS_INFO *)(icarus->device_data);
int read_count_timing = 0;
enum sub_ident ident;
double Hs, fail_time;
char buf[BUFSIZ+1];
char *ptr, *comma, *eq;
size_t max;
int i;
if (opt_icarus_timing == NULL)
buf[0] = '\0';
else {
ptr = opt_icarus_timing;
for (i = 0; i < this_option_offset; i++) {
comma = strchr(ptr, ',');
if (comma == NULL)
break;
ptr = comma + 1;
}
comma = strchr(ptr, ',');
if (comma == NULL)
max = strlen(ptr);
else
max = comma - ptr;
if (max > BUFSIZ)
max = BUFSIZ;
strncpy(buf, ptr, max);
buf[max] = '\0';
}
ident = usb_ident(icarus);
switch (ident) {
case IDENT_ICA:
info->Hs = ICARUS_REV3_HASH_TIME;
read_count_timing = ICARUS_READ_COUNT_TIMING;
break;
case IDENT_BLT:
case IDENT_LLT:
info->Hs = LANCELOT_HASH_TIME;
read_count_timing = ICARUS_READ_COUNT_TIMING;
break;
case IDENT_AMU:
info->Hs = ASICMINERUSB_HASH_TIME;
read_count_timing = ICARUS_READ_COUNT_TIMING;
break;
case IDENT_CMR1:
info->Hs = CAIRNSMORE1_HASH_TIME;
read_count_timing = ICARUS_READ_COUNT_TIMING;
break;
case IDENT_CMR2:
info->Hs = CAIRNSMORE2_HASH_TIME;
read_count_timing = ICARUS_READ_COUNT_TIMING;
break;
case IDENT_ANU:
info->Hs = ANTMINERUSB_HASH_TIME;
read_count_timing = ANTUSB_READ_COUNT_TIMING;
break;
default:
quit(1, "Icarus get_options() called with invalid %s ident=%d",
icarus->drv->name, ident);
}
info->read_time = 0;
info->read_time_limit = 0; // 0 = no limit
if (strcasecmp(buf, MODE_SHORT_STR) == 0) {
// short
info->read_time = read_count_timing;
info->timing_mode = MODE_SHORT;
info->do_icarus_timing = true;
} else if (strncasecmp(buf, MODE_SHORT_STREQ, strlen(MODE_SHORT_STREQ)) == 0) {
// short=limit
info->read_time = read_count_timing;
info->timing_mode = MODE_SHORT;
info->do_icarus_timing = true;
info->read_time_limit = atoi(&buf[strlen(MODE_SHORT_STREQ)]);
if (info->read_time_limit < 0)
info->read_time_limit = 0;
if (info->read_time_limit > ICARUS_READ_TIME_LIMIT_MAX)
info->read_time_limit = ICARUS_READ_TIME_LIMIT_MAX;
} else if (strcasecmp(buf, MODE_LONG_STR) == 0) {
// long
info->read_time = read_count_timing;
info->timing_mode = MODE_LONG;
info->do_icarus_timing = true;
} else if (strncasecmp(buf, MODE_LONG_STREQ, strlen(MODE_LONG_STREQ)) == 0) {
// long=limit
info->read_time = read_count_timing;
info->timing_mode = MODE_LONG;
info->do_icarus_timing = true;
info->read_time_limit = atoi(&buf[strlen(MODE_LONG_STREQ)]);
if (info->read_time_limit < 0)
info->read_time_limit = 0;
if (info->read_time_limit > ICARUS_READ_TIME_LIMIT_MAX)
info->read_time_limit = ICARUS_READ_TIME_LIMIT_MAX;
} else if ((Hs = atof(buf)) != 0) {
// ns[=read_time]
info->Hs = Hs / NANOSEC;
info->fullnonce = info->Hs * (((double)0xffffffff) + 1);
if ((eq = strchr(buf, '=')) != NULL)
info->read_time = atoi(eq+1) * ICARUS_WAIT_TIMEOUT;
if (info->read_time < ICARUS_READ_COUNT_MIN)
info->read_time = SECTOMS(info->fullnonce) - ICARUS_READ_REDUCE;
if (unlikely(info->read_time < ICARUS_READ_COUNT_MIN))
info->read_time = ICARUS_READ_COUNT_MIN;
info->timing_mode = MODE_VALUE;
info->do_icarus_timing = false;
} else {
// Anything else in buf just uses DEFAULT mode
info->fullnonce = info->Hs * (((double)0xffffffff) + 1);
if ((eq = strchr(buf, '=')) != NULL)
info->read_time = atoi(eq+1) * ICARUS_WAIT_TIMEOUT;
if (info->read_time < ICARUS_READ_COUNT_MIN)
info->read_time = SECTOMS(info->fullnonce) - ICARUS_READ_REDUCE;
if (unlikely(info->read_time < ICARUS_READ_COUNT_MIN))
info->read_time = ICARUS_READ_COUNT_MIN;
info->timing_mode = MODE_DEFAULT;
info->do_icarus_timing = false;
}
info->min_data_count = MIN_DATA_COUNT;
// All values are in multiples of ICARUS_WAIT_TIMEOUT
info->read_time_limit *= ICARUS_WAIT_TIMEOUT;
applog(LOG_DEBUG, "%s: cgid %d Init: mode=%s read_time=%dms limit=%dms Hs=%e",
icarus->drv->name, icarus->cgminer_id,
timing_mode_str(info->timing_mode),
info->read_time, info->read_time_limit, info->Hs);
/* Set the time to detect a dead device to 25 full nonce ranges. */
fail_time = info->Hs * 0xffffffffull * 25.0;
/* Integer accuracy is definitely enough. */
info->fail_time = fail_time;
}
static uint32_t mask(int work_division)
{
uint32_t nonce_mask = 0x7fffffff;
// yes we can calculate these, but this way it's easy to see what they are
switch (work_division) {
case 1:
nonce_mask = 0xffffffff;
break;
case 2:
nonce_mask = 0x7fffffff;
break;
case 4:
nonce_mask = 0x3fffffff;
break;
case 8:
nonce_mask = 0x1fffffff;
break;
default:
quit(1, "Invalid2 icarus-options for work_division (%d) must be 1, 2, 4 or 8", work_division);
}
return nonce_mask;
}
static void get_options(int this_option_offset, struct cgpu_info *icarus, int *baud, int *work_division, int *fpga_count)
{
char buf[BUFSIZ+1];
char *ptr, *comma, *colon, *colon2;
enum sub_ident ident;
size_t max;
int i, tmp;
if (opt_icarus_options == NULL)
buf[0] = '\0';
else {
ptr = opt_icarus_options;
for (i = 0; i < this_option_offset; i++) {
comma = strchr(ptr, ',');
if (comma == NULL)
break;
ptr = comma + 1;
}
comma = strchr(ptr, ',');
if (comma == NULL)
max = strlen(ptr);
else
max = comma - ptr;
if (max > BUFSIZ)
max = BUFSIZ;
strncpy(buf, ptr, max);
buf[max] = '\0';
}
ident = usb_ident(icarus);
switch (ident) {
case IDENT_ICA:
case IDENT_BLT:
case IDENT_LLT:
*baud = ICARUS_IO_SPEED;
*work_division = 2;
*fpga_count = 2;
break;
case IDENT_AMU:
case IDENT_ANU:
*baud = ICARUS_IO_SPEED;
*work_division = 1;
*fpga_count = 1;
break;
case IDENT_CMR1:
*baud = ICARUS_IO_SPEED;
*work_division = 2;
*fpga_count = 2;
break;
case IDENT_CMR2:
*baud = ICARUS_IO_SPEED;
*work_division = 1;
*fpga_count = 1;
break;
default:
quit(1, "Icarus get_options() called with invalid %s ident=%d",
icarus->drv->name, ident);
}
if (*buf) {
colon = strchr(buf, ':');
if (colon)
*(colon++) = '\0';
if (*buf) {
tmp = atoi(buf);
switch (tmp) {
case 115200:
*baud = 115200;
break;
case 57600:
*baud = 57600;
break;
default:
quit(1, "Invalid icarus-options for baud (%s) must be 115200 or 57600", buf);
}
}
if (colon && *colon) {
colon2 = strchr(colon, ':');
if (colon2)
*(colon2++) = '\0';
if (*colon) {
tmp = atoi(colon);
if (tmp == 1 || tmp == 2 || tmp == 4 || tmp == 8) {
*work_division = tmp;
*fpga_count = tmp; // default to the same
} else {
quit(1, "Invalid icarus-options for work_division (%s) must be 1, 2, 4 or 8", colon);
}
}
if (colon2 && *colon2) {
tmp = atoi(colon2);
if (tmp > 0 && tmp <= *work_division)
*fpga_count = tmp;
else {
quit(1, "Invalid icarus-options for fpga_count (%s) must be >0 and <=work_division (%d)", colon2, *work_division);
}
}
}
}
}
unsigned char crc5(unsigned char *ptr, unsigned char len)
{
unsigned char i, j, k;
unsigned char crc = 0x1f;
unsigned char crcin[5] = {1, 1, 1, 1, 1};
unsigned char crcout[5] = {1, 1, 1, 1, 1};
unsigned char din = 0;
j = 0x80;
k = 0;
for (i = 0; i < len; i++) {
if (*ptr & j)
din = 1;
else
din = 0;
crcout[0] = crcin[4] ^ din;
crcout[1] = crcin[0];
crcout[2] = crcin[1] ^ crcin[4] ^ din;
crcout[3] = crcin[2];
crcout[4] = crcin[3];
j = j >> 1;
k++;
if (k == 8) {
j = 0x80;
k = 0;
ptr++;
}
memcpy(crcin, crcout, 5);
}
crc = 0;
if(crcin[4])
crc |= 0x10;
if(crcin[3])
crc |= 0x08;
if(crcin[2])
crc |= 0x04;
if(crcin[1])
crc |= 0x02;
if(crcin[0])
crc |= 0x01;
return crc;
}
static bool anu_freqfound = false;
static uint16_t anu_freq_hex;
static void anu_find_freqhex(void)
{
float fout, best_fout = opt_anu_freq;
int od, nf, nr, no, n, m, bs;
float best_diff = 1000;
anu_freqfound = true;
for (od = 0; od < 4; od++) {
no = 1 << od;
for (n = 0; n < 16; n++) {
nr = n + 1;
for (m = 0; m < 64; m++) {
nf = m + 1;
fout = 25 * (float)nf /((float)(nr) * (float)(no));
if (fabsf(fout - opt_anu_freq) > best_diff)
continue;
if (500 <= (fout * no) && (fout * no) <= 1000)
bs = 1;
else
bs = 0;
best_diff = fabsf(fout - opt_anu_freq);
best_fout = fout;
anu_freq_hex = (bs << 14) | (m << 7) | (n << 2) | od;
if (fout == opt_anu_freq) {
applog(LOG_DEBUG, "ANU found exact frequency %.1f with hex %04x",
opt_anu_freq, anu_freq_hex);
return;
}
}
}
}
opt_anu_freq = best_fout;
applog(LOG_NOTICE, "ANU found nearest frequency %.1f with hex %04x", opt_anu_freq,
anu_freq_hex);
}
static bool set_anu_freq(struct cgpu_info *icarus, struct ICARUS_INFO *info)
{
unsigned char cmd_buf[4], rdreg_buf[4];
int amount, err;
char buf[512];
if (!anu_freqfound)
anu_find_freqhex();
memset(cmd_buf, 0, 4);
memset(rdreg_buf, 0, 4);
cmd_buf[0] = 2 | 0x80;
cmd_buf[1] = (anu_freq_hex & 0xff00u) >> 8;
cmd_buf[2] = (anu_freq_hex & 0x00ffu);
cmd_buf[3] = crc5(cmd_buf, 27);