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dat.h
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dat.h
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/* DAT.H (c) Copyright Roger Bowler, 1999-2009 */
/* ESA/390 Dynamic Address Translation */
/* Interpretive Execution - (c) Copyright Jan Jaeger, 1999-2009 */
/* z/Architecture support - (c) Copyright Jan Jaeger, 1999-2009 */
/*-------------------------------------------------------------------*/
/* This module implements the DAT, ALET, and ASN translation */
/* functions of the ESA/390 architecture, described in the manual */
/* SA22-7201-04 ESA/390 Principles of Operation. The numbers in */
/* square brackets in the comments refer to sections in the manual. */
/*-------------------------------------------------------------------*/
/*-------------------------------------------------------------------*/
/* Additional credits: */
/* S/370 DAT support by Jay Maynard (as described in */
/* GA22-7000 System/370 Principles of Operation) */
/* Clear remainder of ASTE when ASF=0 - Jan Jaeger */
/* S/370 DAT support when running under SIE - Jan Jaeger */
/* ESAME DAT support by Roger Bowler (SA22-7832) */
/* ESAME ASN authorization and ALET translation - Roger Bowler */
/*-------------------------------------------------------------------*/
#if !defined(OPTION_NO_INLINE_DAT) || defined(_DAT_C)
#if defined(FEATURE_DUAL_ADDRESS_SPACE)
/*-------------------------------------------------------------------*/
/* Translate ASN to produce address-space control parameters */
/* */
/* Input: */
/* asn Address space number to be translated */
/* regs Pointer to the CPU register context */
/* asteo Pointer to a word to receive real address of ASTE */
/* aste Pointer to 16-word area to receive a copy of the */
/* ASN second table entry associated with the ASN */
/* */
/* Output: */
/* If successful, the ASTE corresponding to the ASN value will */
/* be stored into the 16-word area pointed to by aste, and the */
/* return value is zero. Either 4 or 16 words will be stored */
/* depending on the value of the ASF control bit (CR0 bit 15). */
/* The real address of the ASTE will be stored into the word */
/* pointed to by asteo. */
/* */
/* If unsuccessful, the return value is a non-zero exception */
/* code indicating AFX-translation or ASX-translation error */
/* (this is to allow the LASP instruction to handle these */
/* exceptions by setting the condition code). */
/* */
/* A program check may be generated for addressing and ASN */
/* translation specification exceptions, in which case the */
/* function does not return. */
/*-------------------------------------------------------------------*/
_DAT_C_STATIC U16 ARCH_DEP(translate_asn) (U16 asn, REGS *regs,
U32 *asteo, U32 aste[])
{
U32 afte_addr; /* Address of AFTE */
U32 afte; /* ASN first table entry */
U32 aste_addr; /* Address of ASTE */
BYTE *aste_main; /* ASTE mainstor address */
int code; /* Exception code */
int numwords; /* ASTE size (4 or 16 words) */
int i; /* Array subscript */
/* [3.9.3.1] Use the AFX to obtain the real address of the AFTE */
afte_addr = (regs->CR(14) & CR14_AFTO) << 12;
afte_addr += (asn & ASN_AFX) >> 4;
/* Addressing exception if AFTE is outside main storage */
if (afte_addr > regs->mainlim)
goto asn_addr_excp;
/* Load the AFTE from main storage. All four bytes must be
fetched concurrently as observed by other CPUs */
afte_addr = APPLY_PREFIXING (afte_addr, regs->PX);
afte = ARCH_DEP(fetch_fullword_absolute) (afte_addr, regs);
/* AFX translation exception if AFTE invalid bit is set */
if (afte & AFTE_INVALID)
goto asn_afx_tran_excp;
#if !defined(FEATURE_ESAME)
/* ASN translation specification exception if reserved bits set */
if (!ASF_ENABLED(regs)) {
if (afte & AFTE_RESV_0)
goto asn_asn_tran_spec_excp;
} else {
if (afte & AFTE_RESV_1)
goto asn_asn_tran_spec_excp;
}
#endif /*!defined(FEATURE_ESAME)*/
/* [3.9.3.2] Use AFTE and ASX to obtain real address of ASTE */
if (!ASF_ENABLED(regs)) {
aste_addr = afte & AFTE_ASTO_0;
aste_addr += (asn & ASN_ASX) << 4;
numwords = 4;
} else {
aste_addr = afte & AFTE_ASTO_1;
aste_addr += (asn & ASN_ASX) << 6;
numwords = 16;
}
/* Ignore carry into bit position 0 of ASTO */
aste_addr &= 0x7FFFFFFF;
/* Addressing exception if ASTE is outside main storage */
if (aste_addr > regs->mainlim)
goto asn_addr_excp;
/* Return the real address of the ASTE */
*asteo = aste_addr;
/* Fetch the 16- or 64-byte ASN second table entry from real
storage. Each fullword of the ASTE must be fetched
concurrently as observed by other CPUs */
aste_addr = APPLY_PREFIXING (aste_addr, regs->PX);
aste_main = FETCH_MAIN_ABSOLUTE(aste_addr, regs, numwords * 4);
for (i = 0; i < numwords; i++)
{
aste[i] = fetch_fw(aste_main);
aste_main += 4;
}
/* Clear remaining words if fewer than 16 words were loaded */
while (i < 16) aste[i++] = 0;
/* Check the ASX invalid bit in the ASTE */
if (aste[0] & ASTE0_INVALID)
goto asn_asx_tran_excp;
#if !defined(FEATURE_ESAME)
/* Check the reserved bits in first two words of ASTE */
if ((aste[0] & ASTE0_RESV) || (aste[1] & ASTE1_RESV)
|| ((aste[0] & ASTE0_BASE)
#ifdef FEATURE_SUBSPACE_GROUP
&& !ASF_ENABLED(regs)
#endif /*FEATURE_SUBSPACE_GROUP*/
))
goto asn_asn_tran_spec_excp;
#endif /*!defined(FEATURE_ESAME)*/
return 0;
/* Conditions which always cause program check */
asn_addr_excp:
code = PGM_ADDRESSING_EXCEPTION;
goto asn_prog_check;
#if !defined(FEATURE_ESAME)
asn_asn_tran_spec_excp:
code = PGM_ASN_TRANSLATION_SPECIFICATION_EXCEPTION;
goto asn_prog_check;
#endif /*!defined(FEATURE_ESAME)*/
asn_prog_check:
regs->program_interrupt (regs, code);
/* Conditions which the caller may or may not program check */
asn_afx_tran_excp:
regs->TEA = asn;
code = PGM_AFX_TRANSLATION_EXCEPTION;
return code;
asn_asx_tran_excp:
regs->TEA = asn;
code = PGM_ASX_TRANSLATION_EXCEPTION;
return code;
} /* end function translate_asn */
#endif /*defined(FEATURE_DUAL_ADDRESS_SPACE)*/
#if defined(FEATURE_DUAL_ADDRESS_SPACE)
/*-------------------------------------------------------------------*/
/* Perform ASN authorization process */
/* */
/* Input: */
/* ax Authorization index */
/* aste Pointer to 16-word area containing a copy of the */
/* ASN second table entry associated with the ASN */
/* atemask Specifies which authority bit to test in the ATE: */
/* ATE_PRIMARY (for PT instruction) */
/* ATE_SECONDARY (for PR, SSAR, and LASP instructions, */
/* and all access register translations) */
/* regs Pointer to the CPU register context */
/* */
/* Operation: */
/* The AX is used to select an entry in the authority table */
/* pointed to by the ASTE, and an authorization bit in the ATE */
/* is tested. For ATE_PRIMARY (X'80'), the P bit is tested. */
/* For ATE_SECONDARY (X'40'), the S bit is tested. */
/* Authorization is successful if the ATE falls within the */
/* authority table limit and the tested bit value is 1. */
/* */
/* Output: */
/* If authorization is successful, the return value is zero. */
/* If authorization is unsuccessful, the return value is 1. */
/* */
/* A program check may be generated for addressing exception */
/* if the authority table entry address is invalid, and in */
/* this case the function does not return. */
/*-------------------------------------------------------------------*/
_DAT_C_STATIC int ARCH_DEP(authorize_asn) (U16 ax, U32 aste[],
int atemask, REGS *regs)
{
RADR ato; /* Authority table origin */
int atl; /* Authority table length */
BYTE ate; /* Authority table entry */
/* [3.10.3.1] Authority table lookup */
/* Isolate the authority table origin and length */
ato = aste[0] & ASTE0_ATO;
atl = aste[1] & ASTE1_ATL;
/* Authorization fails if AX is outside table */
if ((ax & 0xFFF0) > atl)
return 1;
/* Calculate the address of the byte in the authority
table which contains the 2 bit entry for this AX */
ato += (ax >> 2);
/* Ignore carry into bit position 0 */
ato &= 0x7FFFFFFF;
/* Addressing exception if ATE is outside main storage */
if (ato > regs->mainlim)
goto auth_addr_excp;
/* Load the byte containing the authority table entry
and shift the entry into the leftmost 2 bits */
ato = APPLY_PREFIXING (ato, regs->PX);
SIE_TRANSLATE(&ato, ACCTYPE_SIE, regs);
ate = regs->mainstor[ato];
ate <<= ((ax & 0x03)*2);
/* Set the main storage reference bit */
STORAGE_KEY(ato, regs) |= STORKEY_REF;
/* Authorization fails if the specified bit (either X'80' or
X'40' of the 2 bit authority table entry) is zero */
if ((ate & atemask) == 0)
return 1;
/* Exit with successful return code */
return 0;
/* Conditions which always cause program check */
auth_addr_excp:
regs->program_interrupt (regs, PGM_ADDRESSING_EXCEPTION);
return 1;
} /* end function authorize_asn */
#endif /*defined(FEATURE_DUAL_ADDRESS_SPACE)*/
#if defined(FEATURE_ACCESS_REGISTERS)
/*-------------------------------------------------------------------*/
/* Translate an ALET to produce the corresponding ASTE */
/* */
/* This routine performs both ordinary ART (as used by DAT when */
/* operating in access register mode, and by the TAR instruction), */
/* and special ART (as used by the BSG instruction). The caller */
/* is assumed to have already eliminated the special cases of ALET */
/* values 0 and 1 (which have different meanings depending on */
/* whether the caller is DAT, TAR, or BSG). */
/* */
/* Input: */
/* alet ALET value */
/* eax The authorization index (normally obtained from */
/* CR8; obtained from R2 for TAR; not used for BSG) */
/* acctype Type of access requested: READ, WRITE, instfetch, */
/* TAR, LRA, TPROT, or BSG */
/* regs Pointer to the CPU register context */
/* asteo Pointer to word to receive ASTE origin address */
/* aste Pointer to 16-word area to receive a copy of the */
/* ASN second table entry associated with the ALET */
/* */
/* Output: */
/* If successful, the ASTE is copied into the 16-word area, */
/* the real address of the ASTE is stored into the word pointed */
/* word pointed to by asteop, and the return value is zero; */
/* regs->dat.protect is set to 2 if the fetch-only bit */
/* in the ALE is set, otherwise it is set to zero. */
/* */
/* If unsuccessful, the return value is a non-zero exception */
/* code in the range X'0028' through X'002D' (this is to allow */
/* the TAR, LRA, and TPROT instructions to handle these */
/* exceptions by setting the condition code). */
/* regs->dat.xcode is also set to the exception code. */
/* */
/* A program check may be generated for addressing and ASN */
/* translation specification exceptions, in which case the */
/* function does not return. */
/*-------------------------------------------------------------------*/
_DAT_C_STATIC U16 ARCH_DEP(translate_alet) (U32 alet, U16 eax,
int acctype, REGS *regs, U32 *asteo, U32 aste[])
{
U32 cb; /* DUCT or PASTE address */
U32 ald; /* Access-list designation */
U32 alo; /* Access-list origin */
U32 all; /* Access-list length */
U32 ale[4]; /* Access-list entry */
U32 aste_addr; /* Real address of ASTE */
U32 abs; /* Absolute address */
BYTE *mn; /* Mainstor address */
int i; /* Array subscript */
regs->dat.protect = 0;
/* [5.8.4.3] Check the reserved bits in the ALET */
if ( alet & ALET_RESV )
goto alet_spec_excp;
/* [5.8.4.4] Obtain the effective access-list designation */
/* Obtain the real address of the control block containing
the effective access-list designation. This is either
the Primary ASTE or the DUCT */
cb = (alet & ALET_PRI_LIST) ?
regs->CR(5) & CR5_PASTEO :
regs->CR(2) & CR2_DUCTO;
/* Addressing exception if outside main storage */
if (cb > regs->mainlim)
goto alet_addr_excp;
/* Load the effective access-list designation (ALD) from
offset 16 in the control block. All four bytes must be
fetched concurrently as observed by other CPUs. Note
that the DUCT and the PASTE cannot cross a page boundary */
cb = APPLY_PREFIXING (cb, regs->PX);
ald = ARCH_DEP(fetch_fullword_absolute) (cb+16, regs);
/* [5.8.4.5] Access-list lookup */
/* Isolate the access-list origin and access-list length */
alo = ald & ALD_ALO;
all = ald & ALD_ALL;
/* Check that the ALEN does not exceed the ALL */
if (((alet & ALET_ALEN) >> ALD_ALL_SHIFT) > all)
goto alen_tran_excp;
/* Add the ALEN x 16 to the access list origin */
alo += (alet & ALET_ALEN) << 4;
/* Addressing exception if outside main storage */
if (alo > regs->mainlim)
goto alet_addr_excp;
/* Fetch the 16-byte access list entry from absolute storage.
Each fullword of the ALE must be fetched concurrently as
observed by other CPUs */
alo = APPLY_PREFIXING (alo, regs->PX);
mn = FETCH_MAIN_ABSOLUTE(alo, regs, 16);
for (i = 0; i < 4; i++)
{
ale[i] = fetch_fw (mn);
mn += 4;
}
/* Check the ALEN invalid bit in the ALE */
if (ale[0] & ALE0_INVALID)
goto alen_tran_excp;
/* For ordinary ART (but not for special ART),
compare the ALE sequence number with the ALET */
if (!(acctype & ACC_SPECIAL_ART)
&& (ale[0] & ALE0_ALESN) != (alet & ALET_ALESN))
goto ale_seq_excp;
/* [5.8.4.6] Locate the ASN-second-table entry */
aste_addr = ale[2] & ALE2_ASTE;
/* Addressing exception if ASTE is outside main storage */
abs = APPLY_PREFIXING (aste_addr, regs->PX);
if (abs > regs->mainlim)
goto alet_addr_excp;
mn = FETCH_MAIN_ABSOLUTE(abs, regs, 64);
/* Fetch the 64-byte ASN second table entry from real storage.
Each fullword of the ASTE must be fetched concurrently as
observed by other CPUs. ASTE cannot cross a page boundary */
for (i = 0; i < 16; i++)
{
aste[i] = fetch_fw(mn);
mn += 4;
}
/* Check the ASX invalid bit in the ASTE */
if (aste[0] & ASTE0_INVALID)
goto aste_vald_excp;
/* Compare the ASTE sequence number with the ALE */
if ((aste[5] & ASTE5_ASTESN) != (ale[3] & ALE3_ASTESN))
goto aste_seq_excp;
/* [5.8.4.7] For ordinary ART (but not for special ART),
authorize the use of the access-list entry */
if (!(acctype & ACC_SPECIAL_ART))
{
/* If ALE private bit is zero, or the ALE AX equals the
EAX, then authorization succeeds. Otherwise perform
the extended authorization process. */
if ((ale[0] & ALE0_PRIVATE)
&& (ale[0] & ALE0_ALEAX) != eax)
{
#if !defined(FEATURE_ESAME)
/* Check the reserved bits in first two words of ASTE */
if ((aste[0] & ASTE0_RESV) || (aste[1] & ASTE1_RESV)
|| ((aste[0] & ASTE0_BASE)
#ifdef FEATURE_SUBSPACE_GROUP
&& !ASF_ENABLED(regs)
#endif /*FEATURE_SUBSPACE_GROUP*/
))
goto alet_asn_tran_spec_excp;
#endif /*!defined(FEATURE_ESAME)*/
/* Perform extended authorization */
if (ARCH_DEP(authorize_asn)(eax, aste, ATE_SECONDARY, regs) != 0)
goto ext_auth_excp;
}
} /* end if(!ACCTYPE_BSG) */
/* [5.8.4.8] Check for access-list controlled protection */
if (ale[0] & ALE0_FETCHONLY)
regs->dat.protect = 2;
/* Return the ASTE origin address */
*asteo = aste_addr;
return 0;
/* Conditions which always cause program check, except
when performing translation for the control panel */
alet_addr_excp:
regs->dat.xcode = PGM_ADDRESSING_EXCEPTION;
goto alet_prog_check;
#if !defined(FEATURE_ESAME)
alet_asn_tran_spec_excp:
regs->dat.xcode = PGM_ASN_TRANSLATION_SPECIFICATION_EXCEPTION;
goto alet_prog_check;
#endif /*!defined(FEATURE_ESAME)*/
alet_prog_check:
regs->program_interrupt (regs, regs->dat.xcode);
/* Conditions which the caller may or may not program check */
alet_spec_excp:
regs->dat.xcode = PGM_ALET_SPECIFICATION_EXCEPTION;
return regs->dat.xcode;
alen_tran_excp:
regs->dat.xcode = PGM_ALEN_TRANSLATION_EXCEPTION;
return regs->dat.xcode;
ale_seq_excp:
regs->dat.xcode = PGM_ALE_SEQUENCE_EXCEPTION;
return regs->dat.xcode;
aste_vald_excp:
regs->dat.xcode = PGM_ASTE_VALIDITY_EXCEPTION;
return regs->dat.xcode;
aste_seq_excp:
regs->dat.xcode = PGM_ASTE_SEQUENCE_EXCEPTION;
return regs->dat.xcode;
ext_auth_excp:
regs->dat.xcode = PGM_EXTENDED_AUTHORITY_EXCEPTION;
return regs->dat.xcode;
} /* end function translate_alet */
#endif /*defined(FEATURE_ACCESS_REGISTERS)*/
#if defined(FEATURE_ACCESS_REGISTERS)
/*-------------------------------------------------------------------*/
/* Purge the ART lookaside buffer */
/*-------------------------------------------------------------------*/
_DAT_C_STATIC void ARCH_DEP(purge_alb) (REGS *regs)
{
int i;
for(i = 1; i < 16; i++)
if(regs->aea_ar[i] >= CR_ALB_OFFSET && regs->aea_ar[i] != CR_ASD_REAL)
regs->aea_ar[i] = 0;
if(regs->host && regs->guestregs)
for(i = 1; i < 16; i++)
if(regs->guestregs->aea_ar[i] >= CR_ALB_OFFSET && regs->guestregs->aea_ar[i] != CR_ASD_REAL)
regs->guestregs->aea_ar[i] = 0;
} /* end function purge_alb */
/*-------------------------------------------------------------------*/
/* Purge the ART lookaside buffer for all CPUs */
/*-------------------------------------------------------------------*/
_DAT_C_STATIC void ARCH_DEP(purge_alb_all) ()
{
int i;
for (i = 0; i < MAX_CPU; i++)
if (IS_CPU_ONLINE(i)
&& (sysblk.regs[i]->cpubit & sysblk.started_mask))
ARCH_DEP(purge_alb) (sysblk.regs[i]);
} /* end function purge_alb_all */
#endif /*defined(FEATURE_ACCESS_REGISTERS)*/
/*-------------------------------------------------------------------*/
/* Determine effective ASCE or STD */
/* */
/* This routine returns either an address-space control element */
/* (for ESAME) or a segment table descriptor (for S/370 and ESA/390) */
/* loaded from control register 1, 7, or 13, or computed from the */
/* contents of an address register, together with an indication of */
/* the addressing mode (home, primary, secondary, or AR mode) */
/* which was used to determine the source of the ASCE or STD. */
/* */
/* Input: */
/* arn Access register number (0-15) to be used if the */
/* address-space control (PSW bits 16-17) indicates */
/* that ARMODE is the current translation mode. */
/* An access register number ORed with the special */
/* value USE_ARMODE forces this routine to use ARMODE */
/* regardless of the PSW address-space control setting. */
/* Access register 0 is treated as if it contained 0 */
/* and its actual contents are not examined. */
/* Alternatively the arn parameter may contain one */
/* of these special values (defined in hconsts.h): */
/* USE_PRIMARY_SPACE, USE_SECONDARY_SPACE, */
/* USE_HOME_SPACE, USE_REAL_ADDR to force the use of */
/* a specific translation mode instead of the mode */
/* indicated by the address-space control in the PSW. */
/* regs Pointer to the CPU register context */
/* acctype Type of access requested: READ, WRITE, INSTFETCH, */
/* LRA, IVSK, TPROT, STACK, PTE, LPTEA */
/* */
/* Output: */
/* regs->dat.asd = the selected ASCE or STD */
/* regs->dat.stid = TEA_ST_PRIMARY, TEA_ST_SECNDRY, */
/* TEA_ST_HOME, or TEA_ST_ARMODE indicates which */
/* address space was used to select the ASCE or STD. */
/* regs->dat.protect = 2 if in AR mode and access-list */
/* controlled protection is indicated by the ALE */
/* fetch-only bit; otherwise it remains unchanged. */
/* */
/* If an ALET translation error occurs, the return value */
/* is the exception code; otherwise the return value is zero, */
/* regs->dat.asd field contains the ASCE or STD, and */
/* regs->dat.stid is set to TEA_ST_PRIMARY, TEA_ST_SECNDRY, */
/* TEA_ST_HOME, or TEA_ST_ARMODE. */
/*-------------------------------------------------------------------*/
_DAT_C_STATIC U16 ARCH_DEP(load_address_space_designator) (int arn,
REGS *regs, int acctype)
{
#if defined(FEATURE_ACCESS_REGISTERS)
U32 alet; /* Access list entry token */
U32 asteo; /* Real address of ASTE */
U32 aste[16]; /* ASN second table entry */
U16 eax; /* Authorization index */
#else
UNREFERENCED(acctype);
#endif /*defined(FEATURE_ACCESS_REGISTERS)*/
switch(arn) {
case USE_PRIMARY_SPACE:
regs->dat.stid = TEA_ST_PRIMARY;
regs->dat.asd = regs->CR(1);
break;
case USE_SECONDARY_SPACE:
regs->dat.stid = TEA_ST_SECNDRY;
regs->dat.asd = regs->CR(7);
break;
case USE_HOME_SPACE:
regs->dat.stid = TEA_ST_HOME;
regs->dat.asd = regs->CR(13);
break;
case USE_REAL_ADDR:
regs->dat.stid = 0;
regs->dat.asd = TLB_REAL_ASD;
break;
case USE_INST_SPACE:
switch(regs->aea_ar[USE_INST_SPACE]) {
case 1:
regs->dat.stid = TEA_ST_PRIMARY;
break;
#if defined(FEATURE_LINKAGE_STACK)
case 13:
regs->dat.stid = TEA_ST_HOME;
break;
#endif
default:
regs->dat.stid = 0;
} /* end switch(regs->aea_ar[USE_INST_SPACE]) */
regs->dat.asd = regs->CR(regs->aea_ar[USE_INST_SPACE]);
break;
default:
#if defined(FEATURE_ACCESS_REGISTERS)
if (ACCESS_REGISTER_MODE(®s->psw)
|| (SIE_ACTIVE(regs) && MULTIPLE_CONTROLLED_DATA_SPACE(regs->guestregs))
|| (arn & USE_ARMODE)
)
{
/* Remove flags giving access register number 0-15 */
arn &= 0xF;
/* [5.8.4.1] Select the access-list-entry token */
alet = (arn == 0) ? 0 :
/* Guest ALET if XC guest in AR mode */
(SIE_ACTIVE(regs) && MULTIPLE_CONTROLLED_DATA_SPACE(regs->guestregs))
? regs->guestregs->AR(arn) :
/* If SIE host but not XC guest in AR mode then alet is 0 */
SIE_ACTIVE(regs) ? 0 :
/* Otherwise alet is in the access register */
regs->AR(arn);
/* Use the ALET to determine the segment table origin */
switch (alet) {
case ALET_PRIMARY:
/* [5.8.4.2] Obtain primary segment table designation */
regs->dat.stid = TEA_ST_PRIMARY;
regs->dat.asd = regs->CR(1);
break;
case ALET_SECONDARY:
/* [5.8.4.2] Obtain secondary segment table designation */
regs->dat.stid = TEA_ST_SECNDRY;
regs->dat.asd = regs->CR(7);
break;
default:
/* ALB Lookup */
if(regs->aea_ar[arn] >= CR_ALB_OFFSET && regs->aea_ar[arn] != CR_ASD_REAL)
{
regs->dat.asd = regs->CR(regs->aea_ar[arn]);
regs->dat.protect = regs->aea_aleprot[arn];
regs->dat.stid = TEA_ST_ARMODE;
}
else
{
/* Extract the extended AX from CR8 bits 0-15 (32-47) */
eax = regs->CR_LHH(8);
/* [5.8.4.3] Perform ALET translation to obtain ASTE */
if (ARCH_DEP(translate_alet) (alet, eax, acctype,
regs, &asteo, aste))
/* Exit if ALET translation error */
return regs->dat.xcode;
/* [5.8.4.9] Obtain the STD or ASCE from the ASTE */
regs->dat.asd = ASTE_AS_DESIGNATOR(aste);
regs->dat.stid = TEA_ST_ARMODE;
if(regs->dat.protect & 2)
{
#if defined(FEATURE_ESAME)
regs->dat.asd ^= ASCE_RESV;
regs->dat.asd |= ASCE_P;
#else
regs->dat.asd ^= STD_RESV;
regs->dat.asd |= STD_PRIVATE;
#endif
}
/* Update ALB */
regs->CR(CR_ALB_OFFSET + arn) = regs->dat.asd;
regs->aea_ar[arn] = CR_ALB_OFFSET + arn;
regs->aea_common[CR_ALB_OFFSET + arn] = (regs->dat.asd & ASD_PRIVATE) == 0;
regs->aea_aleprot[arn] = regs->dat.protect & 2;
}
} /* end switch(alet) */
break;
} /* end if(ACCESS_REGISTER_MODE) */
#endif /*defined(FEATURE_ACCESS_REGISTERS)*/
#if defined(FEATURE_DUAL_ADDRESS_SPACE)
if (SECONDARY_SPACE_MODE(®s->psw))
{
regs->dat.stid = TEA_ST_SECNDRY;
regs->dat.asd = regs->CR(7);
break;
}
#endif /* defined(FEATURE_DUAL_ADDRESS_SPACE) */
#if defined(FEATURE_LINKAGE_STACK)
if (HOME_SPACE_MODE(®s->psw))
{
regs->dat.stid = TEA_ST_HOME;
regs->dat.asd = regs->CR(13);
break;
}
#endif /* defined(FEATURE_LINKAGE_STACK) */
/* Primary space mode */
regs->dat.stid = TEA_ST_PRIMARY;
regs->dat.asd = regs->CR(1);
break;
} /* switch(arn) */
return 0;
} /* end function load_address_space_designator */
/*-------------------------------------------------------------------*/
/* Translate a virtual address to a real address */
/* */
/* Input: */
/* vaddr virtual address to be translated */
/* arn Access register number or special value (see */
/* load_address_space_designator function for a */
/* complete description of this parameter) */
/* regs Pointer to the CPU register context */
/* acctype Type of access requested: READ, WRITE, INSTFETCH, */
/* LRA, IVSK, TPROT, STACK, PTE, LPTEA */
/* */
/* Output: */
/* The return value is set to facilitate the setting of the */
/* condition code by the LRA instruction: */
/* 0 = Translation successful; real address field contains */
/* the real address corresponding to the virtual address */
/* supplied by the caller; exception code set to zero. */
/* 1 = Segment table entry invalid; real address field */
/* contains real address of segment table entry; */
/* exception code is set to X'0010'. */
/* 2 = Page table entry invalid; real address field contains */
/* real address of page table entry; exception code */
/* is set to X'0011'. */
/* 3 = Segment or page table length exceeded; real address */
/* field contains the real address of the entry that */
/* would have been fetched if length violation had not */
/* occurred; exception code is set to X'0010' or X'0011'. */
/* 4 = ALET translation error: real address field is not */
/* set; exception code is set to X'0028' through X'002D'. */
/* ASCE-type or region-translation error: real address */
/* is not set; exception code is X'0038' through X'003B'. */
/* The LRA instruction converts this to condition code 3. */
/* 5 = For ACCTYPE_EMC (Enhanced MC access only): */
/* A translation specification exception occured */
/* */
/* For ACCTYPE_LPTEA, the return value is set to facilitate */
/* setting the condition code by the LPTEA instruction: */
/* 0 = Page table entry found, and page protection bit in the */
/* segment table entry is zero; the real address field */
/* contains the real address of the page table entry; */
/* exception code is set to zero. */
/* 1 = Page table entry found, and page protection bit in the */
/* segment table entry is one; the real address field */
/* contains the real address of the page table entry; */
/* exception code is set to zero. */
/* 2 = Region table or segment table entry invalid bit is set; */
/* the real address field contains the real address of the */
/* region table entry or segment table entry, with the */
/* entry type in the low-order two bits of the address. */
/* 3 = Region table or segment table length exceeded; real */
/* address field is not set; exception code is set to */
/* X'0010' or X'0039' through X'003B'. */
/* ALET translation error: real address field is not */
/* set; exception code is set to X'0028' through X'002D'. */
/* ASCE-type error: real address is not set; exception */
/* exception code is X'0038'. */
/* */
/* regs->dat.raddr is set to the real address if translation */
/* was successful; otherwise it may contain the address of */
/* a page or segment table entry as described above. */
/* For ACCTYPE_PTE or ACCTYPE_LPTEA it contains the address of */
/* the page table entry if translation was successful. */
/* */
/* regs->dat.xcode is set to the exception code if translation */
/* was unsuccessful; otherwise it is set to zero. */
/* */
/* regs->dat.private is set to 1 if translation was */
/* successful and the STD indicates a private address space; */
/* otherwise it is set to zero. */
/* */
/* regs->dat.protect is set to 1 if translation was */
/* successful and page protection, segment protection, or */
/* segment controlled page protection is in effect; it is */
/* set to 2 if translation was successful and ALE controlled */
/* protection (but not page protection) is in effect; */
/* otherwise it is set to zero. */
/* */
/* regs->dat.stid is set to one of the following */
/* values TEA_ST_PRIMARY, TEA_ST_SECNDRY, TEA_ST_HOME, or */
/* TEA_ST_ARMODE if the translation was successful. This */
/* indication is used to set bits 30-31 of the translation */
/* exception address in the event of a protection exception */
/* when the suppression on protection facility is used. */
/* */
/* A program check may be generated for addressing and */
/* translation specification exceptions, in which case the */
/* function does not return. */
/*-------------------------------------------------------------------*/
_DAT_C_STATIC int ARCH_DEP(translate_addr) (VADR vaddr, int arn,
REGS *regs, int acctype)
{
RADR sto = 0; /* Segment table origin */
RADR pto = 0; /* Page table origin */
int cc; /* Condition code */
int tlbix = TLBIX(vaddr); /* TLB entry index */
#if !defined(FEATURE_S390_DAT) && !defined(FEATURE_ESAME)
/*-----------------------------------*/
/* S/370 Dynamic Address Translation */
/*-----------------------------------*/
U32 stl; /* Segment table length */
RADR ste; /* Segment table entry */
U16 pte; /* Page table entry */
U32 ptl; /* Page table length */
regs->dat.private = regs->dat.protect = 0;
/* Load the effective segment table descriptor */
if (ARCH_DEP(load_address_space_designator) (arn, regs, acctype))
goto tran_alet_excp;
/* Check the translation format bits in CR0 */
if ((((regs->CR(0) & CR0_PAGE_SIZE) != CR0_PAGE_SZ_2K) &&
((regs->CR(0) & CR0_PAGE_SIZE) != CR0_PAGE_SZ_4K)) ||
(((regs->CR(0) & CR0_SEG_SIZE) != CR0_SEG_SZ_64K) &&
((regs->CR(0) & CR0_SEG_SIZE) != CR0_SEG_SZ_1M)))
goto tran_spec_excp;
/* Look up the address in the TLB */
if ( ((vaddr & TLBID_PAGEMASK) | regs->tlbID) == regs->tlb.TLB_VADDR(tlbix)
&& (regs->tlb.common[tlbix] || regs->dat.asd == regs->tlb.TLB_ASD(tlbix))
&& !(regs->tlb.common[tlbix] && regs->dat.private)
&& !(acctype & ACC_NOTLB) )
{
pte = regs->tlb.TLB_PTE(tlbix);
#ifdef FEATURE_SEGMENT_PROTECTION
/* Set the protection indicator if segment is protected */
if (regs->tlb.protect[tlbix])
regs->dat.protect = regs->tlb.protect[tlbix];
#endif /*FEATURE_SEGMENT_PROTECTION*/
}
else
{
/* S/370 segment table lookup */
/* Calculate the real address of the segment table entry */
sto = regs->dat.asd & STD_370_STO;
stl = regs->dat.asd & STD_370_STL;
sto += ((regs->CR(0) & CR0_SEG_SIZE) == CR0_SEG_SZ_1M) ?
((vaddr & 0x00F00000) >> 18) :
((vaddr & 0x00FF0000) >> 14);
/* Check that virtual address is within the segment table */
if (((regs->CR(0) & CR0_SEG_SIZE) == CR0_SEG_SZ_64K) &&
((vaddr << 4) & STD_370_STL) > stl)
goto seg_tran_length;
/* Generate addressing exception if outside real storage */
if (sto > regs->mainlim)
goto address_excp;
/* Fetch segment table entry from real storage. All bytes
must be fetched concurrently as observed by other CPUs */
sto = APPLY_PREFIXING (sto, regs->PX);
ste = ARCH_DEP(fetch_fullword_absolute) (sto, regs);
/* Generate segment translation exception if segment invalid */
if (ste & SEGTAB_370_INVL)
goto seg_tran_invalid;
/* Check that all the reserved bits in the STE are zero */
if (ste & SEGTAB_370_RSV)
goto tran_spec_excp;
/* Isolate page table origin and length */
pto = ste & SEGTAB_370_PTO;
ptl = ste & SEGTAB_370_PTL;
/* S/370 page table lookup */
/* Calculate the real address of the page table entry */
pto += ((regs->CR(0) & CR0_SEG_SIZE) == CR0_SEG_SZ_1M) ?
(((regs->CR(0) & CR0_PAGE_SIZE) == CR0_PAGE_SZ_4K) ?
((vaddr & 0x000FF000) >> 11) :
((vaddr & 0x000FF800) >> 10)) :
(((regs->CR(0) & CR0_PAGE_SIZE) == CR0_PAGE_SZ_4K) ?
((vaddr & 0x0000F000) >> 11) :
((vaddr & 0x0000F800) >> 10));
/* Generate addressing exception if outside real storage */
if (pto > regs->mainlim)
goto address_excp;
/* Check that the virtual address is within the page table */
if ((((regs->CR(0) & CR0_SEG_SIZE) == CR0_SEG_SZ_1M) &&
(((vaddr & 0x000F0000) >> 16) > ptl)) ||
(((regs->CR(0) & CR0_SEG_SIZE) == CR0_SEG_SZ_64K) &&
(((vaddr & 0x0000F000) >> 12) > ptl)))
goto page_tran_length;
/* Fetch the page table entry from real storage. All bytes
must be fetched concurrently as observed by other CPUs */
pto = APPLY_PREFIXING (pto, regs->PX);
pte = ARCH_DEP(fetch_halfword_absolute) (pto, regs);
/* Generate page translation exception if page invalid */
if ((((regs->CR(0) & CR0_PAGE_SIZE) == CR0_PAGE_SZ_4K) &&
(pte & PAGETAB_INV_4K)) ||
(((regs->CR(0) & CR0_PAGE_SIZE) == CR0_PAGE_SZ_2K) &&
(pte & PAGETAB_INV_2K)))
goto page_tran_invalid;
/* Check that all the reserved bits in the PTE are zero */
if (((regs->CR(0) & CR0_PAGE_SIZE) == CR0_PAGE_SZ_2K) &&
(pte & PAGETAB_RSV_2K))
goto tran_spec_excp;
#ifdef FEATURE_SEGMENT_PROTECTION
/* Set the protection indicator if segment is protected */
if (ste & SEGTAB_370_PROT)
regs->dat.protect |= 1;
#endif /*FEATURE_SEGMENT_PROTECTION*/
/* Place the translated address in the TLB */
if (!(acctype & ACC_NOTLB))
{
regs->tlb.TLB_ASD(tlbix) = regs->dat.asd;
regs->tlb.TLB_VADDR(tlbix) = (vaddr & TLBID_PAGEMASK) | regs->tlbID;
regs->tlb.TLB_PTE(tlbix) = pte;
regs->tlb.common[tlbix] = (ste & SEGTAB_370_CMN) ? 1 : 0;
regs->tlb.protect[tlbix] = regs->dat.protect;
regs->tlb.acc[tlbix] = 0;
regs->tlb.main[tlbix] = NULL;
/* Set adjacent TLB entry if 4K page sizes */
if ((regs->CR(0) & CR0_PAGE_SIZE) == CR0_PAGE_SZ_4K)
{
regs->tlb.TLB_ASD(tlbix^1) = regs->tlb.TLB_ASD(tlbix);
regs->tlb.TLB_VADDR(tlbix^1) = (vaddr & TLBID_PAGEMASK) | regs->tlbID;
regs->tlb.TLB_PTE(tlbix^1) = regs->tlb.TLB_PTE(tlbix);
regs->tlb.common[tlbix^1] = regs->tlb.common[tlbix];
regs->tlb.protect[tlbix^1] = regs->tlb.protect[tlbix];
regs->tlb.acc[tlbix^1] = 0;
regs->tlb.main[tlbix^1] = NULL;
}
}
} /* end if(!TLB) */
/* Combine the page frame real address with the byte
index of the virtual address to form the real address */
regs->dat.raddr = ((regs->CR(0) & CR0_PAGE_SIZE) == CR0_PAGE_SZ_4K) ?
#if defined(FEATURE_S370E_EXTENDED_ADDRESSING)
(((U32)pte & PAGETAB_EA_4K) << 23) |
#endif
(((U32)pte & PAGETAB_PFRA_4K) << 8) | (vaddr & 0xFFF) :
(((U32)pte & PAGETAB_PFRA_2K) << 8) | (vaddr & 0x7FF);
regs->dat.rpfra = regs->dat.raddr & PAGEFRAME_PAGEMASK;
#endif /*!defined(FEATURE_S390_DAT) && !defined(FEATURE_ESAME)*/
#if defined(FEATURE_S390_DAT)
/*-----------------------------------*/
/* S/390 Dynamic Address Translation */
/*-----------------------------------*/
U32 stl; /* Segment table length */
RADR ste; /* Segment table entry */
RADR pte; /* Page table entry */
U32 ptl; /* Page table length */
regs->dat.private = regs->dat.protect = 0;
/* [3.11.3.1] Load the effective segment table descriptor */
if (ARCH_DEP(load_address_space_designator) (arn, regs, acctype))
goto tran_alet_excp;
/* [3.11.3.2] Check the translation format bits in CR0 */
if ((regs->CR(0) & CR0_TRAN_FMT) != CR0_TRAN_ESA390)
goto tran_spec_excp;
/* Extract the private space bit from segment table descriptor */
regs->dat.private = ((regs->dat.asd & STD_PRIVATE) != 0);